SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/rt2x00/rt2500pci.c

   1 /*
   2         Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt2500pci
  23         Abstract: rt2500pci device specific routines.
  24         Supported chipsets: RT2560.
  25  */
  26
  27 #include <linux/delay.h>
  28 #include <linux/etherdevice.h>
  29 #include <linux/init.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/pci.h>
  33 #include <linux/eeprom_93cx6.h>
  34
  35 #include "rt2x00.h"
  36 #include "rt2x00pci.h"
  37 #include "rt2500pci.h"
  38
  39 /*
  40  * Register access.
  41  * All access to the CSR registers will go through the methods
  42  * rt2x00pci_register_read and rt2x00pci_register_write.
  43  * BBP and RF register require indirect register access,
  44  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  45  * These indirect registers work with busy bits,
  46  * and we will try maximal REGISTER_BUSY_COUNT times to access
  47  * the register while taking a REGISTER_BUSY_DELAY us delay
  48  * between each attampt. When the busy bit is still set at that time,
  49  * the access attempt is considered to have failed,
  50  * and we will print an error.
  51  */
  52 static u32 rt2500pci_bbp_check(struct rt2x00_dev *rt2x00dev)
  53 {
  54         u32 reg;
  55         unsigned int i;
  56
  57         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  58                 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
  59                 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
  60                         break;
  61                 udelay(REGISTER_BUSY_DELAY);
  62         }
  63
  64         return reg;
  65 }
  66
  67 static void rt2500pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  68                                 const unsigned int word, const u8 value)
  69 {
  70         u32 reg;
  71
  72         /*
  73          * Wait until the BBP becomes ready.
  74          */
  75         reg = rt2500pci_bbp_check(rt2x00dev);
  76         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
  77                 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
  78                 return;
  79         }
  80
  81         /*
  82          * Write the data into the BBP.
  83          */
  84         reg = 0;
  85         rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
  86         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  87         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
  88         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
  89
  90         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
  91 }
  92
  93 static void rt2500pci_bbp_read(struct rt2x00_dev *rt2x00dev,
  94                                const unsigned int word, u8 *value)
  95 {
  96         u32 reg;
  97
  98         /*
  99          * Wait until the BBP becomes ready.
 100          */
 101         reg = rt2500pci_bbp_check(rt2x00dev);
 102         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
 103                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
 104                 return;
 105         }
 106
 107         /*
 108          * Write the request into the BBP.
 109          */
 110         reg = 0;
 111         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
 112         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
 113         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
 114
 115         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
 116
 117         /*
 118          * Wait until the BBP becomes ready.
 119          */
 120         reg = rt2500pci_bbp_check(rt2x00dev);
 121         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
 122                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
 123                 *value = 0xff;
 124                 return;
 125         }
 126
 127         *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
 128 }
 129
 130 static void rt2500pci_rf_write(struct rt2x00_dev *rt2x00dev,
 131                                const unsigned int word, const u32 value)
 132 {
 133         u32 reg;
 134         unsigned int i;
 135
 136         if (!word)
 137                 return;
 138
 139         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 140                 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
 141                 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
 142                         goto rf_write;
 143                 udelay(REGISTER_BUSY_DELAY);
 144         }
 145
 146         ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
 147         return;
 148
 149 rf_write:
 150         reg = 0;
 151         rt2x00_set_field32(&reg, RFCSR_VALUE, value);
 152         rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
 153         rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
 154         rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
 155
 156         rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
 157         rt2x00_rf_write(rt2x00dev, word, value);
 158 }
 159
 160 static void rt2500pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 161 {
 162         struct rt2x00_dev *rt2x00dev = eeprom->data;
 163         u32 reg;
 164
 165         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
 166
 167         eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
 168         eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
 169         eeprom->reg_data_clock =
 170             !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
 171         eeprom->reg_chip_select =
 172             !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
 173 }
 174
 175 static void rt2500pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 176 {
 177         struct rt2x00_dev *rt2x00dev = eeprom->data;
 178         u32 reg = 0;
 179
 180         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
 181         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
 182         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
 183                            !!eeprom->reg_data_clock);
 184         rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
 185                            !!eeprom->reg_chip_select);
 186
 187         rt2x00pci_register_write(rt2x00dev, CSR21, reg);
 188 }
 189
 190 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 191 #define CSR_OFFSET(__word)      ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
 192
 193 static void rt2500pci_read_csr(struct rt2x00_dev *rt2x00dev,
 194                                const unsigned int word, u32 *data)
 195 {
 196         rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
 197 }
 198
 199 static void rt2500pci_write_csr(struct rt2x00_dev *rt2x00dev,
 200                                 const unsigned int word, u32 data)
 201 {
 202         rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
 203 }
 204
 205 static const struct rt2x00debug rt2500pci_rt2x00debug = {
 206         .owner  = THIS_MODULE,
 207         .csr    = {
 208                 .read           = rt2500pci_read_csr,
 209                 .write          = rt2500pci_write_csr,
 210                 .word_size      = sizeof(u32),
 211                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 212         },
 213         .eeprom = {
 214                 .read           = rt2x00_eeprom_read,
 215                 .write          = rt2x00_eeprom_write,
 216                 .word_size      = sizeof(u16),
 217                 .word_count     = EEPROM_SIZE / sizeof(u16),
 218         },
 219         .bbp    = {
 220                 .read           = rt2500pci_bbp_read,
 221                 .write          = rt2500pci_bbp_write,
 222                 .word_size      = sizeof(u8),
 223                 .word_count     = BBP_SIZE / sizeof(u8),
 224         },
 225         .rf     = {
 226                 .read           = rt2x00_rf_read,
 227                 .write          = rt2500pci_rf_write,
 228                 .word_size      = sizeof(u32),
 229                 .word_count     = RF_SIZE / sizeof(u32),
 230         },
 231 };
 232 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 233
 234 #ifdef CONFIG_RT2500PCI_RFKILL
 235 static int rt2500pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 236 {
 237         u32 reg;
 238
 239         rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
 240         return rt2x00_get_field32(reg, GPIOCSR_BIT0);
 241 }
 242 #else
 243 #define rt2500pci_rfkill_poll   NULL
 244 #endif /* CONFIG_RT2500PCI_RFKILL */
 245
 246 #ifdef CONFIG_RT2500PCI_LEDS
 247 static void rt2500pci_brightness_set(struct led_classdev *led_cdev,
 248                                      enum led_brightness brightness)
 249 {
 250         struct rt2x00_led *led =
 251             container_of(led_cdev, struct rt2x00_led, led_dev);
 252         unsigned int enabled = brightness != LED_OFF;
 253         u32 reg;
 254
 255         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
 256
 257         if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
 258                 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
 259         else if (led->type == LED_TYPE_ACTIVITY)
 260                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
 261
 262         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
 263 }
 264
 265 static int rt2500pci_blink_set(struct led_classdev *led_cdev,
 266                                unsigned long *delay_on,
 267                                unsigned long *delay_off)
 268 {
 269         struct rt2x00_led *led =
 270             container_of(led_cdev, struct rt2x00_led, led_dev);
 271         u32 reg;
 272
 273         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
 274         rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
 275         rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
 276         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
 277
 278         return 0;
 279 }
 280 #endif /* CONFIG_RT2500PCI_LEDS */
 281
 282 /*
 283  * Configuration handlers.
 284  */
 285 static void rt2500pci_config_filter(struct rt2x00_dev *rt2x00dev,
 286                                     const unsigned int filter_flags)
 287 {
 288         u32 reg;
 289
 290         /*
 291          * Start configuration steps.
 292          * Note that the version error will always be dropped
 293          * and broadcast frames will always be accepted since
 294          * there is no filter for it at this time.
 295          */
 296         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
 297         rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
 298                            !(filter_flags & FIF_FCSFAIL));
 299         rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
 300                            !(filter_flags & FIF_PLCPFAIL));
 301         rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
 302                            !(filter_flags & FIF_CONTROL));
 303         rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
 304                            !(filter_flags & FIF_PROMISC_IN_BSS));
 305         rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
 306                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
 307                            !rt2x00dev->intf_ap_count);
 308         rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
 309         rt2x00_set_field32(&reg, RXCSR0_DROP_MCAST,
 310                            !(filter_flags & FIF_ALLMULTI));
 311         rt2x00_set_field32(&reg, RXCSR0_DROP_BCAST, 0);
 312         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
 313 }
 314
 315 static void rt2500pci_config_intf(struct rt2x00_dev *rt2x00dev,
 316                                   struct rt2x00_intf *intf,
 317                                   struct rt2x00intf_conf *conf,
 318                                   const unsigned int flags)
 319 {
 320         struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, QID_BEACON);
 321         unsigned int bcn_preload;
 322         u32 reg;
 323
 324         if (flags & CONFIG_UPDATE_TYPE) {
 325                 /*
 326                  * Enable beacon config
 327                  */
 328                 bcn_preload = PREAMBLE + get_duration(IEEE80211_HEADER, 20);
 329                 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
 330                 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
 331                 rt2x00_set_field32(&reg, BCNCSR1_BEACON_CWMIN, queue->cw_min);
 332                 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
 333
 334                 /*
 335                  * Enable synchronisation.
 336                  */
 337                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
 338                 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
 339                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
 340                 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
 341                 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 342         }
 343
 344         if (flags & CONFIG_UPDATE_MAC)
 345                 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
 346                                               conf->mac, sizeof(conf->mac));
 347
 348         if (flags & CONFIG_UPDATE_BSSID)
 349                 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
 350                                               conf->bssid, sizeof(conf->bssid));
 351 }
 352
 353 static void rt2500pci_config_erp(struct rt2x00_dev *rt2x00dev,
 354                                  struct rt2x00lib_erp *erp)
 355 {
 356         int preamble_mask;
 357         u32 reg;
 358
 359         /*
 360          * When short preamble is enabled, we should set bit 0x08
 361          */
 362         preamble_mask = erp->short_preamble << 3;
 363
 364         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 365         rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT,
 366                            erp->ack_timeout);
 367         rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME,
 368                            erp->ack_consume_time);
 369         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 370
 371         rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
 372         rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
 373         rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
 374         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
 375         rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
 376
 377         rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
 378         rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
 379         rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
 380         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
 381         rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
 382
 383         rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
 384         rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
 385         rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
 386         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
 387         rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
 388
 389         rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
 390         rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
 391         rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
 392         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
 393         rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
 394 }
 395
 396 static void rt2500pci_config_phymode(struct rt2x00_dev *rt2x00dev,
 397                                      const int basic_rate_mask)
 398 {
 399         rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
 400 }
 401
 402 static void rt2500pci_config_channel(struct rt2x00_dev *rt2x00dev,
 403                                      struct rf_channel *rf, const int txpower)
 404 {
 405         u8 r70;
 406
 407         /*
 408          * Set TXpower.
 409          */
 410         rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 411
 412         /*
 413          * Switch on tuning bits.
 414          * For RT2523 devices we do not need to update the R1 register.
 415          */
 416         if (!rt2x00_rf(&rt2x00dev->chip, RF2523))
 417                 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
 418         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
 419
 420         /*
 421          * For RT2525 we should first set the channel to half band higher.
 422          */
 423         if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
 424                 static const u32 vals[] = {
 425                         0x00080cbe, 0x00080d02, 0x00080d06, 0x00080d0a,
 426                         0x00080d0e, 0x00080d12, 0x00080d16, 0x00080d1a,
 427                         0x00080d1e, 0x00080d22, 0x00080d26, 0x00080d2a,
 428                         0x00080d2e, 0x00080d3a
 429                 };
 430
 431                 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
 432                 rt2500pci_rf_write(rt2x00dev, 2, vals[rf->channel - 1]);
 433                 rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
 434                 if (rf->rf4)
 435                         rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
 436         }
 437
 438         rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
 439         rt2500pci_rf_write(rt2x00dev, 2, rf->rf2);
 440         rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
 441         if (rf->rf4)
 442                 rt2500pci_rf_write(rt2x00dev, 4, rf->rf4);
 443
 444         /*
 445          * Channel 14 requires the Japan filter bit to be set.
 446          */
 447         r70 = 0x46;
 448         rt2x00_set_field8(&r70, BBP_R70_JAPAN_FILTER, rf->channel == 14);
 449         rt2500pci_bbp_write(rt2x00dev, 70, r70);
 450
 451         msleep(1);
 452
 453         /*
 454          * Switch off tuning bits.
 455          * For RT2523 devices we do not need to update the R1 register.
 456          */
 457         if (!rt2x00_rf(&rt2x00dev->chip, RF2523)) {
 458                 rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
 459                 rt2500pci_rf_write(rt2x00dev, 1, rf->rf1);
 460         }
 461
 462         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
 463         rt2500pci_rf_write(rt2x00dev, 3, rf->rf3);
 464
 465         /*
 466          * Clear false CRC during channel switch.
 467          */
 468         rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
 469 }
 470
 471 static void rt2500pci_config_txpower(struct rt2x00_dev *rt2x00dev,
 472                                      const int txpower)
 473 {
 474         u32 rf3;
 475
 476         rt2x00_rf_read(rt2x00dev, 3, &rf3);
 477         rt2x00_set_field32(&rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
 478         rt2500pci_rf_write(rt2x00dev, 3, rf3);
 479 }
 480
 481 static void rt2500pci_config_antenna(struct rt2x00_dev *rt2x00dev,
 482                                      struct antenna_setup *ant)
 483 {
 484         u32 reg;
 485         u8 r14;
 486         u8 r2;
 487
 488         /*
 489          * We should never come here because rt2x00lib is supposed
 490          * to catch this and send us the correct antenna explicitely.
 491          */
 492         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
 493                ant->tx == ANTENNA_SW_DIVERSITY);
 494
 495         rt2x00pci_register_read(rt2x00dev, BBPCSR1, &reg);
 496         rt2500pci_bbp_read(rt2x00dev, 14, &r14);
 497         rt2500pci_bbp_read(rt2x00dev, 2, &r2);
 498
 499         /*
 500          * Configure the TX antenna.
 501          */
 502         switch (ant->tx) {
 503         case ANTENNA_A:
 504                 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 0);
 505                 rt2x00_set_field32(&reg, BBPCSR1_CCK, 0);
 506                 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 0);
 507                 break;
 508         case ANTENNA_B:
 509         default:
 510                 rt2x00_set_field8(&r2, BBP_R2_TX_ANTENNA, 2);
 511                 rt2x00_set_field32(&reg, BBPCSR1_CCK, 2);
 512                 rt2x00_set_field32(&reg, BBPCSR1_OFDM, 2);
 513                 break;
 514         }
 515
 516         /*
 517          * Configure the RX antenna.
 518          */
 519         switch (ant->rx) {
 520         case ANTENNA_A:
 521                 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 0);
 522                 break;
 523         case ANTENNA_B:
 524         default:
 525                 rt2x00_set_field8(&r14, BBP_R14_RX_ANTENNA, 2);
 526                 break;
 527         }
 528
 529         /*
 530          * RT2525E and RT5222 need to flip TX I/Q
 531          */
 532         if (rt2x00_rf(&rt2x00dev->chip, RF2525E) ||
 533             rt2x00_rf(&rt2x00dev->chip, RF5222)) {
 534                 rt2x00_set_field8(&r2, BBP_R2_TX_IQ_FLIP, 1);
 535                 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 1);
 536                 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 1);
 537
 538                 /*
 539                  * RT2525E does not need RX I/Q Flip.
 540                  */
 541                 if (rt2x00_rf(&rt2x00dev->chip, RF2525E))
 542                         rt2x00_set_field8(&r14, BBP_R14_RX_IQ_FLIP, 0);
 543         } else {
 544                 rt2x00_set_field32(&reg, BBPCSR1_CCK_FLIP, 0);
 545                 rt2x00_set_field32(&reg, BBPCSR1_OFDM_FLIP, 0);
 546         }
 547
 548         rt2x00pci_register_write(rt2x00dev, BBPCSR1, reg);
 549         rt2500pci_bbp_write(rt2x00dev, 14, r14);
 550         rt2500pci_bbp_write(rt2x00dev, 2, r2);
 551 }
 552
 553 static void rt2500pci_config_duration(struct rt2x00_dev *rt2x00dev,
 554                                       struct rt2x00lib_conf *libconf)
 555 {
 556         u32 reg;
 557
 558         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 559         rt2x00_set_field32(&reg, CSR11_SLOT_TIME, libconf->slot_time);
 560         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 561
 562         rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
 563         rt2x00_set_field32(&reg, CSR18_SIFS, libconf->sifs);
 564         rt2x00_set_field32(&reg, CSR18_PIFS, libconf->pifs);
 565         rt2x00pci_register_write(rt2x00dev, CSR18, reg);
 566
 567         rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
 568         rt2x00_set_field32(&reg, CSR19_DIFS, libconf->difs);
 569         rt2x00_set_field32(&reg, CSR19_EIFS, libconf->eifs);
 570         rt2x00pci_register_write(rt2x00dev, CSR19, reg);
 571
 572         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 573         rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
 574         rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
 575         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 576
 577         rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
 578         rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
 579                            libconf->conf->beacon_int * 16);
 580         rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
 581                            libconf->conf->beacon_int * 16);
 582         rt2x00pci_register_write(rt2x00dev, CSR12, reg);
 583 }
 584
 585 static void rt2500pci_config(struct rt2x00_dev *rt2x00dev,
 586                              struct rt2x00lib_conf *libconf,
 587                              const unsigned int flags)
 588 {
 589         if (flags & CONFIG_UPDATE_PHYMODE)
 590                 rt2500pci_config_phymode(rt2x00dev, libconf->basic_rates);
 591         if (flags & CONFIG_UPDATE_CHANNEL)
 592                 rt2500pci_config_channel(rt2x00dev, &libconf->rf,
 593                                          libconf->conf->power_level);
 594         if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
 595                 rt2500pci_config_txpower(rt2x00dev,
 596                                          libconf->conf->power_level);
 597         if (flags & CONFIG_UPDATE_ANTENNA)
 598                 rt2500pci_config_antenna(rt2x00dev, &libconf->ant);
 599         if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
 600                 rt2500pci_config_duration(rt2x00dev, libconf);
 601 }
 602
 603 /*
 604  * Link tuning
 605  */
 606 static void rt2500pci_link_stats(struct rt2x00_dev *rt2x00dev,
 607                                  struct link_qual *qual)
 608 {
 609         u32 reg;
 610
 611         /*
 612          * Update FCS error count from register.
 613          */
 614         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 615         qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
 616
 617         /*
 618          * Update False CCA count from register.
 619          */
 620         rt2x00pci_register_read(rt2x00dev, CNT3, &reg);
 621         qual->false_cca = rt2x00_get_field32(reg, CNT3_FALSE_CCA);
 622 }
 623
 624 static void rt2500pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
 625 {
 626         rt2500pci_bbp_write(rt2x00dev, 17, 0x48);
 627         rt2x00dev->link.vgc_level = 0x48;
 628 }
 629
 630 static void rt2500pci_link_tuner(struct rt2x00_dev *rt2x00dev)
 631 {
 632         int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
 633         u8 r17;
 634
 635         /*
 636          * To prevent collisions with MAC ASIC on chipsets
 637          * up to version C the link tuning should halt after 20
 638          * seconds while being associated.
 639          */
 640         if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D &&
 641             rt2x00dev->intf_associated &&
 642             rt2x00dev->link.count > 20)
 643                 return;
 644
 645         rt2500pci_bbp_read(rt2x00dev, 17, &r17);
 646
 647         /*
 648          * Chipset versions C and lower should directly continue
 649          * to the dynamic CCA tuning. Chipset version D and higher
 650          * should go straight to dynamic CCA tuning when they
 651          * are not associated.
 652          */
 653         if (rt2x00_rev(&rt2x00dev->chip) < RT2560_VERSION_D ||
 654             !rt2x00dev->intf_associated)
 655                 goto dynamic_cca_tune;
 656
 657         /*
 658          * A too low RSSI will cause too much false CCA which will
 659          * then corrupt the R17 tuning. To remidy this the tuning should
 660          * be stopped (While making sure the R17 value will not exceed limits)
 661          */
 662         if (rssi < -80 && rt2x00dev->link.count > 20) {
 663                 if (r17 >= 0x41) {
 664                         r17 = rt2x00dev->link.vgc_level;
 665                         rt2500pci_bbp_write(rt2x00dev, 17, r17);
 666                 }
 667                 return;
 668         }
 669
 670         /*
 671          * Special big-R17 for short distance
 672          */
 673         if (rssi >= -58) {
 674                 if (r17 != 0x50)
 675                         rt2500pci_bbp_write(rt2x00dev, 17, 0x50);
 676                 return;
 677         }
 678
 679         /*
 680          * Special mid-R17 for middle distance
 681          */
 682         if (rssi >= -74) {
 683                 if (r17 != 0x41)
 684                         rt2500pci_bbp_write(rt2x00dev, 17, 0x41);
 685                 return;
 686         }
 687
 688         /*
 689          * Leave short or middle distance condition, restore r17
 690          * to the dynamic tuning range.
 691          */
 692         if (r17 >= 0x41) {
 693                 rt2500pci_bbp_write(rt2x00dev, 17, rt2x00dev->link.vgc_level);
 694                 return;
 695         }
 696
 697 dynamic_cca_tune:
 698
 699         /*
 700          * R17 is inside the dynamic tuning range,
 701          * start tuning the link based on the false cca counter.
 702          */
 703         if (rt2x00dev->link.qual.false_cca > 512 && r17 < 0x40) {
 704                 rt2500pci_bbp_write(rt2x00dev, 17, ++r17);
 705                 rt2x00dev->link.vgc_level = r17;
 706         } else if (rt2x00dev->link.qual.false_cca < 100 && r17 > 0x32) {
 707                 rt2500pci_bbp_write(rt2x00dev, 17, --r17);
 708                 rt2x00dev->link.vgc_level = r17;
 709         }
 710 }
 711
 712 /*
 713  * Initialization functions.
 714  */
 715 static void rt2500pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
 716                                    struct queue_entry *entry)
 717 {
 718         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 719         u32 word;
 720
 721         rt2x00_desc_read(entry_priv->desc, 1, &word);
 722         rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, entry_priv->data_dma);
 723         rt2x00_desc_write(entry_priv->desc, 1, word);
 724
 725         rt2x00_desc_read(entry_priv->desc, 0, &word);
 726         rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
 727         rt2x00_desc_write(entry_priv->desc, 0, word);
 728 }
 729
 730 static void rt2500pci_init_txentry(struct rt2x00_dev *rt2x00dev,
 731                                    struct queue_entry *entry)
 732 {
 733         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 734         u32 word;
 735
 736         rt2x00_desc_read(entry_priv->desc, 0, &word);
 737         rt2x00_set_field32(&word, TXD_W0_VALID, 0);
 738         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
 739         rt2x00_desc_write(entry_priv->desc, 0, word);
 740 }
 741
 742 static int rt2500pci_init_queues(struct rt2x00_dev *rt2x00dev)
 743 {
 744         struct queue_entry_priv_pci *entry_priv;
 745         u32 reg;
 746
 747         /*
 748          * Initialize registers.
 749          */
 750         rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
 751         rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
 752         rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
 753         rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
 754         rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
 755         rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
 756
 757         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
 758         rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
 759         rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
 760                            entry_priv->desc_dma);
 761         rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
 762
 763         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
 764         rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
 765         rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
 766                            entry_priv->desc_dma);
 767         rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
 768
 769         entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
 770         rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
 771         rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
 772                            entry_priv->desc_dma);
 773         rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
 774
 775         entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
 776         rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
 777         rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
 778                            entry_priv->desc_dma);
 779         rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
 780
 781         rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
 782         rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
 783         rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
 784         rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
 785
 786         entry_priv = rt2x00dev->rx->entries[0].priv_data;
 787         rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
 788         rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
 789                            entry_priv->desc_dma);
 790         rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
 791
 792         return 0;
 793 }
 794
 795 static int rt2500pci_init_registers(struct rt2x00_dev *rt2x00dev)
 796 {
 797         u32 reg;
 798
 799         rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
 800         rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
 801         rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00020002);
 802         rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
 803
 804         rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
 805         rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
 806         rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
 807         rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
 808         rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
 809
 810         rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
 811         rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
 812                            rt2x00dev->rx->data_size / 128);
 813         rt2x00pci_register_write(rt2x00dev, CSR9, reg);
 814
 815         /*
 816          * Always use CWmin and CWmax set in descriptor.
 817          */
 818         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 819         rt2x00_set_field32(&reg, CSR11_CW_SELECT, 0);
 820         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 821
 822         rt2x00pci_register_write(rt2x00dev, CNT3, 0);
 823
 824         rt2x00pci_register_read(rt2x00dev, TXCSR8, &reg);
 825         rt2x00_set_field32(&reg, TXCSR8_BBP_ID0, 10);
 826         rt2x00_set_field32(&reg, TXCSR8_BBP_ID0_VALID, 1);
 827         rt2x00_set_field32(&reg, TXCSR8_BBP_ID1, 11);
 828         rt2x00_set_field32(&reg, TXCSR8_BBP_ID1_VALID, 1);
 829         rt2x00_set_field32(&reg, TXCSR8_BBP_ID2, 13);
 830         rt2x00_set_field32(&reg, TXCSR8_BBP_ID2_VALID, 1);
 831         rt2x00_set_field32(&reg, TXCSR8_BBP_ID3, 12);
 832         rt2x00_set_field32(&reg, TXCSR8_BBP_ID3_VALID, 1);
 833         rt2x00pci_register_write(rt2x00dev, TXCSR8, reg);
 834
 835         rt2x00pci_register_read(rt2x00dev, ARTCSR0, &reg);
 836         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_1MBS, 112);
 837         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_2MBS, 56);
 838         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_5_5MBS, 20);
 839         rt2x00_set_field32(&reg, ARTCSR0_ACK_CTS_11MBS, 10);
 840         rt2x00pci_register_write(rt2x00dev, ARTCSR0, reg);
 841
 842         rt2x00pci_register_read(rt2x00dev, ARTCSR1, &reg);
 843         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_6MBS, 45);
 844         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_9MBS, 37);
 845         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_12MBS, 33);
 846         rt2x00_set_field32(&reg, ARTCSR1_ACK_CTS_18MBS, 29);
 847         rt2x00pci_register_write(rt2x00dev, ARTCSR1, reg);
 848
 849         rt2x00pci_register_read(rt2x00dev, ARTCSR2, &reg);
 850         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_24MBS, 29);
 851         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_36MBS, 25);
 852         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_48MBS, 25);
 853         rt2x00_set_field32(&reg, ARTCSR2_ACK_CTS_54MBS, 25);
 854         rt2x00pci_register_write(rt2x00dev, ARTCSR2, reg);
 855
 856         rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
 857         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 47); /* CCK Signal */
 858         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
 859         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 51); /* Rssi */
 860         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
 861         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 42); /* OFDM Rate */
 862         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
 863         rt2x00_set_field32(&reg, RXCSR3_BBP_ID3, 51); /* RSSI */
 864         rt2x00_set_field32(&reg, RXCSR3_BBP_ID3_VALID, 1);
 865         rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
 866
 867         rt2x00pci_register_read(rt2x00dev, PCICSR, &reg);
 868         rt2x00_set_field32(&reg, PCICSR_BIG_ENDIAN, 0);
 869         rt2x00_set_field32(&reg, PCICSR_RX_TRESHOLD, 0);
 870         rt2x00_set_field32(&reg, PCICSR_TX_TRESHOLD, 3);
 871         rt2x00_set_field32(&reg, PCICSR_BURST_LENTH, 1);
 872         rt2x00_set_field32(&reg, PCICSR_ENABLE_CLK, 1);
 873         rt2x00_set_field32(&reg, PCICSR_READ_MULTIPLE, 1);
 874         rt2x00_set_field32(&reg, PCICSR_WRITE_INVALID, 1);
 875         rt2x00pci_register_write(rt2x00dev, PCICSR, reg);
 876
 877         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
 878
 879         rt2x00pci_register_write(rt2x00dev, GPIOCSR, 0x0000ff00);
 880         rt2x00pci_register_write(rt2x00dev, TESTCSR, 0x000000f0);
 881
 882         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
 883                 return -EBUSY;
 884
 885         rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00213223);
 886         rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
 887
 888         rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
 889         rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
 890         rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
 891
 892         rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
 893         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
 894         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 26);
 895         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID0, 1);
 896         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
 897         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 26);
 898         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_VALID1, 1);
 899         rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
 900
 901         rt2x00pci_register_write(rt2x00dev, BBPCSR1, 0x82188200);
 902
 903         rt2x00pci_register_write(rt2x00dev, TXACKCSR0, 0x00000020);
 904
 905         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 906         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
 907         rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
 908         rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
 909         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 910
 911         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 912         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
 913         rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
 914         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 915
 916         /*
 917          * We must clear the FCS and FIFO error count.
 918          * These registers are cleared on read,
 919          * so we may pass a useless variable to store the value.
 920          */
 921         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 922         rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
 923
 924         return 0;
 925 }
 926
 927 static int rt2500pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
 928 {
 929         unsigned int i;
 930         u8 value;
 931
 932         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 933                 rt2500pci_bbp_read(rt2x00dev, 0, &value);
 934                 if ((value != 0xff) && (value != 0x00))
 935                         return 0;
 936                 udelay(REGISTER_BUSY_DELAY);
 937         }
 938
 939         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
 940         return -EACCES;
 941 }
 942
 943 static int rt2500pci_init_bbp(struct rt2x00_dev *rt2x00dev)
 944 {
 945         unsigned int i;
 946         u16 eeprom;
 947         u8 reg_id;
 948         u8 value;
 949
 950         if (unlikely(rt2500pci_wait_bbp_ready(rt2x00dev)))
 951                 return -EACCES;
 952
 953         rt2500pci_bbp_write(rt2x00dev, 3, 0x02);
 954         rt2500pci_bbp_write(rt2x00dev, 4, 0x19);
 955         rt2500pci_bbp_write(rt2x00dev, 14, 0x1c);
 956         rt2500pci_bbp_write(rt2x00dev, 15, 0x30);
 957         rt2500pci_bbp_write(rt2x00dev, 16, 0xac);
 958         rt2500pci_bbp_write(rt2x00dev, 18, 0x18);
 959         rt2500pci_bbp_write(rt2x00dev, 19, 0xff);
 960         rt2500pci_bbp_write(rt2x00dev, 20, 0x1e);
 961         rt2500pci_bbp_write(rt2x00dev, 21, 0x08);
 962         rt2500pci_bbp_write(rt2x00dev, 22, 0x08);
 963         rt2500pci_bbp_write(rt2x00dev, 23, 0x08);
 964         rt2500pci_bbp_write(rt2x00dev, 24, 0x70);
 965         rt2500pci_bbp_write(rt2x00dev, 25, 0x40);
 966         rt2500pci_bbp_write(rt2x00dev, 26, 0x08);
 967         rt2500pci_bbp_write(rt2x00dev, 27, 0x23);
 968         rt2500pci_bbp_write(rt2x00dev, 30, 0x10);
 969         rt2500pci_bbp_write(rt2x00dev, 31, 0x2b);
 970         rt2500pci_bbp_write(rt2x00dev, 32, 0xb9);
 971         rt2500pci_bbp_write(rt2x00dev, 34, 0x12);
 972         rt2500pci_bbp_write(rt2x00dev, 35, 0x50);
 973         rt2500pci_bbp_write(rt2x00dev, 39, 0xc4);
 974         rt2500pci_bbp_write(rt2x00dev, 40, 0x02);
 975         rt2500pci_bbp_write(rt2x00dev, 41, 0x60);
 976         rt2500pci_bbp_write(rt2x00dev, 53, 0x10);
 977         rt2500pci_bbp_write(rt2x00dev, 54, 0x18);
 978         rt2500pci_bbp_write(rt2x00dev, 56, 0x08);
 979         rt2500pci_bbp_write(rt2x00dev, 57, 0x10);
 980         rt2500pci_bbp_write(rt2x00dev, 58, 0x08);
 981         rt2500pci_bbp_write(rt2x00dev, 61, 0x6d);
 982         rt2500pci_bbp_write(rt2x00dev, 62, 0x10);
 983
 984         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
 985                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
 986
 987                 if (eeprom != 0xffff && eeprom != 0x0000) {
 988                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
 989                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
 990                         rt2500pci_bbp_write(rt2x00dev, reg_id, value);
 991                 }
 992         }
 993
 994         return 0;
 995 }
 996
 997 /*
 998  * Device state switch handlers.
 999  */
1000 static void rt2500pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1001                                 enum dev_state state)
1002 {
1003         u32 reg;
1004
1005         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1006         rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
1007                            (state == STATE_RADIO_RX_OFF) ||
1008                            (state == STATE_RADIO_RX_OFF_LINK));
1009         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1010 }
1011
1012 static void rt2500pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1013                                  enum dev_state state)
1014 {
1015         int mask = (state == STATE_RADIO_IRQ_OFF);
1016         u32 reg;
1017
1018         /*
1019          * When interrupts are being enabled, the interrupt registers
1020          * should clear the register to assure a clean state.
1021          */
1022         if (state == STATE_RADIO_IRQ_ON) {
1023                 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1024                 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1025         }
1026
1027         /*
1028          * Only toggle the interrupts bits we are going to use.
1029          * Non-checked interrupt bits are disabled by default.
1030          */
1031         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
1032         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
1033         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
1034         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
1035         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
1036         rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
1037         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
1038 }
1039
1040 static int rt2500pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1041 {
1042         /*
1043          * Initialize all registers.
1044          */
1045         if (unlikely(rt2500pci_init_queues(rt2x00dev) ||
1046                      rt2500pci_init_registers(rt2x00dev) ||
1047                      rt2500pci_init_bbp(rt2x00dev)))
1048                 return -EIO;
1049
1050         return 0;
1051 }
1052
1053 static void rt2500pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1054 {
1055         u32 reg;
1056
1057         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
1058
1059         /*
1060          * Disable synchronisation.
1061          */
1062         rt2x00pci_register_write(rt2x00dev, CSR14, 0);
1063
1064         /*
1065          * Cancel RX and TX.
1066          */
1067         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1068         rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
1069         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1070 }
1071
1072 static int rt2500pci_set_state(struct rt2x00_dev *rt2x00dev,
1073                                enum dev_state state)
1074 {
1075         u32 reg;
1076         unsigned int i;
1077         char put_to_sleep;
1078         char bbp_state;
1079         char rf_state;
1080
1081         put_to_sleep = (state != STATE_AWAKE);
1082
1083         rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1084         rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
1085         rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
1086         rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
1087         rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
1088         rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
1089
1090         /*
1091          * Device is not guaranteed to be in the requested state yet.
1092          * We must wait until the register indicates that the
1093          * device has entered the correct state.
1094          */
1095         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1096                 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
1097                 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
1098                 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
1099                 if (bbp_state == state && rf_state == state)
1100                         return 0;
1101                 msleep(10);
1102         }
1103
1104         return -EBUSY;
1105 }
1106
1107 static int rt2500pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1108                                       enum dev_state state)
1109 {
1110         int retval = 0;
1111
1112         switch (state) {
1113         case STATE_RADIO_ON:
1114                 retval = rt2500pci_enable_radio(rt2x00dev);
1115                 break;
1116         case STATE_RADIO_OFF:
1117                 rt2500pci_disable_radio(rt2x00dev);
1118                 break;
1119         case STATE_RADIO_RX_ON:
1120         case STATE_RADIO_RX_ON_LINK:
1121         case STATE_RADIO_RX_OFF:
1122         case STATE_RADIO_RX_OFF_LINK:
1123                 rt2500pci_toggle_rx(rt2x00dev, state);
1124                 break;
1125         case STATE_RADIO_IRQ_ON:
1126         case STATE_RADIO_IRQ_OFF:
1127                 rt2500pci_toggle_irq(rt2x00dev, state);
1128                 break;
1129         case STATE_DEEP_SLEEP:
1130         case STATE_SLEEP:
1131         case STATE_STANDBY:
1132         case STATE_AWAKE:
1133                 retval = rt2500pci_set_state(rt2x00dev, state);
1134                 break;
1135         default:
1136                 retval = -ENOTSUPP;
1137                 break;
1138         }
1139
1140         if (unlikely(retval))
1141                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
1142                       state, retval);
1143
1144         return retval;
1145 }
1146
1147 /*
1148  * TX descriptor initialization
1149  */
1150 static void rt2500pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1151                                     struct sk_buff *skb,
1152                                     struct txentry_desc *txdesc)
1153 {
1154         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
1155         struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
1156         __le32 *txd = skbdesc->desc;
1157         u32 word;
1158
1159         /*
1160          * Start writing the descriptor words.
1161          */
1162         rt2x00_desc_read(entry_priv->desc, 1, &word);
1163         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, entry_priv->data_dma);
1164         rt2x00_desc_write(entry_priv->desc, 1, word);
1165
1166         rt2x00_desc_read(txd, 2, &word);
1167         rt2x00_set_field32(&word, TXD_W2_IV_OFFSET, IEEE80211_HEADER);
1168         rt2x00_set_field32(&word, TXD_W2_AIFS, txdesc->aifs);
1169         rt2x00_set_field32(&word, TXD_W2_CWMIN, txdesc->cw_min);
1170         rt2x00_set_field32(&word, TXD_W2_CWMAX, txdesc->cw_max);
1171         rt2x00_desc_write(txd, 2, word);
1172
1173         rt2x00_desc_read(txd, 3, &word);
1174         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1175         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1176         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW, txdesc->length_low);
1177         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH, txdesc->length_high);
1178         rt2x00_desc_write(txd, 3, word);
1179
1180         rt2x00_desc_read(txd, 10, &word);
1181         rt2x00_set_field32(&word, TXD_W10_RTS,
1182                            test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1183         rt2x00_desc_write(txd, 10, word);
1184
1185         rt2x00_desc_read(txd, 0, &word);
1186         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1187         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1188         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1189                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1190         rt2x00_set_field32(&word, TXD_W0_ACK,
1191                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1192         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1193                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1194         rt2x00_set_field32(&word, TXD_W0_OFDM,
1195                            test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
1196         rt2x00_set_field32(&word, TXD_W0_CIPHER_OWNER, 1);
1197         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1198         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1199                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1200         rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1201         rt2x00_desc_write(txd, 0, word);
1202 }
1203
1204 /*
1205  * TX data initialization
1206  */
1207 static void rt2500pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1208                                     const enum data_queue_qid queue)
1209 {
1210         u32 reg;
1211
1212         if (queue == QID_BEACON) {
1213                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1214                 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1215                         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1216                         rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1217                         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1218                         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1219                 }
1220                 return;
1221         }
1222
1223         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1224         rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1225         rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1226         rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
1227         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1228 }
1229
1230 /*
1231  * RX control handlers
1232  */
1233 static void rt2500pci_fill_rxdone(struct queue_entry *entry,
1234                                   struct rxdone_entry_desc *rxdesc)
1235 {
1236         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1237         u32 word0;
1238         u32 word2;
1239
1240         rt2x00_desc_read(entry_priv->desc, 0, &word0);
1241         rt2x00_desc_read(entry_priv->desc, 2, &word2);
1242
1243         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1244                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1245         if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1246                 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1247
1248         /*
1249          * Obtain the status about this packet.
1250          * When frame was received with an OFDM bitrate,
1251          * the signal is the PLCP value. If it was received with
1252          * a CCK bitrate the signal is the rate in 100kbit/s.
1253          */
1254         rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1255         rxdesc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1256             entry->queue->rt2x00dev->rssi_offset;
1257         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1258
1259         if (rt2x00_get_field32(word0, RXD_W0_OFDM))
1260                 rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1261         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1262                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1263 }
1264
1265 /*
1266  * Interrupt functions.
1267  */
1268 static void rt2500pci_txdone(struct rt2x00_dev *rt2x00dev,
1269                              const enum data_queue_qid queue_idx)
1270 {
1271         struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1272         struct queue_entry_priv_pci *entry_priv;
1273         struct queue_entry *entry;
1274         struct txdone_entry_desc txdesc;
1275         u32 word;
1276
1277         while (!rt2x00queue_empty(queue)) {
1278                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1279                 entry_priv = entry->priv_data;
1280                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1281
1282                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1283                     !rt2x00_get_field32(word, TXD_W0_VALID))
1284                         break;
1285
1286                 /*
1287                  * Obtain the status about this packet.
1288                  */
1289                 txdesc.flags = 0;
1290                 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1291                 case 0: /* Success */
1292                 case 1: /* Success with retry */
1293                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1294                         break;
1295                 case 2: /* Failure, excessive retries */
1296                         __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1297                         /* Don't break, this is a failed frame! */
1298                 default: /* Failure */
1299                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
1300                 }
1301                 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1302
1303                 rt2x00pci_txdone(rt2x00dev, entry, &txdesc);
1304         }
1305 }
1306
1307 static irqreturn_t rt2500pci_interrupt(int irq, void *dev_instance)
1308 {
1309         struct rt2x00_dev *rt2x00dev = dev_instance;
1310         u32 reg;
1311
1312         /*
1313          * Get the interrupt sources & saved to local variable.
1314          * Write register value back to clear pending interrupts.
1315          */
1316         rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1317         rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1318
1319         if (!reg)
1320                 return IRQ_NONE;
1321
1322         if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1323                 return IRQ_HANDLED;
1324
1325         /*
1326          * Handle interrupts, walk through all bits
1327          * and run the tasks, the bits are checked in order of
1328          * priority.
1329          */
1330
1331         /*
1332          * 1 - Beacon timer expired interrupt.
1333          */
1334         if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1335                 rt2x00lib_beacondone(rt2x00dev);
1336
1337         /*
1338          * 2 - Rx ring done interrupt.
1339          */
1340         if (rt2x00_get_field32(reg, CSR7_RXDONE))
1341                 rt2x00pci_rxdone(rt2x00dev);
1342
1343         /*
1344          * 3 - Atim ring transmit done interrupt.
1345          */
1346         if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1347                 rt2500pci_txdone(rt2x00dev, QID_ATIM);
1348
1349         /*
1350          * 4 - Priority ring transmit done interrupt.
1351          */
1352         if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1353                 rt2500pci_txdone(rt2x00dev, QID_AC_BE);
1354
1355         /*
1356          * 5 - Tx ring transmit done interrupt.
1357          */
1358         if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1359                 rt2500pci_txdone(rt2x00dev, QID_AC_BK);
1360
1361         return IRQ_HANDLED;
1362 }
1363
1364 /*
1365  * Device probe functions.
1366  */
1367 static int rt2500pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1368 {
1369         struct eeprom_93cx6 eeprom;
1370         u32 reg;
1371         u16 word;
1372         u8 *mac;
1373
1374         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1375
1376         eeprom.data = rt2x00dev;
1377         eeprom.register_read = rt2500pci_eepromregister_read;
1378         eeprom.register_write = rt2500pci_eepromregister_write;
1379         eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1380             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1381         eeprom.reg_data_in = 0;
1382         eeprom.reg_data_out = 0;
1383         eeprom.reg_data_clock = 0;
1384         eeprom.reg_chip_select = 0;
1385
1386         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1387                                EEPROM_SIZE / sizeof(u16));
1388
1389         /*
1390          * Start validation of the data that has been read.
1391          */
1392         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1393         if (!is_valid_ether_addr(mac)) {
1394                 DECLARE_MAC_BUF(macbuf);
1395
1396                 random_ether_addr(mac);
1397                 EEPROM(rt2x00dev, "MAC: %s\n",
1398                        print_mac(macbuf, mac));
1399         }
1400
1401         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1402         if (word == 0xffff) {
1403                 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1404                 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT,
1405                                    ANTENNA_SW_DIVERSITY);
1406                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT,
1407                                    ANTENNA_SW_DIVERSITY);
1408                 rt2x00_set_field16(&word, EEPROM_ANTENNA_LED_MODE,
1409                                    LED_MODE_DEFAULT);
1410                 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1411                 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1412                 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF2522);
1413                 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1414                 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1415         }
1416
1417         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1418         if (word == 0xffff) {
1419                 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1420                 rt2x00_set_field16(&word, EEPROM_NIC_DYN_BBP_TUNE, 0);
1421                 rt2x00_set_field16(&word, EEPROM_NIC_CCK_TX_POWER, 0);
1422                 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1423                 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
1424         }
1425
1426         rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &word);
1427         if (word == 0xffff) {
1428                 rt2x00_set_field16(&word, EEPROM_CALIBRATE_OFFSET_RSSI,
1429                                    DEFAULT_RSSI_OFFSET);
1430                 rt2x00_eeprom_write(rt2x00dev, EEPROM_CALIBRATE_OFFSET, word);
1431                 EEPROM(rt2x00dev, "Calibrate offset: 0x%04x\n", word);
1432         }
1433
1434         return 0;
1435 }
1436
1437 static int rt2500pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1438 {
1439         u32 reg;
1440         u16 value;
1441         u16 eeprom;
1442
1443         /*
1444          * Read EEPROM word for configuration.
1445          */
1446         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1447
1448         /*
1449          * Identify RF chipset.
1450          */
1451         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1452         rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1453         rt2x00_set_chip(rt2x00dev, RT2560, value, reg);
1454
1455         if (!rt2x00_rf(&rt2x00dev->chip, RF2522) &&
1456             !rt2x00_rf(&rt2x00dev->chip, RF2523) &&
1457             !rt2x00_rf(&rt2x00dev->chip, RF2524) &&
1458             !rt2x00_rf(&rt2x00dev->chip, RF2525) &&
1459             !rt2x00_rf(&rt2x00dev->chip, RF2525E) &&
1460             !rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1461                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1462                 return -ENODEV;
1463         }
1464
1465         /*
1466          * Identify default antenna configuration.
1467          */
1468         rt2x00dev->default_ant.tx =
1469             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1470         rt2x00dev->default_ant.rx =
1471             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1472
1473         /*
1474          * Store led mode, for correct led behaviour.
1475          */
1476 #ifdef CONFIG_RT2500PCI_LEDS
1477         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1478
1479         rt2x00dev->led_radio.rt2x00dev = rt2x00dev;
1480         rt2x00dev->led_radio.type = LED_TYPE_RADIO;
1481         rt2x00dev->led_radio.led_dev.brightness_set =
1482             rt2500pci_brightness_set;
1483         rt2x00dev->led_radio.led_dev.blink_set =
1484             rt2500pci_blink_set;
1485         rt2x00dev->led_radio.flags = LED_INITIALIZED;
1486
1487         if (value == LED_MODE_TXRX_ACTIVITY) {
1488                 rt2x00dev->led_qual.rt2x00dev = rt2x00dev;
1489                 rt2x00dev->led_qual.type = LED_TYPE_ACTIVITY;
1490                 rt2x00dev->led_qual.led_dev.brightness_set =
1491                     rt2500pci_brightness_set;
1492                 rt2x00dev->led_qual.led_dev.blink_set =
1493                     rt2500pci_blink_set;
1494                 rt2x00dev->led_qual.flags = LED_INITIALIZED;
1495         }
1496 #endif /* CONFIG_RT2500PCI_LEDS */
1497
1498         /*
1499          * Detect if this device has an hardware controlled radio.
1500          */
1501 #ifdef CONFIG_RT2500PCI_RFKILL
1502         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1503                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1504 #endif /* CONFIG_RT2500PCI_RFKILL */
1505
1506         /*
1507          * Check if the BBP tuning should be enabled.
1508          */
1509         rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
1510
1511         if (rt2x00_get_field16(eeprom, EEPROM_NIC_DYN_BBP_TUNE))
1512                 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1513
1514         /*
1515          * Read the RSSI <-> dBm offset information.
1516          */
1517         rt2x00_eeprom_read(rt2x00dev, EEPROM_CALIBRATE_OFFSET, &eeprom);
1518         rt2x00dev->rssi_offset =
1519             rt2x00_get_field16(eeprom, EEPROM_CALIBRATE_OFFSET_RSSI);
1520
1521         return 0;
1522 }
1523
1524 /*
1525  * RF value list for RF2522
1526  * Supports: 2.4 GHz
1527  */
1528 static const struct rf_channel rf_vals_bg_2522[] = {
1529         { 1,  0x00002050, 0x000c1fda, 0x00000101, 0 },
1530         { 2,  0x00002050, 0x000c1fee, 0x00000101, 0 },
1531         { 3,  0x00002050, 0x000c2002, 0x00000101, 0 },
1532         { 4,  0x00002050, 0x000c2016, 0x00000101, 0 },
1533         { 5,  0x00002050, 0x000c202a, 0x00000101, 0 },
1534         { 6,  0x00002050, 0x000c203e, 0x00000101, 0 },
1535         { 7,  0x00002050, 0x000c2052, 0x00000101, 0 },
1536         { 8,  0x00002050, 0x000c2066, 0x00000101, 0 },
1537         { 9,  0x00002050, 0x000c207a, 0x00000101, 0 },
1538         { 10, 0x00002050, 0x000c208e, 0x00000101, 0 },
1539         { 11, 0x00002050, 0x000c20a2, 0x00000101, 0 },
1540         { 12, 0x00002050, 0x000c20b6, 0x00000101, 0 },
1541         { 13, 0x00002050, 0x000c20ca, 0x00000101, 0 },
1542         { 14, 0x00002050, 0x000c20fa, 0x00000101, 0 },
1543 };
1544
1545 /*
1546  * RF value list for RF2523
1547  * Supports: 2.4 GHz
1548  */
1549 static const struct rf_channel rf_vals_bg_2523[] = {
1550         { 1,  0x00022010, 0x00000c9e, 0x000e0111, 0x00000a1b },
1551         { 2,  0x00022010, 0x00000ca2, 0x000e0111, 0x00000a1b },
1552         { 3,  0x00022010, 0x00000ca6, 0x000e0111, 0x00000a1b },
1553         { 4,  0x00022010, 0x00000caa, 0x000e0111, 0x00000a1b },
1554         { 5,  0x00022010, 0x00000cae, 0x000e0111, 0x00000a1b },
1555         { 6,  0x00022010, 0x00000cb2, 0x000e0111, 0x00000a1b },
1556         { 7,  0x00022010, 0x00000cb6, 0x000e0111, 0x00000a1b },
1557         { 8,  0x00022010, 0x00000cba, 0x000e0111, 0x00000a1b },
1558         { 9,  0x00022010, 0x00000cbe, 0x000e0111, 0x00000a1b },
1559         { 10, 0x00022010, 0x00000d02, 0x000e0111, 0x00000a1b },
1560         { 11, 0x00022010, 0x00000d06, 0x000e0111, 0x00000a1b },
1561         { 12, 0x00022010, 0x00000d0a, 0x000e0111, 0x00000a1b },
1562         { 13, 0x00022010, 0x00000d0e, 0x000e0111, 0x00000a1b },
1563         { 14, 0x00022010, 0x00000d1a, 0x000e0111, 0x00000a03 },
1564 };
1565
1566 /*
1567  * RF value list for RF2524
1568  * Supports: 2.4 GHz
1569  */
1570 static const struct rf_channel rf_vals_bg_2524[] = {
1571         { 1,  0x00032020, 0x00000c9e, 0x00000101, 0x00000a1b },
1572         { 2,  0x00032020, 0x00000ca2, 0x00000101, 0x00000a1b },
1573         { 3,  0x00032020, 0x00000ca6, 0x00000101, 0x00000a1b },
1574         { 4,  0x00032020, 0x00000caa, 0x00000101, 0x00000a1b },
1575         { 5,  0x00032020, 0x00000cae, 0x00000101, 0x00000a1b },
1576         { 6,  0x00032020, 0x00000cb2, 0x00000101, 0x00000a1b },
1577         { 7,  0x00032020, 0x00000cb6, 0x00000101, 0x00000a1b },
1578         { 8,  0x00032020, 0x00000cba, 0x00000101, 0x00000a1b },
1579         { 9,  0x00032020, 0x00000cbe, 0x00000101, 0x00000a1b },
1580         { 10, 0x00032020, 0x00000d02, 0x00000101, 0x00000a1b },
1581         { 11, 0x00032020, 0x00000d06, 0x00000101, 0x00000a1b },
1582         { 12, 0x00032020, 0x00000d0a, 0x00000101, 0x00000a1b },
1583         { 13, 0x00032020, 0x00000d0e, 0x00000101, 0x00000a1b },
1584         { 14, 0x00032020, 0x00000d1a, 0x00000101, 0x00000a03 },
1585 };
1586
1587 /*
1588  * RF value list for RF2525
1589  * Supports: 2.4 GHz
1590  */
1591 static const struct rf_channel rf_vals_bg_2525[] = {
1592         { 1,  0x00022020, 0x00080c9e, 0x00060111, 0x00000a1b },
1593         { 2,  0x00022020, 0x00080ca2, 0x00060111, 0x00000a1b },
1594         { 3,  0x00022020, 0x00080ca6, 0x00060111, 0x00000a1b },
1595         { 4,  0x00022020, 0x00080caa, 0x00060111, 0x00000a1b },
1596         { 5,  0x00022020, 0x00080cae, 0x00060111, 0x00000a1b },
1597         { 6,  0x00022020, 0x00080cb2, 0x00060111, 0x00000a1b },
1598         { 7,  0x00022020, 0x00080cb6, 0x00060111, 0x00000a1b },
1599         { 8,  0x00022020, 0x00080cba, 0x00060111, 0x00000a1b },
1600         { 9,  0x00022020, 0x00080cbe, 0x00060111, 0x00000a1b },
1601         { 10, 0x00022020, 0x00080d02, 0x00060111, 0x00000a1b },
1602         { 11, 0x00022020, 0x00080d06, 0x00060111, 0x00000a1b },
1603         { 12, 0x00022020, 0x00080d0a, 0x00060111, 0x00000a1b },
1604         { 13, 0x00022020, 0x00080d0e, 0x00060111, 0x00000a1b },
1605         { 14, 0x00022020, 0x00080d1a, 0x00060111, 0x00000a03 },
1606 };
1607
1608 /*
1609  * RF value list for RF2525e
1610  * Supports: 2.4 GHz
1611  */
1612 static const struct rf_channel rf_vals_bg_2525e[] = {
1613         { 1,  0x00022020, 0x00081136, 0x00060111, 0x00000a0b },
1614         { 2,  0x00022020, 0x0008113a, 0x00060111, 0x00000a0b },
1615         { 3,  0x00022020, 0x0008113e, 0x00060111, 0x00000a0b },
1616         { 4,  0x00022020, 0x00081182, 0x00060111, 0x00000a0b },
1617         { 5,  0x00022020, 0x00081186, 0x00060111, 0x00000a0b },
1618         { 6,  0x00022020, 0x0008118a, 0x00060111, 0x00000a0b },
1619         { 7,  0x00022020, 0x0008118e, 0x00060111, 0x00000a0b },
1620         { 8,  0x00022020, 0x00081192, 0x00060111, 0x00000a0b },
1621         { 9,  0x00022020, 0x00081196, 0x00060111, 0x00000a0b },
1622         { 10, 0x00022020, 0x0008119a, 0x00060111, 0x00000a0b },
1623         { 11, 0x00022020, 0x0008119e, 0x00060111, 0x00000a0b },
1624         { 12, 0x00022020, 0x000811a2, 0x00060111, 0x00000a0b },
1625         { 13, 0x00022020, 0x000811a6, 0x00060111, 0x00000a0b },
1626         { 14, 0x00022020, 0x000811ae, 0x00060111, 0x00000a1b },
1627 };
1628
1629 /*
1630  * RF value list for RF5222
1631  * Supports: 2.4 GHz & 5.2 GHz
1632  */
1633 static const struct rf_channel rf_vals_5222[] = {
1634         { 1,  0x00022020, 0x00001136, 0x00000101, 0x00000a0b },
1635         { 2,  0x00022020, 0x0000113a, 0x00000101, 0x00000a0b },
1636         { 3,  0x00022020, 0x0000113e, 0x00000101, 0x00000a0b },
1637         { 4,  0x00022020, 0x00001182, 0x00000101, 0x00000a0b },
1638         { 5,  0x00022020, 0x00001186, 0x00000101, 0x00000a0b },
1639         { 6,  0x00022020, 0x0000118a, 0x00000101, 0x00000a0b },
1640         { 7,  0x00022020, 0x0000118e, 0x00000101, 0x00000a0b },
1641         { 8,  0x00022020, 0x00001192, 0x00000101, 0x00000a0b },
1642         { 9,  0x00022020, 0x00001196, 0x00000101, 0x00000a0b },
1643         { 10, 0x00022020, 0x0000119a, 0x00000101, 0x00000a0b },
1644         { 11, 0x00022020, 0x0000119e, 0x00000101, 0x00000a0b },
1645         { 12, 0x00022020, 0x000011a2, 0x00000101, 0x00000a0b },
1646         { 13, 0x00022020, 0x000011a6, 0x00000101, 0x00000a0b },
1647         { 14, 0x00022020, 0x000011ae, 0x00000101, 0x00000a1b },
1648
1649         /* 802.11 UNI / HyperLan 2 */
1650         { 36, 0x00022010, 0x00018896, 0x00000101, 0x00000a1f },
1651         { 40, 0x00022010, 0x0001889a, 0x00000101, 0x00000a1f },
1652         { 44, 0x00022010, 0x0001889e, 0x00000101, 0x00000a1f },
1653         { 48, 0x00022010, 0x000188a2, 0x00000101, 0x00000a1f },
1654         { 52, 0x00022010, 0x000188a6, 0x00000101, 0x00000a1f },
1655         { 66, 0x00022010, 0x000188aa, 0x00000101, 0x00000a1f },
1656         { 60, 0x00022010, 0x000188ae, 0x00000101, 0x00000a1f },
1657         { 64, 0x00022010, 0x000188b2, 0x00000101, 0x00000a1f },
1658
1659         /* 802.11 HyperLan 2 */
1660         { 100, 0x00022010, 0x00008802, 0x00000101, 0x00000a0f },
1661         { 104, 0x00022010, 0x00008806, 0x00000101, 0x00000a0f },
1662         { 108, 0x00022010, 0x0000880a, 0x00000101, 0x00000a0f },
1663         { 112, 0x00022010, 0x0000880e, 0x00000101, 0x00000a0f },
1664         { 116, 0x00022010, 0x00008812, 0x00000101, 0x00000a0f },
1665         { 120, 0x00022010, 0x00008816, 0x00000101, 0x00000a0f },
1666         { 124, 0x00022010, 0x0000881a, 0x00000101, 0x00000a0f },
1667         { 128, 0x00022010, 0x0000881e, 0x00000101, 0x00000a0f },
1668         { 132, 0x00022010, 0x00008822, 0x00000101, 0x00000a0f },
1669         { 136, 0x00022010, 0x00008826, 0x00000101, 0x00000a0f },
1670
1671         /* 802.11 UNII */
1672         { 140, 0x00022010, 0x0000882a, 0x00000101, 0x00000a0f },
1673         { 149, 0x00022020, 0x000090a6, 0x00000101, 0x00000a07 },
1674         { 153, 0x00022020, 0x000090ae, 0x00000101, 0x00000a07 },
1675         { 157, 0x00022020, 0x000090b6, 0x00000101, 0x00000a07 },
1676         { 161, 0x00022020, 0x000090be, 0x00000101, 0x00000a07 },
1677 };
1678
1679 static void rt2500pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1680 {
1681         struct hw_mode_spec *spec = &rt2x00dev->spec;
1682         u8 *txpower;
1683         unsigned int i;
1684
1685         /*
1686          * Initialize all hw fields.
1687          */
1688         rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1689                                IEEE80211_HW_SIGNAL_DBM;
1690
1691         rt2x00dev->hw->extra_tx_headroom = 0;
1692
1693         SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1694         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1695                                 rt2x00_eeprom_addr(rt2x00dev,
1696                                                    EEPROM_MAC_ADDR_0));
1697
1698         /*
1699          * Convert tx_power array in eeprom.
1700          */
1701         txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1702         for (i = 0; i < 14; i++)
1703                 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1704
1705         /*
1706          * Initialize hw_mode information.
1707          */
1708         spec->supported_bands = SUPPORT_BAND_2GHZ;
1709         spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
1710         spec->tx_power_a = NULL;
1711         spec->tx_power_bg = txpower;
1712         spec->tx_power_default = DEFAULT_TXPOWER;
1713
1714         if (rt2x00_rf(&rt2x00dev->chip, RF2522)) {
1715                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2522);
1716                 spec->channels = rf_vals_bg_2522;
1717         } else if (rt2x00_rf(&rt2x00dev->chip, RF2523)) {
1718                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2523);
1719                 spec->channels = rf_vals_bg_2523;
1720         } else if (rt2x00_rf(&rt2x00dev->chip, RF2524)) {
1721                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2524);
1722                 spec->channels = rf_vals_bg_2524;
1723         } else if (rt2x00_rf(&rt2x00dev->chip, RF2525)) {
1724                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525);
1725                 spec->channels = rf_vals_bg_2525;
1726         } else if (rt2x00_rf(&rt2x00dev->chip, RF2525E)) {
1727                 spec->num_channels = ARRAY_SIZE(rf_vals_bg_2525e);
1728                 spec->channels = rf_vals_bg_2525e;
1729         } else if (rt2x00_rf(&rt2x00dev->chip, RF5222)) {
1730                 spec->supported_bands |= SUPPORT_BAND_5GHZ;
1731                 spec->num_channels = ARRAY_SIZE(rf_vals_5222);
1732                 spec->channels = rf_vals_5222;
1733         }
1734 }
1735
1736 static int rt2500pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1737 {
1738         int retval;
1739
1740         /*
1741          * Allocate eeprom data.
1742          */
1743         retval = rt2500pci_validate_eeprom(rt2x00dev);
1744         if (retval)
1745                 return retval;
1746
1747         retval = rt2500pci_init_eeprom(rt2x00dev);
1748         if (retval)
1749                 return retval;
1750
1751         /*
1752          * Initialize hw specifications.
1753          */
1754         rt2500pci_probe_hw_mode(rt2x00dev);
1755
1756         /*
1757          * This device requires the atim queue
1758          */
1759         __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1760
1761         /*
1762          * Set the rssi offset.
1763          */
1764         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1765
1766         return 0;
1767 }
1768
1769 /*
1770  * IEEE80211 stack callback functions.
1771  */
1772 static int rt2500pci_set_retry_limit(struct ieee80211_hw *hw,
1773                                      u32 short_retry, u32 long_retry)
1774 {
1775         struct rt2x00_dev *rt2x00dev = hw->priv;
1776         u32 reg;
1777
1778         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1779         rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1780         rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1781         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1782
1783         return 0;
1784 }
1785
1786 static u64 rt2500pci_get_tsf(struct ieee80211_hw *hw)
1787 {
1788         struct rt2x00_dev *rt2x00dev = hw->priv;
1789         u64 tsf;
1790         u32 reg;
1791
1792         rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1793         tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1794         rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1795         tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1796
1797         return tsf;
1798 }
1799
1800 static int rt2500pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
1801 {
1802         struct rt2x00_dev *rt2x00dev = hw->priv;
1803         struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1804         struct rt2x00_intf *intf = vif_to_intf(tx_info->control.vif);
1805         struct queue_entry_priv_pci *entry_priv;
1806         struct skb_frame_desc *skbdesc;
1807         struct txentry_desc txdesc;
1808         u32 reg;
1809
1810         if (unlikely(!intf->beacon))
1811                 return -ENOBUFS;
1812
1813         entry_priv = intf->beacon->priv_data;
1814
1815         /*
1816          * Copy all TX descriptor information into txdesc,
1817          * after that we are free to use the skb->cb array
1818          * for our information.
1819          */
1820         intf->beacon->skb = skb;
1821         rt2x00queue_create_tx_descriptor(intf->beacon, &txdesc);
1822
1823         /*
1824          * Fill in skb descriptor
1825          */
1826         skbdesc = get_skb_frame_desc(skb);
1827         memset(skbdesc, 0, sizeof(*skbdesc));
1828         skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
1829         skbdesc->data = skb->data;
1830         skbdesc->data_len = skb->len;
1831         skbdesc->desc = entry_priv->desc;
1832         skbdesc->desc_len = intf->beacon->queue->desc_size;
1833         skbdesc->entry = intf->beacon;
1834
1835         /*
1836          * Disable beaconing while we are reloading the beacon data,
1837          * otherwise we might be sending out invalid data.
1838          */
1839         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1840         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
1841         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
1842         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1843         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1844
1845         /*
1846          * Enable beacon generation.
1847          * Write entire beacon with descriptor to register,
1848          * and kick the beacon generator.
1849          */
1850         memcpy(entry_priv->data, skb->data, skb->len);
1851         rt2x00queue_write_tx_descriptor(intf->beacon, &txdesc);
1852         rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, QID_BEACON);
1853
1854         return 0;
1855 }
1856
1857 static int rt2500pci_tx_last_beacon(struct ieee80211_hw *hw)
1858 {
1859         struct rt2x00_dev *rt2x00dev = hw->priv;
1860         u32 reg;
1861
1862         rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1863         return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1864 }
1865
1866 static const struct ieee80211_ops rt2500pci_mac80211_ops = {
1867         .tx                     = rt2x00mac_tx,
1868         .start                  = rt2x00mac_start,
1869         .stop                   = rt2x00mac_stop,
1870         .add_interface          = rt2x00mac_add_interface,
1871         .remove_interface       = rt2x00mac_remove_interface,
1872         .config                 = rt2x00mac_config,
1873         .config_interface       = rt2x00mac_config_interface,
1874         .configure_filter       = rt2x00mac_configure_filter,
1875         .get_stats              = rt2x00mac_get_stats,
1876         .set_retry_limit        = rt2500pci_set_retry_limit,
1877         .bss_info_changed       = rt2x00mac_bss_info_changed,
1878         .conf_tx                = rt2x00mac_conf_tx,
1879         .get_tx_stats           = rt2x00mac_get_tx_stats,
1880         .get_tsf                = rt2500pci_get_tsf,
1881         .beacon_update          = rt2500pci_beacon_update,
1882         .tx_last_beacon         = rt2500pci_tx_last_beacon,
1883 };
1884
1885 static const struct rt2x00lib_ops rt2500pci_rt2x00_ops = {
1886         .irq_handler            = rt2500pci_interrupt,
1887         .probe_hw               = rt2500pci_probe_hw,
1888         .initialize             = rt2x00pci_initialize,
1889         .uninitialize           = rt2x00pci_uninitialize,
1890         .init_rxentry           = rt2500pci_init_rxentry,
1891         .init_txentry           = rt2500pci_init_txentry,
1892         .set_device_state       = rt2500pci_set_device_state,
1893         .rfkill_poll            = rt2500pci_rfkill_poll,
1894         .link_stats             = rt2500pci_link_stats,
1895         .reset_tuner            = rt2500pci_reset_tuner,
1896         .link_tuner             = rt2500pci_link_tuner,
1897         .write_tx_desc          = rt2500pci_write_tx_desc,
1898         .write_tx_data          = rt2x00pci_write_tx_data,
1899         .kick_tx_queue          = rt2500pci_kick_tx_queue,
1900         .fill_rxdone            = rt2500pci_fill_rxdone,
1901         .config_filter          = rt2500pci_config_filter,
1902         .config_intf            = rt2500pci_config_intf,
1903         .config_erp             = rt2500pci_config_erp,
1904         .config                 = rt2500pci_config,
1905 };
1906
1907 static const struct data_queue_desc rt2500pci_queue_rx = {
1908         .entry_num              = RX_ENTRIES,
1909         .data_size              = DATA_FRAME_SIZE,
1910         .desc_size              = RXD_DESC_SIZE,
1911         .priv_size              = sizeof(struct queue_entry_priv_pci),
1912 };
1913
1914 static const struct data_queue_desc rt2500pci_queue_tx = {
1915         .entry_num              = TX_ENTRIES,
1916         .data_size              = DATA_FRAME_SIZE,
1917         .desc_size              = TXD_DESC_SIZE,
1918         .priv_size              = sizeof(struct queue_entry_priv_pci),
1919 };
1920
1921 static const struct data_queue_desc rt2500pci_queue_bcn = {
1922         .entry_num              = BEACON_ENTRIES,
1923         .data_size              = MGMT_FRAME_SIZE,
1924         .desc_size              = TXD_DESC_SIZE,
1925         .priv_size              = sizeof(struct queue_entry_priv_pci),
1926 };
1927
1928 static const struct data_queue_desc rt2500pci_queue_atim = {
1929         .entry_num              = ATIM_ENTRIES,
1930         .data_size              = DATA_FRAME_SIZE,
1931         .desc_size              = TXD_DESC_SIZE,
1932         .priv_size              = sizeof(struct queue_entry_priv_pci),
1933 };
1934
1935 static const struct rt2x00_ops rt2500pci_ops = {
1936         .name           = KBUILD_MODNAME,
1937         .max_sta_intf   = 1,
1938         .max_ap_intf    = 1,
1939         .eeprom_size    = EEPROM_SIZE,
1940         .rf_size        = RF_SIZE,
1941         .tx_queues      = NUM_TX_QUEUES,
1942         .rx             = &rt2500pci_queue_rx,
1943         .tx             = &rt2500pci_queue_tx,
1944         .bcn            = &rt2500pci_queue_bcn,
1945         .atim           = &rt2500pci_queue_atim,
1946         .lib            = &rt2500pci_rt2x00_ops,
1947         .hw             = &rt2500pci_mac80211_ops,
1948 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1949         .debugfs        = &rt2500pci_rt2x00debug,
1950 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1951 };
1952
1953 /*
1954  * RT2500pci module information.
1955  */
1956 static struct pci_device_id rt2500pci_device_table[] = {
1957         { PCI_DEVICE(0x1814, 0x0201), PCI_DEVICE_DATA(&rt2500pci_ops) },
1958         { 0, }
1959 };
1960
1961 MODULE_AUTHOR(DRV_PROJECT);
1962 MODULE_VERSION(DRV_VERSION);
1963 MODULE_DESCRIPTION("Ralink RT2500 PCI & PCMCIA Wireless LAN driver.");
1964 MODULE_SUPPORTED_DEVICE("Ralink RT2560 PCI & PCMCIA chipset based cards");
1965 MODULE_DEVICE_TABLE(pci, rt2500pci_device_table);
1966 MODULE_LICENSE("GPL");
1967
1968 static struct pci_driver rt2500pci_driver = {
1969         .name           = KBUILD_MODNAME,
1970         .id_table       = rt2500pci_device_table,
1971         .probe          = rt2x00pci_probe,
1972         .remove         = __devexit_p(rt2x00pci_remove),
1973         .suspend        = rt2x00pci_suspend,
1974         .resume         = rt2x00pci_resume,
1975 };
1976
1977 static int __init rt2500pci_init(void)
1978 {
1979         return pci_register_driver(&rt2500pci_driver);
1980 }
1981
1982 static void __exit rt2500pci_exit(void)
1983 {
1984         pci_unregister_driver(&rt2500pci_driver);
1985 }
1986
1987 module_init(rt2500pci_init);
1988 module_exit(rt2500pci_exit);