SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/rt2x00/rt2400pci.c

   1 /*
   2         Copyright (C) 2004 - 2008 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt2400pci
  23         Abstract: rt2400pci device specific routines.
  24         Supported chipsets: RT2460.
  25  */
  26
  27 #include <linux/delay.h>
  28 #include <linux/etherdevice.h>
  29 #include <linux/init.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/pci.h>
  33 #include <linux/eeprom_93cx6.h>
  34
  35 #include "rt2x00.h"
  36 #include "rt2x00pci.h"
  37 #include "rt2400pci.h"
  38
  39 /*
  40  * Register access.
  41  * All access to the CSR registers will go through the methods
  42  * rt2x00pci_register_read and rt2x00pci_register_write.
  43  * BBP and RF register require indirect register access,
  44  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  45  * These indirect registers work with busy bits,
  46  * and we will try maximal REGISTER_BUSY_COUNT times to access
  47  * the register while taking a REGISTER_BUSY_DELAY us delay
  48  * between each attampt. When the busy bit is still set at that time,
  49  * the access attempt is considered to have failed,
  50  * and we will print an error.
  51  */
  52 static u32 rt2400pci_bbp_check(struct rt2x00_dev *rt2x00dev)
  53 {
  54         u32 reg;
  55         unsigned int i;
  56
  57         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  58                 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
  59                 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
  60                         break;
  61                 udelay(REGISTER_BUSY_DELAY);
  62         }
  63
  64         return reg;
  65 }
  66
  67 static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
  68                                 const unsigned int word, const u8 value)
  69 {
  70         u32 reg;
  71
  72         /*
  73          * Wait until the BBP becomes ready.
  74          */
  75         reg = rt2400pci_bbp_check(rt2x00dev);
  76         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
  77                 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
  78                 return;
  79         }
  80
  81         /*
  82          * Write the data into the BBP.
  83          */
  84         reg = 0;
  85         rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
  86         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  87         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
  88         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
  89
  90         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
  91 }
  92
  93 static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
  94                                const unsigned int word, u8 *value)
  95 {
  96         u32 reg;
  97
  98         /*
  99          * Wait until the BBP becomes ready.
 100          */
 101         reg = rt2400pci_bbp_check(rt2x00dev);
 102         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
 103                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
 104                 return;
 105         }
 106
 107         /*
 108          * Write the request into the BBP.
 109          */
 110         reg = 0;
 111         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
 112         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
 113         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
 114
 115         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
 116
 117         /*
 118          * Wait until the BBP becomes ready.
 119          */
 120         reg = rt2400pci_bbp_check(rt2x00dev);
 121         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
 122                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
 123                 *value = 0xff;
 124                 return;
 125         }
 126
 127         *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
 128 }
 129
 130 static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
 131                                const unsigned int word, const u32 value)
 132 {
 133         u32 reg;
 134         unsigned int i;
 135
 136         if (!word)
 137                 return;
 138
 139         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 140                 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
 141                 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
 142                         goto rf_write;
 143                 udelay(REGISTER_BUSY_DELAY);
 144         }
 145
 146         ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
 147         return;
 148
 149 rf_write:
 150         reg = 0;
 151         rt2x00_set_field32(&reg, RFCSR_VALUE, value);
 152         rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
 153         rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
 154         rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
 155
 156         rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
 157         rt2x00_rf_write(rt2x00dev, word, value);
 158 }
 159
 160 static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 161 {
 162         struct rt2x00_dev *rt2x00dev = eeprom->data;
 163         u32 reg;
 164
 165         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
 166
 167         eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
 168         eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
 169         eeprom->reg_data_clock =
 170             !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
 171         eeprom->reg_chip_select =
 172             !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
 173 }
 174
 175 static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 176 {
 177         struct rt2x00_dev *rt2x00dev = eeprom->data;
 178         u32 reg = 0;
 179
 180         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
 181         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
 182         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
 183                            !!eeprom->reg_data_clock);
 184         rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
 185                            !!eeprom->reg_chip_select);
 186
 187         rt2x00pci_register_write(rt2x00dev, CSR21, reg);
 188 }
 189
 190 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 191 #define CSR_OFFSET(__word)      ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
 192
 193 static void rt2400pci_read_csr(struct rt2x00_dev *rt2x00dev,
 194                                const unsigned int word, u32 *data)
 195 {
 196         rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
 197 }
 198
 199 static void rt2400pci_write_csr(struct rt2x00_dev *rt2x00dev,
 200                                 const unsigned int word, u32 data)
 201 {
 202         rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
 203 }
 204
 205 static const struct rt2x00debug rt2400pci_rt2x00debug = {
 206         .owner  = THIS_MODULE,
 207         .csr    = {
 208                 .read           = rt2400pci_read_csr,
 209                 .write          = rt2400pci_write_csr,
 210                 .word_size      = sizeof(u32),
 211                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 212         },
 213         .eeprom = {
 214                 .read           = rt2x00_eeprom_read,
 215                 .write          = rt2x00_eeprom_write,
 216                 .word_size      = sizeof(u16),
 217                 .word_count     = EEPROM_SIZE / sizeof(u16),
 218         },
 219         .bbp    = {
 220                 .read           = rt2400pci_bbp_read,
 221                 .write          = rt2400pci_bbp_write,
 222                 .word_size      = sizeof(u8),
 223                 .word_count     = BBP_SIZE / sizeof(u8),
 224         },
 225         .rf     = {
 226                 .read           = rt2x00_rf_read,
 227                 .write          = rt2400pci_rf_write,
 228                 .word_size      = sizeof(u32),
 229                 .word_count     = RF_SIZE / sizeof(u32),
 230         },
 231 };
 232 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 233
 234 #ifdef CONFIG_RT2400PCI_RFKILL
 235 static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 236 {
 237         u32 reg;
 238
 239         rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
 240         return rt2x00_get_field32(reg, GPIOCSR_BIT0);
 241 }
 242 #else
 243 #define rt2400pci_rfkill_poll   NULL
 244 #endif /* CONFIG_RT2400PCI_RFKILL */
 245
 246 #ifdef CONFIG_RT2400PCI_LEDS
 247 static void rt2400pci_brightness_set(struct led_classdev *led_cdev,
 248                                      enum led_brightness brightness)
 249 {
 250         struct rt2x00_led *led =
 251             container_of(led_cdev, struct rt2x00_led, led_dev);
 252         unsigned int enabled = brightness != LED_OFF;
 253         u32 reg;
 254
 255         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
 256
 257         if (led->type == LED_TYPE_RADIO || led->type == LED_TYPE_ASSOC)
 258                 rt2x00_set_field32(&reg, LEDCSR_LINK, enabled);
 259         else if (led->type == LED_TYPE_ACTIVITY)
 260                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, enabled);
 261
 262         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
 263 }
 264
 265 static int rt2400pci_blink_set(struct led_classdev *led_cdev,
 266                                unsigned long *delay_on,
 267                                unsigned long *delay_off)
 268 {
 269         struct rt2x00_led *led =
 270             container_of(led_cdev, struct rt2x00_led, led_dev);
 271         u32 reg;
 272
 273         rt2x00pci_register_read(led->rt2x00dev, LEDCSR, &reg);
 274         rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, *delay_on);
 275         rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, *delay_off);
 276         rt2x00pci_register_write(led->rt2x00dev, LEDCSR, reg);
 277
 278         return 0;
 279 }
 280 #endif /* CONFIG_RT2400PCI_LEDS */
 281
 282 /*
 283  * Configuration handlers.
 284  */
 285 static void rt2400pci_config_filter(struct rt2x00_dev *rt2x00dev,
 286                                     const unsigned int filter_flags)
 287 {
 288         u32 reg;
 289
 290         /*
 291          * Start configuration steps.
 292          * Note that the version error will always be dropped
 293          * since there is no filter for it at this time.
 294          */
 295         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
 296         rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
 297                            !(filter_flags & FIF_FCSFAIL));
 298         rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
 299                            !(filter_flags & FIF_PLCPFAIL));
 300         rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
 301                            !(filter_flags & FIF_CONTROL));
 302         rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
 303                            !(filter_flags & FIF_PROMISC_IN_BSS));
 304         rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
 305                            !(filter_flags & FIF_PROMISC_IN_BSS) &&
 306                            !rt2x00dev->intf_ap_count);
 307         rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
 308         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
 309 }
 310
 311 static void rt2400pci_config_intf(struct rt2x00_dev *rt2x00dev,
 312                                   struct rt2x00_intf *intf,
 313                                   struct rt2x00intf_conf *conf,
 314                                   const unsigned int flags)
 315 {
 316         unsigned int bcn_preload;
 317         u32 reg;
 318
 319         if (flags & CONFIG_UPDATE_TYPE) {
 320                 /*
 321                  * Enable beacon config
 322                  */
 323                 bcn_preload = PREAMBLE + get_duration(IEEE80211_HEADER, 20);
 324                 rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
 325                 rt2x00_set_field32(&reg, BCNCSR1_PRELOAD, bcn_preload);
 326                 rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
 327
 328                 /*
 329                  * Enable synchronisation.
 330                  */
 331                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
 332                 rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
 333                 rt2x00_set_field32(&reg, CSR14_TSF_SYNC, conf->sync);
 334                 rt2x00_set_field32(&reg, CSR14_TBCN, 1);
 335                 rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 336         }
 337
 338         if (flags & CONFIG_UPDATE_MAC)
 339                 rt2x00pci_register_multiwrite(rt2x00dev, CSR3,
 340                                               conf->mac, sizeof(conf->mac));
 341
 342         if (flags & CONFIG_UPDATE_BSSID)
 343                 rt2x00pci_register_multiwrite(rt2x00dev, CSR5,
 344                                               conf->bssid, sizeof(conf->bssid));
 345 }
 346
 347 static void rt2400pci_config_erp(struct rt2x00_dev *rt2x00dev,
 348                                  struct rt2x00lib_erp *erp)
 349 {
 350         int preamble_mask;
 351         u32 reg;
 352
 353         /*
 354          * When short preamble is enabled, we should set bit 0x08
 355          */
 356         preamble_mask = erp->short_preamble << 3;
 357
 358         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 359         rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT,
 360                            erp->ack_timeout);
 361         rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME,
 362                            erp->ack_consume_time);
 363         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 364
 365         rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
 366         rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00);
 367         rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
 368         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
 369         rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
 370
 371         rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
 372         rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
 373         rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
 374         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
 375         rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
 376
 377         rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
 378         rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
 379         rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
 380         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
 381         rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
 382
 383         rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
 384         rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
 385         rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
 386         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
 387         rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
 388 }
 389
 390 static void rt2400pci_config_phymode(struct rt2x00_dev *rt2x00dev,
 391                                      const int basic_rate_mask)
 392 {
 393         rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
 394 }
 395
 396 static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
 397                                      struct rf_channel *rf)
 398 {
 399         /*
 400          * Switch on tuning bits.
 401          */
 402         rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
 403         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
 404
 405         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 406         rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
 407         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 408
 409         /*
 410          * RF2420 chipset don't need any additional actions.
 411          */
 412         if (rt2x00_rf(&rt2x00dev->chip, RF2420))
 413                 return;
 414
 415         /*
 416          * For the RT2421 chipsets we need to write an invalid
 417          * reference clock rate to activate auto_tune.
 418          * After that we set the value back to the correct channel.
 419          */
 420         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 421         rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
 422         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 423
 424         msleep(1);
 425
 426         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 427         rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
 428         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 429
 430         msleep(1);
 431
 432         /*
 433          * Switch off tuning bits.
 434          */
 435         rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
 436         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
 437
 438         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 439         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 440
 441         /*
 442          * Clear false CRC during channel switch.
 443          */
 444         rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
 445 }
 446
 447 static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
 448 {
 449         rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
 450 }
 451
 452 static void rt2400pci_config_antenna(struct rt2x00_dev *rt2x00dev,
 453                                      struct antenna_setup *ant)
 454 {
 455         u8 r1;
 456         u8 r4;
 457
 458         /*
 459          * We should never come here because rt2x00lib is supposed
 460          * to catch this and send us the correct antenna explicitely.
 461          */
 462         BUG_ON(ant->rx == ANTENNA_SW_DIVERSITY ||
 463                ant->tx == ANTENNA_SW_DIVERSITY);
 464
 465         rt2400pci_bbp_read(rt2x00dev, 4, &r4);
 466         rt2400pci_bbp_read(rt2x00dev, 1, &r1);
 467
 468         /*
 469          * Configure the TX antenna.
 470          */
 471         switch (ant->tx) {
 472         case ANTENNA_HW_DIVERSITY:
 473                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
 474                 break;
 475         case ANTENNA_A:
 476                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
 477                 break;
 478         case ANTENNA_B:
 479         default:
 480                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
 481                 break;
 482         }
 483
 484         /*
 485          * Configure the RX antenna.
 486          */
 487         switch (ant->rx) {
 488         case ANTENNA_HW_DIVERSITY:
 489                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
 490                 break;
 491         case ANTENNA_A:
 492                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
 493                 break;
 494         case ANTENNA_B:
 495         default:
 496                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
 497                 break;
 498         }
 499
 500         rt2400pci_bbp_write(rt2x00dev, 4, r4);
 501         rt2400pci_bbp_write(rt2x00dev, 1, r1);
 502 }
 503
 504 static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev,
 505                                       struct rt2x00lib_conf *libconf)
 506 {
 507         u32 reg;
 508
 509         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 510         rt2x00_set_field32(&reg, CSR11_SLOT_TIME, libconf->slot_time);
 511         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 512
 513         rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
 514         rt2x00_set_field32(&reg, CSR18_SIFS, libconf->sifs);
 515         rt2x00_set_field32(&reg, CSR18_PIFS, libconf->pifs);
 516         rt2x00pci_register_write(rt2x00dev, CSR18, reg);
 517
 518         rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
 519         rt2x00_set_field32(&reg, CSR19_DIFS, libconf->difs);
 520         rt2x00_set_field32(&reg, CSR19_EIFS, libconf->eifs);
 521         rt2x00pci_register_write(rt2x00dev, CSR19, reg);
 522
 523         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 524         rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
 525         rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
 526         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 527
 528         rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
 529         rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
 530                            libconf->conf->beacon_int * 16);
 531         rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
 532                            libconf->conf->beacon_int * 16);
 533         rt2x00pci_register_write(rt2x00dev, CSR12, reg);
 534 }
 535
 536 static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
 537                              struct rt2x00lib_conf *libconf,
 538                              const unsigned int flags)
 539 {
 540         if (flags & CONFIG_UPDATE_PHYMODE)
 541                 rt2400pci_config_phymode(rt2x00dev, libconf->basic_rates);
 542         if (flags & CONFIG_UPDATE_CHANNEL)
 543                 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
 544         if (flags & CONFIG_UPDATE_TXPOWER)
 545                 rt2400pci_config_txpower(rt2x00dev,
 546                                          libconf->conf->power_level);
 547         if (flags & CONFIG_UPDATE_ANTENNA)
 548                 rt2400pci_config_antenna(rt2x00dev, &libconf->ant);
 549         if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
 550                 rt2400pci_config_duration(rt2x00dev, libconf);
 551 }
 552
 553 static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
 554                                 const int cw_min, const int cw_max)
 555 {
 556         u32 reg;
 557
 558         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 559         rt2x00_set_field32(&reg, CSR11_CWMIN, cw_min);
 560         rt2x00_set_field32(&reg, CSR11_CWMAX, cw_max);
 561         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 562 }
 563
 564 /*
 565  * Link tuning
 566  */
 567 static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
 568                                  struct link_qual *qual)
 569 {
 570         u32 reg;
 571         u8 bbp;
 572
 573         /*
 574          * Update FCS error count from register.
 575          */
 576         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 577         qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
 578
 579         /*
 580          * Update False CCA count from register.
 581          */
 582         rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
 583         qual->false_cca = bbp;
 584 }
 585
 586 static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
 587 {
 588         rt2400pci_bbp_write(rt2x00dev, 13, 0x08);
 589         rt2x00dev->link.vgc_level = 0x08;
 590 }
 591
 592 static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev)
 593 {
 594         u8 reg;
 595
 596         /*
 597          * The link tuner should not run longer then 60 seconds,
 598          * and should run once every 2 seconds.
 599          */
 600         if (rt2x00dev->link.count > 60 || !(rt2x00dev->link.count & 1))
 601                 return;
 602
 603         /*
 604          * Base r13 link tuning on the false cca count.
 605          */
 606         rt2400pci_bbp_read(rt2x00dev, 13, &reg);
 607
 608         if (rt2x00dev->link.qual.false_cca > 512 && reg < 0x20) {
 609                 rt2400pci_bbp_write(rt2x00dev, 13, ++reg);
 610                 rt2x00dev->link.vgc_level = reg;
 611         } else if (rt2x00dev->link.qual.false_cca < 100 && reg > 0x08) {
 612                 rt2400pci_bbp_write(rt2x00dev, 13, --reg);
 613                 rt2x00dev->link.vgc_level = reg;
 614         }
 615 }
 616
 617 /*
 618  * Initialization functions.
 619  */
 620 static void rt2400pci_init_rxentry(struct rt2x00_dev *rt2x00dev,
 621                                    struct queue_entry *entry)
 622 {
 623         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 624         u32 word;
 625
 626         rt2x00_desc_read(entry_priv->desc, 2, &word);
 627         rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH,
 628                            entry->queue->data_size);
 629         rt2x00_desc_write(entry_priv->desc, 2, word);
 630
 631         rt2x00_desc_read(entry_priv->desc, 1, &word);
 632         rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS, entry_priv->data_dma);
 633         rt2x00_desc_write(entry_priv->desc, 1, word);
 634
 635         rt2x00_desc_read(entry_priv->desc, 0, &word);
 636         rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
 637         rt2x00_desc_write(entry_priv->desc, 0, word);
 638 }
 639
 640 static void rt2400pci_init_txentry(struct rt2x00_dev *rt2x00dev,
 641                                    struct queue_entry *entry)
 642 {
 643         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
 644         u32 word;
 645
 646         rt2x00_desc_read(entry_priv->desc, 0, &word);
 647         rt2x00_set_field32(&word, TXD_W0_VALID, 0);
 648         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
 649         rt2x00_desc_write(entry_priv->desc, 0, word);
 650 }
 651
 652 static int rt2400pci_init_queues(struct rt2x00_dev *rt2x00dev)
 653 {
 654         struct queue_entry_priv_pci *entry_priv;
 655         u32 reg;
 656
 657         /*
 658          * Initialize registers.
 659          */
 660         rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
 661         rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size);
 662         rt2x00_set_field32(&reg, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit);
 663         rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM, rt2x00dev->bcn[1].limit);
 664         rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit);
 665         rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
 666
 667         entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
 668         rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
 669         rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
 670                            entry_priv->desc_dma);
 671         rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
 672
 673         entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
 674         rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
 675         rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
 676                            entry_priv->desc_dma);
 677         rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
 678
 679         entry_priv = rt2x00dev->bcn[1].entries[0].priv_data;
 680         rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
 681         rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
 682                            entry_priv->desc_dma);
 683         rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
 684
 685         entry_priv = rt2x00dev->bcn[0].entries[0].priv_data;
 686         rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
 687         rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
 688                            entry_priv->desc_dma);
 689         rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
 690
 691         rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
 692         rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
 693         rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->limit);
 694         rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
 695
 696         entry_priv = rt2x00dev->rx->entries[0].priv_data;
 697         rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
 698         rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
 699                            entry_priv->desc_dma);
 700         rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
 701
 702         return 0;
 703 }
 704
 705 static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
 706 {
 707         u32 reg;
 708
 709         rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
 710         rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
 711         rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
 712         rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
 713
 714         rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
 715         rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
 716         rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
 717         rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
 718         rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
 719
 720         rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
 721         rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
 722                            (rt2x00dev->rx->data_size / 128));
 723         rt2x00pci_register_write(rt2x00dev, CSR9, reg);
 724
 725         rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
 726
 727         rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
 728         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
 729         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
 730         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
 731         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
 732         rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
 733
 734         rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
 735         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
 736         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
 737         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
 738         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
 739         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
 740         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
 741         rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
 742
 743         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
 744
 745         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
 746                 return -EBUSY;
 747
 748         rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
 749         rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
 750
 751         rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
 752         rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
 753         rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
 754
 755         rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
 756         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
 757         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
 758         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
 759         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
 760         rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
 761
 762         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 763         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
 764         rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
 765         rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
 766         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 767
 768         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 769         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
 770         rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
 771         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 772
 773         /*
 774          * We must clear the FCS and FIFO error count.
 775          * These registers are cleared on read,
 776          * so we may pass a useless variable to store the value.
 777          */
 778         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 779         rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
 780
 781         return 0;
 782 }
 783
 784 static int rt2400pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
 785 {
 786         unsigned int i;
 787         u8 value;
 788
 789         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 790                 rt2400pci_bbp_read(rt2x00dev, 0, &value);
 791                 if ((value != 0xff) && (value != 0x00))
 792                         return 0;
 793                 udelay(REGISTER_BUSY_DELAY);
 794         }
 795
 796         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
 797         return -EACCES;
 798 }
 799
 800 static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
 801 {
 802         unsigned int i;
 803         u16 eeprom;
 804         u8 reg_id;
 805         u8 value;
 806
 807         if (unlikely(rt2400pci_wait_bbp_ready(rt2x00dev)))
 808                 return -EACCES;
 809
 810         rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
 811         rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
 812         rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
 813         rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
 814         rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
 815         rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
 816         rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
 817         rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
 818         rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
 819         rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
 820         rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
 821         rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
 822         rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
 823         rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
 824
 825         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
 826                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
 827
 828                 if (eeprom != 0xffff && eeprom != 0x0000) {
 829                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
 830                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
 831                         rt2400pci_bbp_write(rt2x00dev, reg_id, value);
 832                 }
 833         }
 834
 835         return 0;
 836 }
 837
 838 /*
 839  * Device state switch handlers.
 840  */
 841 static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
 842                                 enum dev_state state)
 843 {
 844         u32 reg;
 845
 846         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
 847         rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
 848                            (state == STATE_RADIO_RX_OFF) ||
 849                            (state == STATE_RADIO_RX_OFF_LINK));
 850         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
 851 }
 852
 853 static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
 854                                  enum dev_state state)
 855 {
 856         int mask = (state == STATE_RADIO_IRQ_OFF);
 857         u32 reg;
 858
 859         /*
 860          * When interrupts are being enabled, the interrupt registers
 861          * should clear the register to assure a clean state.
 862          */
 863         if (state == STATE_RADIO_IRQ_ON) {
 864                 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
 865                 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
 866         }
 867
 868         /*
 869          * Only toggle the interrupts bits we are going to use.
 870          * Non-checked interrupt bits are disabled by default.
 871          */
 872         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
 873         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
 874         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
 875         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
 876         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
 877         rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
 878         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
 879 }
 880
 881 static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
 882 {
 883         /*
 884          * Initialize all registers.
 885          */
 886         if (unlikely(rt2400pci_init_queues(rt2x00dev) ||
 887                      rt2400pci_init_registers(rt2x00dev) ||
 888                      rt2400pci_init_bbp(rt2x00dev)))
 889                 return -EIO;
 890
 891         return 0;
 892 }
 893
 894 static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
 895 {
 896         u32 reg;
 897
 898         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
 899
 900         /*
 901          * Disable synchronisation.
 902          */
 903         rt2x00pci_register_write(rt2x00dev, CSR14, 0);
 904
 905         /*
 906          * Cancel RX and TX.
 907          */
 908         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
 909         rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
 910         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
 911 }
 912
 913 static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
 914                                enum dev_state state)
 915 {
 916         u32 reg;
 917         unsigned int i;
 918         char put_to_sleep;
 919         char bbp_state;
 920         char rf_state;
 921
 922         put_to_sleep = (state != STATE_AWAKE);
 923
 924         rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
 925         rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
 926         rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
 927         rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
 928         rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
 929         rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
 930
 931         /*
 932          * Device is not guaranteed to be in the requested state yet.
 933          * We must wait until the register indicates that the
 934          * device has entered the correct state.
 935          */
 936         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 937                 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
 938                 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
 939                 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
 940                 if (bbp_state == state && rf_state == state)
 941                         return 0;
 942                 msleep(10);
 943         }
 944
 945         return -EBUSY;
 946 }
 947
 948 static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
 949                                       enum dev_state state)
 950 {
 951         int retval = 0;
 952
 953         switch (state) {
 954         case STATE_RADIO_ON:
 955                 retval = rt2400pci_enable_radio(rt2x00dev);
 956                 break;
 957         case STATE_RADIO_OFF:
 958                 rt2400pci_disable_radio(rt2x00dev);
 959                 break;
 960         case STATE_RADIO_RX_ON:
 961         case STATE_RADIO_RX_ON_LINK:
 962         case STATE_RADIO_RX_OFF:
 963         case STATE_RADIO_RX_OFF_LINK:
 964                 rt2400pci_toggle_rx(rt2x00dev, state);
 965                 break;
 966         case STATE_RADIO_IRQ_ON:
 967         case STATE_RADIO_IRQ_OFF:
 968                 rt2400pci_toggle_irq(rt2x00dev, state);
 969                 break;
 970         case STATE_DEEP_SLEEP:
 971         case STATE_SLEEP:
 972         case STATE_STANDBY:
 973         case STATE_AWAKE:
 974                 retval = rt2400pci_set_state(rt2x00dev, state);
 975                 break;
 976         default:
 977                 retval = -ENOTSUPP;
 978                 break;
 979         }
 980
 981         if (unlikely(retval))
 982                 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
 983                       state, retval);
 984
 985         return retval;
 986 }
 987
 988 /*
 989  * TX descriptor initialization
 990  */
 991 static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
 992                                     struct sk_buff *skb,
 993                                     struct txentry_desc *txdesc)
 994 {
 995         struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
 996         struct queue_entry_priv_pci *entry_priv = skbdesc->entry->priv_data;
 997         __le32 *txd = skbdesc->desc;
 998         u32 word;
 999
1000         /*
1001          * Start writing the descriptor words.
1002          */
1003         rt2x00_desc_read(entry_priv->desc, 1, &word);
1004         rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS, entry_priv->data_dma);
1005         rt2x00_desc_write(entry_priv->desc, 1, word);
1006
1007         rt2x00_desc_read(txd, 2, &word);
1008         rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH, skbdesc->data_len);
1009         rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, skbdesc->data_len);
1010         rt2x00_desc_write(txd, 2, word);
1011
1012         rt2x00_desc_read(txd, 3, &word);
1013         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, txdesc->signal);
1014         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_REGNUM, 5);
1015         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL_BUSY, 1);
1016         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, txdesc->service);
1017         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_REGNUM, 6);
1018         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE_BUSY, 1);
1019         rt2x00_desc_write(txd, 3, word);
1020
1021         rt2x00_desc_read(txd, 4, &word);
1022         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, txdesc->length_low);
1023         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_REGNUM, 8);
1024         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_LOW_BUSY, 1);
1025         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, txdesc->length_high);
1026         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_REGNUM, 7);
1027         rt2x00_set_field32(&word, TXD_W3_PLCP_LENGTH_HIGH_BUSY, 1);
1028         rt2x00_desc_write(txd, 4, word);
1029
1030         rt2x00_desc_read(txd, 0, &word);
1031         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1032         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1033         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1034                            test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
1035         rt2x00_set_field32(&word, TXD_W0_ACK,
1036                            test_bit(ENTRY_TXD_ACK, &txdesc->flags));
1037         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1038                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
1039         rt2x00_set_field32(&word, TXD_W0_RTS,
1040                            test_bit(ENTRY_TXD_RTS_FRAME, &txdesc->flags));
1041         rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
1042         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1043                            test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
1044         rt2x00_desc_write(txd, 0, word);
1045 }
1046
1047 /*
1048  * TX data initialization
1049  */
1050 static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1051                                     const enum data_queue_qid queue)
1052 {
1053         u32 reg;
1054
1055         if (queue == QID_BEACON) {
1056                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1057                 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1058                         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
1059                         rt2x00_set_field32(&reg, CSR14_TBCN, 1);
1060                         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1061                         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1062                 }
1063                 return;
1064         }
1065
1066         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1067         rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, (queue == QID_AC_BE));
1068         rt2x00_set_field32(&reg, TXCSR0_KICK_TX, (queue == QID_AC_BK));
1069         rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, (queue == QID_ATIM));
1070         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1071 }
1072
1073 /*
1074  * RX control handlers
1075  */
1076 static void rt2400pci_fill_rxdone(struct queue_entry *entry,
1077                                   struct rxdone_entry_desc *rxdesc)
1078 {
1079         struct queue_entry_priv_pci *entry_priv = entry->priv_data;
1080         u32 word0;
1081         u32 word2;
1082         u32 word3;
1083
1084         rt2x00_desc_read(entry_priv->desc, 0, &word0);
1085         rt2x00_desc_read(entry_priv->desc, 2, &word2);
1086         rt2x00_desc_read(entry_priv->desc, 3, &word3);
1087
1088         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1089                 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
1090         if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1091                 rxdesc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1092
1093         /*
1094          * Obtain the status about this packet.
1095          * The signal is the PLCP value, and needs to be stripped
1096          * of the preamble bit (0x08).
1097          */
1098         rxdesc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL) & ~0x08;
1099         rxdesc->rssi = rt2x00_get_field32(word2, RXD_W3_RSSI) -
1100             entry->queue->rt2x00dev->rssi_offset;
1101         rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1102
1103         rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
1104         if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
1105                 rxdesc->dev_flags |= RXDONE_MY_BSS;
1106 }
1107
1108 /*
1109  * Interrupt functions.
1110  */
1111 static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev,
1112                              const enum data_queue_qid queue_idx)
1113 {
1114         struct data_queue *queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
1115         struct queue_entry_priv_pci *entry_priv;
1116         struct queue_entry *entry;
1117         struct txdone_entry_desc txdesc;
1118         u32 word;
1119
1120         while (!rt2x00queue_empty(queue)) {
1121                 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
1122                 entry_priv = entry->priv_data;
1123                 rt2x00_desc_read(entry_priv->desc, 0, &word);
1124
1125                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1126                     !rt2x00_get_field32(word, TXD_W0_VALID))
1127                         break;
1128
1129                 /*
1130                  * Obtain the status about this packet.
1131                  */
1132                 txdesc.flags = 0;
1133                 switch (rt2x00_get_field32(word, TXD_W0_RESULT)) {
1134                 case 0: /* Success */
1135                 case 1: /* Success with retry */
1136                         __set_bit(TXDONE_SUCCESS, &txdesc.flags);
1137                         break;
1138                 case 2: /* Failure, excessive retries */
1139                         __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
1140                         /* Don't break, this is a failed frame! */
1141                 default: /* Failure */
1142                         __set_bit(TXDONE_FAILURE, &txdesc.flags);
1143                 }
1144                 txdesc.retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1145
1146                 rt2x00pci_txdone(rt2x00dev, entry, &txdesc);
1147         }
1148 }
1149
1150 static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1151 {
1152         struct rt2x00_dev *rt2x00dev = dev_instance;
1153         u32 reg;
1154
1155         /*
1156          * Get the interrupt sources & saved to local variable.
1157          * Write register value back to clear pending interrupts.
1158          */
1159         rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1160         rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1161
1162         if (!reg)
1163                 return IRQ_NONE;
1164
1165         if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1166                 return IRQ_HANDLED;
1167
1168         /*
1169          * Handle interrupts, walk through all bits
1170          * and run the tasks, the bits are checked in order of
1171          * priority.
1172          */
1173
1174         /*
1175          * 1 - Beacon timer expired interrupt.
1176          */
1177         if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1178                 rt2x00lib_beacondone(rt2x00dev);
1179
1180         /*
1181          * 2 - Rx ring done interrupt.
1182          */
1183         if (rt2x00_get_field32(reg, CSR7_RXDONE))
1184                 rt2x00pci_rxdone(rt2x00dev);
1185
1186         /*
1187          * 3 - Atim ring transmit done interrupt.
1188          */
1189         if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1190                 rt2400pci_txdone(rt2x00dev, QID_ATIM);
1191
1192         /*
1193          * 4 - Priority ring transmit done interrupt.
1194          */
1195         if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1196                 rt2400pci_txdone(rt2x00dev, QID_AC_BE);
1197
1198         /*
1199          * 5 - Tx ring transmit done interrupt.
1200          */
1201         if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1202                 rt2400pci_txdone(rt2x00dev, QID_AC_BK);
1203
1204         return IRQ_HANDLED;
1205 }
1206
1207 /*
1208  * Device probe functions.
1209  */
1210 static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1211 {
1212         struct eeprom_93cx6 eeprom;
1213         u32 reg;
1214         u16 word;
1215         u8 *mac;
1216
1217         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1218
1219         eeprom.data = rt2x00dev;
1220         eeprom.register_read = rt2400pci_eepromregister_read;
1221         eeprom.register_write = rt2400pci_eepromregister_write;
1222         eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1223             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1224         eeprom.reg_data_in = 0;
1225         eeprom.reg_data_out = 0;
1226         eeprom.reg_data_clock = 0;
1227         eeprom.reg_chip_select = 0;
1228
1229         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1230                                EEPROM_SIZE / sizeof(u16));
1231
1232         /*
1233          * Start validation of the data that has been read.
1234          */
1235         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1236         if (!is_valid_ether_addr(mac)) {
1237                 DECLARE_MAC_BUF(macbuf);
1238
1239                 random_ether_addr(mac);
1240                 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
1241         }
1242
1243         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1244         if (word == 0xffff) {
1245                 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1246                 return -EINVAL;
1247         }
1248
1249         return 0;
1250 }
1251
1252 static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1253 {
1254         u32 reg;
1255         u16 value;
1256         u16 eeprom;
1257
1258         /*
1259          * Read EEPROM word for configuration.
1260          */
1261         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1262
1263         /*
1264          * Identify RF chipset.
1265          */
1266         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1267         rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1268         rt2x00_set_chip(rt2x00dev, RT2460, value, reg);
1269
1270         if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
1271             !rt2x00_rf(&rt2x00dev->chip, RF2421)) {
1272                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1273                 return -ENODEV;
1274         }
1275
1276         /*
1277          * Identify default antenna configuration.
1278          */
1279         rt2x00dev->default_ant.tx =
1280             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1281         rt2x00dev->default_ant.rx =
1282             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1283
1284         /*
1285          * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1286          * I am not 100% sure about this, but the legacy drivers do not
1287          * indicate antenna swapping in software is required when
1288          * diversity is enabled.
1289          */
1290         if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1291                 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1292         if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1293                 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1294
1295         /*
1296          * Store led mode, for correct led behaviour.
1297          */
1298 #ifdef CONFIG_RT2400PCI_LEDS
1299         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1300
1301         rt2x00dev->led_radio.rt2x00dev = rt2x00dev;
1302         rt2x00dev->led_radio.type = LED_TYPE_RADIO;
1303         rt2x00dev->led_radio.led_dev.brightness_set =
1304             rt2400pci_brightness_set;
1305         rt2x00dev->led_radio.led_dev.blink_set =
1306             rt2400pci_blink_set;
1307         rt2x00dev->led_radio.flags = LED_INITIALIZED;
1308
1309         if (value == LED_MODE_TXRX_ACTIVITY) {
1310                 rt2x00dev->led_qual.rt2x00dev = rt2x00dev;
1311                 rt2x00dev->led_qual.type = LED_TYPE_ACTIVITY;
1312                 rt2x00dev->led_qual.led_dev.brightness_set =
1313                     rt2400pci_brightness_set;
1314                 rt2x00dev->led_qual.led_dev.blink_set =
1315                     rt2400pci_blink_set;
1316                 rt2x00dev->led_qual.flags = LED_INITIALIZED;
1317         }
1318 #endif /* CONFIG_RT2400PCI_LEDS */
1319
1320         /*
1321          * Detect if this device has an hardware controlled radio.
1322          */
1323 #ifdef CONFIG_RT2400PCI_RFKILL
1324         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1325                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1326 #endif /* CONFIG_RT2400PCI_RFKILL */
1327
1328         /*
1329          * Check if the BBP tuning should be enabled.
1330          */
1331         if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1332                 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1333
1334         return 0;
1335 }
1336
1337 /*
1338  * RF value list for RF2420 & RF2421
1339  * Supports: 2.4 GHz
1340  */
1341 static const struct rf_channel rf_vals_bg[] = {
1342         { 1,  0x00022058, 0x000c1fda, 0x00000101, 0 },
1343         { 2,  0x00022058, 0x000c1fee, 0x00000101, 0 },
1344         { 3,  0x00022058, 0x000c2002, 0x00000101, 0 },
1345         { 4,  0x00022058, 0x000c2016, 0x00000101, 0 },
1346         { 5,  0x00022058, 0x000c202a, 0x00000101, 0 },
1347         { 6,  0x00022058, 0x000c203e, 0x00000101, 0 },
1348         { 7,  0x00022058, 0x000c2052, 0x00000101, 0 },
1349         { 8,  0x00022058, 0x000c2066, 0x00000101, 0 },
1350         { 9,  0x00022058, 0x000c207a, 0x00000101, 0 },
1351         { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1352         { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1353         { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1354         { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1355         { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1356 };
1357
1358 static void rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1359 {
1360         struct hw_mode_spec *spec = &rt2x00dev->spec;
1361         u8 *txpower;
1362         unsigned int i;
1363
1364         /*
1365          * Initialize all hw fields.
1366          */
1367         rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1368                                IEEE80211_HW_SIGNAL_DBM;
1369         rt2x00dev->hw->extra_tx_headroom = 0;
1370
1371         SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1372         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1373                                 rt2x00_eeprom_addr(rt2x00dev,
1374                                                    EEPROM_MAC_ADDR_0));
1375
1376         /*
1377          * Convert tx_power array in eeprom.
1378          */
1379         txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1380         for (i = 0; i < 14; i++)
1381                 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1382
1383         /*
1384          * Initialize hw_mode information.
1385          */
1386         spec->supported_bands = SUPPORT_BAND_2GHZ;
1387         spec->supported_rates = SUPPORT_RATE_CCK;
1388         spec->tx_power_a = NULL;
1389         spec->tx_power_bg = txpower;
1390         spec->tx_power_default = DEFAULT_TXPOWER;
1391
1392         spec->num_channels = ARRAY_SIZE(rf_vals_bg);
1393         spec->channels = rf_vals_bg;
1394 }
1395
1396 static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1397 {
1398         int retval;
1399
1400         /*
1401          * Allocate eeprom data.
1402          */
1403         retval = rt2400pci_validate_eeprom(rt2x00dev);
1404         if (retval)
1405                 return retval;
1406
1407         retval = rt2400pci_init_eeprom(rt2x00dev);
1408         if (retval)
1409                 return retval;
1410
1411         /*
1412          * Initialize hw specifications.
1413          */
1414         rt2400pci_probe_hw_mode(rt2x00dev);
1415
1416         /*
1417          * This device requires the atim queue
1418          */
1419         __set_bit(DRIVER_REQUIRE_ATIM_QUEUE, &rt2x00dev->flags);
1420
1421         /*
1422          * Set the rssi offset.
1423          */
1424         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1425
1426         return 0;
1427 }
1428
1429 /*
1430  * IEEE80211 stack callback functions.
1431  */
1432 static int rt2400pci_set_retry_limit(struct ieee80211_hw *hw,
1433                                      u32 short_retry, u32 long_retry)
1434 {
1435         struct rt2x00_dev *rt2x00dev = hw->priv;
1436         u32 reg;
1437
1438         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1439         rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1440         rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1441         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1442
1443         return 0;
1444 }
1445
1446 static int rt2400pci_conf_tx(struct ieee80211_hw *hw, u16 queue,
1447                              const struct ieee80211_tx_queue_params *params)
1448 {
1449         struct rt2x00_dev *rt2x00dev = hw->priv;
1450
1451         /*
1452          * We don't support variating cw_min and cw_max variables
1453          * per queue. So by default we only configure the TX queue,
1454          * and ignore all other configurations.
1455          */
1456         if (queue != 0)
1457                 return -EINVAL;
1458
1459         if (rt2x00mac_conf_tx(hw, queue, params))
1460                 return -EINVAL;
1461
1462         /*
1463          * Write configuration to register.
1464          */
1465         rt2400pci_config_cw(rt2x00dev,
1466                             rt2x00dev->tx->cw_min, rt2x00dev->tx->cw_max);
1467
1468         return 0;
1469 }
1470
1471 static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1472 {
1473         struct rt2x00_dev *rt2x00dev = hw->priv;
1474         u64 tsf;
1475         u32 reg;
1476
1477         rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1478         tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1479         rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1480         tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1481
1482         return tsf;
1483 }
1484
1485 static int rt2400pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
1486 {
1487         struct rt2x00_dev *rt2x00dev = hw->priv;
1488         struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1489         struct rt2x00_intf *intf = vif_to_intf(tx_info->control.vif);
1490         struct queue_entry_priv_pci *entry_priv;
1491         struct skb_frame_desc *skbdesc;
1492         struct txentry_desc txdesc;
1493         u32 reg;
1494
1495         if (unlikely(!intf->beacon))
1496                 return -ENOBUFS;
1497         entry_priv = intf->beacon->priv_data;
1498
1499         /*
1500          * Copy all TX descriptor information into txdesc,
1501          * after that we are free to use the skb->cb array
1502          * for our information.
1503          */
1504         intf->beacon->skb = skb;
1505         rt2x00queue_create_tx_descriptor(intf->beacon, &txdesc);
1506
1507         /*
1508          * Fill in skb descriptor
1509          */
1510         skbdesc = get_skb_frame_desc(skb);
1511         memset(skbdesc, 0, sizeof(*skbdesc));
1512         skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
1513         skbdesc->data = skb->data;
1514         skbdesc->data_len = skb->len;
1515         skbdesc->desc = entry_priv->desc;
1516         skbdesc->desc_len = intf->beacon->queue->desc_size;
1517         skbdesc->entry = intf->beacon;
1518
1519         /*
1520          * Disable beaconing while we are reloading the beacon data,
1521          * otherwise we might be sending out invalid data.
1522          */
1523         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1524         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 0);
1525         rt2x00_set_field32(&reg, CSR14_TBCN, 0);
1526         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
1527         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1528
1529         /*
1530          * Enable beacon generation.
1531          * Write entire beacon with descriptor to register,
1532          * and kick the beacon generator.
1533          */
1534         memcpy(entry_priv->data, skb->data, skb->len);
1535         rt2x00queue_write_tx_descriptor(intf->beacon, &txdesc);
1536         rt2x00dev->ops->lib->kick_tx_queue(rt2x00dev, QID_BEACON);
1537
1538         return 0;
1539 }
1540
1541 static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1542 {
1543         struct rt2x00_dev *rt2x00dev = hw->priv;
1544         u32 reg;
1545
1546         rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1547         return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1548 }
1549
1550 static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1551         .tx                     = rt2x00mac_tx,
1552         .start                  = rt2x00mac_start,
1553         .stop                   = rt2x00mac_stop,
1554         .add_interface          = rt2x00mac_add_interface,
1555         .remove_interface       = rt2x00mac_remove_interface,
1556         .config                 = rt2x00mac_config,
1557         .config_interface       = rt2x00mac_config_interface,
1558         .configure_filter       = rt2x00mac_configure_filter,
1559         .get_stats              = rt2x00mac_get_stats,
1560         .set_retry_limit        = rt2400pci_set_retry_limit,
1561         .bss_info_changed       = rt2x00mac_bss_info_changed,
1562         .conf_tx                = rt2400pci_conf_tx,
1563         .get_tx_stats           = rt2x00mac_get_tx_stats,
1564         .get_tsf                = rt2400pci_get_tsf,
1565         .beacon_update          = rt2400pci_beacon_update,
1566         .tx_last_beacon         = rt2400pci_tx_last_beacon,
1567 };
1568
1569 static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1570         .irq_handler            = rt2400pci_interrupt,
1571         .probe_hw               = rt2400pci_probe_hw,
1572         .initialize             = rt2x00pci_initialize,
1573         .uninitialize           = rt2x00pci_uninitialize,
1574         .init_rxentry           = rt2400pci_init_rxentry,
1575         .init_txentry           = rt2400pci_init_txentry,
1576         .set_device_state       = rt2400pci_set_device_state,
1577         .rfkill_poll            = rt2400pci_rfkill_poll,
1578         .link_stats             = rt2400pci_link_stats,
1579         .reset_tuner            = rt2400pci_reset_tuner,
1580         .link_tuner             = rt2400pci_link_tuner,
1581         .write_tx_desc          = rt2400pci_write_tx_desc,
1582         .write_tx_data          = rt2x00pci_write_tx_data,
1583         .kick_tx_queue          = rt2400pci_kick_tx_queue,
1584         .fill_rxdone            = rt2400pci_fill_rxdone,
1585         .config_filter          = rt2400pci_config_filter,
1586         .config_intf            = rt2400pci_config_intf,
1587         .config_erp             = rt2400pci_config_erp,
1588         .config                 = rt2400pci_config,
1589 };
1590
1591 static const struct data_queue_desc rt2400pci_queue_rx = {
1592         .entry_num              = RX_ENTRIES,
1593         .data_size              = DATA_FRAME_SIZE,
1594         .desc_size              = RXD_DESC_SIZE,
1595         .priv_size              = sizeof(struct queue_entry_priv_pci),
1596 };
1597
1598 static const struct data_queue_desc rt2400pci_queue_tx = {
1599         .entry_num              = TX_ENTRIES,
1600         .data_size              = DATA_FRAME_SIZE,
1601         .desc_size              = TXD_DESC_SIZE,
1602         .priv_size              = sizeof(struct queue_entry_priv_pci),
1603 };
1604
1605 static const struct data_queue_desc rt2400pci_queue_bcn = {
1606         .entry_num              = BEACON_ENTRIES,
1607         .data_size              = MGMT_FRAME_SIZE,
1608         .desc_size              = TXD_DESC_SIZE,
1609         .priv_size              = sizeof(struct queue_entry_priv_pci),
1610 };
1611
1612 static const struct data_queue_desc rt2400pci_queue_atim = {
1613         .entry_num              = ATIM_ENTRIES,
1614         .data_size              = DATA_FRAME_SIZE,
1615         .desc_size              = TXD_DESC_SIZE,
1616         .priv_size              = sizeof(struct queue_entry_priv_pci),
1617 };
1618
1619 static const struct rt2x00_ops rt2400pci_ops = {
1620         .name           = KBUILD_MODNAME,
1621         .max_sta_intf   = 1,
1622         .max_ap_intf    = 1,
1623         .eeprom_size    = EEPROM_SIZE,
1624         .rf_size        = RF_SIZE,
1625         .tx_queues      = NUM_TX_QUEUES,
1626         .rx             = &rt2400pci_queue_rx,
1627         .tx             = &rt2400pci_queue_tx,
1628         .bcn            = &rt2400pci_queue_bcn,
1629         .atim           = &rt2400pci_queue_atim,
1630         .lib            = &rt2400pci_rt2x00_ops,
1631         .hw             = &rt2400pci_mac80211_ops,
1632 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1633         .debugfs        = &rt2400pci_rt2x00debug,
1634 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1635 };
1636
1637 /*
1638  * RT2400pci module information.
1639  */
1640 static struct pci_device_id rt2400pci_device_table[] = {
1641         { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1642         { 0, }
1643 };
1644
1645 MODULE_AUTHOR(DRV_PROJECT);
1646 MODULE_VERSION(DRV_VERSION);
1647 MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1648 MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1649 MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1650 MODULE_LICENSE("GPL");
1651
1652 static struct pci_driver rt2400pci_driver = {
1653         .name           = KBUILD_MODNAME,
1654         .id_table       = rt2400pci_device_table,
1655         .probe          = rt2x00pci_probe,
1656         .remove         = __devexit_p(rt2x00pci_remove),
1657         .suspend        = rt2x00pci_suspend,
1658         .resume         = rt2x00pci_resume,
1659 };
1660
1661 static int __init rt2400pci_init(void)
1662 {
1663         return pci_register_driver(&rt2400pci_driver);
1664 }
1665
1666 static void __exit rt2400pci_exit(void)
1667 {
1668         pci_unregister_driver(&rt2400pci_driver);
1669 }
1670
1671 module_init(rt2400pci_init);
1672 module_exit(rt2400pci_exit);