SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/rt2x00/rt2400pci.c

   1 /*
   2         Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt2400pci
  23         Abstract: rt2400pci device specific routines.
  24         Supported chipsets: RT2460.
  25  */
  26
  27 /*
  28  * Set enviroment defines for rt2x00.h
  29  */
  30 #define DRV_NAME "rt2400pci"
  31
  32 #include <linux/delay.h>
  33 #include <linux/etherdevice.h>
  34 #include <linux/init.h>
  35 #include <linux/kernel.h>
  36 #include <linux/module.h>
  37 #include <linux/pci.h>
  38 #include <linux/eeprom_93cx6.h>
  39
  40 #include "rt2x00.h"
  41 #include "rt2x00pci.h"
  42 #include "rt2400pci.h"
  43
  44 /*
  45  * Register access.
  46  * All access to the CSR registers will go through the methods
  47  * rt2x00pci_register_read and rt2x00pci_register_write.
  48  * BBP and RF register require indirect register access,
  49  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  50  * These indirect registers work with busy bits,
  51  * and we will try maximal REGISTER_BUSY_COUNT times to access
  52  * the register while taking a REGISTER_BUSY_DELAY us delay
  53  * between each attampt. When the busy bit is still set at that time,
  54  * the access attempt is considered to have failed,
  55  * and we will print an error.
  56  */
  57 static u32 rt2400pci_bbp_check(const struct rt2x00_dev *rt2x00dev)
  58 {
  59         u32 reg;
  60         unsigned int i;
  61
  62         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  63                 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
  64                 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
  65                         break;
  66                 udelay(REGISTER_BUSY_DELAY);
  67         }
  68
  69         return reg;
  70 }
  71
  72 static void rt2400pci_bbp_write(const struct rt2x00_dev *rt2x00dev,
  73                                 const unsigned int word, const u8 value)
  74 {
  75         u32 reg;
  76
  77         /*
  78          * Wait until the BBP becomes ready.
  79          */
  80         reg = rt2400pci_bbp_check(rt2x00dev);
  81         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
  82                 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
  83                 return;
  84         }
  85
  86         /*
  87          * Write the data into the BBP.
  88          */
  89         reg = 0;
  90         rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
  91         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  92         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
  93         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
  94
  95         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
  96 }
  97
  98 static void rt2400pci_bbp_read(const struct rt2x00_dev *rt2x00dev,
  99                                const unsigned int word, u8 *value)
 100 {
 101         u32 reg;
 102
 103         /*
 104          * Wait until the BBP becomes ready.
 105          */
 106         reg = rt2400pci_bbp_check(rt2x00dev);
 107         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
 108                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
 109                 return;
 110         }
 111
 112         /*
 113          * Write the request into the BBP.
 114          */
 115         reg = 0;
 116         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
 117         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
 118         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
 119
 120         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
 121
 122         /*
 123          * Wait until the BBP becomes ready.
 124          */
 125         reg = rt2400pci_bbp_check(rt2x00dev);
 126         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
 127                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
 128                 *value = 0xff;
 129                 return;
 130         }
 131
 132         *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
 133 }
 134
 135 static void rt2400pci_rf_write(const struct rt2x00_dev *rt2x00dev,
 136                                const unsigned int word, const u32 value)
 137 {
 138         u32 reg;
 139         unsigned int i;
 140
 141         if (!word)
 142                 return;
 143
 144         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 145                 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
 146                 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
 147                         goto rf_write;
 148                 udelay(REGISTER_BUSY_DELAY);
 149         }
 150
 151         ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
 152         return;
 153
 154 rf_write:
 155         reg = 0;
 156         rt2x00_set_field32(&reg, RFCSR_VALUE, value);
 157         rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
 158         rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
 159         rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
 160
 161         rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
 162         rt2x00_rf_write(rt2x00dev, word, value);
 163 }
 164
 165 static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 166 {
 167         struct rt2x00_dev *rt2x00dev = eeprom->data;
 168         u32 reg;
 169
 170         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
 171
 172         eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
 173         eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
 174         eeprom->reg_data_clock =
 175             !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
 176         eeprom->reg_chip_select =
 177             !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
 178 }
 179
 180 static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 181 {
 182         struct rt2x00_dev *rt2x00dev = eeprom->data;
 183         u32 reg = 0;
 184
 185         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
 186         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
 187         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
 188                            !!eeprom->reg_data_clock);
 189         rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
 190                            !!eeprom->reg_chip_select);
 191
 192         rt2x00pci_register_write(rt2x00dev, CSR21, reg);
 193 }
 194
 195 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 196 #define CSR_OFFSET(__word)      ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
 197
 198 static void rt2400pci_read_csr(const struct rt2x00_dev *rt2x00dev,
 199                                const unsigned int word, u32 *data)
 200 {
 201         rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
 202 }
 203
 204 static void rt2400pci_write_csr(const struct rt2x00_dev *rt2x00dev,
 205                                 const unsigned int word, u32 data)
 206 {
 207         rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
 208 }
 209
 210 static const struct rt2x00debug rt2400pci_rt2x00debug = {
 211         .owner  = THIS_MODULE,
 212         .csr    = {
 213                 .read           = rt2400pci_read_csr,
 214                 .write          = rt2400pci_write_csr,
 215                 .word_size      = sizeof(u32),
 216                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 217         },
 218         .eeprom = {
 219                 .read           = rt2x00_eeprom_read,
 220                 .write          = rt2x00_eeprom_write,
 221                 .word_size      = sizeof(u16),
 222                 .word_count     = EEPROM_SIZE / sizeof(u16),
 223         },
 224         .bbp    = {
 225                 .read           = rt2400pci_bbp_read,
 226                 .write          = rt2400pci_bbp_write,
 227                 .word_size      = sizeof(u8),
 228                 .word_count     = BBP_SIZE / sizeof(u8),
 229         },
 230         .rf     = {
 231                 .read           = rt2x00_rf_read,
 232                 .write          = rt2400pci_rf_write,
 233                 .word_size      = sizeof(u32),
 234                 .word_count     = RF_SIZE / sizeof(u32),
 235         },
 236 };
 237 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 238
 239 #ifdef CONFIG_RT2400PCI_RFKILL
 240 static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 241 {
 242         u32 reg;
 243
 244         rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
 245         return rt2x00_get_field32(reg, GPIOCSR_BIT0);
 246 }
 247 #else
 248 #define rt2400pci_rfkill_poll   NULL
 249 #endif /* CONFIG_RT2400PCI_RFKILL */
 250
 251 /*
 252  * Configuration handlers.
 253  */
 254 static void rt2400pci_config_mac_addr(struct rt2x00_dev *rt2x00dev,
 255                                       __le32 *mac)
 256 {
 257         rt2x00pci_register_multiwrite(rt2x00dev, CSR3, mac,
 258                                       (2 * sizeof(__le32)));
 259 }
 260
 261 static void rt2400pci_config_bssid(struct rt2x00_dev *rt2x00dev,
 262                                    __le32 *bssid)
 263 {
 264         rt2x00pci_register_multiwrite(rt2x00dev, CSR5, bssid,
 265                                       (2 * sizeof(__le32)));
 266 }
 267
 268 static void rt2400pci_config_type(struct rt2x00_dev *rt2x00dev, const int type,
 269                                   const int tsf_sync)
 270 {
 271         u32 reg;
 272
 273         rt2x00pci_register_write(rt2x00dev, CSR14, 0);
 274
 275         /*
 276          * Enable beacon config
 277          */
 278         rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
 279         rt2x00_set_field32(&reg, BCNCSR1_PRELOAD,
 280                            PREAMBLE + get_duration(IEEE80211_HEADER, 20));
 281         rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
 282
 283         /*
 284          * Enable synchronisation.
 285          */
 286         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
 287         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
 288         rt2x00_set_field32(&reg, CSR14_TBCN, 1);
 289         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
 290         rt2x00_set_field32(&reg, CSR14_TSF_SYNC, tsf_sync);
 291         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 292 }
 293
 294 static void rt2400pci_config_rate(struct rt2x00_dev *rt2x00dev, const int rate)
 295 {
 296         struct ieee80211_conf *conf = &rt2x00dev->hw->conf;
 297         u32 reg;
 298         u32 preamble;
 299         u16 value;
 300
 301         if (DEVICE_GET_RATE_FIELD(rate, PREAMBLE))
 302                 preamble = SHORT_PREAMBLE;
 303         else
 304                 preamble = PREAMBLE;
 305
 306         reg = DEVICE_GET_RATE_FIELD(rate, RATEMASK) & DEV_BASIC_RATEMASK;
 307         rt2x00pci_register_write(rt2x00dev, ARCSR1, reg);
 308
 309         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 310         value = ((conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME) ?
 311                  SHORT_DIFS : DIFS) +
 312             PLCP + preamble + get_duration(ACK_SIZE, 10);
 313         rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, value);
 314         value = SIFS + PLCP + preamble + get_duration(ACK_SIZE, 10);
 315         rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, value);
 316         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 317
 318         preamble = DEVICE_GET_RATE_FIELD(rate, PREAMBLE) ? 0x08 : 0x00;
 319
 320         rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
 321         rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00 | preamble);
 322         rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
 323         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
 324         rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
 325
 326         rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
 327         rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble);
 328         rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
 329         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
 330         rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
 331
 332         rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
 333         rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble);
 334         rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
 335         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
 336         rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
 337
 338         rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
 339         rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble);
 340         rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
 341         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
 342         rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
 343 }
 344
 345 static void rt2400pci_config_phymode(struct rt2x00_dev *rt2x00dev,
 346                                      const int phymode)
 347 {
 348         struct ieee80211_hw_mode *mode;
 349         struct ieee80211_rate *rate;
 350
 351         rt2x00dev->curr_hwmode = HWMODE_B;
 352
 353         mode = &rt2x00dev->hwmodes[rt2x00dev->curr_hwmode];
 354         rate = &mode->rates[mode->num_rates - 1];
 355
 356         rt2400pci_config_rate(rt2x00dev, rate->val2);
 357 }
 358
 359 static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
 360                                      const int index, const int channel)
 361 {
 362         struct rf_channel reg;
 363
 364         /*
 365          * Fill rf_reg structure.
 366          */
 367         memcpy(&reg, &rt2x00dev->spec.channels[index], sizeof(reg));
 368
 369         /*
 370          * Switch on tuning bits.
 371          */
 372         rt2x00_set_field32(&reg.rf1, RF1_TUNER, 1);
 373         rt2x00_set_field32(&reg.rf3, RF3_TUNER, 1);
 374
 375         rt2400pci_rf_write(rt2x00dev, 1, reg.rf1);
 376         rt2400pci_rf_write(rt2x00dev, 2, reg.rf2);
 377         rt2400pci_rf_write(rt2x00dev, 3, reg.rf3);
 378
 379         /*
 380          * RF2420 chipset don't need any additional actions.
 381          */
 382         if (rt2x00_rf(&rt2x00dev->chip, RF2420))
 383                 return;
 384
 385         /*
 386          * For the RT2421 chipsets we need to write an invalid
 387          * reference clock rate to activate auto_tune.
 388          * After that we set the value back to the correct channel.
 389          */
 390         rt2400pci_rf_write(rt2x00dev, 1, reg.rf1);
 391         rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
 392         rt2400pci_rf_write(rt2x00dev, 3, reg.rf3);
 393
 394         msleep(1);
 395
 396         rt2400pci_rf_write(rt2x00dev, 1, reg.rf1);
 397         rt2400pci_rf_write(rt2x00dev, 2, reg.rf2);
 398         rt2400pci_rf_write(rt2x00dev, 3, reg.rf3);
 399
 400         msleep(1);
 401
 402         /*
 403          * Switch off tuning bits.
 404          */
 405         rt2x00_set_field32(&reg.rf1, RF1_TUNER, 0);
 406         rt2x00_set_field32(&reg.rf3, RF3_TUNER, 0);
 407
 408         rt2400pci_rf_write(rt2x00dev, 1, reg.rf1);
 409         rt2400pci_rf_write(rt2x00dev, 3, reg.rf3);
 410
 411         /*
 412          * Clear false CRC during channel switch.
 413          */
 414         rt2x00pci_register_read(rt2x00dev, CNT0, &reg.rf1);
 415 }
 416
 417 static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
 418 {
 419         rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
 420 }
 421
 422 static void rt2400pci_config_antenna(struct rt2x00_dev *rt2x00dev,
 423                                      int antenna_tx, int antenna_rx)
 424 {
 425         u8 r1;
 426         u8 r4;
 427
 428         rt2400pci_bbp_read(rt2x00dev, 4, &r4);
 429         rt2400pci_bbp_read(rt2x00dev, 1, &r1);
 430
 431         /*
 432          * Configure the TX antenna.
 433          */
 434         switch (antenna_tx) {
 435         case ANTENNA_SW_DIVERSITY:
 436         case ANTENNA_HW_DIVERSITY:
 437                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
 438                 break;
 439         case ANTENNA_A:
 440                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
 441                 break;
 442         case ANTENNA_B:
 443                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
 444                 break;
 445         }
 446
 447         /*
 448          * Configure the RX antenna.
 449          */
 450         switch (antenna_rx) {
 451         case ANTENNA_SW_DIVERSITY:
 452         case ANTENNA_HW_DIVERSITY:
 453                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
 454                 break;
 455         case ANTENNA_A:
 456                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
 457                 break;
 458         case ANTENNA_B:
 459                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
 460                 break;
 461         }
 462
 463         rt2400pci_bbp_write(rt2x00dev, 4, r4);
 464         rt2400pci_bbp_write(rt2x00dev, 1, r1);
 465 }
 466
 467 static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev,
 468                                       int short_slot_time, int beacon_int)
 469 {
 470         u32 reg;
 471
 472         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 473         rt2x00_set_field32(&reg, CSR11_SLOT_TIME,
 474                            short_slot_time ? SHORT_SLOT_TIME : SLOT_TIME);
 475         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 476
 477         rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
 478         rt2x00_set_field32(&reg, CSR18_SIFS, SIFS);
 479         rt2x00_set_field32(&reg, CSR18_PIFS,
 480                            short_slot_time ? SHORT_PIFS : PIFS);
 481         rt2x00pci_register_write(rt2x00dev, CSR18, reg);
 482
 483         rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
 484         rt2x00_set_field32(&reg, CSR19_DIFS,
 485                            short_slot_time ? SHORT_DIFS : DIFS);
 486         rt2x00_set_field32(&reg, CSR19_EIFS, EIFS);
 487         rt2x00pci_register_write(rt2x00dev, CSR19, reg);
 488
 489         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 490         rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
 491         rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
 492         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 493
 494         rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
 495         rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL, beacon_int * 16);
 496         rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION, beacon_int * 16);
 497         rt2x00pci_register_write(rt2x00dev, CSR12, reg);
 498 }
 499
 500 static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
 501                              const unsigned int flags,
 502                              struct ieee80211_conf *conf)
 503 {
 504         int short_slot_time = conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME;
 505
 506         if (flags & CONFIG_UPDATE_PHYMODE)
 507                 rt2400pci_config_phymode(rt2x00dev, conf->phymode);
 508         if (flags & CONFIG_UPDATE_CHANNEL)
 509                 rt2400pci_config_channel(rt2x00dev, conf->channel_val,
 510                                          conf->channel);
 511         if (flags & CONFIG_UPDATE_TXPOWER)
 512                 rt2400pci_config_txpower(rt2x00dev, conf->power_level);
 513         if (flags & CONFIG_UPDATE_ANTENNA)
 514                 rt2400pci_config_antenna(rt2x00dev, conf->antenna_sel_tx,
 515                                          conf->antenna_sel_rx);
 516         if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
 517                 rt2400pci_config_duration(rt2x00dev, short_slot_time,
 518                                           conf->beacon_int);
 519 }
 520
 521 static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
 522                                 struct ieee80211_tx_queue_params *params)
 523 {
 524         u32 reg;
 525
 526         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 527         rt2x00_set_field32(&reg, CSR11_CWMIN, params->cw_min);
 528         rt2x00_set_field32(&reg, CSR11_CWMAX, params->cw_max);
 529         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 530 }
 531
 532 /*
 533  * LED functions.
 534  */
 535 static void rt2400pci_enable_led(struct rt2x00_dev *rt2x00dev)
 536 {
 537         u32 reg;
 538
 539         rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
 540
 541         rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, 70);
 542         rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, 30);
 543
 544         if (rt2x00dev->led_mode == LED_MODE_TXRX_ACTIVITY) {
 545                 rt2x00_set_field32(&reg, LEDCSR_LINK, 1);
 546                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 0);
 547         } else if (rt2x00dev->led_mode == LED_MODE_ASUS) {
 548                 rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
 549                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 1);
 550         } else {
 551                 rt2x00_set_field32(&reg, LEDCSR_LINK, 1);
 552                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 1);
 553         }
 554
 555         rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
 556 }
 557
 558 static void rt2400pci_disable_led(struct rt2x00_dev *rt2x00dev)
 559 {
 560         u32 reg;
 561
 562         rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
 563         rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
 564         rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 0);
 565         rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
 566 }
 567
 568 /*
 569  * Link tuning
 570  */
 571 static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev)
 572 {
 573         u32 reg;
 574         u8 bbp;
 575
 576         /*
 577          * Update FCS error count from register.
 578          */
 579         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 580         rt2x00dev->link.rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
 581
 582         /*
 583          * Update False CCA count from register.
 584          */
 585         rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
 586         rt2x00dev->link.false_cca = bbp;
 587 }
 588
 589 static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
 590 {
 591         rt2400pci_bbp_write(rt2x00dev, 13, 0x08);
 592         rt2x00dev->link.vgc_level = 0x08;
 593 }
 594
 595 static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev)
 596 {
 597         u8 reg;
 598
 599         /*
 600          * The link tuner should not run longer then 60 seconds,
 601          * and should run once every 2 seconds.
 602          */
 603         if (rt2x00dev->link.count > 60 || !(rt2x00dev->link.count & 1))
 604                 return;
 605
 606         /*
 607          * Base r13 link tuning on the false cca count.
 608          */
 609         rt2400pci_bbp_read(rt2x00dev, 13, &reg);
 610
 611         if (rt2x00dev->link.false_cca > 512 && reg < 0x20) {
 612                 rt2400pci_bbp_write(rt2x00dev, 13, ++reg);
 613                 rt2x00dev->link.vgc_level = reg;
 614         } else if (rt2x00dev->link.false_cca < 100 && reg > 0x08) {
 615                 rt2400pci_bbp_write(rt2x00dev, 13, --reg);
 616                 rt2x00dev->link.vgc_level = reg;
 617         }
 618 }
 619
 620 /*
 621  * Initialization functions.
 622  */
 623 static void rt2400pci_init_rxring(struct rt2x00_dev *rt2x00dev)
 624 {
 625         struct data_ring *ring = rt2x00dev->rx;
 626         struct data_desc *rxd;
 627         unsigned int i;
 628         u32 word;
 629
 630         memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
 631
 632         for (i = 0; i < ring->stats.limit; i++) {
 633                 rxd = ring->entry[i].priv;
 634
 635                 rt2x00_desc_read(rxd, 2, &word);
 636                 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH,
 637                                    ring->data_size);
 638                 rt2x00_desc_write(rxd, 2, word);
 639
 640                 rt2x00_desc_read(rxd, 1, &word);
 641                 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS,
 642                                    ring->entry[i].data_dma);
 643                 rt2x00_desc_write(rxd, 1, word);
 644
 645                 rt2x00_desc_read(rxd, 0, &word);
 646                 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
 647                 rt2x00_desc_write(rxd, 0, word);
 648         }
 649
 650         rt2x00_ring_index_clear(rt2x00dev->rx);
 651 }
 652
 653 static void rt2400pci_init_txring(struct rt2x00_dev *rt2x00dev, const int queue)
 654 {
 655         struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
 656         struct data_desc *txd;
 657         unsigned int i;
 658         u32 word;
 659
 660         memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
 661
 662         for (i = 0; i < ring->stats.limit; i++) {
 663                 txd = ring->entry[i].priv;
 664
 665                 rt2x00_desc_read(txd, 1, &word);
 666                 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS,
 667                                    ring->entry[i].data_dma);
 668                 rt2x00_desc_write(txd, 1, word);
 669
 670                 rt2x00_desc_read(txd, 2, &word);
 671                 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH,
 672                                    ring->data_size);
 673                 rt2x00_desc_write(txd, 2, word);
 674
 675                 rt2x00_desc_read(txd, 0, &word);
 676                 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
 677                 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
 678                 rt2x00_desc_write(txd, 0, word);
 679         }
 680
 681         rt2x00_ring_index_clear(ring);
 682 }
 683
 684 static int rt2400pci_init_rings(struct rt2x00_dev *rt2x00dev)
 685 {
 686         u32 reg;
 687
 688         /*
 689          * Initialize rings.
 690          */
 691         rt2400pci_init_rxring(rt2x00dev);
 692         rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
 693         rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
 694         rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
 695         rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
 696
 697         /*
 698          * Initialize registers.
 699          */
 700         rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
 701         rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE,
 702                            rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size);
 703         rt2x00_set_field32(&reg, TXCSR2_NUM_TXD,
 704                            rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit);
 705         rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM,
 706                            rt2x00dev->bcn[1].stats.limit);
 707         rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO,
 708                            rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit);
 709         rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
 710
 711         rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
 712         rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
 713                            rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma);
 714         rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
 715
 716         rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
 717         rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
 718                            rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma);
 719         rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
 720
 721         rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
 722         rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
 723                            rt2x00dev->bcn[1].data_dma);
 724         rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
 725
 726         rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
 727         rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
 728                            rt2x00dev->bcn[0].data_dma);
 729         rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
 730
 731         rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
 732         rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
 733         rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->stats.limit);
 734         rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
 735
 736         rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
 737         rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
 738                            rt2x00dev->rx->data_dma);
 739         rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
 740
 741         return 0;
 742 }
 743
 744 static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
 745 {
 746         u32 reg;
 747
 748         rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
 749         rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
 750         rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
 751         rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
 752
 753         rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
 754         rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
 755         rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
 756         rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
 757         rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
 758
 759         rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
 760         rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
 761                            (rt2x00dev->rx->data_size / 128));
 762         rt2x00pci_register_write(rt2x00dev, CSR9, reg);
 763
 764         rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
 765
 766         rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
 767         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
 768         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
 769         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
 770         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
 771         rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
 772
 773         rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
 774         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
 775         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
 776         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
 777         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
 778         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
 779         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
 780         rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
 781
 782         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
 783
 784         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
 785                 return -EBUSY;
 786
 787         rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
 788         rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
 789
 790         rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
 791         rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
 792         rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
 793
 794         rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
 795         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
 796         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
 797         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
 798         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
 799         rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
 800
 801         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 802         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
 803         rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
 804         rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
 805         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 806
 807         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 808         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
 809         rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
 810         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 811
 812         /*
 813          * We must clear the FCS and FIFO error count.
 814          * These registers are cleared on read,
 815          * so we may pass a useless variable to store the value.
 816          */
 817         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 818         rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
 819
 820         return 0;
 821 }
 822
 823 static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
 824 {
 825         unsigned int i;
 826         u16 eeprom;
 827         u8 reg_id;
 828         u8 value;
 829
 830         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 831                 rt2400pci_bbp_read(rt2x00dev, 0, &value);
 832                 if ((value != 0xff) && (value != 0x00))
 833                         goto continue_csr_init;
 834                 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
 835                 udelay(REGISTER_BUSY_DELAY);
 836         }
 837
 838         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
 839         return -EACCES;
 840
 841 continue_csr_init:
 842         rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
 843         rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
 844         rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
 845         rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
 846         rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
 847         rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
 848         rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
 849         rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
 850         rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
 851         rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
 852         rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
 853         rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
 854         rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
 855         rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
 856
 857         DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
 858         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
 859                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
 860
 861                 if (eeprom != 0xffff && eeprom != 0x0000) {
 862                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
 863                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
 864                         DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
 865                               reg_id, value);
 866                         rt2400pci_bbp_write(rt2x00dev, reg_id, value);
 867                 }
 868         }
 869         DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
 870
 871         return 0;
 872 }
 873
 874 /*
 875  * Device state switch handlers.
 876  */
 877 static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
 878                                 enum dev_state state)
 879 {
 880         u32 reg;
 881
 882         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
 883         rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
 884                            state == STATE_RADIO_RX_OFF);
 885         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
 886 }
 887
 888 static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
 889                                  enum dev_state state)
 890 {
 891         int mask = (state == STATE_RADIO_IRQ_OFF);
 892         u32 reg;
 893
 894         /*
 895          * When interrupts are being enabled, the interrupt registers
 896          * should clear the register to assure a clean state.
 897          */
 898         if (state == STATE_RADIO_IRQ_ON) {
 899                 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
 900                 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
 901         }
 902
 903         /*
 904          * Only toggle the interrupts bits we are going to use.
 905          * Non-checked interrupt bits are disabled by default.
 906          */
 907         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
 908         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
 909         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
 910         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
 911         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
 912         rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
 913         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
 914 }
 915
 916 static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
 917 {
 918         /*
 919          * Initialize all registers.
 920          */
 921         if (rt2400pci_init_rings(rt2x00dev) ||
 922             rt2400pci_init_registers(rt2x00dev) ||
 923             rt2400pci_init_bbp(rt2x00dev)) {
 924                 ERROR(rt2x00dev, "Register initialization failed.\n");
 925                 return -EIO;
 926         }
 927
 928         /*
 929          * Enable interrupts.
 930          */
 931         rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
 932
 933         /*
 934          * Enable LED
 935          */
 936         rt2400pci_enable_led(rt2x00dev);
 937
 938         return 0;
 939 }
 940
 941 static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
 942 {
 943         u32 reg;
 944
 945         /*
 946          * Disable LED
 947          */
 948         rt2400pci_disable_led(rt2x00dev);
 949
 950         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
 951
 952         /*
 953          * Disable synchronisation.
 954          */
 955         rt2x00pci_register_write(rt2x00dev, CSR14, 0);
 956
 957         /*
 958          * Cancel RX and TX.
 959          */
 960         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
 961         rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
 962         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
 963
 964         /*
 965          * Disable interrupts.
 966          */
 967         rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
 968 }
 969
 970 static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
 971                                enum dev_state state)
 972 {
 973         u32 reg;
 974         unsigned int i;
 975         char put_to_sleep;
 976         char bbp_state;
 977         char rf_state;
 978
 979         put_to_sleep = (state != STATE_AWAKE);
 980
 981         rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
 982         rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
 983         rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
 984         rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
 985         rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
 986         rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
 987
 988         /*
 989          * Device is not guaranteed to be in the requested state yet.
 990          * We must wait until the register indicates that the
 991          * device has entered the correct state.
 992          */
 993         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 994                 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
 995                 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
 996                 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
 997                 if (bbp_state == state && rf_state == state)
 998                         return 0;
 999                 msleep(10);
1000         }
1001
1002         NOTICE(rt2x00dev, "Device failed to enter state %d, "
1003                "current device state: bbp %d and rf %d.\n",
1004                state, bbp_state, rf_state);
1005
1006         return -EBUSY;
1007 }
1008
1009 static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1010                                       enum dev_state state)
1011 {
1012         int retval = 0;
1013
1014         switch (state) {
1015         case STATE_RADIO_ON:
1016                 retval = rt2400pci_enable_radio(rt2x00dev);
1017                 break;
1018         case STATE_RADIO_OFF:
1019                 rt2400pci_disable_radio(rt2x00dev);
1020                 break;
1021         case STATE_RADIO_RX_ON:
1022         case STATE_RADIO_RX_OFF:
1023                 rt2400pci_toggle_rx(rt2x00dev, state);
1024                 break;
1025         case STATE_DEEP_SLEEP:
1026         case STATE_SLEEP:
1027         case STATE_STANDBY:
1028         case STATE_AWAKE:
1029                 retval = rt2400pci_set_state(rt2x00dev, state);
1030                 break;
1031         default:
1032                 retval = -ENOTSUPP;
1033                 break;
1034         }
1035
1036         return retval;
1037 }
1038
1039 /*
1040  * TX descriptor initialization
1041  */
1042 static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1043                                     struct data_desc *txd,
1044                                     struct txdata_entry_desc *desc,
1045                                     struct ieee80211_hdr *ieee80211hdr,
1046                                     unsigned int length,
1047                                     struct ieee80211_tx_control *control)
1048 {
1049         u32 word;
1050         u32 signal = 0;
1051         u32 service = 0;
1052         u32 length_high = 0;
1053         u32 length_low = 0;
1054
1055         /*
1056          * The PLCP values should be treated as if they
1057          * were BBP values.
1058          */
1059         rt2x00_set_field32(&signal, BBPCSR_VALUE, desc->signal);
1060         rt2x00_set_field32(&signal, BBPCSR_REGNUM, 5);
1061         rt2x00_set_field32(&signal, BBPCSR_BUSY, 1);
1062
1063         rt2x00_set_field32(&service, BBPCSR_VALUE, desc->service);
1064         rt2x00_set_field32(&service, BBPCSR_REGNUM, 6);
1065         rt2x00_set_field32(&service, BBPCSR_BUSY, 1);
1066
1067         rt2x00_set_field32(&length_high, BBPCSR_VALUE, desc->length_high);
1068         rt2x00_set_field32(&length_high, BBPCSR_REGNUM, 7);
1069         rt2x00_set_field32(&length_high, BBPCSR_BUSY, 1);
1070
1071         rt2x00_set_field32(&length_low, BBPCSR_VALUE, desc->length_low);
1072         rt2x00_set_field32(&length_low, BBPCSR_REGNUM, 8);
1073         rt2x00_set_field32(&length_low, BBPCSR_BUSY, 1);
1074
1075         /*
1076          * Start writing the descriptor words.
1077          */
1078         rt2x00_desc_read(txd, 2, &word);
1079         rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, length);
1080         rt2x00_desc_write(txd, 2, word);
1081
1082         rt2x00_desc_read(txd, 3, &word);
1083         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, signal);
1084         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, service);
1085         rt2x00_desc_write(txd, 3, word);
1086
1087         rt2x00_desc_read(txd, 4, &word);
1088         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, length_low);
1089         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, length_high);
1090         rt2x00_desc_write(txd, 4, word);
1091
1092         rt2x00_desc_read(txd, 0, &word);
1093         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1094         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1095         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1096                            test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
1097         rt2x00_set_field32(&word, TXD_W0_ACK,
1098                            !(control->flags & IEEE80211_TXCTL_NO_ACK));
1099         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1100                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
1101         rt2x00_set_field32(&word, TXD_W0_RTS,
1102                            test_bit(ENTRY_TXD_RTS_FRAME, &desc->flags));
1103         rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
1104         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1105                            !!(control->flags &
1106                               IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1107         rt2x00_desc_write(txd, 0, word);
1108 }
1109
1110 /*
1111  * TX data initialization
1112  */
1113 static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1114                                     unsigned int queue)
1115 {
1116         u32 reg;
1117
1118         if (queue == IEEE80211_TX_QUEUE_BEACON) {
1119                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1120                 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1121                         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1122                         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1123                 }
1124                 return;
1125         }
1126
1127         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1128         if (queue == IEEE80211_TX_QUEUE_DATA0)
1129                 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1);
1130         else if (queue == IEEE80211_TX_QUEUE_DATA1)
1131                 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1);
1132         else if (queue == IEEE80211_TX_QUEUE_AFTER_BEACON)
1133                 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1);
1134         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1135 }
1136
1137 /*
1138  * RX control handlers
1139  */
1140 static void rt2400pci_fill_rxdone(struct data_entry *entry,
1141                                   struct rxdata_entry_desc *desc)
1142 {
1143         struct data_desc *rxd = entry->priv;
1144         u32 word0;
1145         u32 word2;
1146
1147         rt2x00_desc_read(rxd, 0, &word0);
1148         rt2x00_desc_read(rxd, 2, &word2);
1149
1150         desc->flags = 0;
1151         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1152                 desc->flags |= RX_FLAG_FAILED_FCS_CRC;
1153         if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1154                 desc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1155
1156         /*
1157          * Obtain the status about this packet.
1158          */
1159         desc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1160         desc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1161             entry->ring->rt2x00dev->rssi_offset;
1162         desc->ofdm = 0;
1163         desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1164 }
1165
1166 /*
1167  * Interrupt functions.
1168  */
1169 static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev, const int queue)
1170 {
1171         struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
1172         struct data_entry *entry;
1173         struct data_desc *txd;
1174         u32 word;
1175         int tx_status;
1176         int retry;
1177
1178         while (!rt2x00_ring_empty(ring)) {
1179                 entry = rt2x00_get_data_entry_done(ring);
1180                 txd = entry->priv;
1181                 rt2x00_desc_read(txd, 0, &word);
1182
1183                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1184                     !rt2x00_get_field32(word, TXD_W0_VALID))
1185                         break;
1186
1187                 /*
1188                  * Obtain the status about this packet.
1189                  */
1190                 tx_status = rt2x00_get_field32(word, TXD_W0_RESULT);
1191                 retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1192
1193                 rt2x00lib_txdone(entry, tx_status, retry);
1194
1195                 /*
1196                  * Make this entry available for reuse.
1197                  */
1198                 entry->flags = 0;
1199                 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1200                 rt2x00_desc_write(txd, 0, word);
1201                 rt2x00_ring_index_done_inc(ring);
1202         }
1203
1204         /*
1205          * If the data ring was full before the txdone handler
1206          * we must make sure the packet queue in the mac80211 stack
1207          * is reenabled when the txdone handler has finished.
1208          */
1209         entry = ring->entry;
1210         if (!rt2x00_ring_full(ring))
1211                 ieee80211_wake_queue(rt2x00dev->hw,
1212                                      entry->tx_status.control.queue);
1213 }
1214
1215 static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1216 {
1217         struct rt2x00_dev *rt2x00dev = dev_instance;
1218         u32 reg;
1219
1220         /*
1221          * Get the interrupt sources & saved to local variable.
1222          * Write register value back to clear pending interrupts.
1223          */
1224         rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1225         rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1226
1227         if (!reg)
1228                 return IRQ_NONE;
1229
1230         if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1231                 return IRQ_HANDLED;
1232
1233         /*
1234          * Handle interrupts, walk through all bits
1235          * and run the tasks, the bits are checked in order of
1236          * priority.
1237          */
1238
1239         /*
1240          * 1 - Beacon timer expired interrupt.
1241          */
1242         if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1243                 rt2x00lib_beacondone(rt2x00dev);
1244
1245         /*
1246          * 2 - Rx ring done interrupt.
1247          */
1248         if (rt2x00_get_field32(reg, CSR7_RXDONE))
1249                 rt2x00pci_rxdone(rt2x00dev);
1250
1251         /*
1252          * 3 - Atim ring transmit done interrupt.
1253          */
1254         if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1255                 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
1256
1257         /*
1258          * 4 - Priority ring transmit done interrupt.
1259          */
1260         if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1261                 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1262
1263         /*
1264          * 5 - Tx ring transmit done interrupt.
1265          */
1266         if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1267                 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1268
1269         return IRQ_HANDLED;
1270 }
1271
1272 /*
1273  * Device probe functions.
1274  */
1275 static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1276 {
1277         struct eeprom_93cx6 eeprom;
1278         u32 reg;
1279         u16 word;
1280         u8 *mac;
1281
1282         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1283
1284         eeprom.data = rt2x00dev;
1285         eeprom.register_read = rt2400pci_eepromregister_read;
1286         eeprom.register_write = rt2400pci_eepromregister_write;
1287         eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1288             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1289         eeprom.reg_data_in = 0;
1290         eeprom.reg_data_out = 0;
1291         eeprom.reg_data_clock = 0;
1292         eeprom.reg_chip_select = 0;
1293
1294         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1295                                EEPROM_SIZE / sizeof(u16));
1296
1297         /*
1298          * Start validation of the data that has been read.
1299          */
1300         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1301         if (!is_valid_ether_addr(mac)) {
1302                 DECLARE_MAC_BUF(macbuf);
1303
1304                 random_ether_addr(mac);
1305                 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
1306         }
1307
1308         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1309         if (word == 0xffff) {
1310                 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1311                 return -EINVAL;
1312         }
1313
1314         return 0;
1315 }
1316
1317 static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1318 {
1319         u32 reg;
1320         u16 value;
1321         u16 eeprom;
1322
1323         /*
1324          * Read EEPROM word for configuration.
1325          */
1326         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1327
1328         /*
1329          * Identify RF chipset.
1330          */
1331         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1332         rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1333         rt2x00_set_chip(rt2x00dev, RT2460, value, reg);
1334
1335         if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
1336             !rt2x00_rf(&rt2x00dev->chip, RF2421)) {
1337                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1338                 return -ENODEV;
1339         }
1340
1341         /*
1342          * Identify default antenna configuration.
1343          */
1344         rt2x00dev->hw->conf.antenna_sel_tx =
1345             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1346         rt2x00dev->hw->conf.antenna_sel_rx =
1347             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1348
1349         /*
1350          * Store led mode, for correct led behaviour.
1351          */
1352         rt2x00dev->led_mode =
1353             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1354
1355         /*
1356          * Detect if this device has an hardware controlled radio.
1357          */
1358 #ifdef CONFIG_RT2400PCI_RFKILL
1359         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1360                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1361 #endif /* CONFIG_RT2400PCI_RFKILL */
1362
1363         /*
1364          * Check if the BBP tuning should be enabled.
1365          */
1366         if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1367                 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1368
1369         return 0;
1370 }
1371
1372 /*
1373  * RF value list for RF2420 & RF2421
1374  * Supports: 2.4 GHz
1375  */
1376 static const struct rf_channel rf_vals_bg[] = {
1377         { 1,  0x00022058, 0x000c1fda, 0x00000101, 0 },
1378         { 2,  0x00022058, 0x000c1fee, 0x00000101, 0 },
1379         { 3,  0x00022058, 0x000c2002, 0x00000101, 0 },
1380         { 4,  0x00022058, 0x000c2016, 0x00000101, 0 },
1381         { 5,  0x00022058, 0x000c202a, 0x00000101, 0 },
1382         { 6,  0x00022058, 0x000c203e, 0x00000101, 0 },
1383         { 7,  0x00022058, 0x000c2052, 0x00000101, 0 },
1384         { 8,  0x00022058, 0x000c2066, 0x00000101, 0 },
1385         { 9,  0x00022058, 0x000c207a, 0x00000101, 0 },
1386         { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1387         { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1388         { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1389         { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1390         { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1391 };
1392
1393 static void rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1394 {
1395         struct hw_mode_spec *spec = &rt2x00dev->spec;
1396         u8 *txpower;
1397         unsigned int i;
1398
1399         /*
1400          * Initialize all hw fields.
1401          */
1402         rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
1403         rt2x00dev->hw->extra_tx_headroom = 0;
1404         rt2x00dev->hw->max_signal = MAX_SIGNAL;
1405         rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1406         rt2x00dev->hw->queues = 2;
1407
1408         SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1409         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1410                                 rt2x00_eeprom_addr(rt2x00dev,
1411                                                    EEPROM_MAC_ADDR_0));
1412
1413         /*
1414          * Convert tx_power array in eeprom.
1415          */
1416         txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1417         for (i = 0; i < 14; i++)
1418                 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1419
1420         /*
1421          * Initialize hw_mode information.
1422          */
1423         spec->num_modes = 1;
1424         spec->num_rates = 4;
1425         spec->tx_power_a = NULL;
1426         spec->tx_power_bg = txpower;
1427         spec->tx_power_default = DEFAULT_TXPOWER;
1428
1429         spec->num_channels = ARRAY_SIZE(rf_vals_bg);
1430         spec->channels = rf_vals_bg;
1431 }
1432
1433 static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1434 {
1435         int retval;
1436
1437         /*
1438          * Allocate eeprom data.
1439          */
1440         retval = rt2400pci_validate_eeprom(rt2x00dev);
1441         if (retval)
1442                 return retval;
1443
1444         retval = rt2400pci_init_eeprom(rt2x00dev);
1445         if (retval)
1446                 return retval;
1447
1448         /*
1449          * Initialize hw specifications.
1450          */
1451         rt2400pci_probe_hw_mode(rt2x00dev);
1452
1453         /*
1454          * This device requires the beacon ring
1455          */
1456         __set_bit(DRIVER_REQUIRE_BEACON_RING, &rt2x00dev->flags);
1457
1458         /*
1459          * Set the rssi offset.
1460          */
1461         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1462
1463         return 0;
1464 }
1465
1466 /*
1467  * IEEE80211 stack callback functions.
1468  */
1469 static void rt2400pci_configure_filter(struct ieee80211_hw *hw,
1470                                        unsigned int changed_flags,
1471                                        unsigned int *total_flags,
1472                                        int mc_count,
1473                                        struct dev_addr_list *mc_list)
1474 {
1475         struct rt2x00_dev *rt2x00dev = hw->priv;
1476         struct interface *intf = &rt2x00dev->interface;
1477         u32 reg;
1478
1479         /*
1480          * Mask off any flags we are going to ignore from
1481          * the total_flags field.
1482          */
1483         *total_flags &=
1484             FIF_ALLMULTI |
1485             FIF_FCSFAIL |
1486             FIF_PLCPFAIL |
1487             FIF_CONTROL |
1488             FIF_OTHER_BSS |
1489             FIF_PROMISC_IN_BSS;
1490
1491         /*
1492          * Apply some rules to the filters:
1493          * - Some filters imply different filters to be set.
1494          * - Some things we can't filter out at all.
1495          * - Some filters are set based on interface type.
1496          */
1497         *total_flags |= FIF_ALLMULTI;
1498         if (*total_flags & FIF_OTHER_BSS ||
1499             *total_flags & FIF_PROMISC_IN_BSS)
1500                 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
1501         if (is_interface_type(intf, IEEE80211_IF_TYPE_AP))
1502                 *total_flags |= FIF_PROMISC_IN_BSS;
1503
1504         /*
1505          * Check if there is any work left for us.
1506          */
1507         if (intf->filter == *total_flags)
1508                 return;
1509         intf->filter = *total_flags;
1510
1511         /*
1512          * Start configuration steps.
1513          * Note that the version error will always be dropped
1514          * since there is no filter for it at this time.
1515          */
1516         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1517         rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
1518                            !(*total_flags & FIF_FCSFAIL));
1519         rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
1520                            !(*total_flags & FIF_PLCPFAIL));
1521         rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
1522                            !(*total_flags & FIF_CONTROL));
1523         rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
1524                            !(*total_flags & FIF_PROMISC_IN_BSS));
1525         rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
1526                            !(*total_flags & FIF_PROMISC_IN_BSS));
1527         rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
1528         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1529 }
1530
1531 static int rt2400pci_set_retry_limit(struct ieee80211_hw *hw,
1532                                      u32 short_retry, u32 long_retry)
1533 {
1534         struct rt2x00_dev *rt2x00dev = hw->priv;
1535         u32 reg;
1536
1537         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1538         rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1539         rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1540         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1541
1542         return 0;
1543 }
1544
1545 static int rt2400pci_conf_tx(struct ieee80211_hw *hw,
1546                              int queue,
1547                              const struct ieee80211_tx_queue_params *params)
1548 {
1549         struct rt2x00_dev *rt2x00dev = hw->priv;
1550
1551         /*
1552          * We don't support variating cw_min and cw_max variables
1553          * per queue. So by default we only configure the TX queue,
1554          * and ignore all other configurations.
1555          */
1556         if (queue != IEEE80211_TX_QUEUE_DATA0)
1557                 return -EINVAL;
1558
1559         if (rt2x00mac_conf_tx(hw, queue, params))
1560                 return -EINVAL;
1561
1562         /*
1563          * Write configuration to register.
1564          */
1565         rt2400pci_config_cw(rt2x00dev, &rt2x00dev->tx->tx_params);
1566
1567         return 0;
1568 }
1569
1570 static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1571 {
1572         struct rt2x00_dev *rt2x00dev = hw->priv;
1573         u64 tsf;
1574         u32 reg;
1575
1576         rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1577         tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1578         rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1579         tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1580
1581         return tsf;
1582 }
1583
1584 static void rt2400pci_reset_tsf(struct ieee80211_hw *hw)
1585 {
1586         struct rt2x00_dev *rt2x00dev = hw->priv;
1587
1588         rt2x00pci_register_write(rt2x00dev, CSR16, 0);
1589         rt2x00pci_register_write(rt2x00dev, CSR17, 0);
1590 }
1591
1592 static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1593 {
1594         struct rt2x00_dev *rt2x00dev = hw->priv;
1595         u32 reg;
1596
1597         rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1598         return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1599 }
1600
1601 static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1602         .tx                     = rt2x00mac_tx,
1603         .start                  = rt2x00mac_start,
1604         .stop                   = rt2x00mac_stop,
1605         .add_interface          = rt2x00mac_add_interface,
1606         .remove_interface       = rt2x00mac_remove_interface,
1607         .config                 = rt2x00mac_config,
1608         .config_interface       = rt2x00mac_config_interface,
1609         .configure_filter       = rt2400pci_configure_filter,
1610         .get_stats              = rt2x00mac_get_stats,
1611         .set_retry_limit        = rt2400pci_set_retry_limit,
1612         .conf_tx                = rt2400pci_conf_tx,
1613         .get_tx_stats           = rt2x00mac_get_tx_stats,
1614         .get_tsf                = rt2400pci_get_tsf,
1615         .reset_tsf              = rt2400pci_reset_tsf,
1616         .beacon_update          = rt2x00pci_beacon_update,
1617         .tx_last_beacon         = rt2400pci_tx_last_beacon,
1618 };
1619
1620 static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1621         .irq_handler            = rt2400pci_interrupt,
1622         .probe_hw               = rt2400pci_probe_hw,
1623         .initialize             = rt2x00pci_initialize,
1624         .uninitialize           = rt2x00pci_uninitialize,
1625         .set_device_state       = rt2400pci_set_device_state,
1626         .rfkill_poll            = rt2400pci_rfkill_poll,
1627         .link_stats             = rt2400pci_link_stats,
1628         .reset_tuner            = rt2400pci_reset_tuner,
1629         .link_tuner             = rt2400pci_link_tuner,
1630         .write_tx_desc          = rt2400pci_write_tx_desc,
1631         .write_tx_data          = rt2x00pci_write_tx_data,
1632         .kick_tx_queue          = rt2400pci_kick_tx_queue,
1633         .fill_rxdone            = rt2400pci_fill_rxdone,
1634         .config_mac_addr        = rt2400pci_config_mac_addr,
1635         .config_bssid           = rt2400pci_config_bssid,
1636         .config_type            = rt2400pci_config_type,
1637         .config                 = rt2400pci_config,
1638 };
1639
1640 static const struct rt2x00_ops rt2400pci_ops = {
1641         .name           = DRV_NAME,
1642         .rxd_size       = RXD_DESC_SIZE,
1643         .txd_size       = TXD_DESC_SIZE,
1644         .eeprom_size    = EEPROM_SIZE,
1645         .rf_size        = RF_SIZE,
1646         .lib            = &rt2400pci_rt2x00_ops,
1647         .hw             = &rt2400pci_mac80211_ops,
1648 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1649         .debugfs        = &rt2400pci_rt2x00debug,
1650 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1651 };
1652
1653 /*
1654  * RT2400pci module information.
1655  */
1656 static struct pci_device_id rt2400pci_device_table[] = {
1657         { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1658         { 0, }
1659 };
1660
1661 MODULE_AUTHOR(DRV_PROJECT);
1662 MODULE_VERSION(DRV_VERSION);
1663 MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1664 MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1665 MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1666 MODULE_LICENSE("GPL");
1667
1668 static struct pci_driver rt2400pci_driver = {
1669         .name           = DRV_NAME,
1670         .id_table       = rt2400pci_device_table,
1671         .probe          = rt2x00pci_probe,
1672         .remove         = __devexit_p(rt2x00pci_remove),
1673         .suspend        = rt2x00pci_suspend,
1674         .resume         = rt2x00pci_resume,
1675 };
1676
1677 static int __init rt2400pci_init(void)
1678 {
1679         return pci_register_driver(&rt2400pci_driver);
1680 }
1681
1682 static void __exit rt2400pci_exit(void)
1683 {
1684         pci_unregister_driver(&rt2400pci_driver);
1685 }
1686
1687 module_init(rt2400pci_init);
1688 module_exit(rt2400pci_exit);