SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/rt2x00/rt2400pci.c

   1 /*
   2         Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
   3         <http://rt2x00.serialmonkey.com>
   4
   5         This program is free software; you can redistribute it and/or modify
   6         it under the terms of the GNU General Public License as published by
   7         the Free Software Foundation; either version 2 of the License, or
   8         (at your option) any later version.
   9
  10         This program is distributed in the hope that it will be useful,
  11         but WITHOUT ANY WARRANTY; without even the implied warranty of
  12         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13         GNU General Public License for more details.
  14
  15         You should have received a copy of the GNU General Public License
  16         along with this program; if not, write to the
  17         Free Software Foundation, Inc.,
  18         59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 /*
  22         Module: rt2400pci
  23         Abstract: rt2400pci device specific routines.
  24         Supported chipsets: RT2460.
  25  */
  26
  27 /*
  28  * Set enviroment defines for rt2x00.h
  29  */
  30 #define DRV_NAME "rt2400pci"
  31
  32 #include <linux/delay.h>
  33 #include <linux/etherdevice.h>
  34 #include <linux/init.h>
  35 #include <linux/kernel.h>
  36 #include <linux/module.h>
  37 #include <linux/pci.h>
  38 #include <linux/eeprom_93cx6.h>
  39
  40 #include "rt2x00.h"
  41 #include "rt2x00pci.h"
  42 #include "rt2400pci.h"
  43
  44 /*
  45  * Register access.
  46  * All access to the CSR registers will go through the methods
  47  * rt2x00pci_register_read and rt2x00pci_register_write.
  48  * BBP and RF register require indirect register access,
  49  * and use the CSR registers BBPCSR and RFCSR to achieve this.
  50  * These indirect registers work with busy bits,
  51  * and we will try maximal REGISTER_BUSY_COUNT times to access
  52  * the register while taking a REGISTER_BUSY_DELAY us delay
  53  * between each attampt. When the busy bit is still set at that time,
  54  * the access attempt is considered to have failed,
  55  * and we will print an error.
  56  */
  57 static u32 rt2400pci_bbp_check(const struct rt2x00_dev *rt2x00dev)
  58 {
  59         u32 reg;
  60         unsigned int i;
  61
  62         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
  63                 rt2x00pci_register_read(rt2x00dev, BBPCSR, &reg);
  64                 if (!rt2x00_get_field32(reg, BBPCSR_BUSY))
  65                         break;
  66                 udelay(REGISTER_BUSY_DELAY);
  67         }
  68
  69         return reg;
  70 }
  71
  72 static void rt2400pci_bbp_write(const struct rt2x00_dev *rt2x00dev,
  73                                 const unsigned int word, const u8 value)
  74 {
  75         u32 reg;
  76
  77         /*
  78          * Wait until the BBP becomes ready.
  79          */
  80         reg = rt2400pci_bbp_check(rt2x00dev);
  81         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
  82                 ERROR(rt2x00dev, "BBPCSR register busy. Write failed.\n");
  83                 return;
  84         }
  85
  86         /*
  87          * Write the data into the BBP.
  88          */
  89         reg = 0;
  90         rt2x00_set_field32(&reg, BBPCSR_VALUE, value);
  91         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
  92         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
  93         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 1);
  94
  95         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
  96 }
  97
  98 static void rt2400pci_bbp_read(const struct rt2x00_dev *rt2x00dev,
  99                                const unsigned int word, u8 *value)
 100 {
 101         u32 reg;
 102
 103         /*
 104          * Wait until the BBP becomes ready.
 105          */
 106         reg = rt2400pci_bbp_check(rt2x00dev);
 107         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
 108                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
 109                 return;
 110         }
 111
 112         /*
 113          * Write the request into the BBP.
 114          */
 115         reg = 0;
 116         rt2x00_set_field32(&reg, BBPCSR_REGNUM, word);
 117         rt2x00_set_field32(&reg, BBPCSR_BUSY, 1);
 118         rt2x00_set_field32(&reg, BBPCSR_WRITE_CONTROL, 0);
 119
 120         rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
 121
 122         /*
 123          * Wait until the BBP becomes ready.
 124          */
 125         reg = rt2400pci_bbp_check(rt2x00dev);
 126         if (rt2x00_get_field32(reg, BBPCSR_BUSY)) {
 127                 ERROR(rt2x00dev, "BBPCSR register busy. Read failed.\n");
 128                 *value = 0xff;
 129                 return;
 130         }
 131
 132         *value = rt2x00_get_field32(reg, BBPCSR_VALUE);
 133 }
 134
 135 static void rt2400pci_rf_write(const struct rt2x00_dev *rt2x00dev,
 136                                const unsigned int word, const u32 value)
 137 {
 138         u32 reg;
 139         unsigned int i;
 140
 141         if (!word)
 142                 return;
 143
 144         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 145                 rt2x00pci_register_read(rt2x00dev, RFCSR, &reg);
 146                 if (!rt2x00_get_field32(reg, RFCSR_BUSY))
 147                         goto rf_write;
 148                 udelay(REGISTER_BUSY_DELAY);
 149         }
 150
 151         ERROR(rt2x00dev, "RFCSR register busy. Write failed.\n");
 152         return;
 153
 154 rf_write:
 155         reg = 0;
 156         rt2x00_set_field32(&reg, RFCSR_VALUE, value);
 157         rt2x00_set_field32(&reg, RFCSR_NUMBER_OF_BITS, 20);
 158         rt2x00_set_field32(&reg, RFCSR_IF_SELECT, 0);
 159         rt2x00_set_field32(&reg, RFCSR_BUSY, 1);
 160
 161         rt2x00pci_register_write(rt2x00dev, RFCSR, reg);
 162         rt2x00_rf_write(rt2x00dev, word, value);
 163 }
 164
 165 static void rt2400pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
 166 {
 167         struct rt2x00_dev *rt2x00dev = eeprom->data;
 168         u32 reg;
 169
 170         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
 171
 172         eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN);
 173         eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT);
 174         eeprom->reg_data_clock =
 175             !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK);
 176         eeprom->reg_chip_select =
 177             !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT);
 178 }
 179
 180 static void rt2400pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
 181 {
 182         struct rt2x00_dev *rt2x00dev = eeprom->data;
 183         u32 reg = 0;
 184
 185         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in);
 186         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out);
 187         rt2x00_set_field32(&reg, CSR21_EEPROM_DATA_CLOCK,
 188                            !!eeprom->reg_data_clock);
 189         rt2x00_set_field32(&reg, CSR21_EEPROM_CHIP_SELECT,
 190                            !!eeprom->reg_chip_select);
 191
 192         rt2x00pci_register_write(rt2x00dev, CSR21, reg);
 193 }
 194
 195 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
 196 #define CSR_OFFSET(__word)      ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
 197
 198 static void rt2400pci_read_csr(const struct rt2x00_dev *rt2x00dev,
 199                                const unsigned int word, u32 *data)
 200 {
 201         rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
 202 }
 203
 204 static void rt2400pci_write_csr(const struct rt2x00_dev *rt2x00dev,
 205                                 const unsigned int word, u32 data)
 206 {
 207         rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
 208 }
 209
 210 static const struct rt2x00debug rt2400pci_rt2x00debug = {
 211         .owner  = THIS_MODULE,
 212         .csr    = {
 213                 .read           = rt2400pci_read_csr,
 214                 .write          = rt2400pci_write_csr,
 215                 .word_size      = sizeof(u32),
 216                 .word_count     = CSR_REG_SIZE / sizeof(u32),
 217         },
 218         .eeprom = {
 219                 .read           = rt2x00_eeprom_read,
 220                 .write          = rt2x00_eeprom_write,
 221                 .word_size      = sizeof(u16),
 222                 .word_count     = EEPROM_SIZE / sizeof(u16),
 223         },
 224         .bbp    = {
 225                 .read           = rt2400pci_bbp_read,
 226                 .write          = rt2400pci_bbp_write,
 227                 .word_size      = sizeof(u8),
 228                 .word_count     = BBP_SIZE / sizeof(u8),
 229         },
 230         .rf     = {
 231                 .read           = rt2x00_rf_read,
 232                 .write          = rt2400pci_rf_write,
 233                 .word_size      = sizeof(u32),
 234                 .word_count     = RF_SIZE / sizeof(u32),
 235         },
 236 };
 237 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
 238
 239 #ifdef CONFIG_RT2400PCI_RFKILL
 240 static int rt2400pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
 241 {
 242         u32 reg;
 243
 244         rt2x00pci_register_read(rt2x00dev, GPIOCSR, &reg);
 245         return rt2x00_get_field32(reg, GPIOCSR_BIT0);
 246 }
 247 #else
 248 #define rt2400pci_rfkill_poll   NULL
 249 #endif /* CONFIG_RT2400PCI_RFKILL */
 250
 251 /*
 252  * Configuration handlers.
 253  */
 254 static void rt2400pci_config_mac_addr(struct rt2x00_dev *rt2x00dev,
 255                                       __le32 *mac)
 256 {
 257         rt2x00pci_register_multiwrite(rt2x00dev, CSR3, mac,
 258                                       (2 * sizeof(__le32)));
 259 }
 260
 261 static void rt2400pci_config_bssid(struct rt2x00_dev *rt2x00dev,
 262                                    __le32 *bssid)
 263 {
 264         rt2x00pci_register_multiwrite(rt2x00dev, CSR5, bssid,
 265                                       (2 * sizeof(__le32)));
 266 }
 267
 268 static void rt2400pci_config_type(struct rt2x00_dev *rt2x00dev, const int type,
 269                                   const int tsf_sync)
 270 {
 271         u32 reg;
 272
 273         rt2x00pci_register_write(rt2x00dev, CSR14, 0);
 274
 275         /*
 276          * Enable beacon config
 277          */
 278         rt2x00pci_register_read(rt2x00dev, BCNCSR1, &reg);
 279         rt2x00_set_field32(&reg, BCNCSR1_PRELOAD,
 280                            PREAMBLE + get_duration(IEEE80211_HEADER, 20));
 281         rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
 282
 283         /*
 284          * Enable synchronisation.
 285          */
 286         rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
 287         rt2x00_set_field32(&reg, CSR14_TSF_COUNT, 1);
 288         rt2x00_set_field32(&reg, CSR14_TBCN, 1);
 289         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 0);
 290         rt2x00_set_field32(&reg, CSR14_TSF_SYNC, tsf_sync);
 291         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
 292 }
 293
 294 static void rt2400pci_config_preamble(struct rt2x00_dev *rt2x00dev,
 295                                       const int short_preamble,
 296                                       const int ack_timeout,
 297                                       const int ack_consume_time)
 298 {
 299         int preamble_mask;
 300         u32 reg;
 301
 302         /*
 303          * When short preamble is enabled, we should set bit 0x08
 304          */
 305         preamble_mask = short_preamble << 3;
 306
 307         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 308         rt2x00_set_field32(&reg, TXCSR1_ACK_TIMEOUT, ack_timeout);
 309         rt2x00_set_field32(&reg, TXCSR1_ACK_CONSUME_TIME, ack_consume_time);
 310         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 311
 312         rt2x00pci_register_read(rt2x00dev, ARCSR2, &reg);
 313         rt2x00_set_field32(&reg, ARCSR2_SIGNAL, 0x00 | preamble_mask);
 314         rt2x00_set_field32(&reg, ARCSR2_SERVICE, 0x04);
 315         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
 316         rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
 317
 318         rt2x00pci_register_read(rt2x00dev, ARCSR3, &reg);
 319         rt2x00_set_field32(&reg, ARCSR3_SIGNAL, 0x01 | preamble_mask);
 320         rt2x00_set_field32(&reg, ARCSR3_SERVICE, 0x04);
 321         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
 322         rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
 323
 324         rt2x00pci_register_read(rt2x00dev, ARCSR4, &reg);
 325         rt2x00_set_field32(&reg, ARCSR4_SIGNAL, 0x02 | preamble_mask);
 326         rt2x00_set_field32(&reg, ARCSR4_SERVICE, 0x04);
 327         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
 328         rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
 329
 330         rt2x00pci_register_read(rt2x00dev, ARCSR5, &reg);
 331         rt2x00_set_field32(&reg, ARCSR5_SIGNAL, 0x03 | preamble_mask);
 332         rt2x00_set_field32(&reg, ARCSR5_SERVICE, 0x84);
 333         rt2x00_set_field32(&reg, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
 334         rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
 335 }
 336
 337 static void rt2400pci_config_phymode(struct rt2x00_dev *rt2x00dev,
 338                                      const int basic_rate_mask)
 339 {
 340         rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
 341 }
 342
 343 static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
 344                                      struct rf_channel *rf)
 345 {
 346         /*
 347          * Switch on tuning bits.
 348          */
 349         rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
 350         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
 351
 352         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 353         rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
 354         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 355
 356         /*
 357          * RF2420 chipset don't need any additional actions.
 358          */
 359         if (rt2x00_rf(&rt2x00dev->chip, RF2420))
 360                 return;
 361
 362         /*
 363          * For the RT2421 chipsets we need to write an invalid
 364          * reference clock rate to activate auto_tune.
 365          * After that we set the value back to the correct channel.
 366          */
 367         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 368         rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
 369         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 370
 371         msleep(1);
 372
 373         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 374         rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
 375         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 376
 377         msleep(1);
 378
 379         /*
 380          * Switch off tuning bits.
 381          */
 382         rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
 383         rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
 384
 385         rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
 386         rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
 387
 388         /*
 389          * Clear false CRC during channel switch.
 390          */
 391         rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
 392 }
 393
 394 static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
 395 {
 396         rt2400pci_bbp_write(rt2x00dev, 3, TXPOWER_TO_DEV(txpower));
 397 }
 398
 399 static void rt2400pci_config_antenna(struct rt2x00_dev *rt2x00dev,
 400                                      struct antenna_setup *ant)
 401 {
 402         u8 r1;
 403         u8 r4;
 404
 405         rt2400pci_bbp_read(rt2x00dev, 4, &r4);
 406         rt2400pci_bbp_read(rt2x00dev, 1, &r1);
 407
 408         /*
 409          * Configure the TX antenna.
 410          */
 411         switch (ant->tx) {
 412         case ANTENNA_HW_DIVERSITY:
 413                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
 414                 break;
 415         case ANTENNA_A:
 416                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
 417                 break;
 418         case ANTENNA_SW_DIVERSITY:
 419                 /*
 420                  * NOTE: We should never come here because rt2x00lib is
 421                  * supposed to catch this and send us the correct antenna
 422                  * explicitely. However we are nog going to bug about this.
 423                  * Instead, just default to antenna B.
 424                  */
 425         case ANTENNA_B:
 426                 rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
 427                 break;
 428         }
 429
 430         /*
 431          * Configure the RX antenna.
 432          */
 433         switch (ant->rx) {
 434         case ANTENNA_HW_DIVERSITY:
 435                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
 436                 break;
 437         case ANTENNA_A:
 438                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
 439                 break;
 440         case ANTENNA_SW_DIVERSITY:
 441                 /*
 442                  * NOTE: We should never come here because rt2x00lib is
 443                  * supposed to catch this and send us the correct antenna
 444                  * explicitely. However we are nog going to bug about this.
 445                  * Instead, just default to antenna B.
 446                  */
 447         case ANTENNA_B:
 448                 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
 449                 break;
 450         }
 451
 452         rt2400pci_bbp_write(rt2x00dev, 4, r4);
 453         rt2400pci_bbp_write(rt2x00dev, 1, r1);
 454 }
 455
 456 static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev,
 457                                       struct rt2x00lib_conf *libconf)
 458 {
 459         u32 reg;
 460
 461         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 462         rt2x00_set_field32(&reg, CSR11_SLOT_TIME, libconf->slot_time);
 463         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 464
 465         rt2x00pci_register_read(rt2x00dev, CSR18, &reg);
 466         rt2x00_set_field32(&reg, CSR18_SIFS, libconf->sifs);
 467         rt2x00_set_field32(&reg, CSR18_PIFS, libconf->pifs);
 468         rt2x00pci_register_write(rt2x00dev, CSR18, reg);
 469
 470         rt2x00pci_register_read(rt2x00dev, CSR19, &reg);
 471         rt2x00_set_field32(&reg, CSR19_DIFS, libconf->difs);
 472         rt2x00_set_field32(&reg, CSR19_EIFS, libconf->eifs);
 473         rt2x00pci_register_write(rt2x00dev, CSR19, reg);
 474
 475         rt2x00pci_register_read(rt2x00dev, TXCSR1, &reg);
 476         rt2x00_set_field32(&reg, TXCSR1_TSF_OFFSET, IEEE80211_HEADER);
 477         rt2x00_set_field32(&reg, TXCSR1_AUTORESPONDER, 1);
 478         rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
 479
 480         rt2x00pci_register_read(rt2x00dev, CSR12, &reg);
 481         rt2x00_set_field32(&reg, CSR12_BEACON_INTERVAL,
 482                            libconf->conf->beacon_int * 16);
 483         rt2x00_set_field32(&reg, CSR12_CFP_MAX_DURATION,
 484                            libconf->conf->beacon_int * 16);
 485         rt2x00pci_register_write(rt2x00dev, CSR12, reg);
 486 }
 487
 488 static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
 489                              const unsigned int flags,
 490                              struct rt2x00lib_conf *libconf)
 491 {
 492         if (flags & CONFIG_UPDATE_PHYMODE)
 493                 rt2400pci_config_phymode(rt2x00dev, libconf->basic_rates);
 494         if (flags & CONFIG_UPDATE_CHANNEL)
 495                 rt2400pci_config_channel(rt2x00dev, &libconf->rf);
 496         if (flags & CONFIG_UPDATE_TXPOWER)
 497                 rt2400pci_config_txpower(rt2x00dev,
 498                                          libconf->conf->power_level);
 499         if (flags & CONFIG_UPDATE_ANTENNA)
 500                 rt2400pci_config_antenna(rt2x00dev, &libconf->ant);
 501         if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
 502                 rt2400pci_config_duration(rt2x00dev, libconf);
 503 }
 504
 505 static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
 506                                 struct ieee80211_tx_queue_params *params)
 507 {
 508         u32 reg;
 509
 510         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
 511         rt2x00_set_field32(&reg, CSR11_CWMIN, params->cw_min);
 512         rt2x00_set_field32(&reg, CSR11_CWMAX, params->cw_max);
 513         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
 514 }
 515
 516 /*
 517  * LED functions.
 518  */
 519 static void rt2400pci_enable_led(struct rt2x00_dev *rt2x00dev)
 520 {
 521         u32 reg;
 522
 523         rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
 524
 525         rt2x00_set_field32(&reg, LEDCSR_ON_PERIOD, 70);
 526         rt2x00_set_field32(&reg, LEDCSR_OFF_PERIOD, 30);
 527
 528         if (rt2x00dev->led_mode == LED_MODE_TXRX_ACTIVITY) {
 529                 rt2x00_set_field32(&reg, LEDCSR_LINK, 1);
 530                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 0);
 531         } else if (rt2x00dev->led_mode == LED_MODE_ASUS) {
 532                 rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
 533                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 1);
 534         } else {
 535                 rt2x00_set_field32(&reg, LEDCSR_LINK, 1);
 536                 rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 1);
 537         }
 538
 539         rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
 540 }
 541
 542 static void rt2400pci_disable_led(struct rt2x00_dev *rt2x00dev)
 543 {
 544         u32 reg;
 545
 546         rt2x00pci_register_read(rt2x00dev, LEDCSR, &reg);
 547         rt2x00_set_field32(&reg, LEDCSR_LINK, 0);
 548         rt2x00_set_field32(&reg, LEDCSR_ACTIVITY, 0);
 549         rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
 550 }
 551
 552 /*
 553  * Link tuning
 554  */
 555 static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
 556                                  struct link_qual *qual)
 557 {
 558         u32 reg;
 559         u8 bbp;
 560
 561         /*
 562          * Update FCS error count from register.
 563          */
 564         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 565         qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
 566
 567         /*
 568          * Update False CCA count from register.
 569          */
 570         rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
 571         qual->false_cca = bbp;
 572 }
 573
 574 static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
 575 {
 576         rt2400pci_bbp_write(rt2x00dev, 13, 0x08);
 577         rt2x00dev->link.vgc_level = 0x08;
 578 }
 579
 580 static void rt2400pci_link_tuner(struct rt2x00_dev *rt2x00dev)
 581 {
 582         u8 reg;
 583
 584         /*
 585          * The link tuner should not run longer then 60 seconds,
 586          * and should run once every 2 seconds.
 587          */
 588         if (rt2x00dev->link.count > 60 || !(rt2x00dev->link.count & 1))
 589                 return;
 590
 591         /*
 592          * Base r13 link tuning on the false cca count.
 593          */
 594         rt2400pci_bbp_read(rt2x00dev, 13, &reg);
 595
 596         if (rt2x00dev->link.qual.false_cca > 512 && reg < 0x20) {
 597                 rt2400pci_bbp_write(rt2x00dev, 13, ++reg);
 598                 rt2x00dev->link.vgc_level = reg;
 599         } else if (rt2x00dev->link.qual.false_cca < 100 && reg > 0x08) {
 600                 rt2400pci_bbp_write(rt2x00dev, 13, --reg);
 601                 rt2x00dev->link.vgc_level = reg;
 602         }
 603 }
 604
 605 /*
 606  * Initialization functions.
 607  */
 608 static void rt2400pci_init_rxring(struct rt2x00_dev *rt2x00dev)
 609 {
 610         struct data_ring *ring = rt2x00dev->rx;
 611         struct data_desc *rxd;
 612         unsigned int i;
 613         u32 word;
 614
 615         memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
 616
 617         for (i = 0; i < ring->stats.limit; i++) {
 618                 rxd = ring->entry[i].priv;
 619
 620                 rt2x00_desc_read(rxd, 2, &word);
 621                 rt2x00_set_field32(&word, RXD_W2_BUFFER_LENGTH,
 622                                    ring->data_size);
 623                 rt2x00_desc_write(rxd, 2, word);
 624
 625                 rt2x00_desc_read(rxd, 1, &word);
 626                 rt2x00_set_field32(&word, RXD_W1_BUFFER_ADDRESS,
 627                                    ring->entry[i].data_dma);
 628                 rt2x00_desc_write(rxd, 1, word);
 629
 630                 rt2x00_desc_read(rxd, 0, &word);
 631                 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
 632                 rt2x00_desc_write(rxd, 0, word);
 633         }
 634
 635         rt2x00_ring_index_clear(rt2x00dev->rx);
 636 }
 637
 638 static void rt2400pci_init_txring(struct rt2x00_dev *rt2x00dev, const int queue)
 639 {
 640         struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
 641         struct data_desc *txd;
 642         unsigned int i;
 643         u32 word;
 644
 645         memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
 646
 647         for (i = 0; i < ring->stats.limit; i++) {
 648                 txd = ring->entry[i].priv;
 649
 650                 rt2x00_desc_read(txd, 1, &word);
 651                 rt2x00_set_field32(&word, TXD_W1_BUFFER_ADDRESS,
 652                                    ring->entry[i].data_dma);
 653                 rt2x00_desc_write(txd, 1, word);
 654
 655                 rt2x00_desc_read(txd, 2, &word);
 656                 rt2x00_set_field32(&word, TXD_W2_BUFFER_LENGTH,
 657                                    ring->data_size);
 658                 rt2x00_desc_write(txd, 2, word);
 659
 660                 rt2x00_desc_read(txd, 0, &word);
 661                 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
 662                 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
 663                 rt2x00_desc_write(txd, 0, word);
 664         }
 665
 666         rt2x00_ring_index_clear(ring);
 667 }
 668
 669 static int rt2400pci_init_rings(struct rt2x00_dev *rt2x00dev)
 670 {
 671         u32 reg;
 672
 673         /*
 674          * Initialize rings.
 675          */
 676         rt2400pci_init_rxring(rt2x00dev);
 677         rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
 678         rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
 679         rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
 680         rt2400pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
 681
 682         /*
 683          * Initialize registers.
 684          */
 685         rt2x00pci_register_read(rt2x00dev, TXCSR2, &reg);
 686         rt2x00_set_field32(&reg, TXCSR2_TXD_SIZE,
 687                            rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size);
 688         rt2x00_set_field32(&reg, TXCSR2_NUM_TXD,
 689                            rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit);
 690         rt2x00_set_field32(&reg, TXCSR2_NUM_ATIM,
 691                            rt2x00dev->bcn[1].stats.limit);
 692         rt2x00_set_field32(&reg, TXCSR2_NUM_PRIO,
 693                            rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit);
 694         rt2x00pci_register_write(rt2x00dev, TXCSR2, reg);
 695
 696         rt2x00pci_register_read(rt2x00dev, TXCSR3, &reg);
 697         rt2x00_set_field32(&reg, TXCSR3_TX_RING_REGISTER,
 698                            rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma);
 699         rt2x00pci_register_write(rt2x00dev, TXCSR3, reg);
 700
 701         rt2x00pci_register_read(rt2x00dev, TXCSR5, &reg);
 702         rt2x00_set_field32(&reg, TXCSR5_PRIO_RING_REGISTER,
 703                            rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma);
 704         rt2x00pci_register_write(rt2x00dev, TXCSR5, reg);
 705
 706         rt2x00pci_register_read(rt2x00dev, TXCSR4, &reg);
 707         rt2x00_set_field32(&reg, TXCSR4_ATIM_RING_REGISTER,
 708                            rt2x00dev->bcn[1].data_dma);
 709         rt2x00pci_register_write(rt2x00dev, TXCSR4, reg);
 710
 711         rt2x00pci_register_read(rt2x00dev, TXCSR6, &reg);
 712         rt2x00_set_field32(&reg, TXCSR6_BEACON_RING_REGISTER,
 713                            rt2x00dev->bcn[0].data_dma);
 714         rt2x00pci_register_write(rt2x00dev, TXCSR6, reg);
 715
 716         rt2x00pci_register_read(rt2x00dev, RXCSR1, &reg);
 717         rt2x00_set_field32(&reg, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size);
 718         rt2x00_set_field32(&reg, RXCSR1_NUM_RXD, rt2x00dev->rx->stats.limit);
 719         rt2x00pci_register_write(rt2x00dev, RXCSR1, reg);
 720
 721         rt2x00pci_register_read(rt2x00dev, RXCSR2, &reg);
 722         rt2x00_set_field32(&reg, RXCSR2_RX_RING_REGISTER,
 723                            rt2x00dev->rx->data_dma);
 724         rt2x00pci_register_write(rt2x00dev, RXCSR2, reg);
 725
 726         return 0;
 727 }
 728
 729 static int rt2400pci_init_registers(struct rt2x00_dev *rt2x00dev)
 730 {
 731         u32 reg;
 732
 733         rt2x00pci_register_write(rt2x00dev, PSCSR0, 0x00020002);
 734         rt2x00pci_register_write(rt2x00dev, PSCSR1, 0x00000002);
 735         rt2x00pci_register_write(rt2x00dev, PSCSR2, 0x00023f20);
 736         rt2x00pci_register_write(rt2x00dev, PSCSR3, 0x00000002);
 737
 738         rt2x00pci_register_read(rt2x00dev, TIMECSR, &reg);
 739         rt2x00_set_field32(&reg, TIMECSR_US_COUNT, 33);
 740         rt2x00_set_field32(&reg, TIMECSR_US_64_COUNT, 63);
 741         rt2x00_set_field32(&reg, TIMECSR_BEACON_EXPECT, 0);
 742         rt2x00pci_register_write(rt2x00dev, TIMECSR, reg);
 743
 744         rt2x00pci_register_read(rt2x00dev, CSR9, &reg);
 745         rt2x00_set_field32(&reg, CSR9_MAX_FRAME_UNIT,
 746                            (rt2x00dev->rx->data_size / 128));
 747         rt2x00pci_register_write(rt2x00dev, CSR9, reg);
 748
 749         rt2x00pci_register_write(rt2x00dev, CNT3, 0x3f080000);
 750
 751         rt2x00pci_register_read(rt2x00dev, ARCSR0, &reg);
 752         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA0, 133);
 753         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID0, 134);
 754         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_DATA1, 136);
 755         rt2x00_set_field32(&reg, ARCSR0_AR_BBP_ID1, 135);
 756         rt2x00pci_register_write(rt2x00dev, ARCSR0, reg);
 757
 758         rt2x00pci_register_read(rt2x00dev, RXCSR3, &reg);
 759         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0, 3); /* Tx power.*/
 760         rt2x00_set_field32(&reg, RXCSR3_BBP_ID0_VALID, 1);
 761         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1, 32); /* Signal */
 762         rt2x00_set_field32(&reg, RXCSR3_BBP_ID1_VALID, 1);
 763         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2, 36); /* Rssi */
 764         rt2x00_set_field32(&reg, RXCSR3_BBP_ID2_VALID, 1);
 765         rt2x00pci_register_write(rt2x00dev, RXCSR3, reg);
 766
 767         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0x3f3b3100);
 768
 769         if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
 770                 return -EBUSY;
 771
 772         rt2x00pci_register_write(rt2x00dev, MACCSR0, 0x00217223);
 773         rt2x00pci_register_write(rt2x00dev, MACCSR1, 0x00235518);
 774
 775         rt2x00pci_register_read(rt2x00dev, MACCSR2, &reg);
 776         rt2x00_set_field32(&reg, MACCSR2_DELAY, 64);
 777         rt2x00pci_register_write(rt2x00dev, MACCSR2, reg);
 778
 779         rt2x00pci_register_read(rt2x00dev, RALINKCSR, &reg);
 780         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA0, 17);
 781         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID0, 154);
 782         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_DATA1, 0);
 783         rt2x00_set_field32(&reg, RALINKCSR_AR_BBP_ID1, 154);
 784         rt2x00pci_register_write(rt2x00dev, RALINKCSR, reg);
 785
 786         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 787         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 1);
 788         rt2x00_set_field32(&reg, CSR1_BBP_RESET, 0);
 789         rt2x00_set_field32(&reg, CSR1_HOST_READY, 0);
 790         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 791
 792         rt2x00pci_register_read(rt2x00dev, CSR1, &reg);
 793         rt2x00_set_field32(&reg, CSR1_SOFT_RESET, 0);
 794         rt2x00_set_field32(&reg, CSR1_HOST_READY, 1);
 795         rt2x00pci_register_write(rt2x00dev, CSR1, reg);
 796
 797         /*
 798          * We must clear the FCS and FIFO error count.
 799          * These registers are cleared on read,
 800          * so we may pass a useless variable to store the value.
 801          */
 802         rt2x00pci_register_read(rt2x00dev, CNT0, &reg);
 803         rt2x00pci_register_read(rt2x00dev, CNT4, &reg);
 804
 805         return 0;
 806 }
 807
 808 static int rt2400pci_init_bbp(struct rt2x00_dev *rt2x00dev)
 809 {
 810         unsigned int i;
 811         u16 eeprom;
 812         u8 reg_id;
 813         u8 value;
 814
 815         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 816                 rt2400pci_bbp_read(rt2x00dev, 0, &value);
 817                 if ((value != 0xff) && (value != 0x00))
 818                         goto continue_csr_init;
 819                 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
 820                 udelay(REGISTER_BUSY_DELAY);
 821         }
 822
 823         ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
 824         return -EACCES;
 825
 826 continue_csr_init:
 827         rt2400pci_bbp_write(rt2x00dev, 1, 0x00);
 828         rt2400pci_bbp_write(rt2x00dev, 3, 0x27);
 829         rt2400pci_bbp_write(rt2x00dev, 4, 0x08);
 830         rt2400pci_bbp_write(rt2x00dev, 10, 0x0f);
 831         rt2400pci_bbp_write(rt2x00dev, 15, 0x72);
 832         rt2400pci_bbp_write(rt2x00dev, 16, 0x74);
 833         rt2400pci_bbp_write(rt2x00dev, 17, 0x20);
 834         rt2400pci_bbp_write(rt2x00dev, 18, 0x72);
 835         rt2400pci_bbp_write(rt2x00dev, 19, 0x0b);
 836         rt2400pci_bbp_write(rt2x00dev, 20, 0x00);
 837         rt2400pci_bbp_write(rt2x00dev, 28, 0x11);
 838         rt2400pci_bbp_write(rt2x00dev, 29, 0x04);
 839         rt2400pci_bbp_write(rt2x00dev, 30, 0x21);
 840         rt2400pci_bbp_write(rt2x00dev, 31, 0x00);
 841
 842         DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
 843         for (i = 0; i < EEPROM_BBP_SIZE; i++) {
 844                 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
 845
 846                 if (eeprom != 0xffff && eeprom != 0x0000) {
 847                         reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
 848                         value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
 849                         DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
 850                               reg_id, value);
 851                         rt2400pci_bbp_write(rt2x00dev, reg_id, value);
 852                 }
 853         }
 854         DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
 855
 856         return 0;
 857 }
 858
 859 /*
 860  * Device state switch handlers.
 861  */
 862 static void rt2400pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
 863                                 enum dev_state state)
 864 {
 865         u32 reg;
 866
 867         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
 868         rt2x00_set_field32(&reg, RXCSR0_DISABLE_RX,
 869                            state == STATE_RADIO_RX_OFF);
 870         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
 871 }
 872
 873 static void rt2400pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
 874                                  enum dev_state state)
 875 {
 876         int mask = (state == STATE_RADIO_IRQ_OFF);
 877         u32 reg;
 878
 879         /*
 880          * When interrupts are being enabled, the interrupt registers
 881          * should clear the register to assure a clean state.
 882          */
 883         if (state == STATE_RADIO_IRQ_ON) {
 884                 rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
 885                 rt2x00pci_register_write(rt2x00dev, CSR7, reg);
 886         }
 887
 888         /*
 889          * Only toggle the interrupts bits we are going to use.
 890          * Non-checked interrupt bits are disabled by default.
 891          */
 892         rt2x00pci_register_read(rt2x00dev, CSR8, &reg);
 893         rt2x00_set_field32(&reg, CSR8_TBCN_EXPIRE, mask);
 894         rt2x00_set_field32(&reg, CSR8_TXDONE_TXRING, mask);
 895         rt2x00_set_field32(&reg, CSR8_TXDONE_ATIMRING, mask);
 896         rt2x00_set_field32(&reg, CSR8_TXDONE_PRIORING, mask);
 897         rt2x00_set_field32(&reg, CSR8_RXDONE, mask);
 898         rt2x00pci_register_write(rt2x00dev, CSR8, reg);
 899 }
 900
 901 static int rt2400pci_enable_radio(struct rt2x00_dev *rt2x00dev)
 902 {
 903         /*
 904          * Initialize all registers.
 905          */
 906         if (rt2400pci_init_rings(rt2x00dev) ||
 907             rt2400pci_init_registers(rt2x00dev) ||
 908             rt2400pci_init_bbp(rt2x00dev)) {
 909                 ERROR(rt2x00dev, "Register initialization failed.\n");
 910                 return -EIO;
 911         }
 912
 913         /*
 914          * Enable interrupts.
 915          */
 916         rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
 917
 918         /*
 919          * Enable LED
 920          */
 921         rt2400pci_enable_led(rt2x00dev);
 922
 923         return 0;
 924 }
 925
 926 static void rt2400pci_disable_radio(struct rt2x00_dev *rt2x00dev)
 927 {
 928         u32 reg;
 929
 930         /*
 931          * Disable LED
 932          */
 933         rt2400pci_disable_led(rt2x00dev);
 934
 935         rt2x00pci_register_write(rt2x00dev, PWRCSR0, 0);
 936
 937         /*
 938          * Disable synchronisation.
 939          */
 940         rt2x00pci_register_write(rt2x00dev, CSR14, 0);
 941
 942         /*
 943          * Cancel RX and TX.
 944          */
 945         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
 946         rt2x00_set_field32(&reg, TXCSR0_ABORT, 1);
 947         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
 948
 949         /*
 950          * Disable interrupts.
 951          */
 952         rt2400pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
 953 }
 954
 955 static int rt2400pci_set_state(struct rt2x00_dev *rt2x00dev,
 956                                enum dev_state state)
 957 {
 958         u32 reg;
 959         unsigned int i;
 960         char put_to_sleep;
 961         char bbp_state;
 962         char rf_state;
 963
 964         put_to_sleep = (state != STATE_AWAKE);
 965
 966         rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
 967         rt2x00_set_field32(&reg, PWRCSR1_SET_STATE, 1);
 968         rt2x00_set_field32(&reg, PWRCSR1_BBP_DESIRE_STATE, state);
 969         rt2x00_set_field32(&reg, PWRCSR1_RF_DESIRE_STATE, state);
 970         rt2x00_set_field32(&reg, PWRCSR1_PUT_TO_SLEEP, put_to_sleep);
 971         rt2x00pci_register_write(rt2x00dev, PWRCSR1, reg);
 972
 973         /*
 974          * Device is not guaranteed to be in the requested state yet.
 975          * We must wait until the register indicates that the
 976          * device has entered the correct state.
 977          */
 978         for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
 979                 rt2x00pci_register_read(rt2x00dev, PWRCSR1, &reg);
 980                 bbp_state = rt2x00_get_field32(reg, PWRCSR1_BBP_CURR_STATE);
 981                 rf_state = rt2x00_get_field32(reg, PWRCSR1_RF_CURR_STATE);
 982                 if (bbp_state == state && rf_state == state)
 983                         return 0;
 984                 msleep(10);
 985         }
 986
 987         NOTICE(rt2x00dev, "Device failed to enter state %d, "
 988                "current device state: bbp %d and rf %d.\n",
 989                state, bbp_state, rf_state);
 990
 991         return -EBUSY;
 992 }
 993
 994 static int rt2400pci_set_device_state(struct rt2x00_dev *rt2x00dev,
 995                                       enum dev_state state)
 996 {
 997         int retval = 0;
 998
 999         switch (state) {
1000         case STATE_RADIO_ON:
1001                 retval = rt2400pci_enable_radio(rt2x00dev);
1002                 break;
1003         case STATE_RADIO_OFF:
1004                 rt2400pci_disable_radio(rt2x00dev);
1005                 break;
1006         case STATE_RADIO_RX_ON:
1007         case STATE_RADIO_RX_OFF:
1008                 rt2400pci_toggle_rx(rt2x00dev, state);
1009                 break;
1010         case STATE_DEEP_SLEEP:
1011         case STATE_SLEEP:
1012         case STATE_STANDBY:
1013         case STATE_AWAKE:
1014                 retval = rt2400pci_set_state(rt2x00dev, state);
1015                 break;
1016         default:
1017                 retval = -ENOTSUPP;
1018                 break;
1019         }
1020
1021         return retval;
1022 }
1023
1024 /*
1025  * TX descriptor initialization
1026  */
1027 static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1028                                     struct data_desc *txd,
1029                                     struct txdata_entry_desc *desc,
1030                                     struct ieee80211_hdr *ieee80211hdr,
1031                                     unsigned int length,
1032                                     struct ieee80211_tx_control *control)
1033 {
1034         u32 word;
1035         u32 signal = 0;
1036         u32 service = 0;
1037         u32 length_high = 0;
1038         u32 length_low = 0;
1039
1040         /*
1041          * The PLCP values should be treated as if they
1042          * were BBP values.
1043          */
1044         rt2x00_set_field32(&signal, BBPCSR_VALUE, desc->signal);
1045         rt2x00_set_field32(&signal, BBPCSR_REGNUM, 5);
1046         rt2x00_set_field32(&signal, BBPCSR_BUSY, 1);
1047
1048         rt2x00_set_field32(&service, BBPCSR_VALUE, desc->service);
1049         rt2x00_set_field32(&service, BBPCSR_REGNUM, 6);
1050         rt2x00_set_field32(&service, BBPCSR_BUSY, 1);
1051
1052         rt2x00_set_field32(&length_high, BBPCSR_VALUE, desc->length_high);
1053         rt2x00_set_field32(&length_high, BBPCSR_REGNUM, 7);
1054         rt2x00_set_field32(&length_high, BBPCSR_BUSY, 1);
1055
1056         rt2x00_set_field32(&length_low, BBPCSR_VALUE, desc->length_low);
1057         rt2x00_set_field32(&length_low, BBPCSR_REGNUM, 8);
1058         rt2x00_set_field32(&length_low, BBPCSR_BUSY, 1);
1059
1060         /*
1061          * Start writing the descriptor words.
1062          */
1063         rt2x00_desc_read(txd, 2, &word);
1064         rt2x00_set_field32(&word, TXD_W2_DATABYTE_COUNT, length);
1065         rt2x00_desc_write(txd, 2, word);
1066
1067         rt2x00_desc_read(txd, 3, &word);
1068         rt2x00_set_field32(&word, TXD_W3_PLCP_SIGNAL, signal);
1069         rt2x00_set_field32(&word, TXD_W3_PLCP_SERVICE, service);
1070         rt2x00_desc_write(txd, 3, word);
1071
1072         rt2x00_desc_read(txd, 4, &word);
1073         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_LOW, length_low);
1074         rt2x00_set_field32(&word, TXD_W4_PLCP_LENGTH_HIGH, length_high);
1075         rt2x00_desc_write(txd, 4, word);
1076
1077         rt2x00_desc_read(txd, 0, &word);
1078         rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1079         rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1080         rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1081                            test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
1082         rt2x00_set_field32(&word, TXD_W0_ACK,
1083                            !(control->flags & IEEE80211_TXCTL_NO_ACK));
1084         rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1085                            test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
1086         rt2x00_set_field32(&word, TXD_W0_RTS,
1087                            test_bit(ENTRY_TXD_RTS_FRAME, &desc->flags));
1088         rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
1089         rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1090                            !!(control->flags &
1091                               IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1092         rt2x00_desc_write(txd, 0, word);
1093 }
1094
1095 /*
1096  * TX data initialization
1097  */
1098 static void rt2400pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1099                                     unsigned int queue)
1100 {
1101         u32 reg;
1102
1103         if (queue == IEEE80211_TX_QUEUE_BEACON) {
1104                 rt2x00pci_register_read(rt2x00dev, CSR14, &reg);
1105                 if (!rt2x00_get_field32(reg, CSR14_BEACON_GEN)) {
1106                         rt2x00_set_field32(&reg, CSR14_BEACON_GEN, 1);
1107                         rt2x00pci_register_write(rt2x00dev, CSR14, reg);
1108                 }
1109                 return;
1110         }
1111
1112         rt2x00pci_register_read(rt2x00dev, TXCSR0, &reg);
1113         if (queue == IEEE80211_TX_QUEUE_DATA0)
1114                 rt2x00_set_field32(&reg, TXCSR0_KICK_PRIO, 1);
1115         else if (queue == IEEE80211_TX_QUEUE_DATA1)
1116                 rt2x00_set_field32(&reg, TXCSR0_KICK_TX, 1);
1117         else if (queue == IEEE80211_TX_QUEUE_AFTER_BEACON)
1118                 rt2x00_set_field32(&reg, TXCSR0_KICK_ATIM, 1);
1119         rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
1120 }
1121
1122 /*
1123  * RX control handlers
1124  */
1125 static void rt2400pci_fill_rxdone(struct data_entry *entry,
1126                                   struct rxdata_entry_desc *desc)
1127 {
1128         struct data_desc *rxd = entry->priv;
1129         u32 word0;
1130         u32 word2;
1131
1132         rt2x00_desc_read(rxd, 0, &word0);
1133         rt2x00_desc_read(rxd, 2, &word2);
1134
1135         desc->flags = 0;
1136         if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1137                 desc->flags |= RX_FLAG_FAILED_FCS_CRC;
1138         if (rt2x00_get_field32(word0, RXD_W0_PHYSICAL_ERROR))
1139                 desc->flags |= RX_FLAG_FAILED_PLCP_CRC;
1140
1141         /*
1142          * Obtain the status about this packet.
1143          */
1144         desc->signal = rt2x00_get_field32(word2, RXD_W2_SIGNAL);
1145         desc->rssi = rt2x00_get_field32(word2, RXD_W2_RSSI) -
1146             entry->ring->rt2x00dev->rssi_offset;
1147         desc->ofdm = 0;
1148         desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1149 }
1150
1151 /*
1152  * Interrupt functions.
1153  */
1154 static void rt2400pci_txdone(struct rt2x00_dev *rt2x00dev, const int queue)
1155 {
1156         struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
1157         struct data_entry *entry;
1158         struct data_desc *txd;
1159         u32 word;
1160         int tx_status;
1161         int retry;
1162
1163         while (!rt2x00_ring_empty(ring)) {
1164                 entry = rt2x00_get_data_entry_done(ring);
1165                 txd = entry->priv;
1166                 rt2x00_desc_read(txd, 0, &word);
1167
1168                 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1169                     !rt2x00_get_field32(word, TXD_W0_VALID))
1170                         break;
1171
1172                 /*
1173                  * Obtain the status about this packet.
1174                  */
1175                 tx_status = rt2x00_get_field32(word, TXD_W0_RESULT);
1176                 retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
1177
1178                 rt2x00lib_txdone(entry, tx_status, retry);
1179
1180                 /*
1181                  * Make this entry available for reuse.
1182                  */
1183                 entry->flags = 0;
1184                 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1185                 rt2x00_desc_write(txd, 0, word);
1186                 rt2x00_ring_index_done_inc(ring);
1187         }
1188
1189         /*
1190          * If the data ring was full before the txdone handler
1191          * we must make sure the packet queue in the mac80211 stack
1192          * is reenabled when the txdone handler has finished.
1193          */
1194         entry = ring->entry;
1195         if (!rt2x00_ring_full(ring))
1196                 ieee80211_wake_queue(rt2x00dev->hw,
1197                                      entry->tx_status.control.queue);
1198 }
1199
1200 static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
1201 {
1202         struct rt2x00_dev *rt2x00dev = dev_instance;
1203         u32 reg;
1204
1205         /*
1206          * Get the interrupt sources & saved to local variable.
1207          * Write register value back to clear pending interrupts.
1208          */
1209         rt2x00pci_register_read(rt2x00dev, CSR7, &reg);
1210         rt2x00pci_register_write(rt2x00dev, CSR7, reg);
1211
1212         if (!reg)
1213                 return IRQ_NONE;
1214
1215         if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1216                 return IRQ_HANDLED;
1217
1218         /*
1219          * Handle interrupts, walk through all bits
1220          * and run the tasks, the bits are checked in order of
1221          * priority.
1222          */
1223
1224         /*
1225          * 1 - Beacon timer expired interrupt.
1226          */
1227         if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE))
1228                 rt2x00lib_beacondone(rt2x00dev);
1229
1230         /*
1231          * 2 - Rx ring done interrupt.
1232          */
1233         if (rt2x00_get_field32(reg, CSR7_RXDONE))
1234                 rt2x00pci_rxdone(rt2x00dev);
1235
1236         /*
1237          * 3 - Atim ring transmit done interrupt.
1238          */
1239         if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING))
1240                 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_AFTER_BEACON);
1241
1242         /*
1243          * 4 - Priority ring transmit done interrupt.
1244          */
1245         if (rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING))
1246                 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1247
1248         /*
1249          * 5 - Tx ring transmit done interrupt.
1250          */
1251         if (rt2x00_get_field32(reg, CSR7_TXDONE_TXRING))
1252                 rt2400pci_txdone(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1253
1254         return IRQ_HANDLED;
1255 }
1256
1257 /*
1258  * Device probe functions.
1259  */
1260 static int rt2400pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1261 {
1262         struct eeprom_93cx6 eeprom;
1263         u32 reg;
1264         u16 word;
1265         u8 *mac;
1266
1267         rt2x00pci_register_read(rt2x00dev, CSR21, &reg);
1268
1269         eeprom.data = rt2x00dev;
1270         eeprom.register_read = rt2400pci_eepromregister_read;
1271         eeprom.register_write = rt2400pci_eepromregister_write;
1272         eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ?
1273             PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1274         eeprom.reg_data_in = 0;
1275         eeprom.reg_data_out = 0;
1276         eeprom.reg_data_clock = 0;
1277         eeprom.reg_chip_select = 0;
1278
1279         eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1280                                EEPROM_SIZE / sizeof(u16));
1281
1282         /*
1283          * Start validation of the data that has been read.
1284          */
1285         mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1286         if (!is_valid_ether_addr(mac)) {
1287                 DECLARE_MAC_BUF(macbuf);
1288
1289                 random_ether_addr(mac);
1290                 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
1291         }
1292
1293         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1294         if (word == 0xffff) {
1295                 ERROR(rt2x00dev, "Invalid EEPROM data detected.\n");
1296                 return -EINVAL;
1297         }
1298
1299         return 0;
1300 }
1301
1302 static int rt2400pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
1303 {
1304         u32 reg;
1305         u16 value;
1306         u16 eeprom;
1307
1308         /*
1309          * Read EEPROM word for configuration.
1310          */
1311         rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
1312
1313         /*
1314          * Identify RF chipset.
1315          */
1316         value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
1317         rt2x00pci_register_read(rt2x00dev, CSR0, &reg);
1318         rt2x00_set_chip(rt2x00dev, RT2460, value, reg);
1319
1320         if (!rt2x00_rf(&rt2x00dev->chip, RF2420) &&
1321             !rt2x00_rf(&rt2x00dev->chip, RF2421)) {
1322                 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
1323                 return -ENODEV;
1324         }
1325
1326         /*
1327          * Identify default antenna configuration.
1328          */
1329         rt2x00dev->default_ant.tx =
1330             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
1331         rt2x00dev->default_ant.rx =
1332             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
1333
1334         /*
1335          * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
1336          * I am not 100% sure about this, but the legacy drivers do not
1337          * indicate antenna swapping in software is required when
1338          * diversity is enabled.
1339          */
1340         if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
1341                 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
1342         if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
1343                 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
1344
1345         /*
1346          * Store led mode, for correct led behaviour.
1347          */
1348         rt2x00dev->led_mode =
1349             rt2x00_get_field16(eeprom, EEPROM_ANTENNA_LED_MODE);
1350
1351         /*
1352          * Detect if this device has an hardware controlled radio.
1353          */
1354 #ifdef CONFIG_RT2400PCI_RFKILL
1355         if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
1356                 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
1357 #endif /* CONFIG_RT2400PCI_RFKILL */
1358
1359         /*
1360          * Check if the BBP tuning should be enabled.
1361          */
1362         if (!rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_AGCVGC_TUNING))
1363                 __set_bit(CONFIG_DISABLE_LINK_TUNING, &rt2x00dev->flags);
1364
1365         return 0;
1366 }
1367
1368 /*
1369  * RF value list for RF2420 & RF2421
1370  * Supports: 2.4 GHz
1371  */
1372 static const struct rf_channel rf_vals_bg[] = {
1373         { 1,  0x00022058, 0x000c1fda, 0x00000101, 0 },
1374         { 2,  0x00022058, 0x000c1fee, 0x00000101, 0 },
1375         { 3,  0x00022058, 0x000c2002, 0x00000101, 0 },
1376         { 4,  0x00022058, 0x000c2016, 0x00000101, 0 },
1377         { 5,  0x00022058, 0x000c202a, 0x00000101, 0 },
1378         { 6,  0x00022058, 0x000c203e, 0x00000101, 0 },
1379         { 7,  0x00022058, 0x000c2052, 0x00000101, 0 },
1380         { 8,  0x00022058, 0x000c2066, 0x00000101, 0 },
1381         { 9,  0x00022058, 0x000c207a, 0x00000101, 0 },
1382         { 10, 0x00022058, 0x000c208e, 0x00000101, 0 },
1383         { 11, 0x00022058, 0x000c20a2, 0x00000101, 0 },
1384         { 12, 0x00022058, 0x000c20b6, 0x00000101, 0 },
1385         { 13, 0x00022058, 0x000c20ca, 0x00000101, 0 },
1386         { 14, 0x00022058, 0x000c20fa, 0x00000101, 0 },
1387 };
1388
1389 static void rt2400pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
1390 {
1391         struct hw_mode_spec *spec = &rt2x00dev->spec;
1392         u8 *txpower;
1393         unsigned int i;
1394
1395         /*
1396          * Initialize all hw fields.
1397          */
1398         rt2x00dev->hw->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
1399         rt2x00dev->hw->extra_tx_headroom = 0;
1400         rt2x00dev->hw->max_signal = MAX_SIGNAL;
1401         rt2x00dev->hw->max_rssi = MAX_RX_SSI;
1402         rt2x00dev->hw->queues = 2;
1403
1404         SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
1405         SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
1406                                 rt2x00_eeprom_addr(rt2x00dev,
1407                                                    EEPROM_MAC_ADDR_0));
1408
1409         /*
1410          * Convert tx_power array in eeprom.
1411          */
1412         txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_START);
1413         for (i = 0; i < 14; i++)
1414                 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
1415
1416         /*
1417          * Initialize hw_mode information.
1418          */
1419         spec->num_modes = 1;
1420         spec->num_rates = 4;
1421         spec->tx_power_a = NULL;
1422         spec->tx_power_bg = txpower;
1423         spec->tx_power_default = DEFAULT_TXPOWER;
1424
1425         spec->num_channels = ARRAY_SIZE(rf_vals_bg);
1426         spec->channels = rf_vals_bg;
1427 }
1428
1429 static int rt2400pci_probe_hw(struct rt2x00_dev *rt2x00dev)
1430 {
1431         int retval;
1432
1433         /*
1434          * Allocate eeprom data.
1435          */
1436         retval = rt2400pci_validate_eeprom(rt2x00dev);
1437         if (retval)
1438                 return retval;
1439
1440         retval = rt2400pci_init_eeprom(rt2x00dev);
1441         if (retval)
1442                 return retval;
1443
1444         /*
1445          * Initialize hw specifications.
1446          */
1447         rt2400pci_probe_hw_mode(rt2x00dev);
1448
1449         /*
1450          * This device requires the beacon ring
1451          */
1452         __set_bit(DRIVER_REQUIRE_BEACON_RING, &rt2x00dev->flags);
1453
1454         /*
1455          * Set the rssi offset.
1456          */
1457         rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1458
1459         return 0;
1460 }
1461
1462 /*
1463  * IEEE80211 stack callback functions.
1464  */
1465 static void rt2400pci_configure_filter(struct ieee80211_hw *hw,
1466                                        unsigned int changed_flags,
1467                                        unsigned int *total_flags,
1468                                        int mc_count,
1469                                        struct dev_addr_list *mc_list)
1470 {
1471         struct rt2x00_dev *rt2x00dev = hw->priv;
1472         struct interface *intf = &rt2x00dev->interface;
1473         u32 reg;
1474
1475         /*
1476          * Mask off any flags we are going to ignore from
1477          * the total_flags field.
1478          */
1479         *total_flags &=
1480             FIF_ALLMULTI |
1481             FIF_FCSFAIL |
1482             FIF_PLCPFAIL |
1483             FIF_CONTROL |
1484             FIF_OTHER_BSS |
1485             FIF_PROMISC_IN_BSS;
1486
1487         /*
1488          * Apply some rules to the filters:
1489          * - Some filters imply different filters to be set.
1490          * - Some things we can't filter out at all.
1491          * - Some filters are set based on interface type.
1492          */
1493         *total_flags |= FIF_ALLMULTI;
1494         if (*total_flags & FIF_OTHER_BSS ||
1495             *total_flags & FIF_PROMISC_IN_BSS)
1496                 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
1497         if (is_interface_type(intf, IEEE80211_IF_TYPE_AP))
1498                 *total_flags |= FIF_PROMISC_IN_BSS;
1499
1500         /*
1501          * Check if there is any work left for us.
1502          */
1503         if (intf->filter == *total_flags)
1504                 return;
1505         intf->filter = *total_flags;
1506
1507         /*
1508          * Start configuration steps.
1509          * Note that the version error will always be dropped
1510          * since there is no filter for it at this time.
1511          */
1512         rt2x00pci_register_read(rt2x00dev, RXCSR0, &reg);
1513         rt2x00_set_field32(&reg, RXCSR0_DROP_CRC,
1514                            !(*total_flags & FIF_FCSFAIL));
1515         rt2x00_set_field32(&reg, RXCSR0_DROP_PHYSICAL,
1516                            !(*total_flags & FIF_PLCPFAIL));
1517         rt2x00_set_field32(&reg, RXCSR0_DROP_CONTROL,
1518                            !(*total_flags & FIF_CONTROL));
1519         rt2x00_set_field32(&reg, RXCSR0_DROP_NOT_TO_ME,
1520                            !(*total_flags & FIF_PROMISC_IN_BSS));
1521         rt2x00_set_field32(&reg, RXCSR0_DROP_TODS,
1522                            !(*total_flags & FIF_PROMISC_IN_BSS));
1523         rt2x00_set_field32(&reg, RXCSR0_DROP_VERSION_ERROR, 1);
1524         rt2x00pci_register_write(rt2x00dev, RXCSR0, reg);
1525 }
1526
1527 static int rt2400pci_set_retry_limit(struct ieee80211_hw *hw,
1528                                      u32 short_retry, u32 long_retry)
1529 {
1530         struct rt2x00_dev *rt2x00dev = hw->priv;
1531         u32 reg;
1532
1533         rt2x00pci_register_read(rt2x00dev, CSR11, &reg);
1534         rt2x00_set_field32(&reg, CSR11_LONG_RETRY, long_retry);
1535         rt2x00_set_field32(&reg, CSR11_SHORT_RETRY, short_retry);
1536         rt2x00pci_register_write(rt2x00dev, CSR11, reg);
1537
1538         return 0;
1539 }
1540
1541 static int rt2400pci_conf_tx(struct ieee80211_hw *hw,
1542                              int queue,
1543                              const struct ieee80211_tx_queue_params *params)
1544 {
1545         struct rt2x00_dev *rt2x00dev = hw->priv;
1546
1547         /*
1548          * We don't support variating cw_min and cw_max variables
1549          * per queue. So by default we only configure the TX queue,
1550          * and ignore all other configurations.
1551          */
1552         if (queue != IEEE80211_TX_QUEUE_DATA0)
1553                 return -EINVAL;
1554
1555         if (rt2x00mac_conf_tx(hw, queue, params))
1556                 return -EINVAL;
1557
1558         /*
1559          * Write configuration to register.
1560          */
1561         rt2400pci_config_cw(rt2x00dev, &rt2x00dev->tx->tx_params);
1562
1563         return 0;
1564 }
1565
1566 static u64 rt2400pci_get_tsf(struct ieee80211_hw *hw)
1567 {
1568         struct rt2x00_dev *rt2x00dev = hw->priv;
1569         u64 tsf;
1570         u32 reg;
1571
1572         rt2x00pci_register_read(rt2x00dev, CSR17, &reg);
1573         tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32;
1574         rt2x00pci_register_read(rt2x00dev, CSR16, &reg);
1575         tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER);
1576
1577         return tsf;
1578 }
1579
1580 static void rt2400pci_reset_tsf(struct ieee80211_hw *hw)
1581 {
1582         struct rt2x00_dev *rt2x00dev = hw->priv;
1583
1584         rt2x00pci_register_write(rt2x00dev, CSR16, 0);
1585         rt2x00pci_register_write(rt2x00dev, CSR17, 0);
1586 }
1587
1588 static int rt2400pci_tx_last_beacon(struct ieee80211_hw *hw)
1589 {
1590         struct rt2x00_dev *rt2x00dev = hw->priv;
1591         u32 reg;
1592
1593         rt2x00pci_register_read(rt2x00dev, CSR15, &reg);
1594         return rt2x00_get_field32(reg, CSR15_BEACON_SENT);
1595 }
1596
1597 static const struct ieee80211_ops rt2400pci_mac80211_ops = {
1598         .tx                     = rt2x00mac_tx,
1599         .start                  = rt2x00mac_start,
1600         .stop                   = rt2x00mac_stop,
1601         .add_interface          = rt2x00mac_add_interface,
1602         .remove_interface       = rt2x00mac_remove_interface,
1603         .config                 = rt2x00mac_config,
1604         .config_interface       = rt2x00mac_config_interface,
1605         .configure_filter       = rt2400pci_configure_filter,
1606         .get_stats              = rt2x00mac_get_stats,
1607         .set_retry_limit        = rt2400pci_set_retry_limit,
1608         .erp_ie_changed         = rt2x00mac_erp_ie_changed,
1609         .conf_tx                = rt2400pci_conf_tx,
1610         .get_tx_stats           = rt2x00mac_get_tx_stats,
1611         .get_tsf                = rt2400pci_get_tsf,
1612         .reset_tsf              = rt2400pci_reset_tsf,
1613         .beacon_update          = rt2x00pci_beacon_update,
1614         .tx_last_beacon         = rt2400pci_tx_last_beacon,
1615 };
1616
1617 static const struct rt2x00lib_ops rt2400pci_rt2x00_ops = {
1618         .irq_handler            = rt2400pci_interrupt,
1619         .probe_hw               = rt2400pci_probe_hw,
1620         .initialize             = rt2x00pci_initialize,
1621         .uninitialize           = rt2x00pci_uninitialize,
1622         .set_device_state       = rt2400pci_set_device_state,
1623         .rfkill_poll            = rt2400pci_rfkill_poll,
1624         .link_stats             = rt2400pci_link_stats,
1625         .reset_tuner            = rt2400pci_reset_tuner,
1626         .link_tuner             = rt2400pci_link_tuner,
1627         .write_tx_desc          = rt2400pci_write_tx_desc,
1628         .write_tx_data          = rt2x00pci_write_tx_data,
1629         .kick_tx_queue          = rt2400pci_kick_tx_queue,
1630         .fill_rxdone            = rt2400pci_fill_rxdone,
1631         .config_mac_addr        = rt2400pci_config_mac_addr,
1632         .config_bssid           = rt2400pci_config_bssid,
1633         .config_type            = rt2400pci_config_type,
1634         .config_preamble        = rt2400pci_config_preamble,
1635         .config                 = rt2400pci_config,
1636 };
1637
1638 static const struct rt2x00_ops rt2400pci_ops = {
1639         .name           = DRV_NAME,
1640         .rxd_size       = RXD_DESC_SIZE,
1641         .txd_size       = TXD_DESC_SIZE,
1642         .eeprom_size    = EEPROM_SIZE,
1643         .rf_size        = RF_SIZE,
1644         .lib            = &rt2400pci_rt2x00_ops,
1645         .hw             = &rt2400pci_mac80211_ops,
1646 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1647         .debugfs        = &rt2400pci_rt2x00debug,
1648 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1649 };
1650
1651 /*
1652  * RT2400pci module information.
1653  */
1654 static struct pci_device_id rt2400pci_device_table[] = {
1655         { PCI_DEVICE(0x1814, 0x0101), PCI_DEVICE_DATA(&rt2400pci_ops) },
1656         { 0, }
1657 };
1658
1659 MODULE_AUTHOR(DRV_PROJECT);
1660 MODULE_VERSION(DRV_VERSION);
1661 MODULE_DESCRIPTION("Ralink RT2400 PCI & PCMCIA Wireless LAN driver.");
1662 MODULE_SUPPORTED_DEVICE("Ralink RT2460 PCI & PCMCIA chipset based cards");
1663 MODULE_DEVICE_TABLE(pci, rt2400pci_device_table);
1664 MODULE_LICENSE("GPL");
1665
1666 static struct pci_driver rt2400pci_driver = {
1667         .name           = DRV_NAME,
1668         .id_table       = rt2400pci_device_table,
1669         .probe          = rt2x00pci_probe,
1670         .remove         = __devexit_p(rt2x00pci_remove),
1671         .suspend        = rt2x00pci_suspend,
1672         .resume         = rt2x00pci_resume,
1673 };
1674
1675 static int __init rt2400pci_init(void)
1676 {
1677         return pci_register_driver(&rt2400pci_driver);
1678 }
1679
1680 static void __exit rt2400pci_exit(void)
1681 {
1682         pci_unregister_driver(&rt2400pci_driver);
1683 }
1684
1685 module_init(rt2400pci_init);
1686 module_exit(rt2400pci_exit);