1 /******************************************************************************
3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved.
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
28 *****************************************************************************/
30 #include <linux/etherdevice.h>
31 #include <linux/sched.h>
32 #include <net/mac80211.h>
33 #include "iwl-eeprom.h"
38 #include "iwl-helpers.h"
40 static const u16 default_tid_to_tx_fifo[] = {
60 static inline int iwl_alloc_dma_ptr(struct iwl_priv *priv,
61 struct iwl_dma_ptr *ptr, size_t size)
63 ptr->addr = dma_alloc_coherent(&priv->pci_dev->dev, size, &ptr->dma,
71 static inline void iwl_free_dma_ptr(struct iwl_priv *priv,
72 struct iwl_dma_ptr *ptr)
74 if (unlikely(!ptr->addr))
77 dma_free_coherent(&priv->pci_dev->dev, ptr->size, ptr->addr, ptr->dma);
78 memset(ptr, 0, sizeof(*ptr));
82 * iwl_txq_update_write_ptr - Send new write index to hardware
84 void iwl_txq_update_write_ptr(struct iwl_priv *priv, struct iwl_tx_queue *txq)
87 int txq_id = txq->q.id;
89 if (txq->need_update == 0)
92 /* if we're trying to save power */
93 if (test_bit(STATUS_POWER_PMI, &priv->status)) {
94 /* wake up nic if it's powered down ...
95 * uCode will wake up, and interrupt us again, so next
96 * time we'll skip this part. */
97 reg = iwl_read32(priv, CSR_UCODE_DRV_GP1);
99 if (reg & CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP) {
100 IWL_DEBUG_INFO(priv, "Tx queue %d requesting wakeup, GP1 = 0x%x\n",
102 iwl_set_bit(priv, CSR_GP_CNTRL,
103 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
107 iwl_write_direct32(priv, HBUS_TARG_WRPTR,
108 txq->q.write_ptr | (txq_id << 8));
110 /* else not in power-save mode, uCode will never sleep when we're
111 * trying to tx (during RFKILL, we're not trying to tx). */
113 iwl_write32(priv, HBUS_TARG_WRPTR,
114 txq->q.write_ptr | (txq_id << 8));
116 txq->need_update = 0;
118 EXPORT_SYMBOL(iwl_txq_update_write_ptr);
122 * iwl_tx_queue_free - Deallocate DMA queue.
123 * @txq: Transmit queue to deallocate.
125 * Empty queue by removing and destroying all BD's.
127 * 0-fill, but do not free "txq" descriptor structure.
129 void iwl_tx_queue_free(struct iwl_priv *priv, int txq_id)
131 struct iwl_tx_queue *txq = &priv->txq[txq_id];
132 struct iwl_queue *q = &txq->q;
133 struct device *dev = &priv->pci_dev->dev;
139 /* first, empty all BD's */
140 for (; q->write_ptr != q->read_ptr;
141 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd))
142 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
144 /* De-alloc array of command/tx buffers */
145 for (i = 0; i < TFD_TX_CMD_SLOTS; i++)
148 /* De-alloc circular buffer of TFDs */
150 dma_free_coherent(dev, priv->hw_params.tfd_size *
151 txq->q.n_bd, txq->tfds, txq->q.dma_addr);
153 /* De-alloc array of per-TFD driver data */
157 /* deallocate arrays */
163 /* 0-fill queue descriptor structure */
164 memset(txq, 0, sizeof(*txq));
166 EXPORT_SYMBOL(iwl_tx_queue_free);
169 * iwl_cmd_queue_free - Deallocate DMA queue.
170 * @txq: Transmit queue to deallocate.
172 * Empty queue by removing and destroying all BD's.
174 * 0-fill, but do not free "txq" descriptor structure.
176 void iwl_cmd_queue_free(struct iwl_priv *priv)
178 struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
179 struct iwl_queue *q = &txq->q;
180 struct device *dev = &priv->pci_dev->dev;
186 /* De-alloc array of command/tx buffers */
187 for (i = 0; i <= TFD_CMD_SLOTS; i++)
190 /* De-alloc circular buffer of TFDs */
192 dma_free_coherent(dev, priv->hw_params.tfd_size * txq->q.n_bd,
193 txq->tfds, txq->q.dma_addr);
195 /* deallocate arrays */
201 /* 0-fill queue descriptor structure */
202 memset(txq, 0, sizeof(*txq));
204 EXPORT_SYMBOL(iwl_cmd_queue_free);
206 /*************** DMA-QUEUE-GENERAL-FUNCTIONS *****
209 * Theory of operation
211 * A Tx or Rx queue resides in host DRAM, and is comprised of a circular buffer
212 * of buffer descriptors, each of which points to one or more data buffers for
213 * the device to read from or fill. Driver and device exchange status of each
214 * queue via "read" and "write" pointers. Driver keeps minimum of 2 empty
215 * entries in each circular buffer, to protect against confusing empty and full
218 * The device reads or writes the data in the queues via the device's several
219 * DMA/FIFO channels. Each queue is mapped to a single DMA channel.
221 * For Tx queue, there are low mark and high mark limits. If, after queuing
222 * the packet for Tx, free space become < low mark, Tx queue stopped. When
223 * reclaiming packets (on 'tx done IRQ), if free space become > high mark,
226 * See more detailed info in iwl-4965-hw.h.
227 ***************************************************/
229 int iwl_queue_space(const struct iwl_queue *q)
231 int s = q->read_ptr - q->write_ptr;
233 if (q->read_ptr > q->write_ptr)
238 /* keep some reserve to not confuse empty and full situations */
244 EXPORT_SYMBOL(iwl_queue_space);
248 * iwl_queue_init - Initialize queue's high/low-water and read/write indexes
250 static int iwl_queue_init(struct iwl_priv *priv, struct iwl_queue *q,
251 int count, int slots_num, u32 id)
254 q->n_window = slots_num;
257 /* count must be power-of-two size, otherwise iwl_queue_inc_wrap
258 * and iwl_queue_dec_wrap are broken. */
259 BUG_ON(!is_power_of_2(count));
261 /* slots_num must be power-of-two size, otherwise
262 * get_cmd_index is broken. */
263 BUG_ON(!is_power_of_2(slots_num));
265 q->low_mark = q->n_window / 4;
269 q->high_mark = q->n_window / 8;
270 if (q->high_mark < 2)
273 q->write_ptr = q->read_ptr = 0;
279 * iwl_tx_queue_alloc - Alloc driver data and TFD CB for one Tx/cmd queue
281 static int iwl_tx_queue_alloc(struct iwl_priv *priv,
282 struct iwl_tx_queue *txq, u32 id)
284 struct device *dev = &priv->pci_dev->dev;
285 size_t tfd_sz = priv->hw_params.tfd_size * TFD_QUEUE_SIZE_MAX;
287 /* Driver private data, only for Tx (not command) queues,
288 * not shared with device. */
289 if (id != IWL_CMD_QUEUE_NUM) {
290 txq->txb = kmalloc(sizeof(txq->txb[0]) *
291 TFD_QUEUE_SIZE_MAX, GFP_KERNEL);
293 IWL_ERR(priv, "kmalloc for auxiliary BD "
294 "structures failed\n");
301 /* Circular buffer of transmit frame descriptors (TFDs),
302 * shared with device */
303 txq->tfds = dma_alloc_coherent(dev, tfd_sz, &txq->q.dma_addr,
306 IWL_ERR(priv, "pci_alloc_consistent(%zd) failed\n", tfd_sz);
321 * iwl_tx_queue_init - Allocate and initialize one tx/cmd queue
323 int iwl_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq,
324 int slots_num, u32 txq_id)
328 int actual_slots = slots_num;
331 * Alloc buffer array for commands (Tx or other types of commands).
332 * For the command queue (#4), allocate command space + one big
333 * command for scan, since scan command is very huge; the system will
334 * not have two scans at the same time, so only one is needed.
335 * For normal Tx queues (all other queues), no super-size command
338 if (txq_id == IWL_CMD_QUEUE_NUM)
341 txq->meta = kzalloc(sizeof(struct iwl_cmd_meta) * actual_slots,
343 txq->cmd = kzalloc(sizeof(struct iwl_device_cmd *) * actual_slots,
346 if (!txq->meta || !txq->cmd)
347 goto out_free_arrays;
349 len = sizeof(struct iwl_device_cmd);
350 for (i = 0; i < actual_slots; i++) {
351 /* only happens for cmd queue */
353 len += IWL_MAX_SCAN_SIZE;
355 txq->cmd[i] = kmalloc(len, GFP_KERNEL);
360 /* Alloc driver data array and TFD circular buffer */
361 ret = iwl_tx_queue_alloc(priv, txq, txq_id);
365 txq->need_update = 0;
368 * Aggregation TX queues will get their ID when aggregation begins;
369 * they overwrite the setting done here. The command FIFO doesn't
370 * need an swq_id so don't set one to catch errors, all others can
371 * be set up to the identity mapping.
373 if (txq_id != IWL_CMD_QUEUE_NUM)
374 txq->swq_id = txq_id;
376 /* TFD_QUEUE_SIZE_MAX must be power-of-two size, otherwise
377 * iwl_queue_inc_wrap and iwl_queue_dec_wrap are broken. */
378 BUILD_BUG_ON(TFD_QUEUE_SIZE_MAX & (TFD_QUEUE_SIZE_MAX - 1));
380 /* Initialize queue's high/low-water marks, and head/tail indexes */
381 iwl_queue_init(priv, &txq->q, TFD_QUEUE_SIZE_MAX, slots_num, txq_id);
383 /* Tell device where to find queue */
384 priv->cfg->ops->lib->txq_init(priv, txq);
388 for (i = 0; i < actual_slots; i++)
396 EXPORT_SYMBOL(iwl_tx_queue_init);
399 * iwl_hw_txq_ctx_free - Free TXQ Context
401 * Destroy all TX DMA queues and structures
403 void iwl_hw_txq_ctx_free(struct iwl_priv *priv)
409 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num;
411 if (txq_id == IWL_CMD_QUEUE_NUM)
412 iwl_cmd_queue_free(priv);
414 iwl_tx_queue_free(priv, txq_id);
416 iwl_free_dma_ptr(priv, &priv->kw);
418 iwl_free_dma_ptr(priv, &priv->scd_bc_tbls);
420 /* free tx queue structure */
421 iwl_free_txq_mem(priv);
423 EXPORT_SYMBOL(iwl_hw_txq_ctx_free);
426 * iwl_txq_ctx_reset - Reset TX queue context
427 * Destroys all DMA structures and initialize them again
432 int iwl_txq_ctx_reset(struct iwl_priv *priv)
435 int txq_id, slots_num;
438 /* Free all tx/cmd queues and keep-warm buffer */
439 iwl_hw_txq_ctx_free(priv);
441 ret = iwl_alloc_dma_ptr(priv, &priv->scd_bc_tbls,
442 priv->hw_params.scd_bc_tbls_size);
444 IWL_ERR(priv, "Scheduler BC Table allocation failed\n");
447 /* Alloc keep-warm buffer */
448 ret = iwl_alloc_dma_ptr(priv, &priv->kw, IWL_KW_SIZE);
450 IWL_ERR(priv, "Keep Warm allocation failed\n");
454 /* allocate tx queue structure */
455 ret = iwl_alloc_txq_mem(priv);
459 spin_lock_irqsave(&priv->lock, flags);
461 /* Turn off all Tx DMA fifos */
462 priv->cfg->ops->lib->txq_set_sched(priv, 0);
464 /* Tell NIC where to find the "keep warm" buffer */
465 iwl_write_direct32(priv, FH_KW_MEM_ADDR_REG, priv->kw.dma >> 4);
467 spin_unlock_irqrestore(&priv->lock, flags);
469 /* Alloc and init all Tx queues, including the command queue (#4) */
470 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
471 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
472 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
473 ret = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
476 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
484 iwl_hw_txq_ctx_free(priv);
485 iwl_free_dma_ptr(priv, &priv->kw);
487 iwl_free_dma_ptr(priv, &priv->scd_bc_tbls);
493 * iwl_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
495 void iwl_txq_ctx_stop(struct iwl_priv *priv)
500 /* Turn off all Tx DMA fifos */
501 spin_lock_irqsave(&priv->lock, flags);
503 priv->cfg->ops->lib->txq_set_sched(priv, 0);
505 /* Stop each Tx DMA channel, and wait for it to be idle */
506 for (ch = 0; ch < priv->hw_params.dma_chnl_num; ch++) {
507 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0);
508 iwl_poll_direct_bit(priv, FH_TSSR_TX_STATUS_REG,
509 FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch),
512 spin_unlock_irqrestore(&priv->lock, flags);
514 /* Deallocate memory for all Tx queues */
515 iwl_hw_txq_ctx_free(priv);
517 EXPORT_SYMBOL(iwl_txq_ctx_stop);
520 * handle build REPLY_TX command notification.
522 static void iwl_tx_cmd_build_basic(struct iwl_priv *priv,
523 struct iwl_tx_cmd *tx_cmd,
524 struct ieee80211_tx_info *info,
525 struct ieee80211_hdr *hdr,
528 __le16 fc = hdr->frame_control;
529 __le32 tx_flags = tx_cmd->tx_flags;
531 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
532 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
533 tx_flags |= TX_CMD_FLG_ACK_MSK;
534 if (ieee80211_is_mgmt(fc))
535 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
536 if (ieee80211_is_probe_resp(fc) &&
537 !(le16_to_cpu(hdr->seq_ctrl) & 0xf))
538 tx_flags |= TX_CMD_FLG_TSF_MSK;
540 tx_flags &= (~TX_CMD_FLG_ACK_MSK);
541 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
544 if (ieee80211_is_back_req(fc))
545 tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK;
548 tx_cmd->sta_id = std_id;
549 if (ieee80211_has_morefrags(fc))
550 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK;
552 if (ieee80211_is_data_qos(fc)) {
553 u8 *qc = ieee80211_get_qos_ctl(hdr);
554 tx_cmd->tid_tspec = qc[0] & 0xf;
555 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK;
557 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK;
560 priv->cfg->ops->utils->rts_tx_cmd_flag(info, &tx_flags);
562 if ((tx_flags & TX_CMD_FLG_RTS_MSK) || (tx_flags & TX_CMD_FLG_CTS_MSK))
563 tx_flags |= TX_CMD_FLG_FULL_TXOP_PROT_MSK;
565 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK);
566 if (ieee80211_is_mgmt(fc)) {
567 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc))
568 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3);
570 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2);
572 tx_cmd->timeout.pm_frame_timeout = 0;
575 tx_cmd->driver_txop = 0;
576 tx_cmd->tx_flags = tx_flags;
577 tx_cmd->next_frame_len = 0;
580 #define RTS_HCCA_RETRY_LIMIT 3
581 #define RTS_DFAULT_RETRY_LIMIT 60
583 static void iwl_tx_cmd_build_rate(struct iwl_priv *priv,
584 struct iwl_tx_cmd *tx_cmd,
585 struct ieee80211_tx_info *info,
586 __le16 fc, int is_hcca)
594 /* Set retry limit on DATA packets and Probe Responses*/
595 if (ieee80211_is_probe_resp(fc))
596 data_retry_limit = 3;
598 data_retry_limit = IWL_DEFAULT_TX_RETRY;
599 tx_cmd->data_retry_limit = data_retry_limit;
601 /* Set retry limit on RTS packets */
602 rts_retry_limit = (is_hcca) ? RTS_HCCA_RETRY_LIMIT :
603 RTS_DFAULT_RETRY_LIMIT;
604 if (data_retry_limit < rts_retry_limit)
605 rts_retry_limit = data_retry_limit;
606 tx_cmd->rts_retry_limit = rts_retry_limit;
608 /* DATA packets will use the uCode station table for rate/antenna
610 if (ieee80211_is_data(fc)) {
611 tx_cmd->initial_rate_index = 0;
612 tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
617 * If the current TX rate stored in mac80211 has the MCS bit set, it's
618 * not really a TX rate. Thus, we use the lowest supported rate for
619 * this band. Also use the lowest supported rate if the stored rate
622 rate_idx = info->control.rates[0].idx;
623 if (info->control.rates[0].flags & IEEE80211_TX_RC_MCS ||
624 (rate_idx < 0) || (rate_idx > IWL_RATE_COUNT_LEGACY))
625 rate_idx = rate_lowest_index(&priv->bands[info->band],
627 /* For 5 GHZ band, remap mac80211 rate indices into driver indices */
628 if (info->band == IEEE80211_BAND_5GHZ)
629 rate_idx += IWL_FIRST_OFDM_RATE;
630 /* Get PLCP rate for tx_cmd->rate_n_flags */
631 rate_plcp = iwl_rates[rate_idx].plcp;
632 /* Zero out flags for this packet */
635 /* Set CCK flag as needed */
636 if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
637 rate_flags |= RATE_MCS_CCK_MSK;
639 /* Set up RTS and CTS flags for certain packets */
640 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
641 case cpu_to_le16(IEEE80211_STYPE_AUTH):
642 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
643 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
644 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
645 if (tx_cmd->tx_flags & TX_CMD_FLG_RTS_MSK) {
646 tx_cmd->tx_flags &= ~TX_CMD_FLG_RTS_MSK;
647 tx_cmd->tx_flags |= TX_CMD_FLG_CTS_MSK;
654 /* Set up antennas */
655 priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant);
656 rate_flags |= iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
658 /* Set the rate in the TX cmd */
659 tx_cmd->rate_n_flags = iwl_hw_set_rate_n_flags(rate_plcp, rate_flags);
662 static void iwl_tx_cmd_build_hwcrypto(struct iwl_priv *priv,
663 struct ieee80211_tx_info *info,
664 struct iwl_tx_cmd *tx_cmd,
665 struct sk_buff *skb_frag,
668 struct ieee80211_key_conf *keyconf = info->control.hw_key;
670 switch (keyconf->alg) {
672 tx_cmd->sec_ctl = TX_CMD_SEC_CCM;
673 memcpy(tx_cmd->key, keyconf->key, keyconf->keylen);
674 if (info->flags & IEEE80211_TX_CTL_AMPDU)
675 tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK;
676 IWL_DEBUG_TX(priv, "tx_cmd with AES hwcrypto\n");
680 tx_cmd->sec_ctl = TX_CMD_SEC_TKIP;
681 ieee80211_get_tkip_key(keyconf, skb_frag,
682 IEEE80211_TKIP_P2_KEY, tx_cmd->key);
683 IWL_DEBUG_TX(priv, "tx_cmd with tkip hwcrypto\n");
687 tx_cmd->sec_ctl |= (TX_CMD_SEC_WEP |
688 (keyconf->keyidx & TX_CMD_SEC_MSK) << TX_CMD_SEC_SHIFT);
690 if (keyconf->keylen == WEP_KEY_LEN_128)
691 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128;
693 memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen);
695 IWL_DEBUG_TX(priv, "Configuring packet for WEP encryption "
696 "with key %d\n", keyconf->keyidx);
700 IWL_ERR(priv, "Unknown encode alg %d\n", keyconf->alg);
706 * start REPLY_TX command process
708 int iwl_tx_skb(struct iwl_priv *priv, struct sk_buff *skb)
710 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
711 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
712 struct ieee80211_sta *sta = info->control.sta;
713 struct iwl_station_priv *sta_priv = NULL;
714 struct iwl_tx_queue *txq;
716 struct iwl_device_cmd *out_cmd;
717 struct iwl_cmd_meta *out_meta;
718 struct iwl_tx_cmd *tx_cmd;
720 dma_addr_t phys_addr;
721 dma_addr_t txcmd_phys;
722 dma_addr_t scratch_phys;
723 u16 len, len_org, firstlen, secondlen;
728 u8 wait_write_ptr = 0;
733 spin_lock_irqsave(&priv->lock, flags);
734 if (iwl_is_rfkill(priv)) {
735 IWL_DEBUG_DROP(priv, "Dropping - RF KILL\n");
739 fc = hdr->frame_control;
741 #ifdef CONFIG_IWLWIFI_DEBUG
742 if (ieee80211_is_auth(fc))
743 IWL_DEBUG_TX(priv, "Sending AUTH frame\n");
744 else if (ieee80211_is_assoc_req(fc))
745 IWL_DEBUG_TX(priv, "Sending ASSOC frame\n");
746 else if (ieee80211_is_reassoc_req(fc))
747 IWL_DEBUG_TX(priv, "Sending REASSOC frame\n");
750 /* drop all non-injected data frame if we are not associated */
751 if (ieee80211_is_data(fc) &&
752 !(info->flags & IEEE80211_TX_CTL_INJECTED) &&
753 (!iwl_is_associated(priv) ||
754 ((priv->iw_mode == NL80211_IFTYPE_STATION) && !priv->assoc_id) ||
755 !priv->assoc_station_added)) {
756 IWL_DEBUG_DROP(priv, "Dropping - !iwl_is_associated\n");
760 hdr_len = ieee80211_hdrlen(fc);
762 /* Find (or create) index into station table for destination station */
763 if (info->flags & IEEE80211_TX_CTL_INJECTED)
764 sta_id = priv->hw_params.bcast_sta_id;
766 sta_id = iwl_get_sta_id(priv, hdr);
767 if (sta_id == IWL_INVALID_STATION) {
768 IWL_DEBUG_DROP(priv, "Dropping - INVALID STATION: %pM\n",
773 IWL_DEBUG_TX(priv, "station Id %d\n", sta_id);
776 sta_priv = (void *)sta->drv_priv;
778 if (sta_priv && sta_id != priv->hw_params.bcast_sta_id &&
780 WARN_ON(!(info->flags & IEEE80211_TX_CTL_PSPOLL_RESPONSE));
782 * This sends an asynchronous command to the device,
783 * but we can rely on it being processed before the
784 * next frame is processed -- and the next frame to
785 * this station is the one that will consume this
787 * For now set the counter to just 1 since we do not
790 iwl_sta_modify_sleep_tx_count(priv, sta_id, 1);
793 txq_id = skb_get_queue_mapping(skb);
794 if (ieee80211_is_data_qos(fc)) {
795 qc = ieee80211_get_qos_ctl(hdr);
796 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK;
797 if (unlikely(tid >= MAX_TID_COUNT))
799 seq_number = priv->stations[sta_id].tid[tid].seq_number;
800 seq_number &= IEEE80211_SCTL_SEQ;
801 hdr->seq_ctrl = hdr->seq_ctrl &
802 cpu_to_le16(IEEE80211_SCTL_FRAG);
803 hdr->seq_ctrl |= cpu_to_le16(seq_number);
805 /* aggregation is on for this <sta,tid> */
806 if (info->flags & IEEE80211_TX_CTL_AMPDU &&
807 priv->stations[sta_id].tid[tid].agg.state == IWL_AGG_ON) {
808 txq_id = priv->stations[sta_id].tid[tid].agg.txq_id;
812 txq = &priv->txq[txq_id];
813 swq_id = txq->swq_id;
816 if (unlikely(iwl_queue_space(q) < q->high_mark))
819 if (ieee80211_is_data_qos(fc))
820 priv->stations[sta_id].tid[tid].tfds_in_queue++;
822 /* Set up driver data for this TFD */
823 memset(&(txq->txb[q->write_ptr]), 0, sizeof(struct iwl_tx_info));
824 txq->txb[q->write_ptr].skb[0] = skb;
826 /* Set up first empty entry in queue's array of Tx/cmd buffers */
827 out_cmd = txq->cmd[q->write_ptr];
828 out_meta = &txq->meta[q->write_ptr];
829 tx_cmd = &out_cmd->cmd.tx;
830 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr));
831 memset(tx_cmd, 0, sizeof(struct iwl_tx_cmd));
834 * Set up the Tx-command (not MAC!) header.
835 * Store the chosen Tx queue and TFD index within the sequence field;
836 * after Tx, uCode's Tx response will return this value so driver can
837 * locate the frame within the tx queue and do post-tx processing.
839 out_cmd->hdr.cmd = REPLY_TX;
840 out_cmd->hdr.sequence = cpu_to_le16((u16)(QUEUE_TO_SEQ(txq_id) |
841 INDEX_TO_SEQ(q->write_ptr)));
843 /* Copy MAC header from skb into command buffer */
844 memcpy(tx_cmd->hdr, hdr, hdr_len);
847 /* Total # bytes to be transmitted */
849 tx_cmd->len = cpu_to_le16(len);
851 if (info->control.hw_key)
852 iwl_tx_cmd_build_hwcrypto(priv, info, tx_cmd, skb, sta_id);
854 /* TODO need this for burst mode later on */
855 iwl_tx_cmd_build_basic(priv, tx_cmd, info, hdr, sta_id);
856 iwl_dbg_log_tx_data_frame(priv, len, hdr);
858 /* set is_hcca to 0; it probably will never be implemented */
859 iwl_tx_cmd_build_rate(priv, tx_cmd, info, fc, 0);
861 iwl_update_stats(priv, true, fc, len);
863 * Use the first empty entry in this queue's command buffer array
864 * to contain the Tx command and MAC header concatenated together
865 * (payload data will be in another buffer).
866 * Size of this varies, due to varying MAC header length.
867 * If end is not dword aligned, we'll have 2 extra bytes at the end
868 * of the MAC header (device reads on dword boundaries).
869 * We'll tell device about this padding later.
871 len = sizeof(struct iwl_tx_cmd) +
872 sizeof(struct iwl_cmd_header) + hdr_len;
875 firstlen = len = (len + 3) & ~3;
882 /* Tell NIC about any 2-byte padding after MAC header */
884 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK;
886 /* Physical address of this Tx command's header (not MAC header!),
887 * within command buffer array. */
888 txcmd_phys = pci_map_single(priv->pci_dev,
890 PCI_DMA_BIDIRECTIONAL);
891 pci_unmap_addr_set(out_meta, mapping, txcmd_phys);
892 pci_unmap_len_set(out_meta, len, len);
893 /* Add buffer containing Tx command and MAC(!) header to TFD's
895 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
896 txcmd_phys, len, 1, 0);
898 if (!ieee80211_has_morefrags(hdr->frame_control)) {
899 txq->need_update = 1;
901 priv->stations[sta_id].tid[tid].seq_number = seq_number;
904 txq->need_update = 0;
907 /* Set up TFD's 2nd entry to point directly to remainder of skb,
908 * if any (802.11 null frames have no payload). */
909 secondlen = len = skb->len - hdr_len;
911 phys_addr = pci_map_single(priv->pci_dev, skb->data + hdr_len,
912 len, PCI_DMA_TODEVICE);
913 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
918 scratch_phys = txcmd_phys + sizeof(struct iwl_cmd_header) +
919 offsetof(struct iwl_tx_cmd, scratch);
921 len = sizeof(struct iwl_tx_cmd) +
922 sizeof(struct iwl_cmd_header) + hdr_len;
923 /* take back ownership of DMA buffer to enable update */
924 pci_dma_sync_single_for_cpu(priv->pci_dev, txcmd_phys,
925 len, PCI_DMA_BIDIRECTIONAL);
926 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys);
927 tx_cmd->dram_msb_ptr = iwl_get_dma_hi_addr(scratch_phys);
929 IWL_DEBUG_TX(priv, "sequence nr = 0X%x \n",
930 le16_to_cpu(out_cmd->hdr.sequence));
931 IWL_DEBUG_TX(priv, "tx_flags = 0X%x \n", le32_to_cpu(tx_cmd->tx_flags));
932 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd, sizeof(*tx_cmd));
933 iwl_print_hex_dump(priv, IWL_DL_TX, (u8 *)tx_cmd->hdr, hdr_len);
935 /* Set up entry for this TFD in Tx byte-count array */
936 if (info->flags & IEEE80211_TX_CTL_AMPDU)
937 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq,
938 le16_to_cpu(tx_cmd->len));
940 pci_dma_sync_single_for_device(priv->pci_dev, txcmd_phys,
941 len, PCI_DMA_BIDIRECTIONAL);
943 trace_iwlwifi_dev_tx(priv,
944 &((struct iwl_tfd *)txq->tfds)[txq->q.write_ptr],
945 sizeof(struct iwl_tfd),
946 &out_cmd->hdr, firstlen,
947 skb->data + hdr_len, secondlen);
949 /* Tell device the write index *just past* this latest filled TFD */
950 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
951 iwl_txq_update_write_ptr(priv, txq);
952 spin_unlock_irqrestore(&priv->lock, flags);
955 * At this point the frame is "transmitted" successfully
956 * and we will get a TX status notification eventually,
957 * regardless of the value of ret. "ret" only indicates
958 * whether or not we should update the write pointer.
961 /* avoid atomic ops if it isn't an associated client */
962 if (sta_priv && sta_priv->client)
963 atomic_inc(&sta_priv->pending_frames);
965 if ((iwl_queue_space(q) < q->high_mark) && priv->mac80211_registered) {
966 if (wait_write_ptr) {
967 spin_lock_irqsave(&priv->lock, flags);
968 txq->need_update = 1;
969 iwl_txq_update_write_ptr(priv, txq);
970 spin_unlock_irqrestore(&priv->lock, flags);
972 iwl_stop_queue(priv, txq->swq_id);
979 spin_unlock_irqrestore(&priv->lock, flags);
982 EXPORT_SYMBOL(iwl_tx_skb);
984 /*************** HOST COMMAND QUEUE FUNCTIONS *****/
987 * iwl_enqueue_hcmd - enqueue a uCode command
988 * @priv: device private data point
989 * @cmd: a point to the ucode command structure
991 * The function returns < 0 values to indicate the operation is
992 * failed. On success, it turns the index (> 0) of command in the
995 int iwl_enqueue_hcmd(struct iwl_priv *priv, struct iwl_host_cmd *cmd)
997 struct iwl_tx_queue *txq = &priv->txq[IWL_CMD_QUEUE_NUM];
998 struct iwl_queue *q = &txq->q;
999 struct iwl_device_cmd *out_cmd;
1000 struct iwl_cmd_meta *out_meta;
1001 dma_addr_t phys_addr;
1002 unsigned long flags;
1007 cmd->len = priv->cfg->ops->utils->get_hcmd_size(cmd->id, cmd->len);
1008 fix_size = (u16)(cmd->len + sizeof(out_cmd->hdr));
1010 /* If any of the command structures end up being larger than
1011 * the TFD_MAX_PAYLOAD_SIZE, and it sent as a 'small' command then
1012 * we will need to increase the size of the TFD entries */
1013 BUG_ON((fix_size > TFD_MAX_PAYLOAD_SIZE) &&
1014 !(cmd->flags & CMD_SIZE_HUGE));
1016 if (iwl_is_rfkill(priv) || iwl_is_ctkill(priv)) {
1017 IWL_WARN(priv, "Not sending command - %s KILL\n",
1018 iwl_is_rfkill(priv) ? "RF" : "CT");
1022 if (iwl_queue_space(q) < ((cmd->flags & CMD_ASYNC) ? 2 : 1)) {
1023 IWL_ERR(priv, "No space in command queue\n");
1024 if (iwl_within_ct_kill_margin(priv))
1025 iwl_tt_enter_ct_kill(priv);
1027 IWL_ERR(priv, "Restarting adapter due to queue full\n");
1028 queue_work(priv->workqueue, &priv->restart);
1033 spin_lock_irqsave(&priv->hcmd_lock, flags);
1035 idx = get_cmd_index(q, q->write_ptr, cmd->flags & CMD_SIZE_HUGE);
1036 out_cmd = txq->cmd[idx];
1037 out_meta = &txq->meta[idx];
1039 memset(out_meta, 0, sizeof(*out_meta)); /* re-initialize to NULL */
1040 out_meta->flags = cmd->flags;
1041 if (cmd->flags & CMD_WANT_SKB)
1042 out_meta->source = cmd;
1043 if (cmd->flags & CMD_ASYNC)
1044 out_meta->callback = cmd->callback;
1046 out_cmd->hdr.cmd = cmd->id;
1047 memcpy(&out_cmd->cmd.payload, cmd->data, cmd->len);
1049 /* At this point, the out_cmd now has all of the incoming cmd
1052 out_cmd->hdr.flags = 0;
1053 out_cmd->hdr.sequence = cpu_to_le16(QUEUE_TO_SEQ(IWL_CMD_QUEUE_NUM) |
1054 INDEX_TO_SEQ(q->write_ptr));
1055 if (cmd->flags & CMD_SIZE_HUGE)
1056 out_cmd->hdr.sequence |= SEQ_HUGE_FRAME;
1057 len = sizeof(struct iwl_device_cmd);
1058 len += (idx == TFD_CMD_SLOTS) ? IWL_MAX_SCAN_SIZE : 0;
1061 #ifdef CONFIG_IWLWIFI_DEBUG
1062 switch (out_cmd->hdr.cmd) {
1063 case REPLY_TX_LINK_QUALITY_CMD:
1064 case SENSITIVITY_CMD:
1065 IWL_DEBUG_HC_DUMP(priv, "Sending command %s (#%x), seq: 0x%04X, "
1066 "%d bytes at %d[%d]:%d\n",
1067 get_cmd_string(out_cmd->hdr.cmd),
1069 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
1070 q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
1073 IWL_DEBUG_HC(priv, "Sending command %s (#%x), seq: 0x%04X, "
1074 "%d bytes at %d[%d]:%d\n",
1075 get_cmd_string(out_cmd->hdr.cmd),
1077 le16_to_cpu(out_cmd->hdr.sequence), fix_size,
1078 q->write_ptr, idx, IWL_CMD_QUEUE_NUM);
1081 txq->need_update = 1;
1083 if (priv->cfg->ops->lib->txq_update_byte_cnt_tbl)
1084 /* Set up entry in queue's byte count circular buffer */
1085 priv->cfg->ops->lib->txq_update_byte_cnt_tbl(priv, txq, 0);
1087 phys_addr = pci_map_single(priv->pci_dev, &out_cmd->hdr,
1088 fix_size, PCI_DMA_BIDIRECTIONAL);
1089 pci_unmap_addr_set(out_meta, mapping, phys_addr);
1090 pci_unmap_len_set(out_meta, len, fix_size);
1092 trace_iwlwifi_dev_hcmd(priv, &out_cmd->hdr, fix_size, cmd->flags);
1094 priv->cfg->ops->lib->txq_attach_buf_to_tfd(priv, txq,
1095 phys_addr, fix_size, 1,
1098 /* Increment and update queue's write index */
1099 q->write_ptr = iwl_queue_inc_wrap(q->write_ptr, q->n_bd);
1100 iwl_txq_update_write_ptr(priv, txq);
1102 spin_unlock_irqrestore(&priv->hcmd_lock, flags);
1106 static void iwl_tx_status(struct iwl_priv *priv, struct sk_buff *skb)
1108 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1109 struct ieee80211_sta *sta;
1110 struct iwl_station_priv *sta_priv;
1112 sta = ieee80211_find_sta(priv->vif, hdr->addr1);
1114 sta_priv = (void *)sta->drv_priv;
1115 /* avoid atomic ops if this isn't a client */
1116 if (sta_priv->client &&
1117 atomic_dec_return(&sta_priv->pending_frames) == 0)
1118 ieee80211_sta_block_awake(priv->hw, sta, false);
1121 ieee80211_tx_status_irqsafe(priv->hw, skb);
1124 int iwl_tx_queue_reclaim(struct iwl_priv *priv, int txq_id, int index)
1126 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1127 struct iwl_queue *q = &txq->q;
1128 struct iwl_tx_info *tx_info;
1131 if ((index >= q->n_bd) || (iwl_queue_used(q, index) == 0)) {
1132 IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
1133 "is out of range [0-%d] %d %d.\n", txq_id,
1134 index, q->n_bd, q->write_ptr, q->read_ptr);
1138 for (index = iwl_queue_inc_wrap(index, q->n_bd);
1139 q->read_ptr != index;
1140 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1142 tx_info = &txq->txb[txq->q.read_ptr];
1143 iwl_tx_status(priv, tx_info->skb[0]);
1144 tx_info->skb[0] = NULL;
1146 if (priv->cfg->ops->lib->txq_inval_byte_cnt_tbl)
1147 priv->cfg->ops->lib->txq_inval_byte_cnt_tbl(priv, txq);
1149 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
1154 EXPORT_SYMBOL(iwl_tx_queue_reclaim);
1158 * iwl_hcmd_queue_reclaim - Reclaim TX command queue entries already Tx'd
1160 * When FW advances 'R' index, all entries between old and new 'R' index
1161 * need to be reclaimed. As result, some free space forms. If there is
1162 * enough free space (> low mark), wake the stack that feeds us.
1164 static void iwl_hcmd_queue_reclaim(struct iwl_priv *priv, int txq_id,
1165 int idx, int cmd_idx)
1167 struct iwl_tx_queue *txq = &priv->txq[txq_id];
1168 struct iwl_queue *q = &txq->q;
1171 if ((idx >= q->n_bd) || (iwl_queue_used(q, idx) == 0)) {
1172 IWL_ERR(priv, "Read index for DMA queue txq id (%d), index %d, "
1173 "is out of range [0-%d] %d %d.\n", txq_id,
1174 idx, q->n_bd, q->write_ptr, q->read_ptr);
1178 for (idx = iwl_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx;
1179 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
1182 IWL_ERR(priv, "HCMD skipped: index (%d) %d %d\n", idx,
1183 q->write_ptr, q->read_ptr);
1184 queue_work(priv->workqueue, &priv->restart);
1191 * iwl_tx_cmd_complete - Pull unused buffers off the queue and reclaim them
1192 * @rxb: Rx buffer to reclaim
1194 * If an Rx buffer has an async callback associated with it the callback
1195 * will be executed. The attached skb (if present) will only be freed
1196 * if the callback returns 1
1198 void iwl_tx_cmd_complete(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
1200 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1201 u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1202 int txq_id = SEQ_TO_QUEUE(sequence);
1203 int index = SEQ_TO_INDEX(sequence);
1205 bool huge = !!(pkt->hdr.sequence & SEQ_HUGE_FRAME);
1206 struct iwl_device_cmd *cmd;
1207 struct iwl_cmd_meta *meta;
1209 /* If a Tx command is being handled and it isn't in the actual
1210 * command queue then there a command routing bug has been introduced
1211 * in the queue management code. */
1212 if (WARN(txq_id != IWL_CMD_QUEUE_NUM,
1213 "wrong command queue %d, sequence 0x%X readp=%d writep=%d\n",
1215 priv->txq[IWL_CMD_QUEUE_NUM].q.read_ptr,
1216 priv->txq[IWL_CMD_QUEUE_NUM].q.write_ptr)) {
1217 iwl_print_hex_error(priv, pkt, 32);
1221 cmd_index = get_cmd_index(&priv->txq[IWL_CMD_QUEUE_NUM].q, index, huge);
1222 cmd = priv->txq[IWL_CMD_QUEUE_NUM].cmd[cmd_index];
1223 meta = &priv->txq[IWL_CMD_QUEUE_NUM].meta[cmd_index];
1225 pci_unmap_single(priv->pci_dev,
1226 pci_unmap_addr(meta, mapping),
1227 pci_unmap_len(meta, len),
1228 PCI_DMA_BIDIRECTIONAL);
1230 /* Input error checking is done when commands are added to queue. */
1231 if (meta->flags & CMD_WANT_SKB) {
1232 meta->source->reply_page = (unsigned long)rxb_addr(rxb);
1234 } else if (meta->callback)
1235 meta->callback(priv, cmd, pkt);
1237 iwl_hcmd_queue_reclaim(priv, txq_id, index, cmd_index);
1239 if (!(meta->flags & CMD_ASYNC)) {
1240 clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1241 wake_up_interruptible(&priv->wait_command_queue);
1244 EXPORT_SYMBOL(iwl_tx_cmd_complete);
1247 * Find first available (lowest unused) Tx Queue, mark it "active".
1248 * Called only when finding queue for aggregation.
1249 * Should never return anything < 7, because they should already
1250 * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6).
1252 static int iwl_txq_ctx_activate_free(struct iwl_priv *priv)
1256 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
1257 if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
1262 int iwl_tx_agg_start(struct iwl_priv *priv, const u8 *ra, u16 tid, u16 *ssn)
1268 unsigned long flags;
1269 struct iwl_tid_data *tid_data;
1271 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
1272 tx_fifo = default_tid_to_tx_fifo[tid];
1276 IWL_WARN(priv, "%s on ra = %pM tid = %d\n",
1279 sta_id = iwl_find_station(priv, ra);
1280 if (sta_id == IWL_INVALID_STATION) {
1281 IWL_ERR(priv, "Start AGG on invalid station\n");
1284 if (unlikely(tid >= MAX_TID_COUNT))
1287 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
1288 IWL_ERR(priv, "Start AGG when state is not IWL_AGG_OFF !\n");
1292 txq_id = iwl_txq_ctx_activate_free(priv);
1294 IWL_ERR(priv, "No free aggregation queue available\n");
1298 spin_lock_irqsave(&priv->sta_lock, flags);
1299 tid_data = &priv->stations[sta_id].tid[tid];
1300 *ssn = SEQ_TO_SN(tid_data->seq_number);
1301 tid_data->agg.txq_id = txq_id;
1302 priv->txq[txq_id].swq_id = iwl_virtual_agg_queue_num(tx_fifo, txq_id);
1303 spin_unlock_irqrestore(&priv->sta_lock, flags);
1305 ret = priv->cfg->ops->lib->txq_agg_enable(priv, txq_id, tx_fifo,
1310 if (tid_data->tfds_in_queue == 0) {
1311 IWL_DEBUG_HT(priv, "HW queue is empty\n");
1312 tid_data->agg.state = IWL_AGG_ON;
1313 ieee80211_start_tx_ba_cb_irqsafe(priv->vif, ra, tid);
1315 IWL_DEBUG_HT(priv, "HW queue is NOT empty: %d packets in HW queue\n",
1316 tid_data->tfds_in_queue);
1317 tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
1321 EXPORT_SYMBOL(iwl_tx_agg_start);
1323 int iwl_tx_agg_stop(struct iwl_priv *priv , const u8 *ra, u16 tid)
1325 int tx_fifo_id, txq_id, sta_id, ssn = -1;
1326 struct iwl_tid_data *tid_data;
1327 int write_ptr, read_ptr;
1328 unsigned long flags;
1331 IWL_ERR(priv, "ra = NULL\n");
1335 if (unlikely(tid >= MAX_TID_COUNT))
1338 if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
1339 tx_fifo_id = default_tid_to_tx_fifo[tid];
1343 sta_id = iwl_find_station(priv, ra);
1345 if (sta_id == IWL_INVALID_STATION) {
1346 IWL_ERR(priv, "Invalid station for AGG tid %d\n", tid);
1350 if (priv->stations[sta_id].tid[tid].agg.state ==
1351 IWL_EMPTYING_HW_QUEUE_ADDBA) {
1352 IWL_DEBUG_HT(priv, "AGG stop before setup done\n");
1353 ieee80211_stop_tx_ba_cb_irqsafe(priv->vif, ra, tid);
1354 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
1358 if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
1359 IWL_WARN(priv, "Stopping AGG while state not ON or starting\n");
1361 tid_data = &priv->stations[sta_id].tid[tid];
1362 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
1363 txq_id = tid_data->agg.txq_id;
1364 write_ptr = priv->txq[txq_id].q.write_ptr;
1365 read_ptr = priv->txq[txq_id].q.read_ptr;
1367 /* The queue is not empty */
1368 if (write_ptr != read_ptr) {
1369 IWL_DEBUG_HT(priv, "Stopping a non empty AGG HW QUEUE\n");
1370 priv->stations[sta_id].tid[tid].agg.state =
1371 IWL_EMPTYING_HW_QUEUE_DELBA;
1375 IWL_DEBUG_HT(priv, "HW queue is empty\n");
1376 priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
1378 spin_lock_irqsave(&priv->lock, flags);
1380 * the only reason this call can fail is queue number out of range,
1381 * which can happen if uCode is reloaded and all the station
1382 * information are lost. if it is outside the range, there is no need
1383 * to deactivate the uCode queue, just return "success" to allow
1384 * mac80211 to clean up it own data.
1386 priv->cfg->ops->lib->txq_agg_disable(priv, txq_id, ssn,
1388 spin_unlock_irqrestore(&priv->lock, flags);
1390 ieee80211_stop_tx_ba_cb_irqsafe(priv->vif, ra, tid);
1394 EXPORT_SYMBOL(iwl_tx_agg_stop);
1396 int iwl_txq_check_empty(struct iwl_priv *priv, int sta_id, u8 tid, int txq_id)
1398 struct iwl_queue *q = &priv->txq[txq_id].q;
1399 u8 *addr = priv->stations[sta_id].sta.sta.addr;
1400 struct iwl_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
1402 switch (priv->stations[sta_id].tid[tid].agg.state) {
1403 case IWL_EMPTYING_HW_QUEUE_DELBA:
1404 /* We are reclaiming the last packet of the */
1405 /* aggregated HW queue */
1406 if ((txq_id == tid_data->agg.txq_id) &&
1407 (q->read_ptr == q->write_ptr)) {
1408 u16 ssn = SEQ_TO_SN(tid_data->seq_number);
1409 int tx_fifo = default_tid_to_tx_fifo[tid];
1410 IWL_DEBUG_HT(priv, "HW queue empty: continue DELBA flow\n");
1411 priv->cfg->ops->lib->txq_agg_disable(priv, txq_id,
1413 tid_data->agg.state = IWL_AGG_OFF;
1414 ieee80211_stop_tx_ba_cb_irqsafe(priv->vif, addr, tid);
1417 case IWL_EMPTYING_HW_QUEUE_ADDBA:
1418 /* We are reclaiming the last packet of the queue */
1419 if (tid_data->tfds_in_queue == 0) {
1420 IWL_DEBUG_HT(priv, "HW queue empty: continue ADDBA flow\n");
1421 tid_data->agg.state = IWL_AGG_ON;
1422 ieee80211_start_tx_ba_cb_irqsafe(priv->vif, addr, tid);
1428 EXPORT_SYMBOL(iwl_txq_check_empty);
1431 * iwl_tx_status_reply_compressed_ba - Update tx status from block-ack
1433 * Go through block-ack's bitmap of ACK'd frames, update driver's record of
1434 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
1436 static int iwl_tx_status_reply_compressed_ba(struct iwl_priv *priv,
1437 struct iwl_ht_agg *agg,
1438 struct iwl_compressed_ba_resp *ba_resp)
1442 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
1443 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1446 struct ieee80211_tx_info *info;
1448 if (unlikely(!agg->wait_for_ba)) {
1449 IWL_ERR(priv, "Received BA when not expected\n");
1453 /* Mark that the expected block-ack response arrived */
1454 agg->wait_for_ba = 0;
1455 IWL_DEBUG_TX_REPLY(priv, "BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
1457 /* Calculate shift to align block-ack bits with our Tx window bits */
1458 sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl >> 4);
1459 if (sh < 0) /* tbw something is wrong with indices */
1462 /* don't use 64-bit values for now */
1463 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
1465 if (agg->frame_count > (64 - sh)) {
1466 IWL_DEBUG_TX_REPLY(priv, "more frames than bitmap size");
1470 /* check for success or failure according to the
1471 * transmitted bitmap and block-ack bitmap */
1472 bitmap &= agg->bitmap;
1474 /* For each frame attempted in aggregation,
1475 * update driver's record of tx frame's status. */
1476 for (i = 0; i < agg->frame_count ; i++) {
1477 ack = bitmap & (1ULL << i);
1479 IWL_DEBUG_TX_REPLY(priv, "%s ON i=%d idx=%d raw=%d\n",
1480 ack ? "ACK" : "NACK", i, (agg->start_idx + i) & 0xff,
1481 agg->start_idx + i);
1484 info = IEEE80211_SKB_CB(priv->txq[scd_flow].txb[agg->start_idx].skb[0]);
1485 memset(&info->status, 0, sizeof(info->status));
1486 info->flags |= IEEE80211_TX_STAT_ACK;
1487 info->flags |= IEEE80211_TX_STAT_AMPDU;
1488 info->status.ampdu_ack_map = successes;
1489 info->status.ampdu_ack_len = agg->frame_count;
1490 iwl_hwrate_to_tx_control(priv, agg->rate_n_flags, info);
1492 IWL_DEBUG_TX_REPLY(priv, "Bitmap %llx\n", (unsigned long long)bitmap);
1498 * iwl_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
1500 * Handles block-acknowledge notification from device, which reports success
1501 * of frames sent via aggregation.
1503 void iwl_rx_reply_compressed_ba(struct iwl_priv *priv,
1504 struct iwl_rx_mem_buffer *rxb)
1506 struct iwl_rx_packet *pkt = rxb_addr(rxb);
1507 struct iwl_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
1508 struct iwl_tx_queue *txq = NULL;
1509 struct iwl_ht_agg *agg;
1514 /* "flow" corresponds to Tx queue */
1515 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
1517 /* "ssn" is start of block-ack Tx window, corresponds to index
1518 * (in Tx queue's circular buffer) of first TFD/frame in window */
1519 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
1521 if (scd_flow >= priv->hw_params.max_txq_num) {
1523 "BUG_ON scd_flow is bigger than number of queues\n");
1527 txq = &priv->txq[scd_flow];
1528 sta_id = ba_resp->sta_id;
1530 agg = &priv->stations[sta_id].tid[tid].agg;
1532 /* Find index just before block-ack window */
1533 index = iwl_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
1535 /* TODO: Need to get this copy more safely - now good for debug */
1537 IWL_DEBUG_TX_REPLY(priv, "REPLY_COMPRESSED_BA [%d] Received from %pM, "
1540 (u8 *) &ba_resp->sta_addr_lo32,
1542 IWL_DEBUG_TX_REPLY(priv, "TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
1543 "%d, scd_ssn = %d\n",
1546 (unsigned long long)le64_to_cpu(ba_resp->bitmap),
1549 IWL_DEBUG_TX_REPLY(priv, "DAT start_idx = %d, bitmap = 0x%llx \n",
1551 (unsigned long long)agg->bitmap);
1553 /* Update driver's record of ACK vs. not for each frame in window */
1554 iwl_tx_status_reply_compressed_ba(priv, agg, ba_resp);
1556 /* Release all TFDs before the SSN, i.e. all TFDs in front of
1557 * block-ack window (we assume that they've been successfully
1558 * transmitted ... if not, it's too late anyway). */
1559 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
1560 /* calculate mac80211 ampdu sw queue to wake */
1561 int freed = iwl_tx_queue_reclaim(priv, scd_flow, index);
1562 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1564 if ((iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1565 priv->mac80211_registered &&
1566 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA))
1567 iwl_wake_queue(priv, txq->swq_id);
1569 iwl_txq_check_empty(priv, sta_id, tid, scd_flow);
1572 EXPORT_SYMBOL(iwl_rx_reply_compressed_ba);
1574 #ifdef CONFIG_IWLWIFI_DEBUG
1575 #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
1577 const char *iwl_get_tx_fail_reason(u32 status)
1579 switch (status & TX_STATUS_MSK) {
1580 case TX_STATUS_SUCCESS:
1582 TX_STATUS_ENTRY(SHORT_LIMIT);
1583 TX_STATUS_ENTRY(LONG_LIMIT);
1584 TX_STATUS_ENTRY(FIFO_UNDERRUN);
1585 TX_STATUS_ENTRY(MGMNT_ABORT);
1586 TX_STATUS_ENTRY(NEXT_FRAG);
1587 TX_STATUS_ENTRY(LIFE_EXPIRE);
1588 TX_STATUS_ENTRY(DEST_PS);
1589 TX_STATUS_ENTRY(ABORTED);
1590 TX_STATUS_ENTRY(BT_RETRY);
1591 TX_STATUS_ENTRY(STA_INVALID);
1592 TX_STATUS_ENTRY(FRAG_DROPPED);
1593 TX_STATUS_ENTRY(TID_DISABLE);
1594 TX_STATUS_ENTRY(FRAME_FLUSHED);
1595 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
1596 TX_STATUS_ENTRY(TX_LOCKED);
1597 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
1602 EXPORT_SYMBOL(iwl_get_tx_fail_reason);
1603 #endif /* CONFIG_IWLWIFI_DEBUG */