1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2005 - 2007 Intel Corporation. All rights reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
27 * Contact Information:
28 * James P. Ketrenos <ipw2100-admin@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
33 * Copyright(c) 2005 - 2007 Intel Corporation. All rights reserved.
34 * All rights reserved.
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *****************************************************************************/
63 #ifndef __iwlwifi_hw_h__
64 #define __iwlwifi_hw_h__
67 * This file defines hardware constants common to 3945 and 4965.
69 * Device-specific constants are defined in iwl-3945-hw.h and iwl-4965-hw.h,
70 * although this file contains a few definitions for which the .c
71 * implementation is the same for 3945 and 4965, except for the value of
74 * uCode API constants are defined in iwl-commands.h.
76 * NOTE: DO NOT PUT OS IMPLEMENTATION-SPECIFIC DECLARATIONS HERE
78 * The iwl-*hw.h (and files they include) files should remain OS/driver
79 * implementation independent, declaring only the hardware interface.
82 /* uCode queue management definitions */
83 #define IWL_CMD_QUEUE_NUM 4
84 #define IWL_CMD_FIFO_NUM 4
85 #define IWL_BACK_QUEUE_FIRST_ID 7
88 #define IWL_CCK_RATES 4
89 #define IWL_OFDM_RATES 8
92 #define IWL_HT_RATES 0
94 #define IWL_HT_RATES 16
97 #define IWL_MAX_RATES (IWL_CCK_RATES+IWL_OFDM_RATES+IWL_HT_RATES)
100 #define SHORT_SLOT_TIME 9
101 #define LONG_SLOT_TIME 20
105 #define IWL_RSSI_OFFSET 95
107 #define IWL_RSSI_OFFSET 44
110 #include "iwl-eeprom.h"
111 #include "iwl-commands.h"
113 #define PCI_LINK_CTRL 0x0F0
114 #define PCI_POWER_SOURCE 0x0C8
115 #define PCI_REG_WUM8 0x0E8
116 #define PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT (0x80000000)
118 /*=== CSR (control and status registers) ===*/
119 #define CSR_BASE (0x000)
121 #define CSR_SW_VER (CSR_BASE+0x000)
122 #define CSR_HW_IF_CONFIG_REG (CSR_BASE+0x000) /* hardware interface config */
123 #define CSR_INT_COALESCING (CSR_BASE+0x004) /* accum ints, 32-usec units */
124 #define CSR_INT (CSR_BASE+0x008) /* host interrupt status/ack */
125 #define CSR_INT_MASK (CSR_BASE+0x00c) /* host interrupt enable */
126 #define CSR_FH_INT_STATUS (CSR_BASE+0x010) /* busmaster int status/ack*/
127 #define CSR_GPIO_IN (CSR_BASE+0x018) /* read external chip pins */
128 #define CSR_RESET (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/
129 #define CSR_GP_CNTRL (CSR_BASE+0x024)
130 #define CSR_HW_REV (CSR_BASE+0x028)
131 #define CSR_EEPROM_REG (CSR_BASE+0x02c)
132 #define CSR_EEPROM_GP (CSR_BASE+0x030)
133 #define CSR_GP_UCODE (CSR_BASE+0x044)
134 #define CSR_UCODE_DRV_GP1 (CSR_BASE+0x054)
135 #define CSR_UCODE_DRV_GP1_SET (CSR_BASE+0x058)
136 #define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c)
137 #define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060)
138 #define CSR_LED_REG (CSR_BASE+0x094)
139 #define CSR_DRAM_INT_TBL_CTL (CSR_BASE+0x0A0)
140 #define CSR_GIO_CHICKEN_BITS (CSR_BASE+0x100)
141 #define CSR_ANA_PLL_CFG (CSR_BASE+0x20c)
142 #define CSR_HW_REV_WA_REG (CSR_BASE+0x22C)
144 /* HW I/F configuration */
145 #define CSR_HW_IF_CONFIG_REG_BIT_ALMAGOR_MB (0x00000100)
146 #define CSR_HW_IF_CONFIG_REG_BIT_ALMAGOR_MM (0x00000200)
147 #define CSR_HW_IF_CONFIG_REG_BIT_SKU_MRC (0x00000400)
148 #define CSR_HW_IF_CONFIG_REG_BIT_BOARD_TYPE (0x00000800)
149 #define CSR_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A (0x00000000)
150 #define CSR_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B (0x00001000)
151 #define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM (0x00200000)
153 /* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
154 * acknowledged (reset) by host writing "1" to flagged bits. */
155 #define CSR_INT_BIT_FH_RX (1<<31) /* Rx DMA, cmd responses, FH_INT[17:16] */
156 #define CSR_INT_BIT_HW_ERR (1<<29) /* DMA hardware error FH_INT[31] */
157 #define CSR_INT_BIT_DNLD (1<<28) /* uCode Download */
158 #define CSR_INT_BIT_FH_TX (1<<27) /* Tx DMA FH_INT[1:0] */
159 #define CSR_INT_BIT_MAC_CLK_ACTV (1<<26) /* NIC controller's clock toggled on/off */
160 #define CSR_INT_BIT_SW_ERR (1<<25) /* uCode error */
161 #define CSR_INT_BIT_RF_KILL (1<<7) /* HW RFKILL switch GP_CNTRL[27] toggled */
162 #define CSR_INT_BIT_CT_KILL (1<<6) /* Critical temp (chip too hot) rfkill */
163 #define CSR_INT_BIT_SW_RX (1<<3) /* Rx, command responses, 3945 */
164 #define CSR_INT_BIT_WAKEUP (1<<1) /* NIC controller waking up (pwr mgmt) */
165 #define CSR_INT_BIT_ALIVE (1<<0) /* uCode interrupts once it initializes */
167 #define CSR_INI_SET_MASK (CSR_INT_BIT_FH_RX | \
168 CSR_INT_BIT_HW_ERR | \
169 CSR_INT_BIT_FH_TX | \
170 CSR_INT_BIT_SW_ERR | \
171 CSR_INT_BIT_RF_KILL | \
172 CSR_INT_BIT_SW_RX | \
173 CSR_INT_BIT_WAKEUP | \
176 /* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
177 #define CSR_FH_INT_BIT_ERR (1<<31) /* Error */
178 #define CSR_FH_INT_BIT_HI_PRIOR (1<<30) /* High priority Rx, bypass coalescing */
179 #define CSR_FH_INT_BIT_RX_CHNL2 (1<<18) /* Rx channel 2 (3945 only) */
180 #define CSR_FH_INT_BIT_RX_CHNL1 (1<<17) /* Rx channel 1 */
181 #define CSR_FH_INT_BIT_RX_CHNL0 (1<<16) /* Rx channel 0 */
182 #define CSR_FH_INT_BIT_TX_CHNL6 (1<<6) /* Tx channel 6 (3945 only) */
183 #define CSR_FH_INT_BIT_TX_CHNL1 (1<<1) /* Tx channel 1 */
184 #define CSR_FH_INT_BIT_TX_CHNL0 (1<<0) /* Tx channel 0 */
186 #define CSR_FH_INT_RX_MASK (CSR_FH_INT_BIT_HI_PRIOR | \
187 CSR_FH_INT_BIT_RX_CHNL2 | \
188 CSR_FH_INT_BIT_RX_CHNL1 | \
189 CSR_FH_INT_BIT_RX_CHNL0)
191 #define CSR_FH_INT_TX_MASK (CSR_FH_INT_BIT_TX_CHNL6 | \
192 CSR_FH_INT_BIT_TX_CHNL1 | \
193 CSR_FH_INT_BIT_TX_CHNL0 )
197 #define CSR_RESET_REG_FLAG_NEVO_RESET (0x00000001)
198 #define CSR_RESET_REG_FLAG_FORCE_NMI (0x00000002)
199 #define CSR_RESET_REG_FLAG_SW_RESET (0x00000080)
200 #define CSR_RESET_REG_FLAG_MASTER_DISABLED (0x00000100)
201 #define CSR_RESET_REG_FLAG_STOP_MASTER (0x00000200)
203 /* GP (general purpose) CONTROL */
204 #define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY (0x00000001)
205 #define CSR_GP_CNTRL_REG_FLAG_INIT_DONE (0x00000004)
206 #define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ (0x00000008)
207 #define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP (0x00000010)
209 #define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN (0x00000001)
211 #define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE (0x07000000)
212 #define CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE (0x04000000)
213 #define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW (0x08000000)
217 #define CSR_EEPROM_REG_READ_VALID_MSK (0x00000001)
218 #define CSR_EEPROM_REG_BIT_CMD (0x00000002)
221 #define CSR_EEPROM_GP_VALID_MSK (0x00000006)
222 #define CSR_EEPROM_GP_BAD_SIGNATURE (0x00000000)
223 #define CSR_EEPROM_GP_IF_OWNER_MSK (0x00000180)
226 #define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP (0x00000001)
227 #define CSR_UCODE_SW_BIT_RFKILL (0x00000002)
228 #define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED (0x00000004)
229 #define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT (0x00000008)
232 #define CSR_GPIO_IN_BIT_AUX_POWER (0x00000200)
233 #define CSR_GPIO_IN_VAL_VAUX_PWR_SRC (0x00000000)
234 #define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC CSR_GPIO_IN_BIT_AUX_POWER
236 /* GI Chicken Bits */
237 #define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX (0x00800000)
238 #define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER (0x20000000)
240 /* CSR_ANA_PLL_CFG */
241 #define CSR_ANA_PLL_CFG_SH (0x00880300)
243 #define CSR_LED_REG_TRUN_ON (0x00000078)
244 #define CSR_LED_REG_TRUN_OFF (0x00000038)
245 #define CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF)
247 /* DRAM_INT_TBL_CTRL */
248 #define CSR_DRAM_INT_TBL_CTRL_EN (1<<31)
249 #define CSR_DRAM_INT_TBL_CTRL_WRAP_CHK (1<<27)
251 /*=== HBUS (Host-side Bus) ===*/
252 #define HBUS_BASE (0x400)
254 #define HBUS_TARG_MEM_RADDR (HBUS_BASE+0x00c)
255 #define HBUS_TARG_MEM_WADDR (HBUS_BASE+0x010)
256 #define HBUS_TARG_MEM_WDAT (HBUS_BASE+0x018)
257 #define HBUS_TARG_MEM_RDAT (HBUS_BASE+0x01c)
258 #define HBUS_TARG_PRPH_WADDR (HBUS_BASE+0x044)
259 #define HBUS_TARG_PRPH_RADDR (HBUS_BASE+0x048)
260 #define HBUS_TARG_PRPH_WDAT (HBUS_BASE+0x04c)
261 #define HBUS_TARG_PRPH_RDAT (HBUS_BASE+0x050)
262 #define HBUS_TARG_WRPTR (HBUS_BASE+0x060)
264 #define HBUS_TARG_MBX_C (HBUS_BASE+0x030)
267 /* SCD (Scheduler) */
268 #define SCD_BASE (CSR_BASE + 0x2E00)
270 #define SCD_MODE_REG (SCD_BASE + 0x000)
271 #define SCD_ARASTAT_REG (SCD_BASE + 0x004)
272 #define SCD_TXFACT_REG (SCD_BASE + 0x010)
273 #define SCD_TXF4MF_REG (SCD_BASE + 0x014)
274 #define SCD_TXF5MF_REG (SCD_BASE + 0x020)
275 #define SCD_SBYP_MODE_1_REG (SCD_BASE + 0x02C)
276 #define SCD_SBYP_MODE_2_REG (SCD_BASE + 0x030)
278 /*=== FH (data Flow Handler) ===*/
279 #define FH_BASE (0x800)
281 #define FH_CBCC_TABLE (FH_BASE+0x140)
282 #define FH_TFDB_TABLE (FH_BASE+0x180)
283 #define FH_RCSR_TABLE (FH_BASE+0x400)
284 #define FH_RSSR_TABLE (FH_BASE+0x4c0)
285 #define FH_TCSR_TABLE (FH_BASE+0x500)
286 #define FH_TSSR_TABLE (FH_BASE+0x680)
288 /* TFDB (Transmit Frame Buffer Descriptor) */
289 #define FH_TFDB(_channel, buf) \
290 (FH_TFDB_TABLE+((_channel)*2+(buf))*0x28)
291 #define ALM_FH_TFDB_CHNL_BUF_CTRL_REG(_channel) \
292 (FH_TFDB_TABLE + 0x50 * _channel)
293 /* CBCC _channel is [0,2] */
294 #define FH_CBCC(_channel) (FH_CBCC_TABLE+(_channel)*0x8)
295 #define FH_CBCC_CTRL(_channel) (FH_CBCC(_channel)+0x00)
296 #define FH_CBCC_BASE(_channel) (FH_CBCC(_channel)+0x04)
298 /* RCSR _channel is [0,2] */
299 #define FH_RCSR(_channel) (FH_RCSR_TABLE+(_channel)*0x40)
300 #define FH_RCSR_CONFIG(_channel) (FH_RCSR(_channel)+0x00)
301 #define FH_RCSR_RBD_BASE(_channel) (FH_RCSR(_channel)+0x04)
302 #define FH_RCSR_WPTR(_channel) (FH_RCSR(_channel)+0x20)
303 #define FH_RCSR_RPTR_ADDR(_channel) (FH_RCSR(_channel)+0x24)
306 #define FH_RSCSR_CHNL0_WPTR (FH_RCSR_WPTR(0))
308 #define FH_RSCSR_CHNL0_WPTR (FH_RSCSR_CHNL0_RBDCB_WPTR_REG)
312 #define FH_RSSR_CTRL (FH_RSSR_TABLE+0x000)
313 #define FH_RSSR_STATUS (FH_RSSR_TABLE+0x004)
315 #define FH_TCSR(_channel) (FH_TCSR_TABLE+(_channel)*0x20)
316 #define FH_TCSR_CONFIG(_channel) (FH_TCSR(_channel)+0x00)
317 #define FH_TCSR_CREDIT(_channel) (FH_TCSR(_channel)+0x04)
318 #define FH_TCSR_BUFF_STTS(_channel) (FH_TCSR(_channel)+0x08)
320 #define FH_TSSR_CBB_BASE (FH_TSSR_TABLE+0x000)
321 #define FH_TSSR_MSG_CONFIG (FH_TSSR_TABLE+0x008)
322 #define FH_TSSR_TX_STATUS (FH_TSSR_TABLE+0x010)
325 /* card static random access memory (SRAM) for processor data and instructs */
326 #define RTC_INST_LOWER_BOUND (0x000000)
327 #define RTC_DATA_LOWER_BOUND (0x800000)
332 #define ALM_FH_SRVC_CHNL (6)
334 #define ALM_FH_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE (20)
335 #define ALM_FH_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH (4)
337 #define ALM_FH_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN (0x08000000)
339 #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE (0x80000000)
341 #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE (0x20000000)
343 #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 (0x01000000)
345 #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST (0x00001000)
347 #define ALM_FH_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH (0x00000000)
349 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF (0x00000000)
350 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_DRIVER (0x00000001)
352 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE_VAL (0x00000000)
353 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL (0x00000008)
355 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD (0x00200000)
357 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT (0x00000000)
359 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE (0x00000000)
360 #define ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE (0x80000000)
362 #define ALM_FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID (0x00004000)
364 #define ALM_FH_TCSR_CHNL_TX_BUF_STS_REG_BIT_TFDB_WPTR (0x00000001)
366 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON (0xFF000000)
367 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON (0x00FF0000)
369 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B (0x00000400)
371 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON (0x00000100)
372 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON (0x00000080)
374 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH (0x00000020)
375 #define ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH (0x00000005)
377 #define ALM_TB_MAX_BYTES_COUNT (0xFFF0)
379 #define ALM_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_channel) \
380 ((1LU << _channel) << 24)
381 #define ALM_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_channel) \
382 ((1LU << _channel) << 16)
384 #define ALM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(_channel) \
385 (ALM_FH_TSSR_TX_STATUS_REG_BIT_BUFS_EMPTY(_channel) | \
386 ALM_FH_TSSR_TX_STATUS_REG_BIT_NO_PEND_REQ(_channel))
387 #define PCI_CFG_REV_ID_BIT_BASIC_SKU (0x40) /* bit 6 */
388 #define PCI_CFG_REV_ID_BIT_RTP (0x80) /* bit 7 */
390 #define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED (0x00000004)
392 #define TFD_QUEUE_MIN 0
393 #define TFD_QUEUE_MAX 6
394 #define TFD_QUEUE_SIZE_MAX (256)
396 /* spectrum and channel data structures */
397 #define IWL_NUM_SCAN_RATES (2)
399 #define IWL_SCAN_FLAG_24GHZ (1<<0)
400 #define IWL_SCAN_FLAG_52GHZ (1<<1)
401 #define IWL_SCAN_FLAG_ACTIVE (1<<2)
402 #define IWL_SCAN_FLAG_DIRECT (1<<3)
404 #define IWL_MAX_CMD_SIZE 1024
406 #define IWL_DEFAULT_TX_RETRY 15
407 #define IWL_MAX_TX_RETRY 16
409 /*********************************************/
412 #define NUM_TFD_CHUNKS 4
414 #define RX_QUEUE_SIZE 256
415 #define RX_QUEUE_MASK 255
416 #define RX_QUEUE_SIZE_LOG 8
418 /* QoS definitions */
420 #define CW_MIN_OFDM 15
421 #define CW_MAX_OFDM 1023
422 #define CW_MIN_CCK 31
423 #define CW_MAX_CCK 1023
425 #define QOS_TX0_CW_MIN_OFDM CW_MIN_OFDM
426 #define QOS_TX1_CW_MIN_OFDM CW_MIN_OFDM
427 #define QOS_TX2_CW_MIN_OFDM ((CW_MIN_OFDM + 1) / 2 - 1)
428 #define QOS_TX3_CW_MIN_OFDM ((CW_MIN_OFDM + 1) / 4 - 1)
430 #define QOS_TX0_CW_MIN_CCK CW_MIN_CCK
431 #define QOS_TX1_CW_MIN_CCK CW_MIN_CCK
432 #define QOS_TX2_CW_MIN_CCK ((CW_MIN_CCK + 1) / 2 - 1)
433 #define QOS_TX3_CW_MIN_CCK ((CW_MIN_CCK + 1) / 4 - 1)
435 #define QOS_TX0_CW_MAX_OFDM CW_MAX_OFDM
436 #define QOS_TX1_CW_MAX_OFDM CW_MAX_OFDM
437 #define QOS_TX2_CW_MAX_OFDM CW_MIN_OFDM
438 #define QOS_TX3_CW_MAX_OFDM ((CW_MIN_OFDM + 1) / 2 - 1)
440 #define QOS_TX0_CW_MAX_CCK CW_MAX_CCK
441 #define QOS_TX1_CW_MAX_CCK CW_MAX_CCK
442 #define QOS_TX2_CW_MAX_CCK CW_MIN_CCK
443 #define QOS_TX3_CW_MAX_CCK ((CW_MIN_CCK + 1) / 2 - 1)
445 #define QOS_TX0_AIFS 3
446 #define QOS_TX1_AIFS 7
447 #define QOS_TX2_AIFS 2
448 #define QOS_TX3_AIFS 2
450 #define QOS_TX0_ACM 0
451 #define QOS_TX1_ACM 0
452 #define QOS_TX2_ACM 0
453 #define QOS_TX3_ACM 0
455 #define QOS_TX0_TXOP_LIMIT_CCK 0
456 #define QOS_TX1_TXOP_LIMIT_CCK 0
457 #define QOS_TX2_TXOP_LIMIT_CCK 6016
458 #define QOS_TX3_TXOP_LIMIT_CCK 3264
460 #define QOS_TX0_TXOP_LIMIT_OFDM 0
461 #define QOS_TX1_TXOP_LIMIT_OFDM 0
462 #define QOS_TX2_TXOP_LIMIT_OFDM 3008
463 #define QOS_TX3_TXOP_LIMIT_OFDM 1504
465 #define DEF_TX0_CW_MIN_OFDM CW_MIN_OFDM
466 #define DEF_TX1_CW_MIN_OFDM CW_MIN_OFDM
467 #define DEF_TX2_CW_MIN_OFDM CW_MIN_OFDM
468 #define DEF_TX3_CW_MIN_OFDM CW_MIN_OFDM
470 #define DEF_TX0_CW_MIN_CCK CW_MIN_CCK
471 #define DEF_TX1_CW_MIN_CCK CW_MIN_CCK
472 #define DEF_TX2_CW_MIN_CCK CW_MIN_CCK
473 #define DEF_TX3_CW_MIN_CCK CW_MIN_CCK
475 #define DEF_TX0_CW_MAX_OFDM CW_MAX_OFDM
476 #define DEF_TX1_CW_MAX_OFDM CW_MAX_OFDM
477 #define DEF_TX2_CW_MAX_OFDM CW_MAX_OFDM
478 #define DEF_TX3_CW_MAX_OFDM CW_MAX_OFDM
480 #define DEF_TX0_CW_MAX_CCK CW_MAX_CCK
481 #define DEF_TX1_CW_MAX_CCK CW_MAX_CCK
482 #define DEF_TX2_CW_MAX_CCK CW_MAX_CCK
483 #define DEF_TX3_CW_MAX_CCK CW_MAX_CCK
485 #define DEF_TX0_AIFS (2)
486 #define DEF_TX1_AIFS (2)
487 #define DEF_TX2_AIFS (2)
488 #define DEF_TX3_AIFS (2)
490 #define DEF_TX0_ACM 0
491 #define DEF_TX1_ACM 0
492 #define DEF_TX2_ACM 0
493 #define DEF_TX3_ACM 0
495 #define DEF_TX0_TXOP_LIMIT_CCK 0
496 #define DEF_TX1_TXOP_LIMIT_CCK 0
497 #define DEF_TX2_TXOP_LIMIT_CCK 0
498 #define DEF_TX3_TXOP_LIMIT_CCK 0
500 #define DEF_TX0_TXOP_LIMIT_OFDM 0
501 #define DEF_TX1_TXOP_LIMIT_OFDM 0
502 #define DEF_TX2_TXOP_LIMIT_OFDM 0
503 #define DEF_TX3_TXOP_LIMIT_OFDM 0
505 #define QOS_QOS_SETS 3
506 #define QOS_PARAM_SET_ACTIVE 0
507 #define QOS_PARAM_SET_DEF_CCK 1
508 #define QOS_PARAM_SET_DEF_OFDM 2
510 #define CTRL_QOS_NO_ACK (0x0020)
511 #define DCT_FLAG_EXT_QOS_ENABLED (0x10)
513 #define U32_PAD(n) ((4-(n))&0x3)
516 * Generic queue structure
518 * Contains common data for Rx and Tx queues
520 #define TFD_CTL_COUNT_SET(n) (n<<24)
521 #define TFD_CTL_COUNT_GET(ctl) ((ctl>>24) & 7)
522 #define TFD_CTL_PAD_SET(n) (n<<28)
523 #define TFD_CTL_PAD_GET(ctl) (ctl>>28)
525 #define TFD_TX_CMD_SLOTS 256
526 #define TFD_CMD_SLOTS 32
528 #define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_cmd) - \
529 sizeof(struct iwl_cmd_meta))
532 * RX related structures and functions
534 #define RX_FREE_BUFFERS 64
535 #define RX_LOW_WATERMARK 8
537 #endif /* __iwlwifi_hw_h__ */
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