1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2008 - 2009 Intel Corporation. All rights reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of version 2 of the GNU General Public License as
12 * published by the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but
15 * WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
24 * The full GNU General Public License is included in this distribution
25 * in the file called LICENSE.GPL.
27 * Contact Information:
28 * Intel Linux Wireless <ilw@linux.intel.com>
29 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
33 * Copyright(c) 2005 - 2009 Intel Corporation. All rights reserved.
34 * All rights reserved.
36 * Redistribution and use in source and binary forms, with or without
37 * modification, are permitted provided that the following conditions
40 * * Redistributions of source code must retain the above copyright
41 * notice, this list of conditions and the following disclaimer.
42 * * Redistributions in binary form must reproduce the above copyright
43 * notice, this list of conditions and the following disclaimer in
44 * the documentation and/or other materials provided with the
46 * * Neither the name Intel Corporation nor the names of its
47 * contributors may be used to endorse or promote products derived
48 * from this software without specific prior written permission.
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
51 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
52 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
53 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
54 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
55 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
56 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
57 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
58 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
59 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
60 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
61 *****************************************************************************/
64 #include <linux/kernel.h>
65 #include <linux/module.h>
66 #include <linux/init.h>
68 #include <net/mac80211.h>
70 #include "iwl-commands.h"
73 #include "iwl-debug.h"
74 #include "iwl-eeprom.h"
77 /************************** EEPROM BANDS ****************************
79 * The iwl_eeprom_band definitions below provide the mapping from the
80 * EEPROM contents to the specific channel number supported for each
83 * For example, iwl_priv->eeprom.band_3_channels[4] from the band_3
84 * definition below maps to physical channel 42 in the 5.2GHz spectrum.
85 * The specific geography and calibration information for that channel
86 * is contained in the eeprom map itself.
88 * During init, we copy the eeprom information and channel map
89 * information into priv->channel_info_24/52 and priv->channel_map_24/52
91 * channel_map_24/52 provides the index in the channel_info array for a
92 * given channel. We have to have two separate maps as there is channel
93 * overlap with the 2.4GHz and 5.2GHz spectrum as seen in band_1 and
96 * A value of 0xff stored in the channel_map indicates that the channel
97 * is not supported by the hardware at all.
99 * A value of 0xfe in the channel_map indicates that the channel is not
100 * valid for Tx with the current hardware. This means that
101 * while the system can tune and receive on a given channel, it may not
102 * be able to associate or transmit any frames on that
103 * channel. There is no corresponding channel information for that
106 *********************************************************************/
109 const u8 iwl_eeprom_band_1[14] = {
110 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14
114 static const u8 iwl_eeprom_band_2[] = { /* 4915-5080MHz */
115 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16
118 static const u8 iwl_eeprom_band_3[] = { /* 5170-5320MHz */
119 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64
122 static const u8 iwl_eeprom_band_4[] = { /* 5500-5700MHz */
123 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140
126 static const u8 iwl_eeprom_band_5[] = { /* 5725-5825MHz */
127 145, 149, 153, 157, 161, 165
130 static const u8 iwl_eeprom_band_6[] = { /* 2.4 ht40 channel */
134 static const u8 iwl_eeprom_band_7[] = { /* 5.2 ht40 channel */
135 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157
138 /******************************************************************************
140 * EEPROM related functions
142 ******************************************************************************/
144 int iwlcore_eeprom_verify_signature(struct iwl_priv *priv)
146 u32 gp = iwl_read32(priv, CSR_EEPROM_GP);
147 if ((gp & CSR_EEPROM_GP_VALID_MSK) == CSR_EEPROM_GP_BAD_SIGNATURE) {
148 IWL_ERR(priv, "EEPROM not found, EEPROM_GP=0x%08x\n", gp);
153 EXPORT_SYMBOL(iwlcore_eeprom_verify_signature);
155 static void iwl_set_otp_access(struct iwl_priv *priv, enum iwl_access_mode mode)
159 otpgp = iwl_read32(priv, CSR_OTP_GP_REG);
160 if (mode == IWL_OTP_ACCESS_ABSOLUTE)
161 iwl_clear_bit(priv, CSR_OTP_GP_REG,
162 CSR_OTP_GP_REG_OTP_ACCESS_MODE);
164 iwl_set_bit(priv, CSR_OTP_GP_REG,
165 CSR_OTP_GP_REG_OTP_ACCESS_MODE);
168 static int iwlcore_get_nvm_type(struct iwl_priv *priv)
173 /* OTP only valid for CP/PP and after */
174 switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
175 case CSR_HW_REV_TYPE_NONE:
176 IWL_ERR(priv, "Unknown hardware type\n");
178 case CSR_HW_REV_TYPE_3945:
179 case CSR_HW_REV_TYPE_4965:
180 case CSR_HW_REV_TYPE_5300:
181 case CSR_HW_REV_TYPE_5350:
182 case CSR_HW_REV_TYPE_5100:
183 case CSR_HW_REV_TYPE_5150:
184 nvm_type = NVM_DEVICE_TYPE_EEPROM;
187 otpgp = iwl_read32(priv, CSR_OTP_GP_REG);
188 if (otpgp & CSR_OTP_GP_REG_DEVICE_SELECT)
189 nvm_type = NVM_DEVICE_TYPE_OTP;
191 nvm_type = NVM_DEVICE_TYPE_EEPROM;
198 * The device's EEPROM semaphore prevents conflicts between driver and uCode
199 * when accessing the EEPROM; each access is a series of pulses to/from the
200 * EEPROM chip, not a single event, so even reads could conflict if they
201 * weren't arbitrated by the semaphore.
203 int iwlcore_eeprom_acquire_semaphore(struct iwl_priv *priv)
208 for (count = 0; count < EEPROM_SEM_RETRY_LIMIT; count++) {
209 /* Request semaphore */
210 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
211 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
213 /* See if we got it */
214 ret = iwl_poll_direct_bit(priv, CSR_HW_IF_CONFIG_REG,
215 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
218 IWL_DEBUG_IO(priv, "Acquired semaphore after %d tries.\n",
226 EXPORT_SYMBOL(iwlcore_eeprom_acquire_semaphore);
228 void iwlcore_eeprom_release_semaphore(struct iwl_priv *priv)
230 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
231 CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
234 EXPORT_SYMBOL(iwlcore_eeprom_release_semaphore);
236 const u8 *iwlcore_eeprom_query_addr(const struct iwl_priv *priv, size_t offset)
238 BUG_ON(offset >= priv->cfg->eeprom_size);
239 return &priv->eeprom[offset];
241 EXPORT_SYMBOL(iwlcore_eeprom_query_addr);
243 static int iwl_init_otp_access(struct iwl_priv *priv)
247 /* Enable 40MHz radio clock */
248 _iwl_write32(priv, CSR_GP_CNTRL,
249 _iwl_read32(priv, CSR_GP_CNTRL) |
250 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
252 /* wait for clock to be ready */
253 ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
254 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
257 IWL_ERR(priv, "Time out access OTP\n");
259 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG,
260 APMG_PS_CTRL_VAL_RESET_REQ);
262 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG,
263 APMG_PS_CTRL_VAL_RESET_REQ);
268 static int iwl_read_otp_word(struct iwl_priv *priv, u16 addr, u16 *eeprom_data)
274 _iwl_write32(priv, CSR_EEPROM_REG,
275 CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
276 ret = iwl_poll_direct_bit(priv, CSR_EEPROM_REG,
277 CSR_EEPROM_REG_READ_VALID_MSK,
278 IWL_EEPROM_ACCESS_TIMEOUT);
280 IWL_ERR(priv, "Time out reading OTP[%d]\n", addr);
283 r = _iwl_read_direct32(priv, CSR_EEPROM_REG);
284 /* check for ECC errors: */
285 otpgp = iwl_read32(priv, CSR_OTP_GP_REG);
286 if (otpgp & CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK) {
287 /* stop in this case */
288 /* set the uncorrectable OTP ECC bit for acknowledgement */
289 iwl_set_bit(priv, CSR_OTP_GP_REG,
290 CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);
291 IWL_ERR(priv, "Uncorrectable OTP ECC error, abort OTP read\n");
294 if (otpgp & CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK) {
295 /* continue in this case */
296 /* set the correctable OTP ECC bit for acknowledgement */
297 iwl_set_bit(priv, CSR_OTP_GP_REG,
298 CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK);
299 IWL_ERR(priv, "Correctable OTP ECC error, continue read\n");
301 *eeprom_data = le16_to_cpu((__force __le16)(r >> 16));
306 * iwl_is_otp_empty: check for empty OTP
308 static bool iwl_is_otp_empty(struct iwl_priv *priv)
310 u16 next_link_addr = 0, link_value;
311 bool is_empty = false;
313 /* locate the beginning of OTP link list */
314 if (!iwl_read_otp_word(priv, next_link_addr, &link_value)) {
316 IWL_ERR(priv, "OTP is empty\n");
320 IWL_ERR(priv, "Unable to read first block of OTP list.\n");
329 * iwl_find_otp_image: find EEPROM image in OTP
330 * finding the OTP block that contains the EEPROM image.
331 * the last valid block on the link list (the block _before_ the last block)
332 * is the block we should read and used to configure the device.
333 * If all the available OTP blocks are full, the last block will be the block
334 * we should read and used to configure the device.
335 * only perform this operation if shadow RAM is disabled
337 static int iwl_find_otp_image(struct iwl_priv *priv,
340 u16 next_link_addr = 0, link_value = 0, valid_addr;
344 /* set addressing mode to absolute to traverse the link list */
345 iwl_set_otp_access(priv, IWL_OTP_ACCESS_ABSOLUTE);
347 /* checking for empty OTP or error */
348 if (iwl_is_otp_empty(priv))
352 * start traverse link list
353 * until reach the max number of OTP blocks
354 * different devices have different number of OTP blocks
357 /* save current valid block address
358 * check for more block on the link list
360 valid_addr = next_link_addr;
361 next_link_addr = link_value;
362 IWL_DEBUG_INFO(priv, "OTP blocks %d addr 0x%x\n",
363 usedblocks, next_link_addr);
364 if (iwl_read_otp_word(priv, next_link_addr, &link_value))
368 * reach the end of link list,
369 * set address point to the starting address
374 /* more in the link list, continue */
376 } while (usedblocks < priv->cfg->max_ll_items);
377 /* OTP full, use last block */
378 IWL_DEBUG_INFO(priv, "OTP is full, use last block\n");
380 *validblockaddr = valid_addr;
381 /* skip first 2 bytes (link list pointer) */
382 *validblockaddr += 2;
387 * iwl_eeprom_init - read EEPROM contents
389 * Load the EEPROM contents from adapter into priv->eeprom
391 * NOTE: This routine uses the non-debug IO access functions.
393 int iwl_eeprom_init(struct iwl_priv *priv)
396 u32 gp = iwl_read32(priv, CSR_EEPROM_GP);
400 u16 validblockaddr = 0;
403 priv->nvm_device_type = iwlcore_get_nvm_type(priv);
404 if (priv->nvm_device_type == -ENOENT)
406 /* allocate eeprom */
407 IWL_DEBUG_INFO(priv, "NVM size = %d\n", priv->cfg->eeprom_size);
408 sz = priv->cfg->eeprom_size;
409 priv->eeprom = kzalloc(sz, GFP_KERNEL);
414 e = (u16 *)priv->eeprom;
416 ret = priv->cfg->ops->lib->eeprom_ops.verify_signature(priv);
418 IWL_ERR(priv, "EEPROM not found, EEPROM_GP=0x%08x\n", gp);
423 /* Make sure driver (instead of uCode) is allowed to read EEPROM */
424 ret = priv->cfg->ops->lib->eeprom_ops.acquire_semaphore(priv);
426 IWL_ERR(priv, "Failed to acquire EEPROM semaphore.\n");
430 if (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP) {
431 ret = iwl_init_otp_access(priv);
433 IWL_ERR(priv, "Failed to initialize OTP access.\n");
437 _iwl_write32(priv, CSR_EEPROM_GP,
438 iwl_read32(priv, CSR_EEPROM_GP) &
439 ~CSR_EEPROM_GP_IF_OWNER_MSK);
441 iwl_set_bit(priv, CSR_OTP_GP_REG,
442 CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK |
443 CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK);
444 /* traversing the linked list if no shadow ram supported */
445 if (!priv->cfg->shadow_ram_support) {
446 if (iwl_find_otp_image(priv, &validblockaddr)) {
451 for (addr = validblockaddr; addr < validblockaddr + sz;
452 addr += sizeof(u16)) {
455 ret = iwl_read_otp_word(priv, addr, &eeprom_data);
458 e[cache_addr / 2] = eeprom_data;
459 cache_addr += sizeof(u16);
462 /* eeprom is an array of 16bit values */
463 for (addr = 0; addr < sz; addr += sizeof(u16)) {
466 _iwl_write32(priv, CSR_EEPROM_REG,
467 CSR_EEPROM_REG_MSK_ADDR & (addr << 1));
469 ret = iwl_poll_direct_bit(priv, CSR_EEPROM_REG,
470 CSR_EEPROM_REG_READ_VALID_MSK,
471 IWL_EEPROM_ACCESS_TIMEOUT);
473 IWL_ERR(priv, "Time out reading EEPROM[%d]\n", addr);
476 r = _iwl_read_direct32(priv, CSR_EEPROM_REG);
477 e[addr / 2] = le16_to_cpu((__force __le16)(r >> 16));
482 priv->cfg->ops->lib->eeprom_ops.release_semaphore(priv);
485 iwl_eeprom_free(priv);
489 EXPORT_SYMBOL(iwl_eeprom_init);
491 void iwl_eeprom_free(struct iwl_priv *priv)
496 EXPORT_SYMBOL(iwl_eeprom_free);
498 int iwl_eeprom_check_version(struct iwl_priv *priv)
503 eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
504 calib_ver = priv->cfg->ops->lib->eeprom_ops.calib_version(priv);
506 if (eeprom_ver < priv->cfg->eeprom_ver ||
507 calib_ver < priv->cfg->eeprom_calib_ver)
512 IWL_ERR(priv, "Unsupported (too old) EEPROM VER=0x%x < 0x%x CALIB=0x%x < 0x%x\n",
513 eeprom_ver, priv->cfg->eeprom_ver,
514 calib_ver, priv->cfg->eeprom_calib_ver);
518 EXPORT_SYMBOL(iwl_eeprom_check_version);
520 const u8 *iwl_eeprom_query_addr(const struct iwl_priv *priv, size_t offset)
522 return priv->cfg->ops->lib->eeprom_ops.query_addr(priv, offset);
524 EXPORT_SYMBOL(iwl_eeprom_query_addr);
526 u16 iwl_eeprom_query16(const struct iwl_priv *priv, size_t offset)
530 return (u16)priv->eeprom[offset] | ((u16)priv->eeprom[offset + 1] << 8);
532 EXPORT_SYMBOL(iwl_eeprom_query16);
534 void iwl_eeprom_get_mac(const struct iwl_priv *priv, u8 *mac)
536 const u8 *addr = priv->cfg->ops->lib->eeprom_ops.query_addr(priv,
538 memcpy(mac, addr, ETH_ALEN);
540 EXPORT_SYMBOL(iwl_eeprom_get_mac);
542 static void iwl_init_band_reference(const struct iwl_priv *priv,
543 int eep_band, int *eeprom_ch_count,
544 const struct iwl_eeprom_channel **eeprom_ch_info,
545 const u8 **eeprom_ch_index)
547 u32 offset = priv->cfg->ops->lib->
548 eeprom_ops.regulatory_bands[eep_band - 1];
550 case 1: /* 2.4GHz band */
551 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_1);
552 *eeprom_ch_info = (struct iwl_eeprom_channel *)
553 iwl_eeprom_query_addr(priv, offset);
554 *eeprom_ch_index = iwl_eeprom_band_1;
556 case 2: /* 4.9GHz band */
557 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_2);
558 *eeprom_ch_info = (struct iwl_eeprom_channel *)
559 iwl_eeprom_query_addr(priv, offset);
560 *eeprom_ch_index = iwl_eeprom_band_2;
562 case 3: /* 5.2GHz band */
563 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_3);
564 *eeprom_ch_info = (struct iwl_eeprom_channel *)
565 iwl_eeprom_query_addr(priv, offset);
566 *eeprom_ch_index = iwl_eeprom_band_3;
568 case 4: /* 5.5GHz band */
569 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_4);
570 *eeprom_ch_info = (struct iwl_eeprom_channel *)
571 iwl_eeprom_query_addr(priv, offset);
572 *eeprom_ch_index = iwl_eeprom_band_4;
574 case 5: /* 5.7GHz band */
575 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_5);
576 *eeprom_ch_info = (struct iwl_eeprom_channel *)
577 iwl_eeprom_query_addr(priv, offset);
578 *eeprom_ch_index = iwl_eeprom_band_5;
580 case 6: /* 2.4GHz ht40 channels */
581 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_6);
582 *eeprom_ch_info = (struct iwl_eeprom_channel *)
583 iwl_eeprom_query_addr(priv, offset);
584 *eeprom_ch_index = iwl_eeprom_band_6;
586 case 7: /* 5 GHz ht40 channels */
587 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_7);
588 *eeprom_ch_info = (struct iwl_eeprom_channel *)
589 iwl_eeprom_query_addr(priv, offset);
590 *eeprom_ch_index = iwl_eeprom_band_7;
598 #define CHECK_AND_PRINT(x) ((eeprom_ch->flags & EEPROM_CHANNEL_##x) \
602 * iwl_mod_ht40_chan_info - Copy ht40 channel info into driver's priv.
604 * Does not set up a command, or touch hardware.
606 static int iwl_mod_ht40_chan_info(struct iwl_priv *priv,
607 enum ieee80211_band band, u16 channel,
608 const struct iwl_eeprom_channel *eeprom_ch,
609 u8 clear_ht40_extension_channel)
611 struct iwl_channel_info *ch_info;
613 ch_info = (struct iwl_channel_info *)
614 iwl_get_channel_info(priv, band, channel);
616 if (!is_channel_valid(ch_info))
619 IWL_DEBUG_INFO(priv, "HT40 Ch. %d [%sGHz] %s%s%s%s%s(0x%02x %ddBm):"
620 " Ad-Hoc %ssupported\n",
622 is_channel_a_band(ch_info) ?
624 CHECK_AND_PRINT(IBSS),
625 CHECK_AND_PRINT(ACTIVE),
626 CHECK_AND_PRINT(RADAR),
627 CHECK_AND_PRINT(WIDE),
628 CHECK_AND_PRINT(DFS),
630 eeprom_ch->max_power_avg,
631 ((eeprom_ch->flags & EEPROM_CHANNEL_IBSS)
632 && !(eeprom_ch->flags & EEPROM_CHANNEL_RADAR)) ?
635 ch_info->ht40_eeprom = *eeprom_ch;
636 ch_info->ht40_max_power_avg = eeprom_ch->max_power_avg;
637 ch_info->ht40_curr_txpow = eeprom_ch->max_power_avg;
638 ch_info->ht40_min_power = 0;
639 ch_info->ht40_scan_power = eeprom_ch->max_power_avg;
640 ch_info->ht40_flags = eeprom_ch->flags;
641 ch_info->ht40_extension_channel &= ~clear_ht40_extension_channel;
646 #define CHECK_AND_PRINT_I(x) ((eeprom_ch_info[ch].flags & EEPROM_CHANNEL_##x) \
650 * iwl_init_channel_map - Set up driver's info for all possible channels
652 int iwl_init_channel_map(struct iwl_priv *priv)
654 int eeprom_ch_count = 0;
655 const u8 *eeprom_ch_index = NULL;
656 const struct iwl_eeprom_channel *eeprom_ch_info = NULL;
658 struct iwl_channel_info *ch_info;
660 if (priv->channel_count) {
661 IWL_DEBUG_INFO(priv, "Channel map already initialized.\n");
665 IWL_DEBUG_INFO(priv, "Initializing regulatory info from EEPROM\n");
667 priv->channel_count =
668 ARRAY_SIZE(iwl_eeprom_band_1) +
669 ARRAY_SIZE(iwl_eeprom_band_2) +
670 ARRAY_SIZE(iwl_eeprom_band_3) +
671 ARRAY_SIZE(iwl_eeprom_band_4) +
672 ARRAY_SIZE(iwl_eeprom_band_5);
674 IWL_DEBUG_INFO(priv, "Parsing data for %d channels.\n", priv->channel_count);
676 priv->channel_info = kzalloc(sizeof(struct iwl_channel_info) *
677 priv->channel_count, GFP_KERNEL);
678 if (!priv->channel_info) {
679 IWL_ERR(priv, "Could not allocate channel_info\n");
680 priv->channel_count = 0;
684 ch_info = priv->channel_info;
686 /* Loop through the 5 EEPROM bands adding them in order to the
687 * channel map we maintain (that contains additional information than
688 * what just in the EEPROM) */
689 for (band = 1; band <= 5; band++) {
691 iwl_init_band_reference(priv, band, &eeprom_ch_count,
692 &eeprom_ch_info, &eeprom_ch_index);
694 /* Loop through each band adding each of the channels */
695 for (ch = 0; ch < eeprom_ch_count; ch++) {
696 ch_info->channel = eeprom_ch_index[ch];
697 ch_info->band = (band == 1) ? IEEE80211_BAND_2GHZ :
700 /* permanently store EEPROM's channel regulatory flags
701 * and max power in channel info database. */
702 ch_info->eeprom = eeprom_ch_info[ch];
704 /* Copy the run-time flags so they are there even on
705 * invalid channels */
706 ch_info->flags = eeprom_ch_info[ch].flags;
707 /* First write that ht40 is not enabled, and then enable
709 ch_info->ht40_extension_channel =
710 IEEE80211_CHAN_NO_HT40;
712 if (!(is_channel_valid(ch_info))) {
713 IWL_DEBUG_INFO(priv, "Ch. %d Flags %x [%sGHz] - "
717 is_channel_a_band(ch_info) ?
723 /* Initialize regulatory-based run-time data */
724 ch_info->max_power_avg = ch_info->curr_txpow =
725 eeprom_ch_info[ch].max_power_avg;
726 ch_info->scan_power = eeprom_ch_info[ch].max_power_avg;
727 ch_info->min_power = 0;
729 IWL_DEBUG_INFO(priv, "Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x %ddBm):"
730 " Ad-Hoc %ssupported\n",
732 is_channel_a_band(ch_info) ?
734 CHECK_AND_PRINT_I(VALID),
735 CHECK_AND_PRINT_I(IBSS),
736 CHECK_AND_PRINT_I(ACTIVE),
737 CHECK_AND_PRINT_I(RADAR),
738 CHECK_AND_PRINT_I(WIDE),
739 CHECK_AND_PRINT_I(DFS),
740 eeprom_ch_info[ch].flags,
741 eeprom_ch_info[ch].max_power_avg,
742 ((eeprom_ch_info[ch].
743 flags & EEPROM_CHANNEL_IBSS)
744 && !(eeprom_ch_info[ch].
745 flags & EEPROM_CHANNEL_RADAR))
748 /* Set the tx_power_user_lmt to the highest power
749 * supported by any channel */
750 if (eeprom_ch_info[ch].max_power_avg >
751 priv->tx_power_user_lmt)
752 priv->tx_power_user_lmt =
753 eeprom_ch_info[ch].max_power_avg;
759 /* Check if we do have HT40 channels */
760 if (priv->cfg->ops->lib->eeprom_ops.regulatory_bands[5] ==
761 EEPROM_REGULATORY_BAND_NO_HT40 &&
762 priv->cfg->ops->lib->eeprom_ops.regulatory_bands[6] ==
763 EEPROM_REGULATORY_BAND_NO_HT40)
766 /* Two additional EEPROM bands for 2.4 and 5 GHz HT40 channels */
767 for (band = 6; band <= 7; band++) {
768 enum ieee80211_band ieeeband;
770 iwl_init_band_reference(priv, band, &eeprom_ch_count,
771 &eeprom_ch_info, &eeprom_ch_index);
773 /* EEPROM band 6 is 2.4, band 7 is 5 GHz */
775 (band == 6) ? IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
777 /* Loop through each band adding each of the channels */
778 for (ch = 0; ch < eeprom_ch_count; ch++) {
779 /* Set up driver's info for lower half */
780 iwl_mod_ht40_chan_info(priv, ieeeband,
783 IEEE80211_CHAN_NO_HT40PLUS);
785 /* Set up driver's info for upper half */
786 iwl_mod_ht40_chan_info(priv, ieeeband,
787 eeprom_ch_index[ch] + 4,
789 IEEE80211_CHAN_NO_HT40MINUS);
795 EXPORT_SYMBOL(iwl_init_channel_map);
798 * iwl_free_channel_map - undo allocations in iwl_init_channel_map
800 void iwl_free_channel_map(struct iwl_priv *priv)
802 kfree(priv->channel_info);
803 priv->channel_count = 0;
805 EXPORT_SYMBOL(iwl_free_channel_map);
808 * iwl_get_channel_info - Find driver's private channel info
810 * Based on band and channel number.
812 const struct iwl_channel_info *iwl_get_channel_info(const struct iwl_priv *priv,
813 enum ieee80211_band band, u16 channel)
818 case IEEE80211_BAND_5GHZ:
819 for (i = 14; i < priv->channel_count; i++) {
820 if (priv->channel_info[i].channel == channel)
821 return &priv->channel_info[i];
824 case IEEE80211_BAND_2GHZ:
825 if (channel >= 1 && channel <= 14)
826 return &priv->channel_info[channel - 1];
834 EXPORT_SYMBOL(iwl_get_channel_info);