SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/iwlwifi/iwl-5000.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2010 Intel Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  23  *
  24  *****************************************************************************/
  25
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28 #include <linux/init.h>
  29 #include <linux/pci.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/delay.h>
  32 #include <linux/sched.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/netdevice.h>
  35 #include <linux/wireless.h>
  36 #include <net/mac80211.h>
  37 #include <linux/etherdevice.h>
  38 #include <asm/unaligned.h>
  39
  40 #include "iwl-eeprom.h"
  41 #include "iwl-dev.h"
  42 #include "iwl-core.h"
  43 #include "iwl-io.h"
  44 #include "iwl-sta.h"
  45 #include "iwl-helpers.h"
  46 #include "iwl-agn.h"
  47 #include "iwl-agn-led.h"
  48 #include "iwl-5000-hw.h"
  49 #include "iwl-6000-hw.h"
  50
  51 /* Highest firmware API version supported */
  52 #define IWL5000_UCODE_API_MAX 2
  53 #define IWL5150_UCODE_API_MAX 2
  54
  55 /* Lowest firmware API version supported */
  56 #define IWL5000_UCODE_API_MIN 1
  57 #define IWL5150_UCODE_API_MIN 1
  58
  59 #define IWL5000_FW_PRE "iwlwifi-5000-"
  60 #define _IWL5000_MODULE_FIRMWARE(api) IWL5000_FW_PRE #api ".ucode"
  61 #define IWL5000_MODULE_FIRMWARE(api) _IWL5000_MODULE_FIRMWARE(api)
  62
  63 #define IWL5150_FW_PRE "iwlwifi-5150-"
  64 #define _IWL5150_MODULE_FIRMWARE(api) IWL5150_FW_PRE #api ".ucode"
  65 #define IWL5150_MODULE_FIRMWARE(api) _IWL5150_MODULE_FIRMWARE(api)
  66
  67 static const s8 iwl5000_default_queue_to_tx_fifo[] = {
  68         IWL_TX_FIFO_VO,
  69         IWL_TX_FIFO_VI,
  70         IWL_TX_FIFO_BE,
  71         IWL_TX_FIFO_BK,
  72         IWL50_CMD_FIFO_NUM,
  73         IWL_TX_FIFO_UNUSED,
  74         IWL_TX_FIFO_UNUSED,
  75         IWL_TX_FIFO_UNUSED,
  76         IWL_TX_FIFO_UNUSED,
  77         IWL_TX_FIFO_UNUSED,
  78 };
  79
  80 /* NIC configuration for 5000 series */
  81 void iwl5000_nic_config(struct iwl_priv *priv)
  82 {
  83         unsigned long flags;
  84         u16 radio_cfg;
  85
  86         spin_lock_irqsave(&priv->lock, flags);
  87
  88         radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
  89
  90         /* write radio config values to register */
  91         if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_RF_CONFIG_TYPE_MAX)
  92                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  93                             EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
  94                             EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
  95                             EEPROM_RF_CFG_DASH_MSK(radio_cfg));
  96
  97         /* set CSR_HW_CONFIG_REG for uCode use */
  98         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  99                     CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
 100                     CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
 101
 102         /* W/A : NIC is stuck in a reset state after Early PCIe power off
 103          * (PCIe power is lost before PERST# is asserted),
 104          * causing ME FW to lose ownership and not being able to obtain it back.
 105          */
 106         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 107                                 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
 108                                 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
 109
 110
 111         spin_unlock_irqrestore(&priv->lock, flags);
 112 }
 113
 114
 115 /*
 116  * EEPROM
 117  */
 118 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
 119 {
 120         u16 offset = 0;
 121
 122         if ((address & INDIRECT_ADDRESS) == 0)
 123                 return address;
 124
 125         switch (address & INDIRECT_TYPE_MSK) {
 126         case INDIRECT_HOST:
 127                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
 128                 break;
 129         case INDIRECT_GENERAL:
 130                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
 131                 break;
 132         case INDIRECT_REGULATORY:
 133                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
 134                 break;
 135         case INDIRECT_CALIBRATION:
 136                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
 137                 break;
 138         case INDIRECT_PROCESS_ADJST:
 139                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
 140                 break;
 141         case INDIRECT_OTHERS:
 142                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
 143                 break;
 144         default:
 145                 IWL_ERR(priv, "illegal indirect type: 0x%X\n",
 146                 address & INDIRECT_TYPE_MSK);
 147                 break;
 148         }
 149
 150         /* translate the offset from words to byte */
 151         return (address & ADDRESS_MSK) + (offset << 1);
 152 }
 153
 154 u16 iwl5000_eeprom_calib_version(struct iwl_priv *priv)
 155 {
 156         struct iwl_eeprom_calib_hdr {
 157                 u8 version;
 158                 u8 pa_type;
 159                 u16 voltage;
 160         } *hdr;
 161
 162         hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
 163                                                         EEPROM_5000_CALIB_ALL);
 164         return hdr->version;
 165
 166 }
 167
 168 static struct iwl_sensitivity_ranges iwl5000_sensitivity = {
 169         .min_nrg_cck = 95,
 170         .max_nrg_cck = 0, /* not used, set to 0 */
 171         .auto_corr_min_ofdm = 90,
 172         .auto_corr_min_ofdm_mrc = 170,
 173         .auto_corr_min_ofdm_x1 = 120,
 174         .auto_corr_min_ofdm_mrc_x1 = 240,
 175
 176         .auto_corr_max_ofdm = 120,
 177         .auto_corr_max_ofdm_mrc = 210,
 178         .auto_corr_max_ofdm_x1 = 120,
 179         .auto_corr_max_ofdm_mrc_x1 = 240,
 180
 181         .auto_corr_min_cck = 125,
 182         .auto_corr_max_cck = 200,
 183         .auto_corr_min_cck_mrc = 170,
 184         .auto_corr_max_cck_mrc = 400,
 185         .nrg_th_cck = 95,
 186         .nrg_th_ofdm = 95,
 187
 188         .barker_corr_th_min = 190,
 189         .barker_corr_th_min_mrc = 390,
 190         .nrg_th_cca = 62,
 191 };
 192
 193 static struct iwl_sensitivity_ranges iwl5150_sensitivity = {
 194         .min_nrg_cck = 95,
 195         .max_nrg_cck = 0, /* not used, set to 0 */
 196         .auto_corr_min_ofdm = 90,
 197         .auto_corr_min_ofdm_mrc = 170,
 198         .auto_corr_min_ofdm_x1 = 105,
 199         .auto_corr_min_ofdm_mrc_x1 = 220,
 200
 201         .auto_corr_max_ofdm = 120,
 202         .auto_corr_max_ofdm_mrc = 210,
 203         /* max = min for performance bug in 5150 DSP */
 204         .auto_corr_max_ofdm_x1 = 105,
 205         .auto_corr_max_ofdm_mrc_x1 = 220,
 206
 207         .auto_corr_min_cck = 125,
 208         .auto_corr_max_cck = 200,
 209         .auto_corr_min_cck_mrc = 170,
 210         .auto_corr_max_cck_mrc = 400,
 211         .nrg_th_cck = 95,
 212         .nrg_th_ofdm = 95,
 213
 214         .barker_corr_th_min = 190,
 215         .barker_corr_th_min_mrc = 390,
 216         .nrg_th_cca = 62,
 217 };
 218
 219 const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
 220                                            size_t offset)
 221 {
 222         u32 address = eeprom_indirect_address(priv, offset);
 223         BUG_ON(address >= priv->cfg->eeprom_size);
 224         return &priv->eeprom[address];
 225 }
 226
 227 static void iwl5150_set_ct_threshold(struct iwl_priv *priv)
 228 {
 229         const s32 volt2temp_coef = IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF;
 230         s32 threshold = (s32)CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD_LEGACY) -
 231                         iwl_temp_calib_to_offset(priv);
 232
 233         priv->hw_params.ct_kill_threshold = threshold * volt2temp_coef;
 234 }
 235
 236 static void iwl5000_set_ct_threshold(struct iwl_priv *priv)
 237 {
 238         /* want Celsius */
 239         priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD_LEGACY;
 240 }
 241
 242 /*
 243  *  Calibration
 244  */
 245 static int iwl5000_set_Xtal_calib(struct iwl_priv *priv)
 246 {
 247         struct iwl_calib_xtal_freq_cmd cmd;
 248         __le16 *xtal_calib =
 249                 (__le16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL);
 250
 251         cmd.hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD;
 252         cmd.hdr.first_group = 0;
 253         cmd.hdr.groups_num = 1;
 254         cmd.hdr.data_valid = 1;
 255         cmd.cap_pin1 = le16_to_cpu(xtal_calib[0]);
 256         cmd.cap_pin2 = le16_to_cpu(xtal_calib[1]);
 257         return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
 258                              (u8 *)&cmd, sizeof(cmd));
 259 }
 260
 261 static int iwl5000_send_calib_cfg(struct iwl_priv *priv)
 262 {
 263         struct iwl_calib_cfg_cmd calib_cfg_cmd;
 264         struct iwl_host_cmd cmd = {
 265                 .id = CALIBRATION_CFG_CMD,
 266                 .len = sizeof(struct iwl_calib_cfg_cmd),
 267                 .data = &calib_cfg_cmd,
 268         };
 269
 270         memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
 271         calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
 272         calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
 273         calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
 274         calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
 275
 276         return iwl_send_cmd(priv, &cmd);
 277 }
 278
 279 static void iwl5000_rx_calib_result(struct iwl_priv *priv,
 280                              struct iwl_rx_mem_buffer *rxb)
 281 {
 282         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 283         struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
 284         int len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
 285         int index;
 286
 287         /* reduce the size of the length field itself */
 288         len -= 4;
 289
 290         /* Define the order in which the results will be sent to the runtime
 291          * uCode. iwl_send_calib_results sends them in a row according to their
 292          * index. We sort them here */
 293         switch (hdr->op_code) {
 294         case IWL_PHY_CALIBRATE_DC_CMD:
 295                 index = IWL_CALIB_DC;
 296                 break;
 297         case IWL_PHY_CALIBRATE_LO_CMD:
 298                 index = IWL_CALIB_LO;
 299                 break;
 300         case IWL_PHY_CALIBRATE_TX_IQ_CMD:
 301                 index = IWL_CALIB_TX_IQ;
 302                 break;
 303         case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
 304                 index = IWL_CALIB_TX_IQ_PERD;
 305                 break;
 306         case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
 307                 index = IWL_CALIB_BASE_BAND;
 308                 break;
 309         default:
 310                 IWL_ERR(priv, "Unknown calibration notification %d\n",
 311                           hdr->op_code);
 312                 return;
 313         }
 314         iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
 315 }
 316
 317 static void iwl5000_rx_calib_complete(struct iwl_priv *priv,
 318                                struct iwl_rx_mem_buffer *rxb)
 319 {
 320         IWL_DEBUG_INFO(priv, "Init. calibration is completed, restarting fw.\n");
 321         queue_work(priv->workqueue, &priv->restart);
 322 }
 323
 324 void iwl5000_init_alive_start(struct iwl_priv *priv)
 325 {
 326         int ret = 0;
 327
 328         /* Check alive response for "valid" sign from uCode */
 329         if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
 330                 /* We had an error bringing up the hardware, so take it
 331                  * all the way back down so we can try again */
 332                 IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
 333                 goto restart;
 334         }
 335
 336         /* initialize uCode was loaded... verify inst image.
 337          * This is a paranoid check, because we would not have gotten the
 338          * "initialize" alive if code weren't properly loaded.  */
 339         if (iwl_verify_ucode(priv)) {
 340                 /* Runtime instruction load was bad;
 341                  * take it all the way back down so we can try again */
 342                 IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
 343                 goto restart;
 344         }
 345
 346         ret = priv->cfg->ops->lib->alive_notify(priv);
 347         if (ret) {
 348                 IWL_WARN(priv,
 349                         "Could not complete ALIVE transition: %d\n", ret);
 350                 goto restart;
 351         }
 352
 353         iwl5000_send_calib_cfg(priv);
 354         return;
 355
 356 restart:
 357         /* real restart (first load init_ucode) */
 358         queue_work(priv->workqueue, &priv->restart);
 359 }
 360
 361 int iwl5000_alive_notify(struct iwl_priv *priv)
 362 {
 363         u32 a;
 364         unsigned long flags;
 365         int i, chan;
 366         u32 reg_val;
 367
 368         spin_lock_irqsave(&priv->lock, flags);
 369
 370         priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
 371         a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
 372         for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
 373                 a += 4)
 374                 iwl_write_targ_mem(priv, a, 0);
 375         for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
 376                 a += 4)
 377                 iwl_write_targ_mem(priv, a, 0);
 378         for (; a < priv->scd_base_addr +
 379                IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(priv->hw_params.max_txq_num); a += 4)
 380                 iwl_write_targ_mem(priv, a, 0);
 381
 382         iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
 383                        priv->scd_bc_tbls.dma >> 10);
 384
 385         /* Enable DMA channel */
 386         for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++)
 387                 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
 388                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
 389                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
 390
 391         /* Update FH chicken bits */
 392         reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
 393         iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
 394                            reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
 395
 396         iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
 397                 IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num));
 398         iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
 399
 400         /* initiate the queues */
 401         for (i = 0; i < priv->hw_params.max_txq_num; i++) {
 402                 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
 403                 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
 404                 iwl_write_targ_mem(priv, priv->scd_base_addr +
 405                                 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
 406                 iwl_write_targ_mem(priv, priv->scd_base_addr +
 407                                 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
 408                                 sizeof(u32),
 409                                 ((SCD_WIN_SIZE <<
 410                                 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
 411                                 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
 412                                 ((SCD_FRAME_LIMIT <<
 413                                 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
 414                                 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
 415         }
 416
 417         iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
 418                         IWL_MASK(0, priv->hw_params.max_txq_num));
 419
 420         /* Activate all Tx DMA/FIFO channels */
 421         priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
 422
 423         iwlagn_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
 424
 425         /* make sure all queue are not stopped */
 426         memset(&priv->queue_stopped[0], 0, sizeof(priv->queue_stopped));
 427         for (i = 0; i < 4; i++)
 428                 atomic_set(&priv->queue_stop_count[i], 0);
 429
 430         /* reset to 0 to enable all the queue first */
 431         priv->txq_ctx_active_msk = 0;
 432         /* map qos queues to fifos one-to-one */
 433         BUILD_BUG_ON(ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo) != 10);
 434
 435         for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
 436                 int ac = iwl5000_default_queue_to_tx_fifo[i];
 437
 438                 iwl_txq_ctx_activate(priv, i);
 439
 440                 if (ac == IWL_TX_FIFO_UNUSED)
 441                         continue;
 442
 443                 iwlagn_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
 444         }
 445
 446         spin_unlock_irqrestore(&priv->lock, flags);
 447
 448         iwl_send_wimax_coex(priv);
 449
 450         iwl5000_set_Xtal_calib(priv);
 451         iwl_send_calib_results(priv);
 452
 453         return 0;
 454 }
 455
 456 int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
 457 {
 458         if (priv->cfg->mod_params->num_of_queues >= IWL_MIN_NUM_QUEUES &&
 459             priv->cfg->mod_params->num_of_queues <= IWL50_NUM_QUEUES)
 460                 priv->cfg->num_of_queues =
 461                         priv->cfg->mod_params->num_of_queues;
 462
 463         priv->hw_params.max_txq_num = priv->cfg->num_of_queues;
 464         priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM;
 465         priv->hw_params.scd_bc_tbls_size =
 466                         priv->cfg->num_of_queues *
 467                         sizeof(struct iwl5000_scd_bc_tbl);
 468         priv->hw_params.tfd_size = sizeof(struct iwl_tfd);
 469         priv->hw_params.max_stations = IWL5000_STATION_COUNT;
 470         priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
 471
 472         priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
 473         priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
 474
 475         priv->hw_params.max_bsm_size = 0;
 476         priv->hw_params.ht40_channel =  BIT(IEEE80211_BAND_2GHZ) |
 477                                         BIT(IEEE80211_BAND_5GHZ);
 478         priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR;
 479
 480         priv->hw_params.tx_chains_num = num_of_ant(priv->cfg->valid_tx_ant);
 481         priv->hw_params.rx_chains_num = num_of_ant(priv->cfg->valid_rx_ant);
 482         priv->hw_params.valid_tx_ant = priv->cfg->valid_tx_ant;
 483         priv->hw_params.valid_rx_ant = priv->cfg->valid_rx_ant;
 484
 485         if (priv->cfg->ops->lib->temp_ops.set_ct_kill)
 486                 priv->cfg->ops->lib->temp_ops.set_ct_kill(priv);
 487
 488         /* Set initial sensitivity parameters */
 489         /* Set initial calibration set */
 490         switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
 491         case CSR_HW_REV_TYPE_5150:
 492                 priv->hw_params.sens = &iwl5150_sensitivity;
 493                 priv->hw_params.calib_init_cfg =
 494                         BIT(IWL_CALIB_DC)               |
 495                         BIT(IWL_CALIB_LO)               |
 496                         BIT(IWL_CALIB_TX_IQ)            |
 497                         BIT(IWL_CALIB_BASE_BAND);
 498
 499                 break;
 500         default:
 501                 priv->hw_params.sens = &iwl5000_sensitivity;
 502                 priv->hw_params.calib_init_cfg =
 503                         BIT(IWL_CALIB_XTAL)             |
 504                         BIT(IWL_CALIB_LO)               |
 505                         BIT(IWL_CALIB_TX_IQ)            |
 506                         BIT(IWL_CALIB_TX_IQ_PERD)       |
 507                         BIT(IWL_CALIB_BASE_BAND);
 508                 break;
 509         }
 510
 511         return 0;
 512 }
 513
 514 static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
 515 {
 516         return le32_to_cpup((__le32 *)&tx_resp->status +
 517                             tx_resp->frame_count) & MAX_SN;
 518 }
 519
 520 static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv,
 521                                       struct iwl_ht_agg *agg,
 522                                       struct iwl5000_tx_resp *tx_resp,
 523                                       int txq_id, u16 start_idx)
 524 {
 525         u16 status;
 526         struct agg_tx_status *frame_status = &tx_resp->status;
 527         struct ieee80211_tx_info *info = NULL;
 528         struct ieee80211_hdr *hdr = NULL;
 529         u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
 530         int i, sh, idx;
 531         u16 seq;
 532
 533         if (agg->wait_for_ba)
 534                 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
 535
 536         agg->frame_count = tx_resp->frame_count;
 537         agg->start_idx = start_idx;
 538         agg->rate_n_flags = rate_n_flags;
 539         agg->bitmap = 0;
 540
 541         /* # frames attempted by Tx command */
 542         if (agg->frame_count == 1) {
 543                 /* Only one frame was attempted; no block-ack will arrive */
 544                 status = le16_to_cpu(frame_status[0].status);
 545                 idx = start_idx;
 546
 547                 /* FIXME: code repetition */
 548                 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
 549                                    agg->frame_count, agg->start_idx, idx);
 550
 551                 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
 552                 info->status.rates[0].count = tx_resp->failure_frame + 1;
 553                 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
 554                 info->flags |= iwl_tx_status_to_mac80211(status);
 555                 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
 556
 557                 /* FIXME: code repetition end */
 558
 559                 IWL_DEBUG_TX_REPLY(priv, "1 Frame 0x%x failure :%d\n",
 560                                     status & 0xff, tx_resp->failure_frame);
 561                 IWL_DEBUG_TX_REPLY(priv, "Rate Info rate_n_flags=%x\n", rate_n_flags);
 562
 563                 agg->wait_for_ba = 0;
 564         } else {
 565                 /* Two or more frames were attempted; expect block-ack */
 566                 u64 bitmap = 0;
 567                 int start = agg->start_idx;
 568
 569                 /* Construct bit-map of pending frames within Tx window */
 570                 for (i = 0; i < agg->frame_count; i++) {
 571                         u16 sc;
 572                         status = le16_to_cpu(frame_status[i].status);
 573                         seq  = le16_to_cpu(frame_status[i].sequence);
 574                         idx = SEQ_TO_INDEX(seq);
 575                         txq_id = SEQ_TO_QUEUE(seq);
 576
 577                         if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
 578                                       AGG_TX_STATE_ABORT_MSK))
 579                                 continue;
 580
 581                         IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
 582                                            agg->frame_count, txq_id, idx);
 583
 584                         hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
 585                         if (!hdr) {
 586                                 IWL_ERR(priv,
 587                                         "BUG_ON idx doesn't point to valid skb"
 588                                         " idx=%d, txq_id=%d\n", idx, txq_id);
 589                                 return -1;
 590                         }
 591
 592                         sc = le16_to_cpu(hdr->seq_ctrl);
 593                         if (idx != (SEQ_TO_SN(sc) & 0xff)) {
 594                                 IWL_ERR(priv,
 595                                         "BUG_ON idx doesn't match seq control"
 596                                         " idx=%d, seq_idx=%d, seq=%d\n",
 597                                           idx, SEQ_TO_SN(sc),
 598                                           hdr->seq_ctrl);
 599                                 return -1;
 600                         }
 601
 602                         IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
 603                                            i, idx, SEQ_TO_SN(sc));
 604
 605                         sh = idx - start;
 606                         if (sh > 64) {
 607                                 sh = (start - idx) + 0xff;
 608                                 bitmap = bitmap << sh;
 609                                 sh = 0;
 610                                 start = idx;
 611                         } else if (sh < -64)
 612                                 sh  = 0xff - (start - idx);
 613                         else if (sh < 0) {
 614                                 sh = start - idx;
 615                                 start = idx;
 616                                 bitmap = bitmap << sh;
 617                                 sh = 0;
 618                         }
 619                         bitmap |= 1ULL << sh;
 620                         IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
 621                                            start, (unsigned long long)bitmap);
 622                 }
 623
 624                 agg->bitmap = bitmap;
 625                 agg->start_idx = start;
 626                 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
 627                                    agg->frame_count, agg->start_idx,
 628                                    (unsigned long long)agg->bitmap);
 629
 630                 if (bitmap)
 631                         agg->wait_for_ba = 1;
 632         }
 633         return 0;
 634 }
 635
 636 static void iwl5000_rx_reply_tx(struct iwl_priv *priv,
 637                                 struct iwl_rx_mem_buffer *rxb)
 638 {
 639         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 640         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
 641         int txq_id = SEQ_TO_QUEUE(sequence);
 642         int index = SEQ_TO_INDEX(sequence);
 643         struct iwl_tx_queue *txq = &priv->txq[txq_id];
 644         struct ieee80211_tx_info *info;
 645         struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
 646         u32  status = le16_to_cpu(tx_resp->status.status);
 647         int tid;
 648         int sta_id;
 649         int freed;
 650
 651         if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
 652                 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
 653                           "is out of range [0-%d] %d %d\n", txq_id,
 654                           index, txq->q.n_bd, txq->q.write_ptr,
 655                           txq->q.read_ptr);
 656                 return;
 657         }
 658
 659         info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
 660         memset(&info->status, 0, sizeof(info->status));
 661
 662         tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS;
 663         sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS;
 664
 665         if (txq->sched_retry) {
 666                 const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp);
 667                 struct iwl_ht_agg *agg = NULL;
 668
 669                 agg = &priv->stations[sta_id].tid[tid].agg;
 670
 671                 iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
 672
 673                 /* check if BAR is needed */
 674                 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
 675                         info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
 676
 677                 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
 678                         index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
 679                         IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
 680                                         "scd_ssn=%d idx=%d txq=%d swq=%d\n",
 681                                         scd_ssn , index, txq_id, txq->swq_id);
 682
 683                         freed = iwl_tx_queue_reclaim(priv, txq_id, index);
 684                         iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
 685
 686                         if (priv->mac80211_registered &&
 687                             (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
 688                             (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
 689                                 if (agg->state == IWL_AGG_OFF)
 690                                         iwl_wake_queue(priv, txq_id);
 691                                 else
 692                                         iwl_wake_queue(priv, txq->swq_id);
 693                         }
 694                 }
 695         } else {
 696                 BUG_ON(txq_id != txq->swq_id);
 697
 698                 info->status.rates[0].count = tx_resp->failure_frame + 1;
 699                 info->flags |= iwl_tx_status_to_mac80211(status);
 700                 iwl_hwrate_to_tx_control(priv,
 701                                         le32_to_cpu(tx_resp->rate_n_flags),
 702                                         info);
 703
 704                 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
 705                                    "0x%x retries %d\n",
 706                                    txq_id,
 707                                    iwl_get_tx_fail_reason(status), status,
 708                                    le32_to_cpu(tx_resp->rate_n_flags),
 709                                    tx_resp->failure_frame);
 710
 711                 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
 712                 iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
 713
 714                 if (priv->mac80211_registered &&
 715                     (iwl_queue_space(&txq->q) > txq->q.low_mark))
 716                         iwl_wake_queue(priv, txq_id);
 717         }
 718
 719         iwl_txq_check_empty(priv, sta_id, tid, txq_id);
 720
 721         if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
 722                 IWL_ERR(priv, "TODO:  Implement Tx ABORT REQUIRED!!!\n");
 723 }
 724
 725 void iwl5000_setup_deferred_work(struct iwl_priv *priv)
 726 {
 727         /* in 5000 the tx power calibration is done in uCode */
 728         priv->disable_tx_power_cal = 1;
 729 }
 730
 731 void iwl5000_rx_handler_setup(struct iwl_priv *priv)
 732 {
 733         /* init calibration handlers */
 734         priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
 735                                         iwl5000_rx_calib_result;
 736         priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
 737                                         iwl5000_rx_calib_complete;
 738         priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx;
 739 }
 740
 741
 742 int iwl5000_hw_valid_rtc_data_addr(u32 addr)
 743 {
 744         return (addr >= IWL50_RTC_DATA_LOWER_BOUND) &&
 745                 (addr < IWL50_RTC_DATA_UPPER_BOUND);
 746 }
 747
 748 int  iwl5000_send_tx_power(struct iwl_priv *priv)
 749 {
 750         struct iwl5000_tx_power_dbm_cmd tx_power_cmd;
 751         u8 tx_ant_cfg_cmd;
 752
 753         /* half dBm need to multiply */
 754         tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
 755
 756         if (priv->tx_power_lmt_in_half_dbm &&
 757             priv->tx_power_lmt_in_half_dbm < tx_power_cmd.global_lmt) {
 758                 /*
 759                  * For the newer devices which using enhanced/extend tx power
 760                  * table in EEPROM, the format is in half dBm. driver need to
 761                  * convert to dBm format before report to mac80211.
 762                  * By doing so, there is a possibility of 1/2 dBm resolution
 763                  * lost. driver will perform "round-up" operation before
 764                  * reporting, but it will cause 1/2 dBm tx power over the
 765                  * regulatory limit. Perform the checking here, if the
 766                  * "tx_power_user_lmt" is higher than EEPROM value (in
 767                  * half-dBm format), lower the tx power based on EEPROM
 768                  */
 769                 tx_power_cmd.global_lmt = priv->tx_power_lmt_in_half_dbm;
 770         }
 771         tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED;
 772         tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO;
 773
 774         if (IWL_UCODE_API(priv->ucode_ver) == 1)
 775                 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1;
 776         else
 777                 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
 778
 779         return  iwl_send_cmd_pdu_async(priv, tx_ant_cfg_cmd,
 780                                        sizeof(tx_power_cmd), &tx_power_cmd,
 781                                        NULL);
 782 }
 783
 784 void iwl5000_temperature(struct iwl_priv *priv)
 785 {
 786         /* store temperature from statistics (in Celsius) */
 787         priv->temperature = le32_to_cpu(priv->statistics.general.temperature);
 788         iwl_tt_handler(priv);
 789 }
 790
 791 static void iwl5150_temperature(struct iwl_priv *priv)
 792 {
 793         u32 vt = 0;
 794         s32 offset =  iwl_temp_calib_to_offset(priv);
 795
 796         vt = le32_to_cpu(priv->statistics.general.temperature);
 797         vt = vt / IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF + offset;
 798         /* now vt hold the temperature in Kelvin */
 799         priv->temperature = KELVIN_TO_CELSIUS(vt);
 800         iwl_tt_handler(priv);
 801 }
 802
 803 static int iwl5000_hw_channel_switch(struct iwl_priv *priv, u16 channel)
 804 {
 805         struct iwl5000_channel_switch_cmd cmd;
 806         const struct iwl_channel_info *ch_info;
 807         struct iwl_host_cmd hcmd = {
 808                 .id = REPLY_CHANNEL_SWITCH,
 809                 .len = sizeof(cmd),
 810                 .flags = CMD_SIZE_HUGE,
 811                 .data = &cmd,
 812         };
 813
 814         IWL_DEBUG_11H(priv, "channel switch from %d to %d\n",
 815                 priv->active_rxon.channel, channel);
 816         cmd.band = priv->band == IEEE80211_BAND_2GHZ;
 817         cmd.channel = cpu_to_le16(channel);
 818         cmd.rxon_flags = priv->staging_rxon.flags;
 819         cmd.rxon_filter_flags = priv->staging_rxon.filter_flags;
 820         cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
 821         ch_info = iwl_get_channel_info(priv, priv->band, channel);
 822         if (ch_info)
 823                 cmd.expect_beacon = is_channel_radar(ch_info);
 824         else {
 825                 IWL_ERR(priv, "invalid channel switch from %u to %u\n",
 826                         priv->active_rxon.channel, channel);
 827                 return -EFAULT;
 828         }
 829         priv->switch_rxon.channel = cpu_to_le16(channel);
 830         priv->switch_rxon.switch_in_progress = true;
 831
 832         return iwl_send_cmd_sync(priv, &hcmd);
 833 }
 834
 835 struct iwl_lib_ops iwl5000_lib = {
 836         .set_hw_params = iwl5000_hw_set_hw_params,
 837         .txq_update_byte_cnt_tbl = iwlagn_txq_update_byte_cnt_tbl,
 838         .txq_inval_byte_cnt_tbl = iwlagn_txq_inval_byte_cnt_tbl,
 839         .txq_set_sched = iwlagn_txq_set_sched,
 840         .txq_agg_enable = iwlagn_txq_agg_enable,
 841         .txq_agg_disable = iwlagn_txq_agg_disable,
 842         .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
 843         .txq_free_tfd = iwl_hw_txq_free_tfd,
 844         .txq_init = iwl_hw_tx_queue_init,
 845         .rx_handler_setup = iwl5000_rx_handler_setup,
 846         .setup_deferred_work = iwl5000_setup_deferred_work,
 847         .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
 848         .dump_nic_event_log = iwl_dump_nic_event_log,
 849         .dump_nic_error_log = iwl_dump_nic_error_log,
 850         .dump_csr = iwl_dump_csr,
 851         .dump_fh = iwl_dump_fh,
 852         .load_ucode = iwlagn_load_ucode,
 853         .init_alive_start = iwl5000_init_alive_start,
 854         .alive_notify = iwl5000_alive_notify,
 855         .send_tx_power = iwl5000_send_tx_power,
 856         .update_chain_flags = iwl_update_chain_flags,
 857         .set_channel_switch = iwl5000_hw_channel_switch,
 858         .apm_ops = {
 859                 .init = iwl_apm_init,
 860                 .stop = iwl_apm_stop,
 861                 .config = iwl5000_nic_config,
 862                 .set_pwr_src = iwl_set_pwr_src,
 863         },
 864         .eeprom_ops = {
 865                 .regulatory_bands = {
 866                         EEPROM_5000_REG_BAND_1_CHANNELS,
 867                         EEPROM_5000_REG_BAND_2_CHANNELS,
 868                         EEPROM_5000_REG_BAND_3_CHANNELS,
 869                         EEPROM_5000_REG_BAND_4_CHANNELS,
 870                         EEPROM_5000_REG_BAND_5_CHANNELS,
 871                         EEPROM_5000_REG_BAND_24_HT40_CHANNELS,
 872                         EEPROM_5000_REG_BAND_52_HT40_CHANNELS
 873                 },
 874                 .verify_signature  = iwlcore_eeprom_verify_signature,
 875                 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
 876                 .release_semaphore = iwlcore_eeprom_release_semaphore,
 877                 .calib_version  = iwl5000_eeprom_calib_version,
 878                 .query_addr = iwl5000_eeprom_query_addr,
 879         },
 880         .post_associate = iwl_post_associate,
 881         .isr = iwl_isr_ict,
 882         .config_ap = iwl_config_ap,
 883         .temp_ops = {
 884                 .temperature = iwl5000_temperature,
 885                 .set_ct_kill = iwl5000_set_ct_threshold,
 886          },
 887         .add_bcast_station = iwl_add_bcast_station,
 888         .recover_from_tx_stall = iwl_bg_monitor_recover,
 889         .check_plcp_health = iwl_good_plcp_health,
 890         .check_ack_health = iwl_good_ack_health,
 891 };
 892
 893 static struct iwl_lib_ops iwl5150_lib = {
 894         .set_hw_params = iwl5000_hw_set_hw_params,
 895         .txq_update_byte_cnt_tbl = iwlagn_txq_update_byte_cnt_tbl,
 896         .txq_inval_byte_cnt_tbl = iwlagn_txq_inval_byte_cnt_tbl,
 897         .txq_set_sched = iwlagn_txq_set_sched,
 898         .txq_agg_enable = iwlagn_txq_agg_enable,
 899         .txq_agg_disable = iwlagn_txq_agg_disable,
 900         .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
 901         .txq_free_tfd = iwl_hw_txq_free_tfd,
 902         .txq_init = iwl_hw_tx_queue_init,
 903         .rx_handler_setup = iwl5000_rx_handler_setup,
 904         .setup_deferred_work = iwl5000_setup_deferred_work,
 905         .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
 906         .dump_nic_event_log = iwl_dump_nic_event_log,
 907         .dump_nic_error_log = iwl_dump_nic_error_log,
 908         .dump_csr = iwl_dump_csr,
 909         .load_ucode = iwlagn_load_ucode,
 910         .init_alive_start = iwl5000_init_alive_start,
 911         .alive_notify = iwl5000_alive_notify,
 912         .send_tx_power = iwl5000_send_tx_power,
 913         .update_chain_flags = iwl_update_chain_flags,
 914         .set_channel_switch = iwl5000_hw_channel_switch,
 915         .apm_ops = {
 916                 .init = iwl_apm_init,
 917                 .stop = iwl_apm_stop,
 918                 .config = iwl5000_nic_config,
 919                 .set_pwr_src = iwl_set_pwr_src,
 920         },
 921         .eeprom_ops = {
 922                 .regulatory_bands = {
 923                         EEPROM_5000_REG_BAND_1_CHANNELS,
 924                         EEPROM_5000_REG_BAND_2_CHANNELS,
 925                         EEPROM_5000_REG_BAND_3_CHANNELS,
 926                         EEPROM_5000_REG_BAND_4_CHANNELS,
 927                         EEPROM_5000_REG_BAND_5_CHANNELS,
 928                         EEPROM_5000_REG_BAND_24_HT40_CHANNELS,
 929                         EEPROM_5000_REG_BAND_52_HT40_CHANNELS
 930                 },
 931                 .verify_signature  = iwlcore_eeprom_verify_signature,
 932                 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
 933                 .release_semaphore = iwlcore_eeprom_release_semaphore,
 934                 .calib_version  = iwl5000_eeprom_calib_version,
 935                 .query_addr = iwl5000_eeprom_query_addr,
 936         },
 937         .post_associate = iwl_post_associate,
 938         .isr = iwl_isr_ict,
 939         .config_ap = iwl_config_ap,
 940         .temp_ops = {
 941                 .temperature = iwl5150_temperature,
 942                 .set_ct_kill = iwl5150_set_ct_threshold,
 943          },
 944         .add_bcast_station = iwl_add_bcast_station,
 945         .recover_from_tx_stall = iwl_bg_monitor_recover,
 946         .check_plcp_health = iwl_good_plcp_health,
 947         .check_ack_health = iwl_good_ack_health,
 948 };
 949
 950 static const struct iwl_ops iwl5000_ops = {
 951         .ucode = &iwlagn_ucode,
 952         .lib = &iwl5000_lib,
 953         .hcmd = &iwlagn_hcmd,
 954         .utils = &iwlagn_hcmd_utils,
 955         .led = &iwlagn_led_ops,
 956 };
 957
 958 static const struct iwl_ops iwl5150_ops = {
 959         .ucode = &iwlagn_ucode,
 960         .lib = &iwl5150_lib,
 961         .hcmd = &iwlagn_hcmd,
 962         .utils = &iwlagn_hcmd_utils,
 963         .led = &iwlagn_led_ops,
 964 };
 965
 966 struct iwl_mod_params iwl50_mod_params = {
 967         .amsdu_size_8K = 1,
 968         .restart_fw = 1,
 969         /* the rest are 0 by default */
 970 };
 971
 972
 973 struct iwl_cfg iwl5300_agn_cfg = {
 974         .name = "Intel(R) Ultimate N WiFi Link 5300 AGN",
 975         .fw_name_pre = IWL5000_FW_PRE,
 976         .ucode_api_max = IWL5000_UCODE_API_MAX,
 977         .ucode_api_min = IWL5000_UCODE_API_MIN,
 978         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
 979         .ops = &iwl5000_ops,
 980         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
 981         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
 982         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
 983         .num_of_queues = IWL50_NUM_QUEUES,
 984         .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
 985         .mod_params = &iwl50_mod_params,
 986         .valid_tx_ant = ANT_ABC,
 987         .valid_rx_ant = ANT_ABC,
 988         .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
 989         .set_l0s = true,
 990         .use_bsm = false,
 991         .ht_greenfield_support = true,
 992         .led_compensation = 51,
 993         .use_rts_for_ht = true, /* use rts/cts protection */
 994         .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
 995         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
 996         .chain_noise_scale = 1000,
 997         .monitor_recover_period = IWL_MONITORING_PERIOD,
 998 };
 999
1000 struct iwl_cfg iwl5100_bgn_cfg = {
1001         .name = "Intel(R) WiFi Link 5100 BGN",
1002         .fw_name_pre = IWL5000_FW_PRE,
1003         .ucode_api_max = IWL5000_UCODE_API_MAX,
1004         .ucode_api_min = IWL5000_UCODE_API_MIN,
1005         .sku = IWL_SKU_G|IWL_SKU_N,
1006         .ops = &iwl5000_ops,
1007         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1008         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1009         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1010         .num_of_queues = IWL50_NUM_QUEUES,
1011         .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1012         .mod_params = &iwl50_mod_params,
1013         .valid_tx_ant = ANT_B,
1014         .valid_rx_ant = ANT_AB,
1015         .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1016         .set_l0s = true,
1017         .use_bsm = false,
1018         .ht_greenfield_support = true,
1019         .led_compensation = 51,
1020         .use_rts_for_ht = true, /* use rts/cts protection */
1021         .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1022         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
1023         .chain_noise_scale = 1000,
1024         .monitor_recover_period = IWL_MONITORING_PERIOD,
1025 };
1026
1027 struct iwl_cfg iwl5100_abg_cfg = {
1028         .name = "Intel(R) WiFi Link 5100 ABG",
1029         .fw_name_pre = IWL5000_FW_PRE,
1030         .ucode_api_max = IWL5000_UCODE_API_MAX,
1031         .ucode_api_min = IWL5000_UCODE_API_MIN,
1032         .sku = IWL_SKU_A|IWL_SKU_G,
1033         .ops = &iwl5000_ops,
1034         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1035         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1036         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1037         .num_of_queues = IWL50_NUM_QUEUES,
1038         .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1039         .mod_params = &iwl50_mod_params,
1040         .valid_tx_ant = ANT_B,
1041         .valid_rx_ant = ANT_AB,
1042         .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1043         .set_l0s = true,
1044         .use_bsm = false,
1045         .led_compensation = 51,
1046         .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1047         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
1048         .chain_noise_scale = 1000,
1049         .monitor_recover_period = IWL_MONITORING_PERIOD,
1050 };
1051
1052 struct iwl_cfg iwl5100_agn_cfg = {
1053         .name = "Intel(R) WiFi Link 5100 AGN",
1054         .fw_name_pre = IWL5000_FW_PRE,
1055         .ucode_api_max = IWL5000_UCODE_API_MAX,
1056         .ucode_api_min = IWL5000_UCODE_API_MIN,
1057         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1058         .ops = &iwl5000_ops,
1059         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1060         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1061         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1062         .num_of_queues = IWL50_NUM_QUEUES,
1063         .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1064         .mod_params = &iwl50_mod_params,
1065         .valid_tx_ant = ANT_B,
1066         .valid_rx_ant = ANT_AB,
1067         .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1068         .set_l0s = true,
1069         .use_bsm = false,
1070         .ht_greenfield_support = true,
1071         .led_compensation = 51,
1072         .use_rts_for_ht = true, /* use rts/cts protection */
1073         .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1074         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
1075         .chain_noise_scale = 1000,
1076         .monitor_recover_period = IWL_MONITORING_PERIOD,
1077 };
1078
1079 struct iwl_cfg iwl5350_agn_cfg = {
1080         .name = "Intel(R) WiMAX/WiFi Link 5350 AGN",
1081         .fw_name_pre = IWL5000_FW_PRE,
1082         .ucode_api_max = IWL5000_UCODE_API_MAX,
1083         .ucode_api_min = IWL5000_UCODE_API_MIN,
1084         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1085         .ops = &iwl5000_ops,
1086         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1087         .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1088         .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1089         .num_of_queues = IWL50_NUM_QUEUES,
1090         .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1091         .mod_params = &iwl50_mod_params,
1092         .valid_tx_ant = ANT_ABC,
1093         .valid_rx_ant = ANT_ABC,
1094         .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1095         .set_l0s = true,
1096         .use_bsm = false,
1097         .ht_greenfield_support = true,
1098         .led_compensation = 51,
1099         .use_rts_for_ht = true, /* use rts/cts protection */
1100         .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1101         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
1102         .chain_noise_scale = 1000,
1103         .monitor_recover_period = IWL_MONITORING_PERIOD,
1104 };
1105
1106 struct iwl_cfg iwl5150_agn_cfg = {
1107         .name = "Intel(R) WiMAX/WiFi Link 5150 AGN",
1108         .fw_name_pre = IWL5150_FW_PRE,
1109         .ucode_api_max = IWL5150_UCODE_API_MAX,
1110         .ucode_api_min = IWL5150_UCODE_API_MIN,
1111         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1112         .ops = &iwl5150_ops,
1113         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1114         .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1115         .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1116         .num_of_queues = IWL50_NUM_QUEUES,
1117         .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1118         .mod_params = &iwl50_mod_params,
1119         .valid_tx_ant = ANT_A,
1120         .valid_rx_ant = ANT_AB,
1121         .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1122         .set_l0s = true,
1123         .use_bsm = false,
1124         .ht_greenfield_support = true,
1125         .led_compensation = 51,
1126         .use_rts_for_ht = true, /* use rts/cts protection */
1127         .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1128         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
1129         .chain_noise_scale = 1000,
1130         .monitor_recover_period = IWL_MONITORING_PERIOD,
1131 };
1132
1133 struct iwl_cfg iwl5150_abg_cfg = {
1134         .name = "Intel(R) WiMAX/WiFi Link 5150 ABG",
1135         .fw_name_pre = IWL5150_FW_PRE,
1136         .ucode_api_max = IWL5150_UCODE_API_MAX,
1137         .ucode_api_min = IWL5150_UCODE_API_MIN,
1138         .sku = IWL_SKU_A|IWL_SKU_G,
1139         .ops = &iwl5150_ops,
1140         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1141         .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1142         .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1143         .num_of_queues = IWL50_NUM_QUEUES,
1144         .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1145         .mod_params = &iwl50_mod_params,
1146         .valid_tx_ant = ANT_A,
1147         .valid_rx_ant = ANT_AB,
1148         .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1149         .set_l0s = true,
1150         .use_bsm = false,
1151         .led_compensation = 51,
1152         .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1153         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
1154         .chain_noise_scale = 1000,
1155         .monitor_recover_period = IWL_MONITORING_PERIOD,
1156 };
1157
1158 MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE(IWL5000_UCODE_API_MAX));
1159 MODULE_FIRMWARE(IWL5150_MODULE_FIRMWARE(IWL5150_UCODE_API_MAX));
1160
1161 module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, S_IRUGO);
1162 MODULE_PARM_DESC(swcrypto50,
1163                   "using software crypto engine (default 0 [hardware])\n");
1164 module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, S_IRUGO);
1165 MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
1166 module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, S_IRUGO);
1167 MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality");
1168 module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K,
1169                    int, S_IRUGO);
1170 MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
1171 module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, S_IRUGO);
1172 MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error");