SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/iwlwifi/iwl-5000.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2010 Intel Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  23  *
  24  *****************************************************************************/
  25
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28 #include <linux/init.h>
  29 #include <linux/pci.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/delay.h>
  32 #include <linux/sched.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/netdevice.h>
  35 #include <linux/wireless.h>
  36 #include <net/mac80211.h>
  37 #include <linux/etherdevice.h>
  38 #include <asm/unaligned.h>
  39
  40 #include "iwl-eeprom.h"
  41 #include "iwl-dev.h"
  42 #include "iwl-core.h"
  43 #include "iwl-io.h"
  44 #include "iwl-sta.h"
  45 #include "iwl-helpers.h"
  46 #include "iwl-agn-led.h"
  47 #include "iwl-5000-hw.h"
  48 #include "iwl-6000-hw.h"
  49
  50 /* Highest firmware API version supported */
  51 #define IWL5000_UCODE_API_MAX 2
  52 #define IWL5150_UCODE_API_MAX 2
  53
  54 /* Lowest firmware API version supported */
  55 #define IWL5000_UCODE_API_MIN 1
  56 #define IWL5150_UCODE_API_MIN 1
  57
  58 #define IWL5000_FW_PRE "iwlwifi-5000-"
  59 #define _IWL5000_MODULE_FIRMWARE(api) IWL5000_FW_PRE #api ".ucode"
  60 #define IWL5000_MODULE_FIRMWARE(api) _IWL5000_MODULE_FIRMWARE(api)
  61
  62 #define IWL5150_FW_PRE "iwlwifi-5150-"
  63 #define _IWL5150_MODULE_FIRMWARE(api) IWL5150_FW_PRE #api ".ucode"
  64 #define IWL5150_MODULE_FIRMWARE(api) _IWL5150_MODULE_FIRMWARE(api)
  65
  66 static const u16 iwl5000_default_queue_to_tx_fifo[] = {
  67         IWL_TX_FIFO_AC3,
  68         IWL_TX_FIFO_AC2,
  69         IWL_TX_FIFO_AC1,
  70         IWL_TX_FIFO_AC0,
  71         IWL50_CMD_FIFO_NUM,
  72         IWL_TX_FIFO_HCCA_1,
  73         IWL_TX_FIFO_HCCA_2
  74 };
  75
  76 /* NIC configuration for 5000 series */
  77 void iwl5000_nic_config(struct iwl_priv *priv)
  78 {
  79         unsigned long flags;
  80         u16 radio_cfg;
  81
  82         spin_lock_irqsave(&priv->lock, flags);
  83
  84         radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
  85
  86         /* write radio config values to register */
  87         if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_RF_CONFIG_TYPE_MAX)
  88                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  89                             EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
  90                             EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
  91                             EEPROM_RF_CFG_DASH_MSK(radio_cfg));
  92
  93         /* set CSR_HW_CONFIG_REG for uCode use */
  94         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  95                     CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
  96                     CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
  97
  98         /* W/A : NIC is stuck in a reset state after Early PCIe power off
  99          * (PCIe power is lost before PERST# is asserted),
 100          * causing ME FW to lose ownership and not being able to obtain it back.
 101          */
 102         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 103                                 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
 104                                 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
 105
 106
 107         spin_unlock_irqrestore(&priv->lock, flags);
 108 }
 109
 110
 111 /*
 112  * EEPROM
 113  */
 114 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
 115 {
 116         u16 offset = 0;
 117
 118         if ((address & INDIRECT_ADDRESS) == 0)
 119                 return address;
 120
 121         switch (address & INDIRECT_TYPE_MSK) {
 122         case INDIRECT_HOST:
 123                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
 124                 break;
 125         case INDIRECT_GENERAL:
 126                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
 127                 break;
 128         case INDIRECT_REGULATORY:
 129                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
 130                 break;
 131         case INDIRECT_CALIBRATION:
 132                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
 133                 break;
 134         case INDIRECT_PROCESS_ADJST:
 135                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
 136                 break;
 137         case INDIRECT_OTHERS:
 138                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
 139                 break;
 140         default:
 141                 IWL_ERR(priv, "illegal indirect type: 0x%X\n",
 142                 address & INDIRECT_TYPE_MSK);
 143                 break;
 144         }
 145
 146         /* translate the offset from words to byte */
 147         return (address & ADDRESS_MSK) + (offset << 1);
 148 }
 149
 150 u16 iwl5000_eeprom_calib_version(struct iwl_priv *priv)
 151 {
 152         struct iwl_eeprom_calib_hdr {
 153                 u8 version;
 154                 u8 pa_type;
 155                 u16 voltage;
 156         } *hdr;
 157
 158         hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
 159                                                         EEPROM_5000_CALIB_ALL);
 160         return hdr->version;
 161
 162 }
 163
 164 static void iwl5000_gain_computation(struct iwl_priv *priv,
 165                 u32 average_noise[NUM_RX_CHAINS],
 166                 u16 min_average_noise_antenna_i,
 167                 u32 min_average_noise,
 168                 u8 default_chain)
 169 {
 170         int i;
 171         s32 delta_g;
 172         struct iwl_chain_noise_data *data = &priv->chain_noise_data;
 173
 174         /*
 175          * Find Gain Code for the chains based on "default chain"
 176          */
 177         for (i = default_chain + 1; i < NUM_RX_CHAINS; i++) {
 178                 if ((data->disconn_array[i])) {
 179                         data->delta_gain_code[i] = 0;
 180                         continue;
 181                 }
 182
 183                 delta_g = (priv->cfg->chain_noise_scale *
 184                         ((s32)average_noise[default_chain] -
 185                         (s32)average_noise[i])) / 1500;
 186
 187                 /* bound gain by 2 bits value max, 3rd bit is sign */
 188                 data->delta_gain_code[i] =
 189                         min(abs(delta_g), (long) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
 190
 191                 if (delta_g < 0)
 192                         /*
 193                          * set negative sign ...
 194                          * note to Intel developers:  This is uCode API format,
 195                          *   not the format of any internal device registers.
 196                          *   Do not change this format for e.g. 6050 or similar
 197                          *   devices.  Change format only if more resolution
 198                          *   (i.e. more than 2 bits magnitude) is needed.
 199                          */
 200                         data->delta_gain_code[i] |= (1 << 2);
 201         }
 202
 203         IWL_DEBUG_CALIB(priv, "Delta gains: ANT_B = %d  ANT_C = %d\n",
 204                         data->delta_gain_code[1], data->delta_gain_code[2]);
 205
 206         if (!data->radio_write) {
 207                 struct iwl_calib_chain_noise_gain_cmd cmd;
 208
 209                 memset(&cmd, 0, sizeof(cmd));
 210
 211                 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD;
 212                 cmd.hdr.first_group = 0;
 213                 cmd.hdr.groups_num = 1;
 214                 cmd.hdr.data_valid = 1;
 215                 cmd.delta_gain_1 = data->delta_gain_code[1];
 216                 cmd.delta_gain_2 = data->delta_gain_code[2];
 217                 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
 218                         sizeof(cmd), &cmd, NULL);
 219
 220                 data->radio_write = 1;
 221                 data->state = IWL_CHAIN_NOISE_CALIBRATED;
 222         }
 223
 224         data->chain_noise_a = 0;
 225         data->chain_noise_b = 0;
 226         data->chain_noise_c = 0;
 227         data->chain_signal_a = 0;
 228         data->chain_signal_b = 0;
 229         data->chain_signal_c = 0;
 230         data->beacon_count = 0;
 231 }
 232
 233 static void iwl5000_chain_noise_reset(struct iwl_priv *priv)
 234 {
 235         struct iwl_chain_noise_data *data = &priv->chain_noise_data;
 236         int ret;
 237
 238         if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
 239                 struct iwl_calib_chain_noise_reset_cmd cmd;
 240                 memset(&cmd, 0, sizeof(cmd));
 241
 242                 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD;
 243                 cmd.hdr.first_group = 0;
 244                 cmd.hdr.groups_num = 1;
 245                 cmd.hdr.data_valid = 1;
 246                 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
 247                                         sizeof(cmd), &cmd);
 248                 if (ret)
 249                         IWL_ERR(priv,
 250                                 "Could not send REPLY_PHY_CALIBRATION_CMD\n");
 251                 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
 252                 IWL_DEBUG_CALIB(priv, "Run chain_noise_calibrate\n");
 253         }
 254 }
 255
 256 void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
 257                         __le32 *tx_flags)
 258 {
 259         if ((info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) ||
 260             (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT))
 261                 *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK;
 262         else
 263                 *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK;
 264 }
 265
 266 static struct iwl_sensitivity_ranges iwl5000_sensitivity = {
 267         .min_nrg_cck = 95,
 268         .max_nrg_cck = 0, /* not used, set to 0 */
 269         .auto_corr_min_ofdm = 90,
 270         .auto_corr_min_ofdm_mrc = 170,
 271         .auto_corr_min_ofdm_x1 = 120,
 272         .auto_corr_min_ofdm_mrc_x1 = 240,
 273
 274         .auto_corr_max_ofdm = 120,
 275         .auto_corr_max_ofdm_mrc = 210,
 276         .auto_corr_max_ofdm_x1 = 120,
 277         .auto_corr_max_ofdm_mrc_x1 = 240,
 278
 279         .auto_corr_min_cck = 125,
 280         .auto_corr_max_cck = 200,
 281         .auto_corr_min_cck_mrc = 170,
 282         .auto_corr_max_cck_mrc = 400,
 283         .nrg_th_cck = 95,
 284         .nrg_th_ofdm = 95,
 285
 286         .barker_corr_th_min = 190,
 287         .barker_corr_th_min_mrc = 390,
 288         .nrg_th_cca = 62,
 289 };
 290
 291 static struct iwl_sensitivity_ranges iwl5150_sensitivity = {
 292         .min_nrg_cck = 95,
 293         .max_nrg_cck = 0, /* not used, set to 0 */
 294         .auto_corr_min_ofdm = 90,
 295         .auto_corr_min_ofdm_mrc = 170,
 296         .auto_corr_min_ofdm_x1 = 105,
 297         .auto_corr_min_ofdm_mrc_x1 = 220,
 298
 299         .auto_corr_max_ofdm = 120,
 300         .auto_corr_max_ofdm_mrc = 210,
 301         /* max = min for performance bug in 5150 DSP */
 302         .auto_corr_max_ofdm_x1 = 105,
 303         .auto_corr_max_ofdm_mrc_x1 = 220,
 304
 305         .auto_corr_min_cck = 125,
 306         .auto_corr_max_cck = 200,
 307         .auto_corr_min_cck_mrc = 170,
 308         .auto_corr_max_cck_mrc = 400,
 309         .nrg_th_cck = 95,
 310         .nrg_th_ofdm = 95,
 311
 312         .barker_corr_th_min = 190,
 313         .barker_corr_th_min_mrc = 390,
 314         .nrg_th_cca = 62,
 315 };
 316
 317 const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
 318                                            size_t offset)
 319 {
 320         u32 address = eeprom_indirect_address(priv, offset);
 321         BUG_ON(address >= priv->cfg->eeprom_size);
 322         return &priv->eeprom[address];
 323 }
 324
 325 static void iwl5150_set_ct_threshold(struct iwl_priv *priv)
 326 {
 327         const s32 volt2temp_coef = IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF;
 328         s32 threshold = (s32)CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD_LEGACY) -
 329                         iwl_temp_calib_to_offset(priv);
 330
 331         priv->hw_params.ct_kill_threshold = threshold * volt2temp_coef;
 332 }
 333
 334 static void iwl5000_set_ct_threshold(struct iwl_priv *priv)
 335 {
 336         /* want Celsius */
 337         priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD_LEGACY;
 338 }
 339
 340 /*
 341  *  Calibration
 342  */
 343 static int iwl5000_set_Xtal_calib(struct iwl_priv *priv)
 344 {
 345         struct iwl_calib_xtal_freq_cmd cmd;
 346         __le16 *xtal_calib =
 347                 (__le16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL);
 348
 349         cmd.hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD;
 350         cmd.hdr.first_group = 0;
 351         cmd.hdr.groups_num = 1;
 352         cmd.hdr.data_valid = 1;
 353         cmd.cap_pin1 = le16_to_cpu(xtal_calib[0]);
 354         cmd.cap_pin2 = le16_to_cpu(xtal_calib[1]);
 355         return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
 356                              (u8 *)&cmd, sizeof(cmd));
 357 }
 358
 359 static int iwl5000_send_calib_cfg(struct iwl_priv *priv)
 360 {
 361         struct iwl_calib_cfg_cmd calib_cfg_cmd;
 362         struct iwl_host_cmd cmd = {
 363                 .id = CALIBRATION_CFG_CMD,
 364                 .len = sizeof(struct iwl_calib_cfg_cmd),
 365                 .data = &calib_cfg_cmd,
 366         };
 367
 368         memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
 369         calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
 370         calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
 371         calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
 372         calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
 373
 374         return iwl_send_cmd(priv, &cmd);
 375 }
 376
 377 static void iwl5000_rx_calib_result(struct iwl_priv *priv,
 378                              struct iwl_rx_mem_buffer *rxb)
 379 {
 380         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 381         struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
 382         int len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
 383         int index;
 384
 385         /* reduce the size of the length field itself */
 386         len -= 4;
 387
 388         /* Define the order in which the results will be sent to the runtime
 389          * uCode. iwl_send_calib_results sends them in a row according to their
 390          * index. We sort them here */
 391         switch (hdr->op_code) {
 392         case IWL_PHY_CALIBRATE_DC_CMD:
 393                 index = IWL_CALIB_DC;
 394                 break;
 395         case IWL_PHY_CALIBRATE_LO_CMD:
 396                 index = IWL_CALIB_LO;
 397                 break;
 398         case IWL_PHY_CALIBRATE_TX_IQ_CMD:
 399                 index = IWL_CALIB_TX_IQ;
 400                 break;
 401         case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
 402                 index = IWL_CALIB_TX_IQ_PERD;
 403                 break;
 404         case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
 405                 index = IWL_CALIB_BASE_BAND;
 406                 break;
 407         default:
 408                 IWL_ERR(priv, "Unknown calibration notification %d\n",
 409                           hdr->op_code);
 410                 return;
 411         }
 412         iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
 413 }
 414
 415 static void iwl5000_rx_calib_complete(struct iwl_priv *priv,
 416                                struct iwl_rx_mem_buffer *rxb)
 417 {
 418         IWL_DEBUG_INFO(priv, "Init. calibration is completed, restarting fw.\n");
 419         queue_work(priv->workqueue, &priv->restart);
 420 }
 421
 422 /*
 423  * ucode
 424  */
 425 static int iwl5000_load_section(struct iwl_priv *priv, const char *name,
 426                                 struct fw_desc *image, u32 dst_addr)
 427 {
 428         dma_addr_t phy_addr = image->p_addr;
 429         u32 byte_cnt = image->len;
 430         int ret;
 431
 432         priv->ucode_write_complete = 0;
 433
 434         iwl_write_direct32(priv,
 435                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 436                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 437
 438         iwl_write_direct32(priv,
 439                 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
 440
 441         iwl_write_direct32(priv,
 442                 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 443                 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 444
 445         iwl_write_direct32(priv,
 446                 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 447                 (iwl_get_dma_hi_addr(phy_addr)
 448                         << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 449
 450         iwl_write_direct32(priv,
 451                 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 452                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 453                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 454                 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 455
 456         iwl_write_direct32(priv,
 457                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 458                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE       |
 459                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE    |
 460                 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 461
 462         IWL_DEBUG_INFO(priv, "%s uCode section being loaded...\n", name);
 463         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
 464                                         priv->ucode_write_complete, 5 * HZ);
 465         if (ret == -ERESTARTSYS) {
 466                 IWL_ERR(priv, "Could not load the %s uCode section due "
 467                         "to interrupt\n", name);
 468                 return ret;
 469         }
 470         if (!ret) {
 471                 IWL_ERR(priv, "Could not load the %s uCode section\n",
 472                         name);
 473                 return -ETIMEDOUT;
 474         }
 475
 476         return 0;
 477 }
 478
 479 static int iwl5000_load_given_ucode(struct iwl_priv *priv,
 480                 struct fw_desc *inst_image,
 481                 struct fw_desc *data_image)
 482 {
 483         int ret = 0;
 484
 485         ret = iwl5000_load_section(priv, "INST", inst_image,
 486                                    IWL50_RTC_INST_LOWER_BOUND);
 487         if (ret)
 488                 return ret;
 489
 490         return iwl5000_load_section(priv, "DATA", data_image,
 491                                     IWL50_RTC_DATA_LOWER_BOUND);
 492 }
 493
 494 int iwl5000_load_ucode(struct iwl_priv *priv)
 495 {
 496         int ret = 0;
 497
 498         /* check whether init ucode should be loaded, or rather runtime ucode */
 499         if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
 500                 IWL_DEBUG_INFO(priv, "Init ucode found. Loading init ucode...\n");
 501                 ret = iwl5000_load_given_ucode(priv,
 502                         &priv->ucode_init, &priv->ucode_init_data);
 503                 if (!ret) {
 504                         IWL_DEBUG_INFO(priv, "Init ucode load complete.\n");
 505                         priv->ucode_type = UCODE_INIT;
 506                 }
 507         } else {
 508                 IWL_DEBUG_INFO(priv, "Init ucode not found, or already loaded. "
 509                         "Loading runtime ucode...\n");
 510                 ret = iwl5000_load_given_ucode(priv,
 511                         &priv->ucode_code, &priv->ucode_data);
 512                 if (!ret) {
 513                         IWL_DEBUG_INFO(priv, "Runtime ucode load complete.\n");
 514                         priv->ucode_type = UCODE_RT;
 515                 }
 516         }
 517
 518         return ret;
 519 }
 520
 521 void iwl5000_init_alive_start(struct iwl_priv *priv)
 522 {
 523         int ret = 0;
 524
 525         /* Check alive response for "valid" sign from uCode */
 526         if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
 527                 /* We had an error bringing up the hardware, so take it
 528                  * all the way back down so we can try again */
 529                 IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
 530                 goto restart;
 531         }
 532
 533         /* initialize uCode was loaded... verify inst image.
 534          * This is a paranoid check, because we would not have gotten the
 535          * "initialize" alive if code weren't properly loaded.  */
 536         if (iwl_verify_ucode(priv)) {
 537                 /* Runtime instruction load was bad;
 538                  * take it all the way back down so we can try again */
 539                 IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
 540                 goto restart;
 541         }
 542
 543         iwl_clear_stations_table(priv);
 544         ret = priv->cfg->ops->lib->alive_notify(priv);
 545         if (ret) {
 546                 IWL_WARN(priv,
 547                         "Could not complete ALIVE transition: %d\n", ret);
 548                 goto restart;
 549         }
 550
 551         iwl5000_send_calib_cfg(priv);
 552         return;
 553
 554 restart:
 555         /* real restart (first load init_ucode) */
 556         queue_work(priv->workqueue, &priv->restart);
 557 }
 558
 559 static void iwl5000_set_wr_ptrs(struct iwl_priv *priv,
 560                                 int txq_id, u32 index)
 561 {
 562         iwl_write_direct32(priv, HBUS_TARG_WRPTR,
 563                         (index & 0xff) | (txq_id << 8));
 564         iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index);
 565 }
 566
 567 static void iwl5000_tx_queue_set_status(struct iwl_priv *priv,
 568                                         struct iwl_tx_queue *txq,
 569                                         int tx_fifo_id, int scd_retry)
 570 {
 571         int txq_id = txq->q.id;
 572         int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
 573
 574         iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
 575                         (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
 576                         (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) |
 577                         (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) |
 578                         IWL50_SCD_QUEUE_STTS_REG_MSK);
 579
 580         txq->sched_retry = scd_retry;
 581
 582         IWL_DEBUG_INFO(priv, "%s %s Queue %d on AC %d\n",
 583                        active ? "Activate" : "Deactivate",
 584                        scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
 585 }
 586
 587 int iwl5000_alive_notify(struct iwl_priv *priv)
 588 {
 589         u32 a;
 590         unsigned long flags;
 591         int i, chan;
 592         u32 reg_val;
 593
 594         spin_lock_irqsave(&priv->lock, flags);
 595
 596         priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
 597         a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
 598         for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
 599                 a += 4)
 600                 iwl_write_targ_mem(priv, a, 0);
 601         for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
 602                 a += 4)
 603                 iwl_write_targ_mem(priv, a, 0);
 604         for (; a < priv->scd_base_addr +
 605                IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(priv->hw_params.max_txq_num); a += 4)
 606                 iwl_write_targ_mem(priv, a, 0);
 607
 608         iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
 609                        priv->scd_bc_tbls.dma >> 10);
 610
 611         /* Enable DMA channel */
 612         for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++)
 613                 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
 614                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
 615                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
 616
 617         /* Update FH chicken bits */
 618         reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
 619         iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
 620                            reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
 621
 622         iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
 623                 IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num));
 624         iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
 625
 626         /* initiate the queues */
 627         for (i = 0; i < priv->hw_params.max_txq_num; i++) {
 628                 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
 629                 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
 630                 iwl_write_targ_mem(priv, priv->scd_base_addr +
 631                                 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
 632                 iwl_write_targ_mem(priv, priv->scd_base_addr +
 633                                 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
 634                                 sizeof(u32),
 635                                 ((SCD_WIN_SIZE <<
 636                                 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
 637                                 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
 638                                 ((SCD_FRAME_LIMIT <<
 639                                 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
 640                                 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
 641         }
 642
 643         iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
 644                         IWL_MASK(0, priv->hw_params.max_txq_num));
 645
 646         /* Activate all Tx DMA/FIFO channels */
 647         priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
 648
 649         iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
 650
 651         /* map qos queues to fifos one-to-one */
 652         for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
 653                 int ac = iwl5000_default_queue_to_tx_fifo[i];
 654                 iwl_txq_ctx_activate(priv, i);
 655                 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
 656         }
 657
 658         /*
 659          * TODO - need to initialize these queues and map them to FIFOs
 660          * in the loop above, not only mark them as active. We do this
 661          * because we want the first aggregation queue to be queue #10,
 662          * but do not use 8 or 9 otherwise yet.
 663          */
 664         iwl_txq_ctx_activate(priv, 7);
 665         iwl_txq_ctx_activate(priv, 8);
 666         iwl_txq_ctx_activate(priv, 9);
 667
 668         spin_unlock_irqrestore(&priv->lock, flags);
 669
 670
 671         iwl_send_wimax_coex(priv);
 672
 673         iwl5000_set_Xtal_calib(priv);
 674         iwl_send_calib_results(priv);
 675
 676         return 0;
 677 }
 678
 679 int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
 680 {
 681         if (priv->cfg->mod_params->num_of_queues >= IWL_MIN_NUM_QUEUES &&
 682             priv->cfg->mod_params->num_of_queues <= IWL50_NUM_QUEUES)
 683                 priv->cfg->num_of_queues =
 684                         priv->cfg->mod_params->num_of_queues;
 685
 686         priv->hw_params.max_txq_num = priv->cfg->num_of_queues;
 687         priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM;
 688         priv->hw_params.scd_bc_tbls_size =
 689                         priv->cfg->num_of_queues *
 690                         sizeof(struct iwl5000_scd_bc_tbl);
 691         priv->hw_params.tfd_size = sizeof(struct iwl_tfd);
 692         priv->hw_params.max_stations = IWL5000_STATION_COUNT;
 693         priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
 694
 695         priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
 696         priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
 697
 698         priv->hw_params.max_bsm_size = 0;
 699         priv->hw_params.ht40_channel =  BIT(IEEE80211_BAND_2GHZ) |
 700                                         BIT(IEEE80211_BAND_5GHZ);
 701         priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR;
 702
 703         priv->hw_params.tx_chains_num = num_of_ant(priv->cfg->valid_tx_ant);
 704         priv->hw_params.rx_chains_num = num_of_ant(priv->cfg->valid_rx_ant);
 705         priv->hw_params.valid_tx_ant = priv->cfg->valid_tx_ant;
 706         priv->hw_params.valid_rx_ant = priv->cfg->valid_rx_ant;
 707
 708         if (priv->cfg->ops->lib->temp_ops.set_ct_kill)
 709                 priv->cfg->ops->lib->temp_ops.set_ct_kill(priv);
 710
 711         /* Set initial sensitivity parameters */
 712         /* Set initial calibration set */
 713         switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
 714         case CSR_HW_REV_TYPE_5150:
 715                 priv->hw_params.sens = &iwl5150_sensitivity;
 716                 priv->hw_params.calib_init_cfg =
 717                         BIT(IWL_CALIB_DC)               |
 718                         BIT(IWL_CALIB_LO)               |
 719                         BIT(IWL_CALIB_TX_IQ)            |
 720                         BIT(IWL_CALIB_BASE_BAND);
 721
 722                 break;
 723         default:
 724                 priv->hw_params.sens = &iwl5000_sensitivity;
 725                 priv->hw_params.calib_init_cfg =
 726                         BIT(IWL_CALIB_XTAL)             |
 727                         BIT(IWL_CALIB_LO)               |
 728                         BIT(IWL_CALIB_TX_IQ)            |
 729                         BIT(IWL_CALIB_TX_IQ_PERD)       |
 730                         BIT(IWL_CALIB_BASE_BAND);
 731                 break;
 732         }
 733
 734         return 0;
 735 }
 736
 737 /**
 738  * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
 739  */
 740 void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
 741                                             struct iwl_tx_queue *txq,
 742                                             u16 byte_cnt)
 743 {
 744         struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
 745         int write_ptr = txq->q.write_ptr;
 746         int txq_id = txq->q.id;
 747         u8 sec_ctl = 0;
 748         u8 sta_id = 0;
 749         u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
 750         __le16 bc_ent;
 751
 752         WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
 753
 754         if (txq_id != IWL_CMD_QUEUE_NUM) {
 755                 sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
 756                 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
 757
 758                 switch (sec_ctl & TX_CMD_SEC_MSK) {
 759                 case TX_CMD_SEC_CCM:
 760                         len += CCMP_MIC_LEN;
 761                         break;
 762                 case TX_CMD_SEC_TKIP:
 763                         len += TKIP_ICV_LEN;
 764                         break;
 765                 case TX_CMD_SEC_WEP:
 766                         len += WEP_IV_LEN + WEP_ICV_LEN;
 767                         break;
 768                 }
 769         }
 770
 771         bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
 772
 773         scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
 774
 775         if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
 776                 scd_bc_tbl[txq_id].
 777                         tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
 778 }
 779
 780 void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
 781                                            struct iwl_tx_queue *txq)
 782 {
 783         struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
 784         int txq_id = txq->q.id;
 785         int read_ptr = txq->q.read_ptr;
 786         u8 sta_id = 0;
 787         __le16 bc_ent;
 788
 789         WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
 790
 791         if (txq_id != IWL_CMD_QUEUE_NUM)
 792                 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
 793
 794         bc_ent = cpu_to_le16(1 | (sta_id << 12));
 795         scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
 796
 797         if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
 798                 scd_bc_tbl[txq_id].
 799                         tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
 800 }
 801
 802 static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
 803                                         u16 txq_id)
 804 {
 805         u32 tbl_dw_addr;
 806         u32 tbl_dw;
 807         u16 scd_q2ratid;
 808
 809         scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
 810
 811         tbl_dw_addr = priv->scd_base_addr +
 812                         IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
 813
 814         tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
 815
 816         if (txq_id & 0x1)
 817                 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
 818         else
 819                 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
 820
 821         iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
 822
 823         return 0;
 824 }
 825 static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
 826 {
 827         /* Simply stop the queue, but don't change any configuration;
 828          * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
 829         iwl_write_prph(priv,
 830                 IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
 831                 (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
 832                 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
 833 }
 834
 835 int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
 836                                   int tx_fifo, int sta_id, int tid, u16 ssn_idx)
 837 {
 838         unsigned long flags;
 839         u16 ra_tid;
 840
 841         if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
 842             (IWL50_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues
 843              <= txq_id)) {
 844                 IWL_WARN(priv,
 845                         "queue number out of range: %d, must be %d to %d\n",
 846                         txq_id, IWL50_FIRST_AMPDU_QUEUE,
 847                         IWL50_FIRST_AMPDU_QUEUE +
 848                         priv->cfg->num_of_ampdu_queues - 1);
 849                 return -EINVAL;
 850         }
 851
 852         ra_tid = BUILD_RAxTID(sta_id, tid);
 853
 854         /* Modify device's station table to Tx this TID */
 855         iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
 856
 857         spin_lock_irqsave(&priv->lock, flags);
 858
 859         /* Stop this Tx queue before configuring it */
 860         iwl5000_tx_queue_stop_scheduler(priv, txq_id);
 861
 862         /* Map receiver-address / traffic-ID to this queue */
 863         iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
 864
 865         /* Set this queue as a chain-building queue */
 866         iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id));
 867
 868         /* enable aggregations for the queue */
 869         iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id));
 870
 871         /* Place first TFD at index corresponding to start sequence number.
 872          * Assumes that ssn_idx is valid (!= 0xFFF) */
 873         priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
 874         priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
 875         iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
 876
 877         /* Set up Tx window size and frame limit for this queue */
 878         iwl_write_targ_mem(priv, priv->scd_base_addr +
 879                         IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
 880                         sizeof(u32),
 881                         ((SCD_WIN_SIZE <<
 882                         IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
 883                         IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
 884                         ((SCD_FRAME_LIMIT <<
 885                         IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
 886                         IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
 887
 888         iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
 889
 890         /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
 891         iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
 892
 893         spin_unlock_irqrestore(&priv->lock, flags);
 894
 895         return 0;
 896 }
 897
 898 int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
 899                                    u16 ssn_idx, u8 tx_fifo)
 900 {
 901         if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
 902             (IWL50_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues
 903              <= txq_id)) {
 904                 IWL_ERR(priv,
 905                         "queue number out of range: %d, must be %d to %d\n",
 906                         txq_id, IWL50_FIRST_AMPDU_QUEUE,
 907                         IWL50_FIRST_AMPDU_QUEUE +
 908                         priv->cfg->num_of_ampdu_queues - 1);
 909                 return -EINVAL;
 910         }
 911
 912         iwl5000_tx_queue_stop_scheduler(priv, txq_id);
 913
 914         iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id));
 915
 916         priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
 917         priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
 918         /* supposes that ssn_idx is valid (!= 0xFFF) */
 919         iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
 920
 921         iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
 922         iwl_txq_ctx_deactivate(priv, txq_id);
 923         iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
 924
 925         return 0;
 926 }
 927
 928 u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
 929 {
 930         u16 size = (u16)sizeof(struct iwl_addsta_cmd);
 931         struct iwl_addsta_cmd *addsta = (struct iwl_addsta_cmd *)data;
 932         memcpy(addsta, cmd, size);
 933         /* resrved in 5000 */
 934         addsta->rate_n_flags = cpu_to_le16(0);
 935         return size;
 936 }
 937
 938
 939 /*
 940  * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
 941  * must be called under priv->lock and mac access
 942  */
 943 void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask)
 944 {
 945         iwl_write_prph(priv, IWL50_SCD_TXFACT, mask);
 946 }
 947
 948
 949 static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
 950 {
 951         return le32_to_cpup((__le32 *)&tx_resp->status +
 952                             tx_resp->frame_count) & MAX_SN;
 953 }
 954
 955 static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv,
 956                                       struct iwl_ht_agg *agg,
 957                                       struct iwl5000_tx_resp *tx_resp,
 958                                       int txq_id, u16 start_idx)
 959 {
 960         u16 status;
 961         struct agg_tx_status *frame_status = &tx_resp->status;
 962         struct ieee80211_tx_info *info = NULL;
 963         struct ieee80211_hdr *hdr = NULL;
 964         u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
 965         int i, sh, idx;
 966         u16 seq;
 967
 968         if (agg->wait_for_ba)
 969                 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
 970
 971         agg->frame_count = tx_resp->frame_count;
 972         agg->start_idx = start_idx;
 973         agg->rate_n_flags = rate_n_flags;
 974         agg->bitmap = 0;
 975
 976         /* # frames attempted by Tx command */
 977         if (agg->frame_count == 1) {
 978                 /* Only one frame was attempted; no block-ack will arrive */
 979                 status = le16_to_cpu(frame_status[0].status);
 980                 idx = start_idx;
 981
 982                 /* FIXME: code repetition */
 983                 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
 984                                    agg->frame_count, agg->start_idx, idx);
 985
 986                 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
 987                 info->status.rates[0].count = tx_resp->failure_frame + 1;
 988                 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
 989                 info->flags |= iwl_tx_status_to_mac80211(status);
 990                 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
 991
 992                 /* FIXME: code repetition end */
 993
 994                 IWL_DEBUG_TX_REPLY(priv, "1 Frame 0x%x failure :%d\n",
 995                                     status & 0xff, tx_resp->failure_frame);
 996                 IWL_DEBUG_TX_REPLY(priv, "Rate Info rate_n_flags=%x\n", rate_n_flags);
 997
 998                 agg->wait_for_ba = 0;
 999         } else {
1000                 /* Two or more frames were attempted; expect block-ack */
1001                 u64 bitmap = 0;
1002                 int start = agg->start_idx;
1003
1004                 /* Construct bit-map of pending frames within Tx window */
1005                 for (i = 0; i < agg->frame_count; i++) {
1006                         u16 sc;
1007                         status = le16_to_cpu(frame_status[i].status);
1008                         seq  = le16_to_cpu(frame_status[i].sequence);
1009                         idx = SEQ_TO_INDEX(seq);
1010                         txq_id = SEQ_TO_QUEUE(seq);
1011
1012                         if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
1013                                       AGG_TX_STATE_ABORT_MSK))
1014                                 continue;
1015
1016                         IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
1017                                            agg->frame_count, txq_id, idx);
1018
1019                         hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
1020                         if (!hdr) {
1021                                 IWL_ERR(priv,
1022                                         "BUG_ON idx doesn't point to valid skb"
1023                                         " idx=%d, txq_id=%d\n", idx, txq_id);
1024                                 return -1;
1025                         }
1026
1027                         sc = le16_to_cpu(hdr->seq_ctrl);
1028                         if (idx != (SEQ_TO_SN(sc) & 0xff)) {
1029                                 IWL_ERR(priv,
1030                                         "BUG_ON idx doesn't match seq control"
1031                                         " idx=%d, seq_idx=%d, seq=%d\n",
1032                                           idx, SEQ_TO_SN(sc),
1033                                           hdr->seq_ctrl);
1034                                 return -1;
1035                         }
1036
1037                         IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
1038                                            i, idx, SEQ_TO_SN(sc));
1039
1040                         sh = idx - start;
1041                         if (sh > 64) {
1042                                 sh = (start - idx) + 0xff;
1043                                 bitmap = bitmap << sh;
1044                                 sh = 0;
1045                                 start = idx;
1046                         } else if (sh < -64)
1047                                 sh  = 0xff - (start - idx);
1048                         else if (sh < 0) {
1049                                 sh = start - idx;
1050                                 start = idx;
1051                                 bitmap = bitmap << sh;
1052                                 sh = 0;
1053                         }
1054                         bitmap |= 1ULL << sh;
1055                         IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
1056                                            start, (unsigned long long)bitmap);
1057                 }
1058
1059                 agg->bitmap = bitmap;
1060                 agg->start_idx = start;
1061                 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
1062                                    agg->frame_count, agg->start_idx,
1063                                    (unsigned long long)agg->bitmap);
1064
1065                 if (bitmap)
1066                         agg->wait_for_ba = 1;
1067         }
1068         return 0;
1069 }
1070
1071 static void iwl5000_rx_reply_tx(struct iwl_priv *priv,
1072                                 struct iwl_rx_mem_buffer *rxb)
1073 {
1074         struct iwl_rx_packet *pkt = rxb_addr(rxb);
1075         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1076         int txq_id = SEQ_TO_QUEUE(sequence);
1077         int index = SEQ_TO_INDEX(sequence);
1078         struct iwl_tx_queue *txq = &priv->txq[txq_id];
1079         struct ieee80211_tx_info *info;
1080         struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
1081         u32  status = le16_to_cpu(tx_resp->status.status);
1082         int tid;
1083         int sta_id;
1084         int freed;
1085
1086         if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
1087                 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
1088                           "is out of range [0-%d] %d %d\n", txq_id,
1089                           index, txq->q.n_bd, txq->q.write_ptr,
1090                           txq->q.read_ptr);
1091                 return;
1092         }
1093
1094         info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
1095         memset(&info->status, 0, sizeof(info->status));
1096
1097         tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS;
1098         sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS;
1099
1100         if (txq->sched_retry) {
1101                 const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp);
1102                 struct iwl_ht_agg *agg = NULL;
1103
1104                 agg = &priv->stations[sta_id].tid[tid].agg;
1105
1106                 iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
1107
1108                 /* check if BAR is needed */
1109                 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
1110                         info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1111
1112                 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
1113                         index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
1114                         IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
1115                                         "scd_ssn=%d idx=%d txq=%d swq=%d\n",
1116                                         scd_ssn , index, txq_id, txq->swq_id);
1117
1118                         freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1119                         priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1120
1121                         if (priv->mac80211_registered &&
1122                             (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1123                             (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
1124                                 if (agg->state == IWL_AGG_OFF)
1125                                         iwl_wake_queue(priv, txq_id);
1126                                 else
1127                                         iwl_wake_queue(priv, txq->swq_id);
1128                         }
1129                 }
1130         } else {
1131                 BUG_ON(txq_id != txq->swq_id);
1132
1133                 info->status.rates[0].count = tx_resp->failure_frame + 1;
1134                 info->flags |= iwl_tx_status_to_mac80211(status);
1135                 iwl_hwrate_to_tx_control(priv,
1136                                         le32_to_cpu(tx_resp->rate_n_flags),
1137                                         info);
1138
1139                 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
1140                                    "0x%x retries %d\n",
1141                                    txq_id,
1142                                    iwl_get_tx_fail_reason(status), status,
1143                                    le32_to_cpu(tx_resp->rate_n_flags),
1144                                    tx_resp->failure_frame);
1145
1146                 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1147                 if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1148                         priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1149
1150                 if (priv->mac80211_registered &&
1151                     (iwl_queue_space(&txq->q) > txq->q.low_mark))
1152                         iwl_wake_queue(priv, txq_id);
1153         }
1154
1155         if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1156                 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
1157
1158         if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
1159                 IWL_ERR(priv, "TODO:  Implement Tx ABORT REQUIRED!!!\n");
1160 }
1161
1162 /* Currently 5000 is the superset of everything */
1163 u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len)
1164 {
1165         return len;
1166 }
1167
1168 void iwl5000_setup_deferred_work(struct iwl_priv *priv)
1169 {
1170         /* in 5000 the tx power calibration is done in uCode */
1171         priv->disable_tx_power_cal = 1;
1172 }
1173
1174 void iwl5000_rx_handler_setup(struct iwl_priv *priv)
1175 {
1176         /* init calibration handlers */
1177         priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
1178                                         iwl5000_rx_calib_result;
1179         priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
1180                                         iwl5000_rx_calib_complete;
1181         priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx;
1182 }
1183
1184
1185 int iwl5000_hw_valid_rtc_data_addr(u32 addr)
1186 {
1187         return (addr >= IWL50_RTC_DATA_LOWER_BOUND) &&
1188                 (addr < IWL50_RTC_DATA_UPPER_BOUND);
1189 }
1190
1191 static int iwl5000_send_rxon_assoc(struct iwl_priv *priv)
1192 {
1193         int ret = 0;
1194         struct iwl5000_rxon_assoc_cmd rxon_assoc;
1195         const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1196         const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1197
1198         if ((rxon1->flags == rxon2->flags) &&
1199             (rxon1->filter_flags == rxon2->filter_flags) &&
1200             (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1201             (rxon1->ofdm_ht_single_stream_basic_rates ==
1202              rxon2->ofdm_ht_single_stream_basic_rates) &&
1203             (rxon1->ofdm_ht_dual_stream_basic_rates ==
1204              rxon2->ofdm_ht_dual_stream_basic_rates) &&
1205             (rxon1->ofdm_ht_triple_stream_basic_rates ==
1206              rxon2->ofdm_ht_triple_stream_basic_rates) &&
1207             (rxon1->acquisition_data == rxon2->acquisition_data) &&
1208             (rxon1->rx_chain == rxon2->rx_chain) &&
1209             (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1210                 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC.  Not resending.\n");
1211                 return 0;
1212         }
1213
1214         rxon_assoc.flags = priv->staging_rxon.flags;
1215         rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1216         rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1217         rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1218         rxon_assoc.reserved1 = 0;
1219         rxon_assoc.reserved2 = 0;
1220         rxon_assoc.reserved3 = 0;
1221         rxon_assoc.ofdm_ht_single_stream_basic_rates =
1222             priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1223         rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1224             priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1225         rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1226         rxon_assoc.ofdm_ht_triple_stream_basic_rates =
1227                  priv->staging_rxon.ofdm_ht_triple_stream_basic_rates;
1228         rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data;
1229
1230         ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1231                                      sizeof(rxon_assoc), &rxon_assoc, NULL);
1232         if (ret)
1233                 return ret;
1234
1235         return ret;
1236 }
1237 int  iwl5000_send_tx_power(struct iwl_priv *priv)
1238 {
1239         struct iwl5000_tx_power_dbm_cmd tx_power_cmd;
1240         u8 tx_ant_cfg_cmd;
1241
1242         /* half dBm need to multiply */
1243         tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
1244
1245         if (priv->tx_power_lmt_in_half_dbm &&
1246             priv->tx_power_lmt_in_half_dbm < tx_power_cmd.global_lmt) {
1247                 /*
1248                  * For the newer devices which using enhanced/extend tx power
1249                  * table in EEPROM, the format is in half dBm. driver need to
1250                  * convert to dBm format before report to mac80211.
1251                  * By doing so, there is a possibility of 1/2 dBm resolution
1252                  * lost. driver will perform "round-up" operation before
1253                  * reporting, but it will cause 1/2 dBm tx power over the
1254                  * regulatory limit. Perform the checking here, if the
1255                  * "tx_power_user_lmt" is higher than EEPROM value (in
1256                  * half-dBm format), lower the tx power based on EEPROM
1257                  */
1258                 tx_power_cmd.global_lmt = priv->tx_power_lmt_in_half_dbm;
1259         }
1260         tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED;
1261         tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO;
1262
1263         if (IWL_UCODE_API(priv->ucode_ver) == 1)
1264                 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1;
1265         else
1266                 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
1267
1268         return  iwl_send_cmd_pdu_async(priv, tx_ant_cfg_cmd,
1269                                        sizeof(tx_power_cmd), &tx_power_cmd,
1270                                        NULL);
1271 }
1272
1273 void iwl5000_temperature(struct iwl_priv *priv)
1274 {
1275         /* store temperature from statistics (in Celsius) */
1276         priv->temperature = le32_to_cpu(priv->statistics.general.temperature);
1277         iwl_tt_handler(priv);
1278 }
1279
1280 static void iwl5150_temperature(struct iwl_priv *priv)
1281 {
1282         u32 vt = 0;
1283         s32 offset =  iwl_temp_calib_to_offset(priv);
1284
1285         vt = le32_to_cpu(priv->statistics.general.temperature);
1286         vt = vt / IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF + offset;
1287         /* now vt hold the temperature in Kelvin */
1288         priv->temperature = KELVIN_TO_CELSIUS(vt);
1289         iwl_tt_handler(priv);
1290 }
1291
1292 /* Calc max signal level (dBm) among 3 possible receivers */
1293 int iwl5000_calc_rssi(struct iwl_priv *priv,
1294                              struct iwl_rx_phy_res *rx_resp)
1295 {
1296         /* data from PHY/DSP regarding signal strength, etc.,
1297          *   contents are always there, not configurable by host
1298          */
1299         struct iwl5000_non_cfg_phy *ncphy =
1300                 (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
1301         u32 val, rssi_a, rssi_b, rssi_c, max_rssi;
1302         u8 agc;
1303
1304         val  = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]);
1305         agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS;
1306
1307         /* Find max rssi among 3 possible receivers.
1308          * These values are measured by the digital signal processor (DSP).
1309          * They should stay fairly constant even as the signal strength varies,
1310          *   if the radio's automatic gain control (AGC) is working right.
1311          * AGC value (see below) will provide the "interesting" info.
1312          */
1313         val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]);
1314         rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS;
1315         rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS;
1316         val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]);
1317         rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS;
1318
1319         max_rssi = max_t(u32, rssi_a, rssi_b);
1320         max_rssi = max_t(u32, max_rssi, rssi_c);
1321
1322         IWL_DEBUG_STATS(priv, "Rssi In A %d B %d C %d Max %d AGC dB %d\n",
1323                 rssi_a, rssi_b, rssi_c, max_rssi, agc);
1324
1325         /* dBm = max_rssi dB - agc dB - constant.
1326          * Higher AGC (higher radio gain) means lower signal. */
1327         return max_rssi - agc - IWL49_RSSI_OFFSET;
1328 }
1329
1330 static int iwl5000_send_tx_ant_config(struct iwl_priv *priv, u8 valid_tx_ant)
1331 {
1332         struct iwl_tx_ant_config_cmd tx_ant_cmd = {
1333           .valid = cpu_to_le32(valid_tx_ant),
1334         };
1335
1336         if (IWL_UCODE_API(priv->ucode_ver) > 1) {
1337                 IWL_DEBUG_HC(priv, "select valid tx ant: %u\n", valid_tx_ant);
1338                 return iwl_send_cmd_pdu(priv, TX_ANT_CONFIGURATION_CMD,
1339                                         sizeof(struct iwl_tx_ant_config_cmd),
1340                                         &tx_ant_cmd);
1341         } else {
1342                 IWL_DEBUG_HC(priv, "TX_ANT_CONFIGURATION_CMD not supported\n");
1343                 return -EOPNOTSUPP;
1344         }
1345 }
1346
1347
1348 #define IWL5000_UCODE_GET(item)                                         \
1349 static u32 iwl5000_ucode_get_##item(const struct iwl_ucode_header *ucode,\
1350                                     u32 api_ver)                        \
1351 {                                                                       \
1352         if (api_ver <= 2)                                               \
1353                 return le32_to_cpu(ucode->u.v1.item);                   \
1354         return le32_to_cpu(ucode->u.v2.item);                           \
1355 }
1356
1357 static u32 iwl5000_ucode_get_header_size(u32 api_ver)
1358 {
1359         if (api_ver <= 2)
1360                 return UCODE_HEADER_SIZE(1);
1361         return UCODE_HEADER_SIZE(2);
1362 }
1363
1364 static u32 iwl5000_ucode_get_build(const struct iwl_ucode_header *ucode,
1365                                    u32 api_ver)
1366 {
1367         if (api_ver <= 2)
1368                 return 0;
1369         return le32_to_cpu(ucode->u.v2.build);
1370 }
1371
1372 static u8 *iwl5000_ucode_get_data(const struct iwl_ucode_header *ucode,
1373                                   u32 api_ver)
1374 {
1375         if (api_ver <= 2)
1376                 return (u8 *) ucode->u.v1.data;
1377         return (u8 *) ucode->u.v2.data;
1378 }
1379
1380 IWL5000_UCODE_GET(inst_size);
1381 IWL5000_UCODE_GET(data_size);
1382 IWL5000_UCODE_GET(init_size);
1383 IWL5000_UCODE_GET(init_data_size);
1384 IWL5000_UCODE_GET(boot_size);
1385
1386 static int iwl5000_hw_channel_switch(struct iwl_priv *priv, u16 channel)
1387 {
1388         struct iwl5000_channel_switch_cmd cmd;
1389         const struct iwl_channel_info *ch_info;
1390         struct iwl_host_cmd hcmd = {
1391                 .id = REPLY_CHANNEL_SWITCH,
1392                 .len = sizeof(cmd),
1393                 .flags = CMD_SIZE_HUGE,
1394                 .data = &cmd,
1395         };
1396
1397         IWL_DEBUG_11H(priv, "channel switch from %d to %d\n",
1398                 priv->active_rxon.channel, channel);
1399         cmd.band = priv->band == IEEE80211_BAND_2GHZ;
1400         cmd.channel = cpu_to_le16(channel);
1401         cmd.rxon_flags = priv->staging_rxon.flags;
1402         cmd.rxon_filter_flags = priv->staging_rxon.filter_flags;
1403         cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
1404         ch_info = iwl_get_channel_info(priv, priv->band, channel);
1405         if (ch_info)
1406                 cmd.expect_beacon = is_channel_radar(ch_info);
1407         else {
1408                 IWL_ERR(priv, "invalid channel switch from %u to %u\n",
1409                         priv->active_rxon.channel, channel);
1410                 return -EFAULT;
1411         }
1412         priv->switch_rxon.channel = cpu_to_le16(channel);
1413         priv->switch_rxon.switch_in_progress = true;
1414
1415         return iwl_send_cmd_sync(priv, &hcmd);
1416 }
1417
1418 struct iwl_hcmd_ops iwl5000_hcmd = {
1419         .rxon_assoc = iwl5000_send_rxon_assoc,
1420         .commit_rxon = iwl_commit_rxon,
1421         .set_rxon_chain = iwl_set_rxon_chain,
1422         .set_tx_ant = iwl5000_send_tx_ant_config,
1423 };
1424
1425 struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
1426         .get_hcmd_size = iwl5000_get_hcmd_size,
1427         .build_addsta_hcmd = iwl5000_build_addsta_hcmd,
1428         .gain_computation = iwl5000_gain_computation,
1429         .chain_noise_reset = iwl5000_chain_noise_reset,
1430         .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag,
1431         .calc_rssi = iwl5000_calc_rssi,
1432 };
1433
1434 struct iwl_ucode_ops iwl5000_ucode = {
1435         .get_header_size = iwl5000_ucode_get_header_size,
1436         .get_build = iwl5000_ucode_get_build,
1437         .get_inst_size = iwl5000_ucode_get_inst_size,
1438         .get_data_size = iwl5000_ucode_get_data_size,
1439         .get_init_size = iwl5000_ucode_get_init_size,
1440         .get_init_data_size = iwl5000_ucode_get_init_data_size,
1441         .get_boot_size = iwl5000_ucode_get_boot_size,
1442         .get_data = iwl5000_ucode_get_data,
1443 };
1444
1445 struct iwl_lib_ops iwl5000_lib = {
1446         .set_hw_params = iwl5000_hw_set_hw_params,
1447         .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1448         .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1449         .txq_set_sched = iwl5000_txq_set_sched,
1450         .txq_agg_enable = iwl5000_txq_agg_enable,
1451         .txq_agg_disable = iwl5000_txq_agg_disable,
1452         .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
1453         .txq_free_tfd = iwl_hw_txq_free_tfd,
1454         .txq_init = iwl_hw_tx_queue_init,
1455         .rx_handler_setup = iwl5000_rx_handler_setup,
1456         .setup_deferred_work = iwl5000_setup_deferred_work,
1457         .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
1458         .dump_nic_event_log = iwl_dump_nic_event_log,
1459         .dump_nic_error_log = iwl_dump_nic_error_log,
1460         .dump_csr = iwl_dump_csr,
1461         .dump_fh = iwl_dump_fh,
1462         .load_ucode = iwl5000_load_ucode,
1463         .init_alive_start = iwl5000_init_alive_start,
1464         .alive_notify = iwl5000_alive_notify,
1465         .send_tx_power = iwl5000_send_tx_power,
1466         .update_chain_flags = iwl_update_chain_flags,
1467         .set_channel_switch = iwl5000_hw_channel_switch,
1468         .apm_ops = {
1469                 .init = iwl_apm_init,
1470                 .stop = iwl_apm_stop,
1471                 .config = iwl5000_nic_config,
1472                 .set_pwr_src = iwl_set_pwr_src,
1473         },
1474         .eeprom_ops = {
1475                 .regulatory_bands = {
1476                         EEPROM_5000_REG_BAND_1_CHANNELS,
1477                         EEPROM_5000_REG_BAND_2_CHANNELS,
1478                         EEPROM_5000_REG_BAND_3_CHANNELS,
1479                         EEPROM_5000_REG_BAND_4_CHANNELS,
1480                         EEPROM_5000_REG_BAND_5_CHANNELS,
1481                         EEPROM_5000_REG_BAND_24_HT40_CHANNELS,
1482                         EEPROM_5000_REG_BAND_52_HT40_CHANNELS
1483                 },
1484                 .verify_signature  = iwlcore_eeprom_verify_signature,
1485                 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1486                 .release_semaphore = iwlcore_eeprom_release_semaphore,
1487                 .calib_version  = iwl5000_eeprom_calib_version,
1488                 .query_addr = iwl5000_eeprom_query_addr,
1489         },
1490         .post_associate = iwl_post_associate,
1491         .isr = iwl_isr_ict,
1492         .config_ap = iwl_config_ap,
1493         .temp_ops = {
1494                 .temperature = iwl5000_temperature,
1495                 .set_ct_kill = iwl5000_set_ct_threshold,
1496          },
1497         .add_bcast_station = iwl_add_bcast_station,
1498 };
1499
1500 static struct iwl_lib_ops iwl5150_lib = {
1501         .set_hw_params = iwl5000_hw_set_hw_params,
1502         .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1503         .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1504         .txq_set_sched = iwl5000_txq_set_sched,
1505         .txq_agg_enable = iwl5000_txq_agg_enable,
1506         .txq_agg_disable = iwl5000_txq_agg_disable,
1507         .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
1508         .txq_free_tfd = iwl_hw_txq_free_tfd,
1509         .txq_init = iwl_hw_tx_queue_init,
1510         .rx_handler_setup = iwl5000_rx_handler_setup,
1511         .setup_deferred_work = iwl5000_setup_deferred_work,
1512         .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
1513         .dump_nic_event_log = iwl_dump_nic_event_log,
1514         .dump_nic_error_log = iwl_dump_nic_error_log,
1515         .dump_csr = iwl_dump_csr,
1516         .load_ucode = iwl5000_load_ucode,
1517         .init_alive_start = iwl5000_init_alive_start,
1518         .alive_notify = iwl5000_alive_notify,
1519         .send_tx_power = iwl5000_send_tx_power,
1520         .update_chain_flags = iwl_update_chain_flags,
1521         .set_channel_switch = iwl5000_hw_channel_switch,
1522         .apm_ops = {
1523                 .init = iwl_apm_init,
1524                 .stop = iwl_apm_stop,
1525                 .config = iwl5000_nic_config,
1526                 .set_pwr_src = iwl_set_pwr_src,
1527         },
1528         .eeprom_ops = {
1529                 .regulatory_bands = {
1530                         EEPROM_5000_REG_BAND_1_CHANNELS,
1531                         EEPROM_5000_REG_BAND_2_CHANNELS,
1532                         EEPROM_5000_REG_BAND_3_CHANNELS,
1533                         EEPROM_5000_REG_BAND_4_CHANNELS,
1534                         EEPROM_5000_REG_BAND_5_CHANNELS,
1535                         EEPROM_5000_REG_BAND_24_HT40_CHANNELS,
1536                         EEPROM_5000_REG_BAND_52_HT40_CHANNELS
1537                 },
1538                 .verify_signature  = iwlcore_eeprom_verify_signature,
1539                 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1540                 .release_semaphore = iwlcore_eeprom_release_semaphore,
1541                 .calib_version  = iwl5000_eeprom_calib_version,
1542                 .query_addr = iwl5000_eeprom_query_addr,
1543         },
1544         .post_associate = iwl_post_associate,
1545         .isr = iwl_isr_ict,
1546         .config_ap = iwl_config_ap,
1547         .temp_ops = {
1548                 .temperature = iwl5150_temperature,
1549                 .set_ct_kill = iwl5150_set_ct_threshold,
1550          },
1551         .add_bcast_station = iwl_add_bcast_station,
1552 };
1553
1554 static const struct iwl_ops iwl5000_ops = {
1555         .ucode = &iwl5000_ucode,
1556         .lib = &iwl5000_lib,
1557         .hcmd = &iwl5000_hcmd,
1558         .utils = &iwl5000_hcmd_utils,
1559         .led = &iwlagn_led_ops,
1560 };
1561
1562 static const struct iwl_ops iwl5150_ops = {
1563         .ucode = &iwl5000_ucode,
1564         .lib = &iwl5150_lib,
1565         .hcmd = &iwl5000_hcmd,
1566         .utils = &iwl5000_hcmd_utils,
1567         .led = &iwlagn_led_ops,
1568 };
1569
1570 struct iwl_mod_params iwl50_mod_params = {
1571         .amsdu_size_8K = 1,
1572         .restart_fw = 1,
1573         /* the rest are 0 by default */
1574 };
1575
1576
1577 struct iwl_cfg iwl5300_agn_cfg = {
1578         .name = "5300AGN",
1579         .fw_name_pre = IWL5000_FW_PRE,
1580         .ucode_api_max = IWL5000_UCODE_API_MAX,
1581         .ucode_api_min = IWL5000_UCODE_API_MIN,
1582         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1583         .ops = &iwl5000_ops,
1584         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1585         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1586         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1587         .num_of_queues = IWL50_NUM_QUEUES,
1588         .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1589         .mod_params = &iwl50_mod_params,
1590         .valid_tx_ant = ANT_ABC,
1591         .valid_rx_ant = ANT_ABC,
1592         .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1593         .set_l0s = true,
1594         .use_bsm = false,
1595         .ht_greenfield_support = true,
1596         .led_compensation = 51,
1597         .use_rts_for_ht = true, /* use rts/cts protection */
1598         .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1599         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
1600         .chain_noise_scale = 1000,
1601 };
1602
1603 struct iwl_cfg iwl5100_bgn_cfg = {
1604         .name = "5100BGN",
1605         .fw_name_pre = IWL5000_FW_PRE,
1606         .ucode_api_max = IWL5000_UCODE_API_MAX,
1607         .ucode_api_min = IWL5000_UCODE_API_MIN,
1608         .sku = IWL_SKU_G|IWL_SKU_N,
1609         .ops = &iwl5000_ops,
1610         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1611         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1612         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1613         .num_of_queues = IWL50_NUM_QUEUES,
1614         .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1615         .mod_params = &iwl50_mod_params,
1616         .valid_tx_ant = ANT_B,
1617         .valid_rx_ant = ANT_AB,
1618         .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1619         .set_l0s = true,
1620         .use_bsm = false,
1621         .ht_greenfield_support = true,
1622         .led_compensation = 51,
1623         .use_rts_for_ht = true, /* use rts/cts protection */
1624         .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1625         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
1626         .chain_noise_scale = 1000,
1627 };
1628
1629 struct iwl_cfg iwl5100_abg_cfg = {
1630         .name = "5100ABG",
1631         .fw_name_pre = IWL5000_FW_PRE,
1632         .ucode_api_max = IWL5000_UCODE_API_MAX,
1633         .ucode_api_min = IWL5000_UCODE_API_MIN,
1634         .sku = IWL_SKU_A|IWL_SKU_G,
1635         .ops = &iwl5000_ops,
1636         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1637         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1638         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1639         .num_of_queues = IWL50_NUM_QUEUES,
1640         .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1641         .mod_params = &iwl50_mod_params,
1642         .valid_tx_ant = ANT_B,
1643         .valid_rx_ant = ANT_AB,
1644         .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1645         .set_l0s = true,
1646         .use_bsm = false,
1647         .led_compensation = 51,
1648         .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1649         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
1650         .chain_noise_scale = 1000,
1651 };
1652
1653 struct iwl_cfg iwl5100_agn_cfg = {
1654         .name = "5100AGN",
1655         .fw_name_pre = IWL5000_FW_PRE,
1656         .ucode_api_max = IWL5000_UCODE_API_MAX,
1657         .ucode_api_min = IWL5000_UCODE_API_MIN,
1658         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1659         .ops = &iwl5000_ops,
1660         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1661         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1662         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1663         .num_of_queues = IWL50_NUM_QUEUES,
1664         .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1665         .mod_params = &iwl50_mod_params,
1666         .valid_tx_ant = ANT_B,
1667         .valid_rx_ant = ANT_AB,
1668         .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1669         .set_l0s = true,
1670         .use_bsm = false,
1671         .ht_greenfield_support = true,
1672         .led_compensation = 51,
1673         .use_rts_for_ht = true, /* use rts/cts protection */
1674         .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1675         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
1676         .chain_noise_scale = 1000,
1677 };
1678
1679 struct iwl_cfg iwl5350_agn_cfg = {
1680         .name = "5350AGN",
1681         .fw_name_pre = IWL5000_FW_PRE,
1682         .ucode_api_max = IWL5000_UCODE_API_MAX,
1683         .ucode_api_min = IWL5000_UCODE_API_MIN,
1684         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1685         .ops = &iwl5000_ops,
1686         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1687         .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1688         .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1689         .num_of_queues = IWL50_NUM_QUEUES,
1690         .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1691         .mod_params = &iwl50_mod_params,
1692         .valid_tx_ant = ANT_ABC,
1693         .valid_rx_ant = ANT_ABC,
1694         .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1695         .set_l0s = true,
1696         .use_bsm = false,
1697         .ht_greenfield_support = true,
1698         .led_compensation = 51,
1699         .use_rts_for_ht = true, /* use rts/cts protection */
1700         .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1701         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
1702         .chain_noise_scale = 1000,
1703 };
1704
1705 struct iwl_cfg iwl5150_agn_cfg = {
1706         .name = "5150AGN",
1707         .fw_name_pre = IWL5150_FW_PRE,
1708         .ucode_api_max = IWL5150_UCODE_API_MAX,
1709         .ucode_api_min = IWL5150_UCODE_API_MIN,
1710         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1711         .ops = &iwl5150_ops,
1712         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1713         .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1714         .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1715         .num_of_queues = IWL50_NUM_QUEUES,
1716         .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1717         .mod_params = &iwl50_mod_params,
1718         .valid_tx_ant = ANT_A,
1719         .valid_rx_ant = ANT_AB,
1720         .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1721         .set_l0s = true,
1722         .use_bsm = false,
1723         .ht_greenfield_support = true,
1724         .led_compensation = 51,
1725         .use_rts_for_ht = true, /* use rts/cts protection */
1726         .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1727         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
1728         .chain_noise_scale = 1000,
1729 };
1730
1731 struct iwl_cfg iwl5150_abg_cfg = {
1732         .name = "5150ABG",
1733         .fw_name_pre = IWL5150_FW_PRE,
1734         .ucode_api_max = IWL5150_UCODE_API_MAX,
1735         .ucode_api_min = IWL5150_UCODE_API_MIN,
1736         .sku = IWL_SKU_A|IWL_SKU_G,
1737         .ops = &iwl5150_ops,
1738         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1739         .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1740         .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1741         .num_of_queues = IWL50_NUM_QUEUES,
1742         .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1743         .mod_params = &iwl50_mod_params,
1744         .valid_tx_ant = ANT_A,
1745         .valid_rx_ant = ANT_AB,
1746         .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1747         .set_l0s = true,
1748         .use_bsm = false,
1749         .led_compensation = 51,
1750         .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1751         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
1752         .chain_noise_scale = 1000,
1753 };
1754
1755 MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE(IWL5000_UCODE_API_MAX));
1756 MODULE_FIRMWARE(IWL5150_MODULE_FIRMWARE(IWL5150_UCODE_API_MAX));
1757
1758 module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, S_IRUGO);
1759 MODULE_PARM_DESC(swcrypto50,
1760                   "using software crypto engine (default 0 [hardware])\n");
1761 module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, S_IRUGO);
1762 MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
1763 module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, S_IRUGO);
1764 MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality");
1765 module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K,
1766                    int, S_IRUGO);
1767 MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
1768 module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, S_IRUGO);
1769 MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error");