SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/iwlwifi/iwl-5000.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2010 Intel Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  23  *
  24  *****************************************************************************/
  25
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28 #include <linux/init.h>
  29 #include <linux/pci.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/delay.h>
  32 #include <linux/sched.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/netdevice.h>
  35 #include <linux/wireless.h>
  36 #include <net/mac80211.h>
  37 #include <linux/etherdevice.h>
  38 #include <asm/unaligned.h>
  39
  40 #include "iwl-eeprom.h"
  41 #include "iwl-dev.h"
  42 #include "iwl-core.h"
  43 #include "iwl-io.h"
  44 #include "iwl-sta.h"
  45 #include "iwl-helpers.h"
  46 #include "iwl-agn-led.h"
  47 #include "iwl-5000-hw.h"
  48 #include "iwl-6000-hw.h"
  49
  50 /* Highest firmware API version supported */
  51 #define IWL5000_UCODE_API_MAX 2
  52 #define IWL5150_UCODE_API_MAX 2
  53
  54 /* Lowest firmware API version supported */
  55 #define IWL5000_UCODE_API_MIN 1
  56 #define IWL5150_UCODE_API_MIN 1
  57
  58 #define IWL5000_FW_PRE "iwlwifi-5000-"
  59 #define _IWL5000_MODULE_FIRMWARE(api) IWL5000_FW_PRE #api ".ucode"
  60 #define IWL5000_MODULE_FIRMWARE(api) _IWL5000_MODULE_FIRMWARE(api)
  61
  62 #define IWL5150_FW_PRE "iwlwifi-5150-"
  63 #define _IWL5150_MODULE_FIRMWARE(api) IWL5150_FW_PRE #api ".ucode"
  64 #define IWL5150_MODULE_FIRMWARE(api) _IWL5150_MODULE_FIRMWARE(api)
  65
  66 static const u16 iwl5000_default_queue_to_tx_fifo[] = {
  67         IWL_TX_FIFO_AC3,
  68         IWL_TX_FIFO_AC2,
  69         IWL_TX_FIFO_AC1,
  70         IWL_TX_FIFO_AC0,
  71         IWL50_CMD_FIFO_NUM,
  72         IWL_TX_FIFO_HCCA_1,
  73         IWL_TX_FIFO_HCCA_2
  74 };
  75
  76 /* NIC configuration for 5000 series */
  77 void iwl5000_nic_config(struct iwl_priv *priv)
  78 {
  79         unsigned long flags;
  80         u16 radio_cfg;
  81
  82         spin_lock_irqsave(&priv->lock, flags);
  83
  84         radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
  85
  86         /* write radio config values to register */
  87         if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_RF_CONFIG_TYPE_MAX)
  88                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  89                             EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
  90                             EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
  91                             EEPROM_RF_CFG_DASH_MSK(radio_cfg));
  92
  93         /* set CSR_HW_CONFIG_REG for uCode use */
  94         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  95                     CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
  96                     CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
  97
  98         /* W/A : NIC is stuck in a reset state after Early PCIe power off
  99          * (PCIe power is lost before PERST# is asserted),
 100          * causing ME FW to lose ownership and not being able to obtain it back.
 101          */
 102         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 103                                 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
 104                                 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
 105
 106
 107         spin_unlock_irqrestore(&priv->lock, flags);
 108 }
 109
 110
 111 /*
 112  * EEPROM
 113  */
 114 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
 115 {
 116         u16 offset = 0;
 117
 118         if ((address & INDIRECT_ADDRESS) == 0)
 119                 return address;
 120
 121         switch (address & INDIRECT_TYPE_MSK) {
 122         case INDIRECT_HOST:
 123                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
 124                 break;
 125         case INDIRECT_GENERAL:
 126                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
 127                 break;
 128         case INDIRECT_REGULATORY:
 129                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
 130                 break;
 131         case INDIRECT_CALIBRATION:
 132                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
 133                 break;
 134         case INDIRECT_PROCESS_ADJST:
 135                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
 136                 break;
 137         case INDIRECT_OTHERS:
 138                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
 139                 break;
 140         default:
 141                 IWL_ERR(priv, "illegal indirect type: 0x%X\n",
 142                 address & INDIRECT_TYPE_MSK);
 143                 break;
 144         }
 145
 146         /* translate the offset from words to byte */
 147         return (address & ADDRESS_MSK) + (offset << 1);
 148 }
 149
 150 u16 iwl5000_eeprom_calib_version(struct iwl_priv *priv)
 151 {
 152         struct iwl_eeprom_calib_hdr {
 153                 u8 version;
 154                 u8 pa_type;
 155                 u16 voltage;
 156         } *hdr;
 157
 158         hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
 159                                                         EEPROM_5000_CALIB_ALL);
 160         return hdr->version;
 161
 162 }
 163
 164 static void iwl5000_gain_computation(struct iwl_priv *priv,
 165                 u32 average_noise[NUM_RX_CHAINS],
 166                 u16 min_average_noise_antenna_i,
 167                 u32 min_average_noise,
 168                 u8 default_chain)
 169 {
 170         int i;
 171         s32 delta_g;
 172         struct iwl_chain_noise_data *data = &priv->chain_noise_data;
 173
 174         /*
 175          * Find Gain Code for the chains based on "default chain"
 176          */
 177         for (i = default_chain + 1; i < NUM_RX_CHAINS; i++) {
 178                 if ((data->disconn_array[i])) {
 179                         data->delta_gain_code[i] = 0;
 180                         continue;
 181                 }
 182
 183                 delta_g = (priv->cfg->chain_noise_scale *
 184                         ((s32)average_noise[default_chain] -
 185                         (s32)average_noise[i])) / 1500;
 186
 187                 /* bound gain by 2 bits value max, 3rd bit is sign */
 188                 data->delta_gain_code[i] =
 189                         min(abs(delta_g), (long) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
 190
 191                 if (delta_g < 0)
 192                         /*
 193                          * set negative sign ...
 194                          * note to Intel developers:  This is uCode API format,
 195                          *   not the format of any internal device registers.
 196                          *   Do not change this format for e.g. 6050 or similar
 197                          *   devices.  Change format only if more resolution
 198                          *   (i.e. more than 2 bits magnitude) is needed.
 199                          */
 200                         data->delta_gain_code[i] |= (1 << 2);
 201         }
 202
 203         IWL_DEBUG_CALIB(priv, "Delta gains: ANT_B = %d  ANT_C = %d\n",
 204                         data->delta_gain_code[1], data->delta_gain_code[2]);
 205
 206         if (!data->radio_write) {
 207                 struct iwl_calib_chain_noise_gain_cmd cmd;
 208
 209                 memset(&cmd, 0, sizeof(cmd));
 210
 211                 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD;
 212                 cmd.hdr.first_group = 0;
 213                 cmd.hdr.groups_num = 1;
 214                 cmd.hdr.data_valid = 1;
 215                 cmd.delta_gain_1 = data->delta_gain_code[1];
 216                 cmd.delta_gain_2 = data->delta_gain_code[2];
 217                 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
 218                         sizeof(cmd), &cmd, NULL);
 219
 220                 data->radio_write = 1;
 221                 data->state = IWL_CHAIN_NOISE_CALIBRATED;
 222         }
 223
 224         data->chain_noise_a = 0;
 225         data->chain_noise_b = 0;
 226         data->chain_noise_c = 0;
 227         data->chain_signal_a = 0;
 228         data->chain_signal_b = 0;
 229         data->chain_signal_c = 0;
 230         data->beacon_count = 0;
 231 }
 232
 233 static void iwl5000_chain_noise_reset(struct iwl_priv *priv)
 234 {
 235         struct iwl_chain_noise_data *data = &priv->chain_noise_data;
 236         int ret;
 237
 238         if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
 239                 struct iwl_calib_chain_noise_reset_cmd cmd;
 240                 memset(&cmd, 0, sizeof(cmd));
 241
 242                 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD;
 243                 cmd.hdr.first_group = 0;
 244                 cmd.hdr.groups_num = 1;
 245                 cmd.hdr.data_valid = 1;
 246                 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
 247                                         sizeof(cmd), &cmd);
 248                 if (ret)
 249                         IWL_ERR(priv,
 250                                 "Could not send REPLY_PHY_CALIBRATION_CMD\n");
 251                 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
 252                 IWL_DEBUG_CALIB(priv, "Run chain_noise_calibrate\n");
 253         }
 254 }
 255
 256 void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
 257                         __le32 *tx_flags)
 258 {
 259         if ((info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) ||
 260             (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT))
 261                 *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK;
 262         else
 263                 *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK;
 264 }
 265
 266 static struct iwl_sensitivity_ranges iwl5000_sensitivity = {
 267         .min_nrg_cck = 95,
 268         .max_nrg_cck = 0, /* not used, set to 0 */
 269         .auto_corr_min_ofdm = 90,
 270         .auto_corr_min_ofdm_mrc = 170,
 271         .auto_corr_min_ofdm_x1 = 120,
 272         .auto_corr_min_ofdm_mrc_x1 = 240,
 273
 274         .auto_corr_max_ofdm = 120,
 275         .auto_corr_max_ofdm_mrc = 210,
 276         .auto_corr_max_ofdm_x1 = 120,
 277         .auto_corr_max_ofdm_mrc_x1 = 240,
 278
 279         .auto_corr_min_cck = 125,
 280         .auto_corr_max_cck = 200,
 281         .auto_corr_min_cck_mrc = 170,
 282         .auto_corr_max_cck_mrc = 400,
 283         .nrg_th_cck = 95,
 284         .nrg_th_ofdm = 95,
 285
 286         .barker_corr_th_min = 190,
 287         .barker_corr_th_min_mrc = 390,
 288         .nrg_th_cca = 62,
 289 };
 290
 291 static struct iwl_sensitivity_ranges iwl5150_sensitivity = {
 292         .min_nrg_cck = 95,
 293         .max_nrg_cck = 0, /* not used, set to 0 */
 294         .auto_corr_min_ofdm = 90,
 295         .auto_corr_min_ofdm_mrc = 170,
 296         .auto_corr_min_ofdm_x1 = 105,
 297         .auto_corr_min_ofdm_mrc_x1 = 220,
 298
 299         .auto_corr_max_ofdm = 120,
 300         .auto_corr_max_ofdm_mrc = 210,
 301         /* max = min for performance bug in 5150 DSP */
 302         .auto_corr_max_ofdm_x1 = 105,
 303         .auto_corr_max_ofdm_mrc_x1 = 220,
 304
 305         .auto_corr_min_cck = 125,
 306         .auto_corr_max_cck = 200,
 307         .auto_corr_min_cck_mrc = 170,
 308         .auto_corr_max_cck_mrc = 400,
 309         .nrg_th_cck = 95,
 310         .nrg_th_ofdm = 95,
 311
 312         .barker_corr_th_min = 190,
 313         .barker_corr_th_min_mrc = 390,
 314         .nrg_th_cca = 62,
 315 };
 316
 317 const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
 318                                            size_t offset)
 319 {
 320         u32 address = eeprom_indirect_address(priv, offset);
 321         BUG_ON(address >= priv->cfg->eeprom_size);
 322         return &priv->eeprom[address];
 323 }
 324
 325 static void iwl5150_set_ct_threshold(struct iwl_priv *priv)
 326 {
 327         const s32 volt2temp_coef = IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF;
 328         s32 threshold = (s32)CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD_LEGACY) -
 329                         iwl_temp_calib_to_offset(priv);
 330
 331         priv->hw_params.ct_kill_threshold = threshold * volt2temp_coef;
 332 }
 333
 334 static void iwl5000_set_ct_threshold(struct iwl_priv *priv)
 335 {
 336         /* want Celsius */
 337         priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD_LEGACY;
 338 }
 339
 340 /*
 341  *  Calibration
 342  */
 343 static int iwl5000_set_Xtal_calib(struct iwl_priv *priv)
 344 {
 345         struct iwl_calib_xtal_freq_cmd cmd;
 346         __le16 *xtal_calib =
 347                 (__le16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL);
 348
 349         cmd.hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD;
 350         cmd.hdr.first_group = 0;
 351         cmd.hdr.groups_num = 1;
 352         cmd.hdr.data_valid = 1;
 353         cmd.cap_pin1 = le16_to_cpu(xtal_calib[0]);
 354         cmd.cap_pin2 = le16_to_cpu(xtal_calib[1]);
 355         return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
 356                              (u8 *)&cmd, sizeof(cmd));
 357 }
 358
 359 static int iwl5000_send_calib_cfg(struct iwl_priv *priv)
 360 {
 361         struct iwl_calib_cfg_cmd calib_cfg_cmd;
 362         struct iwl_host_cmd cmd = {
 363                 .id = CALIBRATION_CFG_CMD,
 364                 .len = sizeof(struct iwl_calib_cfg_cmd),
 365                 .data = &calib_cfg_cmd,
 366         };
 367
 368         memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
 369         calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
 370         calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
 371         calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
 372         calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
 373
 374         return iwl_send_cmd(priv, &cmd);
 375 }
 376
 377 static void iwl5000_rx_calib_result(struct iwl_priv *priv,
 378                              struct iwl_rx_mem_buffer *rxb)
 379 {
 380         struct iwl_rx_packet *pkt = rxb_addr(rxb);
 381         struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
 382         int len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
 383         int index;
 384
 385         /* reduce the size of the length field itself */
 386         len -= 4;
 387
 388         /* Define the order in which the results will be sent to the runtime
 389          * uCode. iwl_send_calib_results sends them in a row according to their
 390          * index. We sort them here */
 391         switch (hdr->op_code) {
 392         case IWL_PHY_CALIBRATE_DC_CMD:
 393                 index = IWL_CALIB_DC;
 394                 break;
 395         case IWL_PHY_CALIBRATE_LO_CMD:
 396                 index = IWL_CALIB_LO;
 397                 break;
 398         case IWL_PHY_CALIBRATE_TX_IQ_CMD:
 399                 index = IWL_CALIB_TX_IQ;
 400                 break;
 401         case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
 402                 index = IWL_CALIB_TX_IQ_PERD;
 403                 break;
 404         case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
 405                 index = IWL_CALIB_BASE_BAND;
 406                 break;
 407         default:
 408                 IWL_ERR(priv, "Unknown calibration notification %d\n",
 409                           hdr->op_code);
 410                 return;
 411         }
 412         iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
 413 }
 414
 415 static void iwl5000_rx_calib_complete(struct iwl_priv *priv,
 416                                struct iwl_rx_mem_buffer *rxb)
 417 {
 418         IWL_DEBUG_INFO(priv, "Init. calibration is completed, restarting fw.\n");
 419         queue_work(priv->workqueue, &priv->restart);
 420 }
 421
 422 /*
 423  * ucode
 424  */
 425 static int iwl5000_load_section(struct iwl_priv *priv, const char *name,
 426                                 struct fw_desc *image, u32 dst_addr)
 427 {
 428         dma_addr_t phy_addr = image->p_addr;
 429         u32 byte_cnt = image->len;
 430         int ret;
 431
 432         priv->ucode_write_complete = 0;
 433
 434         iwl_write_direct32(priv,
 435                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 436                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 437
 438         iwl_write_direct32(priv,
 439                 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
 440
 441         iwl_write_direct32(priv,
 442                 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 443                 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 444
 445         iwl_write_direct32(priv,
 446                 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 447                 (iwl_get_dma_hi_addr(phy_addr)
 448                         << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 449
 450         iwl_write_direct32(priv,
 451                 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 452                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 453                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 454                 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 455
 456         iwl_write_direct32(priv,
 457                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 458                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE       |
 459                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE    |
 460                 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 461
 462         IWL_DEBUG_INFO(priv, "%s uCode section being loaded...\n", name);
 463         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
 464                                         priv->ucode_write_complete, 5 * HZ);
 465         if (ret == -ERESTARTSYS) {
 466                 IWL_ERR(priv, "Could not load the %s uCode section due "
 467                         "to interrupt\n", name);
 468                 return ret;
 469         }
 470         if (!ret) {
 471                 IWL_ERR(priv, "Could not load the %s uCode section\n",
 472                         name);
 473                 return -ETIMEDOUT;
 474         }
 475
 476         return 0;
 477 }
 478
 479 static int iwl5000_load_given_ucode(struct iwl_priv *priv,
 480                 struct fw_desc *inst_image,
 481                 struct fw_desc *data_image)
 482 {
 483         int ret = 0;
 484
 485         ret = iwl5000_load_section(priv, "INST", inst_image,
 486                                    IWL50_RTC_INST_LOWER_BOUND);
 487         if (ret)
 488                 return ret;
 489
 490         return iwl5000_load_section(priv, "DATA", data_image,
 491                                     IWL50_RTC_DATA_LOWER_BOUND);
 492 }
 493
 494 int iwl5000_load_ucode(struct iwl_priv *priv)
 495 {
 496         int ret = 0;
 497
 498         /* check whether init ucode should be loaded, or rather runtime ucode */
 499         if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
 500                 IWL_DEBUG_INFO(priv, "Init ucode found. Loading init ucode...\n");
 501                 ret = iwl5000_load_given_ucode(priv,
 502                         &priv->ucode_init, &priv->ucode_init_data);
 503                 if (!ret) {
 504                         IWL_DEBUG_INFO(priv, "Init ucode load complete.\n");
 505                         priv->ucode_type = UCODE_INIT;
 506                 }
 507         } else {
 508                 IWL_DEBUG_INFO(priv, "Init ucode not found, or already loaded. "
 509                         "Loading runtime ucode...\n");
 510                 ret = iwl5000_load_given_ucode(priv,
 511                         &priv->ucode_code, &priv->ucode_data);
 512                 if (!ret) {
 513                         IWL_DEBUG_INFO(priv, "Runtime ucode load complete.\n");
 514                         priv->ucode_type = UCODE_RT;
 515                 }
 516         }
 517
 518         return ret;
 519 }
 520
 521 void iwl5000_init_alive_start(struct iwl_priv *priv)
 522 {
 523         int ret = 0;
 524
 525         /* Check alive response for "valid" sign from uCode */
 526         if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
 527                 /* We had an error bringing up the hardware, so take it
 528                  * all the way back down so we can try again */
 529                 IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
 530                 goto restart;
 531         }
 532
 533         /* initialize uCode was loaded... verify inst image.
 534          * This is a paranoid check, because we would not have gotten the
 535          * "initialize" alive if code weren't properly loaded.  */
 536         if (iwl_verify_ucode(priv)) {
 537                 /* Runtime instruction load was bad;
 538                  * take it all the way back down so we can try again */
 539                 IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
 540                 goto restart;
 541         }
 542
 543         iwl_clear_stations_table(priv);
 544         ret = priv->cfg->ops->lib->alive_notify(priv);
 545         if (ret) {
 546                 IWL_WARN(priv,
 547                         "Could not complete ALIVE transition: %d\n", ret);
 548                 goto restart;
 549         }
 550
 551         iwl5000_send_calib_cfg(priv);
 552         return;
 553
 554 restart:
 555         /* real restart (first load init_ucode) */
 556         queue_work(priv->workqueue, &priv->restart);
 557 }
 558
 559 static void iwl5000_set_wr_ptrs(struct iwl_priv *priv,
 560                                 int txq_id, u32 index)
 561 {
 562         iwl_write_direct32(priv, HBUS_TARG_WRPTR,
 563                         (index & 0xff) | (txq_id << 8));
 564         iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index);
 565 }
 566
 567 static void iwl5000_tx_queue_set_status(struct iwl_priv *priv,
 568                                         struct iwl_tx_queue *txq,
 569                                         int tx_fifo_id, int scd_retry)
 570 {
 571         int txq_id = txq->q.id;
 572         int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
 573
 574         iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
 575                         (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
 576                         (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) |
 577                         (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) |
 578                         IWL50_SCD_QUEUE_STTS_REG_MSK);
 579
 580         txq->sched_retry = scd_retry;
 581
 582         IWL_DEBUG_INFO(priv, "%s %s Queue %d on AC %d\n",
 583                        active ? "Activate" : "Deactivate",
 584                        scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
 585 }
 586
 587 int iwl5000_alive_notify(struct iwl_priv *priv)
 588 {
 589         u32 a;
 590         unsigned long flags;
 591         int i, chan;
 592         u32 reg_val;
 593
 594         spin_lock_irqsave(&priv->lock, flags);
 595
 596         priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
 597         a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
 598         for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
 599                 a += 4)
 600                 iwl_write_targ_mem(priv, a, 0);
 601         for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
 602                 a += 4)
 603                 iwl_write_targ_mem(priv, a, 0);
 604         for (; a < priv->scd_base_addr +
 605                IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(priv->hw_params.max_txq_num); a += 4)
 606                 iwl_write_targ_mem(priv, a, 0);
 607
 608         iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
 609                        priv->scd_bc_tbls.dma >> 10);
 610
 611         /* Enable DMA channel */
 612         for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++)
 613                 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
 614                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
 615                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
 616
 617         /* Update FH chicken bits */
 618         reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
 619         iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
 620                            reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
 621
 622         iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
 623                 IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num));
 624         iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
 625
 626         /* initiate the queues */
 627         for (i = 0; i < priv->hw_params.max_txq_num; i++) {
 628                 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
 629                 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
 630                 iwl_write_targ_mem(priv, priv->scd_base_addr +
 631                                 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
 632                 iwl_write_targ_mem(priv, priv->scd_base_addr +
 633                                 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
 634                                 sizeof(u32),
 635                                 ((SCD_WIN_SIZE <<
 636                                 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
 637                                 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
 638                                 ((SCD_FRAME_LIMIT <<
 639                                 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
 640                                 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
 641         }
 642
 643         iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
 644                         IWL_MASK(0, priv->hw_params.max_txq_num));
 645
 646         /* Activate all Tx DMA/FIFO channels */
 647         priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
 648
 649         iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
 650
 651         /* reset to 0 to enable all the queue first */
 652         priv->txq_ctx_active_msk = 0;
 653         /* map qos queues to fifos one-to-one */
 654         for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
 655                 int ac = iwl5000_default_queue_to_tx_fifo[i];
 656                 iwl_txq_ctx_activate(priv, i);
 657                 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
 658         }
 659
 660         /*
 661          * TODO - need to initialize these queues and map them to FIFOs
 662          * in the loop above, not only mark them as active. We do this
 663          * because we want the first aggregation queue to be queue #10,
 664          * but do not use 8 or 9 otherwise yet.
 665          */
 666         iwl_txq_ctx_activate(priv, 7);
 667         iwl_txq_ctx_activate(priv, 8);
 668         iwl_txq_ctx_activate(priv, 9);
 669
 670         spin_unlock_irqrestore(&priv->lock, flags);
 671
 672
 673         iwl_send_wimax_coex(priv);
 674
 675         iwl5000_set_Xtal_calib(priv);
 676         iwl_send_calib_results(priv);
 677
 678         return 0;
 679 }
 680
 681 int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
 682 {
 683         if (priv->cfg->mod_params->num_of_queues >= IWL_MIN_NUM_QUEUES &&
 684             priv->cfg->mod_params->num_of_queues <= IWL50_NUM_QUEUES)
 685                 priv->cfg->num_of_queues =
 686                         priv->cfg->mod_params->num_of_queues;
 687
 688         priv->hw_params.max_txq_num = priv->cfg->num_of_queues;
 689         priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM;
 690         priv->hw_params.scd_bc_tbls_size =
 691                         priv->cfg->num_of_queues *
 692                         sizeof(struct iwl5000_scd_bc_tbl);
 693         priv->hw_params.tfd_size = sizeof(struct iwl_tfd);
 694         priv->hw_params.max_stations = IWL5000_STATION_COUNT;
 695         priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
 696
 697         priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
 698         priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
 699
 700         priv->hw_params.max_bsm_size = 0;
 701         priv->hw_params.ht40_channel =  BIT(IEEE80211_BAND_2GHZ) |
 702                                         BIT(IEEE80211_BAND_5GHZ);
 703         priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR;
 704
 705         priv->hw_params.tx_chains_num = num_of_ant(priv->cfg->valid_tx_ant);
 706         priv->hw_params.rx_chains_num = num_of_ant(priv->cfg->valid_rx_ant);
 707         priv->hw_params.valid_tx_ant = priv->cfg->valid_tx_ant;
 708         priv->hw_params.valid_rx_ant = priv->cfg->valid_rx_ant;
 709
 710         if (priv->cfg->ops->lib->temp_ops.set_ct_kill)
 711                 priv->cfg->ops->lib->temp_ops.set_ct_kill(priv);
 712
 713         /* Set initial sensitivity parameters */
 714         /* Set initial calibration set */
 715         switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
 716         case CSR_HW_REV_TYPE_5150:
 717                 priv->hw_params.sens = &iwl5150_sensitivity;
 718                 priv->hw_params.calib_init_cfg =
 719                         BIT(IWL_CALIB_DC)               |
 720                         BIT(IWL_CALIB_LO)               |
 721                         BIT(IWL_CALIB_TX_IQ)            |
 722                         BIT(IWL_CALIB_BASE_BAND);
 723
 724                 break;
 725         default:
 726                 priv->hw_params.sens = &iwl5000_sensitivity;
 727                 priv->hw_params.calib_init_cfg =
 728                         BIT(IWL_CALIB_XTAL)             |
 729                         BIT(IWL_CALIB_LO)               |
 730                         BIT(IWL_CALIB_TX_IQ)            |
 731                         BIT(IWL_CALIB_TX_IQ_PERD)       |
 732                         BIT(IWL_CALIB_BASE_BAND);
 733                 break;
 734         }
 735
 736         return 0;
 737 }
 738
 739 /**
 740  * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
 741  */
 742 void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
 743                                             struct iwl_tx_queue *txq,
 744                                             u16 byte_cnt)
 745 {
 746         struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
 747         int write_ptr = txq->q.write_ptr;
 748         int txq_id = txq->q.id;
 749         u8 sec_ctl = 0;
 750         u8 sta_id = 0;
 751         u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
 752         __le16 bc_ent;
 753
 754         WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
 755
 756         if (txq_id != IWL_CMD_QUEUE_NUM) {
 757                 sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
 758                 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
 759
 760                 switch (sec_ctl & TX_CMD_SEC_MSK) {
 761                 case TX_CMD_SEC_CCM:
 762                         len += CCMP_MIC_LEN;
 763                         break;
 764                 case TX_CMD_SEC_TKIP:
 765                         len += TKIP_ICV_LEN;
 766                         break;
 767                 case TX_CMD_SEC_WEP:
 768                         len += WEP_IV_LEN + WEP_ICV_LEN;
 769                         break;
 770                 }
 771         }
 772
 773         bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
 774
 775         scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
 776
 777         if (write_ptr < TFD_QUEUE_SIZE_BC_DUP)
 778                 scd_bc_tbl[txq_id].
 779                         tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
 780 }
 781
 782 void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
 783                                            struct iwl_tx_queue *txq)
 784 {
 785         struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
 786         int txq_id = txq->q.id;
 787         int read_ptr = txq->q.read_ptr;
 788         u8 sta_id = 0;
 789         __le16 bc_ent;
 790
 791         WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
 792
 793         if (txq_id != IWL_CMD_QUEUE_NUM)
 794                 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
 795
 796         bc_ent = cpu_to_le16(1 | (sta_id << 12));
 797         scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
 798
 799         if (read_ptr < TFD_QUEUE_SIZE_BC_DUP)
 800                 scd_bc_tbl[txq_id].
 801                         tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] = bc_ent;
 802 }
 803
 804 static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
 805                                         u16 txq_id)
 806 {
 807         u32 tbl_dw_addr;
 808         u32 tbl_dw;
 809         u16 scd_q2ratid;
 810
 811         scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
 812
 813         tbl_dw_addr = priv->scd_base_addr +
 814                         IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
 815
 816         tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
 817
 818         if (txq_id & 0x1)
 819                 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
 820         else
 821                 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
 822
 823         iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
 824
 825         return 0;
 826 }
 827 static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
 828 {
 829         /* Simply stop the queue, but don't change any configuration;
 830          * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
 831         iwl_write_prph(priv,
 832                 IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
 833                 (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
 834                 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
 835 }
 836
 837 int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
 838                                   int tx_fifo, int sta_id, int tid, u16 ssn_idx)
 839 {
 840         unsigned long flags;
 841         u16 ra_tid;
 842
 843         if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
 844             (IWL50_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues
 845              <= txq_id)) {
 846                 IWL_WARN(priv,
 847                         "queue number out of range: %d, must be %d to %d\n",
 848                         txq_id, IWL50_FIRST_AMPDU_QUEUE,
 849                         IWL50_FIRST_AMPDU_QUEUE +
 850                         priv->cfg->num_of_ampdu_queues - 1);
 851                 return -EINVAL;
 852         }
 853
 854         ra_tid = BUILD_RAxTID(sta_id, tid);
 855
 856         /* Modify device's station table to Tx this TID */
 857         iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
 858
 859         spin_lock_irqsave(&priv->lock, flags);
 860
 861         /* Stop this Tx queue before configuring it */
 862         iwl5000_tx_queue_stop_scheduler(priv, txq_id);
 863
 864         /* Map receiver-address / traffic-ID to this queue */
 865         iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
 866
 867         /* Set this queue as a chain-building queue */
 868         iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id));
 869
 870         /* enable aggregations for the queue */
 871         iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id));
 872
 873         /* Place first TFD at index corresponding to start sequence number.
 874          * Assumes that ssn_idx is valid (!= 0xFFF) */
 875         priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
 876         priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
 877         iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
 878
 879         /* Set up Tx window size and frame limit for this queue */
 880         iwl_write_targ_mem(priv, priv->scd_base_addr +
 881                         IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
 882                         sizeof(u32),
 883                         ((SCD_WIN_SIZE <<
 884                         IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
 885                         IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
 886                         ((SCD_FRAME_LIMIT <<
 887                         IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
 888                         IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
 889
 890         iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
 891
 892         /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
 893         iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
 894
 895         spin_unlock_irqrestore(&priv->lock, flags);
 896
 897         return 0;
 898 }
 899
 900 int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
 901                                    u16 ssn_idx, u8 tx_fifo)
 902 {
 903         if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
 904             (IWL50_FIRST_AMPDU_QUEUE + priv->cfg->num_of_ampdu_queues
 905              <= txq_id)) {
 906                 IWL_ERR(priv,
 907                         "queue number out of range: %d, must be %d to %d\n",
 908                         txq_id, IWL50_FIRST_AMPDU_QUEUE,
 909                         IWL50_FIRST_AMPDU_QUEUE +
 910                         priv->cfg->num_of_ampdu_queues - 1);
 911                 return -EINVAL;
 912         }
 913
 914         iwl5000_tx_queue_stop_scheduler(priv, txq_id);
 915
 916         iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id));
 917
 918         priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
 919         priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
 920         /* supposes that ssn_idx is valid (!= 0xFFF) */
 921         iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
 922
 923         iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
 924         iwl_txq_ctx_deactivate(priv, txq_id);
 925         iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
 926
 927         return 0;
 928 }
 929
 930 u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
 931 {
 932         u16 size = (u16)sizeof(struct iwl_addsta_cmd);
 933         struct iwl_addsta_cmd *addsta = (struct iwl_addsta_cmd *)data;
 934         memcpy(addsta, cmd, size);
 935         /* resrved in 5000 */
 936         addsta->rate_n_flags = cpu_to_le16(0);
 937         return size;
 938 }
 939
 940
 941 /*
 942  * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
 943  * must be called under priv->lock and mac access
 944  */
 945 void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask)
 946 {
 947         iwl_write_prph(priv, IWL50_SCD_TXFACT, mask);
 948 }
 949
 950
 951 static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
 952 {
 953         return le32_to_cpup((__le32 *)&tx_resp->status +
 954                             tx_resp->frame_count) & MAX_SN;
 955 }
 956
 957 static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv,
 958                                       struct iwl_ht_agg *agg,
 959                                       struct iwl5000_tx_resp *tx_resp,
 960                                       int txq_id, u16 start_idx)
 961 {
 962         u16 status;
 963         struct agg_tx_status *frame_status = &tx_resp->status;
 964         struct ieee80211_tx_info *info = NULL;
 965         struct ieee80211_hdr *hdr = NULL;
 966         u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
 967         int i, sh, idx;
 968         u16 seq;
 969
 970         if (agg->wait_for_ba)
 971                 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
 972
 973         agg->frame_count = tx_resp->frame_count;
 974         agg->start_idx = start_idx;
 975         agg->rate_n_flags = rate_n_flags;
 976         agg->bitmap = 0;
 977
 978         /* # frames attempted by Tx command */
 979         if (agg->frame_count == 1) {
 980                 /* Only one frame was attempted; no block-ack will arrive */
 981                 status = le16_to_cpu(frame_status[0].status);
 982                 idx = start_idx;
 983
 984                 /* FIXME: code repetition */
 985                 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
 986                                    agg->frame_count, agg->start_idx, idx);
 987
 988                 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
 989                 info->status.rates[0].count = tx_resp->failure_frame + 1;
 990                 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
 991                 info->flags |= iwl_tx_status_to_mac80211(status);
 992                 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
 993
 994                 /* FIXME: code repetition end */
 995
 996                 IWL_DEBUG_TX_REPLY(priv, "1 Frame 0x%x failure :%d\n",
 997                                     status & 0xff, tx_resp->failure_frame);
 998                 IWL_DEBUG_TX_REPLY(priv, "Rate Info rate_n_flags=%x\n", rate_n_flags);
 999
1000                 agg->wait_for_ba = 0;
1001         } else {
1002                 /* Two or more frames were attempted; expect block-ack */
1003                 u64 bitmap = 0;
1004                 int start = agg->start_idx;
1005
1006                 /* Construct bit-map of pending frames within Tx window */
1007                 for (i = 0; i < agg->frame_count; i++) {
1008                         u16 sc;
1009                         status = le16_to_cpu(frame_status[i].status);
1010                         seq  = le16_to_cpu(frame_status[i].sequence);
1011                         idx = SEQ_TO_INDEX(seq);
1012                         txq_id = SEQ_TO_QUEUE(seq);
1013
1014                         if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
1015                                       AGG_TX_STATE_ABORT_MSK))
1016                                 continue;
1017
1018                         IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
1019                                            agg->frame_count, txq_id, idx);
1020
1021                         hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
1022                         if (!hdr) {
1023                                 IWL_ERR(priv,
1024                                         "BUG_ON idx doesn't point to valid skb"
1025                                         " idx=%d, txq_id=%d\n", idx, txq_id);
1026                                 return -1;
1027                         }
1028
1029                         sc = le16_to_cpu(hdr->seq_ctrl);
1030                         if (idx != (SEQ_TO_SN(sc) & 0xff)) {
1031                                 IWL_ERR(priv,
1032                                         "BUG_ON idx doesn't match seq control"
1033                                         " idx=%d, seq_idx=%d, seq=%d\n",
1034                                           idx, SEQ_TO_SN(sc),
1035                                           hdr->seq_ctrl);
1036                                 return -1;
1037                         }
1038
1039                         IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
1040                                            i, idx, SEQ_TO_SN(sc));
1041
1042                         sh = idx - start;
1043                         if (sh > 64) {
1044                                 sh = (start - idx) + 0xff;
1045                                 bitmap = bitmap << sh;
1046                                 sh = 0;
1047                                 start = idx;
1048                         } else if (sh < -64)
1049                                 sh  = 0xff - (start - idx);
1050                         else if (sh < 0) {
1051                                 sh = start - idx;
1052                                 start = idx;
1053                                 bitmap = bitmap << sh;
1054                                 sh = 0;
1055                         }
1056                         bitmap |= 1ULL << sh;
1057                         IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
1058                                            start, (unsigned long long)bitmap);
1059                 }
1060
1061                 agg->bitmap = bitmap;
1062                 agg->start_idx = start;
1063                 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
1064                                    agg->frame_count, agg->start_idx,
1065                                    (unsigned long long)agg->bitmap);
1066
1067                 if (bitmap)
1068                         agg->wait_for_ba = 1;
1069         }
1070         return 0;
1071 }
1072
1073 static void iwl5000_rx_reply_tx(struct iwl_priv *priv,
1074                                 struct iwl_rx_mem_buffer *rxb)
1075 {
1076         struct iwl_rx_packet *pkt = rxb_addr(rxb);
1077         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1078         int txq_id = SEQ_TO_QUEUE(sequence);
1079         int index = SEQ_TO_INDEX(sequence);
1080         struct iwl_tx_queue *txq = &priv->txq[txq_id];
1081         struct ieee80211_tx_info *info;
1082         struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
1083         u32  status = le16_to_cpu(tx_resp->status.status);
1084         int tid;
1085         int sta_id;
1086         int freed;
1087
1088         if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
1089                 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
1090                           "is out of range [0-%d] %d %d\n", txq_id,
1091                           index, txq->q.n_bd, txq->q.write_ptr,
1092                           txq->q.read_ptr);
1093                 return;
1094         }
1095
1096         info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
1097         memset(&info->status, 0, sizeof(info->status));
1098
1099         tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS;
1100         sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS;
1101
1102         if (txq->sched_retry) {
1103                 const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp);
1104                 struct iwl_ht_agg *agg = NULL;
1105
1106                 agg = &priv->stations[sta_id].tid[tid].agg;
1107
1108                 iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
1109
1110                 /* check if BAR is needed */
1111                 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
1112                         info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1113
1114                 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
1115                         index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
1116                         IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
1117                                         "scd_ssn=%d idx=%d txq=%d swq=%d\n",
1118                                         scd_ssn , index, txq_id, txq->swq_id);
1119
1120                         freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1121                         priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1122
1123                         if (priv->mac80211_registered &&
1124                             (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1125                             (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
1126                                 if (agg->state == IWL_AGG_OFF)
1127                                         iwl_wake_queue(priv, txq_id);
1128                                 else
1129                                         iwl_wake_queue(priv, txq->swq_id);
1130                         }
1131                 }
1132         } else {
1133                 BUG_ON(txq_id != txq->swq_id);
1134
1135                 info->status.rates[0].count = tx_resp->failure_frame + 1;
1136                 info->flags |= iwl_tx_status_to_mac80211(status);
1137                 iwl_hwrate_to_tx_control(priv,
1138                                         le32_to_cpu(tx_resp->rate_n_flags),
1139                                         info);
1140
1141                 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
1142                                    "0x%x retries %d\n",
1143                                    txq_id,
1144                                    iwl_get_tx_fail_reason(status), status,
1145                                    le32_to_cpu(tx_resp->rate_n_flags),
1146                                    tx_resp->failure_frame);
1147
1148                 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1149                 if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1150                         priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1151
1152                 if (priv->mac80211_registered &&
1153                     (iwl_queue_space(&txq->q) > txq->q.low_mark))
1154                         iwl_wake_queue(priv, txq_id);
1155         }
1156
1157         if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1158                 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
1159
1160         if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
1161                 IWL_ERR(priv, "TODO:  Implement Tx ABORT REQUIRED!!!\n");
1162 }
1163
1164 /* Currently 5000 is the superset of everything */
1165 u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len)
1166 {
1167         return len;
1168 }
1169
1170 void iwl5000_setup_deferred_work(struct iwl_priv *priv)
1171 {
1172         /* in 5000 the tx power calibration is done in uCode */
1173         priv->disable_tx_power_cal = 1;
1174 }
1175
1176 void iwl5000_rx_handler_setup(struct iwl_priv *priv)
1177 {
1178         /* init calibration handlers */
1179         priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
1180                                         iwl5000_rx_calib_result;
1181         priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
1182                                         iwl5000_rx_calib_complete;
1183         priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx;
1184 }
1185
1186
1187 int iwl5000_hw_valid_rtc_data_addr(u32 addr)
1188 {
1189         return (addr >= IWL50_RTC_DATA_LOWER_BOUND) &&
1190                 (addr < IWL50_RTC_DATA_UPPER_BOUND);
1191 }
1192
1193 static int iwl5000_send_rxon_assoc(struct iwl_priv *priv)
1194 {
1195         int ret = 0;
1196         struct iwl5000_rxon_assoc_cmd rxon_assoc;
1197         const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1198         const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1199
1200         if ((rxon1->flags == rxon2->flags) &&
1201             (rxon1->filter_flags == rxon2->filter_flags) &&
1202             (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1203             (rxon1->ofdm_ht_single_stream_basic_rates ==
1204              rxon2->ofdm_ht_single_stream_basic_rates) &&
1205             (rxon1->ofdm_ht_dual_stream_basic_rates ==
1206              rxon2->ofdm_ht_dual_stream_basic_rates) &&
1207             (rxon1->ofdm_ht_triple_stream_basic_rates ==
1208              rxon2->ofdm_ht_triple_stream_basic_rates) &&
1209             (rxon1->acquisition_data == rxon2->acquisition_data) &&
1210             (rxon1->rx_chain == rxon2->rx_chain) &&
1211             (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1212                 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC.  Not resending.\n");
1213                 return 0;
1214         }
1215
1216         rxon_assoc.flags = priv->staging_rxon.flags;
1217         rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1218         rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1219         rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1220         rxon_assoc.reserved1 = 0;
1221         rxon_assoc.reserved2 = 0;
1222         rxon_assoc.reserved3 = 0;
1223         rxon_assoc.ofdm_ht_single_stream_basic_rates =
1224             priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1225         rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1226             priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1227         rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1228         rxon_assoc.ofdm_ht_triple_stream_basic_rates =
1229                  priv->staging_rxon.ofdm_ht_triple_stream_basic_rates;
1230         rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data;
1231
1232         ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1233                                      sizeof(rxon_assoc), &rxon_assoc, NULL);
1234         if (ret)
1235                 return ret;
1236
1237         return ret;
1238 }
1239 int  iwl5000_send_tx_power(struct iwl_priv *priv)
1240 {
1241         struct iwl5000_tx_power_dbm_cmd tx_power_cmd;
1242         u8 tx_ant_cfg_cmd;
1243
1244         /* half dBm need to multiply */
1245         tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
1246
1247         if (priv->tx_power_lmt_in_half_dbm &&
1248             priv->tx_power_lmt_in_half_dbm < tx_power_cmd.global_lmt) {
1249                 /*
1250                  * For the newer devices which using enhanced/extend tx power
1251                  * table in EEPROM, the format is in half dBm. driver need to
1252                  * convert to dBm format before report to mac80211.
1253                  * By doing so, there is a possibility of 1/2 dBm resolution
1254                  * lost. driver will perform "round-up" operation before
1255                  * reporting, but it will cause 1/2 dBm tx power over the
1256                  * regulatory limit. Perform the checking here, if the
1257                  * "tx_power_user_lmt" is higher than EEPROM value (in
1258                  * half-dBm format), lower the tx power based on EEPROM
1259                  */
1260                 tx_power_cmd.global_lmt = priv->tx_power_lmt_in_half_dbm;
1261         }
1262         tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED;
1263         tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO;
1264
1265         if (IWL_UCODE_API(priv->ucode_ver) == 1)
1266                 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1;
1267         else
1268                 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
1269
1270         return  iwl_send_cmd_pdu_async(priv, tx_ant_cfg_cmd,
1271                                        sizeof(tx_power_cmd), &tx_power_cmd,
1272                                        NULL);
1273 }
1274
1275 void iwl5000_temperature(struct iwl_priv *priv)
1276 {
1277         /* store temperature from statistics (in Celsius) */
1278         priv->temperature = le32_to_cpu(priv->statistics.general.temperature);
1279         iwl_tt_handler(priv);
1280 }
1281
1282 static void iwl5150_temperature(struct iwl_priv *priv)
1283 {
1284         u32 vt = 0;
1285         s32 offset =  iwl_temp_calib_to_offset(priv);
1286
1287         vt = le32_to_cpu(priv->statistics.general.temperature);
1288         vt = vt / IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF + offset;
1289         /* now vt hold the temperature in Kelvin */
1290         priv->temperature = KELVIN_TO_CELSIUS(vt);
1291         iwl_tt_handler(priv);
1292 }
1293
1294 /* Calc max signal level (dBm) among 3 possible receivers */
1295 int iwl5000_calc_rssi(struct iwl_priv *priv,
1296                              struct iwl_rx_phy_res *rx_resp)
1297 {
1298         /* data from PHY/DSP regarding signal strength, etc.,
1299          *   contents are always there, not configurable by host
1300          */
1301         struct iwl5000_non_cfg_phy *ncphy =
1302                 (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
1303         u32 val, rssi_a, rssi_b, rssi_c, max_rssi;
1304         u8 agc;
1305
1306         val  = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]);
1307         agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS;
1308
1309         /* Find max rssi among 3 possible receivers.
1310          * These values are measured by the digital signal processor (DSP).
1311          * They should stay fairly constant even as the signal strength varies,
1312          *   if the radio's automatic gain control (AGC) is working right.
1313          * AGC value (see below) will provide the "interesting" info.
1314          */
1315         val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]);
1316         rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS;
1317         rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS;
1318         val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]);
1319         rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS;
1320
1321         max_rssi = max_t(u32, rssi_a, rssi_b);
1322         max_rssi = max_t(u32, max_rssi, rssi_c);
1323
1324         IWL_DEBUG_STATS(priv, "Rssi In A %d B %d C %d Max %d AGC dB %d\n",
1325                 rssi_a, rssi_b, rssi_c, max_rssi, agc);
1326
1327         /* dBm = max_rssi dB - agc dB - constant.
1328          * Higher AGC (higher radio gain) means lower signal. */
1329         return max_rssi - agc - IWL49_RSSI_OFFSET;
1330 }
1331
1332 static int iwl5000_send_tx_ant_config(struct iwl_priv *priv, u8 valid_tx_ant)
1333 {
1334         struct iwl_tx_ant_config_cmd tx_ant_cmd = {
1335           .valid = cpu_to_le32(valid_tx_ant),
1336         };
1337
1338         if (IWL_UCODE_API(priv->ucode_ver) > 1) {
1339                 IWL_DEBUG_HC(priv, "select valid tx ant: %u\n", valid_tx_ant);
1340                 return iwl_send_cmd_pdu(priv, TX_ANT_CONFIGURATION_CMD,
1341                                         sizeof(struct iwl_tx_ant_config_cmd),
1342                                         &tx_ant_cmd);
1343         } else {
1344                 IWL_DEBUG_HC(priv, "TX_ANT_CONFIGURATION_CMD not supported\n");
1345                 return -EOPNOTSUPP;
1346         }
1347 }
1348
1349
1350 #define IWL5000_UCODE_GET(item)                                         \
1351 static u32 iwl5000_ucode_get_##item(const struct iwl_ucode_header *ucode,\
1352                                     u32 api_ver)                        \
1353 {                                                                       \
1354         if (api_ver <= 2)                                               \
1355                 return le32_to_cpu(ucode->u.v1.item);                   \
1356         return le32_to_cpu(ucode->u.v2.item);                           \
1357 }
1358
1359 static u32 iwl5000_ucode_get_header_size(u32 api_ver)
1360 {
1361         if (api_ver <= 2)
1362                 return UCODE_HEADER_SIZE(1);
1363         return UCODE_HEADER_SIZE(2);
1364 }
1365
1366 static u32 iwl5000_ucode_get_build(const struct iwl_ucode_header *ucode,
1367                                    u32 api_ver)
1368 {
1369         if (api_ver <= 2)
1370                 return 0;
1371         return le32_to_cpu(ucode->u.v2.build);
1372 }
1373
1374 static u8 *iwl5000_ucode_get_data(const struct iwl_ucode_header *ucode,
1375                                   u32 api_ver)
1376 {
1377         if (api_ver <= 2)
1378                 return (u8 *) ucode->u.v1.data;
1379         return (u8 *) ucode->u.v2.data;
1380 }
1381
1382 IWL5000_UCODE_GET(inst_size);
1383 IWL5000_UCODE_GET(data_size);
1384 IWL5000_UCODE_GET(init_size);
1385 IWL5000_UCODE_GET(init_data_size);
1386 IWL5000_UCODE_GET(boot_size);
1387
1388 static int iwl5000_hw_channel_switch(struct iwl_priv *priv, u16 channel)
1389 {
1390         struct iwl5000_channel_switch_cmd cmd;
1391         const struct iwl_channel_info *ch_info;
1392         struct iwl_host_cmd hcmd = {
1393                 .id = REPLY_CHANNEL_SWITCH,
1394                 .len = sizeof(cmd),
1395                 .flags = CMD_SIZE_HUGE,
1396                 .data = &cmd,
1397         };
1398
1399         IWL_DEBUG_11H(priv, "channel switch from %d to %d\n",
1400                 priv->active_rxon.channel, channel);
1401         cmd.band = priv->band == IEEE80211_BAND_2GHZ;
1402         cmd.channel = cpu_to_le16(channel);
1403         cmd.rxon_flags = priv->staging_rxon.flags;
1404         cmd.rxon_filter_flags = priv->staging_rxon.filter_flags;
1405         cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
1406         ch_info = iwl_get_channel_info(priv, priv->band, channel);
1407         if (ch_info)
1408                 cmd.expect_beacon = is_channel_radar(ch_info);
1409         else {
1410                 IWL_ERR(priv, "invalid channel switch from %u to %u\n",
1411                         priv->active_rxon.channel, channel);
1412                 return -EFAULT;
1413         }
1414         priv->switch_rxon.channel = cpu_to_le16(channel);
1415         priv->switch_rxon.switch_in_progress = true;
1416
1417         return iwl_send_cmd_sync(priv, &hcmd);
1418 }
1419
1420 struct iwl_hcmd_ops iwl5000_hcmd = {
1421         .rxon_assoc = iwl5000_send_rxon_assoc,
1422         .commit_rxon = iwl_commit_rxon,
1423         .set_rxon_chain = iwl_set_rxon_chain,
1424         .set_tx_ant = iwl5000_send_tx_ant_config,
1425 };
1426
1427 struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
1428         .get_hcmd_size = iwl5000_get_hcmd_size,
1429         .build_addsta_hcmd = iwl5000_build_addsta_hcmd,
1430         .gain_computation = iwl5000_gain_computation,
1431         .chain_noise_reset = iwl5000_chain_noise_reset,
1432         .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag,
1433         .calc_rssi = iwl5000_calc_rssi,
1434 };
1435
1436 struct iwl_ucode_ops iwl5000_ucode = {
1437         .get_header_size = iwl5000_ucode_get_header_size,
1438         .get_build = iwl5000_ucode_get_build,
1439         .get_inst_size = iwl5000_ucode_get_inst_size,
1440         .get_data_size = iwl5000_ucode_get_data_size,
1441         .get_init_size = iwl5000_ucode_get_init_size,
1442         .get_init_data_size = iwl5000_ucode_get_init_data_size,
1443         .get_boot_size = iwl5000_ucode_get_boot_size,
1444         .get_data = iwl5000_ucode_get_data,
1445 };
1446
1447 struct iwl_lib_ops iwl5000_lib = {
1448         .set_hw_params = iwl5000_hw_set_hw_params,
1449         .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1450         .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1451         .txq_set_sched = iwl5000_txq_set_sched,
1452         .txq_agg_enable = iwl5000_txq_agg_enable,
1453         .txq_agg_disable = iwl5000_txq_agg_disable,
1454         .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
1455         .txq_free_tfd = iwl_hw_txq_free_tfd,
1456         .txq_init = iwl_hw_tx_queue_init,
1457         .rx_handler_setup = iwl5000_rx_handler_setup,
1458         .setup_deferred_work = iwl5000_setup_deferred_work,
1459         .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
1460         .dump_nic_event_log = iwl_dump_nic_event_log,
1461         .dump_nic_error_log = iwl_dump_nic_error_log,
1462         .dump_csr = iwl_dump_csr,
1463         .dump_fh = iwl_dump_fh,
1464         .load_ucode = iwl5000_load_ucode,
1465         .init_alive_start = iwl5000_init_alive_start,
1466         .alive_notify = iwl5000_alive_notify,
1467         .send_tx_power = iwl5000_send_tx_power,
1468         .update_chain_flags = iwl_update_chain_flags,
1469         .set_channel_switch = iwl5000_hw_channel_switch,
1470         .apm_ops = {
1471                 .init = iwl_apm_init,
1472                 .stop = iwl_apm_stop,
1473                 .config = iwl5000_nic_config,
1474                 .set_pwr_src = iwl_set_pwr_src,
1475         },
1476         .eeprom_ops = {
1477                 .regulatory_bands = {
1478                         EEPROM_5000_REG_BAND_1_CHANNELS,
1479                         EEPROM_5000_REG_BAND_2_CHANNELS,
1480                         EEPROM_5000_REG_BAND_3_CHANNELS,
1481                         EEPROM_5000_REG_BAND_4_CHANNELS,
1482                         EEPROM_5000_REG_BAND_5_CHANNELS,
1483                         EEPROM_5000_REG_BAND_24_HT40_CHANNELS,
1484                         EEPROM_5000_REG_BAND_52_HT40_CHANNELS
1485                 },
1486                 .verify_signature  = iwlcore_eeprom_verify_signature,
1487                 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1488                 .release_semaphore = iwlcore_eeprom_release_semaphore,
1489                 .calib_version  = iwl5000_eeprom_calib_version,
1490                 .query_addr = iwl5000_eeprom_query_addr,
1491         },
1492         .post_associate = iwl_post_associate,
1493         .isr = iwl_isr_ict,
1494         .config_ap = iwl_config_ap,
1495         .temp_ops = {
1496                 .temperature = iwl5000_temperature,
1497                 .set_ct_kill = iwl5000_set_ct_threshold,
1498          },
1499         .add_bcast_station = iwl_add_bcast_station,
1500 };
1501
1502 static struct iwl_lib_ops iwl5150_lib = {
1503         .set_hw_params = iwl5000_hw_set_hw_params,
1504         .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1505         .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1506         .txq_set_sched = iwl5000_txq_set_sched,
1507         .txq_agg_enable = iwl5000_txq_agg_enable,
1508         .txq_agg_disable = iwl5000_txq_agg_disable,
1509         .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
1510         .txq_free_tfd = iwl_hw_txq_free_tfd,
1511         .txq_init = iwl_hw_tx_queue_init,
1512         .rx_handler_setup = iwl5000_rx_handler_setup,
1513         .setup_deferred_work = iwl5000_setup_deferred_work,
1514         .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
1515         .dump_nic_event_log = iwl_dump_nic_event_log,
1516         .dump_nic_error_log = iwl_dump_nic_error_log,
1517         .dump_csr = iwl_dump_csr,
1518         .load_ucode = iwl5000_load_ucode,
1519         .init_alive_start = iwl5000_init_alive_start,
1520         .alive_notify = iwl5000_alive_notify,
1521         .send_tx_power = iwl5000_send_tx_power,
1522         .update_chain_flags = iwl_update_chain_flags,
1523         .set_channel_switch = iwl5000_hw_channel_switch,
1524         .apm_ops = {
1525                 .init = iwl_apm_init,
1526                 .stop = iwl_apm_stop,
1527                 .config = iwl5000_nic_config,
1528                 .set_pwr_src = iwl_set_pwr_src,
1529         },
1530         .eeprom_ops = {
1531                 .regulatory_bands = {
1532                         EEPROM_5000_REG_BAND_1_CHANNELS,
1533                         EEPROM_5000_REG_BAND_2_CHANNELS,
1534                         EEPROM_5000_REG_BAND_3_CHANNELS,
1535                         EEPROM_5000_REG_BAND_4_CHANNELS,
1536                         EEPROM_5000_REG_BAND_5_CHANNELS,
1537                         EEPROM_5000_REG_BAND_24_HT40_CHANNELS,
1538                         EEPROM_5000_REG_BAND_52_HT40_CHANNELS
1539                 },
1540                 .verify_signature  = iwlcore_eeprom_verify_signature,
1541                 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1542                 .release_semaphore = iwlcore_eeprom_release_semaphore,
1543                 .calib_version  = iwl5000_eeprom_calib_version,
1544                 .query_addr = iwl5000_eeprom_query_addr,
1545         },
1546         .post_associate = iwl_post_associate,
1547         .isr = iwl_isr_ict,
1548         .config_ap = iwl_config_ap,
1549         .temp_ops = {
1550                 .temperature = iwl5150_temperature,
1551                 .set_ct_kill = iwl5150_set_ct_threshold,
1552          },
1553         .add_bcast_station = iwl_add_bcast_station,
1554 };
1555
1556 static const struct iwl_ops iwl5000_ops = {
1557         .ucode = &iwl5000_ucode,
1558         .lib = &iwl5000_lib,
1559         .hcmd = &iwl5000_hcmd,
1560         .utils = &iwl5000_hcmd_utils,
1561         .led = &iwlagn_led_ops,
1562 };
1563
1564 static const struct iwl_ops iwl5150_ops = {
1565         .ucode = &iwl5000_ucode,
1566         .lib = &iwl5150_lib,
1567         .hcmd = &iwl5000_hcmd,
1568         .utils = &iwl5000_hcmd_utils,
1569         .led = &iwlagn_led_ops,
1570 };
1571
1572 struct iwl_mod_params iwl50_mod_params = {
1573         .amsdu_size_8K = 1,
1574         .restart_fw = 1,
1575         /* the rest are 0 by default */
1576 };
1577
1578
1579 struct iwl_cfg iwl5300_agn_cfg = {
1580         .name = "5300AGN",
1581         .fw_name_pre = IWL5000_FW_PRE,
1582         .ucode_api_max = IWL5000_UCODE_API_MAX,
1583         .ucode_api_min = IWL5000_UCODE_API_MIN,
1584         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1585         .ops = &iwl5000_ops,
1586         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1587         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1588         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1589         .num_of_queues = IWL50_NUM_QUEUES,
1590         .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1591         .mod_params = &iwl50_mod_params,
1592         .valid_tx_ant = ANT_ABC,
1593         .valid_rx_ant = ANT_ABC,
1594         .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1595         .set_l0s = true,
1596         .use_bsm = false,
1597         .ht_greenfield_support = true,
1598         .led_compensation = 51,
1599         .use_rts_for_ht = true, /* use rts/cts protection */
1600         .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1601         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
1602         .chain_noise_scale = 1000,
1603 };
1604
1605 struct iwl_cfg iwl5100_bgn_cfg = {
1606         .name = "5100BGN",
1607         .fw_name_pre = IWL5000_FW_PRE,
1608         .ucode_api_max = IWL5000_UCODE_API_MAX,
1609         .ucode_api_min = IWL5000_UCODE_API_MIN,
1610         .sku = IWL_SKU_G|IWL_SKU_N,
1611         .ops = &iwl5000_ops,
1612         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1613         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1614         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1615         .num_of_queues = IWL50_NUM_QUEUES,
1616         .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1617         .mod_params = &iwl50_mod_params,
1618         .valid_tx_ant = ANT_B,
1619         .valid_rx_ant = ANT_AB,
1620         .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1621         .set_l0s = true,
1622         .use_bsm = false,
1623         .ht_greenfield_support = true,
1624         .led_compensation = 51,
1625         .use_rts_for_ht = true, /* use rts/cts protection */
1626         .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1627         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
1628         .chain_noise_scale = 1000,
1629 };
1630
1631 struct iwl_cfg iwl5100_abg_cfg = {
1632         .name = "5100ABG",
1633         .fw_name_pre = IWL5000_FW_PRE,
1634         .ucode_api_max = IWL5000_UCODE_API_MAX,
1635         .ucode_api_min = IWL5000_UCODE_API_MIN,
1636         .sku = IWL_SKU_A|IWL_SKU_G,
1637         .ops = &iwl5000_ops,
1638         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1639         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1640         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1641         .num_of_queues = IWL50_NUM_QUEUES,
1642         .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1643         .mod_params = &iwl50_mod_params,
1644         .valid_tx_ant = ANT_B,
1645         .valid_rx_ant = ANT_AB,
1646         .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1647         .set_l0s = true,
1648         .use_bsm = false,
1649         .led_compensation = 51,
1650         .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1651         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
1652         .chain_noise_scale = 1000,
1653 };
1654
1655 struct iwl_cfg iwl5100_agn_cfg = {
1656         .name = "5100AGN",
1657         .fw_name_pre = IWL5000_FW_PRE,
1658         .ucode_api_max = IWL5000_UCODE_API_MAX,
1659         .ucode_api_min = IWL5000_UCODE_API_MIN,
1660         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1661         .ops = &iwl5000_ops,
1662         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1663         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1664         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1665         .num_of_queues = IWL50_NUM_QUEUES,
1666         .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1667         .mod_params = &iwl50_mod_params,
1668         .valid_tx_ant = ANT_B,
1669         .valid_rx_ant = ANT_AB,
1670         .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1671         .set_l0s = true,
1672         .use_bsm = false,
1673         .ht_greenfield_support = true,
1674         .led_compensation = 51,
1675         .use_rts_for_ht = true, /* use rts/cts protection */
1676         .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1677         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
1678         .chain_noise_scale = 1000,
1679 };
1680
1681 struct iwl_cfg iwl5350_agn_cfg = {
1682         .name = "5350AGN",
1683         .fw_name_pre = IWL5000_FW_PRE,
1684         .ucode_api_max = IWL5000_UCODE_API_MAX,
1685         .ucode_api_min = IWL5000_UCODE_API_MIN,
1686         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1687         .ops = &iwl5000_ops,
1688         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1689         .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1690         .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1691         .num_of_queues = IWL50_NUM_QUEUES,
1692         .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1693         .mod_params = &iwl50_mod_params,
1694         .valid_tx_ant = ANT_ABC,
1695         .valid_rx_ant = ANT_ABC,
1696         .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1697         .set_l0s = true,
1698         .use_bsm = false,
1699         .ht_greenfield_support = true,
1700         .led_compensation = 51,
1701         .use_rts_for_ht = true, /* use rts/cts protection */
1702         .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1703         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
1704         .chain_noise_scale = 1000,
1705 };
1706
1707 struct iwl_cfg iwl5150_agn_cfg = {
1708         .name = "5150AGN",
1709         .fw_name_pre = IWL5150_FW_PRE,
1710         .ucode_api_max = IWL5150_UCODE_API_MAX,
1711         .ucode_api_min = IWL5150_UCODE_API_MIN,
1712         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1713         .ops = &iwl5150_ops,
1714         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1715         .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1716         .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1717         .num_of_queues = IWL50_NUM_QUEUES,
1718         .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1719         .mod_params = &iwl50_mod_params,
1720         .valid_tx_ant = ANT_A,
1721         .valid_rx_ant = ANT_AB,
1722         .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1723         .set_l0s = true,
1724         .use_bsm = false,
1725         .ht_greenfield_support = true,
1726         .led_compensation = 51,
1727         .use_rts_for_ht = true, /* use rts/cts protection */
1728         .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1729         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
1730         .chain_noise_scale = 1000,
1731 };
1732
1733 struct iwl_cfg iwl5150_abg_cfg = {
1734         .name = "5150ABG",
1735         .fw_name_pre = IWL5150_FW_PRE,
1736         .ucode_api_max = IWL5150_UCODE_API_MAX,
1737         .ucode_api_min = IWL5150_UCODE_API_MIN,
1738         .sku = IWL_SKU_A|IWL_SKU_G,
1739         .ops = &iwl5150_ops,
1740         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1741         .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1742         .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1743         .num_of_queues = IWL50_NUM_QUEUES,
1744         .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1745         .mod_params = &iwl50_mod_params,
1746         .valid_tx_ant = ANT_A,
1747         .valid_rx_ant = ANT_AB,
1748         .pll_cfg_val = CSR50_ANA_PLL_CFG_VAL,
1749         .set_l0s = true,
1750         .use_bsm = false,
1751         .led_compensation = 51,
1752         .chain_noise_num_beacons = IWL_CAL_NUM_BEACONS,
1753         .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF,
1754         .chain_noise_scale = 1000,
1755 };
1756
1757 MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE(IWL5000_UCODE_API_MAX));
1758 MODULE_FIRMWARE(IWL5150_MODULE_FIRMWARE(IWL5150_UCODE_API_MAX));
1759
1760 module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, S_IRUGO);
1761 MODULE_PARM_DESC(swcrypto50,
1762                   "using software crypto engine (default 0 [hardware])\n");
1763 module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, S_IRUGO);
1764 MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
1765 module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, S_IRUGO);
1766 MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality");
1767 module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K,
1768                    int, S_IRUGO);
1769 MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
1770 module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, S_IRUGO);
1771 MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error");