SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/iwlwifi/iwl-4965.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * James P. Ketrenos <ipw2100-admin@linux.intel.com>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  *****************************************************************************/
  26
  27 #include <linux/kernel.h>
  28 #include <linux/module.h>
  29 #include <linux/version.h>
  30 #include <linux/init.h>
  31 #include <linux/pci.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/delay.h>
  34 #include <linux/skbuff.h>
  35 #include <linux/netdevice.h>
  36 #include <linux/wireless.h>
  37 #include <net/mac80211.h>
  38 #include <linux/etherdevice.h>
  39 #include <asm/unaligned.h>
  40
  41 #include "iwl-eeprom.h"
  42 #include "iwl-4965.h"
  43 #include "iwl-core.h"
  44 #include "iwl-io.h"
  45 #include "iwl-helpers.h"
  46 #include "iwl-calib.h"
  47
  48 /* module parameters */
  49 static struct iwl_mod_params iwl4965_mod_params = {
  50         .num_of_queues = IWL4965_MAX_NUM_QUEUES,
  51         .enable_qos = 1,
  52         .amsdu_size_8K = 1,
  53         /* the rest are 0 by default */
  54 };
  55
  56 static void iwl4965_hw_card_show_info(struct iwl_priv *priv);
  57
  58 #define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np)    \
  59         [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP,      \
  60                                     IWL_RATE_SISO_##s##M_PLCP, \
  61                                     IWL_RATE_MIMO_##s##M_PLCP, \
  62                                     IWL_RATE_##r##M_IEEE,      \
  63                                     IWL_RATE_##ip##M_INDEX,    \
  64                                     IWL_RATE_##in##M_INDEX,    \
  65                                     IWL_RATE_##rp##M_INDEX,    \
  66                                     IWL_RATE_##rn##M_INDEX,    \
  67                                     IWL_RATE_##pp##M_INDEX,    \
  68                                     IWL_RATE_##np##M_INDEX }
  69
  70 /*
  71  * Parameter order:
  72  *   rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
  73  *
  74  * If there isn't a valid next or previous rate then INV is used which
  75  * maps to IWL_RATE_INVALID
  76  *
  77  */
  78 const struct iwl4965_rate_info iwl4965_rates[IWL_RATE_COUNT] = {
  79         IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2),    /*  1mbps */
  80         IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5),          /*  2mbps */
  81         IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11),        /*5.5mbps */
  82         IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18),      /* 11mbps */
  83         IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11),        /*  6mbps */
  84         IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11),       /*  9mbps */
  85         IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18),   /* 12mbps */
  86         IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24),   /* 18mbps */
  87         IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36),   /* 24mbps */
  88         IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48),   /* 36mbps */
  89         IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54),   /* 48mbps */
  90         IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
  91         IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
  92 };
  93
  94 #ifdef CONFIG_IWL4965_HT
  95
  96 static const u16 default_tid_to_tx_fifo[] = {
  97         IWL_TX_FIFO_AC1,
  98         IWL_TX_FIFO_AC0,
  99         IWL_TX_FIFO_AC0,
 100         IWL_TX_FIFO_AC1,
 101         IWL_TX_FIFO_AC2,
 102         IWL_TX_FIFO_AC2,
 103         IWL_TX_FIFO_AC3,
 104         IWL_TX_FIFO_AC3,
 105         IWL_TX_FIFO_NONE,
 106         IWL_TX_FIFO_NONE,
 107         IWL_TX_FIFO_NONE,
 108         IWL_TX_FIFO_NONE,
 109         IWL_TX_FIFO_NONE,
 110         IWL_TX_FIFO_NONE,
 111         IWL_TX_FIFO_NONE,
 112         IWL_TX_FIFO_NONE,
 113         IWL_TX_FIFO_AC3
 114 };
 115
 116 #endif  /*CONFIG_IWL4965_HT */
 117
 118 /* check contents of special bootstrap uCode SRAM */
 119 static int iwl4965_verify_bsm(struct iwl_priv *priv)
 120 {
 121         __le32 *image = priv->ucode_boot.v_addr;
 122         u32 len = priv->ucode_boot.len;
 123         u32 reg;
 124         u32 val;
 125
 126         IWL_DEBUG_INFO("Begin verify bsm\n");
 127
 128         /* verify BSM SRAM contents */
 129         val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
 130         for (reg = BSM_SRAM_LOWER_BOUND;
 131              reg < BSM_SRAM_LOWER_BOUND + len;
 132              reg += sizeof(u32), image++) {
 133                 val = iwl_read_prph(priv, reg);
 134                 if (val != le32_to_cpu(*image)) {
 135                         IWL_ERROR("BSM uCode verification failed at "
 136                                   "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
 137                                   BSM_SRAM_LOWER_BOUND,
 138                                   reg - BSM_SRAM_LOWER_BOUND, len,
 139                                   val, le32_to_cpu(*image));
 140                         return -EIO;
 141                 }
 142         }
 143
 144         IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
 145
 146         return 0;
 147 }
 148
 149 /**
 150  * iwl4965_load_bsm - Load bootstrap instructions
 151  *
 152  * BSM operation:
 153  *
 154  * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
 155  * in special SRAM that does not power down during RFKILL.  When powering back
 156  * up after power-saving sleeps (or during initial uCode load), the BSM loads
 157  * the bootstrap program into the on-board processor, and starts it.
 158  *
 159  * The bootstrap program loads (via DMA) instructions and data for a new
 160  * program from host DRAM locations indicated by the host driver in the
 161  * BSM_DRAM_* registers.  Once the new program is loaded, it starts
 162  * automatically.
 163  *
 164  * When initializing the NIC, the host driver points the BSM to the
 165  * "initialize" uCode image.  This uCode sets up some internal data, then
 166  * notifies host via "initialize alive" that it is complete.
 167  *
 168  * The host then replaces the BSM_DRAM_* pointer values to point to the
 169  * normal runtime uCode instructions and a backup uCode data cache buffer
 170  * (filled initially with starting data values for the on-board processor),
 171  * then triggers the "initialize" uCode to load and launch the runtime uCode,
 172  * which begins normal operation.
 173  *
 174  * When doing a power-save shutdown, runtime uCode saves data SRAM into
 175  * the backup data cache in DRAM before SRAM is powered down.
 176  *
 177  * When powering back up, the BSM loads the bootstrap program.  This reloads
 178  * the runtime uCode instructions and the backup data cache into SRAM,
 179  * and re-launches the runtime uCode from where it left off.
 180  */
 181 static int iwl4965_load_bsm(struct iwl_priv *priv)
 182 {
 183         __le32 *image = priv->ucode_boot.v_addr;
 184         u32 len = priv->ucode_boot.len;
 185         dma_addr_t pinst;
 186         dma_addr_t pdata;
 187         u32 inst_len;
 188         u32 data_len;
 189         int i;
 190         u32 done;
 191         u32 reg_offset;
 192         int ret;
 193
 194         IWL_DEBUG_INFO("Begin load bsm\n");
 195
 196         /* make sure bootstrap program is no larger than BSM's SRAM size */
 197         if (len > IWL_MAX_BSM_SIZE)
 198                 return -EINVAL;
 199
 200         /* Tell bootstrap uCode where to find the "Initialize" uCode
 201          *   in host DRAM ... host DRAM physical address bits 35:4 for 4965.
 202          * NOTE:  iwl4965_initialize_alive_start() will replace these values,
 203          *        after the "initialize" uCode has run, to point to
 204          *        runtime/protocol instructions and backup data cache. */
 205         pinst = priv->ucode_init.p_addr >> 4;
 206         pdata = priv->ucode_init_data.p_addr >> 4;
 207         inst_len = priv->ucode_init.len;
 208         data_len = priv->ucode_init_data.len;
 209
 210         ret = iwl_grab_nic_access(priv);
 211         if (ret)
 212                 return ret;
 213
 214         iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
 215         iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
 216         iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
 217         iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
 218
 219         /* Fill BSM memory with bootstrap instructions */
 220         for (reg_offset = BSM_SRAM_LOWER_BOUND;
 221              reg_offset < BSM_SRAM_LOWER_BOUND + len;
 222              reg_offset += sizeof(u32), image++)
 223                 _iwl_write_prph(priv, reg_offset, le32_to_cpu(*image));
 224
 225         ret = iwl4965_verify_bsm(priv);
 226         if (ret) {
 227                 iwl_release_nic_access(priv);
 228                 return ret;
 229         }
 230
 231         /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
 232         iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
 233         iwl_write_prph(priv, BSM_WR_MEM_DST_REG, RTC_INST_LOWER_BOUND);
 234         iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
 235
 236         /* Load bootstrap code into instruction SRAM now,
 237          *   to prepare to load "initialize" uCode */
 238         iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START);
 239
 240         /* Wait for load of bootstrap uCode to finish */
 241         for (i = 0; i < 100; i++) {
 242                 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
 243                 if (!(done & BSM_WR_CTRL_REG_BIT_START))
 244                         break;
 245                 udelay(10);
 246         }
 247         if (i < 100)
 248                 IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
 249         else {
 250                 IWL_ERROR("BSM write did not complete!\n");
 251                 return -EIO;
 252         }
 253
 254         /* Enable future boot loads whenever power management unit triggers it
 255          *   (e.g. when powering back up after power-save shutdown) */
 256         iwl_write_prph(priv, BSM_WR_CTRL_REG, BSM_WR_CTRL_REG_BIT_START_EN);
 257
 258         iwl_release_nic_access(priv);
 259
 260         return 0;
 261 }
 262
 263 static int iwl4965_init_drv(struct iwl_priv *priv)
 264 {
 265         int ret;
 266         int i;
 267
 268         priv->antenna = (enum iwl4965_antenna)priv->cfg->mod_params->antenna;
 269         priv->retry_rate = 1;
 270         priv->ibss_beacon = NULL;
 271
 272         spin_lock_init(&priv->lock);
 273         spin_lock_init(&priv->power_data.lock);
 274         spin_lock_init(&priv->sta_lock);
 275         spin_lock_init(&priv->hcmd_lock);
 276         spin_lock_init(&priv->lq_mngr.lock);
 277
 278         priv->shared_virt = pci_alloc_consistent(priv->pci_dev,
 279                                         sizeof(struct iwl4965_shared),
 280                                         &priv->shared_phys);
 281
 282         if (!priv->shared_virt) {
 283                 ret = -ENOMEM;
 284                 goto err;
 285         }
 286
 287         memset(priv->shared_virt, 0, sizeof(struct iwl4965_shared));
 288
 289
 290         for (i = 0; i < IWL_IBSS_MAC_HASH_SIZE; i++)
 291                 INIT_LIST_HEAD(&priv->ibss_mac_hash[i]);
 292
 293         INIT_LIST_HEAD(&priv->free_frames);
 294
 295         mutex_init(&priv->mutex);
 296
 297         /* Clear the driver's (not device's) station table */
 298         iwlcore_clear_stations_table(priv);
 299
 300         priv->data_retry_limit = -1;
 301         priv->ieee_channels = NULL;
 302         priv->ieee_rates = NULL;
 303         priv->band = IEEE80211_BAND_2GHZ;
 304
 305         priv->iw_mode = IEEE80211_IF_TYPE_STA;
 306
 307         priv->use_ant_b_for_management_frame = 1; /* start with ant B */
 308         priv->valid_antenna = 0x7;      /* assume all 3 connected */
 309         priv->ps_mode = IWL_MIMO_PS_NONE;
 310
 311         /* Choose which receivers/antennas to use */
 312         iwl4965_set_rxon_chain(priv);
 313
 314         iwlcore_reset_qos(priv);
 315
 316         priv->qos_data.qos_active = 0;
 317         priv->qos_data.qos_cap.val = 0;
 318
 319         iwlcore_set_rxon_channel(priv, IEEE80211_BAND_2GHZ, 6);
 320
 321         priv->rates_mask = IWL_RATES_MASK;
 322         /* If power management is turned on, default to AC mode */
 323         priv->power_mode = IWL_POWER_AC;
 324         priv->user_txpower_limit = IWL_DEFAULT_TX_POWER;
 325
 326         ret = iwl_init_channel_map(priv);
 327         if (ret) {
 328                 IWL_ERROR("initializing regulatory failed: %d\n", ret);
 329                 goto err;
 330         }
 331
 332         ret = iwl4965_init_geos(priv);
 333         if (ret) {
 334                 IWL_ERROR("initializing geos failed: %d\n", ret);
 335                 goto err_free_channel_map;
 336         }
 337
 338         ret = ieee80211_register_hw(priv->hw);
 339         if (ret) {
 340                 IWL_ERROR("Failed to register network device (error %d)\n",
 341                                 ret);
 342                 goto err_free_geos;
 343         }
 344
 345         priv->hw->conf.beacon_int = 100;
 346         priv->mac80211_registered = 1;
 347
 348         return 0;
 349
 350 err_free_geos:
 351         iwl4965_free_geos(priv);
 352 err_free_channel_map:
 353         iwl_free_channel_map(priv);
 354 err:
 355         return ret;
 356 }
 357
 358 static int is_fat_channel(__le32 rxon_flags)
 359 {
 360         return (rxon_flags & RXON_FLG_CHANNEL_MODE_PURE_40_MSK) ||
 361                 (rxon_flags & RXON_FLG_CHANNEL_MODE_MIXED_MSK);
 362 }
 363
 364 static u8 is_single_stream(struct iwl_priv *priv)
 365 {
 366 #ifdef CONFIG_IWL4965_HT
 367         if (!priv->current_ht_config.is_ht ||
 368             (priv->current_ht_config.supp_mcs_set[1] == 0) ||
 369             (priv->ps_mode == IWL_MIMO_PS_STATIC))
 370                 return 1;
 371 #else
 372         return 1;
 373 #endif  /*CONFIG_IWL4965_HT */
 374         return 0;
 375 }
 376
 377 int iwl4965_hwrate_to_plcp_idx(u32 rate_n_flags)
 378 {
 379         int idx = 0;
 380
 381         /* 4965 HT rate format */
 382         if (rate_n_flags & RATE_MCS_HT_MSK) {
 383                 idx = (rate_n_flags & 0xff);
 384
 385                 if (idx >= IWL_RATE_MIMO_6M_PLCP)
 386                         idx = idx - IWL_RATE_MIMO_6M_PLCP;
 387
 388                 idx += IWL_FIRST_OFDM_RATE;
 389                 /* skip 9M not supported in ht*/
 390                 if (idx >= IWL_RATE_9M_INDEX)
 391                         idx += 1;
 392                 if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
 393                         return idx;
 394
 395         /* 4965 legacy rate format, search for match in table */
 396         } else {
 397                 for (idx = 0; idx < ARRAY_SIZE(iwl4965_rates); idx++)
 398                         if (iwl4965_rates[idx].plcp == (rate_n_flags & 0xFF))
 399                                 return idx;
 400         }
 401
 402         return -1;
 403 }
 404
 405 /**
 406  * translate ucode response to mac80211 tx status control values
 407  */
 408 void iwl4965_hwrate_to_tx_control(struct iwl_priv *priv, u32 rate_n_flags,
 409                                   struct ieee80211_tx_control *control)
 410 {
 411         int rate_index;
 412
 413         control->antenna_sel_tx =
 414                 ((rate_n_flags & RATE_MCS_ANT_AB_MSK) >> RATE_MCS_ANT_POS);
 415         if (rate_n_flags & RATE_MCS_HT_MSK)
 416                 control->flags |= IEEE80211_TXCTL_OFDM_HT;
 417         if (rate_n_flags & RATE_MCS_GF_MSK)
 418                 control->flags |= IEEE80211_TXCTL_GREEN_FIELD;
 419         if (rate_n_flags & RATE_MCS_FAT_MSK)
 420                 control->flags |= IEEE80211_TXCTL_40_MHZ_WIDTH;
 421         if (rate_n_flags & RATE_MCS_DUP_MSK)
 422                 control->flags |= IEEE80211_TXCTL_DUP_DATA;
 423         if (rate_n_flags & RATE_MCS_SGI_MSK)
 424                 control->flags |= IEEE80211_TXCTL_SHORT_GI;
 425         /* since iwl4965_hwrate_to_plcp_idx is band indifferent, we always use
 426          * IEEE80211_BAND_2GHZ band as it contains all the rates */
 427         rate_index = iwl4965_hwrate_to_plcp_idx(rate_n_flags);
 428         if (rate_index == -1)
 429                 control->tx_rate = NULL;
 430         else
 431                 control->tx_rate =
 432                         &priv->bands[IEEE80211_BAND_2GHZ].bitrates[rate_index];
 433 }
 434
 435 /*
 436  * Determine how many receiver/antenna chains to use.
 437  * More provides better reception via diversity.  Fewer saves power.
 438  * MIMO (dual stream) requires at least 2, but works better with 3.
 439  * This does not determine *which* chains to use, just how many.
 440  */
 441 static int iwl4965_get_rx_chain_counter(struct iwl_priv *priv,
 442                                         u8 *idle_state, u8 *rx_state)
 443 {
 444         u8 is_single = is_single_stream(priv);
 445         u8 is_cam = test_bit(STATUS_POWER_PMI, &priv->status) ? 0 : 1;
 446
 447         /* # of Rx chains to use when expecting MIMO. */
 448         if (is_single || (!is_cam && (priv->ps_mode == IWL_MIMO_PS_STATIC)))
 449                 *rx_state = 2;
 450         else
 451                 *rx_state = 3;
 452
 453         /* # Rx chains when idling and maybe trying to save power */
 454         switch (priv->ps_mode) {
 455         case IWL_MIMO_PS_STATIC:
 456         case IWL_MIMO_PS_DYNAMIC:
 457                 *idle_state = (is_cam) ? 2 : 1;
 458                 break;
 459         case IWL_MIMO_PS_NONE:
 460                 *idle_state = (is_cam) ? *rx_state : 1;
 461                 break;
 462         default:
 463                 *idle_state = 1;
 464                 break;
 465         }
 466
 467         return 0;
 468 }
 469
 470 int iwl4965_hw_rxq_stop(struct iwl_priv *priv)
 471 {
 472         int rc;
 473         unsigned long flags;
 474
 475         spin_lock_irqsave(&priv->lock, flags);
 476         rc = iwl_grab_nic_access(priv);
 477         if (rc) {
 478                 spin_unlock_irqrestore(&priv->lock, flags);
 479                 return rc;
 480         }
 481
 482         /* stop Rx DMA */
 483         iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 484         rc = iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
 485                                      (1 << 24), 1000);
 486         if (rc < 0)
 487                 IWL_ERROR("Can't stop Rx DMA.\n");
 488
 489         iwl_release_nic_access(priv);
 490         spin_unlock_irqrestore(&priv->lock, flags);
 491
 492         return 0;
 493 }
 494
 495 u8 iwl4965_hw_find_station(struct iwl_priv *priv, const u8 *addr)
 496 {
 497         int i;
 498         int start = 0;
 499         int ret = IWL_INVALID_STATION;
 500         unsigned long flags;
 501         DECLARE_MAC_BUF(mac);
 502
 503         if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) ||
 504             (priv->iw_mode == IEEE80211_IF_TYPE_AP))
 505                 start = IWL_STA_ID;
 506
 507         if (is_broadcast_ether_addr(addr))
 508                 return priv->hw_params.bcast_sta_id;
 509
 510         spin_lock_irqsave(&priv->sta_lock, flags);
 511         for (i = start; i < priv->hw_params.max_stations; i++)
 512                 if ((priv->stations[i].used) &&
 513                     (!compare_ether_addr
 514                      (priv->stations[i].sta.sta.addr, addr))) {
 515                         ret = i;
 516                         goto out;
 517                 }
 518
 519         IWL_DEBUG_ASSOC_LIMIT("can not find STA %s total %d\n",
 520                         print_mac(mac, addr), priv->num_stations);
 521
 522  out:
 523         spin_unlock_irqrestore(&priv->sta_lock, flags);
 524         return ret;
 525 }
 526
 527 static int iwl4965_nic_set_pwr_src(struct iwl_priv *priv, int pwr_max)
 528 {
 529         int ret;
 530         unsigned long flags;
 531
 532         spin_lock_irqsave(&priv->lock, flags);
 533         ret = iwl_grab_nic_access(priv);
 534         if (ret) {
 535                 spin_unlock_irqrestore(&priv->lock, flags);
 536                 return ret;
 537         }
 538
 539         if (!pwr_max) {
 540                 u32 val;
 541
 542                 ret = pci_read_config_dword(priv->pci_dev, PCI_POWER_SOURCE,
 543                                            &val);
 544
 545                 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT)
 546                         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 547                                 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 548                                 ~APMG_PS_CTRL_MSK_PWR_SRC);
 549         } else
 550                 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 551                         APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 552                         ~APMG_PS_CTRL_MSK_PWR_SRC);
 553
 554         iwl_release_nic_access(priv);
 555         spin_unlock_irqrestore(&priv->lock, flags);
 556
 557         return ret;
 558 }
 559
 560 static int iwl4965_rx_init(struct iwl_priv *priv, struct iwl4965_rx_queue *rxq)
 561 {
 562         int ret;
 563         unsigned long flags;
 564         unsigned int rb_size;
 565
 566         spin_lock_irqsave(&priv->lock, flags);
 567         ret = iwl_grab_nic_access(priv);
 568         if (ret) {
 569                 spin_unlock_irqrestore(&priv->lock, flags);
 570                 return ret;
 571         }
 572
 573         if (priv->cfg->mod_params->amsdu_size_8K)
 574                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
 575         else
 576                 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
 577
 578         /* Stop Rx DMA */
 579         iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
 580
 581         /* Reset driver's Rx queue write index */
 582         iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
 583
 584         /* Tell device where to find RBD circular buffer in DRAM */
 585         iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
 586                            rxq->dma_addr >> 8);
 587
 588         /* Tell device where in DRAM to update its Rx status */
 589         iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
 590                            (priv->shared_phys +
 591                             offsetof(struct iwl4965_shared, rb_closed)) >> 4);
 592
 593         /* Enable Rx DMA, enable host interrupt, Rx buffer size 4k, 256 RBDs */
 594         iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
 595                            FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
 596                            FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
 597                            rb_size |
 598                              /* 0x10 << 4 | */
 599                            (RX_QUEUE_SIZE_LOG <<
 600                               FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT));
 601
 602         /*
 603          * iwl_write32(priv,CSR_INT_COAL_REG,0);
 604          */
 605
 606         iwl_release_nic_access(priv);
 607         spin_unlock_irqrestore(&priv->lock, flags);
 608
 609         return 0;
 610 }
 611
 612 /* Tell 4965 where to find the "keep warm" buffer */
 613 static int iwl4965_kw_init(struct iwl_priv *priv)
 614 {
 615         unsigned long flags;
 616         int rc;
 617
 618         spin_lock_irqsave(&priv->lock, flags);
 619         rc = iwl_grab_nic_access(priv);
 620         if (rc)
 621                 goto out;
 622
 623         iwl_write_direct32(priv, IWL_FH_KW_MEM_ADDR_REG,
 624                              priv->kw.dma_addr >> 4);
 625         iwl_release_nic_access(priv);
 626 out:
 627         spin_unlock_irqrestore(&priv->lock, flags);
 628         return rc;
 629 }
 630
 631 static int iwl4965_kw_alloc(struct iwl_priv *priv)
 632 {
 633         struct pci_dev *dev = priv->pci_dev;
 634         struct iwl4965_kw *kw = &priv->kw;
 635
 636         kw->size = IWL4965_KW_SIZE;     /* TBW need set somewhere else */
 637         kw->v_addr = pci_alloc_consistent(dev, kw->size, &kw->dma_addr);
 638         if (!kw->v_addr)
 639                 return -ENOMEM;
 640
 641         return 0;
 642 }
 643
 644 /**
 645  * iwl4965_kw_free - Free the "keep warm" buffer
 646  */
 647 static void iwl4965_kw_free(struct iwl_priv *priv)
 648 {
 649         struct pci_dev *dev = priv->pci_dev;
 650         struct iwl4965_kw *kw = &priv->kw;
 651
 652         if (kw->v_addr) {
 653                 pci_free_consistent(dev, kw->size, kw->v_addr, kw->dma_addr);
 654                 memset(kw, 0, sizeof(*kw));
 655         }
 656 }
 657
 658 /**
 659  * iwl4965_txq_ctx_reset - Reset TX queue context
 660  * Destroys all DMA structures and initialise them again
 661  *
 662  * @param priv
 663  * @return error code
 664  */
 665 static int iwl4965_txq_ctx_reset(struct iwl_priv *priv)
 666 {
 667         int rc = 0;
 668         int txq_id, slots_num;
 669         unsigned long flags;
 670
 671         iwl4965_kw_free(priv);
 672
 673         /* Free all tx/cmd queues and keep-warm buffer */
 674         iwl4965_hw_txq_ctx_free(priv);
 675
 676         /* Alloc keep-warm buffer */
 677         rc = iwl4965_kw_alloc(priv);
 678         if (rc) {
 679                 IWL_ERROR("Keep Warm allocation failed");
 680                 goto error_kw;
 681         }
 682
 683         spin_lock_irqsave(&priv->lock, flags);
 684
 685         rc = iwl_grab_nic_access(priv);
 686         if (unlikely(rc)) {
 687                 IWL_ERROR("TX reset failed");
 688                 spin_unlock_irqrestore(&priv->lock, flags);
 689                 goto error_reset;
 690         }
 691
 692         /* Turn off all Tx DMA channels */
 693         iwl_write_prph(priv, IWL49_SCD_TXFACT, 0);
 694         iwl_release_nic_access(priv);
 695         spin_unlock_irqrestore(&priv->lock, flags);
 696
 697         /* Tell 4965 where to find the keep-warm buffer */
 698         rc = iwl4965_kw_init(priv);
 699         if (rc) {
 700                 IWL_ERROR("kw_init failed\n");
 701                 goto error_reset;
 702         }
 703
 704         /* Alloc and init all (default 16) Tx queues,
 705          * including the command queue (#4) */
 706         for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
 707                 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
 708                                         TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 709                 rc = iwl4965_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
 710                                        txq_id);
 711                 if (rc) {
 712                         IWL_ERROR("Tx %d queue init failed\n", txq_id);
 713                         goto error;
 714                 }
 715         }
 716
 717         return rc;
 718
 719  error:
 720         iwl4965_hw_txq_ctx_free(priv);
 721  error_reset:
 722         iwl4965_kw_free(priv);
 723  error_kw:
 724         return rc;
 725 }
 726
 727 int iwl4965_hw_nic_init(struct iwl_priv *priv)
 728 {
 729         int rc;
 730         unsigned long flags;
 731         struct iwl4965_rx_queue *rxq = &priv->rxq;
 732         u8 rev_id;
 733         u32 val;
 734         u8 val_link;
 735
 736         iwl4965_power_init_handle(priv);
 737
 738         /* nic_init */
 739         spin_lock_irqsave(&priv->lock, flags);
 740
 741         iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
 742                     CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 743
 744         iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 745         rc = iwl_poll_bit(priv, CSR_GP_CNTRL,
 746                           CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 747                           CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 748         if (rc < 0) {
 749                 spin_unlock_irqrestore(&priv->lock, flags);
 750                 IWL_DEBUG_INFO("Failed to init the card\n");
 751                 return rc;
 752         }
 753
 754         rc = iwl_grab_nic_access(priv);
 755         if (rc) {
 756                 spin_unlock_irqrestore(&priv->lock, flags);
 757                 return rc;
 758         }
 759
 760         iwl_read_prph(priv, APMG_CLK_CTRL_REG);
 761
 762         iwl_write_prph(priv, APMG_CLK_CTRL_REG,
 763                         APMG_CLK_VAL_DMA_CLK_RQT | APMG_CLK_VAL_BSM_CLK_RQT);
 764         iwl_read_prph(priv, APMG_CLK_CTRL_REG);
 765
 766         udelay(20);
 767
 768         iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
 769                                 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 770
 771         iwl_release_nic_access(priv);
 772         iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
 773         spin_unlock_irqrestore(&priv->lock, flags);
 774
 775         /* Determine HW type */
 776         rc = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
 777         if (rc)
 778                 return rc;
 779
 780         IWL_DEBUG_INFO("HW Revision ID = 0x%X\n", rev_id);
 781
 782         iwl4965_nic_set_pwr_src(priv, 1);
 783         spin_lock_irqsave(&priv->lock, flags);
 784
 785         if ((rev_id & 0x80) == 0x80 && (rev_id & 0x7f) < 8) {
 786                 pci_read_config_dword(priv->pci_dev, PCI_REG_WUM8, &val);
 787                 /* Enable No Snoop field */
 788                 pci_write_config_dword(priv->pci_dev, PCI_REG_WUM8,
 789                                        val & ~(1 << 11));
 790         }
 791
 792         spin_unlock_irqrestore(&priv->lock, flags);
 793
 794         if (priv->eeprom.calib_version < EEPROM_TX_POWER_VERSION_NEW) {
 795                 IWL_ERROR("Older EEPROM detected!  Aborting.\n");
 796                 return -EINVAL;
 797         }
 798
 799         pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link);
 800
 801         /* disable L1 entry -- workaround for pre-B1 */
 802         pci_write_config_byte(priv->pci_dev, PCI_LINK_CTRL, val_link & ~0x02);
 803
 804         spin_lock_irqsave(&priv->lock, flags);
 805
 806         /* set CSR_HW_CONFIG_REG for uCode use */
 807
 808         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 809                     CSR49_HW_IF_CONFIG_REG_BIT_4965_R |
 810                     CSR49_HW_IF_CONFIG_REG_BIT_RADIO_SI |
 811                     CSR49_HW_IF_CONFIG_REG_BIT_MAC_SI);
 812
 813         rc = iwl_grab_nic_access(priv);
 814         if (rc < 0) {
 815                 spin_unlock_irqrestore(&priv->lock, flags);
 816                 IWL_DEBUG_INFO("Failed to init the card\n");
 817                 return rc;
 818         }
 819
 820         iwl_read_prph(priv, APMG_PS_CTRL_REG);
 821         iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
 822         udelay(5);
 823         iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ);
 824
 825         iwl_release_nic_access(priv);
 826         spin_unlock_irqrestore(&priv->lock, flags);
 827
 828         iwl4965_hw_card_show_info(priv);
 829
 830         /* end nic_init */
 831
 832         /* Allocate the RX queue, or reset if it is already allocated */
 833         if (!rxq->bd) {
 834                 rc = iwl4965_rx_queue_alloc(priv);
 835                 if (rc) {
 836                         IWL_ERROR("Unable to initialize Rx queue\n");
 837                         return -ENOMEM;
 838                 }
 839         } else
 840                 iwl4965_rx_queue_reset(priv, rxq);
 841
 842         iwl4965_rx_replenish(priv);
 843
 844         iwl4965_rx_init(priv, rxq);
 845
 846         spin_lock_irqsave(&priv->lock, flags);
 847
 848         rxq->need_update = 1;
 849         iwl4965_rx_queue_update_write_ptr(priv, rxq);
 850
 851         spin_unlock_irqrestore(&priv->lock, flags);
 852
 853         /* Allocate and init all Tx and Command queues */
 854         rc = iwl4965_txq_ctx_reset(priv);
 855         if (rc)
 856                 return rc;
 857
 858         if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
 859                 IWL_DEBUG_RF_KILL("SW RF KILL supported in EEPROM.\n");
 860
 861         if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
 862                 IWL_DEBUG_RF_KILL("HW RF KILL supported in EEPROM.\n");
 863
 864         set_bit(STATUS_INIT, &priv->status);
 865
 866         return 0;
 867 }
 868
 869 int iwl4965_hw_nic_stop_master(struct iwl_priv *priv)
 870 {
 871         int rc = 0;
 872         u32 reg_val;
 873         unsigned long flags;
 874
 875         spin_lock_irqsave(&priv->lock, flags);
 876
 877         /* set stop master bit */
 878         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
 879
 880         reg_val = iwl_read32(priv, CSR_GP_CNTRL);
 881
 882         if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE ==
 883             (reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE))
 884                 IWL_DEBUG_INFO("Card in power save, master is already "
 885                                "stopped\n");
 886         else {
 887                 rc = iwl_poll_bit(priv, CSR_RESET,
 888                                   CSR_RESET_REG_FLAG_MASTER_DISABLED,
 889                                   CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
 890                 if (rc < 0) {
 891                         spin_unlock_irqrestore(&priv->lock, flags);
 892                         return rc;
 893                 }
 894         }
 895
 896         spin_unlock_irqrestore(&priv->lock, flags);
 897         IWL_DEBUG_INFO("stop master\n");
 898
 899         return rc;
 900 }
 901
 902 /**
 903  * iwl4965_hw_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
 904  */
 905 void iwl4965_hw_txq_ctx_stop(struct iwl_priv *priv)
 906 {
 907
 908         int txq_id;
 909         unsigned long flags;
 910
 911         /* Stop each Tx DMA channel, and wait for it to be idle */
 912         for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
 913                 spin_lock_irqsave(&priv->lock, flags);
 914                 if (iwl_grab_nic_access(priv)) {
 915                         spin_unlock_irqrestore(&priv->lock, flags);
 916                         continue;
 917                 }
 918
 919                 iwl_write_direct32(priv,
 920                                    IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id), 0x0);
 921                 iwl_poll_direct_bit(priv, IWL_FH_TSSR_TX_STATUS_REG,
 922                                     IWL_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE
 923                                     (txq_id), 200);
 924                 iwl_release_nic_access(priv);
 925                 spin_unlock_irqrestore(&priv->lock, flags);
 926         }
 927
 928         /* Deallocate memory for all Tx queues */
 929         iwl4965_hw_txq_ctx_free(priv);
 930 }
 931
 932 int iwl4965_hw_nic_reset(struct iwl_priv *priv)
 933 {
 934         int rc = 0;
 935         unsigned long flags;
 936
 937         iwl4965_hw_nic_stop_master(priv);
 938
 939         spin_lock_irqsave(&priv->lock, flags);
 940
 941         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 942
 943         udelay(10);
 944
 945         iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 946         rc = iwl_poll_bit(priv, CSR_RESET,
 947                           CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 948                           CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25);
 949
 950         udelay(10);
 951
 952         rc = iwl_grab_nic_access(priv);
 953         if (!rc) {
 954                 iwl_write_prph(priv, APMG_CLK_EN_REG,
 955                                 APMG_CLK_VAL_DMA_CLK_RQT |
 956                                 APMG_CLK_VAL_BSM_CLK_RQT);
 957
 958                 udelay(10);
 959
 960                 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
 961                                         APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 962
 963                 iwl_release_nic_access(priv);
 964         }
 965
 966         clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
 967         wake_up_interruptible(&priv->wait_command_queue);
 968
 969         spin_unlock_irqrestore(&priv->lock, flags);
 970
 971         return rc;
 972
 973 }
 974
 975 #define REG_RECALIB_PERIOD (60)
 976
 977 /**
 978  * iwl4965_bg_statistics_periodic - Timer callback to queue statistics
 979  *
 980  * This callback is provided in order to send a statistics request.
 981  *
 982  * This timer function is continually reset to execute within
 983  * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
 984  * was received.  We need to ensure we receive the statistics in order
 985  * to update the temperature used for calibrating the TXPOWER.
 986  */
 987 static void iwl4965_bg_statistics_periodic(unsigned long data)
 988 {
 989         struct iwl_priv *priv = (struct iwl_priv *)data;
 990
 991         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
 992                 return;
 993
 994         iwl_send_statistics_request(priv, CMD_ASYNC);
 995 }
 996
 997 #define CT_LIMIT_CONST          259
 998 #define TM_CT_KILL_THRESHOLD    110
 999
1000 void iwl4965_rf_kill_ct_config(struct iwl_priv *priv)
1001 {
1002         struct iwl4965_ct_kill_config cmd;
1003         u32 R1, R2, R3;
1004         u32 temp_th;
1005         u32 crit_temperature;
1006         unsigned long flags;
1007         int ret = 0;
1008
1009         spin_lock_irqsave(&priv->lock, flags);
1010         iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
1011                     CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
1012         spin_unlock_irqrestore(&priv->lock, flags);
1013
1014         if (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK) {
1015                 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
1016                 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
1017                 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
1018         } else {
1019                 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
1020                 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
1021                 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
1022         }
1023
1024         temp_th = CELSIUS_TO_KELVIN(TM_CT_KILL_THRESHOLD);
1025
1026         crit_temperature = ((temp_th * (R3-R1))/CT_LIMIT_CONST) + R2;
1027         cmd.critical_temperature_R =  cpu_to_le32(crit_temperature);
1028         ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
1029                                sizeof(cmd), &cmd);
1030         if (ret)
1031                 IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n");
1032         else
1033                 IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded\n");
1034 }
1035
1036 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
1037
1038 /* Reset differential Rx gains in NIC to prepare for chain noise calibration.
1039  * Called after every association, but this runs only once!
1040  *  ... once chain noise is calibrated the first time, it's good forever.  */
1041 static void iwl4965_chain_noise_reset(struct iwl_priv *priv)
1042 {
1043         struct iwl_chain_noise_data *data = &(priv->chain_noise_data);
1044
1045         if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
1046                 struct iwl4965_calibration_cmd cmd;
1047
1048                 memset(&cmd, 0, sizeof(cmd));
1049                 cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
1050                 cmd.diff_gain_a = 0;
1051                 cmd.diff_gain_b = 0;
1052                 cmd.diff_gain_c = 0;
1053                 if (iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
1054                                  sizeof(cmd), &cmd))
1055                         IWL_ERROR("Could not send REPLY_PHY_CALIBRATION_CMD\n");
1056                 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
1057                 IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
1058         }
1059 }
1060
1061 static void iwl4965_gain_computation(struct iwl_priv *priv,
1062                 u32 *average_noise,
1063                 u16 min_average_noise_antenna_i,
1064                 u32 min_average_noise)
1065 {
1066         int i, ret;
1067         struct iwl_chain_noise_data *data = &priv->chain_noise_data;
1068
1069         data->delta_gain_code[min_average_noise_antenna_i] = 0;
1070
1071         for (i = 0; i < NUM_RX_CHAINS; i++) {
1072                 s32 delta_g = 0;
1073
1074                 if (!(data->disconn_array[i]) &&
1075                     (data->delta_gain_code[i] ==
1076                              CHAIN_NOISE_DELTA_GAIN_INIT_VAL)) {
1077                         delta_g = average_noise[i] - min_average_noise;
1078                         data->delta_gain_code[i] = (u8)((delta_g * 10) / 15);
1079                         data->delta_gain_code[i] =
1080                                 min(data->delta_gain_code[i],
1081                                 (u8) CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
1082
1083                         data->delta_gain_code[i] =
1084                                 (data->delta_gain_code[i] | (1 << 2));
1085                 } else {
1086                         data->delta_gain_code[i] = 0;
1087                 }
1088         }
1089         IWL_DEBUG_CALIB("delta_gain_codes: a %d b %d c %d\n",
1090                      data->delta_gain_code[0],
1091                      data->delta_gain_code[1],
1092                      data->delta_gain_code[2]);
1093
1094         /* Differential gain gets sent to uCode only once */
1095         if (!data->radio_write) {
1096                 struct iwl4965_calibration_cmd cmd;
1097                 data->radio_write = 1;
1098
1099                 memset(&cmd, 0, sizeof(cmd));
1100                 cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
1101                 cmd.diff_gain_a = data->delta_gain_code[0];
1102                 cmd.diff_gain_b = data->delta_gain_code[1];
1103                 cmd.diff_gain_c = data->delta_gain_code[2];
1104                 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
1105                                       sizeof(cmd), &cmd);
1106                 if (ret)
1107                         IWL_DEBUG_CALIB("fail sending cmd "
1108                                      "REPLY_PHY_CALIBRATION_CMD \n");
1109
1110                 /* TODO we might want recalculate
1111                  * rx_chain in rxon cmd */
1112
1113                 /* Mark so we run this algo only once! */
1114                 data->state = IWL_CHAIN_NOISE_CALIBRATED;
1115         }
1116         data->chain_noise_a = 0;
1117         data->chain_noise_b = 0;
1118         data->chain_noise_c = 0;
1119         data->chain_signal_a = 0;
1120         data->chain_signal_b = 0;
1121         data->chain_signal_c = 0;
1122         data->beacon_count = 0;
1123 }
1124
1125 static void iwl4965_bg_sensitivity_work(struct work_struct *work)
1126 {
1127         struct iwl_priv *priv = container_of(work, struct iwl_priv,
1128                         sensitivity_work);
1129
1130         mutex_lock(&priv->mutex);
1131
1132         if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
1133             test_bit(STATUS_SCANNING, &priv->status)) {
1134                 mutex_unlock(&priv->mutex);
1135                 return;
1136         }
1137
1138         if (priv->start_calib) {
1139                 iwl_chain_noise_calibration(priv, &priv->statistics);
1140
1141                 iwl_sensitivity_calibration(priv, &priv->statistics);
1142         }
1143
1144         mutex_unlock(&priv->mutex);
1145         return;
1146 }
1147 #endif /*CONFIG_IWL4965_RUN_TIME_CALIB*/
1148
1149 static void iwl4965_bg_txpower_work(struct work_struct *work)
1150 {
1151         struct iwl_priv *priv = container_of(work, struct iwl_priv,
1152                         txpower_work);
1153
1154         /* If a scan happened to start before we got here
1155          * then just return; the statistics notification will
1156          * kick off another scheduled work to compensate for
1157          * any temperature delta we missed here. */
1158         if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
1159             test_bit(STATUS_SCANNING, &priv->status))
1160                 return;
1161
1162         mutex_lock(&priv->mutex);
1163
1164         /* Regardless of if we are assocaited, we must reconfigure the
1165          * TX power since frames can be sent on non-radar channels while
1166          * not associated */
1167         iwl4965_hw_reg_send_txpower(priv);
1168
1169         /* Update last_temperature to keep is_calib_needed from running
1170          * when it isn't needed... */
1171         priv->last_temperature = priv->temperature;
1172
1173         mutex_unlock(&priv->mutex);
1174 }
1175
1176 /*
1177  * Acquire priv->lock before calling this function !
1178  */
1179 static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
1180 {
1181         iwl_write_direct32(priv, HBUS_TARG_WRPTR,
1182                              (index & 0xff) | (txq_id << 8));
1183         iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(txq_id), index);
1184 }
1185
1186 /**
1187  * iwl4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
1188  * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
1189  * @scd_retry: (1) Indicates queue will be used in aggregation mode
1190  *
1191  * NOTE:  Acquire priv->lock before calling this function !
1192  */
1193 static void iwl4965_tx_queue_set_status(struct iwl_priv *priv,
1194                                         struct iwl4965_tx_queue *txq,
1195                                         int tx_fifo_id, int scd_retry)
1196 {
1197         int txq_id = txq->q.id;
1198
1199         /* Find out whether to activate Tx queue */
1200         int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
1201
1202         /* Set up and activate */
1203         iwl_write_prph(priv, IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
1204                                  (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
1205                                  (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) |
1206                                  (scd_retry << SCD_QUEUE_STTS_REG_POS_WSL) |
1207                                  (scd_retry << SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
1208                                  SCD_QUEUE_STTS_REG_MSK);
1209
1210         txq->sched_retry = scd_retry;
1211
1212         IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
1213                        active ? "Activate" : "Deactivate",
1214                        scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
1215 }
1216
1217 static const u16 default_queue_to_tx_fifo[] = {
1218         IWL_TX_FIFO_AC3,
1219         IWL_TX_FIFO_AC2,
1220         IWL_TX_FIFO_AC1,
1221         IWL_TX_FIFO_AC0,
1222         IWL_CMD_FIFO_NUM,
1223         IWL_TX_FIFO_HCCA_1,
1224         IWL_TX_FIFO_HCCA_2
1225 };
1226
1227 static inline void iwl4965_txq_ctx_activate(struct iwl_priv *priv, int txq_id)
1228 {
1229         set_bit(txq_id, &priv->txq_ctx_active_msk);
1230 }
1231
1232 static inline void iwl4965_txq_ctx_deactivate(struct iwl_priv *priv, int txq_id)
1233 {
1234         clear_bit(txq_id, &priv->txq_ctx_active_msk);
1235 }
1236
1237 int iwl4965_alive_notify(struct iwl_priv *priv)
1238 {
1239         u32 a;
1240         int i = 0;
1241         unsigned long flags;
1242         int ret;
1243
1244         spin_lock_irqsave(&priv->lock, flags);
1245
1246 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
1247         memset(&(priv->sensitivity_data), 0,
1248                sizeof(struct iwl_sensitivity_data));
1249         memset(&(priv->chain_noise_data), 0,
1250                sizeof(struct iwl_chain_noise_data));
1251         for (i = 0; i < NUM_RX_CHAINS; i++)
1252                 priv->chain_noise_data.delta_gain_code[i] =
1253                                 CHAIN_NOISE_DELTA_GAIN_INIT_VAL;
1254 #endif /* CONFIG_IWL4965_RUN_TIME_CALIB*/
1255         ret = iwl_grab_nic_access(priv);
1256         if (ret) {
1257                 spin_unlock_irqrestore(&priv->lock, flags);
1258                 return ret;
1259         }
1260
1261         /* Clear 4965's internal Tx Scheduler data base */
1262         priv->scd_base_addr = iwl_read_prph(priv, IWL49_SCD_SRAM_BASE_ADDR);
1263         a = priv->scd_base_addr + SCD_CONTEXT_DATA_OFFSET;
1264         for (; a < priv->scd_base_addr + SCD_TX_STTS_BITMAP_OFFSET; a += 4)
1265                 iwl_write_targ_mem(priv, a, 0);
1266         for (; a < priv->scd_base_addr + SCD_TRANSLATE_TBL_OFFSET; a += 4)
1267                 iwl_write_targ_mem(priv, a, 0);
1268         for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
1269                 iwl_write_targ_mem(priv, a, 0);
1270
1271         /* Tel 4965 where to find Tx byte count tables */
1272         iwl_write_prph(priv, IWL49_SCD_DRAM_BASE_ADDR,
1273                 (priv->shared_phys +
1274                  offsetof(struct iwl4965_shared, queues_byte_cnt_tbls)) >> 10);
1275
1276         /* Disable chain mode for all queues */
1277         iwl_write_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, 0);
1278
1279         /* Initialize each Tx queue (including the command queue) */
1280         for (i = 0; i < priv->hw_params.max_txq_num; i++) {
1281
1282                 /* TFD circular buffer read/write indexes */
1283                 iwl_write_prph(priv, IWL49_SCD_QUEUE_RDPTR(i), 0);
1284                 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
1285
1286                 /* Max Tx Window size for Scheduler-ACK mode */
1287                 iwl_write_targ_mem(priv, priv->scd_base_addr +
1288                                         SCD_CONTEXT_QUEUE_OFFSET(i),
1289                                         (SCD_WIN_SIZE <<
1290                                         SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
1291                                         SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
1292
1293                 /* Frame limit */
1294                 iwl_write_targ_mem(priv, priv->scd_base_addr +
1295                                         SCD_CONTEXT_QUEUE_OFFSET(i) +
1296                                         sizeof(u32),
1297                                         (SCD_FRAME_LIMIT <<
1298                                         SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1299                                         SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
1300
1301         }
1302         iwl_write_prph(priv, IWL49_SCD_INTERRUPT_MASK,
1303                                  (1 << priv->hw_params.max_txq_num) - 1);
1304
1305         /* Activate all Tx DMA/FIFO channels */
1306         iwl_write_prph(priv, IWL49_SCD_TXFACT,
1307                                  SCD_TXFACT_REG_TXFIFO_MASK(0, 7));
1308
1309         iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
1310
1311         /* Map each Tx/cmd queue to its corresponding fifo */
1312         for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
1313                 int ac = default_queue_to_tx_fifo[i];
1314                 iwl4965_txq_ctx_activate(priv, i);
1315                 iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
1316         }
1317
1318         iwl_release_nic_access(priv);
1319         spin_unlock_irqrestore(&priv->lock, flags);
1320
1321         /* Ask for statistics now, the uCode will send statistics notification
1322          * periodically after association */
1323         iwl_send_statistics_request(priv, CMD_ASYNC);
1324         return ret;
1325 }
1326
1327 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
1328 static struct iwl_sensitivity_ranges iwl4965_sensitivity = {
1329         .min_nrg_cck = 97,
1330         .max_nrg_cck = 0,
1331
1332         .auto_corr_min_ofdm = 85,
1333         .auto_corr_min_ofdm_mrc = 170,
1334         .auto_corr_min_ofdm_x1 = 105,
1335         .auto_corr_min_ofdm_mrc_x1 = 220,
1336
1337         .auto_corr_max_ofdm = 120,
1338         .auto_corr_max_ofdm_mrc = 210,
1339         .auto_corr_max_ofdm_x1 = 140,
1340         .auto_corr_max_ofdm_mrc_x1 = 270,
1341
1342         .auto_corr_min_cck = 125,
1343         .auto_corr_max_cck = 200,
1344         .auto_corr_min_cck_mrc = 200,
1345         .auto_corr_max_cck_mrc = 400,
1346
1347         .nrg_th_cck = 100,
1348         .nrg_th_ofdm = 100,
1349 };
1350 #endif
1351
1352 /**
1353  * iwl4965_hw_set_hw_params
1354  *
1355  * Called when initializing driver
1356  */
1357 int iwl4965_hw_set_hw_params(struct iwl_priv *priv)
1358 {
1359
1360         if ((priv->cfg->mod_params->num_of_queues > IWL4965_MAX_NUM_QUEUES) ||
1361             (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
1362                 IWL_ERROR("invalid queues_num, should be between %d and %d\n",
1363                           IWL_MIN_NUM_QUEUES, IWL4965_MAX_NUM_QUEUES);
1364                 return -EINVAL;
1365         }
1366
1367         priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
1368         priv->hw_params.tx_cmd_len = sizeof(struct iwl4965_tx_cmd);
1369         priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
1370         priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
1371         if (priv->cfg->mod_params->amsdu_size_8K)
1372                 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_8K;
1373         else
1374                 priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_4K;
1375         priv->hw_params.max_pkt_size = priv->hw_params.rx_buf_size - 256;
1376         priv->hw_params.max_stations = IWL4965_STATION_COUNT;
1377         priv->hw_params.bcast_sta_id = IWL4965_BROADCAST_ID;
1378
1379         priv->hw_params.tx_chains_num = 2;
1380         priv->hw_params.rx_chains_num = 2;
1381         priv->hw_params.valid_tx_ant = (IWL_ANTENNA_MAIN | IWL_ANTENNA_AUX);
1382         priv->hw_params.valid_rx_ant = (IWL_ANTENNA_MAIN | IWL_ANTENNA_AUX);
1383 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
1384         priv->hw_params.sens = &iwl4965_sensitivity;
1385 #endif
1386
1387         return 0;
1388 }
1389
1390 /**
1391  * iwl4965_hw_txq_ctx_free - Free TXQ Context
1392  *
1393  * Destroy all TX DMA queues and structures
1394  */
1395 void iwl4965_hw_txq_ctx_free(struct iwl_priv *priv)
1396 {
1397         int txq_id;
1398
1399         /* Tx queues */
1400         for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
1401                 iwl4965_tx_queue_free(priv, &priv->txq[txq_id]);
1402
1403         /* Keep-warm buffer */
1404         iwl4965_kw_free(priv);
1405 }
1406
1407 /**
1408  * iwl4965_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
1409  *
1410  * Does NOT advance any TFD circular buffer read/write indexes
1411  * Does NOT free the TFD itself (which is within circular buffer)
1412  */
1413 int iwl4965_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl4965_tx_queue *txq)
1414 {
1415         struct iwl4965_tfd_frame *bd_tmp = (struct iwl4965_tfd_frame *)&txq->bd[0];
1416         struct iwl4965_tfd_frame *bd = &bd_tmp[txq->q.read_ptr];
1417         struct pci_dev *dev = priv->pci_dev;
1418         int i;
1419         int counter = 0;
1420         int index, is_odd;
1421
1422         /* Host command buffers stay mapped in memory, nothing to clean */
1423         if (txq->q.id == IWL_CMD_QUEUE_NUM)
1424                 return 0;
1425
1426         /* Sanity check on number of chunks */
1427         counter = IWL_GET_BITS(*bd, num_tbs);
1428         if (counter > MAX_NUM_OF_TBS) {
1429                 IWL_ERROR("Too many chunks: %i\n", counter);
1430                 /* @todo issue fatal error, it is quite serious situation */
1431                 return 0;
1432         }
1433
1434         /* Unmap chunks, if any.
1435          * TFD info for odd chunks is different format than for even chunks. */
1436         for (i = 0; i < counter; i++) {
1437                 index = i / 2;
1438                 is_odd = i & 0x1;
1439
1440                 if (is_odd)
1441                         pci_unmap_single(
1442                                 dev,
1443                                 IWL_GET_BITS(bd->pa[index], tb2_addr_lo16) |
1444                                 (IWL_GET_BITS(bd->pa[index],
1445                                               tb2_addr_hi20) << 16),
1446                                 IWL_GET_BITS(bd->pa[index], tb2_len),
1447                                 PCI_DMA_TODEVICE);
1448
1449                 else if (i > 0)
1450                         pci_unmap_single(dev,
1451                                          le32_to_cpu(bd->pa[index].tb1_addr),
1452                                          IWL_GET_BITS(bd->pa[index], tb1_len),
1453                                          PCI_DMA_TODEVICE);
1454
1455                 /* Free SKB, if any, for this chunk */
1456                 if (txq->txb[txq->q.read_ptr].skb[i]) {
1457                         struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[i];
1458
1459                         dev_kfree_skb(skb);
1460                         txq->txb[txq->q.read_ptr].skb[i] = NULL;
1461                 }
1462         }
1463         return 0;
1464 }
1465
1466 int iwl4965_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
1467 {
1468         IWL_ERROR("TODO: Implement iwl4965_hw_reg_set_txpower!\n");
1469         return -EINVAL;
1470 }
1471
1472 static s32 iwl4965_math_div_round(s32 num, s32 denom, s32 *res)
1473 {
1474         s32 sign = 1;
1475
1476         if (num < 0) {
1477                 sign = -sign;
1478                 num = -num;
1479         }
1480         if (denom < 0) {
1481                 sign = -sign;
1482                 denom = -denom;
1483         }
1484         *res = 1;
1485         *res = ((num * 2 + denom) / (denom * 2)) * sign;
1486
1487         return 1;
1488 }
1489
1490 /**
1491  * iwl4965_get_voltage_compensation - Power supply voltage comp for txpower
1492  *
1493  * Determines power supply voltage compensation for txpower calculations.
1494  * Returns number of 1/2-dB steps to subtract from gain table index,
1495  * to compensate for difference between power supply voltage during
1496  * factory measurements, vs. current power supply voltage.
1497  *
1498  * Voltage indication is higher for lower voltage.
1499  * Lower voltage requires more gain (lower gain table index).
1500  */
1501 static s32 iwl4965_get_voltage_compensation(s32 eeprom_voltage,
1502                                             s32 current_voltage)
1503 {
1504         s32 comp = 0;
1505
1506         if ((TX_POWER_IWL_ILLEGAL_VOLTAGE == eeprom_voltage) ||
1507             (TX_POWER_IWL_ILLEGAL_VOLTAGE == current_voltage))
1508                 return 0;
1509
1510         iwl4965_math_div_round(current_voltage - eeprom_voltage,
1511                                TX_POWER_IWL_VOLTAGE_CODES_PER_03V, &comp);
1512
1513         if (current_voltage > eeprom_voltage)
1514                 comp *= 2;
1515         if ((comp < -2) || (comp > 2))
1516                 comp = 0;
1517
1518         return comp;
1519 }
1520
1521 static const struct iwl_channel_info *
1522 iwl4965_get_channel_txpower_info(struct iwl_priv *priv,
1523                                  enum ieee80211_band band, u16 channel)
1524 {
1525         const struct iwl_channel_info *ch_info;
1526
1527         ch_info = iwl_get_channel_info(priv, band, channel);
1528
1529         if (!is_channel_valid(ch_info))
1530                 return NULL;
1531
1532         return ch_info;
1533 }
1534
1535 static s32 iwl4965_get_tx_atten_grp(u16 channel)
1536 {
1537         if (channel >= CALIB_IWL_TX_ATTEN_GR5_FCH &&
1538             channel <= CALIB_IWL_TX_ATTEN_GR5_LCH)
1539                 return CALIB_CH_GROUP_5;
1540
1541         if (channel >= CALIB_IWL_TX_ATTEN_GR1_FCH &&
1542             channel <= CALIB_IWL_TX_ATTEN_GR1_LCH)
1543                 return CALIB_CH_GROUP_1;
1544
1545         if (channel >= CALIB_IWL_TX_ATTEN_GR2_FCH &&
1546             channel <= CALIB_IWL_TX_ATTEN_GR2_LCH)
1547                 return CALIB_CH_GROUP_2;
1548
1549         if (channel >= CALIB_IWL_TX_ATTEN_GR3_FCH &&
1550             channel <= CALIB_IWL_TX_ATTEN_GR3_LCH)
1551                 return CALIB_CH_GROUP_3;
1552
1553         if (channel >= CALIB_IWL_TX_ATTEN_GR4_FCH &&
1554             channel <= CALIB_IWL_TX_ATTEN_GR4_LCH)
1555                 return CALIB_CH_GROUP_4;
1556
1557         IWL_ERROR("Can't find txatten group for channel %d.\n", channel);
1558         return -1;
1559 }
1560
1561 static u32 iwl4965_get_sub_band(const struct iwl_priv *priv, u32 channel)
1562 {
1563         s32 b = -1;
1564
1565         for (b = 0; b < EEPROM_TX_POWER_BANDS; b++) {
1566                 if (priv->eeprom.calib_info.band_info[b].ch_from == 0)
1567                         continue;
1568
1569                 if ((channel >= priv->eeprom.calib_info.band_info[b].ch_from)
1570                     && (channel <= priv->eeprom.calib_info.band_info[b].ch_to))
1571                         break;
1572         }
1573
1574         return b;
1575 }
1576
1577 static s32 iwl4965_interpolate_value(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
1578 {
1579         s32 val;
1580
1581         if (x2 == x1)
1582                 return y1;
1583         else {
1584                 iwl4965_math_div_round((x2 - x) * (y1 - y2), (x2 - x1), &val);
1585                 return val + y2;
1586         }
1587 }
1588
1589 /**
1590  * iwl4965_interpolate_chan - Interpolate factory measurements for one channel
1591  *
1592  * Interpolates factory measurements from the two sample channels within a
1593  * sub-band, to apply to channel of interest.  Interpolation is proportional to
1594  * differences in channel frequencies, which is proportional to differences
1595  * in channel number.
1596  */
1597 static int iwl4965_interpolate_chan(struct iwl_priv *priv, u32 channel,
1598                                     struct iwl4965_eeprom_calib_ch_info *chan_info)
1599 {
1600         s32 s = -1;
1601         u32 c;
1602         u32 m;
1603         const struct iwl4965_eeprom_calib_measure *m1;
1604         const struct iwl4965_eeprom_calib_measure *m2;
1605         struct iwl4965_eeprom_calib_measure *omeas;
1606         u32 ch_i1;
1607         u32 ch_i2;
1608
1609         s = iwl4965_get_sub_band(priv, channel);
1610         if (s >= EEPROM_TX_POWER_BANDS) {
1611                 IWL_ERROR("Tx Power can not find channel %d ", channel);
1612                 return -1;
1613         }
1614
1615         ch_i1 = priv->eeprom.calib_info.band_info[s].ch1.ch_num;
1616         ch_i2 = priv->eeprom.calib_info.band_info[s].ch2.ch_num;
1617         chan_info->ch_num = (u8) channel;
1618
1619         IWL_DEBUG_TXPOWER("channel %d subband %d factory cal ch %d & %d\n",
1620                           channel, s, ch_i1, ch_i2);
1621
1622         for (c = 0; c < EEPROM_TX_POWER_TX_CHAINS; c++) {
1623                 for (m = 0; m < EEPROM_TX_POWER_MEASUREMENTS; m++) {
1624                         m1 = &(priv->eeprom.calib_info.band_info[s].ch1.
1625                                measurements[c][m]);
1626                         m2 = &(priv->eeprom.calib_info.band_info[s].ch2.
1627                                measurements[c][m]);
1628                         omeas = &(chan_info->measurements[c][m]);
1629
1630                         omeas->actual_pow =
1631                             (u8) iwl4965_interpolate_value(channel, ch_i1,
1632                                                            m1->actual_pow,
1633                                                            ch_i2,
1634                                                            m2->actual_pow);
1635                         omeas->gain_idx =
1636                             (u8) iwl4965_interpolate_value(channel, ch_i1,
1637                                                            m1->gain_idx, ch_i2,
1638                                                            m2->gain_idx);
1639                         omeas->temperature =
1640                             (u8) iwl4965_interpolate_value(channel, ch_i1,
1641                                                            m1->temperature,
1642                                                            ch_i2,
1643                                                            m2->temperature);
1644                         omeas->pa_det =
1645                             (s8) iwl4965_interpolate_value(channel, ch_i1,
1646                                                            m1->pa_det, ch_i2,
1647                                                            m2->pa_det);
1648
1649                         IWL_DEBUG_TXPOWER
1650                             ("chain %d meas %d AP1=%d AP2=%d AP=%d\n", c, m,
1651                              m1->actual_pow, m2->actual_pow, omeas->actual_pow);
1652                         IWL_DEBUG_TXPOWER
1653                             ("chain %d meas %d NI1=%d NI2=%d NI=%d\n", c, m,
1654                              m1->gain_idx, m2->gain_idx, omeas->gain_idx);
1655                         IWL_DEBUG_TXPOWER
1656                             ("chain %d meas %d PA1=%d PA2=%d PA=%d\n", c, m,
1657                              m1->pa_det, m2->pa_det, omeas->pa_det);
1658                         IWL_DEBUG_TXPOWER
1659                             ("chain %d meas %d  T1=%d  T2=%d  T=%d\n", c, m,
1660                              m1->temperature, m2->temperature,
1661                              omeas->temperature);
1662                 }
1663         }
1664
1665         return 0;
1666 }
1667
1668 /* bit-rate-dependent table to prevent Tx distortion, in half-dB units,
1669  * for OFDM 6, 12, 18, 24, 36, 48, 54, 60 MBit, and CCK all rates. */
1670 static s32 back_off_table[] = {
1671         10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 20 MHz */
1672         10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 20 MHz */
1673         10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 40 MHz */
1674         10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 40 MHz */
1675         10                      /* CCK */
1676 };
1677
1678 /* Thermal compensation values for txpower for various frequency ranges ...
1679  *   ratios from 3:1 to 4.5:1 of degrees (Celsius) per half-dB gain adjust */
1680 static struct iwl4965_txpower_comp_entry {
1681         s32 degrees_per_05db_a;
1682         s32 degrees_per_05db_a_denom;
1683 } tx_power_cmp_tble[CALIB_CH_GROUP_MAX] = {
1684         {9, 2},                 /* group 0 5.2, ch  34-43 */
1685         {4, 1},                 /* group 1 5.2, ch  44-70 */
1686         {4, 1},                 /* group 2 5.2, ch  71-124 */
1687         {4, 1},                 /* group 3 5.2, ch 125-200 */
1688         {3, 1}                  /* group 4 2.4, ch   all */
1689 };
1690
1691 static s32 get_min_power_index(s32 rate_power_index, u32 band)
1692 {
1693         if (!band) {
1694                 if ((rate_power_index & 7) <= 4)
1695                         return MIN_TX_GAIN_INDEX_52GHZ_EXT;
1696         }
1697         return MIN_TX_GAIN_INDEX;
1698 }
1699
1700 struct gain_entry {
1701         u8 dsp;
1702         u8 radio;
1703 };
1704
1705 static const struct gain_entry gain_table[2][108] = {
1706         /* 5.2GHz power gain index table */
1707         {
1708          {123, 0x3F},           /* highest txpower */
1709          {117, 0x3F},
1710          {110, 0x3F},
1711          {104, 0x3F},
1712          {98, 0x3F},
1713          {110, 0x3E},
1714          {104, 0x3E},
1715          {98, 0x3E},
1716          {110, 0x3D},
1717          {104, 0x3D},
1718          {98, 0x3D},
1719          {110, 0x3C},
1720          {104, 0x3C},
1721          {98, 0x3C},
1722          {110, 0x3B},
1723          {104, 0x3B},
1724          {98, 0x3B},
1725          {110, 0x3A},
1726          {104, 0x3A},
1727          {98, 0x3A},
1728          {110, 0x39},
1729          {104, 0x39},
1730          {98, 0x39},
1731          {110, 0x38},
1732          {104, 0x38},
1733          {98, 0x38},
1734          {110, 0x37},
1735          {104, 0x37},
1736          {98, 0x37},
1737          {110, 0x36},
1738          {104, 0x36},
1739          {98, 0x36},
1740          {110, 0x35},
1741          {104, 0x35},
1742          {98, 0x35},
1743          {110, 0x34},
1744          {104, 0x34},
1745          {98, 0x34},
1746          {110, 0x33},
1747          {104, 0x33},
1748          {98, 0x33},
1749          {110, 0x32},
1750          {104, 0x32},
1751          {98, 0x32},
1752          {110, 0x31},
1753          {104, 0x31},
1754          {98, 0x31},
1755          {110, 0x30},
1756          {104, 0x30},
1757          {98, 0x30},
1758          {110, 0x25},
1759          {104, 0x25},
1760          {98, 0x25},
1761          {110, 0x24},
1762          {104, 0x24},
1763          {98, 0x24},
1764          {110, 0x23},
1765          {104, 0x23},
1766          {98, 0x23},
1767          {110, 0x22},
1768          {104, 0x18},
1769          {98, 0x18},
1770          {110, 0x17},
1771          {104, 0x17},
1772          {98, 0x17},
1773          {110, 0x16},
1774          {104, 0x16},
1775          {98, 0x16},
1776          {110, 0x15},
1777          {104, 0x15},
1778          {98, 0x15},
1779          {110, 0x14},
1780          {104, 0x14},
1781          {98, 0x14},
1782          {110, 0x13},
1783          {104, 0x13},
1784          {98, 0x13},
1785          {110, 0x12},
1786          {104, 0x08},
1787          {98, 0x08},
1788          {110, 0x07},
1789          {104, 0x07},
1790          {98, 0x07},
1791          {110, 0x06},
1792          {104, 0x06},
1793          {98, 0x06},
1794          {110, 0x05},
1795          {104, 0x05},
1796          {98, 0x05},
1797          {110, 0x04},
1798          {104, 0x04},
1799          {98, 0x04},
1800          {110, 0x03},
1801          {104, 0x03},
1802          {98, 0x03},
1803          {110, 0x02},
1804          {104, 0x02},
1805          {98, 0x02},
1806          {110, 0x01},
1807          {104, 0x01},
1808          {98, 0x01},
1809          {110, 0x00},
1810          {104, 0x00},
1811          {98, 0x00},
1812          {93, 0x00},
1813          {88, 0x00},
1814          {83, 0x00},
1815          {78, 0x00},
1816          },
1817         /* 2.4GHz power gain index table */
1818         {
1819          {110, 0x3f},           /* highest txpower */
1820          {104, 0x3f},
1821          {98, 0x3f},
1822          {110, 0x3e},
1823          {104, 0x3e},
1824          {98, 0x3e},
1825          {110, 0x3d},
1826          {104, 0x3d},
1827          {98, 0x3d},
1828          {110, 0x3c},
1829          {104, 0x3c},
1830          {98, 0x3c},
1831          {110, 0x3b},
1832          {104, 0x3b},
1833          {98, 0x3b},
1834          {110, 0x3a},
1835          {104, 0x3a},
1836          {98, 0x3a},
1837          {110, 0x39},
1838          {104, 0x39},
1839          {98, 0x39},
1840          {110, 0x38},
1841          {104, 0x38},
1842          {98, 0x38},
1843          {110, 0x37},
1844          {104, 0x37},
1845          {98, 0x37},
1846          {110, 0x36},
1847          {104, 0x36},
1848          {98, 0x36},
1849          {110, 0x35},
1850          {104, 0x35},
1851          {98, 0x35},
1852          {110, 0x34},
1853          {104, 0x34},
1854          {98, 0x34},
1855          {110, 0x33},
1856          {104, 0x33},
1857          {98, 0x33},
1858          {110, 0x32},
1859          {104, 0x32},
1860          {98, 0x32},
1861          {110, 0x31},
1862          {104, 0x31},
1863          {98, 0x31},
1864          {110, 0x30},
1865          {104, 0x30},
1866          {98, 0x30},
1867          {110, 0x6},
1868          {104, 0x6},
1869          {98, 0x6},
1870          {110, 0x5},
1871          {104, 0x5},
1872          {98, 0x5},
1873          {110, 0x4},
1874          {104, 0x4},
1875          {98, 0x4},
1876          {110, 0x3},
1877          {104, 0x3},
1878          {98, 0x3},
1879          {110, 0x2},
1880          {104, 0x2},
1881          {98, 0x2},
1882          {110, 0x1},
1883          {104, 0x1},
1884          {98, 0x1},
1885          {110, 0x0},
1886          {104, 0x0},
1887          {98, 0x0},
1888          {97, 0},
1889          {96, 0},
1890          {95, 0},
1891          {94, 0},
1892          {93, 0},
1893          {92, 0},
1894          {91, 0},
1895          {90, 0},
1896          {89, 0},
1897          {88, 0},
1898          {87, 0},
1899          {86, 0},
1900          {85, 0},
1901          {84, 0},
1902          {83, 0},
1903          {82, 0},
1904          {81, 0},
1905          {80, 0},
1906          {79, 0},
1907          {78, 0},
1908          {77, 0},
1909          {76, 0},
1910          {75, 0},
1911          {74, 0},
1912          {73, 0},
1913          {72, 0},
1914          {71, 0},
1915          {70, 0},
1916          {69, 0},
1917          {68, 0},
1918          {67, 0},
1919          {66, 0},
1920          {65, 0},
1921          {64, 0},
1922          {63, 0},
1923          {62, 0},
1924          {61, 0},
1925          {60, 0},
1926          {59, 0},
1927          }
1928 };
1929
1930 static int iwl4965_fill_txpower_tbl(struct iwl_priv *priv, u8 band, u16 channel,
1931                                     u8 is_fat, u8 ctrl_chan_high,
1932                                     struct iwl4965_tx_power_db *tx_power_tbl)
1933 {
1934         u8 saturation_power;
1935         s32 target_power;
1936         s32 user_target_power;
1937         s32 power_limit;
1938         s32 current_temp;
1939         s32 reg_limit;
1940         s32 current_regulatory;
1941         s32 txatten_grp = CALIB_CH_GROUP_MAX;
1942         int i;
1943         int c;
1944         const struct iwl_channel_info *ch_info = NULL;
1945         struct iwl4965_eeprom_calib_ch_info ch_eeprom_info;
1946         const struct iwl4965_eeprom_calib_measure *measurement;
1947         s16 voltage;
1948         s32 init_voltage;
1949         s32 voltage_compensation;
1950         s32 degrees_per_05db_num;
1951         s32 degrees_per_05db_denom;
1952         s32 factory_temp;
1953         s32 temperature_comp[2];
1954         s32 factory_gain_index[2];
1955         s32 factory_actual_pwr[2];
1956         s32 power_index;
1957
1958         /* Sanity check requested level (dBm) */
1959         if (priv->user_txpower_limit < IWL_TX_POWER_TARGET_POWER_MIN) {
1960                 IWL_WARNING("Requested user TXPOWER %d below limit.\n",
1961                             priv->user_txpower_limit);
1962                 return -EINVAL;
1963         }
1964         if (priv->user_txpower_limit > IWL_TX_POWER_TARGET_POWER_MAX) {
1965                 IWL_WARNING("Requested user TXPOWER %d above limit.\n",
1966                             priv->user_txpower_limit);
1967                 return -EINVAL;
1968         }
1969
1970         /* user_txpower_limit is in dBm, convert to half-dBm (half-dB units
1971          *   are used for indexing into txpower table) */
1972         user_target_power = 2 * priv->user_txpower_limit;
1973
1974         /* Get current (RXON) channel, band, width */
1975         ch_info =
1976                 iwl4965_get_channel_txpower_info(priv, priv->band, channel);
1977
1978         IWL_DEBUG_TXPOWER("chan %d band %d is_fat %d\n", channel, band,
1979                           is_fat);
1980
1981         if (!ch_info)
1982                 return -EINVAL;
1983
1984         /* get txatten group, used to select 1) thermal txpower adjustment
1985          *   and 2) mimo txpower balance between Tx chains. */
1986         txatten_grp = iwl4965_get_tx_atten_grp(channel);
1987         if (txatten_grp < 0)
1988                 return -EINVAL;
1989
1990         IWL_DEBUG_TXPOWER("channel %d belongs to txatten group %d\n",
1991                           channel, txatten_grp);
1992
1993         if (is_fat) {
1994                 if (ctrl_chan_high)
1995                         channel -= 2;
1996                 else
1997                         channel += 2;
1998         }
1999
2000         /* hardware txpower limits ...
2001          * saturation (clipping distortion) txpowers are in half-dBm */
2002         if (band)
2003                 saturation_power = priv->eeprom.calib_info.saturation_power24;
2004         else
2005                 saturation_power = priv->eeprom.calib_info.saturation_power52;
2006
2007         if (saturation_power < IWL_TX_POWER_SATURATION_MIN ||
2008             saturation_power > IWL_TX_POWER_SATURATION_MAX) {
2009                 if (band)
2010                         saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_24;
2011                 else
2012                         saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_52;
2013         }
2014
2015         /* regulatory txpower limits ... reg_limit values are in half-dBm,
2016          *   max_power_avg values are in dBm, convert * 2 */
2017         if (is_fat)
2018                 reg_limit = ch_info->fat_max_power_avg * 2;
2019         else
2020                 reg_limit = ch_info->max_power_avg * 2;
2021
2022         if ((reg_limit < IWL_TX_POWER_REGULATORY_MIN) ||
2023             (reg_limit > IWL_TX_POWER_REGULATORY_MAX)) {
2024                 if (band)
2025                         reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_24;
2026                 else
2027                         reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_52;
2028         }
2029
2030         /* Interpolate txpower calibration values for this channel,
2031          *   based on factory calibration tests on spaced channels. */
2032         iwl4965_interpolate_chan(priv, channel, &ch_eeprom_info);
2033
2034         /* calculate tx gain adjustment based on power supply voltage */
2035         voltage = priv->eeprom.calib_info.voltage;
2036         init_voltage = (s32)le32_to_cpu(priv->card_alive_init.voltage);
2037         voltage_compensation =
2038             iwl4965_get_voltage_compensation(voltage, init_voltage);
2039
2040         IWL_DEBUG_TXPOWER("curr volt %d eeprom volt %d volt comp %d\n",
2041                           init_voltage,
2042                           voltage, voltage_compensation);
2043
2044         /* get current temperature (Celsius) */
2045         current_temp = max(priv->temperature, IWL_TX_POWER_TEMPERATURE_MIN);
2046         current_temp = min(priv->temperature, IWL_TX_POWER_TEMPERATURE_MAX);
2047         current_temp = KELVIN_TO_CELSIUS(current_temp);
2048
2049         /* select thermal txpower adjustment params, based on channel group
2050          *   (same frequency group used for mimo txatten adjustment) */
2051         degrees_per_05db_num =
2052             tx_power_cmp_tble[txatten_grp].degrees_per_05db_a;
2053         degrees_per_05db_denom =
2054             tx_power_cmp_tble[txatten_grp].degrees_per_05db_a_denom;
2055
2056         /* get per-chain txpower values from factory measurements */
2057         for (c = 0; c < 2; c++) {
2058                 measurement = &ch_eeprom_info.measurements[c][1];
2059
2060                 /* txgain adjustment (in half-dB steps) based on difference
2061                  *   between factory and current temperature */
2062                 factory_temp = measurement->temperature;
2063                 iwl4965_math_div_round((current_temp - factory_temp) *
2064                                        degrees_per_05db_denom,
2065                                        degrees_per_05db_num,
2066                                        &temperature_comp[c]);
2067
2068                 factory_gain_index[c] = measurement->gain_idx;
2069                 factory_actual_pwr[c] = measurement->actual_pow;
2070
2071                 IWL_DEBUG_TXPOWER("chain = %d\n", c);
2072                 IWL_DEBUG_TXPOWER("fctry tmp %d, "
2073                                   "curr tmp %d, comp %d steps\n",
2074                                   factory_temp, current_temp,
2075                                   temperature_comp[c]);
2076
2077                 IWL_DEBUG_TXPOWER("fctry idx %d, fctry pwr %d\n",
2078                                   factory_gain_index[c],
2079                                   factory_actual_pwr[c]);
2080         }
2081
2082         /* for each of 33 bit-rates (including 1 for CCK) */
2083         for (i = 0; i < POWER_TABLE_NUM_ENTRIES; i++) {
2084                 u8 is_mimo_rate;
2085                 union iwl4965_tx_power_dual_stream tx_power;
2086
2087                 /* for mimo, reduce each chain's txpower by half
2088                  * (3dB, 6 steps), so total output power is regulatory
2089                  * compliant. */
2090                 if (i & 0x8) {
2091                         current_regulatory = reg_limit -
2092                             IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION;
2093                         is_mimo_rate = 1;
2094                 } else {
2095                         current_regulatory = reg_limit;
2096                         is_mimo_rate = 0;
2097                 }
2098
2099                 /* find txpower limit, either hardware or regulatory */
2100                 power_limit = saturation_power - back_off_table[i];
2101                 if (power_limit > current_regulatory)
2102                         power_limit = current_regulatory;
2103
2104                 /* reduce user's txpower request if necessary
2105                  * for this rate on this channel */
2106                 target_power = user_target_power;
2107                 if (target_power > power_limit)
2108                         target_power = power_limit;
2109
2110                 IWL_DEBUG_TXPOWER("rate %d sat %d reg %d usr %d tgt %d\n",
2111                                   i, saturation_power - back_off_table[i],
2112                                   current_regulatory, user_target_power,
2113                                   target_power);
2114
2115                 /* for each of 2 Tx chains (radio transmitters) */
2116                 for (c = 0; c < 2; c++) {
2117                         s32 atten_value;
2118
2119                         if (is_mimo_rate)
2120                                 atten_value =
2121                                     (s32)le32_to_cpu(priv->card_alive_init.
2122                                     tx_atten[txatten_grp][c]);
2123                         else
2124                                 atten_value = 0;
2125
2126                         /* calculate index; higher index means lower txpower */
2127                         power_index = (u8) (factory_gain_index[c] -
2128                                             (target_power -
2129                                              factory_actual_pwr[c]) -
2130                                             temperature_comp[c] -
2131                                             voltage_compensation +
2132                                             atten_value);
2133
2134 /*                      IWL_DEBUG_TXPOWER("calculated txpower index %d\n",
2135                                                 power_index); */
2136
2137                         if (power_index < get_min_power_index(i, band))
2138                                 power_index = get_min_power_index(i, band);
2139
2140                         /* adjust 5 GHz index to support negative indexes */
2141                         if (!band)
2142                                 power_index += 9;
2143
2144                         /* CCK, rate 32, reduce txpower for CCK */
2145                         if (i == POWER_TABLE_CCK_ENTRY)
2146                                 power_index +=
2147                                     IWL_TX_POWER_CCK_COMPENSATION_C_STEP;
2148
2149                         /* stay within the table! */
2150                         if (power_index > 107) {
2151                                 IWL_WARNING("txpower index %d > 107\n",
2152                                             power_index);
2153                                 power_index = 107;
2154                         }
2155                         if (power_index < 0) {
2156                                 IWL_WARNING("txpower index %d < 0\n",
2157                                             power_index);
2158                                 power_index = 0;
2159                         }
2160
2161                         /* fill txpower command for this rate/chain */
2162                         tx_power.s.radio_tx_gain[c] =
2163                                 gain_table[band][power_index].radio;
2164                         tx_power.s.dsp_predis_atten[c] =
2165                                 gain_table[band][power_index].dsp;
2166
2167                         IWL_DEBUG_TXPOWER("chain %d mimo %d index %d "
2168                                           "gain 0x%02x dsp %d\n",
2169                                           c, atten_value, power_index,
2170                                         tx_power.s.radio_tx_gain[c],
2171                                         tx_power.s.dsp_predis_atten[c]);
2172                 }/* for each chain */
2173
2174                 tx_power_tbl->power_tbl[i].dw = cpu_to_le32(tx_power.dw);
2175
2176         }/* for each rate */
2177
2178         return 0;
2179 }
2180
2181 /**
2182  * iwl4965_hw_reg_send_txpower - Configure the TXPOWER level user limit
2183  *
2184  * Uses the active RXON for channel, band, and characteristics (fat, high)
2185  * The power limit is taken from priv->user_txpower_limit.
2186  */
2187 int iwl4965_hw_reg_send_txpower(struct iwl_priv *priv)
2188 {
2189         struct iwl4965_txpowertable_cmd cmd = { 0 };
2190         int ret;
2191         u8 band = 0;
2192         u8 is_fat = 0;
2193         u8 ctrl_chan_high = 0;
2194
2195         if (test_bit(STATUS_SCANNING, &priv->status)) {
2196                 /* If this gets hit a lot, switch it to a BUG() and catch
2197                  * the stack trace to find out who is calling this during
2198                  * a scan. */
2199                 IWL_WARNING("TX Power requested while scanning!\n");
2200                 return -EAGAIN;
2201         }
2202
2203         band = priv->band == IEEE80211_BAND_2GHZ;
2204
2205         is_fat =  is_fat_channel(priv->active_rxon.flags);
2206
2207         if (is_fat &&
2208             (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
2209                 ctrl_chan_high = 1;
2210
2211         cmd.band = band;
2212         cmd.channel = priv->active_rxon.channel;
2213
2214         ret = iwl4965_fill_txpower_tbl(priv, band,
2215                                 le16_to_cpu(priv->active_rxon.channel),
2216                                 is_fat, ctrl_chan_high, &cmd.tx_power);
2217         if (ret)
2218                 goto out;
2219
2220         ret = iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, sizeof(cmd), &cmd);
2221
2222 out:
2223         return ret;
2224 }
2225
2226 static int iwl4965_send_rxon_assoc(struct iwl_priv *priv)
2227 {
2228         int ret = 0;
2229         struct iwl4965_rxon_assoc_cmd rxon_assoc;
2230         const struct iwl4965_rxon_cmd *rxon1 = &priv->staging_rxon;
2231         const struct iwl4965_rxon_cmd *rxon2 = &priv->active_rxon;
2232
2233         if ((rxon1->flags == rxon2->flags) &&
2234             (rxon1->filter_flags == rxon2->filter_flags) &&
2235             (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
2236             (rxon1->ofdm_ht_single_stream_basic_rates ==
2237              rxon2->ofdm_ht_single_stream_basic_rates) &&
2238             (rxon1->ofdm_ht_dual_stream_basic_rates ==
2239              rxon2->ofdm_ht_dual_stream_basic_rates) &&
2240             (rxon1->rx_chain == rxon2->rx_chain) &&
2241             (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
2242                 IWL_DEBUG_INFO("Using current RXON_ASSOC.  Not resending.\n");
2243                 return 0;
2244         }
2245
2246         rxon_assoc.flags = priv->staging_rxon.flags;
2247         rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
2248         rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
2249         rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
2250         rxon_assoc.reserved = 0;
2251         rxon_assoc.ofdm_ht_single_stream_basic_rates =
2252             priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
2253         rxon_assoc.ofdm_ht_dual_stream_basic_rates =
2254             priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
2255         rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
2256
2257         ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
2258                                      sizeof(rxon_assoc), &rxon_assoc, NULL);
2259         if (ret)
2260                 return ret;
2261
2262         return ret;
2263 }
2264
2265
2266 int iwl4965_hw_channel_switch(struct iwl_priv *priv, u16 channel)
2267 {
2268         int rc;
2269         u8 band = 0;
2270         u8 is_fat = 0;
2271         u8 ctrl_chan_high = 0;
2272         struct iwl4965_channel_switch_cmd cmd = { 0 };
2273         const struct iwl_channel_info *ch_info;
2274
2275         band = priv->band == IEEE80211_BAND_2GHZ;
2276
2277         ch_info = iwl_get_channel_info(priv, priv->band, channel);
2278
2279         is_fat = is_fat_channel(priv->staging_rxon.flags);
2280
2281         if (is_fat &&
2282             (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
2283                 ctrl_chan_high = 1;
2284
2285         cmd.band = band;
2286         cmd.expect_beacon = 0;
2287         cmd.channel = cpu_to_le16(channel);
2288         cmd.rxon_flags = priv->active_rxon.flags;
2289         cmd.rxon_filter_flags = priv->active_rxon.filter_flags;
2290         cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
2291         if (ch_info)
2292                 cmd.expect_beacon = is_channel_radar(ch_info);
2293         else
2294                 cmd.expect_beacon = 1;
2295
2296         rc = iwl4965_fill_txpower_tbl(priv, band, channel, is_fat,
2297                                       ctrl_chan_high, &cmd.tx_power);
2298         if (rc) {
2299                 IWL_DEBUG_11H("error:%d  fill txpower_tbl\n", rc);
2300                 return rc;
2301         }
2302
2303         rc = iwl_send_cmd_pdu(priv, REPLY_CHANNEL_SWITCH, sizeof(cmd), &cmd);
2304         return rc;
2305 }
2306
2307 #define RTS_HCCA_RETRY_LIMIT            3
2308 #define RTS_DFAULT_RETRY_LIMIT          60
2309
2310 void iwl4965_hw_build_tx_cmd_rate(struct iwl_priv *priv,
2311                               struct iwl_cmd *cmd,
2312                               struct ieee80211_tx_control *ctrl,
2313                               struct ieee80211_hdr *hdr, int sta_id,
2314                               int is_hcca)
2315 {
2316         struct iwl4965_tx_cmd *tx = &cmd->cmd.tx;
2317         u8 rts_retry_limit = 0;
2318         u8 data_retry_limit = 0;
2319         u16 fc = le16_to_cpu(hdr->frame_control);
2320         u8 rate_plcp;
2321         u16 rate_flags = 0;
2322         int rate_idx = min(ctrl->tx_rate->hw_value & 0xffff, IWL_RATE_COUNT - 1);
2323
2324         rate_plcp = iwl4965_rates[rate_idx].plcp;
2325
2326         rts_retry_limit = (is_hcca) ?
2327             RTS_HCCA_RETRY_LIMIT : RTS_DFAULT_RETRY_LIMIT;
2328
2329         if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
2330                 rate_flags |= RATE_MCS_CCK_MSK;
2331
2332
2333         if (ieee80211_is_probe_response(fc)) {
2334                 data_retry_limit = 3;
2335                 if (data_retry_limit < rts_retry_limit)
2336                         rts_retry_limit = data_retry_limit;
2337         } else
2338                 data_retry_limit = IWL_DEFAULT_TX_RETRY;
2339
2340         if (priv->data_retry_limit != -1)
2341                 data_retry_limit = priv->data_retry_limit;
2342
2343
2344         if (ieee80211_is_data(fc)) {
2345                 tx->initial_rate_index = 0;
2346                 tx->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
2347         } else {
2348                 switch (fc & IEEE80211_FCTL_STYPE) {
2349                 case IEEE80211_STYPE_AUTH:
2350                 case IEEE80211_STYPE_DEAUTH:
2351                 case IEEE80211_STYPE_ASSOC_REQ:
2352                 case IEEE80211_STYPE_REASSOC_REQ:
2353                         if (tx->tx_flags & TX_CMD_FLG_RTS_MSK) {
2354                                 tx->tx_flags &= ~TX_CMD_FLG_RTS_MSK;
2355                                 tx->tx_flags |= TX_CMD_FLG_CTS_MSK;
2356                         }
2357                         break;
2358                 default:
2359                         break;
2360                 }
2361
2362                 /* Alternate between antenna A and B for successive frames */
2363                 if (priv->use_ant_b_for_management_frame) {
2364                         priv->use_ant_b_for_management_frame = 0;
2365                         rate_flags |= RATE_MCS_ANT_B_MSK;
2366                 } else {
2367                         priv->use_ant_b_for_management_frame = 1;
2368                         rate_flags |= RATE_MCS_ANT_A_MSK;
2369                 }
2370         }
2371
2372         tx->rts_retry_limit = rts_retry_limit;
2373         tx->data_retry_limit = data_retry_limit;
2374         tx->rate_n_flags = iwl4965_hw_set_rate_n_flags(rate_plcp, rate_flags);
2375 }
2376
2377 int iwl4965_hw_get_rx_read(struct iwl_priv *priv)
2378 {
2379         struct iwl4965_shared *s = priv->shared_virt;
2380         return le32_to_cpu(s->rb_closed) & 0xFFF;
2381 }
2382
2383 int iwl4965_hw_get_temperature(struct iwl_priv *priv)
2384 {
2385         return priv->temperature;
2386 }
2387
2388 unsigned int iwl4965_hw_get_beacon_cmd(struct iwl_priv *priv,
2389                           struct iwl4965_frame *frame, u8 rate)
2390 {
2391         struct iwl4965_tx_beacon_cmd *tx_beacon_cmd;
2392         unsigned int frame_size;
2393
2394         tx_beacon_cmd = &frame->u.beacon;
2395         memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2396
2397         tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
2398         tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2399
2400         frame_size = iwl4965_fill_beacon_frame(priv,
2401                                 tx_beacon_cmd->frame,
2402                                 iwl4965_broadcast_addr,
2403                                 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2404
2405         BUG_ON(frame_size > MAX_MPDU_SIZE);
2406         tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2407
2408         if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
2409                 tx_beacon_cmd->tx.rate_n_flags =
2410                         iwl4965_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
2411         else
2412                 tx_beacon_cmd->tx.rate_n_flags =
2413                         iwl4965_hw_set_rate_n_flags(rate, 0);
2414
2415         tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2416                                 TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK);
2417         return (sizeof(*tx_beacon_cmd) + frame_size);
2418 }
2419
2420 /*
2421  * Tell 4965 where to find circular buffer of Tx Frame Descriptors for
2422  * given Tx queue, and enable the DMA channel used for that queue.
2423  *
2424  * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
2425  * channels supported in hardware.
2426  */
2427 int iwl4965_hw_tx_queue_init(struct iwl_priv *priv, struct iwl4965_tx_queue *txq)
2428 {
2429         int rc;
2430         unsigned long flags;
2431         int txq_id = txq->q.id;
2432
2433         spin_lock_irqsave(&priv->lock, flags);
2434         rc = iwl_grab_nic_access(priv);
2435         if (rc) {
2436                 spin_unlock_irqrestore(&priv->lock, flags);
2437                 return rc;
2438         }
2439
2440         /* Circular buffer (TFD queue in DRAM) physical base address */
2441         iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
2442                              txq->q.dma_addr >> 8);
2443
2444         /* Enable DMA channel, using same id as for TFD queue */
2445         iwl_write_direct32(
2446                 priv, IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
2447                 IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
2448                 IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL);
2449         iwl_release_nic_access(priv);
2450         spin_unlock_irqrestore(&priv->lock, flags);
2451
2452         return 0;
2453 }
2454
2455 int iwl4965_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, void *ptr,
2456                                  dma_addr_t addr, u16 len)
2457 {
2458         int index, is_odd;
2459         struct iwl4965_tfd_frame *tfd = ptr;
2460         u32 num_tbs = IWL_GET_BITS(*tfd, num_tbs);
2461
2462         /* Each TFD can point to a maximum 20 Tx buffers */
2463         if ((num_tbs >= MAX_NUM_OF_TBS) || (num_tbs < 0)) {
2464                 IWL_ERROR("Error can not send more than %d chunks\n",
2465                           MAX_NUM_OF_TBS);
2466                 return -EINVAL;
2467         }
2468
2469         index = num_tbs / 2;
2470         is_odd = num_tbs & 0x1;
2471
2472         if (!is_odd) {
2473                 tfd->pa[index].tb1_addr = cpu_to_le32(addr);
2474                 IWL_SET_BITS(tfd->pa[index], tb1_addr_hi,
2475                              iwl_get_dma_hi_address(addr));
2476                 IWL_SET_BITS(tfd->pa[index], tb1_len, len);
2477         } else {
2478                 IWL_SET_BITS(tfd->pa[index], tb2_addr_lo16,
2479                              (u32) (addr & 0xffff));
2480                 IWL_SET_BITS(tfd->pa[index], tb2_addr_hi20, addr >> 16);
2481                 IWL_SET_BITS(tfd->pa[index], tb2_len, len);
2482         }
2483
2484         IWL_SET_BITS(*tfd, num_tbs, num_tbs + 1);
2485
2486         return 0;
2487 }
2488
2489 static void iwl4965_hw_card_show_info(struct iwl_priv *priv)
2490 {
2491         u16 hw_version = priv->eeprom.board_revision_4965;
2492
2493         IWL_DEBUG_INFO("4965ABGN HW Version %u.%u.%u\n",
2494                        ((hw_version >> 8) & 0x0F),
2495                        ((hw_version >> 8) >> 4), (hw_version & 0x00FF));
2496
2497         IWL_DEBUG_INFO("4965ABGN PBA Number %.16s\n",
2498                        priv->eeprom.board_pba_number_4965);
2499 }
2500
2501 #define IWL_TX_CRC_SIZE         4
2502 #define IWL_TX_DELIMITER_SIZE   4
2503
2504 /**
2505  * iwl4965_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
2506  */
2507 static void iwl4965_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
2508                                             struct iwl4965_tx_queue *txq,
2509                                             u16 byte_cnt)
2510 {
2511         int len;
2512         int txq_id = txq->q.id;
2513         struct iwl4965_shared *shared_data = priv->shared_virt;
2514
2515         len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
2516
2517         /* Set up byte count within first 256 entries */
2518         IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
2519                        tfd_offset[txq->q.write_ptr], byte_cnt, len);
2520
2521         /* If within first 64 entries, duplicate at end */
2522         if (txq->q.write_ptr < IWL4965_MAX_WIN_SIZE)
2523                 IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
2524                         tfd_offset[IWL4965_QUEUE_SIZE + txq->q.write_ptr],
2525                         byte_cnt, len);
2526 }
2527
2528 /**
2529  * iwl4965_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
2530  *
2531  * Selects how many and which Rx receivers/antennas/chains to use.
2532  * This should not be used for scan command ... it puts data in wrong place.
2533  */
2534 void iwl4965_set_rxon_chain(struct iwl_priv *priv)
2535 {
2536         u8 is_single = is_single_stream(priv);
2537         u8 idle_state, rx_state;
2538
2539         priv->staging_rxon.rx_chain = 0;
2540         rx_state = idle_state = 3;
2541
2542         /* Tell uCode which antennas are actually connected.
2543          * Before first association, we assume all antennas are connected.
2544          * Just after first association, iwl_chain_noise_calibration()
2545          *    checks which antennas actually *are* connected. */
2546         priv->staging_rxon.rx_chain |=
2547             cpu_to_le16(priv->valid_antenna << RXON_RX_CHAIN_VALID_POS);
2548
2549         /* How many receivers should we use? */
2550         iwl4965_get_rx_chain_counter(priv, &idle_state, &rx_state);
2551         priv->staging_rxon.rx_chain |=
2552                 cpu_to_le16(rx_state << RXON_RX_CHAIN_MIMO_CNT_POS);
2553         priv->staging_rxon.rx_chain |=
2554                 cpu_to_le16(idle_state << RXON_RX_CHAIN_CNT_POS);
2555
2556         if (!is_single && (rx_state >= 2) &&
2557             !test_bit(STATUS_POWER_PMI, &priv->status))
2558                 priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
2559         else
2560                 priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
2561
2562         IWL_DEBUG_ASSOC("rx chain %X\n", priv->staging_rxon.rx_chain);
2563 }
2564
2565 /**
2566  * sign_extend - Sign extend a value using specified bit as sign-bit
2567  *
2568  * Example: sign_extend(9, 3) would return -7 as bit3 of 1001b is 1
2569  * and bit0..2 is 001b which when sign extended to 1111111111111001b is -7.
2570  *
2571  * @param oper value to sign extend
2572  * @param index 0 based bit index (0<=index<32) to sign bit
2573  */
2574 static s32 sign_extend(u32 oper, int index)
2575 {
2576         u8 shift = 31 - index;
2577
2578         return (s32)(oper << shift) >> shift;
2579 }
2580
2581 /**
2582  * iwl4965_get_temperature - return the calibrated temperature (in Kelvin)
2583  * @statistics: Provides the temperature reading from the uCode
2584  *
2585  * A return of <0 indicates bogus data in the statistics
2586  */
2587 int iwl4965_get_temperature(const struct iwl_priv *priv)
2588 {
2589         s32 temperature;
2590         s32 vt;
2591         s32 R1, R2, R3;
2592         u32 R4;
2593
2594         if (test_bit(STATUS_TEMPERATURE, &priv->status) &&
2595                 (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)) {
2596                 IWL_DEBUG_TEMP("Running FAT temperature calibration\n");
2597                 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
2598                 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
2599                 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
2600                 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[1]);
2601         } else {
2602                 IWL_DEBUG_TEMP("Running temperature calibration\n");
2603                 R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
2604                 R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
2605                 R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
2606                 R4 = le32_to_cpu(priv->card_alive_init.therm_r4[0]);
2607         }
2608
2609         /*
2610          * Temperature is only 23 bits, so sign extend out to 32.
2611          *
2612          * NOTE If we haven't received a statistics notification yet
2613          * with an updated temperature, use R4 provided to us in the
2614          * "initialize" ALIVE response.
2615          */
2616         if (!test_bit(STATUS_TEMPERATURE, &priv->status))
2617                 vt = sign_extend(R4, 23);
2618         else
2619                 vt = sign_extend(
2620                         le32_to_cpu(priv->statistics.general.temperature), 23);
2621
2622         IWL_DEBUG_TEMP("Calib values R[1-3]: %d %d %d R4: %d\n",
2623                        R1, R2, R3, vt);
2624
2625         if (R3 == R1) {
2626                 IWL_ERROR("Calibration conflict R1 == R3\n");
2627                 return -1;
2628         }
2629
2630         /* Calculate temperature in degrees Kelvin, adjust by 97%.
2631          * Add offset to center the adjustment around 0 degrees Centigrade. */
2632         temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2);
2633         temperature /= (R3 - R1);
2634         temperature = (temperature * 97) / 100 +
2635             TEMPERATURE_CALIB_KELVIN_OFFSET;
2636
2637         IWL_DEBUG_TEMP("Calibrated temperature: %dK, %dC\n", temperature,
2638             KELVIN_TO_CELSIUS(temperature));
2639
2640         return temperature;
2641 }
2642
2643 /* Adjust Txpower only if temperature variance is greater than threshold. */
2644 #define IWL_TEMPERATURE_THRESHOLD   3
2645
2646 /**
2647  * iwl4965_is_temp_calib_needed - determines if new calibration is needed
2648  *
2649  * If the temperature changed has changed sufficiently, then a recalibration
2650  * is needed.
2651  *
2652  * Assumes caller will replace priv->last_temperature once calibration
2653  * executed.
2654  */
2655 static int iwl4965_is_temp_calib_needed(struct iwl_priv *priv)
2656 {
2657         int temp_diff;
2658
2659         if (!test_bit(STATUS_STATISTICS, &priv->status)) {
2660                 IWL_DEBUG_TEMP("Temperature not updated -- no statistics.\n");
2661                 return 0;
2662         }
2663
2664         temp_diff = priv->temperature - priv->last_temperature;
2665
2666         /* get absolute value */
2667         if (temp_diff < 0) {
2668                 IWL_DEBUG_POWER("Getting cooler, delta %d, \n", temp_diff);
2669                 temp_diff = -temp_diff;
2670         } else if (temp_diff == 0)
2671                 IWL_DEBUG_POWER("Same temp, \n");
2672         else
2673                 IWL_DEBUG_POWER("Getting warmer, delta %d, \n", temp_diff);
2674
2675         if (temp_diff < IWL_TEMPERATURE_THRESHOLD) {
2676                 IWL_DEBUG_POWER("Thermal txpower calib not needed\n");
2677                 return 0;
2678         }
2679
2680         IWL_DEBUG_POWER("Thermal txpower calib needed\n");
2681
2682         return 1;
2683 }
2684
2685 /* Calculate noise level, based on measurements during network silence just
2686  *   before arriving beacon.  This measurement can be done only if we know
2687  *   exactly when to expect beacons, therefore only when we're associated. */
2688 static void iwl4965_rx_calc_noise(struct iwl_priv *priv)
2689 {
2690         struct statistics_rx_non_phy *rx_info
2691                                 = &(priv->statistics.rx.general);
2692         int num_active_rx = 0;
2693         int total_silence = 0;
2694         int bcn_silence_a =
2695                 le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
2696         int bcn_silence_b =
2697                 le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
2698         int bcn_silence_c =
2699                 le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
2700
2701         if (bcn_silence_a) {
2702                 total_silence += bcn_silence_a;
2703                 num_active_rx++;
2704         }
2705         if (bcn_silence_b) {
2706                 total_silence += bcn_silence_b;
2707                 num_active_rx++;
2708         }
2709         if (bcn_silence_c) {
2710                 total_silence += bcn_silence_c;
2711                 num_active_rx++;
2712         }
2713
2714         /* Average among active antennas */
2715         if (num_active_rx)
2716                 priv->last_rx_noise = (total_silence / num_active_rx) - 107;
2717         else
2718                 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
2719
2720         IWL_DEBUG_CALIB("inband silence a %u, b %u, c %u, dBm %d\n",
2721                         bcn_silence_a, bcn_silence_b, bcn_silence_c,
2722                         priv->last_rx_noise);
2723 }
2724
2725 void iwl4965_hw_rx_statistics(struct iwl_priv *priv, struct iwl4965_rx_mem_buffer *rxb)
2726 {
2727         struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
2728         int change;
2729         s32 temp;
2730
2731         IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
2732                      (int)sizeof(priv->statistics), pkt->len);
2733
2734         change = ((priv->statistics.general.temperature !=
2735                    pkt->u.stats.general.temperature) ||
2736                   ((priv->statistics.flag &
2737                     STATISTICS_REPLY_FLG_FAT_MODE_MSK) !=
2738                    (pkt->u.stats.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)));
2739
2740         memcpy(&priv->statistics, &pkt->u.stats, sizeof(priv->statistics));
2741
2742         set_bit(STATUS_STATISTICS, &priv->status);
2743
2744         /* Reschedule the statistics timer to occur in
2745          * REG_RECALIB_PERIOD seconds to ensure we get a
2746          * thermal update even if the uCode doesn't give
2747          * us one */
2748         mod_timer(&priv->statistics_periodic, jiffies +
2749                   msecs_to_jiffies(REG_RECALIB_PERIOD * 1000));
2750
2751         if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
2752             (pkt->hdr.cmd == STATISTICS_NOTIFICATION)) {
2753                 iwl4965_rx_calc_noise(priv);
2754 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
2755                 queue_work(priv->workqueue, &priv->sensitivity_work);
2756 #endif
2757         }
2758
2759         iwl_leds_background(priv);
2760
2761         /* If the hardware hasn't reported a change in
2762          * temperature then don't bother computing a
2763          * calibrated temperature value */
2764         if (!change)
2765                 return;
2766
2767         temp = iwl4965_get_temperature(priv);
2768         if (temp < 0)
2769                 return;
2770
2771         if (priv->temperature != temp) {
2772                 if (priv->temperature)
2773                         IWL_DEBUG_TEMP("Temperature changed "
2774                                        "from %dC to %dC\n",
2775                                        KELVIN_TO_CELSIUS(priv->temperature),
2776                                        KELVIN_TO_CELSIUS(temp));
2777                 else
2778                         IWL_DEBUG_TEMP("Temperature "
2779                                        "initialized to %dC\n",
2780                                        KELVIN_TO_CELSIUS(temp));
2781         }
2782
2783         priv->temperature = temp;
2784         set_bit(STATUS_TEMPERATURE, &priv->status);
2785
2786         if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
2787                      iwl4965_is_temp_calib_needed(priv))
2788                 queue_work(priv->workqueue, &priv->txpower_work);
2789 }
2790
2791 static void iwl4965_add_radiotap(struct iwl_priv *priv,
2792                                  struct sk_buff *skb,
2793                                  struct iwl4965_rx_phy_res *rx_start,
2794                                  struct ieee80211_rx_status *stats,
2795                                  u32 ampdu_status)
2796 {
2797         s8 signal = stats->ssi;
2798         s8 noise = 0;
2799         int rate = stats->rate_idx;
2800         u64 tsf = stats->mactime;
2801         __le16 antenna;
2802         __le16 phy_flags_hw = rx_start->phy_flags;
2803         struct iwl4965_rt_rx_hdr {
2804                 struct ieee80211_radiotap_header rt_hdr;
2805                 __le64 rt_tsf;          /* TSF */
2806                 u8 rt_flags;            /* radiotap packet flags */
2807                 u8 rt_rate;             /* rate in 500kb/s */
2808                 __le16 rt_channelMHz;   /* channel in MHz */
2809                 __le16 rt_chbitmask;    /* channel bitfield */
2810                 s8 rt_dbmsignal;        /* signal in dBm, kluged to signed */
2811                 s8 rt_dbmnoise;
2812                 u8 rt_antenna;          /* antenna number */
2813         } __attribute__ ((packed)) *iwl4965_rt;
2814
2815         /* TODO: We won't have enough headroom for HT frames. Fix it later. */
2816         if (skb_headroom(skb) < sizeof(*iwl4965_rt)) {
2817                 if (net_ratelimit())
2818                         printk(KERN_ERR "not enough headroom [%d] for "
2819                                "radiotap head [%zd]\n",
2820                                skb_headroom(skb), sizeof(*iwl4965_rt));
2821                 return;
2822         }
2823
2824         /* put radiotap header in front of 802.11 header and data */
2825         iwl4965_rt = (void *)skb_push(skb, sizeof(*iwl4965_rt));
2826
2827         /* initialise radiotap header */
2828         iwl4965_rt->rt_hdr.it_version = PKTHDR_RADIOTAP_VERSION;
2829         iwl4965_rt->rt_hdr.it_pad = 0;
2830
2831         /* total header + data */
2832         put_unaligned(cpu_to_le16(sizeof(*iwl4965_rt)),
2833                       &iwl4965_rt->rt_hdr.it_len);
2834
2835         /* Indicate all the fields we add to the radiotap header */
2836         put_unaligned(cpu_to_le32((1 << IEEE80211_RADIOTAP_TSFT) |
2837                                   (1 << IEEE80211_RADIOTAP_FLAGS) |
2838                                   (1 << IEEE80211_RADIOTAP_RATE) |
2839                                   (1 << IEEE80211_RADIOTAP_CHANNEL) |
2840                                   (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) |
2841                                   (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) |
2842                                   (1 << IEEE80211_RADIOTAP_ANTENNA)),
2843                       &iwl4965_rt->rt_hdr.it_present);
2844
2845         /* Zero the flags, we'll add to them as we go */
2846         iwl4965_rt->rt_flags = 0;
2847
2848         put_unaligned(cpu_to_le64(tsf), &iwl4965_rt->rt_tsf);
2849
2850         iwl4965_rt->rt_dbmsignal = signal;
2851         iwl4965_rt->rt_dbmnoise = noise;
2852
2853         /* Convert the channel frequency and set the flags */
2854         put_unaligned(cpu_to_le16(stats->freq), &iwl4965_rt->rt_channelMHz);
2855         if (!(phy_flags_hw & RX_RES_PHY_FLAGS_BAND_24_MSK))
2856                 put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
2857                                           IEEE80211_CHAN_5GHZ),
2858                               &iwl4965_rt->rt_chbitmask);
2859         else if (phy_flags_hw & RX_RES_PHY_FLAGS_MOD_CCK_MSK)
2860                 put_unaligned(cpu_to_le16(IEEE80211_CHAN_CCK |
2861                                           IEEE80211_CHAN_2GHZ),
2862                               &iwl4965_rt->rt_chbitmask);
2863         else    /* 802.11g */
2864                 put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
2865                                           IEEE80211_CHAN_2GHZ),
2866                               &iwl4965_rt->rt_chbitmask);
2867
2868         if (rate == -1)
2869                 iwl4965_rt->rt_rate = 0;
2870         else
2871                 iwl4965_rt->rt_rate = iwl4965_rates[rate].ieee;
2872
2873         /*
2874          * "antenna number"
2875          *
2876          * It seems that the antenna field in the phy flags value
2877          * is actually a bitfield. This is undefined by radiotap,
2878          * it wants an actual antenna number but I always get "7"
2879          * for most legacy frames I receive indicating that the
2880          * same frame was received on all three RX chains.
2881          *
2882          * I think this field should be removed in favour of a
2883          * new 802.11n radiotap field "RX chains" that is defined
2884          * as a bitmask.
2885          */
2886         antenna = phy_flags_hw & RX_RES_PHY_FLAGS_ANTENNA_MSK;
2887         iwl4965_rt->rt_antenna = le16_to_cpu(antenna) >> 4;
2888
2889         /* set the preamble flag if appropriate */
2890         if (phy_flags_hw & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
2891                 iwl4965_rt->rt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
2892
2893         stats->flag |= RX_FLAG_RADIOTAP;
2894 }
2895
2896 static void iwl_update_rx_stats(struct iwl_priv *priv, u16 fc, u16 len)
2897 {
2898         /* 0 - mgmt, 1 - cnt, 2 - data */
2899         int idx = (fc & IEEE80211_FCTL_FTYPE) >> 2;
2900         priv->rx_stats[idx].cnt++;
2901         priv->rx_stats[idx].bytes += len;
2902 }
2903
2904 static u32 iwl4965_translate_rx_status(u32 decrypt_in)
2905 {
2906         u32 decrypt_out = 0;
2907
2908         if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
2909                                         RX_RES_STATUS_STATION_FOUND)
2910                 decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
2911                                 RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
2912
2913         decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
2914
2915         /* packet was not encrypted */
2916         if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
2917                                         RX_RES_STATUS_SEC_TYPE_NONE)
2918                 return decrypt_out;
2919
2920         /* packet was encrypted with unknown alg */
2921         if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
2922                                         RX_RES_STATUS_SEC_TYPE_ERR)
2923                 return decrypt_out;
2924
2925         /* decryption was not done in HW */
2926         if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
2927                                         RX_MPDU_RES_STATUS_DEC_DONE_MSK)
2928                 return decrypt_out;
2929
2930         switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
2931
2932         case RX_RES_STATUS_SEC_TYPE_CCMP:
2933                 /* alg is CCM: check MIC only */
2934                 if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
2935                         /* Bad MIC */
2936                         decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
2937                 else
2938                         decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
2939
2940                 break;
2941
2942         case RX_RES_STATUS_SEC_TYPE_TKIP:
2943                 if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
2944                         /* Bad TTAK */
2945                         decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
2946                         break;
2947                 }
2948                 /* fall through if TTAK OK */
2949         default:
2950                 if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
2951                         decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
2952                 else
2953                         decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
2954                 break;
2955         };
2956
2957         IWL_DEBUG_RX("decrypt_in:0x%x  decrypt_out = 0x%x\n",
2958                                         decrypt_in, decrypt_out);
2959
2960         return decrypt_out;
2961 }
2962
2963 static void iwl4965_handle_data_packet(struct iwl_priv *priv, int is_data,
2964                                        int include_phy,
2965                                        struct iwl4965_rx_mem_buffer *rxb,
2966                                        struct ieee80211_rx_status *stats)
2967 {
2968         struct iwl4965_rx_packet *pkt = (struct iwl4965_rx_packet *)rxb->skb->data;
2969         struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
2970             (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) : NULL;
2971         struct ieee80211_hdr *hdr;
2972         u16 len;
2973         __le32 *rx_end;
2974         unsigned int skblen;
2975         u32 ampdu_status;
2976         u32 ampdu_status_legacy;
2977
2978         if (!include_phy && priv->last_phy_res[0])
2979                 rx_start = (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
2980
2981         if (!rx_start) {
2982                 IWL_ERROR("MPDU frame without a PHY data\n");
2983                 return;
2984         }
2985         if (include_phy) {
2986                 hdr = (struct ieee80211_hdr *)((u8 *) & rx_start[1] +
2987                                                rx_start->cfg_phy_cnt);
2988
2989                 len = le16_to_cpu(rx_start->byte_count);
2990
2991                 rx_end = (__le32 *) ((u8 *) & pkt->u.raw[0] +
2992                                   sizeof(struct iwl4965_rx_phy_res) +
2993                                   rx_start->cfg_phy_cnt + len);
2994
2995         } else {
2996                 struct iwl4965_rx_mpdu_res_start *amsdu =
2997                     (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
2998
2999                 hdr = (struct ieee80211_hdr *)(pkt->u.raw +
3000                                sizeof(struct iwl4965_rx_mpdu_res_start));
3001                 len =  le16_to_cpu(amsdu->byte_count);
3002                 rx_start->byte_count = amsdu->byte_count;
3003                 rx_end = (__le32 *) (((u8 *) hdr) + len);
3004         }
3005         if (len > priv->hw_params.max_pkt_size || len < 16) {
3006                 IWL_WARNING("byte count out of range [16,4K] : %d\n", len);
3007                 return;
3008         }
3009
3010         ampdu_status = le32_to_cpu(*rx_end);
3011         skblen = ((u8 *) rx_end - (u8 *) & pkt->u.raw[0]) + sizeof(u32);
3012
3013         if (!include_phy) {
3014                 /* New status scheme, need to translate */
3015                 ampdu_status_legacy = ampdu_status;
3016                 ampdu_status = iwl4965_translate_rx_status(ampdu_status);
3017         }
3018
3019         /* start from MAC */
3020         skb_reserve(rxb->skb, (void *)hdr - (void *)pkt);
3021         skb_put(rxb->skb, len); /* end where data ends */
3022
3023         /* We only process data packets if the interface is open */
3024         if (unlikely(!priv->is_open)) {
3025                 IWL_DEBUG_DROP_LIMIT
3026                     ("Dropping packet while interface is not open.\n");
3027                 return;
3028         }
3029
3030         stats->flag = 0;
3031         hdr = (struct ieee80211_hdr *)rxb->skb->data;
3032
3033         if (!priv->cfg->mod_params->sw_crypto)
3034                 iwl4965_set_decrypted_flag(priv, rxb->skb, ampdu_status, stats);
3035
3036         if (priv->add_radiotap)
3037                 iwl4965_add_radiotap(priv, rxb->skb, rx_start, stats, ampdu_status);
3038
3039         iwl_update_rx_stats(priv, le16_to_cpu(hdr->frame_control), len);
3040         ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
3041         priv->alloc_rxb_skb--;
3042         rxb->skb = NULL;
3043 }
3044
3045 /* Calc max signal level (dBm) among 3 possible receivers */
3046 static int iwl4965_calc_rssi(struct iwl4965_rx_phy_res *rx_resp)
3047 {
3048         /* data from PHY/DSP regarding signal strength, etc.,
3049          *   contents are always there, not configurable by host.  */
3050         struct iwl4965_rx_non_cfg_phy *ncphy =
3051             (struct iwl4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy;
3052         u32 agc = (le16_to_cpu(ncphy->agc_info) & IWL_AGC_DB_MASK)
3053                         >> IWL_AGC_DB_POS;
3054
3055         u32 valid_antennae =
3056             (le16_to_cpu(rx_resp->phy_flags) & RX_PHY_FLAGS_ANTENNAE_MASK)
3057                         >> RX_PHY_FLAGS_ANTENNAE_OFFSET;
3058         u8 max_rssi = 0;
3059         u32 i;
3060
3061         /* Find max rssi among 3 possible receivers.
3062          * These values are measured by the digital signal processor (DSP).
3063          * They should stay fairly constant even as the signal strength varies,
3064          *   if the radio's automatic gain control (AGC) is working right.
3065          * AGC value (see below) will provide the "interesting" info. */
3066         for (i = 0; i < 3; i++)
3067                 if (valid_antennae & (1 << i))
3068                         max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
3069
3070         IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
3071                 ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
3072                 max_rssi, agc);
3073
3074         /* dBm = max_rssi dB - agc dB - constant.
3075          * Higher AGC (higher radio gain) means lower signal. */
3076         return (max_rssi - agc - IWL_RSSI_OFFSET);
3077 }
3078
3079 #ifdef CONFIG_IWL4965_HT
3080
3081 void iwl4965_init_ht_hw_capab(struct iwl_priv *priv,
3082                               struct ieee80211_ht_info *ht_info,
3083                               enum ieee80211_band band)
3084 {
3085         ht_info->cap = 0;
3086         memset(ht_info->supp_mcs_set, 0, 16);
3087
3088         ht_info->ht_supported = 1;
3089
3090         if (band == IEEE80211_BAND_5GHZ) {
3091                 ht_info->cap |= (u16)IEEE80211_HT_CAP_SUP_WIDTH;
3092                 ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_40;
3093                 ht_info->supp_mcs_set[4] = 0x01;
3094         }
3095         ht_info->cap |= (u16)IEEE80211_HT_CAP_GRN_FLD;
3096         ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_20;
3097         ht_info->cap |= (u16)(IEEE80211_HT_CAP_MIMO_PS &
3098                              (IWL_MIMO_PS_NONE << 2));
3099
3100         if (priv->cfg->mod_params->amsdu_size_8K)
3101                 ht_info->cap |= (u16)IEEE80211_HT_CAP_MAX_AMSDU;
3102
3103         ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
3104         ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
3105
3106         ht_info->supp_mcs_set[0] = 0xFF;
3107         ht_info->supp_mcs_set[1] = 0xFF;
3108 }
3109 #endif /* CONFIG_IWL4965_HT */
3110
3111 static void iwl4965_sta_modify_ps_wake(struct iwl_priv *priv, int sta_id)
3112 {
3113         unsigned long flags;
3114
3115         spin_lock_irqsave(&priv->sta_lock, flags);
3116         priv->stations[sta_id].sta.station_flags &= ~STA_FLG_PWR_SAVE_MSK;
3117         priv->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK;
3118         priv->stations[sta_id].sta.sta.modify_mask = 0;
3119         priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3120         spin_unlock_irqrestore(&priv->sta_lock, flags);
3121
3122         iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
3123 }
3124
3125 static void iwl4965_update_ps_mode(struct iwl_priv *priv, u16 ps_bit, u8 *addr)
3126 {
3127         /* FIXME: need locking over ps_status ??? */
3128         u8 sta_id = iwl4965_hw_find_station(priv, addr);
3129
3130         if (sta_id != IWL_INVALID_STATION) {
3131                 u8 sta_awake = priv->stations[sta_id].
3132                                 ps_status == STA_PS_STATUS_WAKE;
3133
3134                 if (sta_awake && ps_bit)
3135                         priv->stations[sta_id].ps_status = STA_PS_STATUS_SLEEP;
3136                 else if (!sta_awake && !ps_bit) {
3137                         iwl4965_sta_modify_ps_wake(priv, sta_id);
3138                         priv->stations[sta_id].ps_status = STA_PS_STATUS_WAKE;
3139                 }
3140         }
3141 }
3142 #ifdef CONFIG_IWLWIFI_DEBUG
3143
3144 /**
3145  * iwl4965_dbg_report_frame - dump frame to syslog during debug sessions
3146  *
3147  * You may hack this function to show different aspects of received frames,
3148  * including selective frame dumps.
3149  * group100 parameter selects whether to show 1 out of 100 good frames.
3150  *
3151  * TODO:  This was originally written for 3945, need to audit for
3152  *        proper operation with 4965.
3153  */
3154 static void iwl4965_dbg_report_frame(struct iwl_priv *priv,
3155                       struct iwl4965_rx_packet *pkt,
3156                       struct ieee80211_hdr *header, int group100)
3157 {
3158         u32 to_us;
3159         u32 print_summary = 0;
3160         u32 print_dump = 0;     /* set to 1 to dump all frames' contents */
3161         u32 hundred = 0;
3162         u32 dataframe = 0;
3163         u16 fc;
3164         u16 seq_ctl;
3165         u16 channel;
3166         u16 phy_flags;
3167         int rate_sym;
3168         u16 length;
3169         u16 status;
3170         u16 bcn_tmr;
3171         u32 tsf_low;
3172         u64 tsf;
3173         u8 rssi;
3174         u8 agc;
3175         u16 sig_avg;
3176         u16 noise_diff;
3177         struct iwl4965_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
3178         struct iwl4965_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
3179         struct iwl4965_rx_frame_end *rx_end = IWL_RX_END(pkt);
3180         u8 *data = IWL_RX_DATA(pkt);
3181
3182         if (likely(!(iwl_debug_level & IWL_DL_RX)))
3183                 return;
3184
3185         /* MAC header */
3186         fc = le16_to_cpu(header->frame_control);
3187         seq_ctl = le16_to_cpu(header->seq_ctrl);
3188
3189         /* metadata */
3190         channel = le16_to_cpu(rx_hdr->channel);
3191         phy_flags = le16_to_cpu(rx_hdr->phy_flags);
3192         rate_sym = rx_hdr->rate;
3193         length = le16_to_cpu(rx_hdr->len);
3194
3195         /* end-of-frame status and timestamp */
3196         status = le32_to_cpu(rx_end->status);
3197         bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
3198         tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
3199         tsf = le64_to_cpu(rx_end->timestamp);
3200
3201         /* signal statistics */
3202         rssi = rx_stats->rssi;
3203         agc = rx_stats->agc;
3204         sig_avg = le16_to_cpu(rx_stats->sig_avg);
3205         noise_diff = le16_to_cpu(rx_stats->noise_diff);
3206
3207         to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
3208
3209         /* if data frame is to us and all is good,
3210          *   (optionally) print summary for only 1 out of every 100 */
3211         if (to_us && (fc & ~IEEE80211_FCTL_PROTECTED) ==
3212             (IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
3213                 dataframe = 1;
3214                 if (!group100)
3215                         print_summary = 1;      /* print each frame */
3216                 else if (priv->framecnt_to_us < 100) {
3217                         priv->framecnt_to_us++;
3218                         print_summary = 0;
3219                 } else {
3220                         priv->framecnt_to_us = 0;
3221                         print_summary = 1;
3222                         hundred = 1;
3223                 }
3224         } else {
3225                 /* print summary for all other frames */
3226                 print_summary = 1;
3227         }
3228
3229         if (print_summary) {
3230                 char *title;
3231                 int rate_idx;
3232                 u32 bitrate;
3233
3234                 if (hundred)
3235                         title = "100Frames";
3236                 else if (fc & IEEE80211_FCTL_RETRY)
3237                         title = "Retry";
3238                 else if (ieee80211_is_assoc_response(fc))
3239                         title = "AscRsp";
3240                 else if (ieee80211_is_reassoc_response(fc))
3241                         title = "RasRsp";
3242                 else if (ieee80211_is_probe_response(fc)) {
3243                         title = "PrbRsp";
3244                         print_dump = 1; /* dump frame contents */
3245                 } else if (ieee80211_is_beacon(fc)) {
3246                         title = "Beacon";
3247                         print_dump = 1; /* dump frame contents */
3248                 } else if (ieee80211_is_atim(fc))
3249                         title = "ATIM";
3250                 else if (ieee80211_is_auth(fc))
3251                         title = "Auth";
3252                 else if (ieee80211_is_deauth(fc))
3253                         title = "DeAuth";
3254                 else if (ieee80211_is_disassoc(fc))
3255                         title = "DisAssoc";
3256                 else
3257                         title = "Frame";
3258
3259                 rate_idx = iwl4965_hwrate_to_plcp_idx(rate_sym);
3260                 if (unlikely(rate_idx == -1))
3261                         bitrate = 0;
3262                 else
3263                         bitrate = iwl4965_rates[rate_idx].ieee / 2;
3264
3265                 /* print frame summary.
3266                  * MAC addresses show just the last byte (for brevity),
3267                  *    but you can hack it to show more, if you'd like to. */
3268                 if (dataframe)
3269                         IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
3270                                      "len=%u, rssi=%d, chnl=%d, rate=%u, \n",
3271                                      title, fc, header->addr1[5],
3272                                      length, rssi, channel, bitrate);
3273                 else {
3274                         /* src/dst addresses assume managed mode */
3275                         IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
3276                                      "src=0x%02x, rssi=%u, tim=%lu usec, "
3277                                      "phy=0x%02x, chnl=%d\n",
3278                                      title, fc, header->addr1[5],
3279                                      header->addr3[5], rssi,
3280                                      tsf_low - priv->scan_start_tsf,
3281                                      phy_flags, channel);
3282                 }
3283         }
3284         if (print_dump)
3285                 iwl_print_hex_dump(IWL_DL_RX, data, length);
3286 }
3287 #else
3288 static inline void iwl4965_dbg_report_frame(struct iwl_priv *priv,
3289                                             struct iwl4965_rx_packet *pkt,
3290                                             struct ieee80211_hdr *header,
3291                                             int group100)
3292 {
3293 }
3294 #endif
3295
3296
3297
3298 /* Called for REPLY_RX (legacy ABG frames), or
3299  * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
3300 static void iwl4965_rx_reply_rx(struct iwl_priv *priv,
3301                                 struct iwl4965_rx_mem_buffer *rxb)
3302 {
3303         struct ieee80211_hdr *header;
3304         struct ieee80211_rx_status rx_status;
3305         struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3306         /* Use phy data (Rx signal strength, etc.) contained within
3307          *   this rx packet for legacy frames,
3308          *   or phy data cached from REPLY_RX_PHY_CMD for HT frames. */
3309         int include_phy = (pkt->hdr.cmd == REPLY_RX);
3310         struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
3311                 (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) :
3312                 (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
3313         __le32 *rx_end;
3314         unsigned int len = 0;
3315         u16 fc;
3316         u8 network_packet;
3317
3318         rx_status.mactime = le64_to_cpu(rx_start->timestamp);
3319         rx_status.freq =
3320                 ieee80211_frequency_to_channel(le16_to_cpu(rx_start->channel));
3321         rx_status.band = (rx_start->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
3322                                 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
3323         rx_status.rate_idx =
3324                 iwl4965_hwrate_to_plcp_idx(le32_to_cpu(rx_start->rate_n_flags));
3325         if (rx_status.band == IEEE80211_BAND_5GHZ)
3326                 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
3327
3328         rx_status.antenna = 0;
3329         rx_status.flag = 0;
3330
3331         if ((unlikely(rx_start->cfg_phy_cnt > 20))) {
3332                 IWL_DEBUG_DROP("dsp size out of range [0,20]: %d/n",
3333                                 rx_start->cfg_phy_cnt);
3334                 return;
3335         }
3336
3337         if (!include_phy) {
3338                 if (priv->last_phy_res[0])
3339                         rx_start = (struct iwl4965_rx_phy_res *)
3340                                 &priv->last_phy_res[1];
3341                 else
3342                         rx_start = NULL;
3343         }
3344
3345         if (!rx_start) {
3346                 IWL_ERROR("MPDU frame without a PHY data\n");
3347                 return;
3348         }
3349
3350         if (include_phy) {
3351                 header = (struct ieee80211_hdr *)((u8 *) & rx_start[1]
3352                                                   + rx_start->cfg_phy_cnt);
3353
3354                 len = le16_to_cpu(rx_start->byte_count);
3355                 rx_end = (__le32 *)(pkt->u.raw + rx_start->cfg_phy_cnt +
3356                                   sizeof(struct iwl4965_rx_phy_res) + len);
3357         } else {
3358                 struct iwl4965_rx_mpdu_res_start *amsdu =
3359                         (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
3360
3361                 header = (void *)(pkt->u.raw +
3362                         sizeof(struct iwl4965_rx_mpdu_res_start));
3363                 len = le16_to_cpu(amsdu->byte_count);
3364                 rx_end = (__le32 *) (pkt->u.raw +
3365                         sizeof(struct iwl4965_rx_mpdu_res_start) + len);
3366         }
3367
3368         if (!(*rx_end & RX_RES_STATUS_NO_CRC32_ERROR) ||
3369             !(*rx_end & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
3370                 IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n",
3371                                 le32_to_cpu(*rx_end));
3372                 return;
3373         }
3374
3375         priv->ucode_beacon_time = le32_to_cpu(rx_start->beacon_time_stamp);
3376
3377         /* Find max signal strength (dBm) among 3 antenna/receiver chains */
3378         rx_status.ssi = iwl4965_calc_rssi(rx_start);
3379
3380         /* Meaningful noise values are available only from beacon statistics,
3381          *   which are gathered only when associated, and indicate noise
3382          *   only for the associated network channel ...
3383          * Ignore these noise values while scanning (other channels) */
3384         if (iwl_is_associated(priv) &&
3385             !test_bit(STATUS_SCANNING, &priv->status)) {
3386                 rx_status.noise = priv->last_rx_noise;
3387                 rx_status.signal = iwl4965_calc_sig_qual(rx_status.ssi,
3388                                                          rx_status.noise);
3389         } else {
3390                 rx_status.noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
3391                 rx_status.signal = iwl4965_calc_sig_qual(rx_status.ssi, 0);
3392         }
3393
3394         /* Reset beacon noise level if not associated. */
3395         if (!iwl_is_associated(priv))
3396                 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
3397
3398         /* Set "1" to report good data frames in groups of 100 */
3399         /* FIXME: need to optimze the call: */
3400         iwl4965_dbg_report_frame(priv, pkt, header, 1);
3401
3402         IWL_DEBUG_STATS_LIMIT("Rssi %d, noise %d, qual %d, TSF %llu\n",
3403                               rx_status.ssi, rx_status.noise, rx_status.signal,
3404                               (unsigned long long)rx_status.mactime);
3405
3406         network_packet = iwl4965_is_network_packet(priv, header);
3407         if (network_packet) {
3408                 priv->last_rx_rssi = rx_status.ssi;
3409                 priv->last_beacon_time =  priv->ucode_beacon_time;
3410                 priv->last_tsf = le64_to_cpu(rx_start->timestamp);
3411         }
3412
3413         fc = le16_to_cpu(header->frame_control);
3414         switch (fc & IEEE80211_FCTL_FTYPE) {
3415         case IEEE80211_FTYPE_MGMT:
3416                 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
3417                         iwl4965_update_ps_mode(priv, fc  & IEEE80211_FCTL_PM,
3418                                                 header->addr2);
3419                 iwl4965_handle_data_packet(priv, 0, include_phy, rxb, &rx_status);
3420                 break;
3421
3422         case IEEE80211_FTYPE_CTL:
3423 #ifdef CONFIG_IWL4965_HT
3424                 switch (fc & IEEE80211_FCTL_STYPE) {
3425                 case IEEE80211_STYPE_BACK_REQ:
3426                         IWL_DEBUG_HT("IEEE80211_STYPE_BACK_REQ arrived\n");
3427                         iwl4965_handle_data_packet(priv, 0, include_phy,
3428                                                 rxb, &rx_status);
3429                         break;
3430                 default:
3431                         break;
3432                 }
3433 #endif
3434                 break;
3435
3436         case IEEE80211_FTYPE_DATA: {
3437                 DECLARE_MAC_BUF(mac1);
3438                 DECLARE_MAC_BUF(mac2);
3439                 DECLARE_MAC_BUF(mac3);
3440
3441                 if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
3442                         iwl4965_update_ps_mode(priv, fc  & IEEE80211_FCTL_PM,
3443                                                 header->addr2);
3444
3445                 if (unlikely(!network_packet))
3446                         IWL_DEBUG_DROP("Dropping (non network): "
3447                                        "%s, %s, %s\n",
3448                                        print_mac(mac1, header->addr1),
3449                                        print_mac(mac2, header->addr2),
3450                                        print_mac(mac3, header->addr3));
3451                 else if (unlikely(iwl4965_is_duplicate_packet(priv, header)))
3452                         IWL_DEBUG_DROP("Dropping (dup): %s, %s, %s\n",
3453                                        print_mac(mac1, header->addr1),
3454                                        print_mac(mac2, header->addr2),
3455                                        print_mac(mac3, header->addr3));
3456                 else
3457                         iwl4965_handle_data_packet(priv, 1, include_phy, rxb,
3458                                                    &rx_status);
3459                 break;
3460         }
3461         default:
3462                 break;
3463
3464         }
3465 }
3466
3467 /* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
3468  * This will be used later in iwl4965_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
3469 static void iwl4965_rx_reply_rx_phy(struct iwl_priv *priv,
3470                                     struct iwl4965_rx_mem_buffer *rxb)
3471 {
3472         struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3473         priv->last_phy_res[0] = 1;
3474         memcpy(&priv->last_phy_res[1], &(pkt->u.raw[0]),
3475                sizeof(struct iwl4965_rx_phy_res));
3476 }
3477 static void iwl4965_rx_missed_beacon_notif(struct iwl_priv *priv,
3478                                            struct iwl4965_rx_mem_buffer *rxb)
3479
3480 {
3481 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
3482         struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3483         struct iwl4965_missed_beacon_notif *missed_beacon;
3484
3485         missed_beacon = &pkt->u.missed_beacon;
3486         if (le32_to_cpu(missed_beacon->consequtive_missed_beacons) > 5) {
3487                 IWL_DEBUG_CALIB("missed bcn cnsq %d totl %d rcd %d expctd %d\n",
3488                     le32_to_cpu(missed_beacon->consequtive_missed_beacons),
3489                     le32_to_cpu(missed_beacon->total_missed_becons),
3490                     le32_to_cpu(missed_beacon->num_recvd_beacons),
3491                     le32_to_cpu(missed_beacon->num_expected_beacons));
3492                 if (!test_bit(STATUS_SCANNING, &priv->status))
3493                         iwl_init_sensitivity(priv);
3494         }
3495 #endif /*CONFIG_IWL4965_RUN_TIME_CALIB*/
3496 }
3497 #ifdef CONFIG_IWL4965_HT
3498
3499 /**
3500  * iwl4965_sta_modify_enable_tid_tx - Enable Tx for this TID in station table
3501  */
3502 static void iwl4965_sta_modify_enable_tid_tx(struct iwl_priv *priv,
3503                                          int sta_id, int tid)
3504 {
3505         unsigned long flags;
3506
3507         /* Remove "disable" flag, to enable Tx for this TID */
3508         spin_lock_irqsave(&priv->sta_lock, flags);
3509         priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_TID_DISABLE_TX;
3510         priv->stations[sta_id].sta.tid_disable_tx &= cpu_to_le16(~(1 << tid));
3511         priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
3512         spin_unlock_irqrestore(&priv->sta_lock, flags);
3513
3514         iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
3515 }
3516
3517 /**
3518  * iwl4965_tx_status_reply_compressed_ba - Update tx status from block-ack
3519  *
3520  * Go through block-ack's bitmap of ACK'd frames, update driver's record of
3521  * ACK vs. not.  This gets sent to mac80211, then to rate scaling algo.
3522  */
3523 static int iwl4965_tx_status_reply_compressed_ba(struct iwl_priv *priv,
3524                                                  struct iwl4965_ht_agg *agg,
3525                                                  struct iwl4965_compressed_ba_resp*
3526                                                  ba_resp)
3527
3528 {
3529         int i, sh, ack;
3530         u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
3531         u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
3532         u64 bitmap;
3533         int successes = 0;
3534         struct ieee80211_tx_status *tx_status;
3535
3536         if (unlikely(!agg->wait_for_ba))  {
3537                 IWL_ERROR("Received BA when not expected\n");
3538                 return -EINVAL;
3539         }
3540
3541         /* Mark that the expected block-ack response arrived */
3542         agg->wait_for_ba = 0;
3543         IWL_DEBUG_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
3544
3545         /* Calculate shift to align block-ack bits with our Tx window bits */
3546         sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl>>4);
3547         if (sh < 0) /* tbw something is wrong with indices */
3548                 sh += 0x100;
3549
3550         /* don't use 64-bit values for now */
3551         bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
3552
3553         if (agg->frame_count > (64 - sh)) {
3554                 IWL_DEBUG_TX_REPLY("more frames than bitmap size");
3555                 return -1;
3556         }
3557
3558         /* check for success or failure according to the
3559          * transmitted bitmap and block-ack bitmap */
3560         bitmap &= agg->bitmap;
3561
3562         /* For each frame attempted in aggregation,
3563          * update driver's record of tx frame's status. */
3564         for (i = 0; i < agg->frame_count ; i++) {
3565                 ack = bitmap & (1 << i);
3566                 successes += !!ack;
3567                 IWL_DEBUG_TX_REPLY("%s ON i=%d idx=%d raw=%d\n",
3568                         ack? "ACK":"NACK", i, (agg->start_idx + i) & 0xff,
3569                         agg->start_idx + i);
3570         }
3571
3572         tx_status = &priv->txq[scd_flow].txb[agg->start_idx].status;
3573         tx_status->flags = IEEE80211_TX_STATUS_ACK;
3574         tx_status->flags |= IEEE80211_TX_STATUS_AMPDU;
3575         tx_status->ampdu_ack_map = successes;
3576         tx_status->ampdu_ack_len = agg->frame_count;
3577         iwl4965_hwrate_to_tx_control(priv, agg->rate_n_flags,
3578                                      &tx_status->control);
3579
3580         IWL_DEBUG_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap);
3581
3582         return 0;
3583 }
3584
3585 /**
3586  * iwl4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
3587  */
3588 static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv,
3589                                             u16 txq_id)
3590 {
3591         /* Simply stop the queue, but don't change any configuration;
3592          * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
3593         iwl_write_prph(priv,
3594                 IWL49_SCD_QUEUE_STATUS_BITS(txq_id),
3595                 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
3596                 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
3597 }
3598
3599 /**
3600  * txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID
3601  * priv->lock must be held by the caller
3602  */
3603 static int iwl4965_tx_queue_agg_disable(struct iwl_priv *priv, u16 txq_id,
3604                                         u16 ssn_idx, u8 tx_fifo)
3605 {
3606         int ret = 0;
3607
3608         if (IWL_BACK_QUEUE_FIRST_ID > txq_id) {
3609                 IWL_WARNING("queue number too small: %d, must be > %d\n",
3610                                 txq_id, IWL_BACK_QUEUE_FIRST_ID);
3611                 return -EINVAL;
3612         }
3613
3614         ret = iwl_grab_nic_access(priv);
3615         if (ret)
3616                 return ret;
3617
3618         iwl4965_tx_queue_stop_scheduler(priv, txq_id);
3619
3620         iwl_clear_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
3621
3622         priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
3623         priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
3624         /* supposes that ssn_idx is valid (!= 0xFFF) */
3625         iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
3626
3627         iwl_clear_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
3628         iwl4965_txq_ctx_deactivate(priv, txq_id);
3629         iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
3630
3631         iwl_release_nic_access(priv);
3632
3633         return 0;
3634 }
3635
3636 int iwl4965_check_empty_hw_queue(struct iwl_priv *priv, int sta_id,
3637                                          u8 tid, int txq_id)
3638 {
3639         struct iwl4965_queue *q = &priv->txq[txq_id].q;
3640         u8 *addr = priv->stations[sta_id].sta.sta.addr;
3641         struct iwl4965_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
3642
3643         switch (priv->stations[sta_id].tid[tid].agg.state) {
3644         case IWL_EMPTYING_HW_QUEUE_DELBA:
3645                 /* We are reclaiming the last packet of the */
3646                 /* aggregated HW queue */
3647                 if (txq_id  == tid_data->agg.txq_id &&
3648                     q->read_ptr == q->write_ptr) {
3649                         u16 ssn = SEQ_TO_SN(tid_data->seq_number);
3650                         int tx_fifo = default_tid_to_tx_fifo[tid];
3651                         IWL_DEBUG_HT("HW queue empty: continue DELBA flow\n");
3652                         iwl4965_tx_queue_agg_disable(priv, txq_id,
3653                                                      ssn, tx_fifo);
3654                         tid_data->agg.state = IWL_AGG_OFF;
3655                         ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, addr, tid);
3656                 }
3657                 break;
3658         case IWL_EMPTYING_HW_QUEUE_ADDBA:
3659                 /* We are reclaiming the last packet of the queue */
3660                 if (tid_data->tfds_in_queue == 0) {
3661                         IWL_DEBUG_HT("HW queue empty: continue ADDBA flow\n");
3662                         tid_data->agg.state = IWL_AGG_ON;
3663                         ieee80211_start_tx_ba_cb_irqsafe(priv->hw, addr, tid);
3664                 }
3665                 break;
3666         }
3667         return 0;
3668 }
3669
3670 /**
3671  * iwl4965_queue_dec_wrap - Decrement queue index, wrap back to end if needed
3672  * @index -- current index
3673  * @n_bd -- total number of entries in queue (s/b power of 2)
3674  */
3675 static inline int iwl4965_queue_dec_wrap(int index, int n_bd)
3676 {
3677         return (index == 0) ? n_bd - 1 : index - 1;
3678 }
3679
3680 /**
3681  * iwl4965_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
3682  *
3683  * Handles block-acknowledge notification from device, which reports success
3684  * of frames sent via aggregation.
3685  */
3686 static void iwl4965_rx_reply_compressed_ba(struct iwl_priv *priv,
3687                                            struct iwl4965_rx_mem_buffer *rxb)
3688 {
3689         struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
3690         struct iwl4965_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
3691         int index;
3692         struct iwl4965_tx_queue *txq = NULL;
3693         struct iwl4965_ht_agg *agg;
3694         DECLARE_MAC_BUF(mac);
3695
3696         /* "flow" corresponds to Tx queue */
3697         u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
3698
3699         /* "ssn" is start of block-ack Tx window, corresponds to index
3700          * (in Tx queue's circular buffer) of first TFD/frame in window */
3701         u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
3702
3703         if (scd_flow >= priv->hw_params.max_txq_num) {
3704                 IWL_ERROR("BUG_ON scd_flow is bigger than number of queues");
3705                 return;
3706         }
3707
3708         txq = &priv->txq[scd_flow];
3709         agg = &priv->stations[ba_resp->sta_id].tid[ba_resp->tid].agg;
3710
3711         /* Find index just before block-ack window */
3712         index = iwl4965_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
3713
3714         /* TODO: Need to get this copy more safely - now good for debug */
3715
3716         IWL_DEBUG_TX_REPLY("REPLY_COMPRESSED_BA [%d]Received from %s, "
3717                            "sta_id = %d\n",
3718                            agg->wait_for_ba,
3719                            print_mac(mac, (u8*) &ba_resp->sta_addr_lo32),
3720                            ba_resp->sta_id);
3721         IWL_DEBUG_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
3722                            "%d, scd_ssn = %d\n",
3723                            ba_resp->tid,
3724                            ba_resp->seq_ctl,
3725                            (unsigned long long)le64_to_cpu(ba_resp->bitmap),
3726                            ba_resp->scd_flow,
3727                            ba_resp->scd_ssn);
3728         IWL_DEBUG_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx \n",
3729                            agg->start_idx,
3730                            (unsigned long long)agg->bitmap);
3731
3732         /* Update driver's record of ACK vs. not for each frame in window */
3733         iwl4965_tx_status_reply_compressed_ba(priv, agg, ba_resp);
3734
3735         /* Release all TFDs before the SSN, i.e. all TFDs in front of
3736          * block-ack window (we assume that they've been successfully
3737          * transmitted ... if not, it's too late anyway). */
3738         if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
3739                 int freed = iwl4965_tx_queue_reclaim(priv, scd_flow, index);
3740                 priv->stations[ba_resp->sta_id].
3741                         tid[ba_resp->tid].tfds_in_queue -= freed;
3742                 if (iwl4965_queue_space(&txq->q) > txq->q.low_mark &&
3743                         priv->mac80211_registered &&
3744                         agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)
3745                         ieee80211_wake_queue(priv->hw, scd_flow);
3746                 iwl4965_check_empty_hw_queue(priv, ba_resp->sta_id,
3747                         ba_resp->tid, scd_flow);
3748         }
3749 }
3750
3751 /**
3752  * iwl4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
3753  */
3754 static int iwl4965_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
3755                                         u16 txq_id)
3756 {
3757         u32 tbl_dw_addr;
3758         u32 tbl_dw;
3759         u16 scd_q2ratid;
3760
3761         scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
3762
3763         tbl_dw_addr = priv->scd_base_addr +
3764                         SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
3765
3766         tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
3767
3768         if (txq_id & 0x1)
3769                 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
3770         else
3771                 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
3772
3773         iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
3774
3775         return 0;
3776 }
3777
3778
3779 /**
3780  * iwl4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
3781  *
3782  * NOTE:  txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID,
3783  *        i.e. it must be one of the higher queues used for aggregation
3784  */
3785 static int iwl4965_tx_queue_agg_enable(struct iwl_priv *priv, int txq_id,
3786                                        int tx_fifo, int sta_id, int tid,
3787                                        u16 ssn_idx)
3788 {
3789         unsigned long flags;
3790         int rc;
3791         u16 ra_tid;
3792
3793         if (IWL_BACK_QUEUE_FIRST_ID > txq_id)
3794                 IWL_WARNING("queue number too small: %d, must be > %d\n",
3795                         txq_id, IWL_BACK_QUEUE_FIRST_ID);
3796
3797         ra_tid = BUILD_RAxTID(sta_id, tid);
3798
3799         /* Modify device's station table to Tx this TID */
3800         iwl4965_sta_modify_enable_tid_tx(priv, sta_id, tid);
3801
3802         spin_lock_irqsave(&priv->lock, flags);
3803         rc = iwl_grab_nic_access(priv);
3804         if (rc) {
3805                 spin_unlock_irqrestore(&priv->lock, flags);
3806                 return rc;
3807         }
3808
3809         /* Stop this Tx queue before configuring it */
3810         iwl4965_tx_queue_stop_scheduler(priv, txq_id);
3811
3812         /* Map receiver-address / traffic-ID to this queue */
3813         iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
3814
3815         /* Set this queue as a chain-building queue */
3816         iwl_set_bits_prph(priv, IWL49_SCD_QUEUECHAIN_SEL, (1 << txq_id));
3817
3818         /* Place first TFD at index corresponding to start sequence number.
3819          * Assumes that ssn_idx is valid (!= 0xFFF) */
3820         priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
3821         priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
3822         iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
3823
3824         /* Set up Tx window size and frame limit for this queue */
3825         iwl_write_targ_mem(priv,
3826                         priv->scd_base_addr + SCD_CONTEXT_QUEUE_OFFSET(txq_id),
3827                         (SCD_WIN_SIZE << SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
3828                         SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
3829
3830         iwl_write_targ_mem(priv, priv->scd_base_addr +
3831                         SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
3832                         (SCD_FRAME_LIMIT << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
3833                         & SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
3834
3835         iwl_set_bits_prph(priv, IWL49_SCD_INTERRUPT_MASK, (1 << txq_id));
3836
3837         /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
3838         iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
3839
3840         iwl_release_nic_access(priv);
3841         spin_unlock_irqrestore(&priv->lock, flags);
3842
3843         return 0;
3844 }
3845
3846 #endif /* CONFIG_IWL4965_HT */
3847
3848 /**
3849  * iwl4965_add_station - Initialize a station's hardware rate table
3850  *
3851  * The uCode's station table contains a table of fallback rates
3852  * for automatic fallback during transmission.
3853  *
3854  * NOTE: This sets up a default set of values.  These will be replaced later
3855  *       if the driver's iwl-4965-rs rate scaling algorithm is used, instead of
3856  *       rc80211_simple.
3857  *
3858  * NOTE: Run REPLY_ADD_STA command to set up station table entry, before
3859  *       calling this function (which runs REPLY_TX_LINK_QUALITY_CMD,
3860  *       which requires station table entry to exist).
3861  */
3862 void iwl4965_add_station(struct iwl_priv *priv, const u8 *addr, int is_ap)
3863 {
3864         int i, r;
3865         struct iwl_link_quality_cmd link_cmd = {
3866                 .reserved1 = 0,
3867         };
3868         u16 rate_flags;
3869
3870         /* Set up the rate scaling to start at selected rate, fall back
3871          * all the way down to 1M in IEEE order, and then spin on 1M */
3872         if (is_ap)
3873                 r = IWL_RATE_54M_INDEX;
3874         else if (priv->band == IEEE80211_BAND_5GHZ)
3875                 r = IWL_RATE_6M_INDEX;
3876         else
3877                 r = IWL_RATE_1M_INDEX;
3878
3879         for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
3880                 rate_flags = 0;
3881                 if (r >= IWL_FIRST_CCK_RATE && r <= IWL_LAST_CCK_RATE)
3882                         rate_flags |= RATE_MCS_CCK_MSK;
3883
3884                 /* Use Tx antenna B only */
3885                 rate_flags |= RATE_MCS_ANT_B_MSK;
3886                 rate_flags &= ~RATE_MCS_ANT_A_MSK;
3887
3888                 link_cmd.rs_table[i].rate_n_flags =
3889                         iwl4965_hw_set_rate_n_flags(iwl4965_rates[r].plcp, rate_flags);
3890                 r = iwl4965_get_prev_ieee_rate(r);
3891         }
3892
3893         link_cmd.general_params.single_stream_ant_msk = 2;
3894         link_cmd.general_params.dual_stream_ant_msk = 3;
3895         link_cmd.agg_params.agg_dis_start_th = 3;
3896         link_cmd.agg_params.agg_time_limit = cpu_to_le16(4000);
3897
3898         /* Update the rate scaling for control frame Tx to AP */
3899         link_cmd.sta_id = is_ap ? IWL_AP_ID : priv->hw_params.bcast_sta_id;
3900
3901         iwl_send_cmd_pdu_async(priv, REPLY_TX_LINK_QUALITY_CMD,
3902                                sizeof(link_cmd), &link_cmd, NULL);
3903 }
3904
3905 #ifdef CONFIG_IWL4965_HT
3906
3907 static u8 iwl4965_is_channel_extension(struct iwl_priv *priv,
3908                                        enum ieee80211_band band,
3909                                        u16 channel, u8 extension_chan_offset)
3910 {
3911         const struct iwl_channel_info *ch_info;
3912
3913         ch_info = iwl_get_channel_info(priv, band, channel);
3914         if (!is_channel_valid(ch_info))
3915                 return 0;
3916
3917         if (extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_NONE)
3918                 return 0;
3919
3920         if ((ch_info->fat_extension_channel == extension_chan_offset) ||
3921             (ch_info->fat_extension_channel == HT_IE_EXT_CHANNEL_MAX))
3922                 return 1;
3923
3924         return 0;
3925 }
3926
3927 static u8 iwl4965_is_fat_tx_allowed(struct iwl_priv *priv,
3928                                 struct ieee80211_ht_info *sta_ht_inf)
3929 {
3930         struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
3931
3932         if ((!iwl_ht_conf->is_ht) ||
3933            (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ) ||
3934            (iwl_ht_conf->extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_NONE))
3935                 return 0;
3936
3937         if (sta_ht_inf) {
3938                 if ((!sta_ht_inf->ht_supported) ||
3939                    (!(sta_ht_inf->cap & IEEE80211_HT_CAP_SUP_WIDTH)))
3940                         return 0;
3941         }
3942
3943         return (iwl4965_is_channel_extension(priv, priv->band,
3944                                          iwl_ht_conf->control_channel,
3945                                          iwl_ht_conf->extension_chan_offset));
3946 }
3947
3948 void iwl4965_set_rxon_ht(struct iwl_priv *priv, struct iwl_ht_info *ht_info)
3949 {
3950         struct iwl4965_rxon_cmd *rxon = &priv->staging_rxon;
3951         u32 val;
3952
3953         if (!ht_info->is_ht)
3954                 return;
3955
3956         /* Set up channel bandwidth:  20 MHz only, or 20/40 mixed if fat ok */
3957         if (iwl4965_is_fat_tx_allowed(priv, NULL))
3958                 rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED_MSK;
3959         else
3960                 rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
3961                                  RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
3962
3963         if (le16_to_cpu(rxon->channel) != ht_info->control_channel) {
3964                 IWL_DEBUG_ASSOC("control diff than current %d %d\n",
3965                                 le16_to_cpu(rxon->channel),
3966                                 ht_info->control_channel);
3967                 rxon->channel = cpu_to_le16(ht_info->control_channel);
3968                 return;
3969         }
3970
3971         /* Note: control channel is opposite of extension channel */
3972         switch (ht_info->extension_chan_offset) {
3973         case IWL_EXT_CHANNEL_OFFSET_ABOVE:
3974                 rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
3975                 break;
3976         case IWL_EXT_CHANNEL_OFFSET_BELOW:
3977                 rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
3978                 break;
3979         case IWL_EXT_CHANNEL_OFFSET_NONE:
3980         default:
3981                 rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK;
3982                 break;
3983         }
3984
3985         val = ht_info->ht_protection;
3986
3987         rxon->flags |= cpu_to_le32(val << RXON_FLG_HT_OPERATING_MODE_POS);
3988
3989         iwl4965_set_rxon_chain(priv);
3990
3991         IWL_DEBUG_ASSOC("supported HT rate 0x%X %X "
3992                         "rxon flags 0x%X operation mode :0x%X "
3993                         "extension channel offset 0x%x "
3994                         "control chan %d\n",
3995                         ht_info->supp_mcs_set[0], ht_info->supp_mcs_set[1],
3996                         le32_to_cpu(rxon->flags), ht_info->ht_protection,
3997                         ht_info->extension_chan_offset,
3998                         ht_info->control_channel);
3999         return;
4000 }
4001
4002 void iwl4965_set_ht_add_station(struct iwl_priv *priv, u8 index,
4003                                 struct ieee80211_ht_info *sta_ht_inf)
4004 {
4005         __le32 sta_flags;
4006         u8 mimo_ps_mode;
4007
4008         if (!sta_ht_inf || !sta_ht_inf->ht_supported)
4009                 goto done;
4010
4011         mimo_ps_mode = (sta_ht_inf->cap & IEEE80211_HT_CAP_MIMO_PS) >> 2;
4012
4013         sta_flags = priv->stations[index].sta.station_flags;
4014
4015         sta_flags &= ~(STA_FLG_RTS_MIMO_PROT_MSK | STA_FLG_MIMO_DIS_MSK);
4016
4017         switch (mimo_ps_mode) {
4018         case WLAN_HT_CAP_MIMO_PS_STATIC:
4019                 sta_flags |= STA_FLG_MIMO_DIS_MSK;
4020                 break;
4021         case WLAN_HT_CAP_MIMO_PS_DYNAMIC:
4022                 sta_flags |= STA_FLG_RTS_MIMO_PROT_MSK;
4023                 break;
4024         case WLAN_HT_CAP_MIMO_PS_DISABLED:
4025                 break;
4026         default:
4027                 IWL_WARNING("Invalid MIMO PS mode %d", mimo_ps_mode);
4028                 break;
4029         }
4030
4031         sta_flags |= cpu_to_le32(
4032               (u32)sta_ht_inf->ampdu_factor << STA_FLG_MAX_AGG_SIZE_POS);
4033
4034         sta_flags |= cpu_to_le32(
4035               (u32)sta_ht_inf->ampdu_density << STA_FLG_AGG_MPDU_DENSITY_POS);
4036
4037         if (iwl4965_is_fat_tx_allowed(priv, sta_ht_inf))
4038                 sta_flags |= STA_FLG_FAT_EN_MSK;
4039         else
4040                 sta_flags &= ~STA_FLG_FAT_EN_MSK;
4041
4042         priv->stations[index].sta.station_flags = sta_flags;
4043  done:
4044         return;
4045 }
4046
4047 static void iwl4965_sta_modify_add_ba_tid(struct iwl_priv *priv,
4048                                           int sta_id, int tid, u16 ssn)
4049 {
4050         unsigned long flags;
4051
4052         spin_lock_irqsave(&priv->sta_lock, flags);
4053         priv->stations[sta_id].sta.station_flags_msk = 0;
4054         priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK;
4055         priv->stations[sta_id].sta.add_immediate_ba_tid = (u8)tid;
4056         priv->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn);
4057         priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
4058         spin_unlock_irqrestore(&priv->sta_lock, flags);
4059
4060         iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
4061 }
4062
4063 static void iwl4965_sta_modify_del_ba_tid(struct iwl_priv *priv,
4064                                           int sta_id, int tid)
4065 {
4066         unsigned long flags;
4067
4068         spin_lock_irqsave(&priv->sta_lock, flags);
4069         priv->stations[sta_id].sta.station_flags_msk = 0;
4070         priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK;
4071         priv->stations[sta_id].sta.remove_immediate_ba_tid = (u8)tid;
4072         priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
4073         spin_unlock_irqrestore(&priv->sta_lock, flags);
4074
4075         iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
4076 }
4077
4078 /*
4079  * Find first available (lowest unused) Tx Queue, mark it "active".
4080  * Called only when finding queue for aggregation.
4081  * Should never return anything < 7, because they should already
4082  * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6).
4083  */
4084 static int iwl4965_txq_ctx_activate_free(struct iwl_priv *priv)
4085 {
4086         int txq_id;
4087
4088         for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
4089                 if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
4090                         return txq_id;
4091         return -1;
4092 }
4093
4094 static int iwl4965_mac_ht_tx_agg_start(struct ieee80211_hw *hw, const u8 *da,
4095                                        u16 tid, u16 *start_seq_num)
4096 {
4097         struct iwl_priv *priv = hw->priv;
4098         int sta_id;
4099         int tx_fifo;
4100         int txq_id;
4101         int ssn = -1;
4102         int ret = 0;
4103         unsigned long flags;
4104         struct iwl4965_tid_data *tid_data;
4105         DECLARE_MAC_BUF(mac);
4106
4107         if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
4108                 tx_fifo = default_tid_to_tx_fifo[tid];
4109         else
4110                 return -EINVAL;
4111
4112         IWL_WARNING("%s on da = %s tid = %d\n",
4113                         __func__, print_mac(mac, da), tid);
4114
4115         sta_id = iwl4965_hw_find_station(priv, da);
4116         if (sta_id == IWL_INVALID_STATION)
4117                 return -ENXIO;
4118
4119         if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
4120                 IWL_ERROR("Start AGG when state is not IWL_AGG_OFF !\n");
4121                 return -ENXIO;
4122         }
4123
4124         txq_id = iwl4965_txq_ctx_activate_free(priv);
4125         if (txq_id == -1)
4126                 return -ENXIO;
4127
4128         spin_lock_irqsave(&priv->sta_lock, flags);
4129         tid_data = &priv->stations[sta_id].tid[tid];
4130         ssn = SEQ_TO_SN(tid_data->seq_number);
4131         tid_data->agg.txq_id = txq_id;
4132         spin_unlock_irqrestore(&priv->sta_lock, flags);
4133
4134         *start_seq_num = ssn;
4135         ret = iwl4965_tx_queue_agg_enable(priv, txq_id, tx_fifo,
4136                                           sta_id, tid, ssn);
4137         if (ret)
4138                 return ret;
4139
4140         ret = 0;
4141         if (tid_data->tfds_in_queue == 0) {
4142                 printk(KERN_ERR "HW queue is empty\n");
4143                 tid_data->agg.state = IWL_AGG_ON;
4144                 ieee80211_start_tx_ba_cb_irqsafe(hw, da, tid);
4145         } else {
4146                 IWL_DEBUG_HT("HW queue is NOT empty: %d packets in HW queue\n",
4147                                 tid_data->tfds_in_queue);
4148                 tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
4149         }
4150         return ret;
4151 }
4152
4153 static int iwl4965_mac_ht_tx_agg_stop(struct ieee80211_hw *hw, const u8 *da,
4154                                       u16 tid)
4155 {
4156
4157         struct iwl_priv *priv = hw->priv;
4158         int tx_fifo_id, txq_id, sta_id, ssn = -1;
4159         struct iwl4965_tid_data *tid_data;
4160         int ret, write_ptr, read_ptr;
4161         unsigned long flags;
4162         DECLARE_MAC_BUF(mac);
4163
4164         if (!da) {
4165                 IWL_ERROR("da = NULL\n");
4166                 return -EINVAL;
4167         }
4168
4169         if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
4170                 tx_fifo_id = default_tid_to_tx_fifo[tid];
4171         else
4172                 return -EINVAL;
4173
4174         sta_id = iwl4965_hw_find_station(priv, da);
4175
4176         if (sta_id == IWL_INVALID_STATION)
4177                 return -ENXIO;
4178
4179         if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
4180                 IWL_WARNING("Stopping AGG while state not IWL_AGG_ON\n");
4181
4182         tid_data = &priv->stations[sta_id].tid[tid];
4183         ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
4184         txq_id = tid_data->agg.txq_id;
4185         write_ptr = priv->txq[txq_id].q.write_ptr;
4186         read_ptr = priv->txq[txq_id].q.read_ptr;
4187
4188         /* The queue is not empty */
4189         if (write_ptr != read_ptr) {
4190                 IWL_DEBUG_HT("Stopping a non empty AGG HW QUEUE\n");
4191                 priv->stations[sta_id].tid[tid].agg.state =
4192                                 IWL_EMPTYING_HW_QUEUE_DELBA;
4193                 return 0;
4194         }
4195
4196         IWL_DEBUG_HT("HW queue empty\n");;
4197         priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
4198
4199         spin_lock_irqsave(&priv->lock, flags);
4200         ret = iwl4965_tx_queue_agg_disable(priv, txq_id, ssn, tx_fifo_id);
4201         spin_unlock_irqrestore(&priv->lock, flags);
4202
4203         if (ret)
4204                 return ret;
4205
4206         ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, da, tid);
4207
4208         IWL_DEBUG_INFO("iwl4965_mac_ht_tx_agg_stop on da=%s tid=%d\n",
4209                         print_mac(mac, da), tid);
4210
4211         return 0;
4212 }
4213
4214 int iwl4965_mac_ampdu_action(struct ieee80211_hw *hw,
4215                              enum ieee80211_ampdu_mlme_action action,
4216                              const u8 *addr, u16 tid, u16 *ssn)
4217 {
4218         struct iwl_priv *priv = hw->priv;
4219         int sta_id;
4220         DECLARE_MAC_BUF(mac);
4221
4222         IWL_DEBUG_HT("A-MPDU action on da=%s tid=%d ",
4223                         print_mac(mac, addr), tid);
4224         sta_id = iwl4965_hw_find_station(priv, addr);
4225         switch (action) {
4226         case IEEE80211_AMPDU_RX_START:
4227                 IWL_DEBUG_HT("start Rx\n");
4228                 iwl4965_sta_modify_add_ba_tid(priv, sta_id, tid, *ssn);
4229                 break;
4230         case IEEE80211_AMPDU_RX_STOP:
4231                 IWL_DEBUG_HT("stop Rx\n");
4232                 iwl4965_sta_modify_del_ba_tid(priv, sta_id, tid);
4233                 break;
4234         case IEEE80211_AMPDU_TX_START:
4235                 IWL_DEBUG_HT("start Tx\n");
4236                 return iwl4965_mac_ht_tx_agg_start(hw, addr, tid, ssn);
4237         case IEEE80211_AMPDU_TX_STOP:
4238                 IWL_DEBUG_HT("stop Tx\n");
4239                 return iwl4965_mac_ht_tx_agg_stop(hw, addr, tid);
4240         default:
4241                 IWL_DEBUG_HT("unknown\n");
4242                 return -EINVAL;
4243                 break;
4244         }
4245         return 0;
4246 }
4247
4248 #endif /* CONFIG_IWL4965_HT */
4249
4250 /* Set up 4965-specific Rx frame reply handlers */
4251 void iwl4965_hw_rx_handler_setup(struct iwl_priv *priv)
4252 {
4253         /* Legacy Rx frames */
4254         priv->rx_handlers[REPLY_RX] = iwl4965_rx_reply_rx;
4255
4256         /* High-throughput (HT) Rx frames */
4257         priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl4965_rx_reply_rx_phy;
4258         priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl4965_rx_reply_rx;
4259
4260         priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
4261             iwl4965_rx_missed_beacon_notif;
4262
4263 #ifdef CONFIG_IWL4965_HT
4264         priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl4965_rx_reply_compressed_ba;
4265 #endif /* CONFIG_IWL4965_HT */
4266 }
4267
4268 void iwl4965_hw_setup_deferred_work(struct iwl_priv *priv)
4269 {
4270         INIT_WORK(&priv->txpower_work, iwl4965_bg_txpower_work);
4271 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
4272         INIT_WORK(&priv->sensitivity_work, iwl4965_bg_sensitivity_work);
4273 #endif
4274         init_timer(&priv->statistics_periodic);
4275         priv->statistics_periodic.data = (unsigned long)priv;
4276         priv->statistics_periodic.function = iwl4965_bg_statistics_periodic;
4277 }
4278
4279 void iwl4965_hw_cancel_deferred_work(struct iwl_priv *priv)
4280 {
4281         del_timer_sync(&priv->statistics_periodic);
4282
4283         cancel_delayed_work(&priv->init_alive_start);
4284 }
4285
4286
4287 static struct iwl_hcmd_ops iwl4965_hcmd = {
4288         .rxon_assoc = iwl4965_send_rxon_assoc,
4289 };
4290
4291 static struct iwl_hcmd_utils_ops iwl4965_hcmd_utils = {
4292         .enqueue_hcmd = iwl4965_enqueue_hcmd,
4293 #ifdef CONFIG_IWL4965_RUN_TIME_CALIB
4294         .chain_noise_reset = iwl4965_chain_noise_reset,
4295         .gain_computation = iwl4965_gain_computation,
4296 #endif
4297 };
4298
4299 static struct iwl_lib_ops iwl4965_lib = {
4300         .init_drv = iwl4965_init_drv,
4301         .set_hw_params = iwl4965_hw_set_hw_params,
4302         .txq_update_byte_cnt_tbl = iwl4965_txq_update_byte_cnt_tbl,
4303         .hw_nic_init = iwl4965_hw_nic_init,
4304         .is_valid_rtc_data_addr = iwl4965_hw_valid_rtc_data_addr,
4305         .alive_notify = iwl4965_alive_notify,
4306         .load_ucode = iwl4965_load_bsm,
4307         .eeprom_ops = {
4308                 .verify_signature  = iwlcore_eeprom_verify_signature,
4309                 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
4310                 .release_semaphore = iwlcore_eeprom_release_semaphore,
4311         },
4312         .radio_kill_sw = iwl4965_radio_kill_sw,
4313 };
4314
4315 static struct iwl_ops iwl4965_ops = {
4316         .lib = &iwl4965_lib,
4317         .hcmd = &iwl4965_hcmd,
4318         .utils = &iwl4965_hcmd_utils,
4319 };
4320
4321 struct iwl_cfg iwl4965_agn_cfg = {
4322         .name = "4965AGN",
4323         .fw_name = "iwlwifi-4965" IWL4965_UCODE_API ".ucode",
4324         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
4325         .ops = &iwl4965_ops,
4326         .mod_params = &iwl4965_mod_params,
4327 };
4328
4329 module_param_named(antenna, iwl4965_mod_params.antenna, int, 0444);
4330 MODULE_PARM_DESC(antenna, "select antenna (1=Main, 2=Aux, default 0 [both])");
4331 module_param_named(disable, iwl4965_mod_params.disable, int, 0444);
4332 MODULE_PARM_DESC(disable, "manually disable the radio (default 0 [radio on])");
4333 module_param_named(swcrypto, iwl4965_mod_params.sw_crypto, int, 0444);
4334 MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])\n");
4335 module_param_named(debug, iwl4965_mod_params.debug, int, 0444);
4336 MODULE_PARM_DESC(debug, "debug output mask");
4337 module_param_named(
4338         disable_hw_scan, iwl4965_mod_params.disable_hw_scan, int, 0444);
4339 MODULE_PARM_DESC(disable_hw_scan, "disable hardware scanning (default 0)");
4340
4341 module_param_named(queues_num, iwl4965_mod_params.num_of_queues, int, 0444);
4342 MODULE_PARM_DESC(queues_num, "number of hw queues.");
4343
4344 /* QoS */
4345 module_param_named(qos_enable, iwl4965_mod_params.enable_qos, int, 0444);
4346 MODULE_PARM_DESC(qos_enable, "enable all QoS functionality");
4347 module_param_named(amsdu_size_8K, iwl4965_mod_params.amsdu_size_8K, int, 0444);
4348 MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
4349