SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/iwlwifi/iwl-3945.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * James P. Ketrenos <ipw2100-admin@linux.intel.com>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  *****************************************************************************/
  26
  27 #include <linux/kernel.h>
  28 #include <linux/module.h>
  29 #include <linux/init.h>
  30 #include <linux/pci.h>
  31 #include <linux/dma-mapping.h>
  32 #include <linux/delay.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/netdevice.h>
  35 #include <linux/wireless.h>
  36 #include <linux/firmware.h>
  37 #include <linux/etherdevice.h>
  38 #include <asm/unaligned.h>
  39 #include <net/mac80211.h>
  40
  41 #include "iwl-3945-core.h"
  42 #include "iwl-3945.h"
  43 #include "iwl-helpers.h"
  44 #include "iwl-3945-rs.h"
  45
  46 #define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np)    \
  47         [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP,   \
  48                                     IWL_RATE_##r##M_IEEE,   \
  49                                     IWL_RATE_##ip##M_INDEX, \
  50                                     IWL_RATE_##in##M_INDEX, \
  51                                     IWL_RATE_##rp##M_INDEX, \
  52                                     IWL_RATE_##rn##M_INDEX, \
  53                                     IWL_RATE_##pp##M_INDEX, \
  54                                     IWL_RATE_##np##M_INDEX, \
  55                                     IWL_RATE_##r##M_INDEX_TABLE, \
  56                                     IWL_RATE_##ip##M_INDEX_TABLE }
  57
  58 /*
  59  * Parameter order:
  60  *   rate, prev rate, next rate, prev tgg rate, next tgg rate
  61  *
  62  * If there isn't a valid next or previous rate then INV is used which
  63  * maps to IWL_RATE_INVALID
  64  *
  65  */
  66 const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT] = {
  67         IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2),    /*  1mbps */
  68         IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5),          /*  2mbps */
  69         IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11),        /*5.5mbps */
  70         IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18),      /* 11mbps */
  71         IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11),        /*  6mbps */
  72         IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11),       /*  9mbps */
  73         IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18),   /* 12mbps */
  74         IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24),   /* 18mbps */
  75         IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36),   /* 24mbps */
  76         IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48),   /* 36mbps */
  77         IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54),   /* 48mbps */
  78         IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
  79 };
  80
  81 /* 1 = enable the iwl3945_disable_events() function */
  82 #define IWL_EVT_DISABLE (0)
  83 #define IWL_EVT_DISABLE_SIZE (1532/32)
  84
  85 /**
  86  * iwl3945_disable_events - Disable selected events in uCode event log
  87  *
  88  * Disable an event by writing "1"s into "disable"
  89  *   bitmap in SRAM.  Bit position corresponds to Event # (id/type).
  90  *   Default values of 0 enable uCode events to be logged.
  91  * Use for only special debugging.  This function is just a placeholder as-is,
  92  *   you'll need to provide the special bits! ...
  93  *   ... and set IWL_EVT_DISABLE to 1. */
  94 void iwl3945_disable_events(struct iwl3945_priv *priv)
  95 {
  96         int ret;
  97         int i;
  98         u32 base;               /* SRAM address of event log header */
  99         u32 disable_ptr;        /* SRAM address of event-disable bitmap array */
 100         u32 array_size;         /* # of u32 entries in array */
 101         u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
 102                 0x00000000,     /*   31 -    0  Event id numbers */
 103                 0x00000000,     /*   63 -   32 */
 104                 0x00000000,     /*   95 -   64 */
 105                 0x00000000,     /*  127 -   96 */
 106                 0x00000000,     /*  159 -  128 */
 107                 0x00000000,     /*  191 -  160 */
 108                 0x00000000,     /*  223 -  192 */
 109                 0x00000000,     /*  255 -  224 */
 110                 0x00000000,     /*  287 -  256 */
 111                 0x00000000,     /*  319 -  288 */
 112                 0x00000000,     /*  351 -  320 */
 113                 0x00000000,     /*  383 -  352 */
 114                 0x00000000,     /*  415 -  384 */
 115                 0x00000000,     /*  447 -  416 */
 116                 0x00000000,     /*  479 -  448 */
 117                 0x00000000,     /*  511 -  480 */
 118                 0x00000000,     /*  543 -  512 */
 119                 0x00000000,     /*  575 -  544 */
 120                 0x00000000,     /*  607 -  576 */
 121                 0x00000000,     /*  639 -  608 */
 122                 0x00000000,     /*  671 -  640 */
 123                 0x00000000,     /*  703 -  672 */
 124                 0x00000000,     /*  735 -  704 */
 125                 0x00000000,     /*  767 -  736 */
 126                 0x00000000,     /*  799 -  768 */
 127                 0x00000000,     /*  831 -  800 */
 128                 0x00000000,     /*  863 -  832 */
 129                 0x00000000,     /*  895 -  864 */
 130                 0x00000000,     /*  927 -  896 */
 131                 0x00000000,     /*  959 -  928 */
 132                 0x00000000,     /*  991 -  960 */
 133                 0x00000000,     /* 1023 -  992 */
 134                 0x00000000,     /* 1055 - 1024 */
 135                 0x00000000,     /* 1087 - 1056 */
 136                 0x00000000,     /* 1119 - 1088 */
 137                 0x00000000,     /* 1151 - 1120 */
 138                 0x00000000,     /* 1183 - 1152 */
 139                 0x00000000,     /* 1215 - 1184 */
 140                 0x00000000,     /* 1247 - 1216 */
 141                 0x00000000,     /* 1279 - 1248 */
 142                 0x00000000,     /* 1311 - 1280 */
 143                 0x00000000,     /* 1343 - 1312 */
 144                 0x00000000,     /* 1375 - 1344 */
 145                 0x00000000,     /* 1407 - 1376 */
 146                 0x00000000,     /* 1439 - 1408 */
 147                 0x00000000,     /* 1471 - 1440 */
 148                 0x00000000,     /* 1503 - 1472 */
 149         };
 150
 151         base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
 152         if (!iwl3945_hw_valid_rtc_data_addr(base)) {
 153                 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
 154                 return;
 155         }
 156
 157         ret = iwl3945_grab_nic_access(priv);
 158         if (ret) {
 159                 IWL_WARNING("Can not read from adapter at this time.\n");
 160                 return;
 161         }
 162
 163         disable_ptr = iwl3945_read_targ_mem(priv, base + (4 * sizeof(u32)));
 164         array_size = iwl3945_read_targ_mem(priv, base + (5 * sizeof(u32)));
 165         iwl3945_release_nic_access(priv);
 166
 167         if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
 168                 IWL_DEBUG_INFO("Disabling selected uCode log events at 0x%x\n",
 169                                disable_ptr);
 170                 ret = iwl3945_grab_nic_access(priv);
 171                 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
 172                         iwl3945_write_targ_mem(priv,
 173                                            disable_ptr + (i * sizeof(u32)),
 174                                            evt_disable[i]);
 175
 176                 iwl3945_release_nic_access(priv);
 177         } else {
 178                 IWL_DEBUG_INFO("Selected uCode log events may be disabled\n");
 179                 IWL_DEBUG_INFO("  by writing \"1\"s into disable bitmap\n");
 180                 IWL_DEBUG_INFO("  in SRAM at 0x%x, size %d u32s\n",
 181                                disable_ptr, array_size);
 182         }
 183
 184 }
 185
 186 static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
 187 {
 188         int idx;
 189
 190         for (idx = 0; idx < IWL_RATE_COUNT; idx++)
 191                 if (iwl3945_rates[idx].plcp == plcp)
 192                         return idx;
 193         return -1;
 194 }
 195
 196 /**
 197  * iwl3945_get_antenna_flags - Get antenna flags for RXON command
 198  * @priv: eeprom and antenna fields are used to determine antenna flags
 199  *
 200  * priv->eeprom  is used to determine if antenna AUX/MAIN are reversed
 201  * priv->antenna specifies the antenna diversity mode:
 202  *
 203  * IWL_ANTENNA_DIVERISTY - NIC selects best antenna by itself
 204  * IWL_ANTENNA_MAIN      - Force MAIN antenna
 205  * IWL_ANTENNA_AUX       - Force AUX antenna
 206  */
 207 __le32 iwl3945_get_antenna_flags(const struct iwl3945_priv *priv)
 208 {
 209         switch (priv->antenna) {
 210         case IWL_ANTENNA_DIVERSITY:
 211                 return 0;
 212
 213         case IWL_ANTENNA_MAIN:
 214                 if (priv->eeprom.antenna_switch_type)
 215                         return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
 216                 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
 217
 218         case IWL_ANTENNA_AUX:
 219                 if (priv->eeprom.antenna_switch_type)
 220                         return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
 221                 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
 222         }
 223
 224         /* bad antenna selector value */
 225         IWL_ERROR("Bad antenna selector value (0x%x)\n", priv->antenna);
 226         return 0;               /* "diversity" is default if error */
 227 }
 228
 229 #ifdef CONFIG_IWL3945_DEBUG
 230 #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
 231
 232 static const char *iwl3945_get_tx_fail_reason(u32 status)
 233 {
 234         switch (status & TX_STATUS_MSK) {
 235         case TX_STATUS_SUCCESS:
 236                 return "SUCCESS";
 237                 TX_STATUS_ENTRY(SHORT_LIMIT);
 238                 TX_STATUS_ENTRY(LONG_LIMIT);
 239                 TX_STATUS_ENTRY(FIFO_UNDERRUN);
 240                 TX_STATUS_ENTRY(MGMNT_ABORT);
 241                 TX_STATUS_ENTRY(NEXT_FRAG);
 242                 TX_STATUS_ENTRY(LIFE_EXPIRE);
 243                 TX_STATUS_ENTRY(DEST_PS);
 244                 TX_STATUS_ENTRY(ABORTED);
 245                 TX_STATUS_ENTRY(BT_RETRY);
 246                 TX_STATUS_ENTRY(STA_INVALID);
 247                 TX_STATUS_ENTRY(FRAG_DROPPED);
 248                 TX_STATUS_ENTRY(TID_DISABLE);
 249                 TX_STATUS_ENTRY(FRAME_FLUSHED);
 250                 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
 251                 TX_STATUS_ENTRY(TX_LOCKED);
 252                 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
 253         }
 254
 255         return "UNKNOWN";
 256 }
 257 #else
 258 static inline const char *iwl3945_get_tx_fail_reason(u32 status)
 259 {
 260         return "";
 261 }
 262 #endif
 263
 264
 265 /**
 266  * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
 267  *
 268  * When FW advances 'R' index, all entries between old and new 'R' index
 269  * need to be reclaimed. As result, some free space forms. If there is
 270  * enough free space (> low mark), wake the stack that feeds us.
 271  */
 272 static void iwl3945_tx_queue_reclaim(struct iwl3945_priv *priv,
 273                                      int txq_id, int index)
 274 {
 275         struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
 276         struct iwl3945_queue *q = &txq->q;
 277         struct iwl3945_tx_info *tx_info;
 278
 279         BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
 280
 281         for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
 282                 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
 283
 284                 tx_info = &txq->txb[txq->q.read_ptr];
 285                 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
 286                 tx_info->skb[0] = NULL;
 287                 iwl3945_hw_txq_free_tfd(priv, txq);
 288         }
 289
 290         if (iwl3945_queue_space(q) > q->low_mark && (txq_id >= 0) &&
 291                         (txq_id != IWL_CMD_QUEUE_NUM) &&
 292                         priv->mac80211_registered)
 293                 ieee80211_wake_queue(priv->hw, txq_id);
 294 }
 295
 296 /**
 297  * iwl3945_rx_reply_tx - Handle Tx response
 298  */
 299 static void iwl3945_rx_reply_tx(struct iwl3945_priv *priv,
 300                             struct iwl3945_rx_mem_buffer *rxb)
 301 {
 302         struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
 303         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
 304         int txq_id = SEQ_TO_QUEUE(sequence);
 305         int index = SEQ_TO_INDEX(sequence);
 306         struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
 307         struct ieee80211_tx_info *info;
 308         struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
 309         u32  status = le32_to_cpu(tx_resp->status);
 310         int rate_idx;
 311
 312         if ((index >= txq->q.n_bd) || (iwl3945_x2_queue_used(&txq->q, index) == 0)) {
 313                 IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
 314                           "is out of range [0-%d] %d %d\n", txq_id,
 315                           index, txq->q.n_bd, txq->q.write_ptr,
 316                           txq->q.read_ptr);
 317                 return;
 318         }
 319
 320         info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
 321         memset(&info->status, 0, sizeof(info->status));
 322
 323         info->status.retry_count = tx_resp->failure_frame;
 324         /* tx_status->rts_retry_count = tx_resp->failure_rts; */
 325         info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
 326                                 IEEE80211_TX_STAT_ACK : 0;
 327
 328         IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
 329                         txq_id, iwl3945_get_tx_fail_reason(status), status,
 330                         tx_resp->rate, tx_resp->failure_frame);
 331
 332         rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
 333         if (info->band == IEEE80211_BAND_5GHZ)
 334                 rate_idx -= IWL_FIRST_OFDM_RATE;
 335         info->tx_rate_idx = rate_idx;
 336         IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
 337         iwl3945_tx_queue_reclaim(priv, txq_id, index);
 338
 339         if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
 340                 IWL_ERROR("TODO:  Implement Tx ABORT REQUIRED!!!\n");
 341 }
 342
 343
 344
 345 /*****************************************************************************
 346  *
 347  * Intel PRO/Wireless 3945ABG/BG Network Connection
 348  *
 349  *  RX handler implementations
 350  *
 351  *****************************************************************************/
 352
 353 void iwl3945_hw_rx_statistics(struct iwl3945_priv *priv, struct iwl3945_rx_mem_buffer *rxb)
 354 {
 355         struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
 356         IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
 357                      (int)sizeof(struct iwl3945_notif_statistics),
 358                      le32_to_cpu(pkt->len));
 359
 360         memcpy(&priv->statistics, pkt->u.raw, sizeof(priv->statistics));
 361
 362         iwl3945_led_background(priv);
 363
 364         priv->last_statistics_time = jiffies;
 365 }
 366
 367 /******************************************************************************
 368  *
 369  * Misc. internal state and helper functions
 370  *
 371  ******************************************************************************/
 372 #ifdef CONFIG_IWL3945_DEBUG
 373
 374 /**
 375  * iwl3945_report_frame - dump frame to syslog during debug sessions
 376  *
 377  * You may hack this function to show different aspects of received frames,
 378  * including selective frame dumps.
 379  * group100 parameter selects whether to show 1 out of 100 good frames.
 380  */
 381 static void iwl3945_dbg_report_frame(struct iwl3945_priv *priv,
 382                       struct iwl3945_rx_packet *pkt,
 383                       struct ieee80211_hdr *header, int group100)
 384 {
 385         u32 to_us;
 386         u32 print_summary = 0;
 387         u32 print_dump = 0;     /* set to 1 to dump all frames' contents */
 388         u32 hundred = 0;
 389         u32 dataframe = 0;
 390         __le16 fc;
 391         u16 seq_ctl;
 392         u16 channel;
 393         u16 phy_flags;
 394         u16 length;
 395         u16 status;
 396         u16 bcn_tmr;
 397         u32 tsf_low;
 398         u64 tsf;
 399         u8 rssi;
 400         u8 agc;
 401         u16 sig_avg;
 402         u16 noise_diff;
 403         struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
 404         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
 405         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
 406         u8 *data = IWL_RX_DATA(pkt);
 407
 408         /* MAC header */
 409         fc = header->frame_control;
 410         seq_ctl = le16_to_cpu(header->seq_ctrl);
 411
 412         /* metadata */
 413         channel = le16_to_cpu(rx_hdr->channel);
 414         phy_flags = le16_to_cpu(rx_hdr->phy_flags);
 415         length = le16_to_cpu(rx_hdr->len);
 416
 417         /* end-of-frame status and timestamp */
 418         status = le32_to_cpu(rx_end->status);
 419         bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
 420         tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
 421         tsf = le64_to_cpu(rx_end->timestamp);
 422
 423         /* signal statistics */
 424         rssi = rx_stats->rssi;
 425         agc = rx_stats->agc;
 426         sig_avg = le16_to_cpu(rx_stats->sig_avg);
 427         noise_diff = le16_to_cpu(rx_stats->noise_diff);
 428
 429         to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
 430
 431         /* if data frame is to us and all is good,
 432          *   (optionally) print summary for only 1 out of every 100 */
 433         if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
 434             cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
 435                 dataframe = 1;
 436                 if (!group100)
 437                         print_summary = 1;      /* print each frame */
 438                 else if (priv->framecnt_to_us < 100) {
 439                         priv->framecnt_to_us++;
 440                         print_summary = 0;
 441                 } else {
 442                         priv->framecnt_to_us = 0;
 443                         print_summary = 1;
 444                         hundred = 1;
 445                 }
 446         } else {
 447                 /* print summary for all other frames */
 448                 print_summary = 1;
 449         }
 450
 451         if (print_summary) {
 452                 char *title;
 453                 int rate;
 454
 455                 if (hundred)
 456                         title = "100Frames";
 457                 else if (ieee80211_has_retry(fc))
 458                         title = "Retry";
 459                 else if (ieee80211_is_assoc_resp(fc))
 460                         title = "AscRsp";
 461                 else if (ieee80211_is_reassoc_resp(fc))
 462                         title = "RasRsp";
 463                 else if (ieee80211_is_probe_resp(fc)) {
 464                         title = "PrbRsp";
 465                         print_dump = 1; /* dump frame contents */
 466                 } else if (ieee80211_is_beacon(fc)) {
 467                         title = "Beacon";
 468                         print_dump = 1; /* dump frame contents */
 469                 } else if (ieee80211_is_atim(fc))
 470                         title = "ATIM";
 471                 else if (ieee80211_is_auth(fc))
 472                         title = "Auth";
 473                 else if (ieee80211_is_deauth(fc))
 474                         title = "DeAuth";
 475                 else if (ieee80211_is_disassoc(fc))
 476                         title = "DisAssoc";
 477                 else
 478                         title = "Frame";
 479
 480                 rate = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
 481                 if (rate == -1)
 482                         rate = 0;
 483                 else
 484                         rate = iwl3945_rates[rate].ieee / 2;
 485
 486                 /* print frame summary.
 487                  * MAC addresses show just the last byte (for brevity),
 488                  *    but you can hack it to show more, if you'd like to. */
 489                 if (dataframe)
 490                         IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
 491                                      "len=%u, rssi=%d, chnl=%d, rate=%d, \n",
 492                                      title, le16_to_cpu(fc), header->addr1[5],
 493                                      length, rssi, channel, rate);
 494                 else {
 495                         /* src/dst addresses assume managed mode */
 496                         IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
 497                                      "src=0x%02x, rssi=%u, tim=%lu usec, "
 498                                      "phy=0x%02x, chnl=%d\n",
 499                                      title, le16_to_cpu(fc), header->addr1[5],
 500                                      header->addr3[5], rssi,
 501                                      tsf_low - priv->scan_start_tsf,
 502                                      phy_flags, channel);
 503                 }
 504         }
 505         if (print_dump)
 506                 iwl3945_print_hex_dump(IWL_DL_RX, data, length);
 507 }
 508 #else
 509 static inline void iwl3945_dbg_report_frame(struct iwl3945_priv *priv,
 510                       struct iwl3945_rx_packet *pkt,
 511                       struct ieee80211_hdr *header, int group100)
 512 {
 513 }
 514 #endif
 515
 516 /* This is necessary only for a number of statistics, see the caller. */
 517 static int iwl3945_is_network_packet(struct iwl3945_priv *priv,
 518                 struct ieee80211_hdr *header)
 519 {
 520         /* Filter incoming packets to determine if they are targeted toward
 521          * this network, discarding packets coming from ourselves */
 522         switch (priv->iw_mode) {
 523         case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source    | BSSID */
 524                 /* packets to our IBSS update information */
 525                 return !compare_ether_addr(header->addr3, priv->bssid);
 526         case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
 527                 /* packets to our IBSS update information */
 528                 return !compare_ether_addr(header->addr2, priv->bssid);
 529         default:
 530                 return 1;
 531         }
 532 }
 533
 534 static void iwl3945_pass_packet_to_mac80211(struct iwl3945_priv *priv,
 535                                    struct iwl3945_rx_mem_buffer *rxb,
 536                                    struct ieee80211_rx_status *stats)
 537 {
 538         struct iwl3945_rx_packet *pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
 539 #ifdef CONFIG_IWL3945_LEDS
 540         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
 541 #endif
 542         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
 543         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
 544         short len = le16_to_cpu(rx_hdr->len);
 545
 546         /* We received data from the HW, so stop the watchdog */
 547         if (unlikely((len + IWL_RX_FRAME_SIZE) > skb_tailroom(rxb->skb))) {
 548                 IWL_DEBUG_DROP("Corruption detected!\n");
 549                 return;
 550         }
 551
 552         /* We only process data packets if the interface is open */
 553         if (unlikely(!priv->is_open)) {
 554                 IWL_DEBUG_DROP_LIMIT
 555                     ("Dropping packet while interface is not open.\n");
 556                 return;
 557         }
 558
 559         skb_reserve(rxb->skb, (void *)rx_hdr->payload - (void *)pkt);
 560         /* Set the size of the skb to the size of the frame */
 561         skb_put(rxb->skb, le16_to_cpu(rx_hdr->len));
 562
 563         if (iwl3945_param_hwcrypto)
 564                 iwl3945_set_decrypted_flag(priv, rxb->skb,
 565                                        le32_to_cpu(rx_end->status), stats);
 566
 567 #ifdef CONFIG_IWL3945_LEDS
 568         if (ieee80211_is_data(hdr->frame_control))
 569                 priv->rxtxpackets += len;
 570 #endif
 571         ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
 572         rxb->skb = NULL;
 573 }
 574
 575 #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
 576
 577 static void iwl3945_rx_reply_rx(struct iwl3945_priv *priv,
 578                                 struct iwl3945_rx_mem_buffer *rxb)
 579 {
 580         struct ieee80211_hdr *header;
 581         struct ieee80211_rx_status rx_status;
 582         struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
 583         struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
 584         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
 585         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
 586         int snr;
 587         u16 rx_stats_sig_avg = le16_to_cpu(rx_stats->sig_avg);
 588         u16 rx_stats_noise_diff = le16_to_cpu(rx_stats->noise_diff);
 589         u8 network_packet;
 590
 591         rx_status.flag = 0;
 592         rx_status.mactime = le64_to_cpu(rx_end->timestamp);
 593         rx_status.freq =
 594                 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
 595         rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
 596                                 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
 597
 598         rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
 599         if (rx_status.band == IEEE80211_BAND_5GHZ)
 600                 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
 601
 602         rx_status.antenna = le16_to_cpu(rx_hdr->phy_flags &
 603                                         RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
 604
 605         /* set the preamble flag if appropriate */
 606         if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
 607                 rx_status.flag |= RX_FLAG_SHORTPRE;
 608
 609         if ((unlikely(rx_stats->phy_count > 20))) {
 610                 IWL_DEBUG_DROP
 611                     ("dsp size out of range [0,20]: "
 612                      "%d/n", rx_stats->phy_count);
 613                 return;
 614         }
 615
 616         if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
 617             || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
 618                 IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
 619                 return;
 620         }
 621
 622
 623
 624         /* Convert 3945's rssi indicator to dBm */
 625         rx_status.signal = rx_stats->rssi - IWL_RSSI_OFFSET;
 626
 627         /* Set default noise value to -127 */
 628         if (priv->last_rx_noise == 0)
 629                 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
 630
 631         /* 3945 provides noise info for OFDM frames only.
 632          * sig_avg and noise_diff are measured by the 3945's digital signal
 633          *   processor (DSP), and indicate linear levels of signal level and
 634          *   distortion/noise within the packet preamble after
 635          *   automatic gain control (AGC).  sig_avg should stay fairly
 636          *   constant if the radio's AGC is working well.
 637          * Since these values are linear (not dB or dBm), linear
 638          *   signal-to-noise ratio (SNR) is (sig_avg / noise_diff).
 639          * Convert linear SNR to dB SNR, then subtract that from rssi dBm
 640          *   to obtain noise level in dBm.
 641          * Calculate rx_status.signal (quality indicator in %) based on SNR. */
 642         if (rx_stats_noise_diff) {
 643                 snr = rx_stats_sig_avg / rx_stats_noise_diff;
 644                 rx_status.noise = rx_status.signal -
 645                                         iwl3945_calc_db_from_ratio(snr);
 646                 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal,
 647                                                          rx_status.noise);
 648
 649         /* If noise info not available, calculate signal quality indicator (%)
 650          *   using just the dBm signal level. */
 651         } else {
 652                 rx_status.noise = priv->last_rx_noise;
 653                 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal, 0);
 654         }
 655
 656
 657         IWL_DEBUG_STATS("Rssi %d noise %d qual %d sig_avg %d noise_diff %d\n",
 658                         rx_status.signal, rx_status.noise, rx_status.qual,
 659                         rx_stats_sig_avg, rx_stats_noise_diff);
 660
 661         header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
 662
 663         network_packet = iwl3945_is_network_packet(priv, header);
 664
 665         IWL_DEBUG_STATS_LIMIT("[%c] %d RSSI:%d Signal:%u, Noise:%u, Rate:%u\n",
 666                               network_packet ? '*' : ' ',
 667                               le16_to_cpu(rx_hdr->channel),
 668                               rx_status.signal, rx_status.signal,
 669                               rx_status.noise, rx_status.rate_idx);
 670
 671 #ifdef CONFIG_IWL3945_DEBUG
 672         if (iwl3945_debug_level & (IWL_DL_RX))
 673                 /* Set "1" to report good data frames in groups of 100 */
 674                 iwl3945_dbg_report_frame(priv, pkt, header, 1);
 675 #endif
 676
 677         if (network_packet) {
 678                 priv->last_beacon_time = le32_to_cpu(rx_end->beacon_timestamp);
 679                 priv->last_tsf = le64_to_cpu(rx_end->timestamp);
 680                 priv->last_rx_rssi = rx_status.signal;
 681                 priv->last_rx_noise = rx_status.noise;
 682         }
 683
 684         iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
 685 }
 686
 687 int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl3945_priv *priv, void *ptr,
 688                                  dma_addr_t addr, u16 len)
 689 {
 690         int count;
 691         u32 pad;
 692         struct iwl3945_tfd_frame *tfd = (struct iwl3945_tfd_frame *)ptr;
 693
 694         count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
 695         pad = TFD_CTL_PAD_GET(le32_to_cpu(tfd->control_flags));
 696
 697         if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
 698                 IWL_ERROR("Error can not send more than %d chunks\n",
 699                           NUM_TFD_CHUNKS);
 700                 return -EINVAL;
 701         }
 702
 703         tfd->pa[count].addr = cpu_to_le32(addr);
 704         tfd->pa[count].len = cpu_to_le32(len);
 705
 706         count++;
 707
 708         tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
 709                                          TFD_CTL_PAD_SET(pad));
 710
 711         return 0;
 712 }
 713
 714 /**
 715  * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
 716  *
 717  * Does NOT advance any indexes
 718  */
 719 int iwl3945_hw_txq_free_tfd(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
 720 {
 721         struct iwl3945_tfd_frame *bd_tmp = (struct iwl3945_tfd_frame *)&txq->bd[0];
 722         struct iwl3945_tfd_frame *bd = &bd_tmp[txq->q.read_ptr];
 723         struct pci_dev *dev = priv->pci_dev;
 724         int i;
 725         int counter;
 726
 727         /* classify bd */
 728         if (txq->q.id == IWL_CMD_QUEUE_NUM)
 729                 /* nothing to cleanup after for host commands */
 730                 return 0;
 731
 732         /* sanity check */
 733         counter = TFD_CTL_COUNT_GET(le32_to_cpu(bd->control_flags));
 734         if (counter > NUM_TFD_CHUNKS) {
 735                 IWL_ERROR("Too many chunks: %i\n", counter);
 736                 /* @todo issue fatal error, it is quite serious situation */
 737                 return 0;
 738         }
 739
 740         /* unmap chunks if any */
 741
 742         for (i = 1; i < counter; i++) {
 743                 pci_unmap_single(dev, le32_to_cpu(bd->pa[i].addr),
 744                                  le32_to_cpu(bd->pa[i].len), PCI_DMA_TODEVICE);
 745                 if (txq->txb[txq->q.read_ptr].skb[0]) {
 746                         struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
 747                         if (txq->txb[txq->q.read_ptr].skb[0]) {
 748                                 /* Can be called from interrupt context */
 749                                 dev_kfree_skb_any(skb);
 750                                 txq->txb[txq->q.read_ptr].skb[0] = NULL;
 751                         }
 752                 }
 753         }
 754         return 0;
 755 }
 756
 757 u8 iwl3945_hw_find_station(struct iwl3945_priv *priv, const u8 *addr)
 758 {
 759         int i;
 760         int ret = IWL_INVALID_STATION;
 761         unsigned long flags;
 762
 763         spin_lock_irqsave(&priv->sta_lock, flags);
 764         for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++)
 765                 if ((priv->stations[i].used) &&
 766                     (!compare_ether_addr
 767                      (priv->stations[i].sta.sta.addr, addr))) {
 768                         ret = i;
 769                         goto out;
 770                 }
 771
 772         IWL_DEBUG_INFO("can not find STA %pM (total %d)\n",
 773                        addr, priv->num_stations);
 774  out:
 775         spin_unlock_irqrestore(&priv->sta_lock, flags);
 776         return ret;
 777 }
 778
 779 /**
 780  * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
 781  *
 782 */
 783 void iwl3945_hw_build_tx_cmd_rate(struct iwl3945_priv *priv,
 784                               struct iwl3945_cmd *cmd,
 785                               struct ieee80211_tx_info *info,
 786                               struct ieee80211_hdr *hdr, int sta_id, int tx_id)
 787 {
 788         unsigned long flags;
 789         u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
 790         u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT - 1);
 791         u16 rate_mask;
 792         int rate;
 793         u8 rts_retry_limit;
 794         u8 data_retry_limit;
 795         __le32 tx_flags;
 796         __le16 fc = hdr->frame_control;
 797
 798         rate = iwl3945_rates[rate_index].plcp;
 799         tx_flags = cmd->cmd.tx.tx_flags;
 800
 801         /* We need to figure out how to get the sta->supp_rates while
 802          * in this running context */
 803         rate_mask = IWL_RATES_MASK;
 804
 805         spin_lock_irqsave(&priv->sta_lock, flags);
 806
 807         priv->stations[sta_id].current_rate.rate_n_flags = rate;
 808
 809         if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) &&
 810             (sta_id != priv->hw_setting.bcast_sta_id) &&
 811                 (sta_id != IWL_MULTICAST_ID))
 812                 priv->stations[IWL_STA_ID].current_rate.rate_n_flags = rate;
 813
 814         spin_unlock_irqrestore(&priv->sta_lock, flags);
 815
 816         if (tx_id >= IWL_CMD_QUEUE_NUM)
 817                 rts_retry_limit = 3;
 818         else
 819                 rts_retry_limit = 7;
 820
 821         if (ieee80211_is_probe_resp(fc)) {
 822                 data_retry_limit = 3;
 823                 if (data_retry_limit < rts_retry_limit)
 824                         rts_retry_limit = data_retry_limit;
 825         } else
 826                 data_retry_limit = IWL_DEFAULT_TX_RETRY;
 827
 828         if (priv->data_retry_limit != -1)
 829                 data_retry_limit = priv->data_retry_limit;
 830
 831         if (ieee80211_is_mgmt(fc)) {
 832                 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
 833                 case cpu_to_le16(IEEE80211_STYPE_AUTH):
 834                 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
 835                 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
 836                 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
 837                         if (tx_flags & TX_CMD_FLG_RTS_MSK) {
 838                                 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
 839                                 tx_flags |= TX_CMD_FLG_CTS_MSK;
 840                         }
 841                         break;
 842                 default:
 843                         break;
 844                 }
 845         }
 846
 847         cmd->cmd.tx.rts_retry_limit = rts_retry_limit;
 848         cmd->cmd.tx.data_retry_limit = data_retry_limit;
 849         cmd->cmd.tx.rate = rate;
 850         cmd->cmd.tx.tx_flags = tx_flags;
 851
 852         /* OFDM */
 853         cmd->cmd.tx.supp_rates[0] =
 854            ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
 855
 856         /* CCK */
 857         cmd->cmd.tx.supp_rates[1] = (rate_mask & 0xF);
 858
 859         IWL_DEBUG_RATE("Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
 860                        "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
 861                        cmd->cmd.tx.rate, le32_to_cpu(cmd->cmd.tx.tx_flags),
 862                        cmd->cmd.tx.supp_rates[1], cmd->cmd.tx.supp_rates[0]);
 863 }
 864
 865 u8 iwl3945_sync_sta(struct iwl3945_priv *priv, int sta_id, u16 tx_rate, u8 flags)
 866 {
 867         unsigned long flags_spin;
 868         struct iwl3945_station_entry *station;
 869
 870         if (sta_id == IWL_INVALID_STATION)
 871                 return IWL_INVALID_STATION;
 872
 873         spin_lock_irqsave(&priv->sta_lock, flags_spin);
 874         station = &priv->stations[sta_id];
 875
 876         station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
 877         station->sta.rate_n_flags = cpu_to_le16(tx_rate);
 878         station->current_rate.rate_n_flags = tx_rate;
 879         station->sta.mode = STA_CONTROL_MODIFY_MSK;
 880
 881         spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
 882
 883         iwl3945_send_add_station(priv, &station->sta, flags);
 884         IWL_DEBUG_RATE("SCALE sync station %d to rate %d\n",
 885                         sta_id, tx_rate);
 886         return sta_id;
 887 }
 888
 889 static int iwl3945_nic_set_pwr_src(struct iwl3945_priv *priv, int pwr_max)
 890 {
 891         int rc;
 892         unsigned long flags;
 893
 894         spin_lock_irqsave(&priv->lock, flags);
 895         rc = iwl3945_grab_nic_access(priv);
 896         if (rc) {
 897                 spin_unlock_irqrestore(&priv->lock, flags);
 898                 return rc;
 899         }
 900
 901         if (!pwr_max) {
 902                 u32 val;
 903
 904                 rc = pci_read_config_dword(priv->pci_dev,
 905                                 PCI_POWER_SOURCE, &val);
 906                 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
 907                         iwl3945_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 908                                         APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 909                                         ~APMG_PS_CTRL_MSK_PWR_SRC);
 910                         iwl3945_release_nic_access(priv);
 911
 912                         iwl3945_poll_bit(priv, CSR_GPIO_IN,
 913                                      CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
 914                                      CSR_GPIO_IN_BIT_AUX_POWER, 5000);
 915                 } else
 916                         iwl3945_release_nic_access(priv);
 917         } else {
 918                 iwl3945_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 919                                 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 920                                 ~APMG_PS_CTRL_MSK_PWR_SRC);
 921
 922                 iwl3945_release_nic_access(priv);
 923                 iwl3945_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
 924                              CSR_GPIO_IN_BIT_AUX_POWER, 5000);  /* uS */
 925         }
 926         spin_unlock_irqrestore(&priv->lock, flags);
 927
 928         return rc;
 929 }
 930
 931 static int iwl3945_rx_init(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
 932 {
 933         int rc;
 934         unsigned long flags;
 935
 936         spin_lock_irqsave(&priv->lock, flags);
 937         rc = iwl3945_grab_nic_access(priv);
 938         if (rc) {
 939                 spin_unlock_irqrestore(&priv->lock, flags);
 940                 return rc;
 941         }
 942
 943         iwl3945_write_direct32(priv, FH_RCSR_RBD_BASE(0), rxq->dma_addr);
 944         iwl3945_write_direct32(priv, FH_RCSR_RPTR_ADDR(0),
 945                              priv->hw_setting.shared_phys +
 946                              offsetof(struct iwl3945_shared, rx_read_ptr[0]));
 947         iwl3945_write_direct32(priv, FH_RCSR_WPTR(0), 0);
 948         iwl3945_write_direct32(priv, FH_RCSR_CONFIG(0),
 949                 ALM_FH_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
 950                 ALM_FH_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
 951                 ALM_FH_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
 952                 ALM_FH_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
 953                 (RX_QUEUE_SIZE_LOG << ALM_FH_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
 954                 ALM_FH_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
 955                 (1 << ALM_FH_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
 956                 ALM_FH_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
 957
 958         /* fake read to flush all prev I/O */
 959         iwl3945_read_direct32(priv, FH_RSSR_CTRL);
 960
 961         iwl3945_release_nic_access(priv);
 962         spin_unlock_irqrestore(&priv->lock, flags);
 963
 964         return 0;
 965 }
 966
 967 static int iwl3945_tx_reset(struct iwl3945_priv *priv)
 968 {
 969         int rc;
 970         unsigned long flags;
 971
 972         spin_lock_irqsave(&priv->lock, flags);
 973         rc = iwl3945_grab_nic_access(priv);
 974         if (rc) {
 975                 spin_unlock_irqrestore(&priv->lock, flags);
 976                 return rc;
 977         }
 978
 979         /* bypass mode */
 980         iwl3945_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
 981
 982         /* RA 0 is active */
 983         iwl3945_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
 984
 985         /* all 6 fifo are active */
 986         iwl3945_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
 987
 988         iwl3945_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
 989         iwl3945_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
 990         iwl3945_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
 991         iwl3945_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
 992
 993         iwl3945_write_direct32(priv, FH_TSSR_CBB_BASE,
 994                              priv->hw_setting.shared_phys);
 995
 996         iwl3945_write_direct32(priv, FH_TSSR_MSG_CONFIG,
 997                 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
 998                 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
 999                 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
1000                 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
1001                 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
1002                 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
1003                 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
1004
1005         iwl3945_release_nic_access(priv);
1006         spin_unlock_irqrestore(&priv->lock, flags);
1007
1008         return 0;
1009 }
1010
1011 /**
1012  * iwl3945_txq_ctx_reset - Reset TX queue context
1013  *
1014  * Destroys all DMA structures and initialize them again
1015  */
1016 static int iwl3945_txq_ctx_reset(struct iwl3945_priv *priv)
1017 {
1018         int rc;
1019         int txq_id, slots_num;
1020
1021         iwl3945_hw_txq_ctx_free(priv);
1022
1023         /* Tx CMD queue */
1024         rc = iwl3945_tx_reset(priv);
1025         if (rc)
1026                 goto error;
1027
1028         /* Tx queue(s) */
1029         for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
1030                 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
1031                                 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
1032                 rc = iwl3945_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
1033                                 txq_id);
1034                 if (rc) {
1035                         IWL_ERROR("Tx %d queue init failed\n", txq_id);
1036                         goto error;
1037                 }
1038         }
1039
1040         return rc;
1041
1042  error:
1043         iwl3945_hw_txq_ctx_free(priv);
1044         return rc;
1045 }
1046
1047 int iwl3945_hw_nic_init(struct iwl3945_priv *priv)
1048 {
1049         u8 rev_id;
1050         int rc;
1051         unsigned long flags;
1052         struct iwl3945_rx_queue *rxq = &priv->rxq;
1053
1054         iwl3945_power_init_handle(priv);
1055
1056         spin_lock_irqsave(&priv->lock, flags);
1057         iwl3945_set_bit(priv, CSR_ANA_PLL_CFG, CSR39_ANA_PLL_CFG_VAL);
1058         iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1059                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
1060
1061         iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1062         rc = iwl3945_poll_bit(priv, CSR_GP_CNTRL,
1063                           CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1064                           CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1065         if (rc < 0) {
1066                 spin_unlock_irqrestore(&priv->lock, flags);
1067                 IWL_DEBUG_INFO("Failed to init the card\n");
1068                 return rc;
1069         }
1070
1071         rc = iwl3945_grab_nic_access(priv);
1072         if (rc) {
1073                 spin_unlock_irqrestore(&priv->lock, flags);
1074                 return rc;
1075         }
1076         iwl3945_write_prph(priv, APMG_CLK_EN_REG,
1077                                  APMG_CLK_VAL_DMA_CLK_RQT |
1078                                  APMG_CLK_VAL_BSM_CLK_RQT);
1079         udelay(20);
1080         iwl3945_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
1081                                     APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1082         iwl3945_release_nic_access(priv);
1083         spin_unlock_irqrestore(&priv->lock, flags);
1084
1085         /* Determine HW type */
1086         rc = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
1087         if (rc)
1088                 return rc;
1089         IWL_DEBUG_INFO("HW Revision ID = 0x%X\n", rev_id);
1090
1091         iwl3945_nic_set_pwr_src(priv, 1);
1092         spin_lock_irqsave(&priv->lock, flags);
1093
1094         if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
1095                 IWL_DEBUG_INFO("RTP type \n");
1096         else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
1097                 IWL_DEBUG_INFO("3945 RADIO-MB type\n");
1098                 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1099                             CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
1100         } else {
1101                 IWL_DEBUG_INFO("3945 RADIO-MM type\n");
1102                 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1103                             CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
1104         }
1105
1106         if (EEPROM_SKU_CAP_OP_MODE_MRC == priv->eeprom.sku_cap) {
1107                 IWL_DEBUG_INFO("SKU OP mode is mrc\n");
1108                 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1109                             CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
1110         } else
1111                 IWL_DEBUG_INFO("SKU OP mode is basic\n");
1112
1113         if ((priv->eeprom.board_revision & 0xF0) == 0xD0) {
1114                 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
1115                                priv->eeprom.board_revision);
1116                 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1117                             CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1118         } else {
1119                 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
1120                                priv->eeprom.board_revision);
1121                 iwl3945_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
1122                               CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1123         }
1124
1125         if (priv->eeprom.almgor_m_version <= 1) {
1126                 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1127                             CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
1128                 IWL_DEBUG_INFO("Card M type A version is 0x%X\n",
1129                                priv->eeprom.almgor_m_version);
1130         } else {
1131                 IWL_DEBUG_INFO("Card M type B version is 0x%X\n",
1132                                priv->eeprom.almgor_m_version);
1133                 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1134                             CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
1135         }
1136         spin_unlock_irqrestore(&priv->lock, flags);
1137
1138         if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
1139                 IWL_DEBUG_RF_KILL("SW RF KILL supported in EEPROM.\n");
1140
1141         if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
1142                 IWL_DEBUG_RF_KILL("HW RF KILL supported in EEPROM.\n");
1143
1144         /* Allocate the RX queue, or reset if it is already allocated */
1145         if (!rxq->bd) {
1146                 rc = iwl3945_rx_queue_alloc(priv);
1147                 if (rc) {
1148                         IWL_ERROR("Unable to initialize Rx queue\n");
1149                         return -ENOMEM;
1150                 }
1151         } else
1152                 iwl3945_rx_queue_reset(priv, rxq);
1153
1154         iwl3945_rx_replenish(priv);
1155
1156         iwl3945_rx_init(priv, rxq);
1157
1158         spin_lock_irqsave(&priv->lock, flags);
1159
1160         /* Look at using this instead:
1161         rxq->need_update = 1;
1162         iwl3945_rx_queue_update_write_ptr(priv, rxq);
1163         */
1164
1165         rc = iwl3945_grab_nic_access(priv);
1166         if (rc) {
1167                 spin_unlock_irqrestore(&priv->lock, flags);
1168                 return rc;
1169         }
1170         iwl3945_write_direct32(priv, FH_RCSR_WPTR(0), rxq->write & ~7);
1171         iwl3945_release_nic_access(priv);
1172
1173         spin_unlock_irqrestore(&priv->lock, flags);
1174
1175         rc = iwl3945_txq_ctx_reset(priv);
1176         if (rc)
1177                 return rc;
1178
1179         set_bit(STATUS_INIT, &priv->status);
1180
1181         return 0;
1182 }
1183
1184 /**
1185  * iwl3945_hw_txq_ctx_free - Free TXQ Context
1186  *
1187  * Destroy all TX DMA queues and structures
1188  */
1189 void iwl3945_hw_txq_ctx_free(struct iwl3945_priv *priv)
1190 {
1191         int txq_id;
1192
1193         /* Tx queues */
1194         for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++)
1195                 iwl3945_tx_queue_free(priv, &priv->txq[txq_id]);
1196 }
1197
1198 void iwl3945_hw_txq_ctx_stop(struct iwl3945_priv *priv)
1199 {
1200         int queue;
1201         unsigned long flags;
1202
1203         spin_lock_irqsave(&priv->lock, flags);
1204         if (iwl3945_grab_nic_access(priv)) {
1205                 spin_unlock_irqrestore(&priv->lock, flags);
1206                 iwl3945_hw_txq_ctx_free(priv);
1207                 return;
1208         }
1209
1210         /* stop SCD */
1211         iwl3945_write_prph(priv, ALM_SCD_MODE_REG, 0);
1212
1213         /* reset TFD queues */
1214         for (queue = TFD_QUEUE_MIN; queue < TFD_QUEUE_MAX; queue++) {
1215                 iwl3945_write_direct32(priv, FH_TCSR_CONFIG(queue), 0x0);
1216                 iwl3945_poll_direct_bit(priv, FH_TSSR_TX_STATUS,
1217                                 ALM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(queue),
1218                                 1000);
1219         }
1220
1221         iwl3945_release_nic_access(priv);
1222         spin_unlock_irqrestore(&priv->lock, flags);
1223
1224         iwl3945_hw_txq_ctx_free(priv);
1225 }
1226
1227 int iwl3945_hw_nic_stop_master(struct iwl3945_priv *priv)
1228 {
1229         int rc = 0;
1230         u32 reg_val;
1231         unsigned long flags;
1232
1233         spin_lock_irqsave(&priv->lock, flags);
1234
1235         /* set stop master bit */
1236         iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
1237
1238         reg_val = iwl3945_read32(priv, CSR_GP_CNTRL);
1239
1240         if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE ==
1241             (reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE))
1242                 IWL_DEBUG_INFO("Card in power save, master is already "
1243                                "stopped\n");
1244         else {
1245                 rc = iwl3945_poll_bit(priv, CSR_RESET,
1246                                   CSR_RESET_REG_FLAG_MASTER_DISABLED,
1247                                   CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
1248                 if (rc < 0) {
1249                         spin_unlock_irqrestore(&priv->lock, flags);
1250                         return rc;
1251                 }
1252         }
1253
1254         spin_unlock_irqrestore(&priv->lock, flags);
1255         IWL_DEBUG_INFO("stop master\n");
1256
1257         return rc;
1258 }
1259
1260 int iwl3945_hw_nic_reset(struct iwl3945_priv *priv)
1261 {
1262         int rc;
1263         unsigned long flags;
1264
1265         iwl3945_hw_nic_stop_master(priv);
1266
1267         spin_lock_irqsave(&priv->lock, flags);
1268
1269         iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1270
1271         rc = iwl3945_poll_bit(priv, CSR_GP_CNTRL,
1272                           CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1273                           CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1274
1275         rc = iwl3945_grab_nic_access(priv);
1276         if (!rc) {
1277                 iwl3945_write_prph(priv, APMG_CLK_CTRL_REG,
1278                                          APMG_CLK_VAL_BSM_CLK_RQT);
1279
1280                 udelay(10);
1281
1282                 iwl3945_set_bit(priv, CSR_GP_CNTRL,
1283                             CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1284
1285                 iwl3945_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1286                 iwl3945_write_prph(priv, APMG_RTC_INT_STT_REG,
1287                                         0xFFFFFFFF);
1288
1289                 /* enable DMA */
1290                 iwl3945_write_prph(priv, APMG_CLK_EN_REG,
1291                                          APMG_CLK_VAL_DMA_CLK_RQT |
1292                                          APMG_CLK_VAL_BSM_CLK_RQT);
1293                 udelay(10);
1294
1295                 iwl3945_set_bits_prph(priv, APMG_PS_CTRL_REG,
1296                                 APMG_PS_CTRL_VAL_RESET_REQ);
1297                 udelay(5);
1298                 iwl3945_clear_bits_prph(priv, APMG_PS_CTRL_REG,
1299                                 APMG_PS_CTRL_VAL_RESET_REQ);
1300                 iwl3945_release_nic_access(priv);
1301         }
1302
1303         /* Clear the 'host command active' bit... */
1304         clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1305
1306         wake_up_interruptible(&priv->wait_command_queue);
1307         spin_unlock_irqrestore(&priv->lock, flags);
1308
1309         return rc;
1310 }
1311
1312 /**
1313  * iwl3945_hw_reg_adjust_power_by_temp
1314  * return index delta into power gain settings table
1315 */
1316 static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
1317 {
1318         return (new_reading - old_reading) * (-11) / 100;
1319 }
1320
1321 /**
1322  * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
1323  */
1324 static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
1325 {
1326         return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
1327 }
1328
1329 int iwl3945_hw_get_temperature(struct iwl3945_priv *priv)
1330 {
1331         return iwl3945_read32(priv, CSR_UCODE_DRV_GP2);
1332 }
1333
1334 /**
1335  * iwl3945_hw_reg_txpower_get_temperature
1336  * get the current temperature by reading from NIC
1337 */
1338 static int iwl3945_hw_reg_txpower_get_temperature(struct iwl3945_priv *priv)
1339 {
1340         int temperature;
1341
1342         temperature = iwl3945_hw_get_temperature(priv);
1343
1344         /* driver's okay range is -260 to +25.
1345          *   human readable okay range is 0 to +285 */
1346         IWL_DEBUG_INFO("Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
1347
1348         /* handle insane temp reading */
1349         if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
1350                 IWL_ERROR("Error bad temperature value  %d\n", temperature);
1351
1352                 /* if really really hot(?),
1353                  *   substitute the 3rd band/group's temp measured at factory */
1354                 if (priv->last_temperature > 100)
1355                         temperature = priv->eeprom.groups[2].temperature;
1356                 else /* else use most recent "sane" value from driver */
1357                         temperature = priv->last_temperature;
1358         }
1359
1360         return temperature;     /* raw, not "human readable" */
1361 }
1362
1363 /* Adjust Txpower only if temperature variance is greater than threshold.
1364  *
1365  * Both are lower than older versions' 9 degrees */
1366 #define IWL_TEMPERATURE_LIMIT_TIMER   6
1367
1368 /**
1369  * is_temp_calib_needed - determines if new calibration is needed
1370  *
1371  * records new temperature in tx_mgr->temperature.
1372  * replaces tx_mgr->last_temperature *only* if calib needed
1373  *    (assumes caller will actually do the calibration!). */
1374 static int is_temp_calib_needed(struct iwl3945_priv *priv)
1375 {
1376         int temp_diff;
1377
1378         priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
1379         temp_diff = priv->temperature - priv->last_temperature;
1380
1381         /* get absolute value */
1382         if (temp_diff < 0) {
1383                 IWL_DEBUG_POWER("Getting cooler, delta %d,\n", temp_diff);
1384                 temp_diff = -temp_diff;
1385         } else if (temp_diff == 0)
1386                 IWL_DEBUG_POWER("Same temp,\n");
1387         else
1388                 IWL_DEBUG_POWER("Getting warmer, delta %d,\n", temp_diff);
1389
1390         /* if we don't need calibration, *don't* update last_temperature */
1391         if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
1392                 IWL_DEBUG_POWER("Timed thermal calib not needed\n");
1393                 return 0;
1394         }
1395
1396         IWL_DEBUG_POWER("Timed thermal calib needed\n");
1397
1398         /* assume that caller will actually do calib ...
1399          *   update the "last temperature" value */
1400         priv->last_temperature = priv->temperature;
1401         return 1;
1402 }
1403
1404 #define IWL_MAX_GAIN_ENTRIES 78
1405 #define IWL_CCK_FROM_OFDM_POWER_DIFF  -5
1406 #define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1407
1408 /* radio and DSP power table, each step is 1/2 dB.
1409  * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
1410 static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
1411         {
1412          {251, 127},            /* 2.4 GHz, highest power */
1413          {251, 127},
1414          {251, 127},
1415          {251, 127},
1416          {251, 125},
1417          {251, 110},
1418          {251, 105},
1419          {251, 98},
1420          {187, 125},
1421          {187, 115},
1422          {187, 108},
1423          {187, 99},
1424          {243, 119},
1425          {243, 111},
1426          {243, 105},
1427          {243, 97},
1428          {243, 92},
1429          {211, 106},
1430          {211, 100},
1431          {179, 120},
1432          {179, 113},
1433          {179, 107},
1434          {147, 125},
1435          {147, 119},
1436          {147, 112},
1437          {147, 106},
1438          {147, 101},
1439          {147, 97},
1440          {147, 91},
1441          {115, 107},
1442          {235, 121},
1443          {235, 115},
1444          {235, 109},
1445          {203, 127},
1446          {203, 121},
1447          {203, 115},
1448          {203, 108},
1449          {203, 102},
1450          {203, 96},
1451          {203, 92},
1452          {171, 110},
1453          {171, 104},
1454          {171, 98},
1455          {139, 116},
1456          {227, 125},
1457          {227, 119},
1458          {227, 113},
1459          {227, 107},
1460          {227, 101},
1461          {227, 96},
1462          {195, 113},
1463          {195, 106},
1464          {195, 102},
1465          {195, 95},
1466          {163, 113},
1467          {163, 106},
1468          {163, 102},
1469          {163, 95},
1470          {131, 113},
1471          {131, 106},
1472          {131, 102},
1473          {131, 95},
1474          {99, 113},
1475          {99, 106},
1476          {99, 102},
1477          {99, 95},
1478          {67, 113},
1479          {67, 106},
1480          {67, 102},
1481          {67, 95},
1482          {35, 113},
1483          {35, 106},
1484          {35, 102},
1485          {35, 95},
1486          {3, 113},
1487          {3, 106},
1488          {3, 102},
1489          {3, 95} },             /* 2.4 GHz, lowest power */
1490         {
1491          {251, 127},            /* 5.x GHz, highest power */
1492          {251, 120},
1493          {251, 114},
1494          {219, 119},
1495          {219, 101},
1496          {187, 113},
1497          {187, 102},
1498          {155, 114},
1499          {155, 103},
1500          {123, 117},
1501          {123, 107},
1502          {123, 99},
1503          {123, 92},
1504          {91, 108},
1505          {59, 125},
1506          {59, 118},
1507          {59, 109},
1508          {59, 102},
1509          {59, 96},
1510          {59, 90},
1511          {27, 104},
1512          {27, 98},
1513          {27, 92},
1514          {115, 118},
1515          {115, 111},
1516          {115, 104},
1517          {83, 126},
1518          {83, 121},
1519          {83, 113},
1520          {83, 105},
1521          {83, 99},
1522          {51, 118},
1523          {51, 111},
1524          {51, 104},
1525          {51, 98},
1526          {19, 116},
1527          {19, 109},
1528          {19, 102},
1529          {19, 98},
1530          {19, 93},
1531          {171, 113},
1532          {171, 107},
1533          {171, 99},
1534          {139, 120},
1535          {139, 113},
1536          {139, 107},
1537          {139, 99},
1538          {107, 120},
1539          {107, 113},
1540          {107, 107},
1541          {107, 99},
1542          {75, 120},
1543          {75, 113},
1544          {75, 107},
1545          {75, 99},
1546          {43, 120},
1547          {43, 113},
1548          {43, 107},
1549          {43, 99},
1550          {11, 120},
1551          {11, 113},
1552          {11, 107},
1553          {11, 99},
1554          {131, 107},
1555          {131, 99},
1556          {99, 120},
1557          {99, 113},
1558          {99, 107},
1559          {99, 99},
1560          {67, 120},
1561          {67, 113},
1562          {67, 107},
1563          {67, 99},
1564          {35, 120},
1565          {35, 113},
1566          {35, 107},
1567          {35, 99},
1568          {3, 120} }             /* 5.x GHz, lowest power */
1569 };
1570
1571 static inline u8 iwl3945_hw_reg_fix_power_index(int index)
1572 {
1573         if (index < 0)
1574                 return 0;
1575         if (index >= IWL_MAX_GAIN_ENTRIES)
1576                 return IWL_MAX_GAIN_ENTRIES - 1;
1577         return (u8) index;
1578 }
1579
1580 /* Kick off thermal recalibration check every 60 seconds */
1581 #define REG_RECALIB_PERIOD (60)
1582
1583 /**
1584  * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
1585  *
1586  * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1587  * or 6 Mbit (OFDM) rates.
1588  */
1589 static void iwl3945_hw_reg_set_scan_power(struct iwl3945_priv *priv, u32 scan_tbl_index,
1590                                s32 rate_index, const s8 *clip_pwrs,
1591                                struct iwl3945_channel_info *ch_info,
1592                                int band_index)
1593 {
1594         struct iwl3945_scan_power_info *scan_power_info;
1595         s8 power;
1596         u8 power_index;
1597
1598         scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1599
1600         /* use this channel group's 6Mbit clipping/saturation pwr,
1601          *   but cap at regulatory scan power restriction (set during init
1602          *   based on eeprom channel data) for this channel.  */
1603         power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
1604
1605         /* further limit to user's max power preference.
1606          * FIXME:  Other spectrum management power limitations do not
1607          *   seem to apply?? */
1608         power = min(power, priv->user_txpower_limit);
1609         scan_power_info->requested_power = power;
1610
1611         /* find difference between new scan *power* and current "normal"
1612          *   Tx *power* for 6Mb.  Use this difference (x2) to adjust the
1613          *   current "normal" temperature-compensated Tx power *index* for
1614          *   this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1615          *   *index*. */
1616         power_index = ch_info->power_info[rate_index].power_table_index
1617             - (power - ch_info->power_info
1618                [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
1619
1620         /* store reference index that we use when adjusting *all* scan
1621          *   powers.  So we can accommodate user (all channel) or spectrum
1622          *   management (single channel) power changes "between" temperature
1623          *   feedback compensation procedures.
1624          * don't force fit this reference index into gain table; it may be a
1625          *   negative number.  This will help avoid errors when we're at
1626          *   the lower bounds (highest gains, for warmest temperatures)
1627          *   of the table. */
1628
1629         /* don't exceed table bounds for "real" setting */
1630         power_index = iwl3945_hw_reg_fix_power_index(power_index);
1631
1632         scan_power_info->power_table_index = power_index;
1633         scan_power_info->tpc.tx_gain =
1634             power_gain_table[band_index][power_index].tx_gain;
1635         scan_power_info->tpc.dsp_atten =
1636             power_gain_table[band_index][power_index].dsp_atten;
1637 }
1638
1639 /**
1640  * iwl3945_hw_reg_send_txpower - fill in Tx Power command with gain settings
1641  *
1642  * Configures power settings for all rates for the current channel,
1643  * using values from channel info struct, and send to NIC
1644  */
1645 int iwl3945_hw_reg_send_txpower(struct iwl3945_priv *priv)
1646 {
1647         int rate_idx, i;
1648         const struct iwl3945_channel_info *ch_info = NULL;
1649         struct iwl3945_txpowertable_cmd txpower = {
1650                 .channel = priv->active_rxon.channel,
1651         };
1652
1653         txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
1654         ch_info = iwl3945_get_channel_info(priv,
1655                                        priv->band,
1656                                        le16_to_cpu(priv->active_rxon.channel));
1657         if (!ch_info) {
1658                 IWL_ERROR
1659                     ("Failed to get channel info for channel %d [%d]\n",
1660                      le16_to_cpu(priv->active_rxon.channel), priv->band);
1661                 return -EINVAL;
1662         }
1663
1664         if (!is_channel_valid(ch_info)) {
1665                 IWL_DEBUG_POWER("Not calling TX_PWR_TABLE_CMD on "
1666                                 "non-Tx channel.\n");
1667                 return 0;
1668         }
1669
1670         /* fill cmd with power settings for all rates for current channel */
1671         /* Fill OFDM rate */
1672         for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
1673              rate_idx <= IWL_LAST_OFDM_RATE; rate_idx++, i++) {
1674
1675                 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1676                 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1677
1678                 IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1679                                 le16_to_cpu(txpower.channel),
1680                                 txpower.band,
1681                                 txpower.power[i].tpc.tx_gain,
1682                                 txpower.power[i].tpc.dsp_atten,
1683                                 txpower.power[i].rate);
1684         }
1685         /* Fill CCK rates */
1686         for (rate_idx = IWL_FIRST_CCK_RATE;
1687              rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1688                 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1689                 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1690
1691                 IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1692                                 le16_to_cpu(txpower.channel),
1693                                 txpower.band,
1694                                 txpower.power[i].tpc.tx_gain,
1695                                 txpower.power[i].tpc.dsp_atten,
1696                                 txpower.power[i].rate);
1697         }
1698
1699         return iwl3945_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1700                         sizeof(struct iwl3945_txpowertable_cmd), &txpower);
1701
1702 }
1703
1704 /**
1705  * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
1706  * @ch_info: Channel to update.  Uses power_info.requested_power.
1707  *
1708  * Replace requested_power and base_power_index ch_info fields for
1709  * one channel.
1710  *
1711  * Called if user or spectrum management changes power preferences.
1712  * Takes into account h/w and modulation limitations (clip power).
1713  *
1714  * This does *not* send anything to NIC, just sets up ch_info for one channel.
1715  *
1716  * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1717  *       properly fill out the scan powers, and actual h/w gain settings,
1718  *       and send changes to NIC
1719  */
1720 static int iwl3945_hw_reg_set_new_power(struct iwl3945_priv *priv,
1721                              struct iwl3945_channel_info *ch_info)
1722 {
1723         struct iwl3945_channel_power_info *power_info;
1724         int power_changed = 0;
1725         int i;
1726         const s8 *clip_pwrs;
1727         int power;
1728
1729         /* Get this chnlgrp's rate-to-max/clip-powers table */
1730         clip_pwrs = priv->clip_groups[ch_info->group_index].clip_powers;
1731
1732         /* Get this channel's rate-to-current-power settings table */
1733         power_info = ch_info->power_info;
1734
1735         /* update OFDM Txpower settings */
1736         for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
1737              i++, ++power_info) {
1738                 int delta_idx;
1739
1740                 /* limit new power to be no more than h/w capability */
1741                 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1742                 if (power == power_info->requested_power)
1743                         continue;
1744
1745                 /* find difference between old and new requested powers,
1746                  *    update base (non-temp-compensated) power index */
1747                 delta_idx = (power - power_info->requested_power) * 2;
1748                 power_info->base_power_index -= delta_idx;
1749
1750                 /* save new requested power value */
1751                 power_info->requested_power = power;
1752
1753                 power_changed = 1;
1754         }
1755
1756         /* update CCK Txpower settings, based on OFDM 12M setting ...
1757          *    ... all CCK power settings for a given channel are the *same*. */
1758         if (power_changed) {
1759                 power =
1760                     ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1761                     requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1762
1763                 /* do all CCK rates' iwl3945_channel_power_info structures */
1764                 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
1765                         power_info->requested_power = power;
1766                         power_info->base_power_index =
1767                             ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1768                             base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1769                         ++power_info;
1770                 }
1771         }
1772
1773         return 0;
1774 }
1775
1776 /**
1777  * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
1778  *
1779  * NOTE: Returned power limit may be less (but not more) than requested,
1780  *       based strictly on regulatory (eeprom and spectrum mgt) limitations
1781  *       (no consideration for h/w clipping limitations).
1782  */
1783 static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl3945_channel_info *ch_info)
1784 {
1785         s8 max_power;
1786
1787 #if 0
1788         /* if we're using TGd limits, use lower of TGd or EEPROM */
1789         if (ch_info->tgd_data.max_power != 0)
1790                 max_power = min(ch_info->tgd_data.max_power,
1791                                 ch_info->eeprom.max_power_avg);
1792
1793         /* else just use EEPROM limits */
1794         else
1795 #endif
1796                 max_power = ch_info->eeprom.max_power_avg;
1797
1798         return min(max_power, ch_info->max_power_avg);
1799 }
1800
1801 /**
1802  * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
1803  *
1804  * Compensate txpower settings of *all* channels for temperature.
1805  * This only accounts for the difference between current temperature
1806  *   and the factory calibration temperatures, and bases the new settings
1807  *   on the channel's base_power_index.
1808  *
1809  * If RxOn is "associated", this sends the new Txpower to NIC!
1810  */
1811 static int iwl3945_hw_reg_comp_txpower_temp(struct iwl3945_priv *priv)
1812 {
1813         struct iwl3945_channel_info *ch_info = NULL;
1814         int delta_index;
1815         const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1816         u8 a_band;
1817         u8 rate_index;
1818         u8 scan_tbl_index;
1819         u8 i;
1820         int ref_temp;
1821         int temperature = priv->temperature;
1822
1823         /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1824         for (i = 0; i < priv->channel_count; i++) {
1825                 ch_info = &priv->channel_info[i];
1826                 a_band = is_channel_a_band(ch_info);
1827
1828                 /* Get this chnlgrp's factory calibration temperature */
1829                 ref_temp = (s16)priv->eeprom.groups[ch_info->group_index].
1830                     temperature;
1831
1832                 /* get power index adjustment based on curr and factory
1833                  * temps */
1834                 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
1835                                                               ref_temp);
1836
1837                 /* set tx power value for all rates, OFDM and CCK */
1838                 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1839                      rate_index++) {
1840                         int power_idx =
1841                             ch_info->power_info[rate_index].base_power_index;
1842
1843                         /* temperature compensate */
1844                         power_idx += delta_index;
1845
1846                         /* stay within table range */
1847                         power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
1848                         ch_info->power_info[rate_index].
1849                             power_table_index = (u8) power_idx;
1850                         ch_info->power_info[rate_index].tpc =
1851                             power_gain_table[a_band][power_idx];
1852                 }
1853
1854                 /* Get this chnlgrp's rate-to-max/clip-powers table */
1855                 clip_pwrs = priv->clip_groups[ch_info->group_index].clip_powers;
1856
1857                 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1858                 for (scan_tbl_index = 0;
1859                      scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1860                         s32 actual_index = (scan_tbl_index == 0) ?
1861                             IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
1862                         iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
1863                                            actual_index, clip_pwrs,
1864                                            ch_info, a_band);
1865                 }
1866         }
1867
1868         /* send Txpower command for current channel to ucode */
1869         return iwl3945_hw_reg_send_txpower(priv);
1870 }
1871
1872 int iwl3945_hw_reg_set_txpower(struct iwl3945_priv *priv, s8 power)
1873 {
1874         struct iwl3945_channel_info *ch_info;
1875         s8 max_power;
1876         u8 a_band;
1877         u8 i;
1878
1879         if (priv->user_txpower_limit == power) {
1880                 IWL_DEBUG_POWER("Requested Tx power same as current "
1881                                 "limit: %ddBm.\n", power);
1882                 return 0;
1883         }
1884
1885         IWL_DEBUG_POWER("Setting upper limit clamp to %ddBm.\n", power);
1886         priv->user_txpower_limit = power;
1887
1888         /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1889
1890         for (i = 0; i < priv->channel_count; i++) {
1891                 ch_info = &priv->channel_info[i];
1892                 a_band = is_channel_a_band(ch_info);
1893
1894                 /* find minimum power of all user and regulatory constraints
1895                  *    (does not consider h/w clipping limitations) */
1896                 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
1897                 max_power = min(power, max_power);
1898                 if (max_power != ch_info->curr_txpow) {
1899                         ch_info->curr_txpow = max_power;
1900
1901                         /* this considers the h/w clipping limitations */
1902                         iwl3945_hw_reg_set_new_power(priv, ch_info);
1903                 }
1904         }
1905
1906         /* update txpower settings for all channels,
1907          *   send to NIC if associated. */
1908         is_temp_calib_needed(priv);
1909         iwl3945_hw_reg_comp_txpower_temp(priv);
1910
1911         return 0;
1912 }
1913
1914 /* will add 3945 channel switch cmd handling later */
1915 int iwl3945_hw_channel_switch(struct iwl3945_priv *priv, u16 channel)
1916 {
1917         return 0;
1918 }
1919
1920 /**
1921  * iwl3945_reg_txpower_periodic -  called when time to check our temperature.
1922  *
1923  * -- reset periodic timer
1924  * -- see if temp has changed enough to warrant re-calibration ... if so:
1925  *     -- correct coeffs for temp (can reset temp timer)
1926  *     -- save this temp as "last",
1927  *     -- send new set of gain settings to NIC
1928  * NOTE:  This should continue working, even when we're not associated,
1929  *   so we can keep our internal table of scan powers current. */
1930 void iwl3945_reg_txpower_periodic(struct iwl3945_priv *priv)
1931 {
1932         /* This will kick in the "brute force"
1933          * iwl3945_hw_reg_comp_txpower_temp() below */
1934         if (!is_temp_calib_needed(priv))
1935                 goto reschedule;
1936
1937         /* Set up a new set of temp-adjusted TxPowers, send to NIC.
1938          * This is based *only* on current temperature,
1939          * ignoring any previous power measurements */
1940         iwl3945_hw_reg_comp_txpower_temp(priv);
1941
1942  reschedule:
1943         queue_delayed_work(priv->workqueue,
1944                            &priv->thermal_periodic, REG_RECALIB_PERIOD * HZ);
1945 }
1946
1947 static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
1948 {
1949         struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv,
1950                                              thermal_periodic.work);
1951
1952         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1953                 return;
1954
1955         mutex_lock(&priv->mutex);
1956         iwl3945_reg_txpower_periodic(priv);
1957         mutex_unlock(&priv->mutex);
1958 }
1959
1960 /**
1961  * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
1962  *                                 for the channel.
1963  *
1964  * This function is used when initializing channel-info structs.
1965  *
1966  * NOTE: These channel groups do *NOT* match the bands above!
1967  *       These channel groups are based on factory-tested channels;
1968  *       on A-band, EEPROM's "group frequency" entries represent the top
1969  *       channel in each group 1-4.  Group 5 All B/G channels are in group 0.
1970  */
1971 static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl3945_priv *priv,
1972                                        const struct iwl3945_channel_info *ch_info)
1973 {
1974         struct iwl3945_eeprom_txpower_group *ch_grp = &priv->eeprom.groups[0];
1975         u8 group;
1976         u16 group_index = 0;    /* based on factory calib frequencies */
1977         u8 grp_channel;
1978
1979         /* Find the group index for the channel ... don't use index 1(?) */
1980         if (is_channel_a_band(ch_info)) {
1981                 for (group = 1; group < 5; group++) {
1982                         grp_channel = ch_grp[group].group_channel;
1983                         if (ch_info->channel <= grp_channel) {
1984                                 group_index = group;
1985                                 break;
1986                         }
1987                 }
1988                 /* group 4 has a few channels *above* its factory cal freq */
1989                 if (group == 5)
1990                         group_index = 4;
1991         } else
1992                 group_index = 0;        /* 2.4 GHz, group 0 */
1993
1994         IWL_DEBUG_POWER("Chnl %d mapped to grp %d\n", ch_info->channel,
1995                         group_index);
1996         return group_index;
1997 }
1998
1999 /**
2000  * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
2001  *
2002  * Interpolate to get nominal (i.e. at factory calibration temperature) index
2003  *   into radio/DSP gain settings table for requested power.
2004  */
2005 static int iwl3945_hw_reg_get_matched_power_index(struct iwl3945_priv *priv,
2006                                        s8 requested_power,
2007                                        s32 setting_index, s32 *new_index)
2008 {
2009         const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
2010         s32 index0, index1;
2011         s32 power = 2 * requested_power;
2012         s32 i;
2013         const struct iwl3945_eeprom_txpower_sample *samples;
2014         s32 gains0, gains1;
2015         s32 res;
2016         s32 denominator;
2017
2018         chnl_grp = &priv->eeprom.groups[setting_index];
2019         samples = chnl_grp->samples;
2020         for (i = 0; i < 5; i++) {
2021                 if (power == samples[i].power) {
2022                         *new_index = samples[i].gain_index;
2023                         return 0;
2024                 }
2025         }
2026
2027         if (power > samples[1].power) {
2028                 index0 = 0;
2029                 index1 = 1;
2030         } else if (power > samples[2].power) {
2031                 index0 = 1;
2032                 index1 = 2;
2033         } else if (power > samples[3].power) {
2034                 index0 = 2;
2035                 index1 = 3;
2036         } else {
2037                 index0 = 3;
2038                 index1 = 4;
2039         }
2040
2041         denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2042         if (denominator == 0)
2043                 return -EINVAL;
2044         gains0 = (s32) samples[index0].gain_index * (1 << 19);
2045         gains1 = (s32) samples[index1].gain_index * (1 << 19);
2046         res = gains0 + (gains1 - gains0) *
2047             ((s32) power - (s32) samples[index0].power) / denominator +
2048             (1 << 18);
2049         *new_index = res >> 19;
2050         return 0;
2051 }
2052
2053 static void iwl3945_hw_reg_init_channel_groups(struct iwl3945_priv *priv)
2054 {
2055         u32 i;
2056         s32 rate_index;
2057         const struct iwl3945_eeprom_txpower_group *group;
2058
2059         IWL_DEBUG_POWER("Initializing factory calib info from EEPROM\n");
2060
2061         for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2062                 s8 *clip_pwrs;  /* table of power levels for each rate */
2063                 s8 satur_pwr;   /* saturation power for each chnl group */
2064                 group = &priv->eeprom.groups[i];
2065
2066                 /* sanity check on factory saturation power value */
2067                 if (group->saturation_power < 40) {
2068                         IWL_WARNING("Error: saturation power is %d, "
2069                                     "less than minimum expected 40\n",
2070                                     group->saturation_power);
2071                         return;
2072                 }
2073
2074                 /*
2075                  * Derive requested power levels for each rate, based on
2076                  *   hardware capabilities (saturation power for band).
2077                  * Basic value is 3dB down from saturation, with further
2078                  *   power reductions for highest 3 data rates.  These
2079                  *   backoffs provide headroom for high rate modulation
2080                  *   power peaks, without too much distortion (clipping).
2081                  */
2082                 /* we'll fill in this array with h/w max power levels */
2083                 clip_pwrs = (s8 *) priv->clip_groups[i].clip_powers;
2084
2085                 /* divide factory saturation power by 2 to find -3dB level */
2086                 satur_pwr = (s8) (group->saturation_power >> 1);
2087
2088                 /* fill in channel group's nominal powers for each rate */
2089                 for (rate_index = 0;
2090                      rate_index < IWL_RATE_COUNT; rate_index++, clip_pwrs++) {
2091                         switch (rate_index) {
2092                         case IWL_RATE_36M_INDEX_TABLE:
2093                                 if (i == 0)     /* B/G */
2094                                         *clip_pwrs = satur_pwr;
2095                                 else    /* A */
2096                                         *clip_pwrs = satur_pwr - 5;
2097                                 break;
2098                         case IWL_RATE_48M_INDEX_TABLE:
2099                                 if (i == 0)
2100                                         *clip_pwrs = satur_pwr - 7;
2101                                 else
2102                                         *clip_pwrs = satur_pwr - 10;
2103                                 break;
2104                         case IWL_RATE_54M_INDEX_TABLE:
2105                                 if (i == 0)
2106                                         *clip_pwrs = satur_pwr - 9;
2107                                 else
2108                                         *clip_pwrs = satur_pwr - 12;
2109                                 break;
2110                         default:
2111                                 *clip_pwrs = satur_pwr;
2112                                 break;
2113                         }
2114                 }
2115         }
2116 }
2117
2118 /**
2119  * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2120  *
2121  * Second pass (during init) to set up priv->channel_info
2122  *
2123  * Set up Tx-power settings in our channel info database for each VALID
2124  * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2125  * and current temperature.
2126  *
2127  * Since this is based on current temperature (at init time), these values may
2128  * not be valid for very long, but it gives us a starting/default point,
2129  * and allows us to active (i.e. using Tx) scan.
2130  *
2131  * This does *not* write values to NIC, just sets up our internal table.
2132  */
2133 int iwl3945_txpower_set_from_eeprom(struct iwl3945_priv *priv)
2134 {
2135         struct iwl3945_channel_info *ch_info = NULL;
2136         struct iwl3945_channel_power_info *pwr_info;
2137         int delta_index;
2138         u8 rate_index;
2139         u8 scan_tbl_index;
2140         const s8 *clip_pwrs;    /* array of power levels for each rate */
2141         u8 gain, dsp_atten;
2142         s8 power;
2143         u8 pwr_index, base_pwr_index, a_band;
2144         u8 i;
2145         int temperature;
2146
2147         /* save temperature reference,
2148          *   so we can determine next time to calibrate */
2149         temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
2150         priv->last_temperature = temperature;
2151
2152         iwl3945_hw_reg_init_channel_groups(priv);
2153
2154         /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2155         for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2156              i++, ch_info++) {
2157                 a_band = is_channel_a_band(ch_info);
2158                 if (!is_channel_valid(ch_info))
2159                         continue;
2160
2161                 /* find this channel's channel group (*not* "band") index */
2162                 ch_info->group_index =
2163                         iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
2164
2165                 /* Get this chnlgrp's rate->max/clip-powers table */
2166                 clip_pwrs = priv->clip_groups[ch_info->group_index].clip_powers;
2167
2168                 /* calculate power index *adjustment* value according to
2169                  *  diff between current temperature and factory temperature */
2170                 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
2171                                 priv->eeprom.groups[ch_info->group_index].
2172                                 temperature);
2173
2174                 IWL_DEBUG_POWER("Delta index for channel %d: %d [%d]\n",
2175                                 ch_info->channel, delta_index, temperature +
2176                                 IWL_TEMP_CONVERT);
2177
2178                 /* set tx power value for all OFDM rates */
2179                 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2180                      rate_index++) {
2181                         s32 power_idx;
2182                         int rc;
2183
2184                         /* use channel group's clip-power table,
2185                          *   but don't exceed channel's max power */
2186                         s8 pwr = min(ch_info->max_power_avg,
2187                                      clip_pwrs[rate_index]);
2188
2189                         pwr_info = &ch_info->power_info[rate_index];
2190
2191                         /* get base (i.e. at factory-measured temperature)
2192                          *    power table index for this rate's power */
2193                         rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
2194                                                          ch_info->group_index,
2195                                                          &power_idx);
2196                         if (rc) {
2197                                 IWL_ERROR("Invalid power index\n");
2198                                 return rc;
2199                         }
2200                         pwr_info->base_power_index = (u8) power_idx;
2201
2202                         /* temperature compensate */
2203                         power_idx += delta_index;
2204
2205                         /* stay within range of gain table */
2206                         power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
2207
2208                         /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
2209                         pwr_info->requested_power = pwr;
2210                         pwr_info->power_table_index = (u8) power_idx;
2211                         pwr_info->tpc.tx_gain =
2212                             power_gain_table[a_band][power_idx].tx_gain;
2213                         pwr_info->tpc.dsp_atten =
2214                             power_gain_table[a_band][power_idx].dsp_atten;
2215                 }
2216
2217                 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
2218                 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
2219                 power = pwr_info->requested_power +
2220                         IWL_CCK_FROM_OFDM_POWER_DIFF;
2221                 pwr_index = pwr_info->power_table_index +
2222                         IWL_CCK_FROM_OFDM_INDEX_DIFF;
2223                 base_pwr_index = pwr_info->base_power_index +
2224                         IWL_CCK_FROM_OFDM_INDEX_DIFF;
2225
2226                 /* stay within table range */
2227                 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
2228                 gain = power_gain_table[a_band][pwr_index].tx_gain;
2229                 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2230
2231                 /* fill each CCK rate's iwl3945_channel_power_info structure
2232                  * NOTE:  All CCK-rate Txpwrs are the same for a given chnl!
2233                  * NOTE:  CCK rates start at end of OFDM rates! */
2234                 for (rate_index = 0;
2235                      rate_index < IWL_CCK_RATES; rate_index++) {
2236                         pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
2237                         pwr_info->requested_power = power;
2238                         pwr_info->power_table_index = pwr_index;
2239                         pwr_info->base_power_index = base_pwr_index;
2240                         pwr_info->tpc.tx_gain = gain;
2241                         pwr_info->tpc.dsp_atten = dsp_atten;
2242                 }
2243
2244                 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2245                 for (scan_tbl_index = 0;
2246                      scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2247                         s32 actual_index = (scan_tbl_index == 0) ?
2248                                 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
2249                         iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
2250                                 actual_index, clip_pwrs, ch_info, a_band);
2251                 }
2252         }
2253
2254         return 0;
2255 }
2256
2257 int iwl3945_hw_rxq_stop(struct iwl3945_priv *priv)
2258 {
2259         int rc;
2260         unsigned long flags;
2261
2262         spin_lock_irqsave(&priv->lock, flags);
2263         rc = iwl3945_grab_nic_access(priv);
2264         if (rc) {
2265                 spin_unlock_irqrestore(&priv->lock, flags);
2266                 return rc;
2267         }
2268
2269         iwl3945_write_direct32(priv, FH_RCSR_CONFIG(0), 0);
2270         rc = iwl3945_poll_direct_bit(priv, FH_RSSR_STATUS, (1 << 24), 1000);
2271         if (rc < 0)
2272                 IWL_ERROR("Can't stop Rx DMA.\n");
2273
2274         iwl3945_release_nic_access(priv);
2275         spin_unlock_irqrestore(&priv->lock, flags);
2276
2277         return 0;
2278 }
2279
2280 int iwl3945_hw_tx_queue_init(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
2281 {
2282         int rc;
2283         unsigned long flags;
2284         int txq_id = txq->q.id;
2285
2286         struct iwl3945_shared *shared_data = priv->hw_setting.shared_virt;
2287
2288         shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2289
2290         spin_lock_irqsave(&priv->lock, flags);
2291         rc = iwl3945_grab_nic_access(priv);
2292         if (rc) {
2293                 spin_unlock_irqrestore(&priv->lock, flags);
2294                 return rc;
2295         }
2296         iwl3945_write_direct32(priv, FH_CBCC_CTRL(txq_id), 0);
2297         iwl3945_write_direct32(priv, FH_CBCC_BASE(txq_id), 0);
2298
2299         iwl3945_write_direct32(priv, FH_TCSR_CONFIG(txq_id),
2300                 ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2301                 ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2302                 ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2303                 ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2304                 ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
2305         iwl3945_release_nic_access(priv);
2306
2307         /* fake read to flush all prev. writes */
2308         iwl3945_read32(priv, FH_TSSR_CBB_BASE);
2309         spin_unlock_irqrestore(&priv->lock, flags);
2310
2311         return 0;
2312 }
2313
2314 int iwl3945_hw_get_rx_read(struct iwl3945_priv *priv)
2315 {
2316         struct iwl3945_shared *shared_data = priv->hw_setting.shared_virt;
2317
2318         return le32_to_cpu(shared_data->rx_read_ptr[0]);
2319 }
2320
2321 /**
2322  * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2323  */
2324 int iwl3945_init_hw_rate_table(struct iwl3945_priv *priv)
2325 {
2326         int rc, i, index, prev_index;
2327         struct iwl3945_rate_scaling_cmd rate_cmd = {
2328                 .reserved = {0, 0, 0},
2329         };
2330         struct iwl3945_rate_scaling_info *table = rate_cmd.table;
2331
2332         for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2333                 index = iwl3945_rates[i].table_rs_index;
2334
2335                 table[index].rate_n_flags =
2336                         iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
2337                 table[index].try_cnt = priv->retry_rate;
2338                 prev_index = iwl3945_get_prev_ieee_rate(i);
2339                 table[index].next_rate_index = iwl3945_rates[prev_index].table_rs_index;
2340         }
2341
2342         switch (priv->band) {
2343         case IEEE80211_BAND_5GHZ:
2344                 IWL_DEBUG_RATE("Select A mode rate scale\n");
2345                 /* If one of the following CCK rates is used,
2346                  * have it fall back to the 6M OFDM rate */
2347                 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++)
2348                         table[i].next_rate_index = iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2349
2350                 /* Don't fall back to CCK rates */
2351                 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index = IWL_RATE_9M_INDEX_TABLE;
2352
2353                 /* Don't drop out of OFDM rates */
2354                 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
2355                     iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2356                 break;
2357
2358         case IEEE80211_BAND_2GHZ:
2359                 IWL_DEBUG_RATE("Select B/G mode rate scale\n");
2360                 /* If an OFDM rate is used, have it fall back to the
2361                  * 1M CCK rates */
2362                 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE; i++)
2363                         table[i].next_rate_index = iwl3945_rates[IWL_FIRST_CCK_RATE].table_rs_index;
2364
2365                 /* CCK shouldn't fall back to OFDM... */
2366                 table[IWL_RATE_11M_INDEX_TABLE].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2367                 break;
2368
2369         default:
2370                 WARN_ON(1);
2371                 break;
2372         }
2373
2374         /* Update the rate scaling for control frame Tx */
2375         rate_cmd.table_id = 0;
2376         rc = iwl3945_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2377                               &rate_cmd);
2378         if (rc)
2379                 return rc;
2380
2381         /* Update the rate scaling for data frame Tx */
2382         rate_cmd.table_id = 1;
2383         return iwl3945_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2384                                 &rate_cmd);
2385 }
2386
2387 /* Called when initializing driver */
2388 int iwl3945_hw_set_hw_setting(struct iwl3945_priv *priv)
2389 {
2390         memset((void *)&priv->hw_setting, 0,
2391                sizeof(struct iwl3945_driver_hw_info));
2392
2393         priv->hw_setting.shared_virt =
2394             pci_alloc_consistent(priv->pci_dev,
2395                                  sizeof(struct iwl3945_shared),
2396                                  &priv->hw_setting.shared_phys);
2397
2398         if (!priv->hw_setting.shared_virt) {
2399                 IWL_ERROR("failed to allocate pci memory\n");
2400                 mutex_unlock(&priv->mutex);
2401                 return -ENOMEM;
2402         }
2403
2404         priv->hw_setting.rx_buf_size = IWL_RX_BUF_SIZE;
2405         priv->hw_setting.max_pkt_size = 2342;
2406         priv->hw_setting.tx_cmd_len = sizeof(struct iwl3945_tx_cmd);
2407         priv->hw_setting.max_rxq_size = RX_QUEUE_SIZE;
2408         priv->hw_setting.max_rxq_log = RX_QUEUE_SIZE_LOG;
2409         priv->hw_setting.max_stations = IWL3945_STATION_COUNT;
2410         priv->hw_setting.bcast_sta_id = IWL3945_BROADCAST_ID;
2411
2412         priv->hw_setting.tx_ant_num = 2;
2413         return 0;
2414 }
2415
2416 unsigned int iwl3945_hw_get_beacon_cmd(struct iwl3945_priv *priv,
2417                           struct iwl3945_frame *frame, u8 rate)
2418 {
2419         struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
2420         unsigned int frame_size;
2421
2422         tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
2423         memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2424
2425         tx_beacon_cmd->tx.sta_id = priv->hw_setting.bcast_sta_id;
2426         tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2427
2428         frame_size = iwl3945_fill_beacon_frame(priv,
2429                                 tx_beacon_cmd->frame,
2430                                 iwl3945_broadcast_addr,
2431                                 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2432
2433         BUG_ON(frame_size > MAX_MPDU_SIZE);
2434         tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2435
2436         tx_beacon_cmd->tx.rate = rate;
2437         tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2438                                       TX_CMD_FLG_TSF_MSK);
2439
2440         /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2441         tx_beacon_cmd->tx.supp_rates[0] =
2442                 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2443
2444         tx_beacon_cmd->tx.supp_rates[1] =
2445                 (IWL_CCK_BASIC_RATES_MASK & 0xF);
2446
2447         return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
2448 }
2449
2450 void iwl3945_hw_rx_handler_setup(struct iwl3945_priv *priv)
2451 {
2452         priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
2453         priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2454 }
2455
2456 void iwl3945_hw_setup_deferred_work(struct iwl3945_priv *priv)
2457 {
2458         INIT_DELAYED_WORK(&priv->thermal_periodic,
2459                           iwl3945_bg_reg_txpower_periodic);
2460 }
2461
2462 void iwl3945_hw_cancel_deferred_work(struct iwl3945_priv *priv)
2463 {
2464         cancel_delayed_work(&priv->thermal_periodic);
2465 }
2466
2467 static struct iwl_3945_cfg iwl3945_bg_cfg = {
2468         .name = "3945BG",
2469         .fw_name = "iwlwifi-3945" IWL3945_UCODE_API ".ucode",
2470         .sku = IWL_SKU_G,
2471 };
2472
2473 static struct iwl_3945_cfg iwl3945_abg_cfg = {
2474         .name = "3945ABG",
2475         .fw_name = "iwlwifi-3945" IWL3945_UCODE_API ".ucode",
2476         .sku = IWL_SKU_A|IWL_SKU_G,
2477 };
2478
2479 struct pci_device_id iwl3945_hw_card_ids[] = {
2480         {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2481         {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2482         {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2483         {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2484         {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2485         {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
2486         {0}
2487 };
2488
2489 MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);