SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/iwlwifi/iwl-3945.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  *  Intel Linux Wireless <ilw@linux.intel.com>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  *****************************************************************************/
  26
  27 #include <linux/kernel.h>
  28 #include <linux/module.h>
  29 #include <linux/init.h>
  30 #include <linux/pci.h>
  31 #include <linux/dma-mapping.h>
  32 #include <linux/delay.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/netdevice.h>
  35 #include <linux/wireless.h>
  36 #include <linux/firmware.h>
  37 #include <linux/etherdevice.h>
  38 #include <asm/unaligned.h>
  39 #include <net/mac80211.h>
  40
  41 #include "iwl-fh.h"
  42 #include "iwl-3945-fh.h"
  43 #include "iwl-commands.h"
  44 #include "iwl-3945.h"
  45 #include "iwl-eeprom.h"
  46 #include "iwl-helpers.h"
  47 #include "iwl-core.h"
  48 #include "iwl-agn-rs.h"
  49
  50 #define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np)    \
  51         [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP,   \
  52                                     IWL_RATE_##r##M_IEEE,   \
  53                                     IWL_RATE_##ip##M_INDEX, \
  54                                     IWL_RATE_##in##M_INDEX, \
  55                                     IWL_RATE_##rp##M_INDEX, \
  56                                     IWL_RATE_##rn##M_INDEX, \
  57                                     IWL_RATE_##pp##M_INDEX, \
  58                                     IWL_RATE_##np##M_INDEX, \
  59                                     IWL_RATE_##r##M_INDEX_TABLE, \
  60                                     IWL_RATE_##ip##M_INDEX_TABLE }
  61
  62 /*
  63  * Parameter order:
  64  *   rate, prev rate, next rate, prev tgg rate, next tgg rate
  65  *
  66  * If there isn't a valid next or previous rate then INV is used which
  67  * maps to IWL_RATE_INVALID
  68  *
  69  */
  70 const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
  71         IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2),    /*  1mbps */
  72         IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5),          /*  2mbps */
  73         IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11),        /*5.5mbps */
  74         IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18),      /* 11mbps */
  75         IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11),        /*  6mbps */
  76         IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11),       /*  9mbps */
  77         IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18),   /* 12mbps */
  78         IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24),   /* 18mbps */
  79         IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36),   /* 24mbps */
  80         IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48),   /* 36mbps */
  81         IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54),   /* 48mbps */
  82         IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
  83 };
  84
  85 /* 1 = enable the iwl3945_disable_events() function */
  86 #define IWL_EVT_DISABLE (0)
  87 #define IWL_EVT_DISABLE_SIZE (1532/32)
  88
  89 /**
  90  * iwl3945_disable_events - Disable selected events in uCode event log
  91  *
  92  * Disable an event by writing "1"s into "disable"
  93  *   bitmap in SRAM.  Bit position corresponds to Event # (id/type).
  94  *   Default values of 0 enable uCode events to be logged.
  95  * Use for only special debugging.  This function is just a placeholder as-is,
  96  *   you'll need to provide the special bits! ...
  97  *   ... and set IWL_EVT_DISABLE to 1. */
  98 void iwl3945_disable_events(struct iwl_priv *priv)
  99 {
 100         int ret;
 101         int i;
 102         u32 base;               /* SRAM address of event log header */
 103         u32 disable_ptr;        /* SRAM address of event-disable bitmap array */
 104         u32 array_size;         /* # of u32 entries in array */
 105         u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
 106                 0x00000000,     /*   31 -    0  Event id numbers */
 107                 0x00000000,     /*   63 -   32 */
 108                 0x00000000,     /*   95 -   64 */
 109                 0x00000000,     /*  127 -   96 */
 110                 0x00000000,     /*  159 -  128 */
 111                 0x00000000,     /*  191 -  160 */
 112                 0x00000000,     /*  223 -  192 */
 113                 0x00000000,     /*  255 -  224 */
 114                 0x00000000,     /*  287 -  256 */
 115                 0x00000000,     /*  319 -  288 */
 116                 0x00000000,     /*  351 -  320 */
 117                 0x00000000,     /*  383 -  352 */
 118                 0x00000000,     /*  415 -  384 */
 119                 0x00000000,     /*  447 -  416 */
 120                 0x00000000,     /*  479 -  448 */
 121                 0x00000000,     /*  511 -  480 */
 122                 0x00000000,     /*  543 -  512 */
 123                 0x00000000,     /*  575 -  544 */
 124                 0x00000000,     /*  607 -  576 */
 125                 0x00000000,     /*  639 -  608 */
 126                 0x00000000,     /*  671 -  640 */
 127                 0x00000000,     /*  703 -  672 */
 128                 0x00000000,     /*  735 -  704 */
 129                 0x00000000,     /*  767 -  736 */
 130                 0x00000000,     /*  799 -  768 */
 131                 0x00000000,     /*  831 -  800 */
 132                 0x00000000,     /*  863 -  832 */
 133                 0x00000000,     /*  895 -  864 */
 134                 0x00000000,     /*  927 -  896 */
 135                 0x00000000,     /*  959 -  928 */
 136                 0x00000000,     /*  991 -  960 */
 137                 0x00000000,     /* 1023 -  992 */
 138                 0x00000000,     /* 1055 - 1024 */
 139                 0x00000000,     /* 1087 - 1056 */
 140                 0x00000000,     /* 1119 - 1088 */
 141                 0x00000000,     /* 1151 - 1120 */
 142                 0x00000000,     /* 1183 - 1152 */
 143                 0x00000000,     /* 1215 - 1184 */
 144                 0x00000000,     /* 1247 - 1216 */
 145                 0x00000000,     /* 1279 - 1248 */
 146                 0x00000000,     /* 1311 - 1280 */
 147                 0x00000000,     /* 1343 - 1312 */
 148                 0x00000000,     /* 1375 - 1344 */
 149                 0x00000000,     /* 1407 - 1376 */
 150                 0x00000000,     /* 1439 - 1408 */
 151                 0x00000000,     /* 1471 - 1440 */
 152                 0x00000000,     /* 1503 - 1472 */
 153         };
 154
 155         base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
 156         if (!iwl3945_hw_valid_rtc_data_addr(base)) {
 157                 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
 158                 return;
 159         }
 160
 161         ret = iwl_grab_nic_access(priv);
 162         if (ret) {
 163                 IWL_WARN(priv, "Can not read from adapter at this time.\n");
 164                 return;
 165         }
 166
 167         disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
 168         array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
 169         iwl_release_nic_access(priv);
 170
 171         if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
 172                 IWL_DEBUG_INFO("Disabling selected uCode log events at 0x%x\n",
 173                                disable_ptr);
 174                 ret = iwl_grab_nic_access(priv);
 175                 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
 176                         iwl_write_targ_mem(priv,
 177                                            disable_ptr + (i * sizeof(u32)),
 178                                            evt_disable[i]);
 179
 180                 iwl_release_nic_access(priv);
 181         } else {
 182                 IWL_DEBUG_INFO("Selected uCode log events may be disabled\n");
 183                 IWL_DEBUG_INFO("  by writing \"1\"s into disable bitmap\n");
 184                 IWL_DEBUG_INFO("  in SRAM at 0x%x, size %d u32s\n",
 185                                disable_ptr, array_size);
 186         }
 187
 188 }
 189
 190 static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
 191 {
 192         int idx;
 193
 194         for (idx = 0; idx < IWL_RATE_COUNT; idx++)
 195                 if (iwl3945_rates[idx].plcp == plcp)
 196                         return idx;
 197         return -1;
 198 }
 199
 200 /**
 201  * iwl3945_get_antenna_flags - Get antenna flags for RXON command
 202  * @priv: eeprom and antenna fields are used to determine antenna flags
 203  *
 204  * priv->eeprom39  is used to determine if antenna AUX/MAIN are reversed
 205  * priv->antenna specifies the antenna diversity mode:
 206  *
 207  * IWL_ANTENNA_DIVERSITY - NIC selects best antenna by itself
 208  * IWL_ANTENNA_MAIN      - Force MAIN antenna
 209  * IWL_ANTENNA_AUX       - Force AUX antenna
 210  */
 211 __le32 iwl3945_get_antenna_flags(const struct iwl_priv *priv)
 212 {
 213         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
 214
 215         switch (priv->antenna) {
 216         case IWL_ANTENNA_DIVERSITY:
 217                 return 0;
 218
 219         case IWL_ANTENNA_MAIN:
 220                 if (eeprom->antenna_switch_type)
 221                         return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
 222                 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
 223
 224         case IWL_ANTENNA_AUX:
 225                 if (eeprom->antenna_switch_type)
 226                         return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
 227                 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
 228         }
 229
 230         /* bad antenna selector value */
 231         IWL_ERR(priv, "Bad antenna selector value (0x%x)\n", priv->antenna);
 232         return 0;               /* "diversity" is default if error */
 233 }
 234
 235 #ifdef CONFIG_IWLWIFI_DEBUG
 236 #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
 237
 238 static const char *iwl3945_get_tx_fail_reason(u32 status)
 239 {
 240         switch (status & TX_STATUS_MSK) {
 241         case TX_STATUS_SUCCESS:
 242                 return "SUCCESS";
 243                 TX_STATUS_ENTRY(SHORT_LIMIT);
 244                 TX_STATUS_ENTRY(LONG_LIMIT);
 245                 TX_STATUS_ENTRY(FIFO_UNDERRUN);
 246                 TX_STATUS_ENTRY(MGMNT_ABORT);
 247                 TX_STATUS_ENTRY(NEXT_FRAG);
 248                 TX_STATUS_ENTRY(LIFE_EXPIRE);
 249                 TX_STATUS_ENTRY(DEST_PS);
 250                 TX_STATUS_ENTRY(ABORTED);
 251                 TX_STATUS_ENTRY(BT_RETRY);
 252                 TX_STATUS_ENTRY(STA_INVALID);
 253                 TX_STATUS_ENTRY(FRAG_DROPPED);
 254                 TX_STATUS_ENTRY(TID_DISABLE);
 255                 TX_STATUS_ENTRY(FRAME_FLUSHED);
 256                 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
 257                 TX_STATUS_ENTRY(TX_LOCKED);
 258                 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
 259         }
 260
 261         return "UNKNOWN";
 262 }
 263 #else
 264 static inline const char *iwl3945_get_tx_fail_reason(u32 status)
 265 {
 266         return "";
 267 }
 268 #endif
 269
 270 /*
 271  * get ieee prev rate from rate scale table.
 272  * for A and B mode we need to overright prev
 273  * value
 274  */
 275 int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
 276 {
 277         int next_rate = iwl3945_get_prev_ieee_rate(rate);
 278
 279         switch (priv->band) {
 280         case IEEE80211_BAND_5GHZ:
 281                 if (rate == IWL_RATE_12M_INDEX)
 282                         next_rate = IWL_RATE_9M_INDEX;
 283                 else if (rate == IWL_RATE_6M_INDEX)
 284                         next_rate = IWL_RATE_6M_INDEX;
 285                 break;
 286         case IEEE80211_BAND_2GHZ:
 287                 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
 288                     iwl3945_is_associated(priv)) {
 289                         if (rate == IWL_RATE_11M_INDEX)
 290                                 next_rate = IWL_RATE_5M_INDEX;
 291                 }
 292                 break;
 293
 294         default:
 295                 break;
 296         }
 297
 298         return next_rate;
 299 }
 300
 301
 302 /**
 303  * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
 304  *
 305  * When FW advances 'R' index, all entries between old and new 'R' index
 306  * need to be reclaimed. As result, some free space forms. If there is
 307  * enough free space (> low mark), wake the stack that feeds us.
 308  */
 309 static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
 310                                      int txq_id, int index)
 311 {
 312         struct iwl_tx_queue *txq = &priv->txq[txq_id];
 313         struct iwl_queue *q = &txq->q;
 314         struct iwl_tx_info *tx_info;
 315
 316         BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
 317
 318         for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
 319                 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
 320
 321                 tx_info = &txq->txb[txq->q.read_ptr];
 322                 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
 323                 tx_info->skb[0] = NULL;
 324                 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
 325         }
 326
 327         if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
 328                         (txq_id != IWL_CMD_QUEUE_NUM) &&
 329                         priv->mac80211_registered)
 330                 ieee80211_wake_queue(priv->hw, txq_id);
 331 }
 332
 333 /**
 334  * iwl3945_rx_reply_tx - Handle Tx response
 335  */
 336 static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
 337                             struct iwl_rx_mem_buffer *rxb)
 338 {
 339         struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
 340         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
 341         int txq_id = SEQ_TO_QUEUE(sequence);
 342         int index = SEQ_TO_INDEX(sequence);
 343         struct iwl_tx_queue *txq = &priv->txq[txq_id];
 344         struct ieee80211_tx_info *info;
 345         struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
 346         u32  status = le32_to_cpu(tx_resp->status);
 347         int rate_idx;
 348         int fail;
 349
 350         if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
 351                 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
 352                           "is out of range [0-%d] %d %d\n", txq_id,
 353                           index, txq->q.n_bd, txq->q.write_ptr,
 354                           txq->q.read_ptr);
 355                 return;
 356         }
 357
 358         info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
 359         ieee80211_tx_info_clear_status(info);
 360
 361         /* Fill the MRR chain with some info about on-chip retransmissions */
 362         rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
 363         if (info->band == IEEE80211_BAND_5GHZ)
 364                 rate_idx -= IWL_FIRST_OFDM_RATE;
 365
 366         fail = tx_resp->failure_frame;
 367
 368         info->status.rates[0].idx = rate_idx;
 369         info->status.rates[0].count = fail + 1; /* add final attempt */
 370
 371         /* tx_status->rts_retry_count = tx_resp->failure_rts; */
 372         info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
 373                                 IEEE80211_TX_STAT_ACK : 0;
 374
 375         IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
 376                         txq_id, iwl3945_get_tx_fail_reason(status), status,
 377                         tx_resp->rate, tx_resp->failure_frame);
 378
 379         IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
 380         iwl3945_tx_queue_reclaim(priv, txq_id, index);
 381
 382         if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
 383                 IWL_ERR(priv, "TODO:  Implement Tx ABORT REQUIRED!!!\n");
 384 }
 385
 386
 387
 388 /*****************************************************************************
 389  *
 390  * Intel PRO/Wireless 3945ABG/BG Network Connection
 391  *
 392  *  RX handler implementations
 393  *
 394  *****************************************************************************/
 395
 396 void iwl3945_hw_rx_statistics(struct iwl_priv *priv, struct iwl_rx_mem_buffer *rxb)
 397 {
 398         struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
 399         IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
 400                      (int)sizeof(struct iwl3945_notif_statistics),
 401                      le32_to_cpu(pkt->len));
 402
 403         memcpy(&priv->statistics_39, pkt->u.raw, sizeof(priv->statistics_39));
 404
 405         iwl3945_led_background(priv);
 406
 407         priv->last_statistics_time = jiffies;
 408 }
 409
 410 /******************************************************************************
 411  *
 412  * Misc. internal state and helper functions
 413  *
 414  ******************************************************************************/
 415 #ifdef CONFIG_IWLWIFI_DEBUG
 416
 417 /**
 418  * iwl3945_report_frame - dump frame to syslog during debug sessions
 419  *
 420  * You may hack this function to show different aspects of received frames,
 421  * including selective frame dumps.
 422  * group100 parameter selects whether to show 1 out of 100 good frames.
 423  */
 424 static void _iwl3945_dbg_report_frame(struct iwl_priv *priv,
 425                       struct iwl_rx_packet *pkt,
 426                       struct ieee80211_hdr *header, int group100)
 427 {
 428         u32 to_us;
 429         u32 print_summary = 0;
 430         u32 print_dump = 0;     /* set to 1 to dump all frames' contents */
 431         u32 hundred = 0;
 432         u32 dataframe = 0;
 433         __le16 fc;
 434         u16 seq_ctl;
 435         u16 channel;
 436         u16 phy_flags;
 437         u16 length;
 438         u16 status;
 439         u16 bcn_tmr;
 440         u32 tsf_low;
 441         u64 tsf;
 442         u8 rssi;
 443         u8 agc;
 444         u16 sig_avg;
 445         u16 noise_diff;
 446         struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
 447         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
 448         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
 449         u8 *data = IWL_RX_DATA(pkt);
 450
 451         /* MAC header */
 452         fc = header->frame_control;
 453         seq_ctl = le16_to_cpu(header->seq_ctrl);
 454
 455         /* metadata */
 456         channel = le16_to_cpu(rx_hdr->channel);
 457         phy_flags = le16_to_cpu(rx_hdr->phy_flags);
 458         length = le16_to_cpu(rx_hdr->len);
 459
 460         /* end-of-frame status and timestamp */
 461         status = le32_to_cpu(rx_end->status);
 462         bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
 463         tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
 464         tsf = le64_to_cpu(rx_end->timestamp);
 465
 466         /* signal statistics */
 467         rssi = rx_stats->rssi;
 468         agc = rx_stats->agc;
 469         sig_avg = le16_to_cpu(rx_stats->sig_avg);
 470         noise_diff = le16_to_cpu(rx_stats->noise_diff);
 471
 472         to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
 473
 474         /* if data frame is to us and all is good,
 475          *   (optionally) print summary for only 1 out of every 100 */
 476         if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
 477             cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
 478                 dataframe = 1;
 479                 if (!group100)
 480                         print_summary = 1;      /* print each frame */
 481                 else if (priv->framecnt_to_us < 100) {
 482                         priv->framecnt_to_us++;
 483                         print_summary = 0;
 484                 } else {
 485                         priv->framecnt_to_us = 0;
 486                         print_summary = 1;
 487                         hundred = 1;
 488                 }
 489         } else {
 490                 /* print summary for all other frames */
 491                 print_summary = 1;
 492         }
 493
 494         if (print_summary) {
 495                 char *title;
 496                 int rate;
 497
 498                 if (hundred)
 499                         title = "100Frames";
 500                 else if (ieee80211_has_retry(fc))
 501                         title = "Retry";
 502                 else if (ieee80211_is_assoc_resp(fc))
 503                         title = "AscRsp";
 504                 else if (ieee80211_is_reassoc_resp(fc))
 505                         title = "RasRsp";
 506                 else if (ieee80211_is_probe_resp(fc)) {
 507                         title = "PrbRsp";
 508                         print_dump = 1; /* dump frame contents */
 509                 } else if (ieee80211_is_beacon(fc)) {
 510                         title = "Beacon";
 511                         print_dump = 1; /* dump frame contents */
 512                 } else if (ieee80211_is_atim(fc))
 513                         title = "ATIM";
 514                 else if (ieee80211_is_auth(fc))
 515                         title = "Auth";
 516                 else if (ieee80211_is_deauth(fc))
 517                         title = "DeAuth";
 518                 else if (ieee80211_is_disassoc(fc))
 519                         title = "DisAssoc";
 520                 else
 521                         title = "Frame";
 522
 523                 rate = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
 524                 if (rate == -1)
 525                         rate = 0;
 526                 else
 527                         rate = iwl3945_rates[rate].ieee / 2;
 528
 529                 /* print frame summary.
 530                  * MAC addresses show just the last byte (for brevity),
 531                  *    but you can hack it to show more, if you'd like to. */
 532                 if (dataframe)
 533                         IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
 534                                      "len=%u, rssi=%d, chnl=%d, rate=%d, \n",
 535                                      title, le16_to_cpu(fc), header->addr1[5],
 536                                      length, rssi, channel, rate);
 537                 else {
 538                         /* src/dst addresses assume managed mode */
 539                         IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
 540                                      "src=0x%02x, rssi=%u, tim=%lu usec, "
 541                                      "phy=0x%02x, chnl=%d\n",
 542                                      title, le16_to_cpu(fc), header->addr1[5],
 543                                      header->addr3[5], rssi,
 544                                      tsf_low - priv->scan_start_tsf,
 545                                      phy_flags, channel);
 546                 }
 547         }
 548         if (print_dump)
 549                 iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
 550 }
 551
 552 static void iwl3945_dbg_report_frame(struct iwl_priv *priv,
 553                       struct iwl_rx_packet *pkt,
 554                       struct ieee80211_hdr *header, int group100)
 555 {
 556         if (priv->debug_level & IWL_DL_RX)
 557                 _iwl3945_dbg_report_frame(priv, pkt, header, group100);
 558 }
 559
 560 #else
 561 static inline void iwl3945_dbg_report_frame(struct iwl_priv *priv,
 562                       struct iwl_rx_packet *pkt,
 563                       struct ieee80211_hdr *header, int group100)
 564 {
 565 }
 566 #endif
 567
 568 /* This is necessary only for a number of statistics, see the caller. */
 569 static int iwl3945_is_network_packet(struct iwl_priv *priv,
 570                 struct ieee80211_hdr *header)
 571 {
 572         /* Filter incoming packets to determine if they are targeted toward
 573          * this network, discarding packets coming from ourselves */
 574         switch (priv->iw_mode) {
 575         case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source    | BSSID */
 576                 /* packets to our IBSS update information */
 577                 return !compare_ether_addr(header->addr3, priv->bssid);
 578         case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
 579                 /* packets to our IBSS update information */
 580                 return !compare_ether_addr(header->addr2, priv->bssid);
 581         default:
 582                 return 1;
 583         }
 584 }
 585
 586 static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
 587                                    struct iwl_rx_mem_buffer *rxb,
 588                                    struct ieee80211_rx_status *stats)
 589 {
 590         struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
 591 #ifdef CONFIG_IWL3945_LEDS
 592         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
 593 #endif
 594         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
 595         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
 596         short len = le16_to_cpu(rx_hdr->len);
 597
 598         /* We received data from the HW, so stop the watchdog */
 599         if (unlikely((len + IWL39_RX_FRAME_SIZE) > skb_tailroom(rxb->skb))) {
 600                 IWL_DEBUG_DROP("Corruption detected!\n");
 601                 return;
 602         }
 603
 604         /* We only process data packets if the interface is open */
 605         if (unlikely(!priv->is_open)) {
 606                 IWL_DEBUG_DROP_LIMIT
 607                     ("Dropping packet while interface is not open.\n");
 608                 return;
 609         }
 610
 611         skb_reserve(rxb->skb, (void *)rx_hdr->payload - (void *)pkt);
 612         /* Set the size of the skb to the size of the frame */
 613         skb_put(rxb->skb, le16_to_cpu(rx_hdr->len));
 614
 615         if (!iwl3945_mod_params.sw_crypto)
 616                 iwl3945_set_decrypted_flag(priv, rxb->skb,
 617                                        le32_to_cpu(rx_end->status), stats);
 618
 619 #ifdef CONFIG_IWL3945_LEDS
 620         if (ieee80211_is_data(hdr->frame_control))
 621                 priv->rxtxpackets += len;
 622 #endif
 623         ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
 624         rxb->skb = NULL;
 625 }
 626
 627 #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
 628
 629 static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
 630                                 struct iwl_rx_mem_buffer *rxb)
 631 {
 632         struct ieee80211_hdr *header;
 633         struct ieee80211_rx_status rx_status;
 634         struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
 635         struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
 636         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
 637         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
 638         int snr;
 639         u16 rx_stats_sig_avg = le16_to_cpu(rx_stats->sig_avg);
 640         u16 rx_stats_noise_diff = le16_to_cpu(rx_stats->noise_diff);
 641         u8 network_packet;
 642
 643         rx_status.flag = 0;
 644         rx_status.mactime = le64_to_cpu(rx_end->timestamp);
 645         rx_status.freq =
 646                 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
 647         rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
 648                                 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
 649
 650         rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
 651         if (rx_status.band == IEEE80211_BAND_5GHZ)
 652                 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
 653
 654         rx_status.antenna = le16_to_cpu(rx_hdr->phy_flags &
 655                                         RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
 656
 657         /* set the preamble flag if appropriate */
 658         if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
 659                 rx_status.flag |= RX_FLAG_SHORTPRE;
 660
 661         if ((unlikely(rx_stats->phy_count > 20))) {
 662                 IWL_DEBUG_DROP
 663                     ("dsp size out of range [0,20]: "
 664                      "%d/n", rx_stats->phy_count);
 665                 return;
 666         }
 667
 668         if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
 669             || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
 670                 IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
 671                 return;
 672         }
 673
 674
 675
 676         /* Convert 3945's rssi indicator to dBm */
 677         rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
 678
 679         /* Set default noise value to -127 */
 680         if (priv->last_rx_noise == 0)
 681                 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
 682
 683         /* 3945 provides noise info for OFDM frames only.
 684          * sig_avg and noise_diff are measured by the 3945's digital signal
 685          *   processor (DSP), and indicate linear levels of signal level and
 686          *   distortion/noise within the packet preamble after
 687          *   automatic gain control (AGC).  sig_avg should stay fairly
 688          *   constant if the radio's AGC is working well.
 689          * Since these values are linear (not dB or dBm), linear
 690          *   signal-to-noise ratio (SNR) is (sig_avg / noise_diff).
 691          * Convert linear SNR to dB SNR, then subtract that from rssi dBm
 692          *   to obtain noise level in dBm.
 693          * Calculate rx_status.signal (quality indicator in %) based on SNR. */
 694         if (rx_stats_noise_diff) {
 695                 snr = rx_stats_sig_avg / rx_stats_noise_diff;
 696                 rx_status.noise = rx_status.signal -
 697                                         iwl3945_calc_db_from_ratio(snr);
 698                 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal,
 699                                                          rx_status.noise);
 700
 701         /* If noise info not available, calculate signal quality indicator (%)
 702          *   using just the dBm signal level. */
 703         } else {
 704                 rx_status.noise = priv->last_rx_noise;
 705                 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal, 0);
 706         }
 707
 708
 709         IWL_DEBUG_STATS("Rssi %d noise %d qual %d sig_avg %d noise_diff %d\n",
 710                         rx_status.signal, rx_status.noise, rx_status.qual,
 711                         rx_stats_sig_avg, rx_stats_noise_diff);
 712
 713         header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
 714
 715         network_packet = iwl3945_is_network_packet(priv, header);
 716
 717         IWL_DEBUG_STATS_LIMIT("[%c] %d RSSI:%d Signal:%u, Noise:%u, Rate:%u\n",
 718                               network_packet ? '*' : ' ',
 719                               le16_to_cpu(rx_hdr->channel),
 720                               rx_status.signal, rx_status.signal,
 721                               rx_status.noise, rx_status.rate_idx);
 722
 723         /* Set "1" to report good data frames in groups of 100 */
 724         iwl3945_dbg_report_frame(priv, pkt, header, 1);
 725
 726         if (network_packet) {
 727                 priv->last_beacon_time = le32_to_cpu(rx_end->beacon_timestamp);
 728                 priv->last_tsf = le64_to_cpu(rx_end->timestamp);
 729                 priv->last_rx_rssi = rx_status.signal;
 730                 priv->last_rx_noise = rx_status.noise;
 731         }
 732
 733         iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
 734 }
 735
 736 int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
 737                                      struct iwl_tx_queue *txq,
 738                                      dma_addr_t addr, u16 len, u8 reset, u8 pad)
 739 {
 740         int count;
 741         struct iwl_queue *q;
 742         struct iwl3945_tfd *tfd, *tfd_tmp;
 743
 744         q = &txq->q;
 745         tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
 746         tfd = &tfd_tmp[q->write_ptr];
 747
 748         if (reset)
 749                 memset(tfd, 0, sizeof(*tfd));
 750
 751         count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
 752
 753         if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
 754                 IWL_ERR(priv, "Error can not send more than %d chunks\n",
 755                           NUM_TFD_CHUNKS);
 756                 return -EINVAL;
 757         }
 758
 759         tfd->tbs[count].addr = cpu_to_le32(addr);
 760         tfd->tbs[count].len = cpu_to_le32(len);
 761
 762         count++;
 763
 764         tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
 765                                          TFD_CTL_PAD_SET(pad));
 766
 767         return 0;
 768 }
 769
 770 /**
 771  * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
 772  *
 773  * Does NOT advance any indexes
 774  */
 775 void iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
 776 {
 777         struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
 778         struct iwl3945_tfd *tfd = &tfd_tmp[txq->q.read_ptr];
 779         struct pci_dev *dev = priv->pci_dev;
 780         int i;
 781         int counter;
 782
 783         /* classify bd */
 784         if (txq->q.id == IWL_CMD_QUEUE_NUM)
 785                 /* nothing to cleanup after for host commands */
 786                 return;
 787
 788         /* sanity check */
 789         counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
 790         if (counter > NUM_TFD_CHUNKS) {
 791                 IWL_ERR(priv, "Too many chunks: %i\n", counter);
 792                 /* @todo issue fatal error, it is quite serious situation */
 793                 return;
 794         }
 795
 796         /* unmap chunks if any */
 797
 798         for (i = 1; i < counter; i++) {
 799                 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
 800                          le32_to_cpu(tfd->tbs[i].len), PCI_DMA_TODEVICE);
 801                 if (txq->txb[txq->q.read_ptr].skb[0]) {
 802                         struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
 803                         if (txq->txb[txq->q.read_ptr].skb[0]) {
 804                                 /* Can be called from interrupt context */
 805                                 dev_kfree_skb_any(skb);
 806                                 txq->txb[txq->q.read_ptr].skb[0] = NULL;
 807                         }
 808                 }
 809         }
 810         return ;
 811 }
 812
 813 u8 iwl3945_hw_find_station(struct iwl_priv *priv, const u8 *addr)
 814 {
 815         int i, start = IWL_AP_ID;
 816         int ret = IWL_INVALID_STATION;
 817         unsigned long flags;
 818
 819         if ((priv->iw_mode == NL80211_IFTYPE_ADHOC) ||
 820             (priv->iw_mode == NL80211_IFTYPE_AP))
 821                 start = IWL_STA_ID;
 822
 823         if (is_broadcast_ether_addr(addr))
 824                 return priv->hw_params.bcast_sta_id;
 825
 826         spin_lock_irqsave(&priv->sta_lock, flags);
 827         for (i = start; i < priv->hw_params.max_stations; i++)
 828                 if ((priv->stations_39[i].used) &&
 829                     (!compare_ether_addr
 830                      (priv->stations_39[i].sta.sta.addr, addr))) {
 831                         ret = i;
 832                         goto out;
 833                 }
 834
 835         IWL_DEBUG_INFO("can not find STA %pM (total %d)\n",
 836                        addr, priv->num_stations);
 837  out:
 838         spin_unlock_irqrestore(&priv->sta_lock, flags);
 839         return ret;
 840 }
 841
 842 /**
 843  * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
 844  *
 845 */
 846 void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv, struct iwl_cmd *cmd,
 847                               struct ieee80211_tx_info *info,
 848                               struct ieee80211_hdr *hdr, int sta_id, int tx_id)
 849 {
 850         u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
 851         u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT - 1);
 852         u16 rate_mask;
 853         int rate;
 854         u8 rts_retry_limit;
 855         u8 data_retry_limit;
 856         __le32 tx_flags;
 857         __le16 fc = hdr->frame_control;
 858         struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
 859
 860         rate = iwl3945_rates[rate_index].plcp;
 861         tx_flags = tx->tx_flags;
 862
 863         /* We need to figure out how to get the sta->supp_rates while
 864          * in this running context */
 865         rate_mask = IWL_RATES_MASK;
 866
 867         if (tx_id >= IWL_CMD_QUEUE_NUM)
 868                 rts_retry_limit = 3;
 869         else
 870                 rts_retry_limit = 7;
 871
 872         if (ieee80211_is_probe_resp(fc)) {
 873                 data_retry_limit = 3;
 874                 if (data_retry_limit < rts_retry_limit)
 875                         rts_retry_limit = data_retry_limit;
 876         } else
 877                 data_retry_limit = IWL_DEFAULT_TX_RETRY;
 878
 879         if (priv->data_retry_limit != -1)
 880                 data_retry_limit = priv->data_retry_limit;
 881
 882         if (ieee80211_is_mgmt(fc)) {
 883                 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
 884                 case cpu_to_le16(IEEE80211_STYPE_AUTH):
 885                 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
 886                 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
 887                 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
 888                         if (tx_flags & TX_CMD_FLG_RTS_MSK) {
 889                                 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
 890                                 tx_flags |= TX_CMD_FLG_CTS_MSK;
 891                         }
 892                         break;
 893                 default:
 894                         break;
 895                 }
 896         }
 897
 898         tx->rts_retry_limit = rts_retry_limit;
 899         tx->data_retry_limit = data_retry_limit;
 900         tx->rate = rate;
 901         tx->tx_flags = tx_flags;
 902
 903         /* OFDM */
 904         tx->supp_rates[0] =
 905            ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
 906
 907         /* CCK */
 908         tx->supp_rates[1] = (rate_mask & 0xF);
 909
 910         IWL_DEBUG_RATE("Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
 911                        "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
 912                        tx->rate, le32_to_cpu(tx->tx_flags),
 913                        tx->supp_rates[1], tx->supp_rates[0]);
 914 }
 915
 916 u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate, u8 flags)
 917 {
 918         unsigned long flags_spin;
 919         struct iwl3945_station_entry *station;
 920
 921         if (sta_id == IWL_INVALID_STATION)
 922                 return IWL_INVALID_STATION;
 923
 924         spin_lock_irqsave(&priv->sta_lock, flags_spin);
 925         station = &priv->stations_39[sta_id];
 926
 927         station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
 928         station->sta.rate_n_flags = cpu_to_le16(tx_rate);
 929         station->sta.mode = STA_CONTROL_MODIFY_MSK;
 930
 931         spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
 932
 933         iwl3945_send_add_station(priv, &station->sta, flags);
 934         IWL_DEBUG_RATE("SCALE sync station %d to rate %d\n",
 935                         sta_id, tx_rate);
 936         return sta_id;
 937 }
 938
 939 static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
 940 {
 941         int rc;
 942         unsigned long flags;
 943
 944         spin_lock_irqsave(&priv->lock, flags);
 945         rc = iwl_grab_nic_access(priv);
 946         if (rc) {
 947                 spin_unlock_irqrestore(&priv->lock, flags);
 948                 return rc;
 949         }
 950
 951         if (src == IWL_PWR_SRC_VAUX) {
 952                 u32 val;
 953
 954                 rc = pci_read_config_dword(priv->pci_dev,
 955                                 PCI_POWER_SOURCE, &val);
 956                 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
 957                         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 958                                         APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 959                                         ~APMG_PS_CTRL_MSK_PWR_SRC);
 960                         iwl_release_nic_access(priv);
 961
 962                         iwl_poll_bit(priv, CSR_GPIO_IN,
 963                                      CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
 964                                      CSR_GPIO_IN_BIT_AUX_POWER, 5000);
 965                 } else
 966                         iwl_release_nic_access(priv);
 967         } else {
 968                 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 969                                 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 970                                 ~APMG_PS_CTRL_MSK_PWR_SRC);
 971
 972                 iwl_release_nic_access(priv);
 973                 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
 974                              CSR_GPIO_IN_BIT_AUX_POWER, 5000);  /* uS */
 975         }
 976         spin_unlock_irqrestore(&priv->lock, flags);
 977
 978         return rc;
 979 }
 980
 981 static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
 982 {
 983         int rc;
 984         unsigned long flags;
 985
 986         spin_lock_irqsave(&priv->lock, flags);
 987         rc = iwl_grab_nic_access(priv);
 988         if (rc) {
 989                 spin_unlock_irqrestore(&priv->lock, flags);
 990                 return rc;
 991         }
 992
 993         iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
 994         iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
 995         iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
 996         iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
 997                 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
 998                 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
 999                 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
1000                 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
1001                 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
1002                 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
1003                 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
1004                 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
1005
1006         /* fake read to flush all prev I/O */
1007         iwl_read_direct32(priv, FH39_RSSR_CTRL);
1008
1009         iwl_release_nic_access(priv);
1010         spin_unlock_irqrestore(&priv->lock, flags);
1011
1012         return 0;
1013 }
1014
1015 static int iwl3945_tx_reset(struct iwl_priv *priv)
1016 {
1017         int rc;
1018         unsigned long flags;
1019
1020         spin_lock_irqsave(&priv->lock, flags);
1021         rc = iwl_grab_nic_access(priv);
1022         if (rc) {
1023                 spin_unlock_irqrestore(&priv->lock, flags);
1024                 return rc;
1025         }
1026
1027         /* bypass mode */
1028         iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
1029
1030         /* RA 0 is active */
1031         iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
1032
1033         /* all 6 fifo are active */
1034         iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
1035
1036         iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
1037         iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
1038         iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
1039         iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
1040
1041         iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
1042                              priv->shared_phys);
1043
1044         iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
1045                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
1046                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
1047                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
1048                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
1049                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
1050                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
1051                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
1052
1053         iwl_release_nic_access(priv);
1054         spin_unlock_irqrestore(&priv->lock, flags);
1055
1056         return 0;
1057 }
1058
1059 /**
1060  * iwl3945_txq_ctx_reset - Reset TX queue context
1061  *
1062  * Destroys all DMA structures and initialize them again
1063  */
1064 static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
1065 {
1066         int rc;
1067         int txq_id, slots_num;
1068
1069         iwl3945_hw_txq_ctx_free(priv);
1070
1071         /* Tx CMD queue */
1072         rc = iwl3945_tx_reset(priv);
1073         if (rc)
1074                 goto error;
1075
1076         /* Tx queue(s) */
1077         for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
1078                 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
1079                                 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
1080                 rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
1081                                        txq_id);
1082                 if (rc) {
1083                         IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
1084                         goto error;
1085                 }
1086         }
1087
1088         return rc;
1089
1090  error:
1091         iwl3945_hw_txq_ctx_free(priv);
1092         return rc;
1093 }
1094
1095 static int iwl3945_apm_init(struct iwl_priv *priv)
1096 {
1097         int ret = 0;
1098
1099         iwl3945_power_init_handle(priv);
1100
1101         iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1102                           CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
1103
1104         /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
1105         iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1106                           CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
1107
1108         /* set "initialization complete" bit to move adapter
1109         * D0U* --> D0A* state */
1110         iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1111
1112         iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
1113                             CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1114         if (ret < 0) {
1115                 IWL_DEBUG_INFO("Failed to init the card\n");
1116                 goto out;
1117         }
1118
1119         ret = iwl_grab_nic_access(priv);
1120         if (ret)
1121                 goto out;
1122
1123         /* enable DMA */
1124         iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT |
1125                                                 APMG_CLK_VAL_BSM_CLK_RQT);
1126
1127         udelay(20);
1128
1129         /* disable L1-Active */
1130         iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
1131                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1132
1133         iwl_release_nic_access(priv);
1134 out:
1135         return ret;
1136 }
1137
1138 static void iwl3945_nic_config(struct iwl_priv *priv)
1139 {
1140         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1141         unsigned long flags;
1142         u8 rev_id = 0;
1143
1144         spin_lock_irqsave(&priv->lock, flags);
1145
1146         if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
1147                 IWL_DEBUG_INFO("RTP type \n");
1148         else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
1149                 IWL_DEBUG_INFO("3945 RADIO-MB type\n");
1150                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1151                             CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
1152         } else {
1153                 IWL_DEBUG_INFO("3945 RADIO-MM type\n");
1154                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1155                             CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
1156         }
1157
1158         if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) {
1159                 IWL_DEBUG_INFO("SKU OP mode is mrc\n");
1160                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1161                             CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
1162         } else
1163                 IWL_DEBUG_INFO("SKU OP mode is basic\n");
1164
1165         if ((eeprom->board_revision & 0xF0) == 0xD0) {
1166                 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
1167                                eeprom->board_revision);
1168                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1169                             CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1170         } else {
1171                 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
1172                                eeprom->board_revision);
1173                 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
1174                               CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1175         }
1176
1177         if (eeprom->almgor_m_version <= 1) {
1178                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1179                             CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
1180                 IWL_DEBUG_INFO("Card M type A version is 0x%X\n",
1181                                eeprom->almgor_m_version);
1182         } else {
1183                 IWL_DEBUG_INFO("Card M type B version is 0x%X\n",
1184                                eeprom->almgor_m_version);
1185                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1186                             CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
1187         }
1188         spin_unlock_irqrestore(&priv->lock, flags);
1189
1190         if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
1191                 IWL_DEBUG_RF_KILL("SW RF KILL supported in EEPROM.\n");
1192
1193         if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
1194                 IWL_DEBUG_RF_KILL("HW RF KILL supported in EEPROM.\n");
1195 }
1196
1197 int iwl3945_hw_nic_init(struct iwl_priv *priv)
1198 {
1199         u8 rev_id;
1200         int rc;
1201         unsigned long flags;
1202         struct iwl_rx_queue *rxq = &priv->rxq;
1203
1204         spin_lock_irqsave(&priv->lock, flags);
1205         priv->cfg->ops->lib->apm_ops.init(priv);
1206         spin_unlock_irqrestore(&priv->lock, flags);
1207
1208         /* Determine HW type */
1209         rc = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
1210         if (rc)
1211                 return rc;
1212         IWL_DEBUG_INFO("HW Revision ID = 0x%X\n", rev_id);
1213
1214         rc = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
1215         if(rc)
1216                 return rc;
1217
1218         priv->cfg->ops->lib->apm_ops.config(priv);
1219
1220         /* Allocate the RX queue, or reset if it is already allocated */
1221         if (!rxq->bd) {
1222                 rc = iwl_rx_queue_alloc(priv);
1223                 if (rc) {
1224                         IWL_ERR(priv, "Unable to initialize Rx queue\n");
1225                         return -ENOMEM;
1226                 }
1227         } else
1228                 iwl_rx_queue_reset(priv, rxq);
1229
1230         iwl3945_rx_replenish(priv);
1231
1232         iwl3945_rx_init(priv, rxq);
1233
1234         spin_lock_irqsave(&priv->lock, flags);
1235
1236         /* Look at using this instead:
1237         rxq->need_update = 1;
1238         iwl_rx_queue_update_write_ptr(priv, rxq);
1239         */
1240
1241         rc = iwl_grab_nic_access(priv);
1242         if (rc) {
1243                 spin_unlock_irqrestore(&priv->lock, flags);
1244                 return rc;
1245         }
1246         iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
1247         iwl_release_nic_access(priv);
1248
1249         spin_unlock_irqrestore(&priv->lock, flags);
1250
1251         rc = iwl3945_txq_ctx_reset(priv);
1252         if (rc)
1253                 return rc;
1254
1255         set_bit(STATUS_INIT, &priv->status);
1256
1257         return 0;
1258 }
1259
1260 /**
1261  * iwl3945_hw_txq_ctx_free - Free TXQ Context
1262  *
1263  * Destroy all TX DMA queues and structures
1264  */
1265 void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
1266 {
1267         int txq_id;
1268
1269         /* Tx queues */
1270         for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++)
1271                 iwl_tx_queue_free(priv, txq_id);
1272 }
1273
1274 void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
1275 {
1276         int txq_id;
1277         unsigned long flags;
1278
1279         spin_lock_irqsave(&priv->lock, flags);
1280         if (iwl_grab_nic_access(priv)) {
1281                 spin_unlock_irqrestore(&priv->lock, flags);
1282                 iwl3945_hw_txq_ctx_free(priv);
1283                 return;
1284         }
1285
1286         /* stop SCD */
1287         iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
1288
1289         /* reset TFD queues */
1290         for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
1291                 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1292                 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
1293                                 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
1294                                 1000);
1295         }
1296
1297         iwl_release_nic_access(priv);
1298         spin_unlock_irqrestore(&priv->lock, flags);
1299
1300         iwl3945_hw_txq_ctx_free(priv);
1301 }
1302
1303 static int iwl3945_apm_stop_master(struct iwl_priv *priv)
1304 {
1305         int ret = 0;
1306         unsigned long flags;
1307
1308         spin_lock_irqsave(&priv->lock, flags);
1309
1310         /* set stop master bit */
1311         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
1312
1313         iwl_poll_direct_bit(priv, CSR_RESET,
1314                             CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
1315
1316         if (ret < 0)
1317                 goto out;
1318
1319 out:
1320         spin_unlock_irqrestore(&priv->lock, flags);
1321         IWL_DEBUG_INFO("stop master\n");
1322
1323         return ret;
1324 }
1325
1326 static void iwl3945_apm_stop(struct iwl_priv *priv)
1327 {
1328         unsigned long flags;
1329
1330         iwl3945_apm_stop_master(priv);
1331
1332         spin_lock_irqsave(&priv->lock, flags);
1333
1334         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1335
1336         udelay(10);
1337         /* clear "init complete"  move adapter D0A* --> D0U state */
1338         iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1339         spin_unlock_irqrestore(&priv->lock, flags);
1340 }
1341
1342 static int iwl3945_apm_reset(struct iwl_priv *priv)
1343 {
1344         int rc;
1345         unsigned long flags;
1346
1347         iwl3945_apm_stop_master(priv);
1348
1349         spin_lock_irqsave(&priv->lock, flags);
1350
1351         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1352         udelay(10);
1353
1354         iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1355
1356         iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
1357                          CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1358
1359         rc = iwl_grab_nic_access(priv);
1360         if (!rc) {
1361                 iwl_write_prph(priv, APMG_CLK_CTRL_REG,
1362                                          APMG_CLK_VAL_BSM_CLK_RQT);
1363
1364                 iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1365                 iwl_write_prph(priv, APMG_RTC_INT_STT_REG,
1366                                         0xFFFFFFFF);
1367
1368                 /* enable DMA */
1369                 iwl_write_prph(priv, APMG_CLK_EN_REG,
1370                                          APMG_CLK_VAL_DMA_CLK_RQT |
1371                                          APMG_CLK_VAL_BSM_CLK_RQT);
1372                 udelay(10);
1373
1374                 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG,
1375                                 APMG_PS_CTRL_VAL_RESET_REQ);
1376                 udelay(5);
1377                 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG,
1378                                 APMG_PS_CTRL_VAL_RESET_REQ);
1379                 iwl_release_nic_access(priv);
1380         }
1381
1382         /* Clear the 'host command active' bit... */
1383         clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1384
1385         wake_up_interruptible(&priv->wait_command_queue);
1386         spin_unlock_irqrestore(&priv->lock, flags);
1387
1388         return rc;
1389 }
1390
1391 /**
1392  * iwl3945_hw_reg_adjust_power_by_temp
1393  * return index delta into power gain settings table
1394 */
1395 static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
1396 {
1397         return (new_reading - old_reading) * (-11) / 100;
1398 }
1399
1400 /**
1401  * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
1402  */
1403 static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
1404 {
1405         return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
1406 }
1407
1408 int iwl3945_hw_get_temperature(struct iwl_priv *priv)
1409 {
1410         return iwl_read32(priv, CSR_UCODE_DRV_GP2);
1411 }
1412
1413 /**
1414  * iwl3945_hw_reg_txpower_get_temperature
1415  * get the current temperature by reading from NIC
1416 */
1417 static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
1418 {
1419         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1420         int temperature;
1421
1422         temperature = iwl3945_hw_get_temperature(priv);
1423
1424         /* driver's okay range is -260 to +25.
1425          *   human readable okay range is 0 to +285 */
1426         IWL_DEBUG_INFO("Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
1427
1428         /* handle insane temp reading */
1429         if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
1430                 IWL_ERR(priv, "Error bad temperature value  %d\n", temperature);
1431
1432                 /* if really really hot(?),
1433                  *   substitute the 3rd band/group's temp measured at factory */
1434                 if (priv->last_temperature > 100)
1435                         temperature = eeprom->groups[2].temperature;
1436                 else /* else use most recent "sane" value from driver */
1437                         temperature = priv->last_temperature;
1438         }
1439
1440         return temperature;     /* raw, not "human readable" */
1441 }
1442
1443 /* Adjust Txpower only if temperature variance is greater than threshold.
1444  *
1445  * Both are lower than older versions' 9 degrees */
1446 #define IWL_TEMPERATURE_LIMIT_TIMER   6
1447
1448 /**
1449  * is_temp_calib_needed - determines if new calibration is needed
1450  *
1451  * records new temperature in tx_mgr->temperature.
1452  * replaces tx_mgr->last_temperature *only* if calib needed
1453  *    (assumes caller will actually do the calibration!). */
1454 static int is_temp_calib_needed(struct iwl_priv *priv)
1455 {
1456         int temp_diff;
1457
1458         priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
1459         temp_diff = priv->temperature - priv->last_temperature;
1460
1461         /* get absolute value */
1462         if (temp_diff < 0) {
1463                 IWL_DEBUG_POWER("Getting cooler, delta %d,\n", temp_diff);
1464                 temp_diff = -temp_diff;
1465         } else if (temp_diff == 0)
1466                 IWL_DEBUG_POWER("Same temp,\n");
1467         else
1468                 IWL_DEBUG_POWER("Getting warmer, delta %d,\n", temp_diff);
1469
1470         /* if we don't need calibration, *don't* update last_temperature */
1471         if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
1472                 IWL_DEBUG_POWER("Timed thermal calib not needed\n");
1473                 return 0;
1474         }
1475
1476         IWL_DEBUG_POWER("Timed thermal calib needed\n");
1477
1478         /* assume that caller will actually do calib ...
1479          *   update the "last temperature" value */
1480         priv->last_temperature = priv->temperature;
1481         return 1;
1482 }
1483
1484 #define IWL_MAX_GAIN_ENTRIES 78
1485 #define IWL_CCK_FROM_OFDM_POWER_DIFF  -5
1486 #define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1487
1488 /* radio and DSP power table, each step is 1/2 dB.
1489  * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
1490 static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
1491         {
1492          {251, 127},            /* 2.4 GHz, highest power */
1493          {251, 127},
1494          {251, 127},
1495          {251, 127},
1496          {251, 125},
1497          {251, 110},
1498          {251, 105},
1499          {251, 98},
1500          {187, 125},
1501          {187, 115},
1502          {187, 108},
1503          {187, 99},
1504          {243, 119},
1505          {243, 111},
1506          {243, 105},
1507          {243, 97},
1508          {243, 92},
1509          {211, 106},
1510          {211, 100},
1511          {179, 120},
1512          {179, 113},
1513          {179, 107},
1514          {147, 125},
1515          {147, 119},
1516          {147, 112},
1517          {147, 106},
1518          {147, 101},
1519          {147, 97},
1520          {147, 91},
1521          {115, 107},
1522          {235, 121},
1523          {235, 115},
1524          {235, 109},
1525          {203, 127},
1526          {203, 121},
1527          {203, 115},
1528          {203, 108},
1529          {203, 102},
1530          {203, 96},
1531          {203, 92},
1532          {171, 110},
1533          {171, 104},
1534          {171, 98},
1535          {139, 116},
1536          {227, 125},
1537          {227, 119},
1538          {227, 113},
1539          {227, 107},
1540          {227, 101},
1541          {227, 96},
1542          {195, 113},
1543          {195, 106},
1544          {195, 102},
1545          {195, 95},
1546          {163, 113},
1547          {163, 106},
1548          {163, 102},
1549          {163, 95},
1550          {131, 113},
1551          {131, 106},
1552          {131, 102},
1553          {131, 95},
1554          {99, 113},
1555          {99, 106},
1556          {99, 102},
1557          {99, 95},
1558          {67, 113},
1559          {67, 106},
1560          {67, 102},
1561          {67, 95},
1562          {35, 113},
1563          {35, 106},
1564          {35, 102},
1565          {35, 95},
1566          {3, 113},
1567          {3, 106},
1568          {3, 102},
1569          {3, 95} },             /* 2.4 GHz, lowest power */
1570         {
1571          {251, 127},            /* 5.x GHz, highest power */
1572          {251, 120},
1573          {251, 114},
1574          {219, 119},
1575          {219, 101},
1576          {187, 113},
1577          {187, 102},
1578          {155, 114},
1579          {155, 103},
1580          {123, 117},
1581          {123, 107},
1582          {123, 99},
1583          {123, 92},
1584          {91, 108},
1585          {59, 125},
1586          {59, 118},
1587          {59, 109},
1588          {59, 102},
1589          {59, 96},
1590          {59, 90},
1591          {27, 104},
1592          {27, 98},
1593          {27, 92},
1594          {115, 118},
1595          {115, 111},
1596          {115, 104},
1597          {83, 126},
1598          {83, 121},
1599          {83, 113},
1600          {83, 105},
1601          {83, 99},
1602          {51, 118},
1603          {51, 111},
1604          {51, 104},
1605          {51, 98},
1606          {19, 116},
1607          {19, 109},
1608          {19, 102},
1609          {19, 98},
1610          {19, 93},
1611          {171, 113},
1612          {171, 107},
1613          {171, 99},
1614          {139, 120},
1615          {139, 113},
1616          {139, 107},
1617          {139, 99},
1618          {107, 120},
1619          {107, 113},
1620          {107, 107},
1621          {107, 99},
1622          {75, 120},
1623          {75, 113},
1624          {75, 107},
1625          {75, 99},
1626          {43, 120},
1627          {43, 113},
1628          {43, 107},
1629          {43, 99},
1630          {11, 120},
1631          {11, 113},
1632          {11, 107},
1633          {11, 99},
1634          {131, 107},
1635          {131, 99},
1636          {99, 120},
1637          {99, 113},
1638          {99, 107},
1639          {99, 99},
1640          {67, 120},
1641          {67, 113},
1642          {67, 107},
1643          {67, 99},
1644          {35, 120},
1645          {35, 113},
1646          {35, 107},
1647          {35, 99},
1648          {3, 120} }             /* 5.x GHz, lowest power */
1649 };
1650
1651 static inline u8 iwl3945_hw_reg_fix_power_index(int index)
1652 {
1653         if (index < 0)
1654                 return 0;
1655         if (index >= IWL_MAX_GAIN_ENTRIES)
1656                 return IWL_MAX_GAIN_ENTRIES - 1;
1657         return (u8) index;
1658 }
1659
1660 /* Kick off thermal recalibration check every 60 seconds */
1661 #define REG_RECALIB_PERIOD (60)
1662
1663 /**
1664  * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
1665  *
1666  * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1667  * or 6 Mbit (OFDM) rates.
1668  */
1669 static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
1670                                s32 rate_index, const s8 *clip_pwrs,
1671                                struct iwl_channel_info *ch_info,
1672                                int band_index)
1673 {
1674         struct iwl3945_scan_power_info *scan_power_info;
1675         s8 power;
1676         u8 power_index;
1677
1678         scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1679
1680         /* use this channel group's 6Mbit clipping/saturation pwr,
1681          *   but cap at regulatory scan power restriction (set during init
1682          *   based on eeprom channel data) for this channel.  */
1683         power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
1684
1685         /* further limit to user's max power preference.
1686          * FIXME:  Other spectrum management power limitations do not
1687          *   seem to apply?? */
1688         power = min(power, priv->tx_power_user_lmt);
1689         scan_power_info->requested_power = power;
1690
1691         /* find difference between new scan *power* and current "normal"
1692          *   Tx *power* for 6Mb.  Use this difference (x2) to adjust the
1693          *   current "normal" temperature-compensated Tx power *index* for
1694          *   this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1695          *   *index*. */
1696         power_index = ch_info->power_info[rate_index].power_table_index
1697             - (power - ch_info->power_info
1698                [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
1699
1700         /* store reference index that we use when adjusting *all* scan
1701          *   powers.  So we can accommodate user (all channel) or spectrum
1702          *   management (single channel) power changes "between" temperature
1703          *   feedback compensation procedures.
1704          * don't force fit this reference index into gain table; it may be a
1705          *   negative number.  This will help avoid errors when we're at
1706          *   the lower bounds (highest gains, for warmest temperatures)
1707          *   of the table. */
1708
1709         /* don't exceed table bounds for "real" setting */
1710         power_index = iwl3945_hw_reg_fix_power_index(power_index);
1711
1712         scan_power_info->power_table_index = power_index;
1713         scan_power_info->tpc.tx_gain =
1714             power_gain_table[band_index][power_index].tx_gain;
1715         scan_power_info->tpc.dsp_atten =
1716             power_gain_table[band_index][power_index].dsp_atten;
1717 }
1718
1719 /**
1720  * iwl3945_send_tx_power - fill in Tx Power command with gain settings
1721  *
1722  * Configures power settings for all rates for the current channel,
1723  * using values from channel info struct, and send to NIC
1724  */
1725 int iwl3945_send_tx_power(struct iwl_priv *priv)
1726 {
1727         int rate_idx, i;
1728         const struct iwl_channel_info *ch_info = NULL;
1729         struct iwl3945_txpowertable_cmd txpower = {
1730                 .channel = priv->active39_rxon.channel,
1731         };
1732
1733         txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
1734         ch_info = iwl_get_channel_info(priv,
1735                                        priv->band,
1736                                        le16_to_cpu(priv->active39_rxon.channel));
1737         if (!ch_info) {
1738                 IWL_ERR(priv,
1739                         "Failed to get channel info for channel %d [%d]\n",
1740                         le16_to_cpu(priv->active39_rxon.channel), priv->band);
1741                 return -EINVAL;
1742         }
1743
1744         if (!is_channel_valid(ch_info)) {
1745                 IWL_DEBUG_POWER("Not calling TX_PWR_TABLE_CMD on "
1746                                 "non-Tx channel.\n");
1747                 return 0;
1748         }
1749
1750         /* fill cmd with power settings for all rates for current channel */
1751         /* Fill OFDM rate */
1752         for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
1753              rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
1754
1755                 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1756                 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1757
1758                 IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1759                                 le16_to_cpu(txpower.channel),
1760                                 txpower.band,
1761                                 txpower.power[i].tpc.tx_gain,
1762                                 txpower.power[i].tpc.dsp_atten,
1763                                 txpower.power[i].rate);
1764         }
1765         /* Fill CCK rates */
1766         for (rate_idx = IWL_FIRST_CCK_RATE;
1767              rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1768                 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1769                 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1770
1771                 IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1772                                 le16_to_cpu(txpower.channel),
1773                                 txpower.band,
1774                                 txpower.power[i].tpc.tx_gain,
1775                                 txpower.power[i].tpc.dsp_atten,
1776                                 txpower.power[i].rate);
1777         }
1778
1779         return iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1780                                 sizeof(struct iwl3945_txpowertable_cmd),
1781                                 &txpower);
1782
1783 }
1784
1785 /**
1786  * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
1787  * @ch_info: Channel to update.  Uses power_info.requested_power.
1788  *
1789  * Replace requested_power and base_power_index ch_info fields for
1790  * one channel.
1791  *
1792  * Called if user or spectrum management changes power preferences.
1793  * Takes into account h/w and modulation limitations (clip power).
1794  *
1795  * This does *not* send anything to NIC, just sets up ch_info for one channel.
1796  *
1797  * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1798  *       properly fill out the scan powers, and actual h/w gain settings,
1799  *       and send changes to NIC
1800  */
1801 static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
1802                              struct iwl_channel_info *ch_info)
1803 {
1804         struct iwl3945_channel_power_info *power_info;
1805         int power_changed = 0;
1806         int i;
1807         const s8 *clip_pwrs;
1808         int power;
1809
1810         /* Get this chnlgrp's rate-to-max/clip-powers table */
1811         clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
1812
1813         /* Get this channel's rate-to-current-power settings table */
1814         power_info = ch_info->power_info;
1815
1816         /* update OFDM Txpower settings */
1817         for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
1818              i++, ++power_info) {
1819                 int delta_idx;
1820
1821                 /* limit new power to be no more than h/w capability */
1822                 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1823                 if (power == power_info->requested_power)
1824                         continue;
1825
1826                 /* find difference between old and new requested powers,
1827                  *    update base (non-temp-compensated) power index */
1828                 delta_idx = (power - power_info->requested_power) * 2;
1829                 power_info->base_power_index -= delta_idx;
1830
1831                 /* save new requested power value */
1832                 power_info->requested_power = power;
1833
1834                 power_changed = 1;
1835         }
1836
1837         /* update CCK Txpower settings, based on OFDM 12M setting ...
1838          *    ... all CCK power settings for a given channel are the *same*. */
1839         if (power_changed) {
1840                 power =
1841                     ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1842                     requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1843
1844                 /* do all CCK rates' iwl3945_channel_power_info structures */
1845                 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
1846                         power_info->requested_power = power;
1847                         power_info->base_power_index =
1848                             ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1849                             base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1850                         ++power_info;
1851                 }
1852         }
1853
1854         return 0;
1855 }
1856
1857 /**
1858  * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
1859  *
1860  * NOTE: Returned power limit may be less (but not more) than requested,
1861  *       based strictly on regulatory (eeprom and spectrum mgt) limitations
1862  *       (no consideration for h/w clipping limitations).
1863  */
1864 static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
1865 {
1866         s8 max_power;
1867
1868 #if 0
1869         /* if we're using TGd limits, use lower of TGd or EEPROM */
1870         if (ch_info->tgd_data.max_power != 0)
1871                 max_power = min(ch_info->tgd_data.max_power,
1872                                 ch_info->eeprom.max_power_avg);
1873
1874         /* else just use EEPROM limits */
1875         else
1876 #endif
1877                 max_power = ch_info->eeprom.max_power_avg;
1878
1879         return min(max_power, ch_info->max_power_avg);
1880 }
1881
1882 /**
1883  * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
1884  *
1885  * Compensate txpower settings of *all* channels for temperature.
1886  * This only accounts for the difference between current temperature
1887  *   and the factory calibration temperatures, and bases the new settings
1888  *   on the channel's base_power_index.
1889  *
1890  * If RxOn is "associated", this sends the new Txpower to NIC!
1891  */
1892 static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
1893 {
1894         struct iwl_channel_info *ch_info = NULL;
1895         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1896         int delta_index;
1897         const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1898         u8 a_band;
1899         u8 rate_index;
1900         u8 scan_tbl_index;
1901         u8 i;
1902         int ref_temp;
1903         int temperature = priv->temperature;
1904
1905         /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1906         for (i = 0; i < priv->channel_count; i++) {
1907                 ch_info = &priv->channel_info[i];
1908                 a_band = is_channel_a_band(ch_info);
1909
1910                 /* Get this chnlgrp's factory calibration temperature */
1911                 ref_temp = (s16)eeprom->groups[ch_info->group_index].
1912                     temperature;
1913
1914                 /* get power index adjustment based on current and factory
1915                  * temps */
1916                 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
1917                                                               ref_temp);
1918
1919                 /* set tx power value for all rates, OFDM and CCK */
1920                 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1921                      rate_index++) {
1922                         int power_idx =
1923                             ch_info->power_info[rate_index].base_power_index;
1924
1925                         /* temperature compensate */
1926                         power_idx += delta_index;
1927
1928                         /* stay within table range */
1929                         power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
1930                         ch_info->power_info[rate_index].
1931                             power_table_index = (u8) power_idx;
1932                         ch_info->power_info[rate_index].tpc =
1933                             power_gain_table[a_band][power_idx];
1934                 }
1935
1936                 /* Get this chnlgrp's rate-to-max/clip-powers table */
1937                 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
1938
1939                 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1940                 for (scan_tbl_index = 0;
1941                      scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1942                         s32 actual_index = (scan_tbl_index == 0) ?
1943                             IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
1944                         iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
1945                                            actual_index, clip_pwrs,
1946                                            ch_info, a_band);
1947                 }
1948         }
1949
1950         /* send Txpower command for current channel to ucode */
1951         return priv->cfg->ops->lib->send_tx_power(priv);
1952 }
1953
1954 int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
1955 {
1956         struct iwl_channel_info *ch_info;
1957         s8 max_power;
1958         u8 a_band;
1959         u8 i;
1960
1961         if (priv->tx_power_user_lmt == power) {
1962                 IWL_DEBUG_POWER("Requested Tx power same as current "
1963                                 "limit: %ddBm.\n", power);
1964                 return 0;
1965         }
1966
1967         IWL_DEBUG_POWER("Setting upper limit clamp to %ddBm.\n", power);
1968         priv->tx_power_user_lmt = power;
1969
1970         /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1971
1972         for (i = 0; i < priv->channel_count; i++) {
1973                 ch_info = &priv->channel_info[i];
1974                 a_band = is_channel_a_band(ch_info);
1975
1976                 /* find minimum power of all user and regulatory constraints
1977                  *    (does not consider h/w clipping limitations) */
1978                 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
1979                 max_power = min(power, max_power);
1980                 if (max_power != ch_info->curr_txpow) {
1981                         ch_info->curr_txpow = max_power;
1982
1983                         /* this considers the h/w clipping limitations */
1984                         iwl3945_hw_reg_set_new_power(priv, ch_info);
1985                 }
1986         }
1987
1988         /* update txpower settings for all channels,
1989          *   send to NIC if associated. */
1990         is_temp_calib_needed(priv);
1991         iwl3945_hw_reg_comp_txpower_temp(priv);
1992
1993         return 0;
1994 }
1995
1996 /* will add 3945 channel switch cmd handling later */
1997 int iwl3945_hw_channel_switch(struct iwl_priv *priv, u16 channel)
1998 {
1999         return 0;
2000 }
2001
2002 /**
2003  * iwl3945_reg_txpower_periodic -  called when time to check our temperature.
2004  *
2005  * -- reset periodic timer
2006  * -- see if temp has changed enough to warrant re-calibration ... if so:
2007  *     -- correct coeffs for temp (can reset temp timer)
2008  *     -- save this temp as "last",
2009  *     -- send new set of gain settings to NIC
2010  * NOTE:  This should continue working, even when we're not associated,
2011  *   so we can keep our internal table of scan powers current. */
2012 void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
2013 {
2014         /* This will kick in the "brute force"
2015          * iwl3945_hw_reg_comp_txpower_temp() below */
2016         if (!is_temp_calib_needed(priv))
2017                 goto reschedule;
2018
2019         /* Set up a new set of temp-adjusted TxPowers, send to NIC.
2020          * This is based *only* on current temperature,
2021          * ignoring any previous power measurements */
2022         iwl3945_hw_reg_comp_txpower_temp(priv);
2023
2024  reschedule:
2025         queue_delayed_work(priv->workqueue,
2026                            &priv->thermal_periodic, REG_RECALIB_PERIOD * HZ);
2027 }
2028
2029 static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
2030 {
2031         struct iwl_priv *priv = container_of(work, struct iwl_priv,
2032                                              thermal_periodic.work);
2033
2034         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2035                 return;
2036
2037         mutex_lock(&priv->mutex);
2038         iwl3945_reg_txpower_periodic(priv);
2039         mutex_unlock(&priv->mutex);
2040 }
2041
2042 /**
2043  * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
2044  *                                 for the channel.
2045  *
2046  * This function is used when initializing channel-info structs.
2047  *
2048  * NOTE: These channel groups do *NOT* match the bands above!
2049  *       These channel groups are based on factory-tested channels;
2050  *       on A-band, EEPROM's "group frequency" entries represent the top
2051  *       channel in each group 1-4.  Group 5 All B/G channels are in group 0.
2052  */
2053 static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
2054                                        const struct iwl_channel_info *ch_info)
2055 {
2056         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2057         struct iwl3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0];
2058         u8 group;
2059         u16 group_index = 0;    /* based on factory calib frequencies */
2060         u8 grp_channel;
2061
2062         /* Find the group index for the channel ... don't use index 1(?) */
2063         if (is_channel_a_band(ch_info)) {
2064                 for (group = 1; group < 5; group++) {
2065                         grp_channel = ch_grp[group].group_channel;
2066                         if (ch_info->channel <= grp_channel) {
2067                                 group_index = group;
2068                                 break;
2069                         }
2070                 }
2071                 /* group 4 has a few channels *above* its factory cal freq */
2072                 if (group == 5)
2073                         group_index = 4;
2074         } else
2075                 group_index = 0;        /* 2.4 GHz, group 0 */
2076
2077         IWL_DEBUG_POWER("Chnl %d mapped to grp %d\n", ch_info->channel,
2078                         group_index);
2079         return group_index;
2080 }
2081
2082 /**
2083  * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
2084  *
2085  * Interpolate to get nominal (i.e. at factory calibration temperature) index
2086  *   into radio/DSP gain settings table for requested power.
2087  */
2088 static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
2089                                        s8 requested_power,
2090                                        s32 setting_index, s32 *new_index)
2091 {
2092         const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
2093         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2094         s32 index0, index1;
2095         s32 power = 2 * requested_power;
2096         s32 i;
2097         const struct iwl3945_eeprom_txpower_sample *samples;
2098         s32 gains0, gains1;
2099         s32 res;
2100         s32 denominator;
2101
2102         chnl_grp = &eeprom->groups[setting_index];
2103         samples = chnl_grp->samples;
2104         for (i = 0; i < 5; i++) {
2105                 if (power == samples[i].power) {
2106                         *new_index = samples[i].gain_index;
2107                         return 0;
2108                 }
2109         }
2110
2111         if (power > samples[1].power) {
2112                 index0 = 0;
2113                 index1 = 1;
2114         } else if (power > samples[2].power) {
2115                 index0 = 1;
2116                 index1 = 2;
2117         } else if (power > samples[3].power) {
2118                 index0 = 2;
2119                 index1 = 3;
2120         } else {
2121                 index0 = 3;
2122                 index1 = 4;
2123         }
2124
2125         denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2126         if (denominator == 0)
2127                 return -EINVAL;
2128         gains0 = (s32) samples[index0].gain_index * (1 << 19);
2129         gains1 = (s32) samples[index1].gain_index * (1 << 19);
2130         res = gains0 + (gains1 - gains0) *
2131             ((s32) power - (s32) samples[index0].power) / denominator +
2132             (1 << 18);
2133         *new_index = res >> 19;
2134         return 0;
2135 }
2136
2137 static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
2138 {
2139         u32 i;
2140         s32 rate_index;
2141         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2142         const struct iwl3945_eeprom_txpower_group *group;
2143
2144         IWL_DEBUG_POWER("Initializing factory calib info from EEPROM\n");
2145
2146         for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2147                 s8 *clip_pwrs;  /* table of power levels for each rate */
2148                 s8 satur_pwr;   /* saturation power for each chnl group */
2149                 group = &eeprom->groups[i];
2150
2151                 /* sanity check on factory saturation power value */
2152                 if (group->saturation_power < 40) {
2153                         IWL_WARN(priv, "Error: saturation power is %d, "
2154                                     "less than minimum expected 40\n",
2155                                     group->saturation_power);
2156                         return;
2157                 }
2158
2159                 /*
2160                  * Derive requested power levels for each rate, based on
2161                  *   hardware capabilities (saturation power for band).
2162                  * Basic value is 3dB down from saturation, with further
2163                  *   power reductions for highest 3 data rates.  These
2164                  *   backoffs provide headroom for high rate modulation
2165                  *   power peaks, without too much distortion (clipping).
2166                  */
2167                 /* we'll fill in this array with h/w max power levels */
2168                 clip_pwrs = (s8 *) priv->clip39_groups[i].clip_powers;
2169
2170                 /* divide factory saturation power by 2 to find -3dB level */
2171                 satur_pwr = (s8) (group->saturation_power >> 1);
2172
2173                 /* fill in channel group's nominal powers for each rate */
2174                 for (rate_index = 0;
2175                      rate_index < IWL_RATE_COUNT; rate_index++, clip_pwrs++) {
2176                         switch (rate_index) {
2177                         case IWL_RATE_36M_INDEX_TABLE:
2178                                 if (i == 0)     /* B/G */
2179                                         *clip_pwrs = satur_pwr;
2180                                 else    /* A */
2181                                         *clip_pwrs = satur_pwr - 5;
2182                                 break;
2183                         case IWL_RATE_48M_INDEX_TABLE:
2184                                 if (i == 0)
2185                                         *clip_pwrs = satur_pwr - 7;
2186                                 else
2187                                         *clip_pwrs = satur_pwr - 10;
2188                                 break;
2189                         case IWL_RATE_54M_INDEX_TABLE:
2190                                 if (i == 0)
2191                                         *clip_pwrs = satur_pwr - 9;
2192                                 else
2193                                         *clip_pwrs = satur_pwr - 12;
2194                                 break;
2195                         default:
2196                                 *clip_pwrs = satur_pwr;
2197                                 break;
2198                         }
2199                 }
2200         }
2201 }
2202
2203 /**
2204  * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2205  *
2206  * Second pass (during init) to set up priv->channel_info
2207  *
2208  * Set up Tx-power settings in our channel info database for each VALID
2209  * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2210  * and current temperature.
2211  *
2212  * Since this is based on current temperature (at init time), these values may
2213  * not be valid for very long, but it gives us a starting/default point,
2214  * and allows us to active (i.e. using Tx) scan.
2215  *
2216  * This does *not* write values to NIC, just sets up our internal table.
2217  */
2218 int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
2219 {
2220         struct iwl_channel_info *ch_info = NULL;
2221         struct iwl3945_channel_power_info *pwr_info;
2222         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2223         int delta_index;
2224         u8 rate_index;
2225         u8 scan_tbl_index;
2226         const s8 *clip_pwrs;    /* array of power levels for each rate */
2227         u8 gain, dsp_atten;
2228         s8 power;
2229         u8 pwr_index, base_pwr_index, a_band;
2230         u8 i;
2231         int temperature;
2232
2233         /* save temperature reference,
2234          *   so we can determine next time to calibrate */
2235         temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
2236         priv->last_temperature = temperature;
2237
2238         iwl3945_hw_reg_init_channel_groups(priv);
2239
2240         /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2241         for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2242              i++, ch_info++) {
2243                 a_band = is_channel_a_band(ch_info);
2244                 if (!is_channel_valid(ch_info))
2245                         continue;
2246
2247                 /* find this channel's channel group (*not* "band") index */
2248                 ch_info->group_index =
2249                         iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
2250
2251                 /* Get this chnlgrp's rate->max/clip-powers table */
2252                 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
2253
2254                 /* calculate power index *adjustment* value according to
2255                  *  diff between current temperature and factory temperature */
2256                 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
2257                                 eeprom->groups[ch_info->group_index].
2258                                 temperature);
2259
2260                 IWL_DEBUG_POWER("Delta index for channel %d: %d [%d]\n",
2261                                 ch_info->channel, delta_index, temperature +
2262                                 IWL_TEMP_CONVERT);
2263
2264                 /* set tx power value for all OFDM rates */
2265                 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2266                      rate_index++) {
2267                         s32 uninitialized_var(power_idx);
2268                         int rc;
2269
2270                         /* use channel group's clip-power table,
2271                          *   but don't exceed channel's max power */
2272                         s8 pwr = min(ch_info->max_power_avg,
2273                                      clip_pwrs[rate_index]);
2274
2275                         pwr_info = &ch_info->power_info[rate_index];
2276
2277                         /* get base (i.e. at factory-measured temperature)
2278                          *    power table index for this rate's power */
2279                         rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
2280                                                          ch_info->group_index,
2281                                                          &power_idx);
2282                         if (rc) {
2283                                 IWL_ERR(priv, "Invalid power index\n");
2284                                 return rc;
2285                         }
2286                         pwr_info->base_power_index = (u8) power_idx;
2287
2288                         /* temperature compensate */
2289                         power_idx += delta_index;
2290
2291                         /* stay within range of gain table */
2292                         power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
2293
2294                         /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
2295                         pwr_info->requested_power = pwr;
2296                         pwr_info->power_table_index = (u8) power_idx;
2297                         pwr_info->tpc.tx_gain =
2298                             power_gain_table[a_band][power_idx].tx_gain;
2299                         pwr_info->tpc.dsp_atten =
2300                             power_gain_table[a_band][power_idx].dsp_atten;
2301                 }
2302
2303                 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
2304                 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
2305                 power = pwr_info->requested_power +
2306                         IWL_CCK_FROM_OFDM_POWER_DIFF;
2307                 pwr_index = pwr_info->power_table_index +
2308                         IWL_CCK_FROM_OFDM_INDEX_DIFF;
2309                 base_pwr_index = pwr_info->base_power_index +
2310                         IWL_CCK_FROM_OFDM_INDEX_DIFF;
2311
2312                 /* stay within table range */
2313                 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
2314                 gain = power_gain_table[a_band][pwr_index].tx_gain;
2315                 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2316
2317                 /* fill each CCK rate's iwl3945_channel_power_info structure
2318                  * NOTE:  All CCK-rate Txpwrs are the same for a given chnl!
2319                  * NOTE:  CCK rates start at end of OFDM rates! */
2320                 for (rate_index = 0;
2321                      rate_index < IWL_CCK_RATES; rate_index++) {
2322                         pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
2323                         pwr_info->requested_power = power;
2324                         pwr_info->power_table_index = pwr_index;
2325                         pwr_info->base_power_index = base_pwr_index;
2326                         pwr_info->tpc.tx_gain = gain;
2327                         pwr_info->tpc.dsp_atten = dsp_atten;
2328                 }
2329
2330                 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2331                 for (scan_tbl_index = 0;
2332                      scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2333                         s32 actual_index = (scan_tbl_index == 0) ?
2334                                 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
2335                         iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
2336                                 actual_index, clip_pwrs, ch_info, a_band);
2337                 }
2338         }
2339
2340         return 0;
2341 }
2342
2343 int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
2344 {
2345         int rc;
2346         unsigned long flags;
2347
2348         spin_lock_irqsave(&priv->lock, flags);
2349         rc = iwl_grab_nic_access(priv);
2350         if (rc) {
2351                 spin_unlock_irqrestore(&priv->lock, flags);
2352                 return rc;
2353         }
2354
2355         iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2356         rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
2357                         FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
2358         if (rc < 0)
2359                 IWL_ERR(priv, "Can't stop Rx DMA.\n");
2360
2361         iwl_release_nic_access(priv);
2362         spin_unlock_irqrestore(&priv->lock, flags);
2363
2364         return 0;
2365 }
2366
2367 int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
2368 {
2369         int rc;
2370         unsigned long flags;
2371         int txq_id = txq->q.id;
2372
2373         struct iwl3945_shared *shared_data = priv->shared_virt;
2374
2375         shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2376
2377         spin_lock_irqsave(&priv->lock, flags);
2378         rc = iwl_grab_nic_access(priv);
2379         if (rc) {
2380                 spin_unlock_irqrestore(&priv->lock, flags);
2381                 return rc;
2382         }
2383         iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2384         iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
2385
2386         iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
2387                 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2388                 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2389                 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2390                 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2391                 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
2392         iwl_release_nic_access(priv);
2393
2394         /* fake read to flush all prev. writes */
2395         iwl_read32(priv, FH39_TSSR_CBB_BASE);
2396         spin_unlock_irqrestore(&priv->lock, flags);
2397
2398         return 0;
2399 }
2400
2401 /*
2402  * HCMD utils
2403  */
2404 static u16 iwl3945_get_hcmd_size(u8 cmd_id, u16 len)
2405 {
2406         switch (cmd_id) {
2407         case REPLY_RXON:
2408                 return (u16) sizeof(struct iwl3945_rxon_cmd);
2409         default:
2410                 return len;
2411         }
2412 }
2413
2414 /**
2415  * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2416  */
2417 int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
2418 {
2419         int rc, i, index, prev_index;
2420         struct iwl3945_rate_scaling_cmd rate_cmd = {
2421                 .reserved = {0, 0, 0},
2422         };
2423         struct iwl3945_rate_scaling_info *table = rate_cmd.table;
2424
2425         for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2426                 index = iwl3945_rates[i].table_rs_index;
2427
2428                 table[index].rate_n_flags =
2429                         iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
2430                 table[index].try_cnt = priv->retry_rate;
2431                 prev_index = iwl3945_get_prev_ieee_rate(i);
2432                 table[index].next_rate_index =
2433                                 iwl3945_rates[prev_index].table_rs_index;
2434         }
2435
2436         switch (priv->band) {
2437         case IEEE80211_BAND_5GHZ:
2438                 IWL_DEBUG_RATE("Select A mode rate scale\n");
2439                 /* If one of the following CCK rates is used,
2440                  * have it fall back to the 6M OFDM rate */
2441                 for (i = IWL_RATE_1M_INDEX_TABLE;
2442                         i <= IWL_RATE_11M_INDEX_TABLE; i++)
2443                         table[i].next_rate_index =
2444                           iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2445
2446                 /* Don't fall back to CCK rates */
2447                 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2448                                                 IWL_RATE_9M_INDEX_TABLE;
2449
2450                 /* Don't drop out of OFDM rates */
2451                 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
2452                     iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2453                 break;
2454
2455         case IEEE80211_BAND_2GHZ:
2456                 IWL_DEBUG_RATE("Select B/G mode rate scale\n");
2457                 /* If an OFDM rate is used, have it fall back to the
2458                  * 1M CCK rates */
2459
2460                 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
2461                     iwl3945_is_associated(priv)) {
2462
2463                         index = IWL_FIRST_CCK_RATE;
2464                         for (i = IWL_RATE_6M_INDEX_TABLE;
2465                              i <= IWL_RATE_54M_INDEX_TABLE; i++)
2466                                 table[i].next_rate_index =
2467                                         iwl3945_rates[index].table_rs_index;
2468
2469                         index = IWL_RATE_11M_INDEX_TABLE;
2470                         /* CCK shouldn't fall back to OFDM... */
2471                         table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2472                 }
2473                 break;
2474
2475         default:
2476                 WARN_ON(1);
2477                 break;
2478         }
2479
2480         /* Update the rate scaling for control frame Tx */
2481         rate_cmd.table_id = 0;
2482         rc = iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2483                               &rate_cmd);
2484         if (rc)
2485                 return rc;
2486
2487         /* Update the rate scaling for data frame Tx */
2488         rate_cmd.table_id = 1;
2489         return iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2490                                 &rate_cmd);
2491 }
2492
2493 /* Called when initializing driver */
2494 int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
2495 {
2496         memset((void *)&priv->hw_params, 0,
2497                sizeof(struct iwl_hw_params));
2498
2499         priv->shared_virt =
2500             pci_alloc_consistent(priv->pci_dev,
2501                                  sizeof(struct iwl3945_shared),
2502                                  &priv->shared_phys);
2503
2504         if (!priv->shared_virt) {
2505                 IWL_ERR(priv, "failed to allocate pci memory\n");
2506                 mutex_unlock(&priv->mutex);
2507                 return -ENOMEM;
2508         }
2509
2510         priv->hw_params.tfd_size = sizeof(struct iwl3945_tfd);
2511         priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_3K;
2512         priv->hw_params.max_pkt_size = 2342;
2513         priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2514         priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2515         priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2516         priv->hw_params.bcast_sta_id = IWL3945_BROADCAST_ID;
2517
2518         priv->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2519
2520         return 0;
2521 }
2522
2523 unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
2524                           struct iwl3945_frame *frame, u8 rate)
2525 {
2526         struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
2527         unsigned int frame_size;
2528
2529         tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
2530         memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2531
2532         tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
2533         tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2534
2535         frame_size = iwl3945_fill_beacon_frame(priv,
2536                                 tx_beacon_cmd->frame,
2537                                 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2538
2539         BUG_ON(frame_size > MAX_MPDU_SIZE);
2540         tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2541
2542         tx_beacon_cmd->tx.rate = rate;
2543         tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2544                                       TX_CMD_FLG_TSF_MSK);
2545
2546         /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2547         tx_beacon_cmd->tx.supp_rates[0] =
2548                 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2549
2550         tx_beacon_cmd->tx.supp_rates[1] =
2551                 (IWL_CCK_BASIC_RATES_MASK & 0xF);
2552
2553         return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
2554 }
2555
2556 void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
2557 {
2558         priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
2559         priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2560 }
2561
2562 void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
2563 {
2564         INIT_DELAYED_WORK(&priv->thermal_periodic,
2565                           iwl3945_bg_reg_txpower_periodic);
2566 }
2567
2568 void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
2569 {
2570         cancel_delayed_work(&priv->thermal_periodic);
2571 }
2572
2573 /* check contents of special bootstrap uCode SRAM */
2574 static int iwl3945_verify_bsm(struct iwl_priv *priv)
2575  {
2576         __le32 *image = priv->ucode_boot.v_addr;
2577         u32 len = priv->ucode_boot.len;
2578         u32 reg;
2579         u32 val;
2580
2581         IWL_DEBUG_INFO("Begin verify bsm\n");
2582
2583         /* verify BSM SRAM contents */
2584         val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
2585         for (reg = BSM_SRAM_LOWER_BOUND;
2586              reg < BSM_SRAM_LOWER_BOUND + len;
2587              reg += sizeof(u32), image++) {
2588                 val = iwl_read_prph(priv, reg);
2589                 if (val != le32_to_cpu(*image)) {
2590                         IWL_ERR(priv, "BSM uCode verification failed at "
2591                                   "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2592                                   BSM_SRAM_LOWER_BOUND,
2593                                   reg - BSM_SRAM_LOWER_BOUND, len,
2594                                   val, le32_to_cpu(*image));
2595                         return -EIO;
2596                 }
2597         }
2598
2599         IWL_DEBUG_INFO("BSM bootstrap uCode image OK\n");
2600
2601         return 0;
2602 }
2603
2604
2605 /******************************************************************************
2606  *
2607  * EEPROM related functions
2608  *
2609  ******************************************************************************/
2610
2611 /*
2612  * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2613  * embedded controller) as EEPROM reader; each read is a series of pulses
2614  * to/from the EEPROM chip, not a single event, so even reads could conflict
2615  * if they weren't arbitrated by some ownership mechanism.  Here, the driver
2616  * simply claims ownership, which should be safe when this function is called
2617  * (i.e. before loading uCode!).
2618  */
2619 static int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
2620 {
2621         _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2622         return 0;
2623 }
2624
2625
2626 static void iwl3945_eeprom_release_semaphore(struct iwl_priv *priv)
2627 {
2628         return;
2629 }
2630
2631  /**
2632   * iwl3945_load_bsm - Load bootstrap instructions
2633   *
2634   * BSM operation:
2635   *
2636   * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2637   * in special SRAM that does not power down during RFKILL.  When powering back
2638   * up after power-saving sleeps (or during initial uCode load), the BSM loads
2639   * the bootstrap program into the on-board processor, and starts it.
2640   *
2641   * The bootstrap program loads (via DMA) instructions and data for a new
2642   * program from host DRAM locations indicated by the host driver in the
2643   * BSM_DRAM_* registers.  Once the new program is loaded, it starts
2644   * automatically.
2645   *
2646   * When initializing the NIC, the host driver points the BSM to the
2647   * "initialize" uCode image.  This uCode sets up some internal data, then
2648   * notifies host via "initialize alive" that it is complete.
2649   *
2650   * The host then replaces the BSM_DRAM_* pointer values to point to the
2651   * normal runtime uCode instructions and a backup uCode data cache buffer
2652   * (filled initially with starting data values for the on-board processor),
2653   * then triggers the "initialize" uCode to load and launch the runtime uCode,
2654   * which begins normal operation.
2655   *
2656   * When doing a power-save shutdown, runtime uCode saves data SRAM into
2657   * the backup data cache in DRAM before SRAM is powered down.
2658   *
2659   * When powering back up, the BSM loads the bootstrap program.  This reloads
2660   * the runtime uCode instructions and the backup data cache into SRAM,
2661   * and re-launches the runtime uCode from where it left off.
2662   */
2663 static int iwl3945_load_bsm(struct iwl_priv *priv)
2664 {
2665         __le32 *image = priv->ucode_boot.v_addr;
2666         u32 len = priv->ucode_boot.len;
2667         dma_addr_t pinst;
2668         dma_addr_t pdata;
2669         u32 inst_len;
2670         u32 data_len;
2671         int rc;
2672         int i;
2673         u32 done;
2674         u32 reg_offset;
2675
2676         IWL_DEBUG_INFO("Begin load bsm\n");
2677
2678         /* make sure bootstrap program is no larger than BSM's SRAM size */
2679         if (len > IWL39_MAX_BSM_SIZE)
2680                 return -EINVAL;
2681
2682         /* Tell bootstrap uCode where to find the "Initialize" uCode
2683         *   in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2684         * NOTE:  iwl3945_initialize_alive_start() will replace these values,
2685         *        after the "initialize" uCode has run, to point to
2686         *        runtime/protocol instructions and backup data cache. */
2687         pinst = priv->ucode_init.p_addr;
2688         pdata = priv->ucode_init_data.p_addr;
2689         inst_len = priv->ucode_init.len;
2690         data_len = priv->ucode_init_data.len;
2691
2692         rc = iwl_grab_nic_access(priv);
2693         if (rc)
2694                 return rc;
2695
2696         iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2697         iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2698         iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2699         iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2700
2701         /* Fill BSM memory with bootstrap instructions */
2702         for (reg_offset = BSM_SRAM_LOWER_BOUND;
2703              reg_offset < BSM_SRAM_LOWER_BOUND + len;
2704              reg_offset += sizeof(u32), image++)
2705                 _iwl_write_prph(priv, reg_offset,
2706                                           le32_to_cpu(*image));
2707
2708         rc = iwl3945_verify_bsm(priv);
2709         if (rc) {
2710                 iwl_release_nic_access(priv);
2711                 return rc;
2712         }
2713
2714         /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2715         iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
2716         iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
2717                                  IWL39_RTC_INST_LOWER_BOUND);
2718         iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2719
2720         /* Load bootstrap code into instruction SRAM now,
2721          *   to prepare to load "initialize" uCode */
2722         iwl_write_prph(priv, BSM_WR_CTRL_REG,
2723                 BSM_WR_CTRL_REG_BIT_START);
2724
2725         /* Wait for load of bootstrap uCode to finish */
2726         for (i = 0; i < 100; i++) {
2727                 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
2728                 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2729                         break;
2730                 udelay(10);
2731         }
2732         if (i < 100)
2733                 IWL_DEBUG_INFO("BSM write complete, poll %d iterations\n", i);
2734         else {
2735                 IWL_ERR(priv, "BSM write did not complete!\n");
2736                 return -EIO;
2737         }
2738
2739         /* Enable future boot loads whenever power management unit triggers it
2740          *   (e.g. when powering back up after power-save shutdown) */
2741         iwl_write_prph(priv, BSM_WR_CTRL_REG,
2742                 BSM_WR_CTRL_REG_BIT_START_EN);
2743
2744         iwl_release_nic_access(priv);
2745
2746         return 0;
2747 }
2748
2749 static struct iwl_lib_ops iwl3945_lib = {
2750         .txq_attach_buf_to_tfd = iwl3945_hw_txq_attach_buf_to_tfd,
2751         .txq_free_tfd = iwl3945_hw_txq_free_tfd,
2752         .txq_init = iwl3945_hw_tx_queue_init,
2753         .load_ucode = iwl3945_load_bsm,
2754         .apm_ops = {
2755                 .init = iwl3945_apm_init,
2756                 .reset = iwl3945_apm_reset,
2757                 .stop = iwl3945_apm_stop,
2758                 .config = iwl3945_nic_config,
2759                 .set_pwr_src = iwl3945_set_pwr_src,
2760         },
2761         .eeprom_ops = {
2762                 .regulatory_bands = {
2763                         EEPROM_REGULATORY_BAND_1_CHANNELS,
2764                         EEPROM_REGULATORY_BAND_2_CHANNELS,
2765                         EEPROM_REGULATORY_BAND_3_CHANNELS,
2766                         EEPROM_REGULATORY_BAND_4_CHANNELS,
2767                         EEPROM_REGULATORY_BAND_5_CHANNELS,
2768                         IWL3945_EEPROM_IMG_SIZE,
2769                         IWL3945_EEPROM_IMG_SIZE,
2770                 },
2771                 .verify_signature  = iwlcore_eeprom_verify_signature,
2772                 .acquire_semaphore = iwl3945_eeprom_acquire_semaphore,
2773                 .release_semaphore = iwl3945_eeprom_release_semaphore,
2774                 .query_addr = iwlcore_eeprom_query_addr,
2775         },
2776         .send_tx_power  = iwl3945_send_tx_power,
2777 };
2778
2779 static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = {
2780         .get_hcmd_size = iwl3945_get_hcmd_size,
2781 };
2782
2783 static struct iwl_ops iwl3945_ops = {
2784         .lib = &iwl3945_lib,
2785         .utils = &iwl3945_hcmd_utils,
2786 };
2787
2788 static struct iwl_cfg iwl3945_bg_cfg = {
2789         .name = "3945BG",
2790         .fw_name_pre = IWL3945_FW_PRE,
2791         .ucode_api_max = IWL3945_UCODE_API_MAX,
2792         .ucode_api_min = IWL3945_UCODE_API_MIN,
2793         .sku = IWL_SKU_G,
2794         .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2795         .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2796         .ops = &iwl3945_ops,
2797         .mod_params = &iwl3945_mod_params
2798 };
2799
2800 static struct iwl_cfg iwl3945_abg_cfg = {
2801         .name = "3945ABG",
2802         .fw_name_pre = IWL3945_FW_PRE,
2803         .ucode_api_max = IWL3945_UCODE_API_MAX,
2804         .ucode_api_min = IWL3945_UCODE_API_MIN,
2805         .sku = IWL_SKU_A|IWL_SKU_G,
2806         .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2807         .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2808         .ops = &iwl3945_ops,
2809         .mod_params = &iwl3945_mod_params
2810 };
2811
2812 struct pci_device_id iwl3945_hw_card_ids[] = {
2813         {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2814         {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2815         {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2816         {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2817         {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2818         {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
2819         {0}
2820 };
2821
2822 MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);