SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/iwlwifi/iwl-3945.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2008 Intel Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * James P. Ketrenos <ipw2100-admin@linux.intel.com>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  *****************************************************************************/
  26
  27 #include <linux/kernel.h>
  28 #include <linux/module.h>
  29 #include <linux/init.h>
  30 #include <linux/pci.h>
  31 #include <linux/dma-mapping.h>
  32 #include <linux/delay.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/netdevice.h>
  35 #include <linux/wireless.h>
  36 #include <linux/firmware.h>
  37 #include <linux/etherdevice.h>
  38 #include <asm/unaligned.h>
  39 #include <net/mac80211.h>
  40
  41 #include "iwl-3945-core.h"
  42 #include "iwl-3945.h"
  43 #include "iwl-helpers.h"
  44 #include "iwl-3945-rs.h"
  45
  46 #define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np)    \
  47         [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP,   \
  48                                     IWL_RATE_##r##M_IEEE,   \
  49                                     IWL_RATE_##ip##M_INDEX, \
  50                                     IWL_RATE_##in##M_INDEX, \
  51                                     IWL_RATE_##rp##M_INDEX, \
  52                                     IWL_RATE_##rn##M_INDEX, \
  53                                     IWL_RATE_##pp##M_INDEX, \
  54                                     IWL_RATE_##np##M_INDEX, \
  55                                     IWL_RATE_##r##M_INDEX_TABLE, \
  56                                     IWL_RATE_##ip##M_INDEX_TABLE }
  57
  58 /*
  59  * Parameter order:
  60  *   rate, prev rate, next rate, prev tgg rate, next tgg rate
  61  *
  62  * If there isn't a valid next or previous rate then INV is used which
  63  * maps to IWL_RATE_INVALID
  64  *
  65  */
  66 const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT] = {
  67         IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2),    /*  1mbps */
  68         IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5),          /*  2mbps */
  69         IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11),        /*5.5mbps */
  70         IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18),      /* 11mbps */
  71         IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11),        /*  6mbps */
  72         IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11),       /*  9mbps */
  73         IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18),   /* 12mbps */
  74         IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24),   /* 18mbps */
  75         IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36),   /* 24mbps */
  76         IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48),   /* 36mbps */
  77         IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54),   /* 48mbps */
  78         IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
  79 };
  80
  81 /* 1 = enable the iwl3945_disable_events() function */
  82 #define IWL_EVT_DISABLE (0)
  83 #define IWL_EVT_DISABLE_SIZE (1532/32)
  84
  85 /**
  86  * iwl3945_disable_events - Disable selected events in uCode event log
  87  *
  88  * Disable an event by writing "1"s into "disable"
  89  *   bitmap in SRAM.  Bit position corresponds to Event # (id/type).
  90  *   Default values of 0 enable uCode events to be logged.
  91  * Use for only special debugging.  This function is just a placeholder as-is,
  92  *   you'll need to provide the special bits! ...
  93  *   ... and set IWL_EVT_DISABLE to 1. */
  94 void iwl3945_disable_events(struct iwl3945_priv *priv)
  95 {
  96         int ret;
  97         int i;
  98         u32 base;               /* SRAM address of event log header */
  99         u32 disable_ptr;        /* SRAM address of event-disable bitmap array */
 100         u32 array_size;         /* # of u32 entries in array */
 101         u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
 102                 0x00000000,     /*   31 -    0  Event id numbers */
 103                 0x00000000,     /*   63 -   32 */
 104                 0x00000000,     /*   95 -   64 */
 105                 0x00000000,     /*  127 -   96 */
 106                 0x00000000,     /*  159 -  128 */
 107                 0x00000000,     /*  191 -  160 */
 108                 0x00000000,     /*  223 -  192 */
 109                 0x00000000,     /*  255 -  224 */
 110                 0x00000000,     /*  287 -  256 */
 111                 0x00000000,     /*  319 -  288 */
 112                 0x00000000,     /*  351 -  320 */
 113                 0x00000000,     /*  383 -  352 */
 114                 0x00000000,     /*  415 -  384 */
 115                 0x00000000,     /*  447 -  416 */
 116                 0x00000000,     /*  479 -  448 */
 117                 0x00000000,     /*  511 -  480 */
 118                 0x00000000,     /*  543 -  512 */
 119                 0x00000000,     /*  575 -  544 */
 120                 0x00000000,     /*  607 -  576 */
 121                 0x00000000,     /*  639 -  608 */
 122                 0x00000000,     /*  671 -  640 */
 123                 0x00000000,     /*  703 -  672 */
 124                 0x00000000,     /*  735 -  704 */
 125                 0x00000000,     /*  767 -  736 */
 126                 0x00000000,     /*  799 -  768 */
 127                 0x00000000,     /*  831 -  800 */
 128                 0x00000000,     /*  863 -  832 */
 129                 0x00000000,     /*  895 -  864 */
 130                 0x00000000,     /*  927 -  896 */
 131                 0x00000000,     /*  959 -  928 */
 132                 0x00000000,     /*  991 -  960 */
 133                 0x00000000,     /* 1023 -  992 */
 134                 0x00000000,     /* 1055 - 1024 */
 135                 0x00000000,     /* 1087 - 1056 */
 136                 0x00000000,     /* 1119 - 1088 */
 137                 0x00000000,     /* 1151 - 1120 */
 138                 0x00000000,     /* 1183 - 1152 */
 139                 0x00000000,     /* 1215 - 1184 */
 140                 0x00000000,     /* 1247 - 1216 */
 141                 0x00000000,     /* 1279 - 1248 */
 142                 0x00000000,     /* 1311 - 1280 */
 143                 0x00000000,     /* 1343 - 1312 */
 144                 0x00000000,     /* 1375 - 1344 */
 145                 0x00000000,     /* 1407 - 1376 */
 146                 0x00000000,     /* 1439 - 1408 */
 147                 0x00000000,     /* 1471 - 1440 */
 148                 0x00000000,     /* 1503 - 1472 */
 149         };
 150
 151         base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
 152         if (!iwl3945_hw_valid_rtc_data_addr(base)) {
 153                 IWL_ERROR("Invalid event log pointer 0x%08X\n", base);
 154                 return;
 155         }
 156
 157         ret = iwl3945_grab_nic_access(priv);
 158         if (ret) {
 159                 IWL_WARNING("Can not read from adapter at this time.\n");
 160                 return;
 161         }
 162
 163         disable_ptr = iwl3945_read_targ_mem(priv, base + (4 * sizeof(u32)));
 164         array_size = iwl3945_read_targ_mem(priv, base + (5 * sizeof(u32)));
 165         iwl3945_release_nic_access(priv);
 166
 167         if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
 168                 IWL_DEBUG_INFO("Disabling selected uCode log events at 0x%x\n",
 169                                disable_ptr);
 170                 ret = iwl3945_grab_nic_access(priv);
 171                 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
 172                         iwl3945_write_targ_mem(priv,
 173                                            disable_ptr + (i * sizeof(u32)),
 174                                            evt_disable[i]);
 175
 176                 iwl3945_release_nic_access(priv);
 177         } else {
 178                 IWL_DEBUG_INFO("Selected uCode log events may be disabled\n");
 179                 IWL_DEBUG_INFO("  by writing \"1\"s into disable bitmap\n");
 180                 IWL_DEBUG_INFO("  in SRAM at 0x%x, size %d u32s\n",
 181                                disable_ptr, array_size);
 182         }
 183
 184 }
 185
 186 static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
 187 {
 188         int idx;
 189
 190         for (idx = 0; idx < IWL_RATE_COUNT; idx++)
 191                 if (iwl3945_rates[idx].plcp == plcp)
 192                         return idx;
 193         return -1;
 194 }
 195
 196 /**
 197  * iwl3945_get_antenna_flags - Get antenna flags for RXON command
 198  * @priv: eeprom and antenna fields are used to determine antenna flags
 199  *
 200  * priv->eeprom  is used to determine if antenna AUX/MAIN are reversed
 201  * priv->antenna specifies the antenna diversity mode:
 202  *
 203  * IWL_ANTENNA_DIVERISTY - NIC selects best antenna by itself
 204  * IWL_ANTENNA_MAIN      - Force MAIN antenna
 205  * IWL_ANTENNA_AUX       - Force AUX antenna
 206  */
 207 __le32 iwl3945_get_antenna_flags(const struct iwl3945_priv *priv)
 208 {
 209         switch (priv->antenna) {
 210         case IWL_ANTENNA_DIVERSITY:
 211                 return 0;
 212
 213         case IWL_ANTENNA_MAIN:
 214                 if (priv->eeprom.antenna_switch_type)
 215                         return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
 216                 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
 217
 218         case IWL_ANTENNA_AUX:
 219                 if (priv->eeprom.antenna_switch_type)
 220                         return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_A_MSK;
 221                 return RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_B_MSK;
 222         }
 223
 224         /* bad antenna selector value */
 225         IWL_ERROR("Bad antenna selector value (0x%x)\n", priv->antenna);
 226         return 0;               /* "diversity" is default if error */
 227 }
 228
 229 #ifdef CONFIG_IWL3945_DEBUG
 230 #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
 231
 232 static const char *iwl3945_get_tx_fail_reason(u32 status)
 233 {
 234         switch (status & TX_STATUS_MSK) {
 235         case TX_STATUS_SUCCESS:
 236                 return "SUCCESS";
 237                 TX_STATUS_ENTRY(SHORT_LIMIT);
 238                 TX_STATUS_ENTRY(LONG_LIMIT);
 239                 TX_STATUS_ENTRY(FIFO_UNDERRUN);
 240                 TX_STATUS_ENTRY(MGMNT_ABORT);
 241                 TX_STATUS_ENTRY(NEXT_FRAG);
 242                 TX_STATUS_ENTRY(LIFE_EXPIRE);
 243                 TX_STATUS_ENTRY(DEST_PS);
 244                 TX_STATUS_ENTRY(ABORTED);
 245                 TX_STATUS_ENTRY(BT_RETRY);
 246                 TX_STATUS_ENTRY(STA_INVALID);
 247                 TX_STATUS_ENTRY(FRAG_DROPPED);
 248                 TX_STATUS_ENTRY(TID_DISABLE);
 249                 TX_STATUS_ENTRY(FRAME_FLUSHED);
 250                 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
 251                 TX_STATUS_ENTRY(TX_LOCKED);
 252                 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
 253         }
 254
 255         return "UNKNOWN";
 256 }
 257 #else
 258 static inline const char *iwl3945_get_tx_fail_reason(u32 status)
 259 {
 260         return "";
 261 }
 262 #endif
 263
 264
 265 /**
 266  * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
 267  *
 268  * When FW advances 'R' index, all entries between old and new 'R' index
 269  * need to be reclaimed. As result, some free space forms. If there is
 270  * enough free space (> low mark), wake the stack that feeds us.
 271  */
 272 static void iwl3945_tx_queue_reclaim(struct iwl3945_priv *priv,
 273                                      int txq_id, int index)
 274 {
 275         struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
 276         struct iwl3945_queue *q = &txq->q;
 277         struct iwl3945_tx_info *tx_info;
 278
 279         BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
 280
 281         for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
 282                 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
 283
 284                 tx_info = &txq->txb[txq->q.read_ptr];
 285                 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
 286                 tx_info->skb[0] = NULL;
 287                 iwl3945_hw_txq_free_tfd(priv, txq);
 288         }
 289
 290         if (iwl3945_queue_space(q) > q->low_mark && (txq_id >= 0) &&
 291                         (txq_id != IWL_CMD_QUEUE_NUM) &&
 292                         priv->mac80211_registered)
 293                 ieee80211_wake_queue(priv->hw, txq_id);
 294 }
 295
 296 /**
 297  * iwl3945_rx_reply_tx - Handle Tx response
 298  */
 299 static void iwl3945_rx_reply_tx(struct iwl3945_priv *priv,
 300                             struct iwl3945_rx_mem_buffer *rxb)
 301 {
 302         struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
 303         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
 304         int txq_id = SEQ_TO_QUEUE(sequence);
 305         int index = SEQ_TO_INDEX(sequence);
 306         struct iwl3945_tx_queue *txq = &priv->txq[txq_id];
 307         struct ieee80211_tx_info *info;
 308         struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
 309         u32  status = le32_to_cpu(tx_resp->status);
 310         int rate_idx;
 311
 312         if ((index >= txq->q.n_bd) || (iwl3945_x2_queue_used(&txq->q, index) == 0)) {
 313                 IWL_ERROR("Read index for DMA queue txq_id (%d) index %d "
 314                           "is out of range [0-%d] %d %d\n", txq_id,
 315                           index, txq->q.n_bd, txq->q.write_ptr,
 316                           txq->q.read_ptr);
 317                 return;
 318         }
 319
 320         info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
 321         memset(&info->status, 0, sizeof(info->status));
 322
 323         info->status.retry_count = tx_resp->failure_frame;
 324         /* tx_status->rts_retry_count = tx_resp->failure_rts; */
 325         info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
 326                                 IEEE80211_TX_STAT_ACK : 0;
 327
 328         IWL_DEBUG_TX("Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
 329                         txq_id, iwl3945_get_tx_fail_reason(status), status,
 330                         tx_resp->rate, tx_resp->failure_frame);
 331
 332         rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
 333         if (info->band == IEEE80211_BAND_5GHZ)
 334                 rate_idx -= IWL_FIRST_OFDM_RATE;
 335         info->tx_rate_idx = rate_idx;
 336         IWL_DEBUG_TX_REPLY("Tx queue reclaim %d\n", index);
 337         iwl3945_tx_queue_reclaim(priv, txq_id, index);
 338
 339         if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
 340                 IWL_ERROR("TODO:  Implement Tx ABORT REQUIRED!!!\n");
 341 }
 342
 343
 344
 345 /*****************************************************************************
 346  *
 347  * Intel PRO/Wireless 3945ABG/BG Network Connection
 348  *
 349  *  RX handler implementations
 350  *
 351  *****************************************************************************/
 352
 353 void iwl3945_hw_rx_statistics(struct iwl3945_priv *priv, struct iwl3945_rx_mem_buffer *rxb)
 354 {
 355         struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
 356         IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
 357                      (int)sizeof(struct iwl3945_notif_statistics),
 358                      le32_to_cpu(pkt->len));
 359
 360         memcpy(&priv->statistics, pkt->u.raw, sizeof(priv->statistics));
 361
 362         iwl3945_led_background(priv);
 363
 364         priv->last_statistics_time = jiffies;
 365 }
 366
 367 /******************************************************************************
 368  *
 369  * Misc. internal state and helper functions
 370  *
 371  ******************************************************************************/
 372 #ifdef CONFIG_IWL3945_DEBUG
 373
 374 /**
 375  * iwl3945_report_frame - dump frame to syslog during debug sessions
 376  *
 377  * You may hack this function to show different aspects of received frames,
 378  * including selective frame dumps.
 379  * group100 parameter selects whether to show 1 out of 100 good frames.
 380  */
 381 static void iwl3945_dbg_report_frame(struct iwl3945_priv *priv,
 382                       struct iwl3945_rx_packet *pkt,
 383                       struct ieee80211_hdr *header, int group100)
 384 {
 385         u32 to_us;
 386         u32 print_summary = 0;
 387         u32 print_dump = 0;     /* set to 1 to dump all frames' contents */
 388         u32 hundred = 0;
 389         u32 dataframe = 0;
 390         __le16 fc;
 391         u16 seq_ctl;
 392         u16 channel;
 393         u16 phy_flags;
 394         u16 length;
 395         u16 status;
 396         u16 bcn_tmr;
 397         u32 tsf_low;
 398         u64 tsf;
 399         u8 rssi;
 400         u8 agc;
 401         u16 sig_avg;
 402         u16 noise_diff;
 403         struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
 404         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
 405         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
 406         u8 *data = IWL_RX_DATA(pkt);
 407
 408         /* MAC header */
 409         fc = header->frame_control;
 410         seq_ctl = le16_to_cpu(header->seq_ctrl);
 411
 412         /* metadata */
 413         channel = le16_to_cpu(rx_hdr->channel);
 414         phy_flags = le16_to_cpu(rx_hdr->phy_flags);
 415         length = le16_to_cpu(rx_hdr->len);
 416
 417         /* end-of-frame status and timestamp */
 418         status = le32_to_cpu(rx_end->status);
 419         bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
 420         tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
 421         tsf = le64_to_cpu(rx_end->timestamp);
 422
 423         /* signal statistics */
 424         rssi = rx_stats->rssi;
 425         agc = rx_stats->agc;
 426         sig_avg = le16_to_cpu(rx_stats->sig_avg);
 427         noise_diff = le16_to_cpu(rx_stats->noise_diff);
 428
 429         to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
 430
 431         /* if data frame is to us and all is good,
 432          *   (optionally) print summary for only 1 out of every 100 */
 433         if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
 434             cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
 435                 dataframe = 1;
 436                 if (!group100)
 437                         print_summary = 1;      /* print each frame */
 438                 else if (priv->framecnt_to_us < 100) {
 439                         priv->framecnt_to_us++;
 440                         print_summary = 0;
 441                 } else {
 442                         priv->framecnt_to_us = 0;
 443                         print_summary = 1;
 444                         hundred = 1;
 445                 }
 446         } else {
 447                 /* print summary for all other frames */
 448                 print_summary = 1;
 449         }
 450
 451         if (print_summary) {
 452                 char *title;
 453                 int rate;
 454
 455                 if (hundred)
 456                         title = "100Frames";
 457                 else if (ieee80211_has_retry(fc))
 458                         title = "Retry";
 459                 else if (ieee80211_is_assoc_resp(fc))
 460                         title = "AscRsp";
 461                 else if (ieee80211_is_reassoc_resp(fc))
 462                         title = "RasRsp";
 463                 else if (ieee80211_is_probe_resp(fc)) {
 464                         title = "PrbRsp";
 465                         print_dump = 1; /* dump frame contents */
 466                 } else if (ieee80211_is_beacon(fc)) {
 467                         title = "Beacon";
 468                         print_dump = 1; /* dump frame contents */
 469                 } else if (ieee80211_is_atim(fc))
 470                         title = "ATIM";
 471                 else if (ieee80211_is_auth(fc))
 472                         title = "Auth";
 473                 else if (ieee80211_is_deauth(fc))
 474                         title = "DeAuth";
 475                 else if (ieee80211_is_disassoc(fc))
 476                         title = "DisAssoc";
 477                 else
 478                         title = "Frame";
 479
 480                 rate = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
 481                 if (rate == -1)
 482                         rate = 0;
 483                 else
 484                         rate = iwl3945_rates[rate].ieee / 2;
 485
 486                 /* print frame summary.
 487                  * MAC addresses show just the last byte (for brevity),
 488                  *    but you can hack it to show more, if you'd like to. */
 489                 if (dataframe)
 490                         IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
 491                                      "len=%u, rssi=%d, chnl=%d, rate=%d, \n",
 492                                      title, le16_to_cpu(fc), header->addr1[5],
 493                                      length, rssi, channel, rate);
 494                 else {
 495                         /* src/dst addresses assume managed mode */
 496                         IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
 497                                      "src=0x%02x, rssi=%u, tim=%lu usec, "
 498                                      "phy=0x%02x, chnl=%d\n",
 499                                      title, le16_to_cpu(fc), header->addr1[5],
 500                                      header->addr3[5], rssi,
 501                                      tsf_low - priv->scan_start_tsf,
 502                                      phy_flags, channel);
 503                 }
 504         }
 505         if (print_dump)
 506                 iwl3945_print_hex_dump(IWL_DL_RX, data, length);
 507 }
 508 #else
 509 static inline void iwl3945_dbg_report_frame(struct iwl3945_priv *priv,
 510                       struct iwl3945_rx_packet *pkt,
 511                       struct ieee80211_hdr *header, int group100)
 512 {
 513 }
 514 #endif
 515
 516 /* This is necessary only for a number of statistics, see the caller. */
 517 static int iwl3945_is_network_packet(struct iwl3945_priv *priv,
 518                 struct ieee80211_hdr *header)
 519 {
 520         /* Filter incoming packets to determine if they are targeted toward
 521          * this network, discarding packets coming from ourselves */
 522         switch (priv->iw_mode) {
 523         case IEEE80211_IF_TYPE_IBSS: /* Header: Dest. | Source    | BSSID */
 524                 /* packets to our IBSS update information */
 525                 return !compare_ether_addr(header->addr3, priv->bssid);
 526         case IEEE80211_IF_TYPE_STA: /* Header: Dest. | AP{BSSID} | Source */
 527                 /* packets to our IBSS update information */
 528                 return !compare_ether_addr(header->addr2, priv->bssid);
 529         default:
 530                 return 1;
 531         }
 532 }
 533
 534 static void iwl3945_pass_packet_to_mac80211(struct iwl3945_priv *priv,
 535                                    struct iwl3945_rx_mem_buffer *rxb,
 536                                    struct ieee80211_rx_status *stats)
 537 {
 538         struct iwl3945_rx_packet *pkt = (struct iwl3945_rx_packet *)rxb->skb->data;
 539 #ifdef CONFIG_IWL3945_LEDS
 540         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
 541 #endif
 542         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
 543         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
 544         short len = le16_to_cpu(rx_hdr->len);
 545
 546         /* We received data from the HW, so stop the watchdog */
 547         if (unlikely((len + IWL_RX_FRAME_SIZE) > skb_tailroom(rxb->skb))) {
 548                 IWL_DEBUG_DROP("Corruption detected!\n");
 549                 return;
 550         }
 551
 552         /* We only process data packets if the interface is open */
 553         if (unlikely(!priv->is_open)) {
 554                 IWL_DEBUG_DROP_LIMIT
 555                     ("Dropping packet while interface is not open.\n");
 556                 return;
 557         }
 558
 559         skb_reserve(rxb->skb, (void *)rx_hdr->payload - (void *)pkt);
 560         /* Set the size of the skb to the size of the frame */
 561         skb_put(rxb->skb, le16_to_cpu(rx_hdr->len));
 562
 563         if (iwl3945_param_hwcrypto)
 564                 iwl3945_set_decrypted_flag(priv, rxb->skb,
 565                                        le32_to_cpu(rx_end->status), stats);
 566
 567 #ifdef CONFIG_IWL3945_LEDS
 568         if (ieee80211_is_data(hdr->frame_control))
 569                 priv->rxtxpackets += len;
 570 #endif
 571         ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
 572         rxb->skb = NULL;
 573 }
 574
 575 #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
 576
 577 static void iwl3945_rx_reply_rx(struct iwl3945_priv *priv,
 578                                 struct iwl3945_rx_mem_buffer *rxb)
 579 {
 580         struct ieee80211_hdr *header;
 581         struct ieee80211_rx_status rx_status;
 582         struct iwl3945_rx_packet *pkt = (void *)rxb->skb->data;
 583         struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
 584         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
 585         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
 586         int snr;
 587         u16 rx_stats_sig_avg = le16_to_cpu(rx_stats->sig_avg);
 588         u16 rx_stats_noise_diff = le16_to_cpu(rx_stats->noise_diff);
 589         u8 network_packet;
 590
 591         rx_status.flag = 0;
 592         rx_status.mactime = le64_to_cpu(rx_end->timestamp);
 593         rx_status.freq =
 594                 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
 595         rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
 596                                 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
 597
 598         rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
 599         if (rx_status.band == IEEE80211_BAND_5GHZ)
 600                 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
 601
 602         rx_status.antenna = le16_to_cpu(rx_hdr->phy_flags &
 603                                         RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
 604
 605         /* set the preamble flag if appropriate */
 606         if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
 607                 rx_status.flag |= RX_FLAG_SHORTPRE;
 608
 609         if ((unlikely(rx_stats->phy_count > 20))) {
 610                 IWL_DEBUG_DROP
 611                     ("dsp size out of range [0,20]: "
 612                      "%d/n", rx_stats->phy_count);
 613                 return;
 614         }
 615
 616         if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
 617             || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
 618                 IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
 619                 return;
 620         }
 621
 622
 623
 624         /* Convert 3945's rssi indicator to dBm */
 625         rx_status.signal = rx_stats->rssi - IWL_RSSI_OFFSET;
 626
 627         /* Set default noise value to -127 */
 628         if (priv->last_rx_noise == 0)
 629                 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
 630
 631         /* 3945 provides noise info for OFDM frames only.
 632          * sig_avg and noise_diff are measured by the 3945's digital signal
 633          *   processor (DSP), and indicate linear levels of signal level and
 634          *   distortion/noise within the packet preamble after
 635          *   automatic gain control (AGC).  sig_avg should stay fairly
 636          *   constant if the radio's AGC is working well.
 637          * Since these values are linear (not dB or dBm), linear
 638          *   signal-to-noise ratio (SNR) is (sig_avg / noise_diff).
 639          * Convert linear SNR to dB SNR, then subtract that from rssi dBm
 640          *   to obtain noise level in dBm.
 641          * Calculate rx_status.signal (quality indicator in %) based on SNR. */
 642         if (rx_stats_noise_diff) {
 643                 snr = rx_stats_sig_avg / rx_stats_noise_diff;
 644                 rx_status.noise = rx_status.signal -
 645                                         iwl3945_calc_db_from_ratio(snr);
 646                 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal,
 647                                                          rx_status.noise);
 648
 649         /* If noise info not available, calculate signal quality indicator (%)
 650          *   using just the dBm signal level. */
 651         } else {
 652                 rx_status.noise = priv->last_rx_noise;
 653                 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal, 0);
 654         }
 655
 656
 657         IWL_DEBUG_STATS("Rssi %d noise %d qual %d sig_avg %d noise_diff %d\n",
 658                         rx_status.signal, rx_status.noise, rx_status.qual,
 659                         rx_stats_sig_avg, rx_stats_noise_diff);
 660
 661         header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
 662
 663         network_packet = iwl3945_is_network_packet(priv, header);
 664
 665         IWL_DEBUG_STATS_LIMIT("[%c] %d RSSI:%d Signal:%u, Noise:%u, Rate:%u\n",
 666                               network_packet ? '*' : ' ',
 667                               le16_to_cpu(rx_hdr->channel),
 668                               rx_status.signal, rx_status.signal,
 669                               rx_status.noise, rx_status.rate_idx);
 670
 671 #ifdef CONFIG_IWL3945_DEBUG
 672         if (iwl3945_debug_level & (IWL_DL_RX))
 673                 /* Set "1" to report good data frames in groups of 100 */
 674                 iwl3945_dbg_report_frame(priv, pkt, header, 1);
 675 #endif
 676
 677         if (network_packet) {
 678                 priv->last_beacon_time = le32_to_cpu(rx_end->beacon_timestamp);
 679                 priv->last_tsf = le64_to_cpu(rx_end->timestamp);
 680                 priv->last_rx_rssi = rx_status.signal;
 681                 priv->last_rx_noise = rx_status.noise;
 682         }
 683
 684         if (priv->iw_mode == IEEE80211_IF_TYPE_MNTR) {
 685                 iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
 686                 return;
 687         }
 688
 689         switch (le16_to_cpu(header->frame_control) & IEEE80211_FCTL_FTYPE) {
 690         case IEEE80211_FTYPE_MGMT:
 691         case IEEE80211_FTYPE_DATA:
 692                 /* fall through */
 693         default:
 694                 iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
 695                 break;
 696         }
 697 }
 698
 699 int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl3945_priv *priv, void *ptr,
 700                                  dma_addr_t addr, u16 len)
 701 {
 702         int count;
 703         u32 pad;
 704         struct iwl3945_tfd_frame *tfd = (struct iwl3945_tfd_frame *)ptr;
 705
 706         count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
 707         pad = TFD_CTL_PAD_GET(le32_to_cpu(tfd->control_flags));
 708
 709         if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
 710                 IWL_ERROR("Error can not send more than %d chunks\n",
 711                           NUM_TFD_CHUNKS);
 712                 return -EINVAL;
 713         }
 714
 715         tfd->pa[count].addr = cpu_to_le32(addr);
 716         tfd->pa[count].len = cpu_to_le32(len);
 717
 718         count++;
 719
 720         tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
 721                                          TFD_CTL_PAD_SET(pad));
 722
 723         return 0;
 724 }
 725
 726 /**
 727  * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
 728  *
 729  * Does NOT advance any indexes
 730  */
 731 int iwl3945_hw_txq_free_tfd(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
 732 {
 733         struct iwl3945_tfd_frame *bd_tmp = (struct iwl3945_tfd_frame *)&txq->bd[0];
 734         struct iwl3945_tfd_frame *bd = &bd_tmp[txq->q.read_ptr];
 735         struct pci_dev *dev = priv->pci_dev;
 736         int i;
 737         int counter;
 738
 739         /* classify bd */
 740         if (txq->q.id == IWL_CMD_QUEUE_NUM)
 741                 /* nothing to cleanup after for host commands */
 742                 return 0;
 743
 744         /* sanity check */
 745         counter = TFD_CTL_COUNT_GET(le32_to_cpu(bd->control_flags));
 746         if (counter > NUM_TFD_CHUNKS) {
 747                 IWL_ERROR("Too many chunks: %i\n", counter);
 748                 /* @todo issue fatal error, it is quite serious situation */
 749                 return 0;
 750         }
 751
 752         /* unmap chunks if any */
 753
 754         for (i = 1; i < counter; i++) {
 755                 pci_unmap_single(dev, le32_to_cpu(bd->pa[i].addr),
 756                                  le32_to_cpu(bd->pa[i].len), PCI_DMA_TODEVICE);
 757                 if (txq->txb[txq->q.read_ptr].skb[0]) {
 758                         struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
 759                         if (txq->txb[txq->q.read_ptr].skb[0]) {
 760                                 /* Can be called from interrupt context */
 761                                 dev_kfree_skb_any(skb);
 762                                 txq->txb[txq->q.read_ptr].skb[0] = NULL;
 763                         }
 764                 }
 765         }
 766         return 0;
 767 }
 768
 769 u8 iwl3945_hw_find_station(struct iwl3945_priv *priv, const u8 *addr)
 770 {
 771         int i;
 772         int ret = IWL_INVALID_STATION;
 773         unsigned long flags;
 774         DECLARE_MAC_BUF(mac);
 775
 776         spin_lock_irqsave(&priv->sta_lock, flags);
 777         for (i = IWL_STA_ID; i < priv->hw_setting.max_stations; i++)
 778                 if ((priv->stations[i].used) &&
 779                     (!compare_ether_addr
 780                      (priv->stations[i].sta.sta.addr, addr))) {
 781                         ret = i;
 782                         goto out;
 783                 }
 784
 785         IWL_DEBUG_INFO("can not find STA %s (total %d)\n",
 786                        print_mac(mac, addr), priv->num_stations);
 787  out:
 788         spin_unlock_irqrestore(&priv->sta_lock, flags);
 789         return ret;
 790 }
 791
 792 /**
 793  * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
 794  *
 795 */
 796 void iwl3945_hw_build_tx_cmd_rate(struct iwl3945_priv *priv,
 797                               struct iwl3945_cmd *cmd,
 798                               struct ieee80211_tx_info *info,
 799                               struct ieee80211_hdr *hdr, int sta_id, int tx_id)
 800 {
 801         unsigned long flags;
 802         u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
 803         u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT - 1);
 804         u16 rate_mask;
 805         int rate;
 806         u8 rts_retry_limit;
 807         u8 data_retry_limit;
 808         __le32 tx_flags;
 809         __le16 fc = hdr->frame_control;
 810
 811         rate = iwl3945_rates[rate_index].plcp;
 812         tx_flags = cmd->cmd.tx.tx_flags;
 813
 814         /* We need to figure out how to get the sta->supp_rates while
 815          * in this running context */
 816         rate_mask = IWL_RATES_MASK;
 817
 818         spin_lock_irqsave(&priv->sta_lock, flags);
 819
 820         priv->stations[sta_id].current_rate.rate_n_flags = rate;
 821
 822         if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) &&
 823             (sta_id != priv->hw_setting.bcast_sta_id) &&
 824                 (sta_id != IWL_MULTICAST_ID))
 825                 priv->stations[IWL_STA_ID].current_rate.rate_n_flags = rate;
 826
 827         spin_unlock_irqrestore(&priv->sta_lock, flags);
 828
 829         if (tx_id >= IWL_CMD_QUEUE_NUM)
 830                 rts_retry_limit = 3;
 831         else
 832                 rts_retry_limit = 7;
 833
 834         if (ieee80211_is_probe_resp(fc)) {
 835                 data_retry_limit = 3;
 836                 if (data_retry_limit < rts_retry_limit)
 837                         rts_retry_limit = data_retry_limit;
 838         } else
 839                 data_retry_limit = IWL_DEFAULT_TX_RETRY;
 840
 841         if (priv->data_retry_limit != -1)
 842                 data_retry_limit = priv->data_retry_limit;
 843
 844         if (ieee80211_is_mgmt(fc)) {
 845                 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
 846                 case cpu_to_le16(IEEE80211_STYPE_AUTH):
 847                 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
 848                 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
 849                 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
 850                         if (tx_flags & TX_CMD_FLG_RTS_MSK) {
 851                                 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
 852                                 tx_flags |= TX_CMD_FLG_CTS_MSK;
 853                         }
 854                         break;
 855                 default:
 856                         break;
 857                 }
 858         }
 859
 860         cmd->cmd.tx.rts_retry_limit = rts_retry_limit;
 861         cmd->cmd.tx.data_retry_limit = data_retry_limit;
 862         cmd->cmd.tx.rate = rate;
 863         cmd->cmd.tx.tx_flags = tx_flags;
 864
 865         /* OFDM */
 866         cmd->cmd.tx.supp_rates[0] =
 867            ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
 868
 869         /* CCK */
 870         cmd->cmd.tx.supp_rates[1] = (rate_mask & 0xF);
 871
 872         IWL_DEBUG_RATE("Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
 873                        "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
 874                        cmd->cmd.tx.rate, le32_to_cpu(cmd->cmd.tx.tx_flags),
 875                        cmd->cmd.tx.supp_rates[1], cmd->cmd.tx.supp_rates[0]);
 876 }
 877
 878 u8 iwl3945_sync_sta(struct iwl3945_priv *priv, int sta_id, u16 tx_rate, u8 flags)
 879 {
 880         unsigned long flags_spin;
 881         struct iwl3945_station_entry *station;
 882
 883         if (sta_id == IWL_INVALID_STATION)
 884                 return IWL_INVALID_STATION;
 885
 886         spin_lock_irqsave(&priv->sta_lock, flags_spin);
 887         station = &priv->stations[sta_id];
 888
 889         station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
 890         station->sta.rate_n_flags = cpu_to_le16(tx_rate);
 891         station->current_rate.rate_n_flags = tx_rate;
 892         station->sta.mode = STA_CONTROL_MODIFY_MSK;
 893
 894         spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
 895
 896         iwl3945_send_add_station(priv, &station->sta, flags);
 897         IWL_DEBUG_RATE("SCALE sync station %d to rate %d\n",
 898                         sta_id, tx_rate);
 899         return sta_id;
 900 }
 901
 902 static int iwl3945_nic_set_pwr_src(struct iwl3945_priv *priv, int pwr_max)
 903 {
 904         int rc;
 905         unsigned long flags;
 906
 907         spin_lock_irqsave(&priv->lock, flags);
 908         rc = iwl3945_grab_nic_access(priv);
 909         if (rc) {
 910                 spin_unlock_irqrestore(&priv->lock, flags);
 911                 return rc;
 912         }
 913
 914         if (!pwr_max) {
 915                 u32 val;
 916
 917                 rc = pci_read_config_dword(priv->pci_dev,
 918                                 PCI_POWER_SOURCE, &val);
 919                 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
 920                         iwl3945_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 921                                         APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 922                                         ~APMG_PS_CTRL_MSK_PWR_SRC);
 923                         iwl3945_release_nic_access(priv);
 924
 925                         iwl3945_poll_bit(priv, CSR_GPIO_IN,
 926                                      CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
 927                                      CSR_GPIO_IN_BIT_AUX_POWER, 5000);
 928                 } else
 929                         iwl3945_release_nic_access(priv);
 930         } else {
 931                 iwl3945_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 932                                 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 933                                 ~APMG_PS_CTRL_MSK_PWR_SRC);
 934
 935                 iwl3945_release_nic_access(priv);
 936                 iwl3945_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
 937                              CSR_GPIO_IN_BIT_AUX_POWER, 5000);  /* uS */
 938         }
 939         spin_unlock_irqrestore(&priv->lock, flags);
 940
 941         return rc;
 942 }
 943
 944 static int iwl3945_rx_init(struct iwl3945_priv *priv, struct iwl3945_rx_queue *rxq)
 945 {
 946         int rc;
 947         unsigned long flags;
 948
 949         spin_lock_irqsave(&priv->lock, flags);
 950         rc = iwl3945_grab_nic_access(priv);
 951         if (rc) {
 952                 spin_unlock_irqrestore(&priv->lock, flags);
 953                 return rc;
 954         }
 955
 956         iwl3945_write_direct32(priv, FH_RCSR_RBD_BASE(0), rxq->dma_addr);
 957         iwl3945_write_direct32(priv, FH_RCSR_RPTR_ADDR(0),
 958                              priv->hw_setting.shared_phys +
 959                              offsetof(struct iwl3945_shared, rx_read_ptr[0]));
 960         iwl3945_write_direct32(priv, FH_RCSR_WPTR(0), 0);
 961         iwl3945_write_direct32(priv, FH_RCSR_CONFIG(0),
 962                 ALM_FH_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
 963                 ALM_FH_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
 964                 ALM_FH_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
 965                 ALM_FH_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
 966                 (RX_QUEUE_SIZE_LOG << ALM_FH_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
 967                 ALM_FH_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
 968                 (1 << ALM_FH_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
 969                 ALM_FH_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
 970
 971         /* fake read to flush all prev I/O */
 972         iwl3945_read_direct32(priv, FH_RSSR_CTRL);
 973
 974         iwl3945_release_nic_access(priv);
 975         spin_unlock_irqrestore(&priv->lock, flags);
 976
 977         return 0;
 978 }
 979
 980 static int iwl3945_tx_reset(struct iwl3945_priv *priv)
 981 {
 982         int rc;
 983         unsigned long flags;
 984
 985         spin_lock_irqsave(&priv->lock, flags);
 986         rc = iwl3945_grab_nic_access(priv);
 987         if (rc) {
 988                 spin_unlock_irqrestore(&priv->lock, flags);
 989                 return rc;
 990         }
 991
 992         /* bypass mode */
 993         iwl3945_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
 994
 995         /* RA 0 is active */
 996         iwl3945_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
 997
 998         /* all 6 fifo are active */
 999         iwl3945_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
1000
1001         iwl3945_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
1002         iwl3945_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
1003         iwl3945_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
1004         iwl3945_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
1005
1006         iwl3945_write_direct32(priv, FH_TSSR_CBB_BASE,
1007                              priv->hw_setting.shared_phys);
1008
1009         iwl3945_write_direct32(priv, FH_TSSR_MSG_CONFIG,
1010                 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
1011                 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
1012                 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
1013                 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
1014                 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
1015                 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
1016                 ALM_FH_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
1017
1018         iwl3945_release_nic_access(priv);
1019         spin_unlock_irqrestore(&priv->lock, flags);
1020
1021         return 0;
1022 }
1023
1024 /**
1025  * iwl3945_txq_ctx_reset - Reset TX queue context
1026  *
1027  * Destroys all DMA structures and initialize them again
1028  */
1029 static int iwl3945_txq_ctx_reset(struct iwl3945_priv *priv)
1030 {
1031         int rc;
1032         int txq_id, slots_num;
1033
1034         iwl3945_hw_txq_ctx_free(priv);
1035
1036         /* Tx CMD queue */
1037         rc = iwl3945_tx_reset(priv);
1038         if (rc)
1039                 goto error;
1040
1041         /* Tx queue(s) */
1042         for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++) {
1043                 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
1044                                 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
1045                 rc = iwl3945_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
1046                                 txq_id);
1047                 if (rc) {
1048                         IWL_ERROR("Tx %d queue init failed\n", txq_id);
1049                         goto error;
1050                 }
1051         }
1052
1053         return rc;
1054
1055  error:
1056         iwl3945_hw_txq_ctx_free(priv);
1057         return rc;
1058 }
1059
1060 int iwl3945_hw_nic_init(struct iwl3945_priv *priv)
1061 {
1062         u8 rev_id;
1063         int rc;
1064         unsigned long flags;
1065         struct iwl3945_rx_queue *rxq = &priv->rxq;
1066
1067         iwl3945_power_init_handle(priv);
1068
1069         spin_lock_irqsave(&priv->lock, flags);
1070         iwl3945_set_bit(priv, CSR_ANA_PLL_CFG, CSR39_ANA_PLL_CFG_VAL);
1071         iwl3945_set_bit(priv, CSR_GIO_CHICKEN_BITS,
1072                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
1073
1074         iwl3945_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1075         rc = iwl3945_poll_bit(priv, CSR_GP_CNTRL,
1076                           CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1077                           CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1078         if (rc < 0) {
1079                 spin_unlock_irqrestore(&priv->lock, flags);
1080                 IWL_DEBUG_INFO("Failed to init the card\n");
1081                 return rc;
1082         }
1083
1084         rc = iwl3945_grab_nic_access(priv);
1085         if (rc) {
1086                 spin_unlock_irqrestore(&priv->lock, flags);
1087                 return rc;
1088         }
1089         iwl3945_write_prph(priv, APMG_CLK_EN_REG,
1090                                  APMG_CLK_VAL_DMA_CLK_RQT |
1091                                  APMG_CLK_VAL_BSM_CLK_RQT);
1092         udelay(20);
1093         iwl3945_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
1094                                     APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1095         iwl3945_release_nic_access(priv);
1096         spin_unlock_irqrestore(&priv->lock, flags);
1097
1098         /* Determine HW type */
1099         rc = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
1100         if (rc)
1101                 return rc;
1102         IWL_DEBUG_INFO("HW Revision ID = 0x%X\n", rev_id);
1103
1104         iwl3945_nic_set_pwr_src(priv, 1);
1105         spin_lock_irqsave(&priv->lock, flags);
1106
1107         if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
1108                 IWL_DEBUG_INFO("RTP type \n");
1109         else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
1110                 IWL_DEBUG_INFO("3945 RADIO-MB type\n");
1111                 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1112                             CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
1113         } else {
1114                 IWL_DEBUG_INFO("3945 RADIO-MM type\n");
1115                 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1116                             CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
1117         }
1118
1119         if (EEPROM_SKU_CAP_OP_MODE_MRC == priv->eeprom.sku_cap) {
1120                 IWL_DEBUG_INFO("SKU OP mode is mrc\n");
1121                 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1122                             CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
1123         } else
1124                 IWL_DEBUG_INFO("SKU OP mode is basic\n");
1125
1126         if ((priv->eeprom.board_revision & 0xF0) == 0xD0) {
1127                 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
1128                                priv->eeprom.board_revision);
1129                 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1130                             CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1131         } else {
1132                 IWL_DEBUG_INFO("3945ABG revision is 0x%X\n",
1133                                priv->eeprom.board_revision);
1134                 iwl3945_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
1135                               CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1136         }
1137
1138         if (priv->eeprom.almgor_m_version <= 1) {
1139                 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1140                             CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
1141                 IWL_DEBUG_INFO("Card M type A version is 0x%X\n",
1142                                priv->eeprom.almgor_m_version);
1143         } else {
1144                 IWL_DEBUG_INFO("Card M type B version is 0x%X\n",
1145                                priv->eeprom.almgor_m_version);
1146                 iwl3945_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1147                             CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
1148         }
1149         spin_unlock_irqrestore(&priv->lock, flags);
1150
1151         if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
1152                 IWL_DEBUG_RF_KILL("SW RF KILL supported in EEPROM.\n");
1153
1154         if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
1155                 IWL_DEBUG_RF_KILL("HW RF KILL supported in EEPROM.\n");
1156
1157         /* Allocate the RX queue, or reset if it is already allocated */
1158         if (!rxq->bd) {
1159                 rc = iwl3945_rx_queue_alloc(priv);
1160                 if (rc) {
1161                         IWL_ERROR("Unable to initialize Rx queue\n");
1162                         return -ENOMEM;
1163                 }
1164         } else
1165                 iwl3945_rx_queue_reset(priv, rxq);
1166
1167         iwl3945_rx_replenish(priv);
1168
1169         iwl3945_rx_init(priv, rxq);
1170
1171         spin_lock_irqsave(&priv->lock, flags);
1172
1173         /* Look at using this instead:
1174         rxq->need_update = 1;
1175         iwl3945_rx_queue_update_write_ptr(priv, rxq);
1176         */
1177
1178         rc = iwl3945_grab_nic_access(priv);
1179         if (rc) {
1180                 spin_unlock_irqrestore(&priv->lock, flags);
1181                 return rc;
1182         }
1183         iwl3945_write_direct32(priv, FH_RCSR_WPTR(0), rxq->write & ~7);
1184         iwl3945_release_nic_access(priv);
1185
1186         spin_unlock_irqrestore(&priv->lock, flags);
1187
1188         rc = iwl3945_txq_ctx_reset(priv);
1189         if (rc)
1190                 return rc;
1191
1192         set_bit(STATUS_INIT, &priv->status);
1193
1194         return 0;
1195 }
1196
1197 /**
1198  * iwl3945_hw_txq_ctx_free - Free TXQ Context
1199  *
1200  * Destroy all TX DMA queues and structures
1201  */
1202 void iwl3945_hw_txq_ctx_free(struct iwl3945_priv *priv)
1203 {
1204         int txq_id;
1205
1206         /* Tx queues */
1207         for (txq_id = 0; txq_id < TFD_QUEUE_MAX; txq_id++)
1208                 iwl3945_tx_queue_free(priv, &priv->txq[txq_id]);
1209 }
1210
1211 void iwl3945_hw_txq_ctx_stop(struct iwl3945_priv *priv)
1212 {
1213         int queue;
1214         unsigned long flags;
1215
1216         spin_lock_irqsave(&priv->lock, flags);
1217         if (iwl3945_grab_nic_access(priv)) {
1218                 spin_unlock_irqrestore(&priv->lock, flags);
1219                 iwl3945_hw_txq_ctx_free(priv);
1220                 return;
1221         }
1222
1223         /* stop SCD */
1224         iwl3945_write_prph(priv, ALM_SCD_MODE_REG, 0);
1225
1226         /* reset TFD queues */
1227         for (queue = TFD_QUEUE_MIN; queue < TFD_QUEUE_MAX; queue++) {
1228                 iwl3945_write_direct32(priv, FH_TCSR_CONFIG(queue), 0x0);
1229                 iwl3945_poll_direct_bit(priv, FH_TSSR_TX_STATUS,
1230                                 ALM_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(queue),
1231                                 1000);
1232         }
1233
1234         iwl3945_release_nic_access(priv);
1235         spin_unlock_irqrestore(&priv->lock, flags);
1236
1237         iwl3945_hw_txq_ctx_free(priv);
1238 }
1239
1240 int iwl3945_hw_nic_stop_master(struct iwl3945_priv *priv)
1241 {
1242         int rc = 0;
1243         u32 reg_val;
1244         unsigned long flags;
1245
1246         spin_lock_irqsave(&priv->lock, flags);
1247
1248         /* set stop master bit */
1249         iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
1250
1251         reg_val = iwl3945_read32(priv, CSR_GP_CNTRL);
1252
1253         if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE ==
1254             (reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE))
1255                 IWL_DEBUG_INFO("Card in power save, master is already "
1256                                "stopped\n");
1257         else {
1258                 rc = iwl3945_poll_bit(priv, CSR_RESET,
1259                                   CSR_RESET_REG_FLAG_MASTER_DISABLED,
1260                                   CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
1261                 if (rc < 0) {
1262                         spin_unlock_irqrestore(&priv->lock, flags);
1263                         return rc;
1264                 }
1265         }
1266
1267         spin_unlock_irqrestore(&priv->lock, flags);
1268         IWL_DEBUG_INFO("stop master\n");
1269
1270         return rc;
1271 }
1272
1273 int iwl3945_hw_nic_reset(struct iwl3945_priv *priv)
1274 {
1275         int rc;
1276         unsigned long flags;
1277
1278         iwl3945_hw_nic_stop_master(priv);
1279
1280         spin_lock_irqsave(&priv->lock, flags);
1281
1282         iwl3945_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1283
1284         rc = iwl3945_poll_bit(priv, CSR_GP_CNTRL,
1285                           CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1286                           CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1287
1288         rc = iwl3945_grab_nic_access(priv);
1289         if (!rc) {
1290                 iwl3945_write_prph(priv, APMG_CLK_CTRL_REG,
1291                                          APMG_CLK_VAL_BSM_CLK_RQT);
1292
1293                 udelay(10);
1294
1295                 iwl3945_set_bit(priv, CSR_GP_CNTRL,
1296                             CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1297
1298                 iwl3945_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1299                 iwl3945_write_prph(priv, APMG_RTC_INT_STT_REG,
1300                                         0xFFFFFFFF);
1301
1302                 /* enable DMA */
1303                 iwl3945_write_prph(priv, APMG_CLK_EN_REG,
1304                                          APMG_CLK_VAL_DMA_CLK_RQT |
1305                                          APMG_CLK_VAL_BSM_CLK_RQT);
1306                 udelay(10);
1307
1308                 iwl3945_set_bits_prph(priv, APMG_PS_CTRL_REG,
1309                                 APMG_PS_CTRL_VAL_RESET_REQ);
1310                 udelay(5);
1311                 iwl3945_clear_bits_prph(priv, APMG_PS_CTRL_REG,
1312                                 APMG_PS_CTRL_VAL_RESET_REQ);
1313                 iwl3945_release_nic_access(priv);
1314         }
1315
1316         /* Clear the 'host command active' bit... */
1317         clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1318
1319         wake_up_interruptible(&priv->wait_command_queue);
1320         spin_unlock_irqrestore(&priv->lock, flags);
1321
1322         return rc;
1323 }
1324
1325 /**
1326  * iwl3945_hw_reg_adjust_power_by_temp
1327  * return index delta into power gain settings table
1328 */
1329 static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
1330 {
1331         return (new_reading - old_reading) * (-11) / 100;
1332 }
1333
1334 /**
1335  * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
1336  */
1337 static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
1338 {
1339         return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
1340 }
1341
1342 int iwl3945_hw_get_temperature(struct iwl3945_priv *priv)
1343 {
1344         return iwl3945_read32(priv, CSR_UCODE_DRV_GP2);
1345 }
1346
1347 /**
1348  * iwl3945_hw_reg_txpower_get_temperature
1349  * get the current temperature by reading from NIC
1350 */
1351 static int iwl3945_hw_reg_txpower_get_temperature(struct iwl3945_priv *priv)
1352 {
1353         int temperature;
1354
1355         temperature = iwl3945_hw_get_temperature(priv);
1356
1357         /* driver's okay range is -260 to +25.
1358          *   human readable okay range is 0 to +285 */
1359         IWL_DEBUG_INFO("Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
1360
1361         /* handle insane temp reading */
1362         if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
1363                 IWL_ERROR("Error bad temperature value  %d\n", temperature);
1364
1365                 /* if really really hot(?),
1366                  *   substitute the 3rd band/group's temp measured at factory */
1367                 if (priv->last_temperature > 100)
1368                         temperature = priv->eeprom.groups[2].temperature;
1369                 else /* else use most recent "sane" value from driver */
1370                         temperature = priv->last_temperature;
1371         }
1372
1373         return temperature;     /* raw, not "human readable" */
1374 }
1375
1376 /* Adjust Txpower only if temperature variance is greater than threshold.
1377  *
1378  * Both are lower than older versions' 9 degrees */
1379 #define IWL_TEMPERATURE_LIMIT_TIMER   6
1380
1381 /**
1382  * is_temp_calib_needed - determines if new calibration is needed
1383  *
1384  * records new temperature in tx_mgr->temperature.
1385  * replaces tx_mgr->last_temperature *only* if calib needed
1386  *    (assumes caller will actually do the calibration!). */
1387 static int is_temp_calib_needed(struct iwl3945_priv *priv)
1388 {
1389         int temp_diff;
1390
1391         priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
1392         temp_diff = priv->temperature - priv->last_temperature;
1393
1394         /* get absolute value */
1395         if (temp_diff < 0) {
1396                 IWL_DEBUG_POWER("Getting cooler, delta %d,\n", temp_diff);
1397                 temp_diff = -temp_diff;
1398         } else if (temp_diff == 0)
1399                 IWL_DEBUG_POWER("Same temp,\n");
1400         else
1401                 IWL_DEBUG_POWER("Getting warmer, delta %d,\n", temp_diff);
1402
1403         /* if we don't need calibration, *don't* update last_temperature */
1404         if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
1405                 IWL_DEBUG_POWER("Timed thermal calib not needed\n");
1406                 return 0;
1407         }
1408
1409         IWL_DEBUG_POWER("Timed thermal calib needed\n");
1410
1411         /* assume that caller will actually do calib ...
1412          *   update the "last temperature" value */
1413         priv->last_temperature = priv->temperature;
1414         return 1;
1415 }
1416
1417 #define IWL_MAX_GAIN_ENTRIES 78
1418 #define IWL_CCK_FROM_OFDM_POWER_DIFF  -5
1419 #define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1420
1421 /* radio and DSP power table, each step is 1/2 dB.
1422  * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
1423 static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
1424         {
1425          {251, 127},            /* 2.4 GHz, highest power */
1426          {251, 127},
1427          {251, 127},
1428          {251, 127},
1429          {251, 125},
1430          {251, 110},
1431          {251, 105},
1432          {251, 98},
1433          {187, 125},
1434          {187, 115},
1435          {187, 108},
1436          {187, 99},
1437          {243, 119},
1438          {243, 111},
1439          {243, 105},
1440          {243, 97},
1441          {243, 92},
1442          {211, 106},
1443          {211, 100},
1444          {179, 120},
1445          {179, 113},
1446          {179, 107},
1447          {147, 125},
1448          {147, 119},
1449          {147, 112},
1450          {147, 106},
1451          {147, 101},
1452          {147, 97},
1453          {147, 91},
1454          {115, 107},
1455          {235, 121},
1456          {235, 115},
1457          {235, 109},
1458          {203, 127},
1459          {203, 121},
1460          {203, 115},
1461          {203, 108},
1462          {203, 102},
1463          {203, 96},
1464          {203, 92},
1465          {171, 110},
1466          {171, 104},
1467          {171, 98},
1468          {139, 116},
1469          {227, 125},
1470          {227, 119},
1471          {227, 113},
1472          {227, 107},
1473          {227, 101},
1474          {227, 96},
1475          {195, 113},
1476          {195, 106},
1477          {195, 102},
1478          {195, 95},
1479          {163, 113},
1480          {163, 106},
1481          {163, 102},
1482          {163, 95},
1483          {131, 113},
1484          {131, 106},
1485          {131, 102},
1486          {131, 95},
1487          {99, 113},
1488          {99, 106},
1489          {99, 102},
1490          {99, 95},
1491          {67, 113},
1492          {67, 106},
1493          {67, 102},
1494          {67, 95},
1495          {35, 113},
1496          {35, 106},
1497          {35, 102},
1498          {35, 95},
1499          {3, 113},
1500          {3, 106},
1501          {3, 102},
1502          {3, 95} },             /* 2.4 GHz, lowest power */
1503         {
1504          {251, 127},            /* 5.x GHz, highest power */
1505          {251, 120},
1506          {251, 114},
1507          {219, 119},
1508          {219, 101},
1509          {187, 113},
1510          {187, 102},
1511          {155, 114},
1512          {155, 103},
1513          {123, 117},
1514          {123, 107},
1515          {123, 99},
1516          {123, 92},
1517          {91, 108},
1518          {59, 125},
1519          {59, 118},
1520          {59, 109},
1521          {59, 102},
1522          {59, 96},
1523          {59, 90},
1524          {27, 104},
1525          {27, 98},
1526          {27, 92},
1527          {115, 118},
1528          {115, 111},
1529          {115, 104},
1530          {83, 126},
1531          {83, 121},
1532          {83, 113},
1533          {83, 105},
1534          {83, 99},
1535          {51, 118},
1536          {51, 111},
1537          {51, 104},
1538          {51, 98},
1539          {19, 116},
1540          {19, 109},
1541          {19, 102},
1542          {19, 98},
1543          {19, 93},
1544          {171, 113},
1545          {171, 107},
1546          {171, 99},
1547          {139, 120},
1548          {139, 113},
1549          {139, 107},
1550          {139, 99},
1551          {107, 120},
1552          {107, 113},
1553          {107, 107},
1554          {107, 99},
1555          {75, 120},
1556          {75, 113},
1557          {75, 107},
1558          {75, 99},
1559          {43, 120},
1560          {43, 113},
1561          {43, 107},
1562          {43, 99},
1563          {11, 120},
1564          {11, 113},
1565          {11, 107},
1566          {11, 99},
1567          {131, 107},
1568          {131, 99},
1569          {99, 120},
1570          {99, 113},
1571          {99, 107},
1572          {99, 99},
1573          {67, 120},
1574          {67, 113},
1575          {67, 107},
1576          {67, 99},
1577          {35, 120},
1578          {35, 113},
1579          {35, 107},
1580          {35, 99},
1581          {3, 120} }             /* 5.x GHz, lowest power */
1582 };
1583
1584 static inline u8 iwl3945_hw_reg_fix_power_index(int index)
1585 {
1586         if (index < 0)
1587                 return 0;
1588         if (index >= IWL_MAX_GAIN_ENTRIES)
1589                 return IWL_MAX_GAIN_ENTRIES - 1;
1590         return (u8) index;
1591 }
1592
1593 /* Kick off thermal recalibration check every 60 seconds */
1594 #define REG_RECALIB_PERIOD (60)
1595
1596 /**
1597  * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
1598  *
1599  * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1600  * or 6 Mbit (OFDM) rates.
1601  */
1602 static void iwl3945_hw_reg_set_scan_power(struct iwl3945_priv *priv, u32 scan_tbl_index,
1603                                s32 rate_index, const s8 *clip_pwrs,
1604                                struct iwl3945_channel_info *ch_info,
1605                                int band_index)
1606 {
1607         struct iwl3945_scan_power_info *scan_power_info;
1608         s8 power;
1609         u8 power_index;
1610
1611         scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1612
1613         /* use this channel group's 6Mbit clipping/saturation pwr,
1614          *   but cap at regulatory scan power restriction (set during init
1615          *   based on eeprom channel data) for this channel.  */
1616         power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
1617
1618         /* further limit to user's max power preference.
1619          * FIXME:  Other spectrum management power limitations do not
1620          *   seem to apply?? */
1621         power = min(power, priv->user_txpower_limit);
1622         scan_power_info->requested_power = power;
1623
1624         /* find difference between new scan *power* and current "normal"
1625          *   Tx *power* for 6Mb.  Use this difference (x2) to adjust the
1626          *   current "normal" temperature-compensated Tx power *index* for
1627          *   this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1628          *   *index*. */
1629         power_index = ch_info->power_info[rate_index].power_table_index
1630             - (power - ch_info->power_info
1631                [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
1632
1633         /* store reference index that we use when adjusting *all* scan
1634          *   powers.  So we can accommodate user (all channel) or spectrum
1635          *   management (single channel) power changes "between" temperature
1636          *   feedback compensation procedures.
1637          * don't force fit this reference index into gain table; it may be a
1638          *   negative number.  This will help avoid errors when we're at
1639          *   the lower bounds (highest gains, for warmest temperatures)
1640          *   of the table. */
1641
1642         /* don't exceed table bounds for "real" setting */
1643         power_index = iwl3945_hw_reg_fix_power_index(power_index);
1644
1645         scan_power_info->power_table_index = power_index;
1646         scan_power_info->tpc.tx_gain =
1647             power_gain_table[band_index][power_index].tx_gain;
1648         scan_power_info->tpc.dsp_atten =
1649             power_gain_table[band_index][power_index].dsp_atten;
1650 }
1651
1652 /**
1653  * iwl3945_hw_reg_send_txpower - fill in Tx Power command with gain settings
1654  *
1655  * Configures power settings for all rates for the current channel,
1656  * using values from channel info struct, and send to NIC
1657  */
1658 int iwl3945_hw_reg_send_txpower(struct iwl3945_priv *priv)
1659 {
1660         int rate_idx, i;
1661         const struct iwl3945_channel_info *ch_info = NULL;
1662         struct iwl3945_txpowertable_cmd txpower = {
1663                 .channel = priv->active_rxon.channel,
1664         };
1665
1666         txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
1667         ch_info = iwl3945_get_channel_info(priv,
1668                                        priv->band,
1669                                        le16_to_cpu(priv->active_rxon.channel));
1670         if (!ch_info) {
1671                 IWL_ERROR
1672                     ("Failed to get channel info for channel %d [%d]\n",
1673                      le16_to_cpu(priv->active_rxon.channel), priv->band);
1674                 return -EINVAL;
1675         }
1676
1677         if (!is_channel_valid(ch_info)) {
1678                 IWL_DEBUG_POWER("Not calling TX_PWR_TABLE_CMD on "
1679                                 "non-Tx channel.\n");
1680                 return 0;
1681         }
1682
1683         /* fill cmd with power settings for all rates for current channel */
1684         /* Fill OFDM rate */
1685         for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
1686              rate_idx <= IWL_LAST_OFDM_RATE; rate_idx++, i++) {
1687
1688                 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1689                 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1690
1691                 IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1692                                 le16_to_cpu(txpower.channel),
1693                                 txpower.band,
1694                                 txpower.power[i].tpc.tx_gain,
1695                                 txpower.power[i].tpc.dsp_atten,
1696                                 txpower.power[i].rate);
1697         }
1698         /* Fill CCK rates */
1699         for (rate_idx = IWL_FIRST_CCK_RATE;
1700              rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1701                 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1702                 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1703
1704                 IWL_DEBUG_POWER("ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1705                                 le16_to_cpu(txpower.channel),
1706                                 txpower.band,
1707                                 txpower.power[i].tpc.tx_gain,
1708                                 txpower.power[i].tpc.dsp_atten,
1709                                 txpower.power[i].rate);
1710         }
1711
1712         return iwl3945_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1713                         sizeof(struct iwl3945_txpowertable_cmd), &txpower);
1714
1715 }
1716
1717 /**
1718  * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
1719  * @ch_info: Channel to update.  Uses power_info.requested_power.
1720  *
1721  * Replace requested_power and base_power_index ch_info fields for
1722  * one channel.
1723  *
1724  * Called if user or spectrum management changes power preferences.
1725  * Takes into account h/w and modulation limitations (clip power).
1726  *
1727  * This does *not* send anything to NIC, just sets up ch_info for one channel.
1728  *
1729  * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1730  *       properly fill out the scan powers, and actual h/w gain settings,
1731  *       and send changes to NIC
1732  */
1733 static int iwl3945_hw_reg_set_new_power(struct iwl3945_priv *priv,
1734                              struct iwl3945_channel_info *ch_info)
1735 {
1736         struct iwl3945_channel_power_info *power_info;
1737         int power_changed = 0;
1738         int i;
1739         const s8 *clip_pwrs;
1740         int power;
1741
1742         /* Get this chnlgrp's rate-to-max/clip-powers table */
1743         clip_pwrs = priv->clip_groups[ch_info->group_index].clip_powers;
1744
1745         /* Get this channel's rate-to-current-power settings table */
1746         power_info = ch_info->power_info;
1747
1748         /* update OFDM Txpower settings */
1749         for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
1750              i++, ++power_info) {
1751                 int delta_idx;
1752
1753                 /* limit new power to be no more than h/w capability */
1754                 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1755                 if (power == power_info->requested_power)
1756                         continue;
1757
1758                 /* find difference between old and new requested powers,
1759                  *    update base (non-temp-compensated) power index */
1760                 delta_idx = (power - power_info->requested_power) * 2;
1761                 power_info->base_power_index -= delta_idx;
1762
1763                 /* save new requested power value */
1764                 power_info->requested_power = power;
1765
1766                 power_changed = 1;
1767         }
1768
1769         /* update CCK Txpower settings, based on OFDM 12M setting ...
1770          *    ... all CCK power settings for a given channel are the *same*. */
1771         if (power_changed) {
1772                 power =
1773                     ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1774                     requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1775
1776                 /* do all CCK rates' iwl3945_channel_power_info structures */
1777                 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
1778                         power_info->requested_power = power;
1779                         power_info->base_power_index =
1780                             ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1781                             base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1782                         ++power_info;
1783                 }
1784         }
1785
1786         return 0;
1787 }
1788
1789 /**
1790  * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
1791  *
1792  * NOTE: Returned power limit may be less (but not more) than requested,
1793  *       based strictly on regulatory (eeprom and spectrum mgt) limitations
1794  *       (no consideration for h/w clipping limitations).
1795  */
1796 static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl3945_channel_info *ch_info)
1797 {
1798         s8 max_power;
1799
1800 #if 0
1801         /* if we're using TGd limits, use lower of TGd or EEPROM */
1802         if (ch_info->tgd_data.max_power != 0)
1803                 max_power = min(ch_info->tgd_data.max_power,
1804                                 ch_info->eeprom.max_power_avg);
1805
1806         /* else just use EEPROM limits */
1807         else
1808 #endif
1809                 max_power = ch_info->eeprom.max_power_avg;
1810
1811         return min(max_power, ch_info->max_power_avg);
1812 }
1813
1814 /**
1815  * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
1816  *
1817  * Compensate txpower settings of *all* channels for temperature.
1818  * This only accounts for the difference between current temperature
1819  *   and the factory calibration temperatures, and bases the new settings
1820  *   on the channel's base_power_index.
1821  *
1822  * If RxOn is "associated", this sends the new Txpower to NIC!
1823  */
1824 static int iwl3945_hw_reg_comp_txpower_temp(struct iwl3945_priv *priv)
1825 {
1826         struct iwl3945_channel_info *ch_info = NULL;
1827         int delta_index;
1828         const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1829         u8 a_band;
1830         u8 rate_index;
1831         u8 scan_tbl_index;
1832         u8 i;
1833         int ref_temp;
1834         int temperature = priv->temperature;
1835
1836         /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1837         for (i = 0; i < priv->channel_count; i++) {
1838                 ch_info = &priv->channel_info[i];
1839                 a_band = is_channel_a_band(ch_info);
1840
1841                 /* Get this chnlgrp's factory calibration temperature */
1842                 ref_temp = (s16)priv->eeprom.groups[ch_info->group_index].
1843                     temperature;
1844
1845                 /* get power index adjustment based on curr and factory
1846                  * temps */
1847                 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
1848                                                               ref_temp);
1849
1850                 /* set tx power value for all rates, OFDM and CCK */
1851                 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1852                      rate_index++) {
1853                         int power_idx =
1854                             ch_info->power_info[rate_index].base_power_index;
1855
1856                         /* temperature compensate */
1857                         power_idx += delta_index;
1858
1859                         /* stay within table range */
1860                         power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
1861                         ch_info->power_info[rate_index].
1862                             power_table_index = (u8) power_idx;
1863                         ch_info->power_info[rate_index].tpc =
1864                             power_gain_table[a_band][power_idx];
1865                 }
1866
1867                 /* Get this chnlgrp's rate-to-max/clip-powers table */
1868                 clip_pwrs = priv->clip_groups[ch_info->group_index].clip_powers;
1869
1870                 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1871                 for (scan_tbl_index = 0;
1872                      scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1873                         s32 actual_index = (scan_tbl_index == 0) ?
1874                             IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
1875                         iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
1876                                            actual_index, clip_pwrs,
1877                                            ch_info, a_band);
1878                 }
1879         }
1880
1881         /* send Txpower command for current channel to ucode */
1882         return iwl3945_hw_reg_send_txpower(priv);
1883 }
1884
1885 int iwl3945_hw_reg_set_txpower(struct iwl3945_priv *priv, s8 power)
1886 {
1887         struct iwl3945_channel_info *ch_info;
1888         s8 max_power;
1889         u8 a_band;
1890         u8 i;
1891
1892         if (priv->user_txpower_limit == power) {
1893                 IWL_DEBUG_POWER("Requested Tx power same as current "
1894                                 "limit: %ddBm.\n", power);
1895                 return 0;
1896         }
1897
1898         IWL_DEBUG_POWER("Setting upper limit clamp to %ddBm.\n", power);
1899         priv->user_txpower_limit = power;
1900
1901         /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1902
1903         for (i = 0; i < priv->channel_count; i++) {
1904                 ch_info = &priv->channel_info[i];
1905                 a_band = is_channel_a_band(ch_info);
1906
1907                 /* find minimum power of all user and regulatory constraints
1908                  *    (does not consider h/w clipping limitations) */
1909                 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
1910                 max_power = min(power, max_power);
1911                 if (max_power != ch_info->curr_txpow) {
1912                         ch_info->curr_txpow = max_power;
1913
1914                         /* this considers the h/w clipping limitations */
1915                         iwl3945_hw_reg_set_new_power(priv, ch_info);
1916                 }
1917         }
1918
1919         /* update txpower settings for all channels,
1920          *   send to NIC if associated. */
1921         is_temp_calib_needed(priv);
1922         iwl3945_hw_reg_comp_txpower_temp(priv);
1923
1924         return 0;
1925 }
1926
1927 /* will add 3945 channel switch cmd handling later */
1928 int iwl3945_hw_channel_switch(struct iwl3945_priv *priv, u16 channel)
1929 {
1930         return 0;
1931 }
1932
1933 /**
1934  * iwl3945_reg_txpower_periodic -  called when time to check our temperature.
1935  *
1936  * -- reset periodic timer
1937  * -- see if temp has changed enough to warrant re-calibration ... if so:
1938  *     -- correct coeffs for temp (can reset temp timer)
1939  *     -- save this temp as "last",
1940  *     -- send new set of gain settings to NIC
1941  * NOTE:  This should continue working, even when we're not associated,
1942  *   so we can keep our internal table of scan powers current. */
1943 void iwl3945_reg_txpower_periodic(struct iwl3945_priv *priv)
1944 {
1945         /* This will kick in the "brute force"
1946          * iwl3945_hw_reg_comp_txpower_temp() below */
1947         if (!is_temp_calib_needed(priv))
1948                 goto reschedule;
1949
1950         /* Set up a new set of temp-adjusted TxPowers, send to NIC.
1951          * This is based *only* on current temperature,
1952          * ignoring any previous power measurements */
1953         iwl3945_hw_reg_comp_txpower_temp(priv);
1954
1955  reschedule:
1956         queue_delayed_work(priv->workqueue,
1957                            &priv->thermal_periodic, REG_RECALIB_PERIOD * HZ);
1958 }
1959
1960 static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
1961 {
1962         struct iwl3945_priv *priv = container_of(work, struct iwl3945_priv,
1963                                              thermal_periodic.work);
1964
1965         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
1966                 return;
1967
1968         mutex_lock(&priv->mutex);
1969         iwl3945_reg_txpower_periodic(priv);
1970         mutex_unlock(&priv->mutex);
1971 }
1972
1973 /**
1974  * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
1975  *                                 for the channel.
1976  *
1977  * This function is used when initializing channel-info structs.
1978  *
1979  * NOTE: These channel groups do *NOT* match the bands above!
1980  *       These channel groups are based on factory-tested channels;
1981  *       on A-band, EEPROM's "group frequency" entries represent the top
1982  *       channel in each group 1-4.  Group 5 All B/G channels are in group 0.
1983  */
1984 static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl3945_priv *priv,
1985                                        const struct iwl3945_channel_info *ch_info)
1986 {
1987         struct iwl3945_eeprom_txpower_group *ch_grp = &priv->eeprom.groups[0];
1988         u8 group;
1989         u16 group_index = 0;    /* based on factory calib frequencies */
1990         u8 grp_channel;
1991
1992         /* Find the group index for the channel ... don't use index 1(?) */
1993         if (is_channel_a_band(ch_info)) {
1994                 for (group = 1; group < 5; group++) {
1995                         grp_channel = ch_grp[group].group_channel;
1996                         if (ch_info->channel <= grp_channel) {
1997                                 group_index = group;
1998                                 break;
1999                         }
2000                 }
2001                 /* group 4 has a few channels *above* its factory cal freq */
2002                 if (group == 5)
2003                         group_index = 4;
2004         } else
2005                 group_index = 0;        /* 2.4 GHz, group 0 */
2006
2007         IWL_DEBUG_POWER("Chnl %d mapped to grp %d\n", ch_info->channel,
2008                         group_index);
2009         return group_index;
2010 }
2011
2012 /**
2013  * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
2014  *
2015  * Interpolate to get nominal (i.e. at factory calibration temperature) index
2016  *   into radio/DSP gain settings table for requested power.
2017  */
2018 static int iwl3945_hw_reg_get_matched_power_index(struct iwl3945_priv *priv,
2019                                        s8 requested_power,
2020                                        s32 setting_index, s32 *new_index)
2021 {
2022         const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
2023         s32 index0, index1;
2024         s32 power = 2 * requested_power;
2025         s32 i;
2026         const struct iwl3945_eeprom_txpower_sample *samples;
2027         s32 gains0, gains1;
2028         s32 res;
2029         s32 denominator;
2030
2031         chnl_grp = &priv->eeprom.groups[setting_index];
2032         samples = chnl_grp->samples;
2033         for (i = 0; i < 5; i++) {
2034                 if (power == samples[i].power) {
2035                         *new_index = samples[i].gain_index;
2036                         return 0;
2037                 }
2038         }
2039
2040         if (power > samples[1].power) {
2041                 index0 = 0;
2042                 index1 = 1;
2043         } else if (power > samples[2].power) {
2044                 index0 = 1;
2045                 index1 = 2;
2046         } else if (power > samples[3].power) {
2047                 index0 = 2;
2048                 index1 = 3;
2049         } else {
2050                 index0 = 3;
2051                 index1 = 4;
2052         }
2053
2054         denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2055         if (denominator == 0)
2056                 return -EINVAL;
2057         gains0 = (s32) samples[index0].gain_index * (1 << 19);
2058         gains1 = (s32) samples[index1].gain_index * (1 << 19);
2059         res = gains0 + (gains1 - gains0) *
2060             ((s32) power - (s32) samples[index0].power) / denominator +
2061             (1 << 18);
2062         *new_index = res >> 19;
2063         return 0;
2064 }
2065
2066 static void iwl3945_hw_reg_init_channel_groups(struct iwl3945_priv *priv)
2067 {
2068         u32 i;
2069         s32 rate_index;
2070         const struct iwl3945_eeprom_txpower_group *group;
2071
2072         IWL_DEBUG_POWER("Initializing factory calib info from EEPROM\n");
2073
2074         for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2075                 s8 *clip_pwrs;  /* table of power levels for each rate */
2076                 s8 satur_pwr;   /* saturation power for each chnl group */
2077                 group = &priv->eeprom.groups[i];
2078
2079                 /* sanity check on factory saturation power value */
2080                 if (group->saturation_power < 40) {
2081                         IWL_WARNING("Error: saturation power is %d, "
2082                                     "less than minimum expected 40\n",
2083                                     group->saturation_power);
2084                         return;
2085                 }
2086
2087                 /*
2088                  * Derive requested power levels for each rate, based on
2089                  *   hardware capabilities (saturation power for band).
2090                  * Basic value is 3dB down from saturation, with further
2091                  *   power reductions for highest 3 data rates.  These
2092                  *   backoffs provide headroom for high rate modulation
2093                  *   power peaks, without too much distortion (clipping).
2094                  */
2095                 /* we'll fill in this array with h/w max power levels */
2096                 clip_pwrs = (s8 *) priv->clip_groups[i].clip_powers;
2097
2098                 /* divide factory saturation power by 2 to find -3dB level */
2099                 satur_pwr = (s8) (group->saturation_power >> 1);
2100
2101                 /* fill in channel group's nominal powers for each rate */
2102                 for (rate_index = 0;
2103                      rate_index < IWL_RATE_COUNT; rate_index++, clip_pwrs++) {
2104                         switch (rate_index) {
2105                         case IWL_RATE_36M_INDEX_TABLE:
2106                                 if (i == 0)     /* B/G */
2107                                         *clip_pwrs = satur_pwr;
2108                                 else    /* A */
2109                                         *clip_pwrs = satur_pwr - 5;
2110                                 break;
2111                         case IWL_RATE_48M_INDEX_TABLE:
2112                                 if (i == 0)
2113                                         *clip_pwrs = satur_pwr - 7;
2114                                 else
2115                                         *clip_pwrs = satur_pwr - 10;
2116                                 break;
2117                         case IWL_RATE_54M_INDEX_TABLE:
2118                                 if (i == 0)
2119                                         *clip_pwrs = satur_pwr - 9;
2120                                 else
2121                                         *clip_pwrs = satur_pwr - 12;
2122                                 break;
2123                         default:
2124                                 *clip_pwrs = satur_pwr;
2125                                 break;
2126                         }
2127                 }
2128         }
2129 }
2130
2131 /**
2132  * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2133  *
2134  * Second pass (during init) to set up priv->channel_info
2135  *
2136  * Set up Tx-power settings in our channel info database for each VALID
2137  * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2138  * and current temperature.
2139  *
2140  * Since this is based on current temperature (at init time), these values may
2141  * not be valid for very long, but it gives us a starting/default point,
2142  * and allows us to active (i.e. using Tx) scan.
2143  *
2144  * This does *not* write values to NIC, just sets up our internal table.
2145  */
2146 int iwl3945_txpower_set_from_eeprom(struct iwl3945_priv *priv)
2147 {
2148         struct iwl3945_channel_info *ch_info = NULL;
2149         struct iwl3945_channel_power_info *pwr_info;
2150         int delta_index;
2151         u8 rate_index;
2152         u8 scan_tbl_index;
2153         const s8 *clip_pwrs;    /* array of power levels for each rate */
2154         u8 gain, dsp_atten;
2155         s8 power;
2156         u8 pwr_index, base_pwr_index, a_band;
2157         u8 i;
2158         int temperature;
2159
2160         /* save temperature reference,
2161          *   so we can determine next time to calibrate */
2162         temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
2163         priv->last_temperature = temperature;
2164
2165         iwl3945_hw_reg_init_channel_groups(priv);
2166
2167         /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2168         for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2169              i++, ch_info++) {
2170                 a_band = is_channel_a_band(ch_info);
2171                 if (!is_channel_valid(ch_info))
2172                         continue;
2173
2174                 /* find this channel's channel group (*not* "band") index */
2175                 ch_info->group_index =
2176                         iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
2177
2178                 /* Get this chnlgrp's rate->max/clip-powers table */
2179                 clip_pwrs = priv->clip_groups[ch_info->group_index].clip_powers;
2180
2181                 /* calculate power index *adjustment* value according to
2182                  *  diff between current temperature and factory temperature */
2183                 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
2184                                 priv->eeprom.groups[ch_info->group_index].
2185                                 temperature);
2186
2187                 IWL_DEBUG_POWER("Delta index for channel %d: %d [%d]\n",
2188                                 ch_info->channel, delta_index, temperature +
2189                                 IWL_TEMP_CONVERT);
2190
2191                 /* set tx power value for all OFDM rates */
2192                 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2193                      rate_index++) {
2194                         s32 power_idx;
2195                         int rc;
2196
2197                         /* use channel group's clip-power table,
2198                          *   but don't exceed channel's max power */
2199                         s8 pwr = min(ch_info->max_power_avg,
2200                                      clip_pwrs[rate_index]);
2201
2202                         pwr_info = &ch_info->power_info[rate_index];
2203
2204                         /* get base (i.e. at factory-measured temperature)
2205                          *    power table index for this rate's power */
2206                         rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
2207                                                          ch_info->group_index,
2208                                                          &power_idx);
2209                         if (rc) {
2210                                 IWL_ERROR("Invalid power index\n");
2211                                 return rc;
2212                         }
2213                         pwr_info->base_power_index = (u8) power_idx;
2214
2215                         /* temperature compensate */
2216                         power_idx += delta_index;
2217
2218                         /* stay within range of gain table */
2219                         power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
2220
2221                         /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
2222                         pwr_info->requested_power = pwr;
2223                         pwr_info->power_table_index = (u8) power_idx;
2224                         pwr_info->tpc.tx_gain =
2225                             power_gain_table[a_band][power_idx].tx_gain;
2226                         pwr_info->tpc.dsp_atten =
2227                             power_gain_table[a_band][power_idx].dsp_atten;
2228                 }
2229
2230                 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
2231                 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
2232                 power = pwr_info->requested_power +
2233                         IWL_CCK_FROM_OFDM_POWER_DIFF;
2234                 pwr_index = pwr_info->power_table_index +
2235                         IWL_CCK_FROM_OFDM_INDEX_DIFF;
2236                 base_pwr_index = pwr_info->base_power_index +
2237                         IWL_CCK_FROM_OFDM_INDEX_DIFF;
2238
2239                 /* stay within table range */
2240                 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
2241                 gain = power_gain_table[a_band][pwr_index].tx_gain;
2242                 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2243
2244                 /* fill each CCK rate's iwl3945_channel_power_info structure
2245                  * NOTE:  All CCK-rate Txpwrs are the same for a given chnl!
2246                  * NOTE:  CCK rates start at end of OFDM rates! */
2247                 for (rate_index = 0;
2248                      rate_index < IWL_CCK_RATES; rate_index++) {
2249                         pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
2250                         pwr_info->requested_power = power;
2251                         pwr_info->power_table_index = pwr_index;
2252                         pwr_info->base_power_index = base_pwr_index;
2253                         pwr_info->tpc.tx_gain = gain;
2254                         pwr_info->tpc.dsp_atten = dsp_atten;
2255                 }
2256
2257                 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2258                 for (scan_tbl_index = 0;
2259                      scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2260                         s32 actual_index = (scan_tbl_index == 0) ?
2261                                 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
2262                         iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
2263                                 actual_index, clip_pwrs, ch_info, a_band);
2264                 }
2265         }
2266
2267         return 0;
2268 }
2269
2270 int iwl3945_hw_rxq_stop(struct iwl3945_priv *priv)
2271 {
2272         int rc;
2273         unsigned long flags;
2274
2275         spin_lock_irqsave(&priv->lock, flags);
2276         rc = iwl3945_grab_nic_access(priv);
2277         if (rc) {
2278                 spin_unlock_irqrestore(&priv->lock, flags);
2279                 return rc;
2280         }
2281
2282         iwl3945_write_direct32(priv, FH_RCSR_CONFIG(0), 0);
2283         rc = iwl3945_poll_direct_bit(priv, FH_RSSR_STATUS, (1 << 24), 1000);
2284         if (rc < 0)
2285                 IWL_ERROR("Can't stop Rx DMA.\n");
2286
2287         iwl3945_release_nic_access(priv);
2288         spin_unlock_irqrestore(&priv->lock, flags);
2289
2290         return 0;
2291 }
2292
2293 int iwl3945_hw_tx_queue_init(struct iwl3945_priv *priv, struct iwl3945_tx_queue *txq)
2294 {
2295         int rc;
2296         unsigned long flags;
2297         int txq_id = txq->q.id;
2298
2299         struct iwl3945_shared *shared_data = priv->hw_setting.shared_virt;
2300
2301         shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2302
2303         spin_lock_irqsave(&priv->lock, flags);
2304         rc = iwl3945_grab_nic_access(priv);
2305         if (rc) {
2306                 spin_unlock_irqrestore(&priv->lock, flags);
2307                 return rc;
2308         }
2309         iwl3945_write_direct32(priv, FH_CBCC_CTRL(txq_id), 0);
2310         iwl3945_write_direct32(priv, FH_CBCC_BASE(txq_id), 0);
2311
2312         iwl3945_write_direct32(priv, FH_TCSR_CONFIG(txq_id),
2313                 ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2314                 ALM_FH_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2315                 ALM_FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2316                 ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2317                 ALM_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
2318         iwl3945_release_nic_access(priv);
2319
2320         /* fake read to flush all prev. writes */
2321         iwl3945_read32(priv, FH_TSSR_CBB_BASE);
2322         spin_unlock_irqrestore(&priv->lock, flags);
2323
2324         return 0;
2325 }
2326
2327 int iwl3945_hw_get_rx_read(struct iwl3945_priv *priv)
2328 {
2329         struct iwl3945_shared *shared_data = priv->hw_setting.shared_virt;
2330
2331         return le32_to_cpu(shared_data->rx_read_ptr[0]);
2332 }
2333
2334 /**
2335  * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2336  */
2337 int iwl3945_init_hw_rate_table(struct iwl3945_priv *priv)
2338 {
2339         int rc, i, index, prev_index;
2340         struct iwl3945_rate_scaling_cmd rate_cmd = {
2341                 .reserved = {0, 0, 0},
2342         };
2343         struct iwl3945_rate_scaling_info *table = rate_cmd.table;
2344
2345         for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2346                 index = iwl3945_rates[i].table_rs_index;
2347
2348                 table[index].rate_n_flags =
2349                         iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
2350                 table[index].try_cnt = priv->retry_rate;
2351                 prev_index = iwl3945_get_prev_ieee_rate(i);
2352                 table[index].next_rate_index = iwl3945_rates[prev_index].table_rs_index;
2353         }
2354
2355         switch (priv->band) {
2356         case IEEE80211_BAND_5GHZ:
2357                 IWL_DEBUG_RATE("Select A mode rate scale\n");
2358                 /* If one of the following CCK rates is used,
2359                  * have it fall back to the 6M OFDM rate */
2360                 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++)
2361                         table[i].next_rate_index = iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2362
2363                 /* Don't fall back to CCK rates */
2364                 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index = IWL_RATE_9M_INDEX_TABLE;
2365
2366                 /* Don't drop out of OFDM rates */
2367                 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
2368                     iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2369                 break;
2370
2371         case IEEE80211_BAND_2GHZ:
2372                 IWL_DEBUG_RATE("Select B/G mode rate scale\n");
2373                 /* If an OFDM rate is used, have it fall back to the
2374                  * 1M CCK rates */
2375                 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE; i++)
2376                         table[i].next_rate_index = iwl3945_rates[IWL_FIRST_CCK_RATE].table_rs_index;
2377
2378                 /* CCK shouldn't fall back to OFDM... */
2379                 table[IWL_RATE_11M_INDEX_TABLE].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2380                 break;
2381
2382         default:
2383                 WARN_ON(1);
2384                 break;
2385         }
2386
2387         /* Update the rate scaling for control frame Tx */
2388         rate_cmd.table_id = 0;
2389         rc = iwl3945_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2390                               &rate_cmd);
2391         if (rc)
2392                 return rc;
2393
2394         /* Update the rate scaling for data frame Tx */
2395         rate_cmd.table_id = 1;
2396         return iwl3945_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2397                                 &rate_cmd);
2398 }
2399
2400 /* Called when initializing driver */
2401 int iwl3945_hw_set_hw_setting(struct iwl3945_priv *priv)
2402 {
2403         memset((void *)&priv->hw_setting, 0,
2404                sizeof(struct iwl3945_driver_hw_info));
2405
2406         priv->hw_setting.shared_virt =
2407             pci_alloc_consistent(priv->pci_dev,
2408                                  sizeof(struct iwl3945_shared),
2409                                  &priv->hw_setting.shared_phys);
2410
2411         if (!priv->hw_setting.shared_virt) {
2412                 IWL_ERROR("failed to allocate pci memory\n");
2413                 mutex_unlock(&priv->mutex);
2414                 return -ENOMEM;
2415         }
2416
2417         priv->hw_setting.rx_buf_size = IWL_RX_BUF_SIZE;
2418         priv->hw_setting.max_pkt_size = 2342;
2419         priv->hw_setting.tx_cmd_len = sizeof(struct iwl3945_tx_cmd);
2420         priv->hw_setting.max_rxq_size = RX_QUEUE_SIZE;
2421         priv->hw_setting.max_rxq_log = RX_QUEUE_SIZE_LOG;
2422         priv->hw_setting.max_stations = IWL3945_STATION_COUNT;
2423         priv->hw_setting.bcast_sta_id = IWL3945_BROADCAST_ID;
2424
2425         priv->hw_setting.tx_ant_num = 2;
2426         return 0;
2427 }
2428
2429 unsigned int iwl3945_hw_get_beacon_cmd(struct iwl3945_priv *priv,
2430                           struct iwl3945_frame *frame, u8 rate)
2431 {
2432         struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
2433         unsigned int frame_size;
2434
2435         tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
2436         memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2437
2438         tx_beacon_cmd->tx.sta_id = priv->hw_setting.bcast_sta_id;
2439         tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2440
2441         frame_size = iwl3945_fill_beacon_frame(priv,
2442                                 tx_beacon_cmd->frame,
2443                                 iwl3945_broadcast_addr,
2444                                 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2445
2446         BUG_ON(frame_size > MAX_MPDU_SIZE);
2447         tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2448
2449         tx_beacon_cmd->tx.rate = rate;
2450         tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2451                                       TX_CMD_FLG_TSF_MSK);
2452
2453         /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2454         tx_beacon_cmd->tx.supp_rates[0] =
2455                 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2456
2457         tx_beacon_cmd->tx.supp_rates[1] =
2458                 (IWL_CCK_BASIC_RATES_MASK & 0xF);
2459
2460         return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
2461 }
2462
2463 void iwl3945_hw_rx_handler_setup(struct iwl3945_priv *priv)
2464 {
2465         priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
2466         priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2467 }
2468
2469 void iwl3945_hw_setup_deferred_work(struct iwl3945_priv *priv)
2470 {
2471         INIT_DELAYED_WORK(&priv->thermal_periodic,
2472                           iwl3945_bg_reg_txpower_periodic);
2473 }
2474
2475 void iwl3945_hw_cancel_deferred_work(struct iwl3945_priv *priv)
2476 {
2477         cancel_delayed_work(&priv->thermal_periodic);
2478 }
2479
2480 static struct iwl_3945_cfg iwl3945_bg_cfg = {
2481         .name = "3945BG",
2482         .fw_name = "iwlwifi-3945" IWL3945_UCODE_API ".ucode",
2483         .sku = IWL_SKU_G,
2484 };
2485
2486 static struct iwl_3945_cfg iwl3945_abg_cfg = {
2487         .name = "3945ABG",
2488         .fw_name = "iwlwifi-3945" IWL3945_UCODE_API ".ucode",
2489         .sku = IWL_SKU_A|IWL_SKU_G,
2490 };
2491
2492 struct pci_device_id iwl3945_hw_card_ids[] = {
2493         {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2494         {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2495         {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2496         {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2497         {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2498         {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
2499         {0}
2500 };
2501
2502 MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);