SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/iwlwifi/iwl-3945.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  *  Intel Linux Wireless <ilw@linux.intel.com>
  23  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24  *
  25  *****************************************************************************/
  26
  27 #include <linux/kernel.h>
  28 #include <linux/module.h>
  29 #include <linux/init.h>
  30 #include <linux/pci.h>
  31 #include <linux/dma-mapping.h>
  32 #include <linux/delay.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/netdevice.h>
  35 #include <linux/wireless.h>
  36 #include <linux/firmware.h>
  37 #include <linux/etherdevice.h>
  38 #include <asm/unaligned.h>
  39 #include <net/mac80211.h>
  40
  41 #include "iwl-fh.h"
  42 #include "iwl-3945-fh.h"
  43 #include "iwl-commands.h"
  44 #include "iwl-sta.h"
  45 #include "iwl-3945.h"
  46 #include "iwl-eeprom.h"
  47 #include "iwl-helpers.h"
  48 #include "iwl-core.h"
  49 #include "iwl-led.h"
  50 #include "iwl-3945-led.h"
  51
  52 #define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np)    \
  53         [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP,   \
  54                                     IWL_RATE_##r##M_IEEE,   \
  55                                     IWL_RATE_##ip##M_INDEX, \
  56                                     IWL_RATE_##in##M_INDEX, \
  57                                     IWL_RATE_##rp##M_INDEX, \
  58                                     IWL_RATE_##rn##M_INDEX, \
  59                                     IWL_RATE_##pp##M_INDEX, \
  60                                     IWL_RATE_##np##M_INDEX, \
  61                                     IWL_RATE_##r##M_INDEX_TABLE, \
  62                                     IWL_RATE_##ip##M_INDEX_TABLE }
  63
  64 /*
  65  * Parameter order:
  66  *   rate, prev rate, next rate, prev tgg rate, next tgg rate
  67  *
  68  * If there isn't a valid next or previous rate then INV is used which
  69  * maps to IWL_RATE_INVALID
  70  *
  71  */
  72 const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = {
  73         IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2),    /*  1mbps */
  74         IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5),          /*  2mbps */
  75         IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11),        /*5.5mbps */
  76         IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18),      /* 11mbps */
  77         IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11),        /*  6mbps */
  78         IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11),       /*  9mbps */
  79         IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18),   /* 12mbps */
  80         IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24),   /* 18mbps */
  81         IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36),   /* 24mbps */
  82         IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48),   /* 36mbps */
  83         IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54),   /* 48mbps */
  84         IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */
  85 };
  86
  87 /* 1 = enable the iwl3945_disable_events() function */
  88 #define IWL_EVT_DISABLE (0)
  89 #define IWL_EVT_DISABLE_SIZE (1532/32)
  90
  91 /**
  92  * iwl3945_disable_events - Disable selected events in uCode event log
  93  *
  94  * Disable an event by writing "1"s into "disable"
  95  *   bitmap in SRAM.  Bit position corresponds to Event # (id/type).
  96  *   Default values of 0 enable uCode events to be logged.
  97  * Use for only special debugging.  This function is just a placeholder as-is,
  98  *   you'll need to provide the special bits! ...
  99  *   ... and set IWL_EVT_DISABLE to 1. */
 100 void iwl3945_disable_events(struct iwl_priv *priv)
 101 {
 102         int i;
 103         u32 base;               /* SRAM address of event log header */
 104         u32 disable_ptr;        /* SRAM address of event-disable bitmap array */
 105         u32 array_size;         /* # of u32 entries in array */
 106         u32 evt_disable[IWL_EVT_DISABLE_SIZE] = {
 107                 0x00000000,     /*   31 -    0  Event id numbers */
 108                 0x00000000,     /*   63 -   32 */
 109                 0x00000000,     /*   95 -   64 */
 110                 0x00000000,     /*  127 -   96 */
 111                 0x00000000,     /*  159 -  128 */
 112                 0x00000000,     /*  191 -  160 */
 113                 0x00000000,     /*  223 -  192 */
 114                 0x00000000,     /*  255 -  224 */
 115                 0x00000000,     /*  287 -  256 */
 116                 0x00000000,     /*  319 -  288 */
 117                 0x00000000,     /*  351 -  320 */
 118                 0x00000000,     /*  383 -  352 */
 119                 0x00000000,     /*  415 -  384 */
 120                 0x00000000,     /*  447 -  416 */
 121                 0x00000000,     /*  479 -  448 */
 122                 0x00000000,     /*  511 -  480 */
 123                 0x00000000,     /*  543 -  512 */
 124                 0x00000000,     /*  575 -  544 */
 125                 0x00000000,     /*  607 -  576 */
 126                 0x00000000,     /*  639 -  608 */
 127                 0x00000000,     /*  671 -  640 */
 128                 0x00000000,     /*  703 -  672 */
 129                 0x00000000,     /*  735 -  704 */
 130                 0x00000000,     /*  767 -  736 */
 131                 0x00000000,     /*  799 -  768 */
 132                 0x00000000,     /*  831 -  800 */
 133                 0x00000000,     /*  863 -  832 */
 134                 0x00000000,     /*  895 -  864 */
 135                 0x00000000,     /*  927 -  896 */
 136                 0x00000000,     /*  959 -  928 */
 137                 0x00000000,     /*  991 -  960 */
 138                 0x00000000,     /* 1023 -  992 */
 139                 0x00000000,     /* 1055 - 1024 */
 140                 0x00000000,     /* 1087 - 1056 */
 141                 0x00000000,     /* 1119 - 1088 */
 142                 0x00000000,     /* 1151 - 1120 */
 143                 0x00000000,     /* 1183 - 1152 */
 144                 0x00000000,     /* 1215 - 1184 */
 145                 0x00000000,     /* 1247 - 1216 */
 146                 0x00000000,     /* 1279 - 1248 */
 147                 0x00000000,     /* 1311 - 1280 */
 148                 0x00000000,     /* 1343 - 1312 */
 149                 0x00000000,     /* 1375 - 1344 */
 150                 0x00000000,     /* 1407 - 1376 */
 151                 0x00000000,     /* 1439 - 1408 */
 152                 0x00000000,     /* 1471 - 1440 */
 153                 0x00000000,     /* 1503 - 1472 */
 154         };
 155
 156         base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
 157         if (!iwl3945_hw_valid_rtc_data_addr(base)) {
 158                 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
 159                 return;
 160         }
 161
 162         disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32)));
 163         array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32)));
 164
 165         if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) {
 166                 IWL_DEBUG_INFO(priv, "Disabling selected uCode log events at 0x%x\n",
 167                                disable_ptr);
 168                 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++)
 169                         iwl_write_targ_mem(priv,
 170                                            disable_ptr + (i * sizeof(u32)),
 171                                            evt_disable[i]);
 172
 173         } else {
 174                 IWL_DEBUG_INFO(priv, "Selected uCode log events may be disabled\n");
 175                 IWL_DEBUG_INFO(priv, "  by writing \"1\"s into disable bitmap\n");
 176                 IWL_DEBUG_INFO(priv, "  in SRAM at 0x%x, size %d u32s\n",
 177                                disable_ptr, array_size);
 178         }
 179
 180 }
 181
 182 static int iwl3945_hwrate_to_plcp_idx(u8 plcp)
 183 {
 184         int idx;
 185
 186         for (idx = 0; idx < IWL_RATE_COUNT; idx++)
 187                 if (iwl3945_rates[idx].plcp == plcp)
 188                         return idx;
 189         return -1;
 190 }
 191
 192 #ifdef CONFIG_IWLWIFI_DEBUG
 193 #define TX_STATUS_ENTRY(x) case TX_STATUS_FAIL_ ## x: return #x
 194
 195 static const char *iwl3945_get_tx_fail_reason(u32 status)
 196 {
 197         switch (status & TX_STATUS_MSK) {
 198         case TX_STATUS_SUCCESS:
 199                 return "SUCCESS";
 200                 TX_STATUS_ENTRY(SHORT_LIMIT);
 201                 TX_STATUS_ENTRY(LONG_LIMIT);
 202                 TX_STATUS_ENTRY(FIFO_UNDERRUN);
 203                 TX_STATUS_ENTRY(MGMNT_ABORT);
 204                 TX_STATUS_ENTRY(NEXT_FRAG);
 205                 TX_STATUS_ENTRY(LIFE_EXPIRE);
 206                 TX_STATUS_ENTRY(DEST_PS);
 207                 TX_STATUS_ENTRY(ABORTED);
 208                 TX_STATUS_ENTRY(BT_RETRY);
 209                 TX_STATUS_ENTRY(STA_INVALID);
 210                 TX_STATUS_ENTRY(FRAG_DROPPED);
 211                 TX_STATUS_ENTRY(TID_DISABLE);
 212                 TX_STATUS_ENTRY(FRAME_FLUSHED);
 213                 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL);
 214                 TX_STATUS_ENTRY(TX_LOCKED);
 215                 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR);
 216         }
 217
 218         return "UNKNOWN";
 219 }
 220 #else
 221 static inline const char *iwl3945_get_tx_fail_reason(u32 status)
 222 {
 223         return "";
 224 }
 225 #endif
 226
 227 /*
 228  * get ieee prev rate from rate scale table.
 229  * for A and B mode we need to overright prev
 230  * value
 231  */
 232 int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate)
 233 {
 234         int next_rate = iwl3945_get_prev_ieee_rate(rate);
 235
 236         switch (priv->band) {
 237         case IEEE80211_BAND_5GHZ:
 238                 if (rate == IWL_RATE_12M_INDEX)
 239                         next_rate = IWL_RATE_9M_INDEX;
 240                 else if (rate == IWL_RATE_6M_INDEX)
 241                         next_rate = IWL_RATE_6M_INDEX;
 242                 break;
 243         case IEEE80211_BAND_2GHZ:
 244                 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
 245                     iwl_is_associated(priv)) {
 246                         if (rate == IWL_RATE_11M_INDEX)
 247                                 next_rate = IWL_RATE_5M_INDEX;
 248                 }
 249                 break;
 250
 251         default:
 252                 break;
 253         }
 254
 255         return next_rate;
 256 }
 257
 258
 259 /**
 260  * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd
 261  *
 262  * When FW advances 'R' index, all entries between old and new 'R' index
 263  * need to be reclaimed. As result, some free space forms. If there is
 264  * enough free space (> low mark), wake the stack that feeds us.
 265  */
 266 static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv,
 267                                      int txq_id, int index)
 268 {
 269         struct iwl_tx_queue *txq = &priv->txq[txq_id];
 270         struct iwl_queue *q = &txq->q;
 271         struct iwl_tx_info *tx_info;
 272
 273         BUG_ON(txq_id == IWL_CMD_QUEUE_NUM);
 274
 275         for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index;
 276                 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) {
 277
 278                 tx_info = &txq->txb[txq->q.read_ptr];
 279                 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb[0]);
 280                 tx_info->skb[0] = NULL;
 281                 priv->cfg->ops->lib->txq_free_tfd(priv, txq);
 282         }
 283
 284         if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) &&
 285                         (txq_id != IWL_CMD_QUEUE_NUM) &&
 286                         priv->mac80211_registered)
 287                 iwl_wake_queue(priv, txq_id);
 288 }
 289
 290 /**
 291  * iwl3945_rx_reply_tx - Handle Tx response
 292  */
 293 static void iwl3945_rx_reply_tx(struct iwl_priv *priv,
 294                             struct iwl_rx_mem_buffer *rxb)
 295 {
 296         struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
 297         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
 298         int txq_id = SEQ_TO_QUEUE(sequence);
 299         int index = SEQ_TO_INDEX(sequence);
 300         struct iwl_tx_queue *txq = &priv->txq[txq_id];
 301         struct ieee80211_tx_info *info;
 302         struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
 303         u32  status = le32_to_cpu(tx_resp->status);
 304         int rate_idx;
 305         int fail;
 306
 307         if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
 308                 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
 309                           "is out of range [0-%d] %d %d\n", txq_id,
 310                           index, txq->q.n_bd, txq->q.write_ptr,
 311                           txq->q.read_ptr);
 312                 return;
 313         }
 314
 315         info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
 316         ieee80211_tx_info_clear_status(info);
 317
 318         /* Fill the MRR chain with some info about on-chip retransmissions */
 319         rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate);
 320         if (info->band == IEEE80211_BAND_5GHZ)
 321                 rate_idx -= IWL_FIRST_OFDM_RATE;
 322
 323         fail = tx_resp->failure_frame;
 324
 325         info->status.rates[0].idx = rate_idx;
 326         info->status.rates[0].count = fail + 1; /* add final attempt */
 327
 328         /* tx_status->rts_retry_count = tx_resp->failure_rts; */
 329         info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ?
 330                                 IEEE80211_TX_STAT_ACK : 0;
 331
 332         IWL_DEBUG_TX(priv, "Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n",
 333                         txq_id, iwl3945_get_tx_fail_reason(status), status,
 334                         tx_resp->rate, tx_resp->failure_frame);
 335
 336         IWL_DEBUG_TX_REPLY(priv, "Tx queue reclaim %d\n", index);
 337         iwl3945_tx_queue_reclaim(priv, txq_id, index);
 338
 339         if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
 340                 IWL_ERR(priv, "TODO:  Implement Tx ABORT REQUIRED!!!\n");
 341 }
 342
 343
 344
 345 /*****************************************************************************
 346  *
 347  * Intel PRO/Wireless 3945ABG/BG Network Connection
 348  *
 349  *  RX handler implementations
 350  *
 351  *****************************************************************************/
 352
 353 void iwl3945_hw_rx_statistics(struct iwl_priv *priv,
 354                 struct iwl_rx_mem_buffer *rxb)
 355 {
 356         struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
 357         IWL_DEBUG_RX(priv, "Statistics notification received (%d vs %d).\n",
 358                      (int)sizeof(struct iwl3945_notif_statistics),
 359                      le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
 360
 361         memcpy(&priv->statistics_39, pkt->u.raw, sizeof(priv->statistics_39));
 362
 363         iwl_leds_background(priv);
 364
 365         priv->last_statistics_time = jiffies;
 366 }
 367
 368 /******************************************************************************
 369  *
 370  * Misc. internal state and helper functions
 371  *
 372  ******************************************************************************/
 373 #ifdef CONFIG_IWLWIFI_DEBUG
 374
 375 /**
 376  * iwl3945_report_frame - dump frame to syslog during debug sessions
 377  *
 378  * You may hack this function to show different aspects of received frames,
 379  * including selective frame dumps.
 380  * group100 parameter selects whether to show 1 out of 100 good frames.
 381  */
 382 static void _iwl3945_dbg_report_frame(struct iwl_priv *priv,
 383                       struct iwl_rx_packet *pkt,
 384                       struct ieee80211_hdr *header, int group100)
 385 {
 386         u32 to_us;
 387         u32 print_summary = 0;
 388         u32 print_dump = 0;     /* set to 1 to dump all frames' contents */
 389         u32 hundred = 0;
 390         u32 dataframe = 0;
 391         __le16 fc;
 392         u16 seq_ctl;
 393         u16 channel;
 394         u16 phy_flags;
 395         u16 length;
 396         u16 status;
 397         u16 bcn_tmr;
 398         u32 tsf_low;
 399         u64 tsf;
 400         u8 rssi;
 401         u8 agc;
 402         u16 sig_avg;
 403         u16 noise_diff;
 404         struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
 405         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
 406         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
 407         u8 *data = IWL_RX_DATA(pkt);
 408
 409         /* MAC header */
 410         fc = header->frame_control;
 411         seq_ctl = le16_to_cpu(header->seq_ctrl);
 412
 413         /* metadata */
 414         channel = le16_to_cpu(rx_hdr->channel);
 415         phy_flags = le16_to_cpu(rx_hdr->phy_flags);
 416         length = le16_to_cpu(rx_hdr->len);
 417
 418         /* end-of-frame status and timestamp */
 419         status = le32_to_cpu(rx_end->status);
 420         bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
 421         tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
 422         tsf = le64_to_cpu(rx_end->timestamp);
 423
 424         /* signal statistics */
 425         rssi = rx_stats->rssi;
 426         agc = rx_stats->agc;
 427         sig_avg = le16_to_cpu(rx_stats->sig_avg);
 428         noise_diff = le16_to_cpu(rx_stats->noise_diff);
 429
 430         to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
 431
 432         /* if data frame is to us and all is good,
 433          *   (optionally) print summary for only 1 out of every 100 */
 434         if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
 435             cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
 436                 dataframe = 1;
 437                 if (!group100)
 438                         print_summary = 1;      /* print each frame */
 439                 else if (priv->framecnt_to_us < 100) {
 440                         priv->framecnt_to_us++;
 441                         print_summary = 0;
 442                 } else {
 443                         priv->framecnt_to_us = 0;
 444                         print_summary = 1;
 445                         hundred = 1;
 446                 }
 447         } else {
 448                 /* print summary for all other frames */
 449                 print_summary = 1;
 450         }
 451
 452         if (print_summary) {
 453                 char *title;
 454                 int rate;
 455
 456                 if (hundred)
 457                         title = "100Frames";
 458                 else if (ieee80211_has_retry(fc))
 459                         title = "Retry";
 460                 else if (ieee80211_is_assoc_resp(fc))
 461                         title = "AscRsp";
 462                 else if (ieee80211_is_reassoc_resp(fc))
 463                         title = "RasRsp";
 464                 else if (ieee80211_is_probe_resp(fc)) {
 465                         title = "PrbRsp";
 466                         print_dump = 1; /* dump frame contents */
 467                 } else if (ieee80211_is_beacon(fc)) {
 468                         title = "Beacon";
 469                         print_dump = 1; /* dump frame contents */
 470                 } else if (ieee80211_is_atim(fc))
 471                         title = "ATIM";
 472                 else if (ieee80211_is_auth(fc))
 473                         title = "Auth";
 474                 else if (ieee80211_is_deauth(fc))
 475                         title = "DeAuth";
 476                 else if (ieee80211_is_disassoc(fc))
 477                         title = "DisAssoc";
 478                 else
 479                         title = "Frame";
 480
 481                 rate = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
 482                 if (rate == -1)
 483                         rate = 0;
 484                 else
 485                         rate = iwl3945_rates[rate].ieee / 2;
 486
 487                 /* print frame summary.
 488                  * MAC addresses show just the last byte (for brevity),
 489                  *    but you can hack it to show more, if you'd like to. */
 490                 if (dataframe)
 491                         IWL_DEBUG_RX(priv, "%s: mhd=0x%04x, dst=0x%02x, "
 492                                      "len=%u, rssi=%d, chnl=%d, rate=%d, \n",
 493                                      title, le16_to_cpu(fc), header->addr1[5],
 494                                      length, rssi, channel, rate);
 495                 else {
 496                         /* src/dst addresses assume managed mode */
 497                         IWL_DEBUG_RX(priv, "%s: 0x%04x, dst=0x%02x, "
 498                                      "src=0x%02x, rssi=%u, tim=%lu usec, "
 499                                      "phy=0x%02x, chnl=%d\n",
 500                                      title, le16_to_cpu(fc), header->addr1[5],
 501                                      header->addr3[5], rssi,
 502                                      tsf_low - priv->scan_start_tsf,
 503                                      phy_flags, channel);
 504                 }
 505         }
 506         if (print_dump)
 507                 iwl_print_hex_dump(priv, IWL_DL_RX, data, length);
 508 }
 509
 510 static void iwl3945_dbg_report_frame(struct iwl_priv *priv,
 511                       struct iwl_rx_packet *pkt,
 512                       struct ieee80211_hdr *header, int group100)
 513 {
 514         if (iwl_get_debug_level(priv) & IWL_DL_RX)
 515                 _iwl3945_dbg_report_frame(priv, pkt, header, group100);
 516 }
 517
 518 #else
 519 static inline void iwl3945_dbg_report_frame(struct iwl_priv *priv,
 520                       struct iwl_rx_packet *pkt,
 521                       struct ieee80211_hdr *header, int group100)
 522 {
 523 }
 524 #endif
 525
 526 /* This is necessary only for a number of statistics, see the caller. */
 527 static int iwl3945_is_network_packet(struct iwl_priv *priv,
 528                 struct ieee80211_hdr *header)
 529 {
 530         /* Filter incoming packets to determine if they are targeted toward
 531          * this network, discarding packets coming from ourselves */
 532         switch (priv->iw_mode) {
 533         case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source    | BSSID */
 534                 /* packets to our IBSS update information */
 535                 return !compare_ether_addr(header->addr3, priv->bssid);
 536         case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */
 537                 /* packets to our IBSS update information */
 538                 return !compare_ether_addr(header->addr2, priv->bssid);
 539         default:
 540                 return 1;
 541         }
 542 }
 543
 544 static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv,
 545                                    struct iwl_rx_mem_buffer *rxb,
 546                                    struct ieee80211_rx_status *stats)
 547 {
 548         struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
 549         struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
 550         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
 551         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
 552         short len = le16_to_cpu(rx_hdr->len);
 553
 554         /* We received data from the HW, so stop the watchdog */
 555         if (unlikely((len + IWL39_RX_FRAME_SIZE) > skb_tailroom(rxb->skb))) {
 556                 IWL_DEBUG_DROP(priv, "Corruption detected!\n");
 557                 return;
 558         }
 559
 560         /* We only process data packets if the interface is open */
 561         if (unlikely(!priv->is_open)) {
 562                 IWL_DEBUG_DROP_LIMIT(priv,
 563                         "Dropping packet while interface is not open.\n");
 564                 return;
 565         }
 566
 567         skb_reserve(rxb->skb, (void *)rx_hdr->payload - (void *)pkt);
 568         /* Set the size of the skb to the size of the frame */
 569         skb_put(rxb->skb, le16_to_cpu(rx_hdr->len));
 570
 571         if (!iwl3945_mod_params.sw_crypto)
 572                 iwl_set_decrypted_flag(priv,
 573                                        (struct ieee80211_hdr *)rxb->skb->data,
 574                                        le32_to_cpu(rx_end->status), stats);
 575
 576         iwl_update_stats(priv, false, hdr->frame_control, len);
 577
 578         memcpy(IEEE80211_SKB_RXCB(rxb->skb), stats, sizeof(*stats));
 579         ieee80211_rx_irqsafe(priv->hw, rxb->skb);
 580         rxb->skb = NULL;
 581 }
 582
 583 #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
 584
 585 static void iwl3945_rx_reply_rx(struct iwl_priv *priv,
 586                                 struct iwl_rx_mem_buffer *rxb)
 587 {
 588         struct ieee80211_hdr *header;
 589         struct ieee80211_rx_status rx_status;
 590         struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
 591         struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
 592         struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
 593         struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt);
 594         int snr;
 595         u16 rx_stats_sig_avg = le16_to_cpu(rx_stats->sig_avg);
 596         u16 rx_stats_noise_diff = le16_to_cpu(rx_stats->noise_diff);
 597         u8 network_packet;
 598
 599         rx_status.flag = 0;
 600         rx_status.mactime = le64_to_cpu(rx_end->timestamp);
 601         rx_status.freq =
 602                 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel));
 603         rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
 604                                 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
 605
 606         rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate);
 607         if (rx_status.band == IEEE80211_BAND_5GHZ)
 608                 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
 609
 610         rx_status.antenna = le16_to_cpu(rx_hdr->phy_flags &
 611                                         RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
 612
 613         /* set the preamble flag if appropriate */
 614         if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
 615                 rx_status.flag |= RX_FLAG_SHORTPRE;
 616
 617         if ((unlikely(rx_stats->phy_count > 20))) {
 618                 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
 619                                 rx_stats->phy_count);
 620                 return;
 621         }
 622
 623         if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR)
 624             || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
 625                 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n", rx_end->status);
 626                 return;
 627         }
 628
 629
 630
 631         /* Convert 3945's rssi indicator to dBm */
 632         rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET;
 633
 634         /* Set default noise value to -127 */
 635         if (priv->last_rx_noise == 0)
 636                 priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
 637
 638         /* 3945 provides noise info for OFDM frames only.
 639          * sig_avg and noise_diff are measured by the 3945's digital signal
 640          *   processor (DSP), and indicate linear levels of signal level and
 641          *   distortion/noise within the packet preamble after
 642          *   automatic gain control (AGC).  sig_avg should stay fairly
 643          *   constant if the radio's AGC is working well.
 644          * Since these values are linear (not dB or dBm), linear
 645          *   signal-to-noise ratio (SNR) is (sig_avg / noise_diff).
 646          * Convert linear SNR to dB SNR, then subtract that from rssi dBm
 647          *   to obtain noise level in dBm.
 648          * Calculate rx_status.signal (quality indicator in %) based on SNR. */
 649         if (rx_stats_noise_diff) {
 650                 snr = rx_stats_sig_avg / rx_stats_noise_diff;
 651                 rx_status.noise = rx_status.signal -
 652                                         iwl3945_calc_db_from_ratio(snr);
 653                 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal,
 654                                                          rx_status.noise);
 655
 656         /* If noise info not available, calculate signal quality indicator (%)
 657          *   using just the dBm signal level. */
 658         } else {
 659                 rx_status.noise = priv->last_rx_noise;
 660                 rx_status.qual = iwl3945_calc_sig_qual(rx_status.signal, 0);
 661         }
 662
 663
 664         IWL_DEBUG_STATS(priv, "Rssi %d noise %d qual %d sig_avg %d noise_diff %d\n",
 665                         rx_status.signal, rx_status.noise, rx_status.qual,
 666                         rx_stats_sig_avg, rx_stats_noise_diff);
 667
 668         header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt);
 669
 670         network_packet = iwl3945_is_network_packet(priv, header);
 671
 672         IWL_DEBUG_STATS_LIMIT(priv, "[%c] %d RSSI:%d Signal:%u, Noise:%u, Rate:%u\n",
 673                               network_packet ? '*' : ' ',
 674                               le16_to_cpu(rx_hdr->channel),
 675                               rx_status.signal, rx_status.signal,
 676                               rx_status.noise, rx_status.rate_idx);
 677
 678         /* Set "1" to report good data frames in groups of 100 */
 679         iwl3945_dbg_report_frame(priv, pkt, header, 1);
 680         iwl_dbg_log_rx_data_frame(priv, le16_to_cpu(rx_hdr->len), header);
 681
 682         if (network_packet) {
 683                 priv->last_beacon_time = le32_to_cpu(rx_end->beacon_timestamp);
 684                 priv->last_tsf = le64_to_cpu(rx_end->timestamp);
 685                 priv->last_rx_rssi = rx_status.signal;
 686                 priv->last_rx_noise = rx_status.noise;
 687         }
 688
 689         iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status);
 690 }
 691
 692 int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
 693                                      struct iwl_tx_queue *txq,
 694                                      dma_addr_t addr, u16 len, u8 reset, u8 pad)
 695 {
 696         int count;
 697         struct iwl_queue *q;
 698         struct iwl3945_tfd *tfd, *tfd_tmp;
 699
 700         q = &txq->q;
 701         tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
 702         tfd = &tfd_tmp[q->write_ptr];
 703
 704         if (reset)
 705                 memset(tfd, 0, sizeof(*tfd));
 706
 707         count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
 708
 709         if ((count >= NUM_TFD_CHUNKS) || (count < 0)) {
 710                 IWL_ERR(priv, "Error can not send more than %d chunks\n",
 711                           NUM_TFD_CHUNKS);
 712                 return -EINVAL;
 713         }
 714
 715         tfd->tbs[count].addr = cpu_to_le32(addr);
 716         tfd->tbs[count].len = cpu_to_le32(len);
 717
 718         count++;
 719
 720         tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) |
 721                                          TFD_CTL_PAD_SET(pad));
 722
 723         return 0;
 724 }
 725
 726 /**
 727  * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
 728  *
 729  * Does NOT advance any indexes
 730  */
 731 void iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
 732 {
 733         struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)txq->tfds;
 734         int index = txq->q.read_ptr;
 735         struct iwl3945_tfd *tfd = &tfd_tmp[index];
 736         struct pci_dev *dev = priv->pci_dev;
 737         int i;
 738         int counter;
 739
 740         /* sanity check */
 741         counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags));
 742         if (counter > NUM_TFD_CHUNKS) {
 743                 IWL_ERR(priv, "Too many chunks: %i\n", counter);
 744                 /* @todo issue fatal error, it is quite serious situation */
 745                 return;
 746         }
 747
 748         /* Unmap tx_cmd */
 749         if (counter)
 750                 pci_unmap_single(dev,
 751                                 pci_unmap_addr(&txq->meta[index], mapping),
 752                                 pci_unmap_len(&txq->meta[index], len),
 753                                 PCI_DMA_TODEVICE);
 754
 755         /* unmap chunks if any */
 756
 757         for (i = 1; i < counter; i++) {
 758                 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr),
 759                          le32_to_cpu(tfd->tbs[i].len), PCI_DMA_TODEVICE);
 760                 if (txq->txb[txq->q.read_ptr].skb[0]) {
 761                         struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[0];
 762                         if (txq->txb[txq->q.read_ptr].skb[0]) {
 763                                 /* Can be called from interrupt context */
 764                                 dev_kfree_skb_any(skb);
 765                                 txq->txb[txq->q.read_ptr].skb[0] = NULL;
 766                         }
 767                 }
 768         }
 769         return ;
 770 }
 771
 772 /**
 773  * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD:
 774  *
 775 */
 776 void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv,
 777                                   struct iwl_device_cmd *cmd,
 778                                   struct ieee80211_tx_info *info,
 779                                   struct ieee80211_hdr *hdr,
 780                                   int sta_id, int tx_id)
 781 {
 782         u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value;
 783         u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT - 1);
 784         u16 rate_mask;
 785         int rate;
 786         u8 rts_retry_limit;
 787         u8 data_retry_limit;
 788         __le32 tx_flags;
 789         __le16 fc = hdr->frame_control;
 790         struct iwl3945_tx_cmd *tx = (struct iwl3945_tx_cmd *)cmd->cmd.payload;
 791
 792         rate = iwl3945_rates[rate_index].plcp;
 793         tx_flags = tx->tx_flags;
 794
 795         /* We need to figure out how to get the sta->supp_rates while
 796          * in this running context */
 797         rate_mask = IWL_RATES_MASK;
 798
 799         if (tx_id >= IWL_CMD_QUEUE_NUM)
 800                 rts_retry_limit = 3;
 801         else
 802                 rts_retry_limit = 7;
 803
 804         if (ieee80211_is_probe_resp(fc)) {
 805                 data_retry_limit = 3;
 806                 if (data_retry_limit < rts_retry_limit)
 807                         rts_retry_limit = data_retry_limit;
 808         } else
 809                 data_retry_limit = IWL_DEFAULT_TX_RETRY;
 810
 811         if (priv->data_retry_limit != -1)
 812                 data_retry_limit = priv->data_retry_limit;
 813
 814         if (ieee80211_is_mgmt(fc)) {
 815                 switch (fc & cpu_to_le16(IEEE80211_FCTL_STYPE)) {
 816                 case cpu_to_le16(IEEE80211_STYPE_AUTH):
 817                 case cpu_to_le16(IEEE80211_STYPE_DEAUTH):
 818                 case cpu_to_le16(IEEE80211_STYPE_ASSOC_REQ):
 819                 case cpu_to_le16(IEEE80211_STYPE_REASSOC_REQ):
 820                         if (tx_flags & TX_CMD_FLG_RTS_MSK) {
 821                                 tx_flags &= ~TX_CMD_FLG_RTS_MSK;
 822                                 tx_flags |= TX_CMD_FLG_CTS_MSK;
 823                         }
 824                         break;
 825                 default:
 826                         break;
 827                 }
 828         }
 829
 830         tx->rts_retry_limit = rts_retry_limit;
 831         tx->data_retry_limit = data_retry_limit;
 832         tx->rate = rate;
 833         tx->tx_flags = tx_flags;
 834
 835         /* OFDM */
 836         tx->supp_rates[0] =
 837            ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF;
 838
 839         /* CCK */
 840         tx->supp_rates[1] = (rate_mask & 0xF);
 841
 842         IWL_DEBUG_RATE(priv, "Tx sta id: %d, rate: %d (plcp), flags: 0x%4X "
 843                        "cck/ofdm mask: 0x%x/0x%x\n", sta_id,
 844                        tx->rate, le32_to_cpu(tx->tx_flags),
 845                        tx->supp_rates[1], tx->supp_rates[0]);
 846 }
 847
 848 u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate, u8 flags)
 849 {
 850         unsigned long flags_spin;
 851         struct iwl_station_entry *station;
 852
 853         if (sta_id == IWL_INVALID_STATION)
 854                 return IWL_INVALID_STATION;
 855
 856         spin_lock_irqsave(&priv->sta_lock, flags_spin);
 857         station = &priv->stations[sta_id];
 858
 859         station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK;
 860         station->sta.rate_n_flags = cpu_to_le16(tx_rate);
 861         station->sta.mode = STA_CONTROL_MODIFY_MSK;
 862
 863         spin_unlock_irqrestore(&priv->sta_lock, flags_spin);
 864
 865         iwl_send_add_sta(priv, &station->sta, flags);
 866         IWL_DEBUG_RATE(priv, "SCALE sync station %d to rate %d\n",
 867                         sta_id, tx_rate);
 868         return sta_id;
 869 }
 870
 871 static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
 872 {
 873         if (src == IWL_PWR_SRC_VAUX) {
 874                 if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) {
 875                         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 876                                         APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 877                                         ~APMG_PS_CTRL_MSK_PWR_SRC);
 878
 879                         iwl_poll_bit(priv, CSR_GPIO_IN,
 880                                      CSR_GPIO_IN_VAL_VAUX_PWR_SRC,
 881                                      CSR_GPIO_IN_BIT_AUX_POWER, 5000);
 882                 }
 883         } else {
 884                 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 885                                 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 886                                 ~APMG_PS_CTRL_MSK_PWR_SRC);
 887
 888                 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC,
 889                              CSR_GPIO_IN_BIT_AUX_POWER, 5000);  /* uS */
 890         }
 891
 892         return 0;
 893 }
 894
 895 static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
 896 {
 897         iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->dma_addr);
 898         iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma);
 899         iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0);
 900         iwl_write_direct32(priv, FH39_RCSR_CONFIG(0),
 901                 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE |
 902                 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE |
 903                 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN |
 904                 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 |
 905                 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) |
 906                 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST |
 907                 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) |
 908                 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH);
 909
 910         /* fake read to flush all prev I/O */
 911         iwl_read_direct32(priv, FH39_RSSR_CTRL);
 912
 913         return 0;
 914 }
 915
 916 static int iwl3945_tx_reset(struct iwl_priv *priv)
 917 {
 918
 919         /* bypass mode */
 920         iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2);
 921
 922         /* RA 0 is active */
 923         iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01);
 924
 925         /* all 6 fifo are active */
 926         iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f);
 927
 928         iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000);
 929         iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002);
 930         iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004);
 931         iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005);
 932
 933         iwl_write_direct32(priv, FH39_TSSR_CBB_BASE,
 934                              priv->shared_phys);
 935
 936         iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG,
 937                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON |
 938                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON |
 939                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B |
 940                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON |
 941                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON |
 942                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH |
 943                 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH);
 944
 945
 946         return 0;
 947 }
 948
 949 /**
 950  * iwl3945_txq_ctx_reset - Reset TX queue context
 951  *
 952  * Destroys all DMA structures and initialize them again
 953  */
 954 static int iwl3945_txq_ctx_reset(struct iwl_priv *priv)
 955 {
 956         int rc;
 957         int txq_id, slots_num;
 958
 959         iwl3945_hw_txq_ctx_free(priv);
 960
 961         /* Tx CMD queue */
 962         rc = iwl3945_tx_reset(priv);
 963         if (rc)
 964                 goto error;
 965
 966         /* Tx queue(s) */
 967         for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
 968                 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
 969                                 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
 970                 rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
 971                                        txq_id);
 972                 if (rc) {
 973                         IWL_ERR(priv, "Tx %d queue init failed\n", txq_id);
 974                         goto error;
 975                 }
 976         }
 977
 978         return rc;
 979
 980  error:
 981         iwl3945_hw_txq_ctx_free(priv);
 982         return rc;
 983 }
 984
 985 static int iwl3945_apm_init(struct iwl_priv *priv)
 986 {
 987         int ret;
 988
 989         iwl_power_initialize(priv);
 990
 991         iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
 992                           CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 993
 994         /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
 995         iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
 996                           CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 997
 998         /* set "initialization complete" bit to move adapter
 999         * D0U* --> D0A* state */
1000         iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1001
1002         ret = iwl_poll_bit(priv, CSR_GP_CNTRL,
1003                         CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1004                         CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1005         if (ret < 0) {
1006                 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
1007                 goto out;
1008         }
1009
1010         /* enable DMA */
1011         iwl_write_prph(priv, APMG_CLK_CTRL_REG, APMG_CLK_VAL_DMA_CLK_RQT |
1012                                                 APMG_CLK_VAL_BSM_CLK_RQT);
1013
1014         udelay(20);
1015
1016         /* disable L1-Active */
1017         iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
1018                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
1019
1020 out:
1021         return ret;
1022 }
1023
1024 static void iwl3945_nic_config(struct iwl_priv *priv)
1025 {
1026         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1027         unsigned long flags;
1028         u8 rev_id = 0;
1029
1030         spin_lock_irqsave(&priv->lock, flags);
1031
1032         /* Determine HW type */
1033         pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
1034
1035         IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
1036
1037         if (rev_id & PCI_CFG_REV_ID_BIT_RTP)
1038                 IWL_DEBUG_INFO(priv, "RTP type \n");
1039         else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) {
1040                 IWL_DEBUG_INFO(priv, "3945 RADIO-MB type\n");
1041                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1042                             CSR39_HW_IF_CONFIG_REG_BIT_3945_MB);
1043         } else {
1044                 IWL_DEBUG_INFO(priv, "3945 RADIO-MM type\n");
1045                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1046                             CSR39_HW_IF_CONFIG_REG_BIT_3945_MM);
1047         }
1048
1049         if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) {
1050                 IWL_DEBUG_INFO(priv, "SKU OP mode is mrc\n");
1051                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1052                             CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC);
1053         } else
1054                 IWL_DEBUG_INFO(priv, "SKU OP mode is basic\n");
1055
1056         if ((eeprom->board_revision & 0xF0) == 0xD0) {
1057                 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
1058                                eeprom->board_revision);
1059                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1060                             CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1061         } else {
1062                 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n",
1063                                eeprom->board_revision);
1064                 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG,
1065                               CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE);
1066         }
1067
1068         if (eeprom->almgor_m_version <= 1) {
1069                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1070                             CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A);
1071                 IWL_DEBUG_INFO(priv, "Card M type A version is 0x%X\n",
1072                                eeprom->almgor_m_version);
1073         } else {
1074                 IWL_DEBUG_INFO(priv, "Card M type B version is 0x%X\n",
1075                                eeprom->almgor_m_version);
1076                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1077                             CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B);
1078         }
1079         spin_unlock_irqrestore(&priv->lock, flags);
1080
1081         if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
1082                 IWL_DEBUG_RF_KILL(priv, "SW RF KILL supported in EEPROM.\n");
1083
1084         if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
1085                 IWL_DEBUG_RF_KILL(priv, "HW RF KILL supported in EEPROM.\n");
1086 }
1087
1088 int iwl3945_hw_nic_init(struct iwl_priv *priv)
1089 {
1090         int rc;
1091         unsigned long flags;
1092         struct iwl_rx_queue *rxq = &priv->rxq;
1093
1094         spin_lock_irqsave(&priv->lock, flags);
1095         priv->cfg->ops->lib->apm_ops.init(priv);
1096         spin_unlock_irqrestore(&priv->lock, flags);
1097
1098         rc = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
1099         if (rc)
1100                 return rc;
1101
1102         priv->cfg->ops->lib->apm_ops.config(priv);
1103
1104         /* Allocate the RX queue, or reset if it is already allocated */
1105         if (!rxq->bd) {
1106                 rc = iwl_rx_queue_alloc(priv);
1107                 if (rc) {
1108                         IWL_ERR(priv, "Unable to initialize Rx queue\n");
1109                         return -ENOMEM;
1110                 }
1111         } else
1112                 iwl3945_rx_queue_reset(priv, rxq);
1113
1114         iwl3945_rx_replenish(priv);
1115
1116         iwl3945_rx_init(priv, rxq);
1117
1118
1119         /* Look at using this instead:
1120         rxq->need_update = 1;
1121         iwl_rx_queue_update_write_ptr(priv, rxq);
1122         */
1123
1124         iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7);
1125
1126         rc = iwl3945_txq_ctx_reset(priv);
1127         if (rc)
1128                 return rc;
1129
1130         set_bit(STATUS_INIT, &priv->status);
1131
1132         return 0;
1133 }
1134
1135 /**
1136  * iwl3945_hw_txq_ctx_free - Free TXQ Context
1137  *
1138  * Destroy all TX DMA queues and structures
1139  */
1140 void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv)
1141 {
1142         int txq_id;
1143
1144         /* Tx queues */
1145         for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++)
1146                 if (txq_id == IWL_CMD_QUEUE_NUM)
1147                         iwl_cmd_queue_free(priv);
1148                 else
1149                         iwl_tx_queue_free(priv, txq_id);
1150
1151 }
1152
1153 void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv)
1154 {
1155         int txq_id;
1156
1157         /* stop SCD */
1158         iwl_write_prph(priv, ALM_SCD_MODE_REG, 0);
1159
1160         /* reset TFD queues */
1161         for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
1162                 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0);
1163                 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS,
1164                                 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id),
1165                                 1000);
1166         }
1167
1168         iwl3945_hw_txq_ctx_free(priv);
1169 }
1170
1171 static int iwl3945_apm_reset(struct iwl_priv *priv)
1172 {
1173         iwl_apm_stop_master(priv);
1174
1175
1176         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
1177         udelay(10);
1178
1179         iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1180
1181         iwl_poll_bit(priv, CSR_GP_CNTRL,
1182                         CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
1183                         CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
1184
1185         iwl_write_prph(priv, APMG_CLK_CTRL_REG,
1186                                 APMG_CLK_VAL_BSM_CLK_RQT);
1187
1188         iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1189         iwl_write_prph(priv, APMG_RTC_INT_STT_REG,
1190                                         0xFFFFFFFF);
1191
1192         /* enable DMA */
1193         iwl_write_prph(priv, APMG_CLK_EN_REG,
1194                                 APMG_CLK_VAL_DMA_CLK_RQT |
1195                                 APMG_CLK_VAL_BSM_CLK_RQT);
1196         udelay(10);
1197
1198         iwl_set_bits_prph(priv, APMG_PS_CTRL_REG,
1199                                 APMG_PS_CTRL_VAL_RESET_REQ);
1200         udelay(5);
1201         iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG,
1202                                 APMG_PS_CTRL_VAL_RESET_REQ);
1203
1204         /* Clear the 'host command active' bit... */
1205         clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
1206
1207         wake_up_interruptible(&priv->wait_command_queue);
1208
1209         return 0;
1210 }
1211
1212 /**
1213  * iwl3945_hw_reg_adjust_power_by_temp
1214  * return index delta into power gain settings table
1215 */
1216 static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading)
1217 {
1218         return (new_reading - old_reading) * (-11) / 100;
1219 }
1220
1221 /**
1222  * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range
1223  */
1224 static inline int iwl3945_hw_reg_temp_out_of_range(int temperature)
1225 {
1226         return ((temperature < -260) || (temperature > 25)) ? 1 : 0;
1227 }
1228
1229 int iwl3945_hw_get_temperature(struct iwl_priv *priv)
1230 {
1231         return iwl_read32(priv, CSR_UCODE_DRV_GP2);
1232 }
1233
1234 /**
1235  * iwl3945_hw_reg_txpower_get_temperature
1236  * get the current temperature by reading from NIC
1237 */
1238 static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv)
1239 {
1240         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1241         int temperature;
1242
1243         temperature = iwl3945_hw_get_temperature(priv);
1244
1245         /* driver's okay range is -260 to +25.
1246          *   human readable okay range is 0 to +285 */
1247         IWL_DEBUG_INFO(priv, "Temperature: %d\n", temperature + IWL_TEMP_CONVERT);
1248
1249         /* handle insane temp reading */
1250         if (iwl3945_hw_reg_temp_out_of_range(temperature)) {
1251                 IWL_ERR(priv, "Error bad temperature value  %d\n", temperature);
1252
1253                 /* if really really hot(?),
1254                  *   substitute the 3rd band/group's temp measured at factory */
1255                 if (priv->last_temperature > 100)
1256                         temperature = eeprom->groups[2].temperature;
1257                 else /* else use most recent "sane" value from driver */
1258                         temperature = priv->last_temperature;
1259         }
1260
1261         return temperature;     /* raw, not "human readable" */
1262 }
1263
1264 /* Adjust Txpower only if temperature variance is greater than threshold.
1265  *
1266  * Both are lower than older versions' 9 degrees */
1267 #define IWL_TEMPERATURE_LIMIT_TIMER   6
1268
1269 /**
1270  * is_temp_calib_needed - determines if new calibration is needed
1271  *
1272  * records new temperature in tx_mgr->temperature.
1273  * replaces tx_mgr->last_temperature *only* if calib needed
1274  *    (assumes caller will actually do the calibration!). */
1275 static int is_temp_calib_needed(struct iwl_priv *priv)
1276 {
1277         int temp_diff;
1278
1279         priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
1280         temp_diff = priv->temperature - priv->last_temperature;
1281
1282         /* get absolute value */
1283         if (temp_diff < 0) {
1284                 IWL_DEBUG_POWER(priv, "Getting cooler, delta %d,\n", temp_diff);
1285                 temp_diff = -temp_diff;
1286         } else if (temp_diff == 0)
1287                 IWL_DEBUG_POWER(priv, "Same temp,\n");
1288         else
1289                 IWL_DEBUG_POWER(priv, "Getting warmer, delta %d,\n", temp_diff);
1290
1291         /* if we don't need calibration, *don't* update last_temperature */
1292         if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) {
1293                 IWL_DEBUG_POWER(priv, "Timed thermal calib not needed\n");
1294                 return 0;
1295         }
1296
1297         IWL_DEBUG_POWER(priv, "Timed thermal calib needed\n");
1298
1299         /* assume that caller will actually do calib ...
1300          *   update the "last temperature" value */
1301         priv->last_temperature = priv->temperature;
1302         return 1;
1303 }
1304
1305 #define IWL_MAX_GAIN_ENTRIES 78
1306 #define IWL_CCK_FROM_OFDM_POWER_DIFF  -5
1307 #define IWL_CCK_FROM_OFDM_INDEX_DIFF (10)
1308
1309 /* radio and DSP power table, each step is 1/2 dB.
1310  * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */
1311 static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = {
1312         {
1313          {251, 127},            /* 2.4 GHz, highest power */
1314          {251, 127},
1315          {251, 127},
1316          {251, 127},
1317          {251, 125},
1318          {251, 110},
1319          {251, 105},
1320          {251, 98},
1321          {187, 125},
1322          {187, 115},
1323          {187, 108},
1324          {187, 99},
1325          {243, 119},
1326          {243, 111},
1327          {243, 105},
1328          {243, 97},
1329          {243, 92},
1330          {211, 106},
1331          {211, 100},
1332          {179, 120},
1333          {179, 113},
1334          {179, 107},
1335          {147, 125},
1336          {147, 119},
1337          {147, 112},
1338          {147, 106},
1339          {147, 101},
1340          {147, 97},
1341          {147, 91},
1342          {115, 107},
1343          {235, 121},
1344          {235, 115},
1345          {235, 109},
1346          {203, 127},
1347          {203, 121},
1348          {203, 115},
1349          {203, 108},
1350          {203, 102},
1351          {203, 96},
1352          {203, 92},
1353          {171, 110},
1354          {171, 104},
1355          {171, 98},
1356          {139, 116},
1357          {227, 125},
1358          {227, 119},
1359          {227, 113},
1360          {227, 107},
1361          {227, 101},
1362          {227, 96},
1363          {195, 113},
1364          {195, 106},
1365          {195, 102},
1366          {195, 95},
1367          {163, 113},
1368          {163, 106},
1369          {163, 102},
1370          {163, 95},
1371          {131, 113},
1372          {131, 106},
1373          {131, 102},
1374          {131, 95},
1375          {99, 113},
1376          {99, 106},
1377          {99, 102},
1378          {99, 95},
1379          {67, 113},
1380          {67, 106},
1381          {67, 102},
1382          {67, 95},
1383          {35, 113},
1384          {35, 106},
1385          {35, 102},
1386          {35, 95},
1387          {3, 113},
1388          {3, 106},
1389          {3, 102},
1390          {3, 95} },             /* 2.4 GHz, lowest power */
1391         {
1392          {251, 127},            /* 5.x GHz, highest power */
1393          {251, 120},
1394          {251, 114},
1395          {219, 119},
1396          {219, 101},
1397          {187, 113},
1398          {187, 102},
1399          {155, 114},
1400          {155, 103},
1401          {123, 117},
1402          {123, 107},
1403          {123, 99},
1404          {123, 92},
1405          {91, 108},
1406          {59, 125},
1407          {59, 118},
1408          {59, 109},
1409          {59, 102},
1410          {59, 96},
1411          {59, 90},
1412          {27, 104},
1413          {27, 98},
1414          {27, 92},
1415          {115, 118},
1416          {115, 111},
1417          {115, 104},
1418          {83, 126},
1419          {83, 121},
1420          {83, 113},
1421          {83, 105},
1422          {83, 99},
1423          {51, 118},
1424          {51, 111},
1425          {51, 104},
1426          {51, 98},
1427          {19, 116},
1428          {19, 109},
1429          {19, 102},
1430          {19, 98},
1431          {19, 93},
1432          {171, 113},
1433          {171, 107},
1434          {171, 99},
1435          {139, 120},
1436          {139, 113},
1437          {139, 107},
1438          {139, 99},
1439          {107, 120},
1440          {107, 113},
1441          {107, 107},
1442          {107, 99},
1443          {75, 120},
1444          {75, 113},
1445          {75, 107},
1446          {75, 99},
1447          {43, 120},
1448          {43, 113},
1449          {43, 107},
1450          {43, 99},
1451          {11, 120},
1452          {11, 113},
1453          {11, 107},
1454          {11, 99},
1455          {131, 107},
1456          {131, 99},
1457          {99, 120},
1458          {99, 113},
1459          {99, 107},
1460          {99, 99},
1461          {67, 120},
1462          {67, 113},
1463          {67, 107},
1464          {67, 99},
1465          {35, 120},
1466          {35, 113},
1467          {35, 107},
1468          {35, 99},
1469          {3, 120} }             /* 5.x GHz, lowest power */
1470 };
1471
1472 static inline u8 iwl3945_hw_reg_fix_power_index(int index)
1473 {
1474         if (index < 0)
1475                 return 0;
1476         if (index >= IWL_MAX_GAIN_ENTRIES)
1477                 return IWL_MAX_GAIN_ENTRIES - 1;
1478         return (u8) index;
1479 }
1480
1481 /* Kick off thermal recalibration check every 60 seconds */
1482 #define REG_RECALIB_PERIOD (60)
1483
1484 /**
1485  * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests
1486  *
1487  * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK)
1488  * or 6 Mbit (OFDM) rates.
1489  */
1490 static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index,
1491                                s32 rate_index, const s8 *clip_pwrs,
1492                                struct iwl_channel_info *ch_info,
1493                                int band_index)
1494 {
1495         struct iwl3945_scan_power_info *scan_power_info;
1496         s8 power;
1497         u8 power_index;
1498
1499         scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index];
1500
1501         /* use this channel group's 6Mbit clipping/saturation pwr,
1502          *   but cap at regulatory scan power restriction (set during init
1503          *   based on eeprom channel data) for this channel.  */
1504         power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]);
1505
1506         /* further limit to user's max power preference.
1507          * FIXME:  Other spectrum management power limitations do not
1508          *   seem to apply?? */
1509         power = min(power, priv->tx_power_user_lmt);
1510         scan_power_info->requested_power = power;
1511
1512         /* find difference between new scan *power* and current "normal"
1513          *   Tx *power* for 6Mb.  Use this difference (x2) to adjust the
1514          *   current "normal" temperature-compensated Tx power *index* for
1515          *   this rate (1Mb or 6Mb) to yield new temp-compensated scan power
1516          *   *index*. */
1517         power_index = ch_info->power_info[rate_index].power_table_index
1518             - (power - ch_info->power_info
1519                [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2;
1520
1521         /* store reference index that we use when adjusting *all* scan
1522          *   powers.  So we can accommodate user (all channel) or spectrum
1523          *   management (single channel) power changes "between" temperature
1524          *   feedback compensation procedures.
1525          * don't force fit this reference index into gain table; it may be a
1526          *   negative number.  This will help avoid errors when we're at
1527          *   the lower bounds (highest gains, for warmest temperatures)
1528          *   of the table. */
1529
1530         /* don't exceed table bounds for "real" setting */
1531         power_index = iwl3945_hw_reg_fix_power_index(power_index);
1532
1533         scan_power_info->power_table_index = power_index;
1534         scan_power_info->tpc.tx_gain =
1535             power_gain_table[band_index][power_index].tx_gain;
1536         scan_power_info->tpc.dsp_atten =
1537             power_gain_table[band_index][power_index].dsp_atten;
1538 }
1539
1540 /**
1541  * iwl3945_send_tx_power - fill in Tx Power command with gain settings
1542  *
1543  * Configures power settings for all rates for the current channel,
1544  * using values from channel info struct, and send to NIC
1545  */
1546 static int iwl3945_send_tx_power(struct iwl_priv *priv)
1547 {
1548         int rate_idx, i;
1549         const struct iwl_channel_info *ch_info = NULL;
1550         struct iwl3945_txpowertable_cmd txpower = {
1551                 .channel = priv->active_rxon.channel,
1552         };
1553
1554         txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1;
1555         ch_info = iwl_get_channel_info(priv,
1556                                        priv->band,
1557                                        le16_to_cpu(priv->active_rxon.channel));
1558         if (!ch_info) {
1559                 IWL_ERR(priv,
1560                         "Failed to get channel info for channel %d [%d]\n",
1561                         le16_to_cpu(priv->active_rxon.channel), priv->band);
1562                 return -EINVAL;
1563         }
1564
1565         if (!is_channel_valid(ch_info)) {
1566                 IWL_DEBUG_POWER(priv, "Not calling TX_PWR_TABLE_CMD on "
1567                                 "non-Tx channel.\n");
1568                 return 0;
1569         }
1570
1571         /* fill cmd with power settings for all rates for current channel */
1572         /* Fill OFDM rate */
1573         for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0;
1574              rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) {
1575
1576                 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1577                 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1578
1579                 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1580                                 le16_to_cpu(txpower.channel),
1581                                 txpower.band,
1582                                 txpower.power[i].tpc.tx_gain,
1583                                 txpower.power[i].tpc.dsp_atten,
1584                                 txpower.power[i].rate);
1585         }
1586         /* Fill CCK rates */
1587         for (rate_idx = IWL_FIRST_CCK_RATE;
1588              rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) {
1589                 txpower.power[i].tpc = ch_info->power_info[i].tpc;
1590                 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp;
1591
1592                 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n",
1593                                 le16_to_cpu(txpower.channel),
1594                                 txpower.band,
1595                                 txpower.power[i].tpc.tx_gain,
1596                                 txpower.power[i].tpc.dsp_atten,
1597                                 txpower.power[i].rate);
1598         }
1599
1600         return iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD,
1601                                 sizeof(struct iwl3945_txpowertable_cmd),
1602                                 &txpower);
1603
1604 }
1605
1606 /**
1607  * iwl3945_hw_reg_set_new_power - Configures power tables at new levels
1608  * @ch_info: Channel to update.  Uses power_info.requested_power.
1609  *
1610  * Replace requested_power and base_power_index ch_info fields for
1611  * one channel.
1612  *
1613  * Called if user or spectrum management changes power preferences.
1614  * Takes into account h/w and modulation limitations (clip power).
1615  *
1616  * This does *not* send anything to NIC, just sets up ch_info for one channel.
1617  *
1618  * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to
1619  *       properly fill out the scan powers, and actual h/w gain settings,
1620  *       and send changes to NIC
1621  */
1622 static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv,
1623                              struct iwl_channel_info *ch_info)
1624 {
1625         struct iwl3945_channel_power_info *power_info;
1626         int power_changed = 0;
1627         int i;
1628         const s8 *clip_pwrs;
1629         int power;
1630
1631         /* Get this chnlgrp's rate-to-max/clip-powers table */
1632         clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
1633
1634         /* Get this channel's rate-to-current-power settings table */
1635         power_info = ch_info->power_info;
1636
1637         /* update OFDM Txpower settings */
1638         for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE;
1639              i++, ++power_info) {
1640                 int delta_idx;
1641
1642                 /* limit new power to be no more than h/w capability */
1643                 power = min(ch_info->curr_txpow, clip_pwrs[i]);
1644                 if (power == power_info->requested_power)
1645                         continue;
1646
1647                 /* find difference between old and new requested powers,
1648                  *    update base (non-temp-compensated) power index */
1649                 delta_idx = (power - power_info->requested_power) * 2;
1650                 power_info->base_power_index -= delta_idx;
1651
1652                 /* save new requested power value */
1653                 power_info->requested_power = power;
1654
1655                 power_changed = 1;
1656         }
1657
1658         /* update CCK Txpower settings, based on OFDM 12M setting ...
1659          *    ... all CCK power settings for a given channel are the *same*. */
1660         if (power_changed) {
1661                 power =
1662                     ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1663                     requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF;
1664
1665                 /* do all CCK rates' iwl3945_channel_power_info structures */
1666                 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) {
1667                         power_info->requested_power = power;
1668                         power_info->base_power_index =
1669                             ch_info->power_info[IWL_RATE_12M_INDEX_TABLE].
1670                             base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF;
1671                         ++power_info;
1672                 }
1673         }
1674
1675         return 0;
1676 }
1677
1678 /**
1679  * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel
1680  *
1681  * NOTE: Returned power limit may be less (but not more) than requested,
1682  *       based strictly on regulatory (eeprom and spectrum mgt) limitations
1683  *       (no consideration for h/w clipping limitations).
1684  */
1685 static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info)
1686 {
1687         s8 max_power;
1688
1689 #if 0
1690         /* if we're using TGd limits, use lower of TGd or EEPROM */
1691         if (ch_info->tgd_data.max_power != 0)
1692                 max_power = min(ch_info->tgd_data.max_power,
1693                                 ch_info->eeprom.max_power_avg);
1694
1695         /* else just use EEPROM limits */
1696         else
1697 #endif
1698                 max_power = ch_info->eeprom.max_power_avg;
1699
1700         return min(max_power, ch_info->max_power_avg);
1701 }
1702
1703 /**
1704  * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature
1705  *
1706  * Compensate txpower settings of *all* channels for temperature.
1707  * This only accounts for the difference between current temperature
1708  *   and the factory calibration temperatures, and bases the new settings
1709  *   on the channel's base_power_index.
1710  *
1711  * If RxOn is "associated", this sends the new Txpower to NIC!
1712  */
1713 static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv)
1714 {
1715         struct iwl_channel_info *ch_info = NULL;
1716         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
1717         int delta_index;
1718         const s8 *clip_pwrs; /* array of h/w max power levels for each rate */
1719         u8 a_band;
1720         u8 rate_index;
1721         u8 scan_tbl_index;
1722         u8 i;
1723         int ref_temp;
1724         int temperature = priv->temperature;
1725
1726         /* set up new Tx power info for each and every channel, 2.4 and 5.x */
1727         for (i = 0; i < priv->channel_count; i++) {
1728                 ch_info = &priv->channel_info[i];
1729                 a_band = is_channel_a_band(ch_info);
1730
1731                 /* Get this chnlgrp's factory calibration temperature */
1732                 ref_temp = (s16)eeprom->groups[ch_info->group_index].
1733                     temperature;
1734
1735                 /* get power index adjustment based on current and factory
1736                  * temps */
1737                 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
1738                                                               ref_temp);
1739
1740                 /* set tx power value for all rates, OFDM and CCK */
1741                 for (rate_index = 0; rate_index < IWL_RATE_COUNT;
1742                      rate_index++) {
1743                         int power_idx =
1744                             ch_info->power_info[rate_index].base_power_index;
1745
1746                         /* temperature compensate */
1747                         power_idx += delta_index;
1748
1749                         /* stay within table range */
1750                         power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
1751                         ch_info->power_info[rate_index].
1752                             power_table_index = (u8) power_idx;
1753                         ch_info->power_info[rate_index].tpc =
1754                             power_gain_table[a_band][power_idx];
1755                 }
1756
1757                 /* Get this chnlgrp's rate-to-max/clip-powers table */
1758                 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
1759
1760                 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
1761                 for (scan_tbl_index = 0;
1762                      scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
1763                         s32 actual_index = (scan_tbl_index == 0) ?
1764                             IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
1765                         iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
1766                                            actual_index, clip_pwrs,
1767                                            ch_info, a_band);
1768                 }
1769         }
1770
1771         /* send Txpower command for current channel to ucode */
1772         return priv->cfg->ops->lib->send_tx_power(priv);
1773 }
1774
1775 int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power)
1776 {
1777         struct iwl_channel_info *ch_info;
1778         s8 max_power;
1779         u8 a_band;
1780         u8 i;
1781
1782         if (priv->tx_power_user_lmt == power) {
1783                 IWL_DEBUG_POWER(priv, "Requested Tx power same as current "
1784                                 "limit: %ddBm.\n", power);
1785                 return 0;
1786         }
1787
1788         IWL_DEBUG_POWER(priv, "Setting upper limit clamp to %ddBm.\n", power);
1789         priv->tx_power_user_lmt = power;
1790
1791         /* set up new Tx powers for each and every channel, 2.4 and 5.x */
1792
1793         for (i = 0; i < priv->channel_count; i++) {
1794                 ch_info = &priv->channel_info[i];
1795                 a_band = is_channel_a_band(ch_info);
1796
1797                 /* find minimum power of all user and regulatory constraints
1798                  *    (does not consider h/w clipping limitations) */
1799                 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info);
1800                 max_power = min(power, max_power);
1801                 if (max_power != ch_info->curr_txpow) {
1802                         ch_info->curr_txpow = max_power;
1803
1804                         /* this considers the h/w clipping limitations */
1805                         iwl3945_hw_reg_set_new_power(priv, ch_info);
1806                 }
1807         }
1808
1809         /* update txpower settings for all channels,
1810          *   send to NIC if associated. */
1811         is_temp_calib_needed(priv);
1812         iwl3945_hw_reg_comp_txpower_temp(priv);
1813
1814         return 0;
1815 }
1816
1817 static int iwl3945_send_rxon_assoc(struct iwl_priv *priv)
1818 {
1819         int rc = 0;
1820         struct iwl_rx_packet *res = NULL;
1821         struct iwl3945_rxon_assoc_cmd rxon_assoc;
1822         struct iwl_host_cmd cmd = {
1823                 .id = REPLY_RXON_ASSOC,
1824                 .len = sizeof(rxon_assoc),
1825                 .flags = CMD_WANT_SKB,
1826                 .data = &rxon_assoc,
1827         };
1828         const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1829         const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1830
1831         if ((rxon1->flags == rxon2->flags) &&
1832             (rxon1->filter_flags == rxon2->filter_flags) &&
1833             (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1834             (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1835                 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC.  Not resending.\n");
1836                 return 0;
1837         }
1838
1839         rxon_assoc.flags = priv->staging_rxon.flags;
1840         rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1841         rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1842         rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1843         rxon_assoc.reserved = 0;
1844
1845         rc = iwl_send_cmd_sync(priv, &cmd);
1846         if (rc)
1847                 return rc;
1848
1849         res = (struct iwl_rx_packet *)cmd.reply_skb->data;
1850         if (res->hdr.flags & IWL_CMD_FAILED_MSK) {
1851                 IWL_ERR(priv, "Bad return from REPLY_RXON_ASSOC command\n");
1852                 rc = -EIO;
1853         }
1854
1855         priv->alloc_rxb_skb--;
1856         dev_kfree_skb_any(cmd.reply_skb);
1857
1858         return rc;
1859 }
1860
1861 /**
1862  * iwl3945_commit_rxon - commit staging_rxon to hardware
1863  *
1864  * The RXON command in staging_rxon is committed to the hardware and
1865  * the active_rxon structure is updated with the new data.  This
1866  * function correctly transitions out of the RXON_ASSOC_MSK state if
1867  * a HW tune is required based on the RXON structure changes.
1868  */
1869 static int iwl3945_commit_rxon(struct iwl_priv *priv)
1870 {
1871         /* cast away the const for active_rxon in this function */
1872         struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
1873         struct iwl3945_rxon_cmd *staging_rxon = (void *)&priv->staging_rxon;
1874         int rc = 0;
1875         bool new_assoc =
1876                 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
1877
1878         if (!iwl_is_alive(priv))
1879                 return -1;
1880
1881         /* always get timestamp with Rx frame */
1882         staging_rxon->flags |= RXON_FLG_TSF2HOST_MSK;
1883
1884         /* select antenna */
1885         staging_rxon->flags &=
1886             ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK);
1887         staging_rxon->flags |= iwl3945_get_antenna_flags(priv);
1888
1889         rc = iwl_check_rxon_cmd(priv);
1890         if (rc) {
1891                 IWL_ERR(priv, "Invalid RXON configuration.  Not committing.\n");
1892                 return -EINVAL;
1893         }
1894
1895         /* If we don't need to send a full RXON, we can use
1896          * iwl3945_rxon_assoc_cmd which is used to reconfigure filter
1897          * and other flags for the current radio configuration. */
1898         if (!iwl_full_rxon_required(priv)) {
1899                 rc = iwl_send_rxon_assoc(priv);
1900                 if (rc) {
1901                         IWL_ERR(priv, "Error setting RXON_ASSOC "
1902                                   "configuration (%d).\n", rc);
1903                         return rc;
1904                 }
1905
1906                 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1907
1908                 return 0;
1909         }
1910
1911         /* If we are currently associated and the new config requires
1912          * an RXON_ASSOC and the new config wants the associated mask enabled,
1913          * we must clear the associated from the active configuration
1914          * before we apply the new config */
1915         if (iwl_is_associated(priv) && new_assoc) {
1916                 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
1917                 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1918
1919                 /*
1920                  * reserved4 and 5 could have been filled by the iwlcore code.
1921                  * Let's clear them before pushing to the 3945.
1922                  */
1923                 active_rxon->reserved4 = 0;
1924                 active_rxon->reserved5 = 0;
1925                 rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1926                                       sizeof(struct iwl3945_rxon_cmd),
1927                                       &priv->active_rxon);
1928
1929                 /* If the mask clearing failed then we set
1930                  * active_rxon back to what it was previously */
1931                 if (rc) {
1932                         active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
1933                         IWL_ERR(priv, "Error clearing ASSOC_MSK on current "
1934                                   "configuration (%d).\n", rc);
1935                         return rc;
1936                 }
1937         }
1938
1939         IWL_DEBUG_INFO(priv, "Sending RXON\n"
1940                        "* with%s RXON_FILTER_ASSOC_MSK\n"
1941                        "* channel = %d\n"
1942                        "* bssid = %pM\n",
1943                        (new_assoc ? "" : "out"),
1944                        le16_to_cpu(staging_rxon->channel),
1945                        staging_rxon->bssid_addr);
1946
1947         /*
1948          * reserved4 and 5 could have been filled by the iwlcore code.
1949          * Let's clear them before pushing to the 3945.
1950          */
1951         staging_rxon->reserved4 = 0;
1952         staging_rxon->reserved5 = 0;
1953
1954         iwl_set_rxon_hwcrypto(priv, !iwl3945_mod_params.sw_crypto);
1955
1956         /* Apply the new configuration */
1957         rc = iwl_send_cmd_pdu(priv, REPLY_RXON,
1958                               sizeof(struct iwl3945_rxon_cmd),
1959                               staging_rxon);
1960         if (rc) {
1961                 IWL_ERR(priv, "Error setting new configuration (%d).\n", rc);
1962                 return rc;
1963         }
1964
1965         memcpy(active_rxon, staging_rxon, sizeof(*active_rxon));
1966
1967         iwl_clear_stations_table(priv);
1968
1969         /* If we issue a new RXON command which required a tune then we must
1970          * send a new TXPOWER command or we won't be able to Tx any frames */
1971         rc = priv->cfg->ops->lib->send_tx_power(priv);
1972         if (rc) {
1973                 IWL_ERR(priv, "Error setting Tx power (%d).\n", rc);
1974                 return rc;
1975         }
1976
1977         /* Add the broadcast address so we can send broadcast frames */
1978         if (iwl_add_station(priv, iwl_bcast_addr, false, CMD_SYNC, NULL) ==
1979             IWL_INVALID_STATION) {
1980                 IWL_ERR(priv, "Error adding BROADCAST address for transmit.\n");
1981                 return -EIO;
1982         }
1983
1984         /* If we have set the ASSOC_MSK and we are in BSS mode then
1985          * add the IWL_AP_ID to the station rate table */
1986         if (iwl_is_associated(priv) &&
1987             (priv->iw_mode == NL80211_IFTYPE_STATION))
1988                 if (iwl_add_station(priv, priv->active_rxon.bssid_addr,
1989                                 true, CMD_SYNC, NULL) == IWL_INVALID_STATION) {
1990                         IWL_ERR(priv, "Error adding AP address for transmit\n");
1991                         return -EIO;
1992                 }
1993
1994         /* Init the hardware's rate fallback order based on the band */
1995         rc = iwl3945_init_hw_rate_table(priv);
1996         if (rc) {
1997                 IWL_ERR(priv, "Error setting HW rate table: %02X\n", rc);
1998                 return -EIO;
1999         }
2000
2001         return 0;
2002 }
2003
2004 /* will add 3945 channel switch cmd handling later */
2005 int iwl3945_hw_channel_switch(struct iwl_priv *priv, u16 channel)
2006 {
2007         return 0;
2008 }
2009
2010 /**
2011  * iwl3945_reg_txpower_periodic -  called when time to check our temperature.
2012  *
2013  * -- reset periodic timer
2014  * -- see if temp has changed enough to warrant re-calibration ... if so:
2015  *     -- correct coeffs for temp (can reset temp timer)
2016  *     -- save this temp as "last",
2017  *     -- send new set of gain settings to NIC
2018  * NOTE:  This should continue working, even when we're not associated,
2019  *   so we can keep our internal table of scan powers current. */
2020 void iwl3945_reg_txpower_periodic(struct iwl_priv *priv)
2021 {
2022         /* This will kick in the "brute force"
2023          * iwl3945_hw_reg_comp_txpower_temp() below */
2024         if (!is_temp_calib_needed(priv))
2025                 goto reschedule;
2026
2027         /* Set up a new set of temp-adjusted TxPowers, send to NIC.
2028          * This is based *only* on current temperature,
2029          * ignoring any previous power measurements */
2030         iwl3945_hw_reg_comp_txpower_temp(priv);
2031
2032  reschedule:
2033         queue_delayed_work(priv->workqueue,
2034                            &priv->thermal_periodic, REG_RECALIB_PERIOD * HZ);
2035 }
2036
2037 static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work)
2038 {
2039         struct iwl_priv *priv = container_of(work, struct iwl_priv,
2040                                              thermal_periodic.work);
2041
2042         if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2043                 return;
2044
2045         mutex_lock(&priv->mutex);
2046         iwl3945_reg_txpower_periodic(priv);
2047         mutex_unlock(&priv->mutex);
2048 }
2049
2050 /**
2051  * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4)
2052  *                                 for the channel.
2053  *
2054  * This function is used when initializing channel-info structs.
2055  *
2056  * NOTE: These channel groups do *NOT* match the bands above!
2057  *       These channel groups are based on factory-tested channels;
2058  *       on A-band, EEPROM's "group frequency" entries represent the top
2059  *       channel in each group 1-4.  Group 5 All B/G channels are in group 0.
2060  */
2061 static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv,
2062                                        const struct iwl_channel_info *ch_info)
2063 {
2064         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2065         struct iwl3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0];
2066         u8 group;
2067         u16 group_index = 0;    /* based on factory calib frequencies */
2068         u8 grp_channel;
2069
2070         /* Find the group index for the channel ... don't use index 1(?) */
2071         if (is_channel_a_band(ch_info)) {
2072                 for (group = 1; group < 5; group++) {
2073                         grp_channel = ch_grp[group].group_channel;
2074                         if (ch_info->channel <= grp_channel) {
2075                                 group_index = group;
2076                                 break;
2077                         }
2078                 }
2079                 /* group 4 has a few channels *above* its factory cal freq */
2080                 if (group == 5)
2081                         group_index = 4;
2082         } else
2083                 group_index = 0;        /* 2.4 GHz, group 0 */
2084
2085         IWL_DEBUG_POWER(priv, "Chnl %d mapped to grp %d\n", ch_info->channel,
2086                         group_index);
2087         return group_index;
2088 }
2089
2090 /**
2091  * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index
2092  *
2093  * Interpolate to get nominal (i.e. at factory calibration temperature) index
2094  *   into radio/DSP gain settings table for requested power.
2095  */
2096 static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv,
2097                                        s8 requested_power,
2098                                        s32 setting_index, s32 *new_index)
2099 {
2100         const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL;
2101         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2102         s32 index0, index1;
2103         s32 power = 2 * requested_power;
2104         s32 i;
2105         const struct iwl3945_eeprom_txpower_sample *samples;
2106         s32 gains0, gains1;
2107         s32 res;
2108         s32 denominator;
2109
2110         chnl_grp = &eeprom->groups[setting_index];
2111         samples = chnl_grp->samples;
2112         for (i = 0; i < 5; i++) {
2113                 if (power == samples[i].power) {
2114                         *new_index = samples[i].gain_index;
2115                         return 0;
2116                 }
2117         }
2118
2119         if (power > samples[1].power) {
2120                 index0 = 0;
2121                 index1 = 1;
2122         } else if (power > samples[2].power) {
2123                 index0 = 1;
2124                 index1 = 2;
2125         } else if (power > samples[3].power) {
2126                 index0 = 2;
2127                 index1 = 3;
2128         } else {
2129                 index0 = 3;
2130                 index1 = 4;
2131         }
2132
2133         denominator = (s32) samples[index1].power - (s32) samples[index0].power;
2134         if (denominator == 0)
2135                 return -EINVAL;
2136         gains0 = (s32) samples[index0].gain_index * (1 << 19);
2137         gains1 = (s32) samples[index1].gain_index * (1 << 19);
2138         res = gains0 + (gains1 - gains0) *
2139             ((s32) power - (s32) samples[index0].power) / denominator +
2140             (1 << 18);
2141         *new_index = res >> 19;
2142         return 0;
2143 }
2144
2145 static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv)
2146 {
2147         u32 i;
2148         s32 rate_index;
2149         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2150         const struct iwl3945_eeprom_txpower_group *group;
2151
2152         IWL_DEBUG_POWER(priv, "Initializing factory calib info from EEPROM\n");
2153
2154         for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) {
2155                 s8 *clip_pwrs;  /* table of power levels for each rate */
2156                 s8 satur_pwr;   /* saturation power for each chnl group */
2157                 group = &eeprom->groups[i];
2158
2159                 /* sanity check on factory saturation power value */
2160                 if (group->saturation_power < 40) {
2161                         IWL_WARN(priv, "Error: saturation power is %d, "
2162                                     "less than minimum expected 40\n",
2163                                     group->saturation_power);
2164                         return;
2165                 }
2166
2167                 /*
2168                  * Derive requested power levels for each rate, based on
2169                  *   hardware capabilities (saturation power for band).
2170                  * Basic value is 3dB down from saturation, with further
2171                  *   power reductions for highest 3 data rates.  These
2172                  *   backoffs provide headroom for high rate modulation
2173                  *   power peaks, without too much distortion (clipping).
2174                  */
2175                 /* we'll fill in this array with h/w max power levels */
2176                 clip_pwrs = (s8 *) priv->clip39_groups[i].clip_powers;
2177
2178                 /* divide factory saturation power by 2 to find -3dB level */
2179                 satur_pwr = (s8) (group->saturation_power >> 1);
2180
2181                 /* fill in channel group's nominal powers for each rate */
2182                 for (rate_index = 0;
2183                      rate_index < IWL_RATE_COUNT; rate_index++, clip_pwrs++) {
2184                         switch (rate_index) {
2185                         case IWL_RATE_36M_INDEX_TABLE:
2186                                 if (i == 0)     /* B/G */
2187                                         *clip_pwrs = satur_pwr;
2188                                 else    /* A */
2189                                         *clip_pwrs = satur_pwr - 5;
2190                                 break;
2191                         case IWL_RATE_48M_INDEX_TABLE:
2192                                 if (i == 0)
2193                                         *clip_pwrs = satur_pwr - 7;
2194                                 else
2195                                         *clip_pwrs = satur_pwr - 10;
2196                                 break;
2197                         case IWL_RATE_54M_INDEX_TABLE:
2198                                 if (i == 0)
2199                                         *clip_pwrs = satur_pwr - 9;
2200                                 else
2201                                         *clip_pwrs = satur_pwr - 12;
2202                                 break;
2203                         default:
2204                                 *clip_pwrs = satur_pwr;
2205                                 break;
2206                         }
2207                 }
2208         }
2209 }
2210
2211 /**
2212  * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM
2213  *
2214  * Second pass (during init) to set up priv->channel_info
2215  *
2216  * Set up Tx-power settings in our channel info database for each VALID
2217  * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values
2218  * and current temperature.
2219  *
2220  * Since this is based on current temperature (at init time), these values may
2221  * not be valid for very long, but it gives us a starting/default point,
2222  * and allows us to active (i.e. using Tx) scan.
2223  *
2224  * This does *not* write values to NIC, just sets up our internal table.
2225  */
2226 int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv)
2227 {
2228         struct iwl_channel_info *ch_info = NULL;
2229         struct iwl3945_channel_power_info *pwr_info;
2230         struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom;
2231         int delta_index;
2232         u8 rate_index;
2233         u8 scan_tbl_index;
2234         const s8 *clip_pwrs;    /* array of power levels for each rate */
2235         u8 gain, dsp_atten;
2236         s8 power;
2237         u8 pwr_index, base_pwr_index, a_band;
2238         u8 i;
2239         int temperature;
2240
2241         /* save temperature reference,
2242          *   so we can determine next time to calibrate */
2243         temperature = iwl3945_hw_reg_txpower_get_temperature(priv);
2244         priv->last_temperature = temperature;
2245
2246         iwl3945_hw_reg_init_channel_groups(priv);
2247
2248         /* initialize Tx power info for each and every channel, 2.4 and 5.x */
2249         for (i = 0, ch_info = priv->channel_info; i < priv->channel_count;
2250              i++, ch_info++) {
2251                 a_band = is_channel_a_band(ch_info);
2252                 if (!is_channel_valid(ch_info))
2253                         continue;
2254
2255                 /* find this channel's channel group (*not* "band") index */
2256                 ch_info->group_index =
2257                         iwl3945_hw_reg_get_ch_grp_index(priv, ch_info);
2258
2259                 /* Get this chnlgrp's rate->max/clip-powers table */
2260                 clip_pwrs = priv->clip39_groups[ch_info->group_index].clip_powers;
2261
2262                 /* calculate power index *adjustment* value according to
2263                  *  diff between current temperature and factory temperature */
2264                 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature,
2265                                 eeprom->groups[ch_info->group_index].
2266                                 temperature);
2267
2268                 IWL_DEBUG_POWER(priv, "Delta index for channel %d: %d [%d]\n",
2269                                 ch_info->channel, delta_index, temperature +
2270                                 IWL_TEMP_CONVERT);
2271
2272                 /* set tx power value for all OFDM rates */
2273                 for (rate_index = 0; rate_index < IWL_OFDM_RATES;
2274                      rate_index++) {
2275                         s32 uninitialized_var(power_idx);
2276                         int rc;
2277
2278                         /* use channel group's clip-power table,
2279                          *   but don't exceed channel's max power */
2280                         s8 pwr = min(ch_info->max_power_avg,
2281                                      clip_pwrs[rate_index]);
2282
2283                         pwr_info = &ch_info->power_info[rate_index];
2284
2285                         /* get base (i.e. at factory-measured temperature)
2286                          *    power table index for this rate's power */
2287                         rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr,
2288                                                          ch_info->group_index,
2289                                                          &power_idx);
2290                         if (rc) {
2291                                 IWL_ERR(priv, "Invalid power index\n");
2292                                 return rc;
2293                         }
2294                         pwr_info->base_power_index = (u8) power_idx;
2295
2296                         /* temperature compensate */
2297                         power_idx += delta_index;
2298
2299                         /* stay within range of gain table */
2300                         power_idx = iwl3945_hw_reg_fix_power_index(power_idx);
2301
2302                         /* fill 1 OFDM rate's iwl3945_channel_power_info struct */
2303                         pwr_info->requested_power = pwr;
2304                         pwr_info->power_table_index = (u8) power_idx;
2305                         pwr_info->tpc.tx_gain =
2306                             power_gain_table[a_band][power_idx].tx_gain;
2307                         pwr_info->tpc.dsp_atten =
2308                             power_gain_table[a_band][power_idx].dsp_atten;
2309                 }
2310
2311                 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/
2312                 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE];
2313                 power = pwr_info->requested_power +
2314                         IWL_CCK_FROM_OFDM_POWER_DIFF;
2315                 pwr_index = pwr_info->power_table_index +
2316                         IWL_CCK_FROM_OFDM_INDEX_DIFF;
2317                 base_pwr_index = pwr_info->base_power_index +
2318                         IWL_CCK_FROM_OFDM_INDEX_DIFF;
2319
2320                 /* stay within table range */
2321                 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index);
2322                 gain = power_gain_table[a_band][pwr_index].tx_gain;
2323                 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten;
2324
2325                 /* fill each CCK rate's iwl3945_channel_power_info structure
2326                  * NOTE:  All CCK-rate Txpwrs are the same for a given chnl!
2327                  * NOTE:  CCK rates start at end of OFDM rates! */
2328                 for (rate_index = 0;
2329                      rate_index < IWL_CCK_RATES; rate_index++) {
2330                         pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES];
2331                         pwr_info->requested_power = power;
2332                         pwr_info->power_table_index = pwr_index;
2333                         pwr_info->base_power_index = base_pwr_index;
2334                         pwr_info->tpc.tx_gain = gain;
2335                         pwr_info->tpc.dsp_atten = dsp_atten;
2336                 }
2337
2338                 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */
2339                 for (scan_tbl_index = 0;
2340                      scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) {
2341                         s32 actual_index = (scan_tbl_index == 0) ?
2342                                 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE;
2343                         iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index,
2344                                 actual_index, clip_pwrs, ch_info, a_band);
2345                 }
2346         }
2347
2348         return 0;
2349 }
2350
2351 int iwl3945_hw_rxq_stop(struct iwl_priv *priv)
2352 {
2353         int rc;
2354
2355         iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0);
2356         rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS,
2357                         FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
2358         if (rc < 0)
2359                 IWL_ERR(priv, "Can't stop Rx DMA.\n");
2360
2361         return 0;
2362 }
2363
2364 int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq)
2365 {
2366         int txq_id = txq->q.id;
2367
2368         struct iwl3945_shared *shared_data = priv->shared_virt;
2369
2370         shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr);
2371
2372         iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0);
2373         iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0);
2374
2375         iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id),
2376                 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT |
2377                 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF |
2378                 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD |
2379                 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL |
2380                 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE);
2381
2382         /* fake read to flush all prev. writes */
2383         iwl_read32(priv, FH39_TSSR_CBB_BASE);
2384
2385         return 0;
2386 }
2387
2388 /*
2389  * HCMD utils
2390  */
2391 static u16 iwl3945_get_hcmd_size(u8 cmd_id, u16 len)
2392 {
2393         switch (cmd_id) {
2394         case REPLY_RXON:
2395                 return sizeof(struct iwl3945_rxon_cmd);
2396         case POWER_TABLE_CMD:
2397                 return sizeof(struct iwl3945_powertable_cmd);
2398         default:
2399                 return len;
2400         }
2401 }
2402
2403
2404 static u16 iwl3945_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
2405 {
2406         struct iwl3945_addsta_cmd *addsta = (struct iwl3945_addsta_cmd *)data;
2407         addsta->mode = cmd->mode;
2408         memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify));
2409         memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo));
2410         addsta->station_flags = cmd->station_flags;
2411         addsta->station_flags_msk = cmd->station_flags_msk;
2412         addsta->tid_disable_tx = cpu_to_le16(0);
2413         addsta->rate_n_flags = cmd->rate_n_flags;
2414         addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid;
2415         addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid;
2416         addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn;
2417
2418         return (u16)sizeof(struct iwl3945_addsta_cmd);
2419 }
2420
2421
2422 /**
2423  * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table
2424  */
2425 int iwl3945_init_hw_rate_table(struct iwl_priv *priv)
2426 {
2427         int rc, i, index, prev_index;
2428         struct iwl3945_rate_scaling_cmd rate_cmd = {
2429                 .reserved = {0, 0, 0},
2430         };
2431         struct iwl3945_rate_scaling_info *table = rate_cmd.table;
2432
2433         for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) {
2434                 index = iwl3945_rates[i].table_rs_index;
2435
2436                 table[index].rate_n_flags =
2437                         iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0);
2438                 table[index].try_cnt = priv->retry_rate;
2439                 prev_index = iwl3945_get_prev_ieee_rate(i);
2440                 table[index].next_rate_index =
2441                                 iwl3945_rates[prev_index].table_rs_index;
2442         }
2443
2444         switch (priv->band) {
2445         case IEEE80211_BAND_5GHZ:
2446                 IWL_DEBUG_RATE(priv, "Select A mode rate scale\n");
2447                 /* If one of the following CCK rates is used,
2448                  * have it fall back to the 6M OFDM rate */
2449                 for (i = IWL_RATE_1M_INDEX_TABLE;
2450                         i <= IWL_RATE_11M_INDEX_TABLE; i++)
2451                         table[i].next_rate_index =
2452                           iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2453
2454                 /* Don't fall back to CCK rates */
2455                 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index =
2456                                                 IWL_RATE_9M_INDEX_TABLE;
2457
2458                 /* Don't drop out of OFDM rates */
2459                 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index =
2460                     iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index;
2461                 break;
2462
2463         case IEEE80211_BAND_2GHZ:
2464                 IWL_DEBUG_RATE(priv, "Select B/G mode rate scale\n");
2465                 /* If an OFDM rate is used, have it fall back to the
2466                  * 1M CCK rates */
2467
2468                 if (!(priv->sta_supp_rates & IWL_OFDM_RATES_MASK) &&
2469                     iwl_is_associated(priv)) {
2470
2471                         index = IWL_FIRST_CCK_RATE;
2472                         for (i = IWL_RATE_6M_INDEX_TABLE;
2473                              i <= IWL_RATE_54M_INDEX_TABLE; i++)
2474                                 table[i].next_rate_index =
2475                                         iwl3945_rates[index].table_rs_index;
2476
2477                         index = IWL_RATE_11M_INDEX_TABLE;
2478                         /* CCK shouldn't fall back to OFDM... */
2479                         table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE;
2480                 }
2481                 break;
2482
2483         default:
2484                 WARN_ON(1);
2485                 break;
2486         }
2487
2488         /* Update the rate scaling for control frame Tx */
2489         rate_cmd.table_id = 0;
2490         rc = iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2491                               &rate_cmd);
2492         if (rc)
2493                 return rc;
2494
2495         /* Update the rate scaling for data frame Tx */
2496         rate_cmd.table_id = 1;
2497         return iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd),
2498                                 &rate_cmd);
2499 }
2500
2501 /* Called when initializing driver */
2502 int iwl3945_hw_set_hw_params(struct iwl_priv *priv)
2503 {
2504         memset((void *)&priv->hw_params, 0,
2505                sizeof(struct iwl_hw_params));
2506
2507         priv->shared_virt =
2508             pci_alloc_consistent(priv->pci_dev,
2509                                  sizeof(struct iwl3945_shared),
2510                                  &priv->shared_phys);
2511
2512         if (!priv->shared_virt) {
2513                 IWL_ERR(priv, "failed to allocate pci memory\n");
2514                 mutex_unlock(&priv->mutex);
2515                 return -ENOMEM;
2516         }
2517
2518         /* Assign number of Usable TX queues */
2519         priv->hw_params.max_txq_num = IWL39_NUM_QUEUES;
2520
2521         priv->hw_params.tfd_size = sizeof(struct iwl3945_tfd);
2522         priv->hw_params.rx_buf_size = IWL_RX_BUF_SIZE_3K;
2523         priv->hw_params.max_pkt_size = 2342;
2524         priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
2525         priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
2526         priv->hw_params.max_stations = IWL3945_STATION_COUNT;
2527         priv->hw_params.bcast_sta_id = IWL3945_BROADCAST_ID;
2528
2529         priv->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR;
2530         priv->hw_params.max_beacon_itrvl = IWL39_MAX_UCODE_BEACON_INTERVAL;
2531
2532         return 0;
2533 }
2534
2535 unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv,
2536                           struct iwl3945_frame *frame, u8 rate)
2537 {
2538         struct iwl3945_tx_beacon_cmd *tx_beacon_cmd;
2539         unsigned int frame_size;
2540
2541         tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u;
2542         memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
2543
2544         tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
2545         tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
2546
2547         frame_size = iwl3945_fill_beacon_frame(priv,
2548                                 tx_beacon_cmd->frame,
2549                                 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
2550
2551         BUG_ON(frame_size > MAX_MPDU_SIZE);
2552         tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
2553
2554         tx_beacon_cmd->tx.rate = rate;
2555         tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
2556                                       TX_CMD_FLG_TSF_MSK);
2557
2558         /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/
2559         tx_beacon_cmd->tx.supp_rates[0] =
2560                 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF;
2561
2562         tx_beacon_cmd->tx.supp_rates[1] =
2563                 (IWL_CCK_BASIC_RATES_MASK & 0xF);
2564
2565         return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size;
2566 }
2567
2568 void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv)
2569 {
2570         priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx;
2571         priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx;
2572 }
2573
2574 void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv)
2575 {
2576         INIT_DELAYED_WORK(&priv->thermal_periodic,
2577                           iwl3945_bg_reg_txpower_periodic);
2578 }
2579
2580 void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv)
2581 {
2582         cancel_delayed_work(&priv->thermal_periodic);
2583 }
2584
2585 /* check contents of special bootstrap uCode SRAM */
2586 static int iwl3945_verify_bsm(struct iwl_priv *priv)
2587  {
2588         __le32 *image = priv->ucode_boot.v_addr;
2589         u32 len = priv->ucode_boot.len;
2590         u32 reg;
2591         u32 val;
2592
2593         IWL_DEBUG_INFO(priv, "Begin verify bsm\n");
2594
2595         /* verify BSM SRAM contents */
2596         val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
2597         for (reg = BSM_SRAM_LOWER_BOUND;
2598              reg < BSM_SRAM_LOWER_BOUND + len;
2599              reg += sizeof(u32), image++) {
2600                 val = iwl_read_prph(priv, reg);
2601                 if (val != le32_to_cpu(*image)) {
2602                         IWL_ERR(priv, "BSM uCode verification failed at "
2603                                   "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
2604                                   BSM_SRAM_LOWER_BOUND,
2605                                   reg - BSM_SRAM_LOWER_BOUND, len,
2606                                   val, le32_to_cpu(*image));
2607                         return -EIO;
2608                 }
2609         }
2610
2611         IWL_DEBUG_INFO(priv, "BSM bootstrap uCode image OK\n");
2612
2613         return 0;
2614 }
2615
2616
2617 /******************************************************************************
2618  *
2619  * EEPROM related functions
2620  *
2621  ******************************************************************************/
2622
2623 /*
2624  * Clear the OWNER_MSK, to establish driver (instead of uCode running on
2625  * embedded controller) as EEPROM reader; each read is a series of pulses
2626  * to/from the EEPROM chip, not a single event, so even reads could conflict
2627  * if they weren't arbitrated by some ownership mechanism.  Here, the driver
2628  * simply claims ownership, which should be safe when this function is called
2629  * (i.e. before loading uCode!).
2630  */
2631 static int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv)
2632 {
2633         _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK);
2634         return 0;
2635 }
2636
2637
2638 static void iwl3945_eeprom_release_semaphore(struct iwl_priv *priv)
2639 {
2640         return;
2641 }
2642
2643  /**
2644   * iwl3945_load_bsm - Load bootstrap instructions
2645   *
2646   * BSM operation:
2647   *
2648   * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program
2649   * in special SRAM that does not power down during RFKILL.  When powering back
2650   * up after power-saving sleeps (or during initial uCode load), the BSM loads
2651   * the bootstrap program into the on-board processor, and starts it.
2652   *
2653   * The bootstrap program loads (via DMA) instructions and data for a new
2654   * program from host DRAM locations indicated by the host driver in the
2655   * BSM_DRAM_* registers.  Once the new program is loaded, it starts
2656   * automatically.
2657   *
2658   * When initializing the NIC, the host driver points the BSM to the
2659   * "initialize" uCode image.  This uCode sets up some internal data, then
2660   * notifies host via "initialize alive" that it is complete.
2661   *
2662   * The host then replaces the BSM_DRAM_* pointer values to point to the
2663   * normal runtime uCode instructions and a backup uCode data cache buffer
2664   * (filled initially with starting data values for the on-board processor),
2665   * then triggers the "initialize" uCode to load and launch the runtime uCode,
2666   * which begins normal operation.
2667   *
2668   * When doing a power-save shutdown, runtime uCode saves data SRAM into
2669   * the backup data cache in DRAM before SRAM is powered down.
2670   *
2671   * When powering back up, the BSM loads the bootstrap program.  This reloads
2672   * the runtime uCode instructions and the backup data cache into SRAM,
2673   * and re-launches the runtime uCode from where it left off.
2674   */
2675 static int iwl3945_load_bsm(struct iwl_priv *priv)
2676 {
2677         __le32 *image = priv->ucode_boot.v_addr;
2678         u32 len = priv->ucode_boot.len;
2679         dma_addr_t pinst;
2680         dma_addr_t pdata;
2681         u32 inst_len;
2682         u32 data_len;
2683         int rc;
2684         int i;
2685         u32 done;
2686         u32 reg_offset;
2687
2688         IWL_DEBUG_INFO(priv, "Begin load bsm\n");
2689
2690         /* make sure bootstrap program is no larger than BSM's SRAM size */
2691         if (len > IWL39_MAX_BSM_SIZE)
2692                 return -EINVAL;
2693
2694         /* Tell bootstrap uCode where to find the "Initialize" uCode
2695         *   in host DRAM ... host DRAM physical address bits 31:0 for 3945.
2696         * NOTE:  iwl3945_initialize_alive_start() will replace these values,
2697         *        after the "initialize" uCode has run, to point to
2698         *        runtime/protocol instructions and backup data cache. */
2699         pinst = priv->ucode_init.p_addr;
2700         pdata = priv->ucode_init_data.p_addr;
2701         inst_len = priv->ucode_init.len;
2702         data_len = priv->ucode_init_data.len;
2703
2704         iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
2705         iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
2706         iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
2707         iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
2708
2709         /* Fill BSM memory with bootstrap instructions */
2710         for (reg_offset = BSM_SRAM_LOWER_BOUND;
2711              reg_offset < BSM_SRAM_LOWER_BOUND + len;
2712              reg_offset += sizeof(u32), image++)
2713                 _iwl_write_prph(priv, reg_offset,
2714                                           le32_to_cpu(*image));
2715
2716         rc = iwl3945_verify_bsm(priv);
2717         if (rc)
2718                 return rc;
2719
2720         /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
2721         iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
2722         iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
2723                                  IWL39_RTC_INST_LOWER_BOUND);
2724         iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
2725
2726         /* Load bootstrap code into instruction SRAM now,
2727          *   to prepare to load "initialize" uCode */
2728         iwl_write_prph(priv, BSM_WR_CTRL_REG,
2729                 BSM_WR_CTRL_REG_BIT_START);
2730
2731         /* Wait for load of bootstrap uCode to finish */
2732         for (i = 0; i < 100; i++) {
2733                 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
2734                 if (!(done & BSM_WR_CTRL_REG_BIT_START))
2735                         break;
2736                 udelay(10);
2737         }
2738         if (i < 100)
2739                 IWL_DEBUG_INFO(priv, "BSM write complete, poll %d iterations\n", i);
2740         else {
2741                 IWL_ERR(priv, "BSM write did not complete!\n");
2742                 return -EIO;
2743         }
2744
2745         /* Enable future boot loads whenever power management unit triggers it
2746          *   (e.g. when powering back up after power-save shutdown) */
2747         iwl_write_prph(priv, BSM_WR_CTRL_REG,
2748                 BSM_WR_CTRL_REG_BIT_START_EN);
2749
2750         return 0;
2751 }
2752
2753 #define IWL3945_UCODE_GET(item)                                         \
2754 static u32 iwl3945_ucode_get_##item(const struct iwl_ucode_header *ucode,\
2755                                     u32 api_ver)                        \
2756 {                                                                       \
2757         return le32_to_cpu(ucode->u.v1.item);                           \
2758 }
2759
2760 static u32 iwl3945_ucode_get_header_size(u32 api_ver)
2761 {
2762         return UCODE_HEADER_SIZE(1);
2763 }
2764 static u32 iwl3945_ucode_get_build(const struct iwl_ucode_header *ucode,
2765                                    u32 api_ver)
2766 {
2767         return 0;
2768 }
2769 static u8 *iwl3945_ucode_get_data(const struct iwl_ucode_header *ucode,
2770                                   u32 api_ver)
2771 {
2772         return (u8 *) ucode->u.v1.data;
2773 }
2774
2775 IWL3945_UCODE_GET(inst_size);
2776 IWL3945_UCODE_GET(data_size);
2777 IWL3945_UCODE_GET(init_size);
2778 IWL3945_UCODE_GET(init_data_size);
2779 IWL3945_UCODE_GET(boot_size);
2780
2781 static struct iwl_hcmd_ops iwl3945_hcmd = {
2782         .rxon_assoc = iwl3945_send_rxon_assoc,
2783         .commit_rxon = iwl3945_commit_rxon,
2784 };
2785
2786 static struct iwl_ucode_ops iwl3945_ucode = {
2787         .get_header_size = iwl3945_ucode_get_header_size,
2788         .get_build = iwl3945_ucode_get_build,
2789         .get_inst_size = iwl3945_ucode_get_inst_size,
2790         .get_data_size = iwl3945_ucode_get_data_size,
2791         .get_init_size = iwl3945_ucode_get_init_size,
2792         .get_init_data_size = iwl3945_ucode_get_init_data_size,
2793         .get_boot_size = iwl3945_ucode_get_boot_size,
2794         .get_data = iwl3945_ucode_get_data,
2795 };
2796
2797 static struct iwl_lib_ops iwl3945_lib = {
2798         .txq_attach_buf_to_tfd = iwl3945_hw_txq_attach_buf_to_tfd,
2799         .txq_free_tfd = iwl3945_hw_txq_free_tfd,
2800         .txq_init = iwl3945_hw_tx_queue_init,
2801         .load_ucode = iwl3945_load_bsm,
2802         .dump_nic_event_log = iwl3945_dump_nic_event_log,
2803         .dump_nic_error_log = iwl3945_dump_nic_error_log,
2804         .apm_ops = {
2805                 .init = iwl3945_apm_init,
2806                 .reset = iwl3945_apm_reset,
2807                 .stop = iwl_apm_stop,
2808                 .config = iwl3945_nic_config,
2809                 .set_pwr_src = iwl3945_set_pwr_src,
2810         },
2811         .eeprom_ops = {
2812                 .regulatory_bands = {
2813                         EEPROM_REGULATORY_BAND_1_CHANNELS,
2814                         EEPROM_REGULATORY_BAND_2_CHANNELS,
2815                         EEPROM_REGULATORY_BAND_3_CHANNELS,
2816                         EEPROM_REGULATORY_BAND_4_CHANNELS,
2817                         EEPROM_REGULATORY_BAND_5_CHANNELS,
2818                         EEPROM_REGULATORY_BAND_NO_HT40,
2819                         EEPROM_REGULATORY_BAND_NO_HT40,
2820                 },
2821                 .verify_signature  = iwlcore_eeprom_verify_signature,
2822                 .acquire_semaphore = iwl3945_eeprom_acquire_semaphore,
2823                 .release_semaphore = iwl3945_eeprom_release_semaphore,
2824                 .query_addr = iwlcore_eeprom_query_addr,
2825         },
2826         .send_tx_power  = iwl3945_send_tx_power,
2827         .is_valid_rtc_data_addr = iwl3945_hw_valid_rtc_data_addr,
2828         .post_associate = iwl3945_post_associate,
2829         .isr = iwl_isr_legacy,
2830         .config_ap = iwl3945_config_ap,
2831 };
2832
2833 static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = {
2834         .get_hcmd_size = iwl3945_get_hcmd_size,
2835         .build_addsta_hcmd = iwl3945_build_addsta_hcmd,
2836 };
2837
2838 static struct iwl_ops iwl3945_ops = {
2839         .ucode = &iwl3945_ucode,
2840         .lib = &iwl3945_lib,
2841         .hcmd = &iwl3945_hcmd,
2842         .utils = &iwl3945_hcmd_utils,
2843         .led = &iwl3945_led_ops,
2844 };
2845
2846 static struct iwl_cfg iwl3945_bg_cfg = {
2847         .name = "3945BG",
2848         .fw_name_pre = IWL3945_FW_PRE,
2849         .ucode_api_max = IWL3945_UCODE_API_MAX,
2850         .ucode_api_min = IWL3945_UCODE_API_MIN,
2851         .sku = IWL_SKU_G,
2852         .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2853         .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2854         .ops = &iwl3945_ops,
2855         .mod_params = &iwl3945_mod_params,
2856         .use_isr_legacy = true,
2857         .ht_greenfield_support = false,
2858         .led_compensation = 64,
2859 };
2860
2861 static struct iwl_cfg iwl3945_abg_cfg = {
2862         .name = "3945ABG",
2863         .fw_name_pre = IWL3945_FW_PRE,
2864         .ucode_api_max = IWL3945_UCODE_API_MAX,
2865         .ucode_api_min = IWL3945_UCODE_API_MIN,
2866         .sku = IWL_SKU_A|IWL_SKU_G,
2867         .eeprom_size = IWL3945_EEPROM_IMG_SIZE,
2868         .eeprom_ver = EEPROM_3945_EEPROM_VERSION,
2869         .ops = &iwl3945_ops,
2870         .mod_params = &iwl3945_mod_params,
2871         .use_isr_legacy = true,
2872         .ht_greenfield_support = false,
2873         .led_compensation = 64,
2874 };
2875
2876 struct pci_device_id iwl3945_hw_card_ids[] = {
2877         {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)},
2878         {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)},
2879         {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)},
2880         {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)},
2881         {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)},
2882         {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)},
2883         {0}
2884 };
2885
2886 MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids);