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   1 /*
   2  *
   3  *  Broadcom B43legacy wireless driver
   4  *
   5  *  Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
   6  *  Copyright (c) 2005-2008 Stefano Brivio <stefano.brivio@polimi.it>
   7  *  Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
   8  *  Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
   9  *  Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
  10  *  Copyright (c) 2007 Larry Finger <Larry.Finger@lwfinger.net>
  11  *
  12  *  Some parts of the code in this file are derived from the ipw2200
  13  *  driver  Copyright(c) 2003 - 2004 Intel Corporation.
  14
  15  *  This program is free software; you can redistribute it and/or modify
  16  *  it under the terms of the GNU General Public License as published by
  17  *  the Free Software Foundation; either version 2 of the License, or
  18  *  (at your option) any later version.
  19  *
  20  *  This program is distributed in the hope that it will be useful,
  21  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  *  GNU General Public License for more details.
  24  *
  25  *  You should have received a copy of the GNU General Public License
  26  *  along with this program; see the file COPYING.  If not, write to
  27  *  the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  28  *  Boston, MA 02110-1301, USA.
  29  *
  30  */
  31
  32 #include <linux/delay.h>
  33 #include <linux/init.h>
  34 #include <linux/moduleparam.h>
  35 #include <linux/if_arp.h>
  36 #include <linux/etherdevice.h>
  37 #include <linux/firmware.h>
  38 #include <linux/wireless.h>
  39 #include <linux/workqueue.h>
  40 #include <linux/sched.h>
  41 #include <linux/skbuff.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/slab.h>
  44 #include <net/dst.h>
  45 #include <asm/unaligned.h>
  46
  47 #include "b43legacy.h"
  48 #include "main.h"
  49 #include "debugfs.h"
  50 #include "phy.h"
  51 #include "dma.h"
  52 #include "pio.h"
  53 #include "sysfs.h"
  54 #include "xmit.h"
  55 #include "radio.h"
  56
  57
  58 MODULE_DESCRIPTION("Broadcom B43legacy wireless driver");
  59 MODULE_AUTHOR("Martin Langer");
  60 MODULE_AUTHOR("Stefano Brivio");
  61 MODULE_AUTHOR("Michael Buesch");
  62 MODULE_LICENSE("GPL");
  63
  64 MODULE_FIRMWARE(B43legacy_SUPPORTED_FIRMWARE_ID);
  65 MODULE_FIRMWARE("b43legacy/ucode2.fw");
  66 MODULE_FIRMWARE("b43legacy/ucode4.fw");
  67
  68 #if defined(CONFIG_B43LEGACY_DMA) && defined(CONFIG_B43LEGACY_PIO)
  69 static int modparam_pio;
  70 module_param_named(pio, modparam_pio, int, 0444);
  71 MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
  72 #elif defined(CONFIG_B43LEGACY_DMA)
  73 # define modparam_pio   0
  74 #elif defined(CONFIG_B43LEGACY_PIO)
  75 # define modparam_pio   1
  76 #endif
  77
  78 static int modparam_bad_frames_preempt;
  79 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
  80 MODULE_PARM_DESC(bad_frames_preempt, "enable(1) / disable(0) Bad Frames"
  81                  " Preemption");
  82
  83 static char modparam_fwpostfix[16];
  84 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
  85 MODULE_PARM_DESC(fwpostfix, "Postfix for the firmware files to load.");
  86
  87 /* The following table supports BCM4301, BCM4303 and BCM4306/2 devices. */
  88 static const struct ssb_device_id b43legacy_ssb_tbl[] = {
  89         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 2),
  90         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 4),
  91         SSB_DEVTABLE_END
  92 };
  93 MODULE_DEVICE_TABLE(ssb, b43legacy_ssb_tbl);
  94
  95
  96 /* Channel and ratetables are shared for all devices.
  97  * They can't be const, because ieee80211 puts some precalculated
  98  * data in there. This data is the same for all devices, so we don't
  99  * get concurrency issues */
 100 #define RATETAB_ENT(_rateid, _flags) \
 101         {                                                               \
 102                 .bitrate        = B43legacy_RATE_TO_100KBPS(_rateid),   \
 103                 .hw_value       = (_rateid),                            \
 104                 .flags          = (_flags),                             \
 105         }
 106 /*
 107  * NOTE: When changing this, sync with xmit.c's
 108  *       b43legacy_plcp_get_bitrate_idx_* functions!
 109  */
 110 static struct ieee80211_rate __b43legacy_ratetable[] = {
 111         RATETAB_ENT(B43legacy_CCK_RATE_1MB, 0),
 112         RATETAB_ENT(B43legacy_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
 113         RATETAB_ENT(B43legacy_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
 114         RATETAB_ENT(B43legacy_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
 115         RATETAB_ENT(B43legacy_OFDM_RATE_6MB, 0),
 116         RATETAB_ENT(B43legacy_OFDM_RATE_9MB, 0),
 117         RATETAB_ENT(B43legacy_OFDM_RATE_12MB, 0),
 118         RATETAB_ENT(B43legacy_OFDM_RATE_18MB, 0),
 119         RATETAB_ENT(B43legacy_OFDM_RATE_24MB, 0),
 120         RATETAB_ENT(B43legacy_OFDM_RATE_36MB, 0),
 121         RATETAB_ENT(B43legacy_OFDM_RATE_48MB, 0),
 122         RATETAB_ENT(B43legacy_OFDM_RATE_54MB, 0),
 123 };
 124 #define b43legacy_b_ratetable           (__b43legacy_ratetable + 0)
 125 #define b43legacy_b_ratetable_size      4
 126 #define b43legacy_g_ratetable           (__b43legacy_ratetable + 0)
 127 #define b43legacy_g_ratetable_size      12
 128
 129 #define CHANTAB_ENT(_chanid, _freq) \
 130         {                                                       \
 131                 .center_freq    = (_freq),                      \
 132                 .hw_value       = (_chanid),                    \
 133         }
 134 static struct ieee80211_channel b43legacy_bg_chantable[] = {
 135         CHANTAB_ENT(1, 2412),
 136         CHANTAB_ENT(2, 2417),
 137         CHANTAB_ENT(3, 2422),
 138         CHANTAB_ENT(4, 2427),
 139         CHANTAB_ENT(5, 2432),
 140         CHANTAB_ENT(6, 2437),
 141         CHANTAB_ENT(7, 2442),
 142         CHANTAB_ENT(8, 2447),
 143         CHANTAB_ENT(9, 2452),
 144         CHANTAB_ENT(10, 2457),
 145         CHANTAB_ENT(11, 2462),
 146         CHANTAB_ENT(12, 2467),
 147         CHANTAB_ENT(13, 2472),
 148         CHANTAB_ENT(14, 2484),
 149 };
 150
 151 static struct ieee80211_supported_band b43legacy_band_2GHz_BPHY = {
 152         .channels = b43legacy_bg_chantable,
 153         .n_channels = ARRAY_SIZE(b43legacy_bg_chantable),
 154         .bitrates = b43legacy_b_ratetable,
 155         .n_bitrates = b43legacy_b_ratetable_size,
 156 };
 157
 158 static struct ieee80211_supported_band b43legacy_band_2GHz_GPHY = {
 159         .channels = b43legacy_bg_chantable,
 160         .n_channels = ARRAY_SIZE(b43legacy_bg_chantable),
 161         .bitrates = b43legacy_g_ratetable,
 162         .n_bitrates = b43legacy_g_ratetable_size,
 163 };
 164
 165 static void b43legacy_wireless_core_exit(struct b43legacy_wldev *dev);
 166 static int b43legacy_wireless_core_init(struct b43legacy_wldev *dev);
 167 static void b43legacy_wireless_core_stop(struct b43legacy_wldev *dev);
 168 static int b43legacy_wireless_core_start(struct b43legacy_wldev *dev);
 169
 170
 171 static int b43legacy_ratelimit(struct b43legacy_wl *wl)
 172 {
 173         if (!wl || !wl->current_dev)
 174                 return 1;
 175         if (b43legacy_status(wl->current_dev) < B43legacy_STAT_STARTED)
 176                 return 1;
 177         /* We are up and running.
 178          * Ratelimit the messages to avoid DoS over the net. */
 179         return net_ratelimit();
 180 }
 181
 182 void b43legacyinfo(struct b43legacy_wl *wl, const char *fmt, ...)
 183 {
 184         va_list args;
 185
 186         if (!b43legacy_ratelimit(wl))
 187                 return;
 188         va_start(args, fmt);
 189         printk(KERN_INFO "b43legacy-%s: ",
 190                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
 191         vprintk(fmt, args);
 192         va_end(args);
 193 }
 194
 195 void b43legacyerr(struct b43legacy_wl *wl, const char *fmt, ...)
 196 {
 197         va_list args;
 198
 199         if (!b43legacy_ratelimit(wl))
 200                 return;
 201         va_start(args, fmt);
 202         printk(KERN_ERR "b43legacy-%s ERROR: ",
 203                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
 204         vprintk(fmt, args);
 205         va_end(args);
 206 }
 207
 208 void b43legacywarn(struct b43legacy_wl *wl, const char *fmt, ...)
 209 {
 210         va_list args;
 211
 212         if (!b43legacy_ratelimit(wl))
 213                 return;
 214         va_start(args, fmt);
 215         printk(KERN_WARNING "b43legacy-%s warning: ",
 216                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
 217         vprintk(fmt, args);
 218         va_end(args);
 219 }
 220
 221 #if B43legacy_DEBUG
 222 void b43legacydbg(struct b43legacy_wl *wl, const char *fmt, ...)
 223 {
 224         va_list args;
 225
 226         va_start(args, fmt);
 227         printk(KERN_DEBUG "b43legacy-%s debug: ",
 228                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
 229         vprintk(fmt, args);
 230         va_end(args);
 231 }
 232 #endif /* DEBUG */
 233
 234 static void b43legacy_ram_write(struct b43legacy_wldev *dev, u16 offset,
 235                                 u32 val)
 236 {
 237         u32 status;
 238
 239         B43legacy_WARN_ON(offset % 4 != 0);
 240
 241         status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
 242         if (status & B43legacy_MACCTL_BE)
 243                 val = swab32(val);
 244
 245         b43legacy_write32(dev, B43legacy_MMIO_RAM_CONTROL, offset);
 246         mmiowb();
 247         b43legacy_write32(dev, B43legacy_MMIO_RAM_DATA, val);
 248 }
 249
 250 static inline
 251 void b43legacy_shm_control_word(struct b43legacy_wldev *dev,
 252                                 u16 routing, u16 offset)
 253 {
 254         u32 control;
 255
 256         /* "offset" is the WORD offset. */
 257
 258         control = routing;
 259         control <<= 16;
 260         control |= offset;
 261         b43legacy_write32(dev, B43legacy_MMIO_SHM_CONTROL, control);
 262 }
 263
 264 u32 b43legacy_shm_read32(struct b43legacy_wldev *dev,
 265                        u16 routing, u16 offset)
 266 {
 267         u32 ret;
 268
 269         if (routing == B43legacy_SHM_SHARED) {
 270                 B43legacy_WARN_ON((offset & 0x0001) != 0);
 271                 if (offset & 0x0003) {
 272                         /* Unaligned access */
 273                         b43legacy_shm_control_word(dev, routing, offset >> 2);
 274                         ret = b43legacy_read16(dev,
 275                                 B43legacy_MMIO_SHM_DATA_UNALIGNED);
 276                         ret <<= 16;
 277                         b43legacy_shm_control_word(dev, routing,
 278                                                      (offset >> 2) + 1);
 279                         ret |= b43legacy_read16(dev, B43legacy_MMIO_SHM_DATA);
 280
 281                         return ret;
 282                 }
 283                 offset >>= 2;
 284         }
 285         b43legacy_shm_control_word(dev, routing, offset);
 286         ret = b43legacy_read32(dev, B43legacy_MMIO_SHM_DATA);
 287
 288         return ret;
 289 }
 290
 291 u16 b43legacy_shm_read16(struct b43legacy_wldev *dev,
 292                            u16 routing, u16 offset)
 293 {
 294         u16 ret;
 295
 296         if (routing == B43legacy_SHM_SHARED) {
 297                 B43legacy_WARN_ON((offset & 0x0001) != 0);
 298                 if (offset & 0x0003) {
 299                         /* Unaligned access */
 300                         b43legacy_shm_control_word(dev, routing, offset >> 2);
 301                         ret = b43legacy_read16(dev,
 302                                              B43legacy_MMIO_SHM_DATA_UNALIGNED);
 303
 304                         return ret;
 305                 }
 306                 offset >>= 2;
 307         }
 308         b43legacy_shm_control_word(dev, routing, offset);
 309         ret = b43legacy_read16(dev, B43legacy_MMIO_SHM_DATA);
 310
 311         return ret;
 312 }
 313
 314 void b43legacy_shm_write32(struct b43legacy_wldev *dev,
 315                            u16 routing, u16 offset,
 316                            u32 value)
 317 {
 318         if (routing == B43legacy_SHM_SHARED) {
 319                 B43legacy_WARN_ON((offset & 0x0001) != 0);
 320                 if (offset & 0x0003) {
 321                         /* Unaligned access */
 322                         b43legacy_shm_control_word(dev, routing, offset >> 2);
 323                         mmiowb();
 324                         b43legacy_write16(dev,
 325                                           B43legacy_MMIO_SHM_DATA_UNALIGNED,
 326                                           (value >> 16) & 0xffff);
 327                         mmiowb();
 328                         b43legacy_shm_control_word(dev, routing,
 329                                                    (offset >> 2) + 1);
 330                         mmiowb();
 331                         b43legacy_write16(dev, B43legacy_MMIO_SHM_DATA,
 332                                           value & 0xffff);
 333                         return;
 334                 }
 335                 offset >>= 2;
 336         }
 337         b43legacy_shm_control_word(dev, routing, offset);
 338         mmiowb();
 339         b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA, value);
 340 }
 341
 342 void b43legacy_shm_write16(struct b43legacy_wldev *dev, u16 routing, u16 offset,
 343                            u16 value)
 344 {
 345         if (routing == B43legacy_SHM_SHARED) {
 346                 B43legacy_WARN_ON((offset & 0x0001) != 0);
 347                 if (offset & 0x0003) {
 348                         /* Unaligned access */
 349                         b43legacy_shm_control_word(dev, routing, offset >> 2);
 350                         mmiowb();
 351                         b43legacy_write16(dev,
 352                                           B43legacy_MMIO_SHM_DATA_UNALIGNED,
 353                                           value);
 354                         return;
 355                 }
 356                 offset >>= 2;
 357         }
 358         b43legacy_shm_control_word(dev, routing, offset);
 359         mmiowb();
 360         b43legacy_write16(dev, B43legacy_MMIO_SHM_DATA, value);
 361 }
 362
 363 /* Read HostFlags */
 364 u32 b43legacy_hf_read(struct b43legacy_wldev *dev)
 365 {
 366         u32 ret;
 367
 368         ret = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
 369                                    B43legacy_SHM_SH_HOSTFHI);
 370         ret <<= 16;
 371         ret |= b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
 372                                     B43legacy_SHM_SH_HOSTFLO);
 373
 374         return ret;
 375 }
 376
 377 /* Write HostFlags */
 378 void b43legacy_hf_write(struct b43legacy_wldev *dev, u32 value)
 379 {
 380         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
 381                               B43legacy_SHM_SH_HOSTFLO,
 382                               (value & 0x0000FFFF));
 383         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
 384                               B43legacy_SHM_SH_HOSTFHI,
 385                               ((value & 0xFFFF0000) >> 16));
 386 }
 387
 388 void b43legacy_tsf_read(struct b43legacy_wldev *dev, u64 *tsf)
 389 {
 390         /* We need to be careful. As we read the TSF from multiple
 391          * registers, we should take care of register overflows.
 392          * In theory, the whole tsf read process should be atomic.
 393          * We try to be atomic here, by restaring the read process,
 394          * if any of the high registers changed (overflew).
 395          */
 396         if (dev->dev->id.revision >= 3) {
 397                 u32 low;
 398                 u32 high;
 399                 u32 high2;
 400
 401                 do {
 402                         high = b43legacy_read32(dev,
 403                                         B43legacy_MMIO_REV3PLUS_TSF_HIGH);
 404                         low = b43legacy_read32(dev,
 405                                         B43legacy_MMIO_REV3PLUS_TSF_LOW);
 406                         high2 = b43legacy_read32(dev,
 407                                         B43legacy_MMIO_REV3PLUS_TSF_HIGH);
 408                 } while (unlikely(high != high2));
 409
 410                 *tsf = high;
 411                 *tsf <<= 32;
 412                 *tsf |= low;
 413         } else {
 414                 u64 tmp;
 415                 u16 v0;
 416                 u16 v1;
 417                 u16 v2;
 418                 u16 v3;
 419                 u16 test1;
 420                 u16 test2;
 421                 u16 test3;
 422
 423                 do {
 424                         v3 = b43legacy_read16(dev, B43legacy_MMIO_TSF_3);
 425                         v2 = b43legacy_read16(dev, B43legacy_MMIO_TSF_2);
 426                         v1 = b43legacy_read16(dev, B43legacy_MMIO_TSF_1);
 427                         v0 = b43legacy_read16(dev, B43legacy_MMIO_TSF_0);
 428
 429                         test3 = b43legacy_read16(dev, B43legacy_MMIO_TSF_3);
 430                         test2 = b43legacy_read16(dev, B43legacy_MMIO_TSF_2);
 431                         test1 = b43legacy_read16(dev, B43legacy_MMIO_TSF_1);
 432                 } while (v3 != test3 || v2 != test2 || v1 != test1);
 433
 434                 *tsf = v3;
 435                 *tsf <<= 48;
 436                 tmp = v2;
 437                 tmp <<= 32;
 438                 *tsf |= tmp;
 439                 tmp = v1;
 440                 tmp <<= 16;
 441                 *tsf |= tmp;
 442                 *tsf |= v0;
 443         }
 444 }
 445
 446 static void b43legacy_time_lock(struct b43legacy_wldev *dev)
 447 {
 448         u32 status;
 449
 450         status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
 451         status |= B43legacy_MACCTL_TBTTHOLD;
 452         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, status);
 453         mmiowb();
 454 }
 455
 456 static void b43legacy_time_unlock(struct b43legacy_wldev *dev)
 457 {
 458         u32 status;
 459
 460         status = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
 461         status &= ~B43legacy_MACCTL_TBTTHOLD;
 462         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, status);
 463 }
 464
 465 static void b43legacy_tsf_write_locked(struct b43legacy_wldev *dev, u64 tsf)
 466 {
 467         /* Be careful with the in-progress timer.
 468          * First zero out the low register, so we have a full
 469          * register-overflow duration to complete the operation.
 470          */
 471         if (dev->dev->id.revision >= 3) {
 472                 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
 473                 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
 474
 475                 b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_LOW, 0);
 476                 mmiowb();
 477                 b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_HIGH,
 478                                     hi);
 479                 mmiowb();
 480                 b43legacy_write32(dev, B43legacy_MMIO_REV3PLUS_TSF_LOW,
 481                                     lo);
 482         } else {
 483                 u16 v0 = (tsf & 0x000000000000FFFFULL);
 484                 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
 485                 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
 486                 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
 487
 488                 b43legacy_write16(dev, B43legacy_MMIO_TSF_0, 0);
 489                 mmiowb();
 490                 b43legacy_write16(dev, B43legacy_MMIO_TSF_3, v3);
 491                 mmiowb();
 492                 b43legacy_write16(dev, B43legacy_MMIO_TSF_2, v2);
 493                 mmiowb();
 494                 b43legacy_write16(dev, B43legacy_MMIO_TSF_1, v1);
 495                 mmiowb();
 496                 b43legacy_write16(dev, B43legacy_MMIO_TSF_0, v0);
 497         }
 498 }
 499
 500 void b43legacy_tsf_write(struct b43legacy_wldev *dev, u64 tsf)
 501 {
 502         b43legacy_time_lock(dev);
 503         b43legacy_tsf_write_locked(dev, tsf);
 504         b43legacy_time_unlock(dev);
 505 }
 506
 507 static
 508 void b43legacy_macfilter_set(struct b43legacy_wldev *dev,
 509                              u16 offset, const u8 *mac)
 510 {
 511         static const u8 zero_addr[ETH_ALEN] = { 0 };
 512         u16 data;
 513
 514         if (!mac)
 515                 mac = zero_addr;
 516
 517         offset |= 0x0020;
 518         b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_CONTROL, offset);
 519
 520         data = mac[0];
 521         data |= mac[1] << 8;
 522         b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
 523         data = mac[2];
 524         data |= mac[3] << 8;
 525         b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
 526         data = mac[4];
 527         data |= mac[5] << 8;
 528         b43legacy_write16(dev, B43legacy_MMIO_MACFILTER_DATA, data);
 529 }
 530
 531 static void b43legacy_write_mac_bssid_templates(struct b43legacy_wldev *dev)
 532 {
 533         static const u8 zero_addr[ETH_ALEN] = { 0 };
 534         const u8 *mac = dev->wl->mac_addr;
 535         const u8 *bssid = dev->wl->bssid;
 536         u8 mac_bssid[ETH_ALEN * 2];
 537         int i;
 538         u32 tmp;
 539
 540         if (!bssid)
 541                 bssid = zero_addr;
 542         if (!mac)
 543                 mac = zero_addr;
 544
 545         b43legacy_macfilter_set(dev, B43legacy_MACFILTER_BSSID, bssid);
 546
 547         memcpy(mac_bssid, mac, ETH_ALEN);
 548         memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
 549
 550         /* Write our MAC address and BSSID to template ram */
 551         for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
 552                 tmp =  (u32)(mac_bssid[i + 0]);
 553                 tmp |= (u32)(mac_bssid[i + 1]) << 8;
 554                 tmp |= (u32)(mac_bssid[i + 2]) << 16;
 555                 tmp |= (u32)(mac_bssid[i + 3]) << 24;
 556                 b43legacy_ram_write(dev, 0x20 + i, tmp);
 557                 b43legacy_ram_write(dev, 0x78 + i, tmp);
 558                 b43legacy_ram_write(dev, 0x478 + i, tmp);
 559         }
 560 }
 561
 562 static void b43legacy_upload_card_macaddress(struct b43legacy_wldev *dev)
 563 {
 564         b43legacy_write_mac_bssid_templates(dev);
 565         b43legacy_macfilter_set(dev, B43legacy_MACFILTER_SELF,
 566                                 dev->wl->mac_addr);
 567 }
 568
 569 static void b43legacy_set_slot_time(struct b43legacy_wldev *dev,
 570                                     u16 slot_time)
 571 {
 572         /* slot_time is in usec. */
 573         if (dev->phy.type != B43legacy_PHYTYPE_G)
 574                 return;
 575         b43legacy_write16(dev, 0x684, 510 + slot_time);
 576         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0010,
 577                               slot_time);
 578 }
 579
 580 static void b43legacy_short_slot_timing_enable(struct b43legacy_wldev *dev)
 581 {
 582         b43legacy_set_slot_time(dev, 9);
 583 }
 584
 585 static void b43legacy_short_slot_timing_disable(struct b43legacy_wldev *dev)
 586 {
 587         b43legacy_set_slot_time(dev, 20);
 588 }
 589
 590 /* Synchronize IRQ top- and bottom-half.
 591  * IRQs must be masked before calling this.
 592  * This must not be called with the irq_lock held.
 593  */
 594 static void b43legacy_synchronize_irq(struct b43legacy_wldev *dev)
 595 {
 596         synchronize_irq(dev->dev->irq);
 597         tasklet_kill(&dev->isr_tasklet);
 598 }
 599
 600 /* DummyTransmission function, as documented on
 601  * http://bcm-specs.sipsolutions.net/DummyTransmission
 602  */
 603 void b43legacy_dummy_transmission(struct b43legacy_wldev *dev)
 604 {
 605         struct b43legacy_phy *phy = &dev->phy;
 606         unsigned int i;
 607         unsigned int max_loop;
 608         u16 value;
 609         u32 buffer[5] = {
 610                 0x00000000,
 611                 0x00D40000,
 612                 0x00000000,
 613                 0x01000000,
 614                 0x00000000,
 615         };
 616
 617         switch (phy->type) {
 618         case B43legacy_PHYTYPE_B:
 619         case B43legacy_PHYTYPE_G:
 620                 max_loop = 0xFA;
 621                 buffer[0] = 0x000B846E;
 622                 break;
 623         default:
 624                 B43legacy_BUG_ON(1);
 625                 return;
 626         }
 627
 628         for (i = 0; i < 5; i++)
 629                 b43legacy_ram_write(dev, i * 4, buffer[i]);
 630
 631         /* dummy read follows */
 632         b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
 633
 634         b43legacy_write16(dev, 0x0568, 0x0000);
 635         b43legacy_write16(dev, 0x07C0, 0x0000);
 636         b43legacy_write16(dev, 0x050C, 0x0000);
 637         b43legacy_write16(dev, 0x0508, 0x0000);
 638         b43legacy_write16(dev, 0x050A, 0x0000);
 639         b43legacy_write16(dev, 0x054C, 0x0000);
 640         b43legacy_write16(dev, 0x056A, 0x0014);
 641         b43legacy_write16(dev, 0x0568, 0x0826);
 642         b43legacy_write16(dev, 0x0500, 0x0000);
 643         b43legacy_write16(dev, 0x0502, 0x0030);
 644
 645         if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
 646                 b43legacy_radio_write16(dev, 0x0051, 0x0017);
 647         for (i = 0x00; i < max_loop; i++) {
 648                 value = b43legacy_read16(dev, 0x050E);
 649                 if (value & 0x0080)
 650                         break;
 651                 udelay(10);
 652         }
 653         for (i = 0x00; i < 0x0A; i++) {
 654                 value = b43legacy_read16(dev, 0x050E);
 655                 if (value & 0x0400)
 656                         break;
 657                 udelay(10);
 658         }
 659         for (i = 0x00; i < 0x0A; i++) {
 660                 value = b43legacy_read16(dev, 0x0690);
 661                 if (!(value & 0x0100))
 662                         break;
 663                 udelay(10);
 664         }
 665         if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
 666                 b43legacy_radio_write16(dev, 0x0051, 0x0037);
 667 }
 668
 669 /* Turn the Analog ON/OFF */
 670 static void b43legacy_switch_analog(struct b43legacy_wldev *dev, int on)
 671 {
 672         b43legacy_write16(dev, B43legacy_MMIO_PHY0, on ? 0 : 0xF4);
 673 }
 674
 675 void b43legacy_wireless_core_reset(struct b43legacy_wldev *dev, u32 flags)
 676 {
 677         u32 tmslow;
 678         u32 macctl;
 679
 680         flags |= B43legacy_TMSLOW_PHYCLKEN;
 681         flags |= B43legacy_TMSLOW_PHYRESET;
 682         ssb_device_enable(dev->dev, flags);
 683         msleep(2); /* Wait for the PLL to turn on. */
 684
 685         /* Now take the PHY out of Reset again */
 686         tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
 687         tmslow |= SSB_TMSLOW_FGC;
 688         tmslow &= ~B43legacy_TMSLOW_PHYRESET;
 689         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
 690         ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
 691         msleep(1);
 692         tmslow &= ~SSB_TMSLOW_FGC;
 693         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
 694         ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
 695         msleep(1);
 696
 697         /* Turn Analog ON */
 698         b43legacy_switch_analog(dev, 1);
 699
 700         macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
 701         macctl &= ~B43legacy_MACCTL_GMODE;
 702         if (flags & B43legacy_TMSLOW_GMODE) {
 703                 macctl |= B43legacy_MACCTL_GMODE;
 704                 dev->phy.gmode = 1;
 705         } else
 706                 dev->phy.gmode = 0;
 707         macctl |= B43legacy_MACCTL_IHR_ENABLED;
 708         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
 709 }
 710
 711 static void handle_irq_transmit_status(struct b43legacy_wldev *dev)
 712 {
 713         u32 v0;
 714         u32 v1;
 715         u16 tmp;
 716         struct b43legacy_txstatus stat;
 717
 718         while (1) {
 719                 v0 = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_0);
 720                 if (!(v0 & 0x00000001))
 721                         break;
 722                 v1 = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_1);
 723
 724                 stat.cookie = (v0 >> 16);
 725                 stat.seq = (v1 & 0x0000FFFF);
 726                 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
 727                 tmp = (v0 & 0x0000FFFF);
 728                 stat.frame_count = ((tmp & 0xF000) >> 12);
 729                 stat.rts_count = ((tmp & 0x0F00) >> 8);
 730                 stat.supp_reason = ((tmp & 0x001C) >> 2);
 731                 stat.pm_indicated = !!(tmp & 0x0080);
 732                 stat.intermediate = !!(tmp & 0x0040);
 733                 stat.for_ampdu = !!(tmp & 0x0020);
 734                 stat.acked = !!(tmp & 0x0002);
 735
 736                 b43legacy_handle_txstatus(dev, &stat);
 737         }
 738 }
 739
 740 static void drain_txstatus_queue(struct b43legacy_wldev *dev)
 741 {
 742         u32 dummy;
 743
 744         if (dev->dev->id.revision < 5)
 745                 return;
 746         /* Read all entries from the microcode TXstatus FIFO
 747          * and throw them away.
 748          */
 749         while (1) {
 750                 dummy = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_0);
 751                 if (!(dummy & 0x00000001))
 752                         break;
 753                 dummy = b43legacy_read32(dev, B43legacy_MMIO_XMITSTAT_1);
 754         }
 755 }
 756
 757 static u32 b43legacy_jssi_read(struct b43legacy_wldev *dev)
 758 {
 759         u32 val = 0;
 760
 761         val = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x40A);
 762         val <<= 16;
 763         val |= b43legacy_shm_read16(dev, B43legacy_SHM_SHARED, 0x408);
 764
 765         return val;
 766 }
 767
 768 static void b43legacy_jssi_write(struct b43legacy_wldev *dev, u32 jssi)
 769 {
 770         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x408,
 771                               (jssi & 0x0000FFFF));
 772         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x40A,
 773                               (jssi & 0xFFFF0000) >> 16);
 774 }
 775
 776 static void b43legacy_generate_noise_sample(struct b43legacy_wldev *dev)
 777 {
 778         b43legacy_jssi_write(dev, 0x7F7F7F7F);
 779         b43legacy_write32(dev, B43legacy_MMIO_MACCMD,
 780                           b43legacy_read32(dev, B43legacy_MMIO_MACCMD)
 781                           | B43legacy_MACCMD_BGNOISE);
 782         B43legacy_WARN_ON(dev->noisecalc.channel_at_start !=
 783                             dev->phy.channel);
 784 }
 785
 786 static void b43legacy_calculate_link_quality(struct b43legacy_wldev *dev)
 787 {
 788         /* Top half of Link Quality calculation. */
 789
 790         if (dev->noisecalc.calculation_running)
 791                 return;
 792         dev->noisecalc.channel_at_start = dev->phy.channel;
 793         dev->noisecalc.calculation_running = 1;
 794         dev->noisecalc.nr_samples = 0;
 795
 796         b43legacy_generate_noise_sample(dev);
 797 }
 798
 799 static void handle_irq_noise(struct b43legacy_wldev *dev)
 800 {
 801         struct b43legacy_phy *phy = &dev->phy;
 802         u16 tmp;
 803         u8 noise[4];
 804         u8 i;
 805         u8 j;
 806         s32 average;
 807
 808         /* Bottom half of Link Quality calculation. */
 809
 810         B43legacy_WARN_ON(!dev->noisecalc.calculation_running);
 811         if (dev->noisecalc.channel_at_start != phy->channel)
 812                 goto drop_calculation;
 813         *((__le32 *)noise) = cpu_to_le32(b43legacy_jssi_read(dev));
 814         if (noise[0] == 0x7F || noise[1] == 0x7F ||
 815             noise[2] == 0x7F || noise[3] == 0x7F)
 816                 goto generate_new;
 817
 818         /* Get the noise samples. */
 819         B43legacy_WARN_ON(dev->noisecalc.nr_samples >= 8);
 820         i = dev->noisecalc.nr_samples;
 821         noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
 822         noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
 823         noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
 824         noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
 825         dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
 826         dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
 827         dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
 828         dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
 829         dev->noisecalc.nr_samples++;
 830         if (dev->noisecalc.nr_samples == 8) {
 831                 /* Calculate the Link Quality by the noise samples. */
 832                 average = 0;
 833                 for (i = 0; i < 8; i++) {
 834                         for (j = 0; j < 4; j++)
 835                                 average += dev->noisecalc.samples[i][j];
 836                 }
 837                 average /= (8 * 4);
 838                 average *= 125;
 839                 average += 64;
 840                 average /= 128;
 841                 tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
 842                                              0x40C);
 843                 tmp = (tmp / 128) & 0x1F;
 844                 if (tmp >= 8)
 845                         average += 2;
 846                 else
 847                         average -= 25;
 848                 if (tmp == 8)
 849                         average -= 72;
 850                 else
 851                         average -= 48;
 852
 853                 dev->stats.link_noise = average;
 854 drop_calculation:
 855                 dev->noisecalc.calculation_running = 0;
 856                 return;
 857         }
 858 generate_new:
 859         b43legacy_generate_noise_sample(dev);
 860 }
 861
 862 static void handle_irq_tbtt_indication(struct b43legacy_wldev *dev)
 863 {
 864         if (b43legacy_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
 865                 /* TODO: PS TBTT */
 866         } else {
 867                 if (1/*FIXME: the last PSpoll frame was sent successfully */)
 868                         b43legacy_power_saving_ctl_bits(dev, -1, -1);
 869         }
 870         if (b43legacy_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
 871                 dev->dfq_valid = 1;
 872 }
 873
 874 static void handle_irq_atim_end(struct b43legacy_wldev *dev)
 875 {
 876         if (dev->dfq_valid) {
 877                 b43legacy_write32(dev, B43legacy_MMIO_MACCMD,
 878                                   b43legacy_read32(dev, B43legacy_MMIO_MACCMD)
 879                                   | B43legacy_MACCMD_DFQ_VALID);
 880                 dev->dfq_valid = 0;
 881         }
 882 }
 883
 884 static void handle_irq_pmq(struct b43legacy_wldev *dev)
 885 {
 886         u32 tmp;
 887
 888         /* TODO: AP mode. */
 889
 890         while (1) {
 891                 tmp = b43legacy_read32(dev, B43legacy_MMIO_PS_STATUS);
 892                 if (!(tmp & 0x00000008))
 893                         break;
 894         }
 895         /* 16bit write is odd, but correct. */
 896         b43legacy_write16(dev, B43legacy_MMIO_PS_STATUS, 0x0002);
 897 }
 898
 899 static void b43legacy_write_template_common(struct b43legacy_wldev *dev,
 900                                             const u8 *data, u16 size,
 901                                             u16 ram_offset,
 902                                             u16 shm_size_offset, u8 rate)
 903 {
 904         u32 i;
 905         u32 tmp;
 906         struct b43legacy_plcp_hdr4 plcp;
 907
 908         plcp.data = 0;
 909         b43legacy_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
 910         b43legacy_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
 911         ram_offset += sizeof(u32);
 912         /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
 913          * So leave the first two bytes of the next write blank.
 914          */
 915         tmp = (u32)(data[0]) << 16;
 916         tmp |= (u32)(data[1]) << 24;
 917         b43legacy_ram_write(dev, ram_offset, tmp);
 918         ram_offset += sizeof(u32);
 919         for (i = 2; i < size; i += sizeof(u32)) {
 920                 tmp = (u32)(data[i + 0]);
 921                 if (i + 1 < size)
 922                         tmp |= (u32)(data[i + 1]) << 8;
 923                 if (i + 2 < size)
 924                         tmp |= (u32)(data[i + 2]) << 16;
 925                 if (i + 3 < size)
 926                         tmp |= (u32)(data[i + 3]) << 24;
 927                 b43legacy_ram_write(dev, ram_offset + i - 2, tmp);
 928         }
 929         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_size_offset,
 930                               size + sizeof(struct b43legacy_plcp_hdr6));
 931 }
 932
 933 /* Convert a b43legacy antenna number value to the PHY TX control value. */
 934 static u16 b43legacy_antenna_to_phyctl(int antenna)
 935 {
 936         switch (antenna) {
 937         case B43legacy_ANTENNA0:
 938                 return B43legacy_TX4_PHY_ANT0;
 939         case B43legacy_ANTENNA1:
 940                 return B43legacy_TX4_PHY_ANT1;
 941         }
 942         return B43legacy_TX4_PHY_ANTLAST;
 943 }
 944
 945 static void b43legacy_write_beacon_template(struct b43legacy_wldev *dev,
 946                                             u16 ram_offset,
 947                                             u16 shm_size_offset)
 948 {
 949
 950         unsigned int i, len, variable_len;
 951         const struct ieee80211_mgmt *bcn;
 952         const u8 *ie;
 953         bool tim_found = 0;
 954         unsigned int rate;
 955         u16 ctl;
 956         int antenna;
 957         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
 958
 959         bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
 960         len = min((size_t)dev->wl->current_beacon->len,
 961                   0x200 - sizeof(struct b43legacy_plcp_hdr6));
 962         rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
 963
 964         b43legacy_write_template_common(dev, (const u8 *)bcn, len, ram_offset,
 965                                         shm_size_offset, rate);
 966
 967         /* Write the PHY TX control parameters. */
 968         antenna = B43legacy_ANTENNA_DEFAULT;
 969         antenna = b43legacy_antenna_to_phyctl(antenna);
 970         ctl = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
 971                                    B43legacy_SHM_SH_BEACPHYCTL);
 972         /* We can't send beacons with short preamble. Would get PHY errors. */
 973         ctl &= ~B43legacy_TX4_PHY_SHORTPRMBL;
 974         ctl &= ~B43legacy_TX4_PHY_ANT;
 975         ctl &= ~B43legacy_TX4_PHY_ENC;
 976         ctl |= antenna;
 977         ctl |= B43legacy_TX4_PHY_ENC_CCK;
 978         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
 979                               B43legacy_SHM_SH_BEACPHYCTL, ctl);
 980
 981         /* Find the position of the TIM and the DTIM_period value
 982          * and write them to SHM. */
 983         ie = bcn->u.beacon.variable;
 984         variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
 985         for (i = 0; i < variable_len - 2; ) {
 986                 uint8_t ie_id, ie_len;
 987
 988                 ie_id = ie[i];
 989                 ie_len = ie[i + 1];
 990                 if (ie_id == 5) {
 991                         u16 tim_position;
 992                         u16 dtim_period;
 993                         /* This is the TIM Information Element */
 994
 995                         /* Check whether the ie_len is in the beacon data range. */
 996                         if (variable_len < ie_len + 2 + i)
 997                                 break;
 998                         /* A valid TIM is at least 4 bytes long. */
 999                         if (ie_len < 4)
1000                                 break;
1001                         tim_found = 1;
1002
1003                         tim_position = sizeof(struct b43legacy_plcp_hdr6);
1004                         tim_position += offsetof(struct ieee80211_mgmt,
1005                                                  u.beacon.variable);
1006                         tim_position += i;
1007
1008                         dtim_period = ie[i + 3];
1009
1010                         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
1011                                         B43legacy_SHM_SH_TIMPOS, tim_position);
1012                         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
1013                                         B43legacy_SHM_SH_DTIMP, dtim_period);
1014                         break;
1015                 }
1016                 i += ie_len + 2;
1017         }
1018         if (!tim_found) {
1019                 b43legacywarn(dev->wl, "Did not find a valid TIM IE in the "
1020                               "beacon template packet. AP or IBSS operation "
1021                               "may be broken.\n");
1022         } else
1023                 b43legacydbg(dev->wl, "Updated beacon template\n");
1024 }
1025
1026 static void b43legacy_write_probe_resp_plcp(struct b43legacy_wldev *dev,
1027                                             u16 shm_offset, u16 size,
1028                                             struct ieee80211_rate *rate)
1029 {
1030         struct b43legacy_plcp_hdr4 plcp;
1031         u32 tmp;
1032         __le16 dur;
1033
1034         plcp.data = 0;
1035         b43legacy_generate_plcp_hdr(&plcp, size + FCS_LEN, rate->hw_value);
1036         dur = ieee80211_generic_frame_duration(dev->wl->hw,
1037                                                dev->wl->vif,
1038                                                size,
1039                                                rate);
1040         /* Write PLCP in two parts and timing for packet transfer */
1041         tmp = le32_to_cpu(plcp.data);
1042         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset,
1043                               tmp & 0xFFFF);
1044         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset + 2,
1045                               tmp >> 16);
1046         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, shm_offset + 6,
1047                               le16_to_cpu(dur));
1048 }
1049
1050 /* Instead of using custom probe response template, this function
1051  * just patches custom beacon template by:
1052  * 1) Changing packet type
1053  * 2) Patching duration field
1054  * 3) Stripping TIM
1055  */
1056 static const u8 *b43legacy_generate_probe_resp(struct b43legacy_wldev *dev,
1057                                                u16 *dest_size,
1058                                                struct ieee80211_rate *rate)
1059 {
1060         const u8 *src_data;
1061         u8 *dest_data;
1062         u16 src_size, elem_size, src_pos, dest_pos;
1063         __le16 dur;
1064         struct ieee80211_hdr *hdr;
1065         size_t ie_start;
1066
1067         src_size = dev->wl->current_beacon->len;
1068         src_data = (const u8 *)dev->wl->current_beacon->data;
1069
1070         /* Get the start offset of the variable IEs in the packet. */
1071         ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
1072         B43legacy_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt,
1073                                                u.beacon.variable));
1074
1075         if (B43legacy_WARN_ON(src_size < ie_start))
1076                 return NULL;
1077
1078         dest_data = kmalloc(src_size, GFP_ATOMIC);
1079         if (unlikely(!dest_data))
1080                 return NULL;
1081
1082         /* Copy the static data and all Information Elements, except the TIM. */
1083         memcpy(dest_data, src_data, ie_start);
1084         src_pos = ie_start;
1085         dest_pos = ie_start;
1086         for ( ; src_pos < src_size - 2; src_pos += elem_size) {
1087                 elem_size = src_data[src_pos + 1] + 2;
1088                 if (src_data[src_pos] == 5) {
1089                         /* This is the TIM. */
1090                         continue;
1091                 }
1092                 memcpy(dest_data + dest_pos, src_data + src_pos, elem_size);
1093                 dest_pos += elem_size;
1094         }
1095         *dest_size = dest_pos;
1096         hdr = (struct ieee80211_hdr *)dest_data;
1097
1098         /* Set the frame control. */
1099         hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1100                                          IEEE80211_STYPE_PROBE_RESP);
1101         dur = ieee80211_generic_frame_duration(dev->wl->hw,
1102                                                dev->wl->vif,
1103                                                *dest_size,
1104                                                rate);
1105         hdr->duration_id = dur;
1106
1107         return dest_data;
1108 }
1109
1110 static void b43legacy_write_probe_resp_template(struct b43legacy_wldev *dev,
1111                                                 u16 ram_offset,
1112                                                 u16 shm_size_offset,
1113                                                 struct ieee80211_rate *rate)
1114 {
1115         const u8 *probe_resp_data;
1116         u16 size;
1117
1118         size = dev->wl->current_beacon->len;
1119         probe_resp_data = b43legacy_generate_probe_resp(dev, &size, rate);
1120         if (unlikely(!probe_resp_data))
1121                 return;
1122
1123         /* Looks like PLCP headers plus packet timings are stored for
1124          * all possible basic rates
1125          */
1126         b43legacy_write_probe_resp_plcp(dev, 0x31A, size,
1127                                         &b43legacy_b_ratetable[0]);
1128         b43legacy_write_probe_resp_plcp(dev, 0x32C, size,
1129                                         &b43legacy_b_ratetable[1]);
1130         b43legacy_write_probe_resp_plcp(dev, 0x33E, size,
1131                                         &b43legacy_b_ratetable[2]);
1132         b43legacy_write_probe_resp_plcp(dev, 0x350, size,
1133                                         &b43legacy_b_ratetable[3]);
1134
1135         size = min((size_t)size,
1136                    0x200 - sizeof(struct b43legacy_plcp_hdr6));
1137         b43legacy_write_template_common(dev, probe_resp_data,
1138                                         size, ram_offset,
1139                                         shm_size_offset, rate->hw_value);
1140         kfree(probe_resp_data);
1141 }
1142
1143 static void b43legacy_upload_beacon0(struct b43legacy_wldev *dev)
1144 {
1145         struct b43legacy_wl *wl = dev->wl;
1146
1147         if (wl->beacon0_uploaded)
1148                 return;
1149         b43legacy_write_beacon_template(dev, 0x68, 0x18);
1150         /* FIXME: Probe resp upload doesn't really belong here,
1151          *        but we don't use that feature anyway. */
1152         b43legacy_write_probe_resp_template(dev, 0x268, 0x4A,
1153                                       &__b43legacy_ratetable[3]);
1154         wl->beacon0_uploaded = 1;
1155 }
1156
1157 static void b43legacy_upload_beacon1(struct b43legacy_wldev *dev)
1158 {
1159         struct b43legacy_wl *wl = dev->wl;
1160
1161         if (wl->beacon1_uploaded)
1162                 return;
1163         b43legacy_write_beacon_template(dev, 0x468, 0x1A);
1164         wl->beacon1_uploaded = 1;
1165 }
1166
1167 static void handle_irq_beacon(struct b43legacy_wldev *dev)
1168 {
1169         struct b43legacy_wl *wl = dev->wl;
1170         u32 cmd, beacon0_valid, beacon1_valid;
1171
1172         if (!b43legacy_is_mode(wl, NL80211_IFTYPE_AP))
1173                 return;
1174
1175         /* This is the bottom half of the asynchronous beacon update. */
1176
1177         /* Ignore interrupt in the future. */
1178         dev->irq_mask &= ~B43legacy_IRQ_BEACON;
1179
1180         cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
1181         beacon0_valid = (cmd & B43legacy_MACCMD_BEACON0_VALID);
1182         beacon1_valid = (cmd & B43legacy_MACCMD_BEACON1_VALID);
1183
1184         /* Schedule interrupt manually, if busy. */
1185         if (beacon0_valid && beacon1_valid) {
1186                 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, B43legacy_IRQ_BEACON);
1187                 dev->irq_mask |= B43legacy_IRQ_BEACON;
1188                 return;
1189         }
1190
1191         if (unlikely(wl->beacon_templates_virgin)) {
1192                 /* We never uploaded a beacon before.
1193                  * Upload both templates now, but only mark one valid. */
1194                 wl->beacon_templates_virgin = 0;
1195                 b43legacy_upload_beacon0(dev);
1196                 b43legacy_upload_beacon1(dev);
1197                 cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
1198                 cmd |= B43legacy_MACCMD_BEACON0_VALID;
1199                 b43legacy_write32(dev, B43legacy_MMIO_MACCMD, cmd);
1200         } else {
1201                 if (!beacon0_valid) {
1202                         b43legacy_upload_beacon0(dev);
1203                         cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
1204                         cmd |= B43legacy_MACCMD_BEACON0_VALID;
1205                         b43legacy_write32(dev, B43legacy_MMIO_MACCMD, cmd);
1206                 } else if (!beacon1_valid) {
1207                         b43legacy_upload_beacon1(dev);
1208                         cmd = b43legacy_read32(dev, B43legacy_MMIO_MACCMD);
1209                         cmd |= B43legacy_MACCMD_BEACON1_VALID;
1210                         b43legacy_write32(dev, B43legacy_MMIO_MACCMD, cmd);
1211                 }
1212         }
1213 }
1214
1215 static void b43legacy_beacon_update_trigger_work(struct work_struct *work)
1216 {
1217         struct b43legacy_wl *wl = container_of(work, struct b43legacy_wl,
1218                                          beacon_update_trigger);
1219         struct b43legacy_wldev *dev;
1220
1221         mutex_lock(&wl->mutex);
1222         dev = wl->current_dev;
1223         if (likely(dev && (b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED))) {
1224                 spin_lock_irq(&wl->irq_lock);
1225                 /* Update beacon right away or defer to IRQ. */
1226                 handle_irq_beacon(dev);
1227                 /* The handler might have updated the IRQ mask. */
1228                 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK,
1229                                   dev->irq_mask);
1230                 mmiowb();
1231                 spin_unlock_irq(&wl->irq_lock);
1232         }
1233         mutex_unlock(&wl->mutex);
1234 }
1235
1236 /* Asynchronously update the packet templates in template RAM.
1237  * Locking: Requires wl->irq_lock to be locked. */
1238 static void b43legacy_update_templates(struct b43legacy_wl *wl)
1239 {
1240         struct sk_buff *beacon;
1241         /* This is the top half of the ansynchronous beacon update. The bottom
1242          * half is the beacon IRQ. Beacon update must be asynchronous to avoid
1243          * sending an invalid beacon. This can happen for example, if the
1244          * firmware transmits a beacon while we are updating it. */
1245
1246         /* We could modify the existing beacon and set the aid bit in the TIM
1247          * field, but that would probably require resizing and moving of data
1248          * within the beacon template. Simply request a new beacon and let
1249          * mac80211 do the hard work. */
1250         beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1251         if (unlikely(!beacon))
1252                 return;
1253
1254         if (wl->current_beacon)
1255                 dev_kfree_skb_any(wl->current_beacon);
1256         wl->current_beacon = beacon;
1257         wl->beacon0_uploaded = 0;
1258         wl->beacon1_uploaded = 0;
1259         ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
1260 }
1261
1262 static void b43legacy_set_beacon_int(struct b43legacy_wldev *dev,
1263                                      u16 beacon_int)
1264 {
1265         b43legacy_time_lock(dev);
1266         if (dev->dev->id.revision >= 3) {
1267                 b43legacy_write32(dev, B43legacy_MMIO_TSF_CFP_REP,
1268                                  (beacon_int << 16));
1269                 b43legacy_write32(dev, B43legacy_MMIO_TSF_CFP_START,
1270                                  (beacon_int << 10));
1271         } else {
1272                 b43legacy_write16(dev, 0x606, (beacon_int >> 6));
1273                 b43legacy_write16(dev, 0x610, beacon_int);
1274         }
1275         b43legacy_time_unlock(dev);
1276         b43legacydbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
1277 }
1278
1279 static void handle_irq_ucode_debug(struct b43legacy_wldev *dev)
1280 {
1281 }
1282
1283 /* Interrupt handler bottom-half */
1284 static void b43legacy_interrupt_tasklet(struct b43legacy_wldev *dev)
1285 {
1286         u32 reason;
1287         u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1288         u32 merged_dma_reason = 0;
1289         int i;
1290         unsigned long flags;
1291
1292         spin_lock_irqsave(&dev->wl->irq_lock, flags);
1293
1294         B43legacy_WARN_ON(b43legacy_status(dev) <
1295                           B43legacy_STAT_INITIALIZED);
1296
1297         reason = dev->irq_reason;
1298         for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1299                 dma_reason[i] = dev->dma_reason[i];
1300                 merged_dma_reason |= dma_reason[i];
1301         }
1302
1303         if (unlikely(reason & B43legacy_IRQ_MAC_TXERR))
1304                 b43legacyerr(dev->wl, "MAC transmission error\n");
1305
1306         if (unlikely(reason & B43legacy_IRQ_PHY_TXERR)) {
1307                 b43legacyerr(dev->wl, "PHY transmission error\n");
1308                 rmb();
1309                 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1310                         b43legacyerr(dev->wl, "Too many PHY TX errors, "
1311                                               "restarting the controller\n");
1312                         b43legacy_controller_restart(dev, "PHY TX errors");
1313                 }
1314         }
1315
1316         if (unlikely(merged_dma_reason & (B43legacy_DMAIRQ_FATALMASK |
1317                                           B43legacy_DMAIRQ_NONFATALMASK))) {
1318                 if (merged_dma_reason & B43legacy_DMAIRQ_FATALMASK) {
1319                         b43legacyerr(dev->wl, "Fatal DMA error: "
1320                                "0x%08X, 0x%08X, 0x%08X, "
1321                                "0x%08X, 0x%08X, 0x%08X\n",
1322                                dma_reason[0], dma_reason[1],
1323                                dma_reason[2], dma_reason[3],
1324                                dma_reason[4], dma_reason[5]);
1325                         b43legacy_controller_restart(dev, "DMA error");
1326                         mmiowb();
1327                         spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1328                         return;
1329                 }
1330                 if (merged_dma_reason & B43legacy_DMAIRQ_NONFATALMASK)
1331                         b43legacyerr(dev->wl, "DMA error: "
1332                                "0x%08X, 0x%08X, 0x%08X, "
1333                                "0x%08X, 0x%08X, 0x%08X\n",
1334                                dma_reason[0], dma_reason[1],
1335                                dma_reason[2], dma_reason[3],
1336                                dma_reason[4], dma_reason[5]);
1337         }
1338
1339         if (unlikely(reason & B43legacy_IRQ_UCODE_DEBUG))
1340                 handle_irq_ucode_debug(dev);
1341         if (reason & B43legacy_IRQ_TBTT_INDI)
1342                 handle_irq_tbtt_indication(dev);
1343         if (reason & B43legacy_IRQ_ATIM_END)
1344                 handle_irq_atim_end(dev);
1345         if (reason & B43legacy_IRQ_BEACON)
1346                 handle_irq_beacon(dev);
1347         if (reason & B43legacy_IRQ_PMQ)
1348                 handle_irq_pmq(dev);
1349         if (reason & B43legacy_IRQ_TXFIFO_FLUSH_OK)
1350                 ;/*TODO*/
1351         if (reason & B43legacy_IRQ_NOISESAMPLE_OK)
1352                 handle_irq_noise(dev);
1353
1354         /* Check the DMA reason registers for received data. */
1355         if (dma_reason[0] & B43legacy_DMAIRQ_RX_DONE) {
1356                 if (b43legacy_using_pio(dev))
1357                         b43legacy_pio_rx(dev->pio.queue0);
1358                 else
1359                         b43legacy_dma_rx(dev->dma.rx_ring0);
1360         }
1361         B43legacy_WARN_ON(dma_reason[1] & B43legacy_DMAIRQ_RX_DONE);
1362         B43legacy_WARN_ON(dma_reason[2] & B43legacy_DMAIRQ_RX_DONE);
1363         if (dma_reason[3] & B43legacy_DMAIRQ_RX_DONE) {
1364                 if (b43legacy_using_pio(dev))
1365                         b43legacy_pio_rx(dev->pio.queue3);
1366                 else
1367                         b43legacy_dma_rx(dev->dma.rx_ring3);
1368         }
1369         B43legacy_WARN_ON(dma_reason[4] & B43legacy_DMAIRQ_RX_DONE);
1370         B43legacy_WARN_ON(dma_reason[5] & B43legacy_DMAIRQ_RX_DONE);
1371
1372         if (reason & B43legacy_IRQ_TX_OK)
1373                 handle_irq_transmit_status(dev);
1374
1375         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1376         mmiowb();
1377         spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1378 }
1379
1380 static void pio_irq_workaround(struct b43legacy_wldev *dev,
1381                                u16 base, int queueidx)
1382 {
1383         u16 rxctl;
1384
1385         rxctl = b43legacy_read16(dev, base + B43legacy_PIO_RXCTL);
1386         if (rxctl & B43legacy_PIO_RXCTL_DATAAVAILABLE)
1387                 dev->dma_reason[queueidx] |= B43legacy_DMAIRQ_RX_DONE;
1388         else
1389                 dev->dma_reason[queueidx] &= ~B43legacy_DMAIRQ_RX_DONE;
1390 }
1391
1392 static void b43legacy_interrupt_ack(struct b43legacy_wldev *dev, u32 reason)
1393 {
1394         if (b43legacy_using_pio(dev) &&
1395             (dev->dev->id.revision < 3) &&
1396             (!(reason & B43legacy_IRQ_PIO_WORKAROUND))) {
1397                 /* Apply a PIO specific workaround to the dma_reasons */
1398                 pio_irq_workaround(dev, B43legacy_MMIO_PIO1_BASE, 0);
1399                 pio_irq_workaround(dev, B43legacy_MMIO_PIO2_BASE, 1);
1400                 pio_irq_workaround(dev, B43legacy_MMIO_PIO3_BASE, 2);
1401                 pio_irq_workaround(dev, B43legacy_MMIO_PIO4_BASE, 3);
1402         }
1403
1404         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, reason);
1405
1406         b43legacy_write32(dev, B43legacy_MMIO_DMA0_REASON,
1407                           dev->dma_reason[0]);
1408         b43legacy_write32(dev, B43legacy_MMIO_DMA1_REASON,
1409                           dev->dma_reason[1]);
1410         b43legacy_write32(dev, B43legacy_MMIO_DMA2_REASON,
1411                           dev->dma_reason[2]);
1412         b43legacy_write32(dev, B43legacy_MMIO_DMA3_REASON,
1413                           dev->dma_reason[3]);
1414         b43legacy_write32(dev, B43legacy_MMIO_DMA4_REASON,
1415                           dev->dma_reason[4]);
1416         b43legacy_write32(dev, B43legacy_MMIO_DMA5_REASON,
1417                           dev->dma_reason[5]);
1418 }
1419
1420 /* Interrupt handler top-half */
1421 static irqreturn_t b43legacy_interrupt_handler(int irq, void *dev_id)
1422 {
1423         irqreturn_t ret = IRQ_NONE;
1424         struct b43legacy_wldev *dev = dev_id;
1425         u32 reason;
1426
1427         B43legacy_WARN_ON(!dev);
1428
1429         spin_lock(&dev->wl->irq_lock);
1430
1431         if (unlikely(b43legacy_status(dev) < B43legacy_STAT_STARTED))
1432                 /* This can only happen on shared IRQ lines. */
1433                 goto out;
1434         reason = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1435         if (reason == 0xffffffff) /* shared IRQ */
1436                 goto out;
1437         ret = IRQ_HANDLED;
1438         reason &= dev->irq_mask;
1439         if (!reason)
1440                 goto out;
1441
1442         dev->dma_reason[0] = b43legacy_read32(dev,
1443                                               B43legacy_MMIO_DMA0_REASON)
1444                                               & 0x0001DC00;
1445         dev->dma_reason[1] = b43legacy_read32(dev,
1446                                               B43legacy_MMIO_DMA1_REASON)
1447                                               & 0x0000DC00;
1448         dev->dma_reason[2] = b43legacy_read32(dev,
1449                                               B43legacy_MMIO_DMA2_REASON)
1450                                               & 0x0000DC00;
1451         dev->dma_reason[3] = b43legacy_read32(dev,
1452                                               B43legacy_MMIO_DMA3_REASON)
1453                                               & 0x0001DC00;
1454         dev->dma_reason[4] = b43legacy_read32(dev,
1455                                               B43legacy_MMIO_DMA4_REASON)
1456                                               & 0x0000DC00;
1457         dev->dma_reason[5] = b43legacy_read32(dev,
1458                                               B43legacy_MMIO_DMA5_REASON)
1459                                               & 0x0000DC00;
1460
1461         b43legacy_interrupt_ack(dev, reason);
1462         /* Disable all IRQs. They are enabled again in the bottom half. */
1463         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
1464         /* Save the reason code and call our bottom half. */
1465         dev->irq_reason = reason;
1466         tasklet_schedule(&dev->isr_tasklet);
1467 out:
1468         mmiowb();
1469         spin_unlock(&dev->wl->irq_lock);
1470
1471         return ret;
1472 }
1473
1474 static void b43legacy_release_firmware(struct b43legacy_wldev *dev)
1475 {
1476         release_firmware(dev->fw.ucode);
1477         dev->fw.ucode = NULL;
1478         release_firmware(dev->fw.pcm);
1479         dev->fw.pcm = NULL;
1480         release_firmware(dev->fw.initvals);
1481         dev->fw.initvals = NULL;
1482         release_firmware(dev->fw.initvals_band);
1483         dev->fw.initvals_band = NULL;
1484 }
1485
1486 static void b43legacy_print_fw_helptext(struct b43legacy_wl *wl)
1487 {
1488         b43legacyerr(wl, "You must go to http://linuxwireless.org/en/users/"
1489                      "Drivers/b43#devicefirmware "
1490                      "and download the correct firmware (version 3).\n");
1491 }
1492
1493 static int do_request_fw(struct b43legacy_wldev *dev,
1494                          const char *name,
1495                          const struct firmware **fw)
1496 {
1497         char path[sizeof(modparam_fwpostfix) + 32];
1498         struct b43legacy_fw_header *hdr;
1499         u32 size;
1500         int err;
1501
1502         if (!name)
1503                 return 0;
1504
1505         snprintf(path, ARRAY_SIZE(path),
1506                  "b43legacy%s/%s.fw",
1507                  modparam_fwpostfix, name);
1508         err = request_firmware(fw, path, dev->dev->dev);
1509         if (err) {
1510                 b43legacyerr(dev->wl, "Firmware file \"%s\" not found "
1511                        "or load failed.\n", path);
1512                 return err;
1513         }
1514         if ((*fw)->size < sizeof(struct b43legacy_fw_header))
1515                 goto err_format;
1516         hdr = (struct b43legacy_fw_header *)((*fw)->data);
1517         switch (hdr->type) {
1518         case B43legacy_FW_TYPE_UCODE:
1519         case B43legacy_FW_TYPE_PCM:
1520                 size = be32_to_cpu(hdr->size);
1521                 if (size != (*fw)->size - sizeof(struct b43legacy_fw_header))
1522                         goto err_format;
1523                 /* fallthrough */
1524         case B43legacy_FW_TYPE_IV:
1525                 if (hdr->ver != 1)
1526                         goto err_format;
1527                 break;
1528         default:
1529                 goto err_format;
1530         }
1531
1532         return err;
1533
1534 err_format:
1535         b43legacyerr(dev->wl, "Firmware file \"%s\" format error.\n", path);
1536         return -EPROTO;
1537 }
1538
1539 static int b43legacy_request_firmware(struct b43legacy_wldev *dev)
1540 {
1541         struct b43legacy_firmware *fw = &dev->fw;
1542         const u8 rev = dev->dev->id.revision;
1543         const char *filename;
1544         u32 tmshigh;
1545         int err;
1546
1547         tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
1548         if (!fw->ucode) {
1549                 if (rev == 2)
1550                         filename = "ucode2";
1551                 else if (rev == 4)
1552                         filename = "ucode4";
1553                 else
1554                         filename = "ucode5";
1555                 err = do_request_fw(dev, filename, &fw->ucode);
1556                 if (err)
1557                         goto err_load;
1558         }
1559         if (!fw->pcm) {
1560                 if (rev < 5)
1561                         filename = "pcm4";
1562                 else
1563                         filename = "pcm5";
1564                 err = do_request_fw(dev, filename, &fw->pcm);
1565                 if (err)
1566                         goto err_load;
1567         }
1568         if (!fw->initvals) {
1569                 switch (dev->phy.type) {
1570                 case B43legacy_PHYTYPE_B:
1571                 case B43legacy_PHYTYPE_G:
1572                         if ((rev >= 5) && (rev <= 10))
1573                                 filename = "b0g0initvals5";
1574                         else if (rev == 2 || rev == 4)
1575                                 filename = "b0g0initvals2";
1576                         else
1577                                 goto err_no_initvals;
1578                         break;
1579                 default:
1580                         goto err_no_initvals;
1581                 }
1582                 err = do_request_fw(dev, filename, &fw->initvals);
1583                 if (err)
1584                         goto err_load;
1585         }
1586         if (!fw->initvals_band) {
1587                 switch (dev->phy.type) {
1588                 case B43legacy_PHYTYPE_B:
1589                 case B43legacy_PHYTYPE_G:
1590                         if ((rev >= 5) && (rev <= 10))
1591                                 filename = "b0g0bsinitvals5";
1592                         else if (rev >= 11)
1593                                 filename = NULL;
1594                         else if (rev == 2 || rev == 4)
1595                                 filename = NULL;
1596                         else
1597                                 goto err_no_initvals;
1598                         break;
1599                 default:
1600                         goto err_no_initvals;
1601                 }
1602                 err = do_request_fw(dev, filename, &fw->initvals_band);
1603                 if (err)
1604                         goto err_load;
1605         }
1606
1607         return 0;
1608
1609 err_load:
1610         b43legacy_print_fw_helptext(dev->wl);
1611         goto error;
1612
1613 err_no_initvals:
1614         err = -ENODEV;
1615         b43legacyerr(dev->wl, "No Initial Values firmware file for PHY %u, "
1616                "core rev %u\n", dev->phy.type, rev);
1617         goto error;
1618
1619 error:
1620         b43legacy_release_firmware(dev);
1621         return err;
1622 }
1623
1624 static int b43legacy_upload_microcode(struct b43legacy_wldev *dev)
1625 {
1626         const size_t hdr_len = sizeof(struct b43legacy_fw_header);
1627         const __be32 *data;
1628         unsigned int i;
1629         unsigned int len;
1630         u16 fwrev;
1631         u16 fwpatch;
1632         u16 fwdate;
1633         u16 fwtime;
1634         u32 tmp, macctl;
1635         int err = 0;
1636
1637         /* Jump the microcode PSM to offset 0 */
1638         macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1639         B43legacy_WARN_ON(macctl & B43legacy_MACCTL_PSM_RUN);
1640         macctl |= B43legacy_MACCTL_PSM_JMP0;
1641         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
1642         /* Zero out all microcode PSM registers and shared memory. */
1643         for (i = 0; i < 64; i++)
1644                 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, i, 0);
1645         for (i = 0; i < 4096; i += 2)
1646                 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, i, 0);
1647
1648         /* Upload Microcode. */
1649         data = (__be32 *) (dev->fw.ucode->data + hdr_len);
1650         len = (dev->fw.ucode->size - hdr_len) / sizeof(__be32);
1651         b43legacy_shm_control_word(dev,
1652                                    B43legacy_SHM_UCODE |
1653                                    B43legacy_SHM_AUTOINC_W,
1654                                    0x0000);
1655         for (i = 0; i < len; i++) {
1656                 b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA,
1657                                     be32_to_cpu(data[i]));
1658                 udelay(10);
1659         }
1660
1661         if (dev->fw.pcm) {
1662                 /* Upload PCM data. */
1663                 data = (__be32 *) (dev->fw.pcm->data + hdr_len);
1664                 len = (dev->fw.pcm->size - hdr_len) / sizeof(__be32);
1665                 b43legacy_shm_control_word(dev, B43legacy_SHM_HW, 0x01EA);
1666                 b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA, 0x00004000);
1667                 /* No need for autoinc bit in SHM_HW */
1668                 b43legacy_shm_control_word(dev, B43legacy_SHM_HW, 0x01EB);
1669                 for (i = 0; i < len; i++) {
1670                         b43legacy_write32(dev, B43legacy_MMIO_SHM_DATA,
1671                                           be32_to_cpu(data[i]));
1672                         udelay(10);
1673                 }
1674         }
1675
1676         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON,
1677                           B43legacy_IRQ_ALL);
1678
1679         /* Start the microcode PSM */
1680         macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1681         macctl &= ~B43legacy_MACCTL_PSM_JMP0;
1682         macctl |= B43legacy_MACCTL_PSM_RUN;
1683         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
1684
1685         /* Wait for the microcode to load and respond */
1686         i = 0;
1687         while (1) {
1688                 tmp = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1689                 if (tmp == B43legacy_IRQ_MAC_SUSPENDED)
1690                         break;
1691                 i++;
1692                 if (i >= B43legacy_IRQWAIT_MAX_RETRIES) {
1693                         b43legacyerr(dev->wl, "Microcode not responding\n");
1694                         b43legacy_print_fw_helptext(dev->wl);
1695                         err = -ENODEV;
1696                         goto error;
1697                 }
1698                 msleep_interruptible(50);
1699                 if (signal_pending(current)) {
1700                         err = -EINTR;
1701                         goto error;
1702                 }
1703         }
1704         /* dummy read follows */
1705         b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1706
1707         /* Get and check the revisions. */
1708         fwrev = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1709                                      B43legacy_SHM_SH_UCODEREV);
1710         fwpatch = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1711                                        B43legacy_SHM_SH_UCODEPATCH);
1712         fwdate = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1713                                       B43legacy_SHM_SH_UCODEDATE);
1714         fwtime = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
1715                                       B43legacy_SHM_SH_UCODETIME);
1716
1717         if (fwrev > 0x128) {
1718                 b43legacyerr(dev->wl, "YOU ARE TRYING TO LOAD V4 FIRMWARE."
1719                              " Only firmware from binary drivers version 3.x"
1720                              " is supported. You must change your firmware"
1721                              " files.\n");
1722                 b43legacy_print_fw_helptext(dev->wl);
1723                 err = -EOPNOTSUPP;
1724                 goto error;
1725         }
1726         b43legacyinfo(dev->wl, "Loading firmware version 0x%X, patch level %u "
1727                       "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n", fwrev, fwpatch,
1728                       (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
1729                       (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F,
1730                       fwtime & 0x1F);
1731
1732         dev->fw.rev = fwrev;
1733         dev->fw.patch = fwpatch;
1734
1735         return 0;
1736
1737 error:
1738         macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1739         macctl &= ~B43legacy_MACCTL_PSM_RUN;
1740         macctl |= B43legacy_MACCTL_PSM_JMP0;
1741         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
1742
1743         return err;
1744 }
1745
1746 static int b43legacy_write_initvals(struct b43legacy_wldev *dev,
1747                                     const struct b43legacy_iv *ivals,
1748                                     size_t count,
1749                                     size_t array_size)
1750 {
1751         const struct b43legacy_iv *iv;
1752         u16 offset;
1753         size_t i;
1754         bool bit32;
1755
1756         BUILD_BUG_ON(sizeof(struct b43legacy_iv) != 6);
1757         iv = ivals;
1758         for (i = 0; i < count; i++) {
1759                 if (array_size < sizeof(iv->offset_size))
1760                         goto err_format;
1761                 array_size -= sizeof(iv->offset_size);
1762                 offset = be16_to_cpu(iv->offset_size);
1763                 bit32 = !!(offset & B43legacy_IV_32BIT);
1764                 offset &= B43legacy_IV_OFFSET_MASK;
1765                 if (offset >= 0x1000)
1766                         goto err_format;
1767                 if (bit32) {
1768                         u32 value;
1769
1770                         if (array_size < sizeof(iv->data.d32))
1771                                 goto err_format;
1772                         array_size -= sizeof(iv->data.d32);
1773
1774                         value = get_unaligned_be32(&iv->data.d32);
1775                         b43legacy_write32(dev, offset, value);
1776
1777                         iv = (const struct b43legacy_iv *)((const uint8_t *)iv +
1778                                                         sizeof(__be16) +
1779                                                         sizeof(__be32));
1780                 } else {
1781                         u16 value;
1782
1783                         if (array_size < sizeof(iv->data.d16))
1784                                 goto err_format;
1785                         array_size -= sizeof(iv->data.d16);
1786
1787                         value = be16_to_cpu(iv->data.d16);
1788                         b43legacy_write16(dev, offset, value);
1789
1790                         iv = (const struct b43legacy_iv *)((const uint8_t *)iv +
1791                                                         sizeof(__be16) +
1792                                                         sizeof(__be16));
1793                 }
1794         }
1795         if (array_size)
1796                 goto err_format;
1797
1798         return 0;
1799
1800 err_format:
1801         b43legacyerr(dev->wl, "Initial Values Firmware file-format error.\n");
1802         b43legacy_print_fw_helptext(dev->wl);
1803
1804         return -EPROTO;
1805 }
1806
1807 static int b43legacy_upload_initvals(struct b43legacy_wldev *dev)
1808 {
1809         const size_t hdr_len = sizeof(struct b43legacy_fw_header);
1810         const struct b43legacy_fw_header *hdr;
1811         struct b43legacy_firmware *fw = &dev->fw;
1812         const struct b43legacy_iv *ivals;
1813         size_t count;
1814         int err;
1815
1816         hdr = (const struct b43legacy_fw_header *)(fw->initvals->data);
1817         ivals = (const struct b43legacy_iv *)(fw->initvals->data + hdr_len);
1818         count = be32_to_cpu(hdr->size);
1819         err = b43legacy_write_initvals(dev, ivals, count,
1820                                  fw->initvals->size - hdr_len);
1821         if (err)
1822                 goto out;
1823         if (fw->initvals_band) {
1824                 hdr = (const struct b43legacy_fw_header *)
1825                       (fw->initvals_band->data);
1826                 ivals = (const struct b43legacy_iv *)(fw->initvals_band->data
1827                         + hdr_len);
1828                 count = be32_to_cpu(hdr->size);
1829                 err = b43legacy_write_initvals(dev, ivals, count,
1830                                          fw->initvals_band->size - hdr_len);
1831                 if (err)
1832                         goto out;
1833         }
1834 out:
1835
1836         return err;
1837 }
1838
1839 /* Initialize the GPIOs
1840  * http://bcm-specs.sipsolutions.net/GPIO
1841  */
1842 static int b43legacy_gpio_init(struct b43legacy_wldev *dev)
1843 {
1844         struct ssb_bus *bus = dev->dev->bus;
1845         struct ssb_device *gpiodev, *pcidev = NULL;
1846         u32 mask;
1847         u32 set;
1848
1849         b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
1850                           b43legacy_read32(dev,
1851                           B43legacy_MMIO_MACCTL)
1852                           & 0xFFFF3FFF);
1853
1854         b43legacy_write16(dev, B43legacy_MMIO_GPIO_MASK,
1855                           b43legacy_read16(dev,
1856                           B43legacy_MMIO_GPIO_MASK)
1857                           | 0x000F);
1858
1859         mask = 0x0000001F;
1860         set = 0x0000000F;
1861         if (dev->dev->bus->chip_id == 0x4301) {
1862                 mask |= 0x0060;
1863                 set |= 0x0060;
1864         }
1865         if (dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_PACTRL) {
1866                 b43legacy_write16(dev, B43legacy_MMIO_GPIO_MASK,
1867                                   b43legacy_read16(dev,
1868                                   B43legacy_MMIO_GPIO_MASK)
1869                                   | 0x0200);
1870                 mask |= 0x0200;
1871                 set |= 0x0200;
1872         }
1873         if (dev->dev->id.revision >= 2)
1874                 mask  |= 0x0010; /* FIXME: This is redundant. */
1875
1876 #ifdef CONFIG_SSB_DRIVER_PCICORE
1877         pcidev = bus->pcicore.dev;
1878 #endif
1879         gpiodev = bus->chipco.dev ? : pcidev;
1880         if (!gpiodev)
1881                 return 0;
1882         ssb_write32(gpiodev, B43legacy_GPIO_CONTROL,
1883                     (ssb_read32(gpiodev, B43legacy_GPIO_CONTROL)
1884                      & mask) | set);
1885
1886         return 0;
1887 }
1888
1889 /* Turn off all GPIO stuff. Call this on module unload, for example. */
1890 static void b43legacy_gpio_cleanup(struct b43legacy_wldev *dev)
1891 {
1892         struct ssb_bus *bus = dev->dev->bus;
1893         struct ssb_device *gpiodev, *pcidev = NULL;
1894
1895 #ifdef CONFIG_SSB_DRIVER_PCICORE
1896         pcidev = bus->pcicore.dev;
1897 #endif
1898         gpiodev = bus->chipco.dev ? : pcidev;
1899         if (!gpiodev)
1900                 return;
1901         ssb_write32(gpiodev, B43legacy_GPIO_CONTROL, 0);
1902 }
1903
1904 /* http://bcm-specs.sipsolutions.net/EnableMac */
1905 void b43legacy_mac_enable(struct b43legacy_wldev *dev)
1906 {
1907         dev->mac_suspended--;
1908         B43legacy_WARN_ON(dev->mac_suspended < 0);
1909         B43legacy_WARN_ON(irqs_disabled());
1910         if (dev->mac_suspended == 0) {
1911                 b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
1912                                   b43legacy_read32(dev,
1913                                   B43legacy_MMIO_MACCTL)
1914                                   | B43legacy_MACCTL_ENABLED);
1915                 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON,
1916                                   B43legacy_IRQ_MAC_SUSPENDED);
1917                 /* the next two are dummy reads */
1918                 b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1919                 b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1920                 b43legacy_power_saving_ctl_bits(dev, -1, -1);
1921
1922                 /* Re-enable IRQs. */
1923                 spin_lock_irq(&dev->wl->irq_lock);
1924                 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK,
1925                                   dev->irq_mask);
1926                 spin_unlock_irq(&dev->wl->irq_lock);
1927         }
1928 }
1929
1930 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
1931 void b43legacy_mac_suspend(struct b43legacy_wldev *dev)
1932 {
1933         int i;
1934         u32 tmp;
1935
1936         might_sleep();
1937         B43legacy_WARN_ON(irqs_disabled());
1938         B43legacy_WARN_ON(dev->mac_suspended < 0);
1939
1940         if (dev->mac_suspended == 0) {
1941                 /* Mask IRQs before suspending MAC. Otherwise
1942                  * the MAC stays busy and won't suspend. */
1943                 spin_lock_irq(&dev->wl->irq_lock);
1944                 b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
1945                 spin_unlock_irq(&dev->wl->irq_lock);
1946                 b43legacy_synchronize_irq(dev);
1947
1948                 b43legacy_power_saving_ctl_bits(dev, -1, 1);
1949                 b43legacy_write32(dev, B43legacy_MMIO_MACCTL,
1950                                   b43legacy_read32(dev,
1951                                   B43legacy_MMIO_MACCTL)
1952                                   & ~B43legacy_MACCTL_ENABLED);
1953                 b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
1954                 for (i = 40; i; i--) {
1955                         tmp = b43legacy_read32(dev,
1956                                                B43legacy_MMIO_GEN_IRQ_REASON);
1957                         if (tmp & B43legacy_IRQ_MAC_SUSPENDED)
1958                                 goto out;
1959                         msleep(1);
1960                 }
1961                 b43legacyerr(dev->wl, "MAC suspend failed\n");
1962         }
1963 out:
1964         dev->mac_suspended++;
1965 }
1966
1967 static void b43legacy_adjust_opmode(struct b43legacy_wldev *dev)
1968 {
1969         struct b43legacy_wl *wl = dev->wl;
1970         u32 ctl;
1971         u16 cfp_pretbtt;
1972
1973         ctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
1974         /* Reset status to STA infrastructure mode. */
1975         ctl &= ~B43legacy_MACCTL_AP;
1976         ctl &= ~B43legacy_MACCTL_KEEP_CTL;
1977         ctl &= ~B43legacy_MACCTL_KEEP_BADPLCP;
1978         ctl &= ~B43legacy_MACCTL_KEEP_BAD;
1979         ctl &= ~B43legacy_MACCTL_PROMISC;
1980         ctl &= ~B43legacy_MACCTL_BEACPROMISC;
1981         ctl |= B43legacy_MACCTL_INFRA;
1982
1983         if (b43legacy_is_mode(wl, NL80211_IFTYPE_AP))
1984                 ctl |= B43legacy_MACCTL_AP;
1985         else if (b43legacy_is_mode(wl, NL80211_IFTYPE_ADHOC))
1986                 ctl &= ~B43legacy_MACCTL_INFRA;
1987
1988         if (wl->filter_flags & FIF_CONTROL)
1989                 ctl |= B43legacy_MACCTL_KEEP_CTL;
1990         if (wl->filter_flags & FIF_FCSFAIL)
1991                 ctl |= B43legacy_MACCTL_KEEP_BAD;
1992         if (wl->filter_flags & FIF_PLCPFAIL)
1993                 ctl |= B43legacy_MACCTL_KEEP_BADPLCP;
1994         if (wl->filter_flags & FIF_PROMISC_IN_BSS)
1995                 ctl |= B43legacy_MACCTL_PROMISC;
1996         if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
1997                 ctl |= B43legacy_MACCTL_BEACPROMISC;
1998
1999         /* Workaround: On old hardware the HW-MAC-address-filter
2000          * doesn't work properly, so always run promisc in filter
2001          * it in software. */
2002         if (dev->dev->id.revision <= 4)
2003                 ctl |= B43legacy_MACCTL_PROMISC;
2004
2005         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, ctl);
2006
2007         cfp_pretbtt = 2;
2008         if ((ctl & B43legacy_MACCTL_INFRA) &&
2009             !(ctl & B43legacy_MACCTL_AP)) {
2010                 if (dev->dev->bus->chip_id == 0x4306 &&
2011                     dev->dev->bus->chip_rev == 3)
2012                         cfp_pretbtt = 100;
2013                 else
2014                         cfp_pretbtt = 50;
2015         }
2016         b43legacy_write16(dev, 0x612, cfp_pretbtt);
2017 }
2018
2019 static void b43legacy_rate_memory_write(struct b43legacy_wldev *dev,
2020                                         u16 rate,
2021                                         int is_ofdm)
2022 {
2023         u16 offset;
2024
2025         if (is_ofdm) {
2026                 offset = 0x480;
2027                 offset += (b43legacy_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2028         } else {
2029                 offset = 0x4C0;
2030                 offset += (b43legacy_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2031         }
2032         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, offset + 0x20,
2033                               b43legacy_shm_read16(dev,
2034                               B43legacy_SHM_SHARED, offset));
2035 }
2036
2037 static void b43legacy_rate_memory_init(struct b43legacy_wldev *dev)
2038 {
2039         switch (dev->phy.type) {
2040         case B43legacy_PHYTYPE_G:
2041                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_6MB, 1);
2042                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_12MB, 1);
2043                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_18MB, 1);
2044                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_24MB, 1);
2045                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_36MB, 1);
2046                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_48MB, 1);
2047                 b43legacy_rate_memory_write(dev, B43legacy_OFDM_RATE_54MB, 1);
2048                 /* fallthrough */
2049         case B43legacy_PHYTYPE_B:
2050                 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_1MB, 0);
2051                 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_2MB, 0);
2052                 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_5MB, 0);
2053                 b43legacy_rate_memory_write(dev, B43legacy_CCK_RATE_11MB, 0);
2054                 break;
2055         default:
2056                 B43legacy_BUG_ON(1);
2057         }
2058 }
2059
2060 /* Set the TX-Antenna for management frames sent by firmware. */
2061 static void b43legacy_mgmtframe_txantenna(struct b43legacy_wldev *dev,
2062                                           int antenna)
2063 {
2064         u16 ant = 0;
2065         u16 tmp;
2066
2067         switch (antenna) {
2068         case B43legacy_ANTENNA0:
2069                 ant |= B43legacy_TX4_PHY_ANT0;
2070                 break;
2071         case B43legacy_ANTENNA1:
2072                 ant |= B43legacy_TX4_PHY_ANT1;
2073                 break;
2074         case B43legacy_ANTENNA_AUTO:
2075                 ant |= B43legacy_TX4_PHY_ANTLAST;
2076                 break;
2077         default:
2078                 B43legacy_BUG_ON(1);
2079         }
2080
2081         /* FIXME We also need to set the other flags of the PHY control
2082          * field somewhere. */
2083
2084         /* For Beacons */
2085         tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2086                                    B43legacy_SHM_SH_BEACPHYCTL);
2087         tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
2088         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2089                               B43legacy_SHM_SH_BEACPHYCTL, tmp);
2090         /* For ACK/CTS */
2091         tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2092                                    B43legacy_SHM_SH_ACKCTSPHYCTL);
2093         tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
2094         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2095                               B43legacy_SHM_SH_ACKCTSPHYCTL, tmp);
2096         /* For Probe Resposes */
2097         tmp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2098                                    B43legacy_SHM_SH_PRPHYCTL);
2099         tmp = (tmp & ~B43legacy_TX4_PHY_ANT) | ant;
2100         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2101                               B43legacy_SHM_SH_PRPHYCTL, tmp);
2102 }
2103
2104 /* This is the opposite of b43legacy_chip_init() */
2105 static void b43legacy_chip_exit(struct b43legacy_wldev *dev)
2106 {
2107         b43legacy_radio_turn_off(dev, 1);
2108         b43legacy_gpio_cleanup(dev);
2109         /* firmware is released later */
2110 }
2111
2112 /* Initialize the chip
2113  * http://bcm-specs.sipsolutions.net/ChipInit
2114  */
2115 static int b43legacy_chip_init(struct b43legacy_wldev *dev)
2116 {
2117         struct b43legacy_phy *phy = &dev->phy;
2118         int err;
2119         int tmp;
2120         u32 value32, macctl;
2121         u16 value16;
2122
2123         /* Initialize the MAC control */
2124         macctl = B43legacy_MACCTL_IHR_ENABLED | B43legacy_MACCTL_SHM_ENABLED;
2125         if (dev->phy.gmode)
2126                 macctl |= B43legacy_MACCTL_GMODE;
2127         macctl |= B43legacy_MACCTL_INFRA;
2128         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
2129
2130         err = b43legacy_request_firmware(dev);
2131         if (err)
2132                 goto out;
2133         err = b43legacy_upload_microcode(dev);
2134         if (err)
2135                 goto out; /* firmware is released later */
2136
2137         err = b43legacy_gpio_init(dev);
2138         if (err)
2139                 goto out; /* firmware is released later */
2140
2141         err = b43legacy_upload_initvals(dev);
2142         if (err)
2143                 goto err_gpio_clean;
2144         b43legacy_radio_turn_on(dev);
2145
2146         b43legacy_write16(dev, 0x03E6, 0x0000);
2147         err = b43legacy_phy_init(dev);
2148         if (err)
2149                 goto err_radio_off;
2150
2151         /* Select initial Interference Mitigation. */
2152         tmp = phy->interfmode;
2153         phy->interfmode = B43legacy_INTERFMODE_NONE;
2154         b43legacy_radio_set_interference_mitigation(dev, tmp);
2155
2156         b43legacy_phy_set_antenna_diversity(dev);
2157         b43legacy_mgmtframe_txantenna(dev, B43legacy_ANTENNA_DEFAULT);
2158
2159         if (phy->type == B43legacy_PHYTYPE_B) {
2160                 value16 = b43legacy_read16(dev, 0x005E);
2161                 value16 |= 0x0004;
2162                 b43legacy_write16(dev, 0x005E, value16);
2163         }
2164         b43legacy_write32(dev, 0x0100, 0x01000000);
2165         if (dev->dev->id.revision < 5)
2166                 b43legacy_write32(dev, 0x010C, 0x01000000);
2167
2168         value32 = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2169         value32 &= ~B43legacy_MACCTL_INFRA;
2170         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, value32);
2171         value32 = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2172         value32 |= B43legacy_MACCTL_INFRA;
2173         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, value32);
2174
2175         if (b43legacy_using_pio(dev)) {
2176                 b43legacy_write32(dev, 0x0210, 0x00000100);
2177                 b43legacy_write32(dev, 0x0230, 0x00000100);
2178                 b43legacy_write32(dev, 0x0250, 0x00000100);
2179                 b43legacy_write32(dev, 0x0270, 0x00000100);
2180                 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0034,
2181                                       0x0000);
2182         }
2183
2184         /* Probe Response Timeout value */
2185         /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2186         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED, 0x0074, 0x0000);
2187
2188         /* Initially set the wireless operation mode. */
2189         b43legacy_adjust_opmode(dev);
2190
2191         if (dev->dev->id.revision < 3) {
2192                 b43legacy_write16(dev, 0x060E, 0x0000);
2193                 b43legacy_write16(dev, 0x0610, 0x8000);
2194                 b43legacy_write16(dev, 0x0604, 0x0000);
2195                 b43legacy_write16(dev, 0x0606, 0x0200);
2196         } else {
2197                 b43legacy_write32(dev, 0x0188, 0x80000000);
2198                 b43legacy_write32(dev, 0x018C, 0x02000000);
2199         }
2200         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_REASON, 0x00004000);
2201         b43legacy_write32(dev, B43legacy_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2202         b43legacy_write32(dev, B43legacy_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2203         b43legacy_write32(dev, B43legacy_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2204         b43legacy_write32(dev, B43legacy_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2205         b43legacy_write32(dev, B43legacy_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2206         b43legacy_write32(dev, B43legacy_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2207
2208         value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2209         value32 |= 0x00100000;
2210         ssb_write32(dev->dev, SSB_TMSLOW, value32);
2211
2212         b43legacy_write16(dev, B43legacy_MMIO_POWERUP_DELAY,
2213                           dev->dev->bus->chipco.fast_pwrup_delay);
2214
2215         /* PHY TX errors counter. */
2216         atomic_set(&phy->txerr_cnt, B43legacy_PHY_TX_BADNESS_LIMIT);
2217
2218         B43legacy_WARN_ON(err != 0);
2219         b43legacydbg(dev->wl, "Chip initialized\n");
2220 out:
2221         return err;
2222
2223 err_radio_off:
2224         b43legacy_radio_turn_off(dev, 1);
2225 err_gpio_clean:
2226         b43legacy_gpio_cleanup(dev);
2227         goto out;
2228 }
2229
2230 static void b43legacy_periodic_every120sec(struct b43legacy_wldev *dev)
2231 {
2232         struct b43legacy_phy *phy = &dev->phy;
2233
2234         if (phy->type != B43legacy_PHYTYPE_G || phy->rev < 2)
2235                 return;
2236
2237         b43legacy_mac_suspend(dev);
2238         b43legacy_phy_lo_g_measure(dev);
2239         b43legacy_mac_enable(dev);
2240 }
2241
2242 static void b43legacy_periodic_every60sec(struct b43legacy_wldev *dev)
2243 {
2244         b43legacy_phy_lo_mark_all_unused(dev);
2245         if (dev->dev->bus->sprom.boardflags_lo & B43legacy_BFL_RSSI) {
2246                 b43legacy_mac_suspend(dev);
2247                 b43legacy_calc_nrssi_slope(dev);
2248                 b43legacy_mac_enable(dev);
2249         }
2250 }
2251
2252 static void b43legacy_periodic_every30sec(struct b43legacy_wldev *dev)
2253 {
2254         /* Update device statistics. */
2255         b43legacy_calculate_link_quality(dev);
2256 }
2257
2258 static void b43legacy_periodic_every15sec(struct b43legacy_wldev *dev)
2259 {
2260         b43legacy_phy_xmitpower(dev); /* FIXME: unless scanning? */
2261
2262         atomic_set(&dev->phy.txerr_cnt, B43legacy_PHY_TX_BADNESS_LIMIT);
2263         wmb();
2264 }
2265
2266 static void do_periodic_work(struct b43legacy_wldev *dev)
2267 {
2268         unsigned int state;
2269
2270         state = dev->periodic_state;
2271         if (state % 8 == 0)
2272                 b43legacy_periodic_every120sec(dev);
2273         if (state % 4 == 0)
2274                 b43legacy_periodic_every60sec(dev);
2275         if (state % 2 == 0)
2276                 b43legacy_periodic_every30sec(dev);
2277         b43legacy_periodic_every15sec(dev);
2278 }
2279
2280 /* Periodic work locking policy:
2281  *      The whole periodic work handler is protected by
2282  *      wl->mutex. If another lock is needed somewhere in the
2283  *      pwork callchain, it's acquired in-place, where it's needed.
2284  */
2285 static void b43legacy_periodic_work_handler(struct work_struct *work)
2286 {
2287         struct b43legacy_wldev *dev = container_of(work, struct b43legacy_wldev,
2288                                              periodic_work.work);
2289         struct b43legacy_wl *wl = dev->wl;
2290         unsigned long delay;
2291
2292         mutex_lock(&wl->mutex);
2293
2294         if (unlikely(b43legacy_status(dev) != B43legacy_STAT_STARTED))
2295                 goto out;
2296         if (b43legacy_debug(dev, B43legacy_DBG_PWORK_STOP))
2297                 goto out_requeue;
2298
2299         do_periodic_work(dev);
2300
2301         dev->periodic_state++;
2302 out_requeue:
2303         if (b43legacy_debug(dev, B43legacy_DBG_PWORK_FAST))
2304                 delay = msecs_to_jiffies(50);
2305         else
2306                 delay = round_jiffies_relative(HZ * 15);
2307         ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
2308 out:
2309         mutex_unlock(&wl->mutex);
2310 }
2311
2312 static void b43legacy_periodic_tasks_setup(struct b43legacy_wldev *dev)
2313 {
2314         struct delayed_work *work = &dev->periodic_work;
2315
2316         dev->periodic_state = 0;
2317         INIT_DELAYED_WORK(work, b43legacy_periodic_work_handler);
2318         ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
2319 }
2320
2321 /* Validate access to the chip (SHM) */
2322 static int b43legacy_validate_chipaccess(struct b43legacy_wldev *dev)
2323 {
2324         u32 value;
2325         u32 shm_backup;
2326
2327         shm_backup = b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0);
2328         b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, 0xAA5555AA);
2329         if (b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0) !=
2330                                  0xAA5555AA)
2331                 goto error;
2332         b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, 0x55AAAA55);
2333         if (b43legacy_shm_read32(dev, B43legacy_SHM_SHARED, 0) !=
2334                                  0x55AAAA55)
2335                 goto error;
2336         b43legacy_shm_write32(dev, B43legacy_SHM_SHARED, 0, shm_backup);
2337
2338         value = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
2339         if ((value | B43legacy_MACCTL_GMODE) !=
2340             (B43legacy_MACCTL_GMODE | B43legacy_MACCTL_IHR_ENABLED))
2341                 goto error;
2342
2343         value = b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_REASON);
2344         if (value)
2345                 goto error;
2346
2347         return 0;
2348 error:
2349         b43legacyerr(dev->wl, "Failed to validate the chipaccess\n");
2350         return -ENODEV;
2351 }
2352
2353 static void b43legacy_security_init(struct b43legacy_wldev *dev)
2354 {
2355         dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2356         B43legacy_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2357         dev->ktp = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2358                                         0x0056);
2359         /* KTP is a word address, but we address SHM bytewise.
2360          * So multiply by two.
2361          */
2362         dev->ktp *= 2;
2363         if (dev->dev->id.revision >= 5)
2364                 /* Number of RCMTA address slots */
2365                 b43legacy_write16(dev, B43legacy_MMIO_RCMTA_COUNT,
2366                                   dev->max_nr_keys - 8);
2367 }
2368
2369 #ifdef CONFIG_B43LEGACY_HWRNG
2370 static int b43legacy_rng_read(struct hwrng *rng, u32 *data)
2371 {
2372         struct b43legacy_wl *wl = (struct b43legacy_wl *)rng->priv;
2373         unsigned long flags;
2374
2375         /* Don't take wl->mutex here, as it could deadlock with
2376          * hwrng internal locking. It's not needed to take
2377          * wl->mutex here, anyway. */
2378
2379         spin_lock_irqsave(&wl->irq_lock, flags);
2380         *data = b43legacy_read16(wl->current_dev, B43legacy_MMIO_RNG);
2381         spin_unlock_irqrestore(&wl->irq_lock, flags);
2382
2383         return (sizeof(u16));
2384 }
2385 #endif
2386
2387 static void b43legacy_rng_exit(struct b43legacy_wl *wl)
2388 {
2389 #ifdef CONFIG_B43LEGACY_HWRNG
2390         if (wl->rng_initialized)
2391                 hwrng_unregister(&wl->rng);
2392 #endif
2393 }
2394
2395 static int b43legacy_rng_init(struct b43legacy_wl *wl)
2396 {
2397         int err = 0;
2398
2399 #ifdef CONFIG_B43LEGACY_HWRNG
2400         snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2401                  "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2402         wl->rng.name = wl->rng_name;
2403         wl->rng.data_read = b43legacy_rng_read;
2404         wl->rng.priv = (unsigned long)wl;
2405         wl->rng_initialized = 1;
2406         err = hwrng_register(&wl->rng);
2407         if (err) {
2408                 wl->rng_initialized = 0;
2409                 b43legacyerr(wl, "Failed to register the random "
2410                        "number generator (%d)\n", err);
2411         }
2412
2413 #endif
2414         return err;
2415 }
2416
2417 static int b43legacy_op_tx(struct ieee80211_hw *hw,
2418                            struct sk_buff *skb)
2419 {
2420         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2421         struct b43legacy_wldev *dev = wl->current_dev;
2422         int err = -ENODEV;
2423         unsigned long flags;
2424
2425         if (unlikely(!dev))
2426                 goto out;
2427         if (unlikely(b43legacy_status(dev) < B43legacy_STAT_STARTED))
2428                 goto out;
2429         /* DMA-TX is done without a global lock. */
2430         if (b43legacy_using_pio(dev)) {
2431                 spin_lock_irqsave(&wl->irq_lock, flags);
2432                 err = b43legacy_pio_tx(dev, skb);
2433                 spin_unlock_irqrestore(&wl->irq_lock, flags);
2434         } else
2435                 err = b43legacy_dma_tx(dev, skb);
2436 out:
2437         if (unlikely(err)) {
2438                 /* Drop the packet. */
2439                 dev_kfree_skb_any(skb);
2440         }
2441         return NETDEV_TX_OK;
2442 }
2443
2444 static int b43legacy_op_conf_tx(struct ieee80211_hw *hw, u16 queue,
2445                                 const struct ieee80211_tx_queue_params *params)
2446 {
2447         return 0;
2448 }
2449
2450 static int b43legacy_op_get_stats(struct ieee80211_hw *hw,
2451                                   struct ieee80211_low_level_stats *stats)
2452 {
2453         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2454         unsigned long flags;
2455
2456         spin_lock_irqsave(&wl->irq_lock, flags);
2457         memcpy(stats, &wl->ieee_stats, sizeof(*stats));
2458         spin_unlock_irqrestore(&wl->irq_lock, flags);
2459
2460         return 0;
2461 }
2462
2463 static const char *phymode_to_string(unsigned int phymode)
2464 {
2465         switch (phymode) {
2466         case B43legacy_PHYMODE_B:
2467                 return "B";
2468         case B43legacy_PHYMODE_G:
2469                 return "G";
2470         default:
2471                 B43legacy_BUG_ON(1);
2472         }
2473         return "";
2474 }
2475
2476 static int find_wldev_for_phymode(struct b43legacy_wl *wl,
2477                                   unsigned int phymode,
2478                                   struct b43legacy_wldev **dev,
2479                                   bool *gmode)
2480 {
2481         struct b43legacy_wldev *d;
2482
2483         list_for_each_entry(d, &wl->devlist, list) {
2484                 if (d->phy.possible_phymodes & phymode) {
2485                         /* Ok, this device supports the PHY-mode.
2486                          * Set the gmode bit. */
2487                         *gmode = 1;
2488                         *dev = d;
2489
2490                         return 0;
2491                 }
2492         }
2493
2494         return -ESRCH;
2495 }
2496
2497 static void b43legacy_put_phy_into_reset(struct b43legacy_wldev *dev)
2498 {
2499         struct ssb_device *sdev = dev->dev;
2500         u32 tmslow;
2501
2502         tmslow = ssb_read32(sdev, SSB_TMSLOW);
2503         tmslow &= ~B43legacy_TMSLOW_GMODE;
2504         tmslow |= B43legacy_TMSLOW_PHYRESET;
2505         tmslow |= SSB_TMSLOW_FGC;
2506         ssb_write32(sdev, SSB_TMSLOW, tmslow);
2507         msleep(1);
2508
2509         tmslow = ssb_read32(sdev, SSB_TMSLOW);
2510         tmslow &= ~SSB_TMSLOW_FGC;
2511         tmslow |= B43legacy_TMSLOW_PHYRESET;
2512         ssb_write32(sdev, SSB_TMSLOW, tmslow);
2513         msleep(1);
2514 }
2515
2516 /* Expects wl->mutex locked */
2517 static int b43legacy_switch_phymode(struct b43legacy_wl *wl,
2518                                       unsigned int new_mode)
2519 {
2520         struct b43legacy_wldev *uninitialized_var(up_dev);
2521         struct b43legacy_wldev *down_dev;
2522         int err;
2523         bool gmode = 0;
2524         int prev_status;
2525
2526         err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
2527         if (err) {
2528                 b43legacyerr(wl, "Could not find a device for %s-PHY mode\n",
2529                        phymode_to_string(new_mode));
2530                 return err;
2531         }
2532         if ((up_dev == wl->current_dev) &&
2533             (!!wl->current_dev->phy.gmode == !!gmode))
2534                 /* This device is already running. */
2535                 return 0;
2536         b43legacydbg(wl, "Reconfiguring PHYmode to %s-PHY\n",
2537                phymode_to_string(new_mode));
2538         down_dev = wl->current_dev;
2539
2540         prev_status = b43legacy_status(down_dev);
2541         /* Shutdown the currently running core. */
2542         if (prev_status >= B43legacy_STAT_STARTED)
2543                 b43legacy_wireless_core_stop(down_dev);
2544         if (prev_status >= B43legacy_STAT_INITIALIZED)
2545                 b43legacy_wireless_core_exit(down_dev);
2546
2547         if (down_dev != up_dev)
2548                 /* We switch to a different core, so we put PHY into
2549                  * RESET on the old core. */
2550                 b43legacy_put_phy_into_reset(down_dev);
2551
2552         /* Now start the new core. */
2553         up_dev->phy.gmode = gmode;
2554         if (prev_status >= B43legacy_STAT_INITIALIZED) {
2555                 err = b43legacy_wireless_core_init(up_dev);
2556                 if (err) {
2557                         b43legacyerr(wl, "Fatal: Could not initialize device"
2558                                      " for newly selected %s-PHY mode\n",
2559                                      phymode_to_string(new_mode));
2560                         goto init_failure;
2561                 }
2562         }
2563         if (prev_status >= B43legacy_STAT_STARTED) {
2564                 err = b43legacy_wireless_core_start(up_dev);
2565                 if (err) {
2566                         b43legacyerr(wl, "Fatal: Coult not start device for "
2567                                "newly selected %s-PHY mode\n",
2568                                phymode_to_string(new_mode));
2569                         b43legacy_wireless_core_exit(up_dev);
2570                         goto init_failure;
2571                 }
2572         }
2573         B43legacy_WARN_ON(b43legacy_status(up_dev) != prev_status);
2574
2575         b43legacy_shm_write32(up_dev, B43legacy_SHM_SHARED, 0x003E, 0);
2576
2577         wl->current_dev = up_dev;
2578
2579         return 0;
2580 init_failure:
2581         /* Whoops, failed to init the new core. No core is operating now. */
2582         wl->current_dev = NULL;
2583         return err;
2584 }
2585
2586 /* Write the short and long frame retry limit values. */
2587 static void b43legacy_set_retry_limits(struct b43legacy_wldev *dev,
2588                                        unsigned int short_retry,
2589                                        unsigned int long_retry)
2590 {
2591         /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
2592          * the chip-internal counter. */
2593         short_retry = min(short_retry, (unsigned int)0xF);
2594         long_retry = min(long_retry, (unsigned int)0xF);
2595
2596         b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, 0x0006, short_retry);
2597         b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS, 0x0007, long_retry);
2598 }
2599
2600 static int b43legacy_op_dev_config(struct ieee80211_hw *hw,
2601                                    u32 changed)
2602 {
2603         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2604         struct b43legacy_wldev *dev;
2605         struct b43legacy_phy *phy;
2606         struct ieee80211_conf *conf = &hw->conf;
2607         unsigned long flags;
2608         unsigned int new_phymode = 0xFFFF;
2609         int antenna_tx;
2610         int antenna_rx;
2611         int err = 0;
2612
2613         antenna_tx = B43legacy_ANTENNA_DEFAULT;
2614         antenna_rx = B43legacy_ANTENNA_DEFAULT;
2615
2616         mutex_lock(&wl->mutex);
2617         dev = wl->current_dev;
2618         phy = &dev->phy;
2619
2620         if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
2621                 b43legacy_set_retry_limits(dev,
2622                                            conf->short_frame_max_tx_count,
2623                                            conf->long_frame_max_tx_count);
2624         changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
2625         if (!changed)
2626                 goto out_unlock_mutex;
2627
2628         /* Switch the PHY mode (if necessary). */
2629         switch (conf->channel->band) {
2630         case IEEE80211_BAND_2GHZ:
2631                 if (phy->type == B43legacy_PHYTYPE_B)
2632                         new_phymode = B43legacy_PHYMODE_B;
2633                 else
2634                         new_phymode = B43legacy_PHYMODE_G;
2635                 break;
2636         default:
2637                 B43legacy_WARN_ON(1);
2638         }
2639         err = b43legacy_switch_phymode(wl, new_phymode);
2640         if (err)
2641                 goto out_unlock_mutex;
2642
2643         /* Disable IRQs while reconfiguring the device.
2644          * This makes it possible to drop the spinlock throughout
2645          * the reconfiguration process. */
2646         spin_lock_irqsave(&wl->irq_lock, flags);
2647         if (b43legacy_status(dev) < B43legacy_STAT_STARTED) {
2648                 spin_unlock_irqrestore(&wl->irq_lock, flags);
2649                 goto out_unlock_mutex;
2650         }
2651         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
2652         spin_unlock_irqrestore(&wl->irq_lock, flags);
2653         b43legacy_synchronize_irq(dev);
2654
2655         /* Switch to the requested channel.
2656          * The firmware takes care of races with the TX handler. */
2657         if (conf->channel->hw_value != phy->channel)
2658                 b43legacy_radio_selectchannel(dev, conf->channel->hw_value, 0);
2659
2660         dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_MONITOR);
2661
2662         /* Adjust the desired TX power level. */
2663         if (conf->power_level != 0) {
2664                 if (conf->power_level != phy->power_level) {
2665                         phy->power_level = conf->power_level;
2666                         b43legacy_phy_xmitpower(dev);
2667                 }
2668         }
2669
2670         /* Antennas for RX and management frame TX. */
2671         b43legacy_mgmtframe_txantenna(dev, antenna_tx);
2672
2673         if (wl->radio_enabled != phy->radio_on) {
2674                 if (wl->radio_enabled) {
2675                         b43legacy_radio_turn_on(dev);
2676                         b43legacyinfo(dev->wl, "Radio turned on by software\n");
2677                         if (!dev->radio_hw_enable)
2678                                 b43legacyinfo(dev->wl, "The hardware RF-kill"
2679                                               " button still turns the radio"
2680                                               " physically off. Press the"
2681                                               " button to turn it on.\n");
2682                 } else {
2683                         b43legacy_radio_turn_off(dev, 0);
2684                         b43legacyinfo(dev->wl, "Radio turned off by"
2685                                       " software\n");
2686                 }
2687         }
2688
2689         spin_lock_irqsave(&wl->irq_lock, flags);
2690         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, dev->irq_mask);
2691         mmiowb();
2692         spin_unlock_irqrestore(&wl->irq_lock, flags);
2693 out_unlock_mutex:
2694         mutex_unlock(&wl->mutex);
2695
2696         return err;
2697 }
2698
2699 static void b43legacy_update_basic_rates(struct b43legacy_wldev *dev, u32 brates)
2700 {
2701         struct ieee80211_supported_band *sband =
2702                 dev->wl->hw->wiphy->bands[IEEE80211_BAND_2GHZ];
2703         struct ieee80211_rate *rate;
2704         int i;
2705         u16 basic, direct, offset, basic_offset, rateptr;
2706
2707         for (i = 0; i < sband->n_bitrates; i++) {
2708                 rate = &sband->bitrates[i];
2709
2710                 if (b43legacy_is_cck_rate(rate->hw_value)) {
2711                         direct = B43legacy_SHM_SH_CCKDIRECT;
2712                         basic = B43legacy_SHM_SH_CCKBASIC;
2713                         offset = b43legacy_plcp_get_ratecode_cck(rate->hw_value);
2714                         offset &= 0xF;
2715                 } else {
2716                         direct = B43legacy_SHM_SH_OFDMDIRECT;
2717                         basic = B43legacy_SHM_SH_OFDMBASIC;
2718                         offset = b43legacy_plcp_get_ratecode_ofdm(rate->hw_value);
2719                         offset &= 0xF;
2720                 }
2721
2722                 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
2723
2724                 if (b43legacy_is_cck_rate(rate->hw_value)) {
2725                         basic_offset = b43legacy_plcp_get_ratecode_cck(rate->hw_value);
2726                         basic_offset &= 0xF;
2727                 } else {
2728                         basic_offset = b43legacy_plcp_get_ratecode_ofdm(rate->hw_value);
2729                         basic_offset &= 0xF;
2730                 }
2731
2732                 /*
2733                  * Get the pointer that we need to point to
2734                  * from the direct map
2735                  */
2736                 rateptr = b43legacy_shm_read16(dev, B43legacy_SHM_SHARED,
2737                                                direct + 2 * basic_offset);
2738                 /* and write it to the basic map */
2739                 b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
2740                                       basic + 2 * offset, rateptr);
2741         }
2742 }
2743
2744 static void b43legacy_op_bss_info_changed(struct ieee80211_hw *hw,
2745                                     struct ieee80211_vif *vif,
2746                                     struct ieee80211_bss_conf *conf,
2747                                     u32 changed)
2748 {
2749         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2750         struct b43legacy_wldev *dev;
2751         struct b43legacy_phy *phy;
2752         unsigned long flags;
2753
2754         mutex_lock(&wl->mutex);
2755         B43legacy_WARN_ON(wl->vif != vif);
2756
2757         dev = wl->current_dev;
2758         phy = &dev->phy;
2759
2760         /* Disable IRQs while reconfiguring the device.
2761          * This makes it possible to drop the spinlock throughout
2762          * the reconfiguration process. */
2763         spin_lock_irqsave(&wl->irq_lock, flags);
2764         if (b43legacy_status(dev) < B43legacy_STAT_STARTED) {
2765                 spin_unlock_irqrestore(&wl->irq_lock, flags);
2766                 goto out_unlock_mutex;
2767         }
2768         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
2769
2770         if (changed & BSS_CHANGED_BSSID) {
2771                 b43legacy_synchronize_irq(dev);
2772
2773                 if (conf->bssid)
2774                         memcpy(wl->bssid, conf->bssid, ETH_ALEN);
2775                 else
2776                         memset(wl->bssid, 0, ETH_ALEN);
2777         }
2778
2779         if (b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED) {
2780                 if (changed & BSS_CHANGED_BEACON &&
2781                     (b43legacy_is_mode(wl, NL80211_IFTYPE_AP) ||
2782                      b43legacy_is_mode(wl, NL80211_IFTYPE_ADHOC)))
2783                         b43legacy_update_templates(wl);
2784
2785                 if (changed & BSS_CHANGED_BSSID)
2786                         b43legacy_write_mac_bssid_templates(dev);
2787         }
2788         spin_unlock_irqrestore(&wl->irq_lock, flags);
2789
2790         b43legacy_mac_suspend(dev);
2791
2792         if (changed & BSS_CHANGED_BEACON_INT &&
2793             (b43legacy_is_mode(wl, NL80211_IFTYPE_AP) ||
2794              b43legacy_is_mode(wl, NL80211_IFTYPE_ADHOC)))
2795                 b43legacy_set_beacon_int(dev, conf->beacon_int);
2796
2797         if (changed & BSS_CHANGED_BASIC_RATES)
2798                 b43legacy_update_basic_rates(dev, conf->basic_rates);
2799
2800         if (changed & BSS_CHANGED_ERP_SLOT) {
2801                 if (conf->use_short_slot)
2802                         b43legacy_short_slot_timing_enable(dev);
2803                 else
2804                         b43legacy_short_slot_timing_disable(dev);
2805         }
2806
2807         b43legacy_mac_enable(dev);
2808
2809         spin_lock_irqsave(&wl->irq_lock, flags);
2810         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, dev->irq_mask);
2811         /* XXX: why? */
2812         mmiowb();
2813         spin_unlock_irqrestore(&wl->irq_lock, flags);
2814  out_unlock_mutex:
2815         mutex_unlock(&wl->mutex);
2816 }
2817
2818 static void b43legacy_op_configure_filter(struct ieee80211_hw *hw,
2819                                           unsigned int changed,
2820                                           unsigned int *fflags,u64 multicast)
2821 {
2822         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
2823         struct b43legacy_wldev *dev = wl->current_dev;
2824         unsigned long flags;
2825
2826         if (!dev) {
2827                 *fflags = 0;
2828                 return;
2829         }
2830
2831         spin_lock_irqsave(&wl->irq_lock, flags);
2832         *fflags &= FIF_PROMISC_IN_BSS |
2833                   FIF_ALLMULTI |
2834                   FIF_FCSFAIL |
2835                   FIF_PLCPFAIL |
2836                   FIF_CONTROL |
2837                   FIF_OTHER_BSS |
2838                   FIF_BCN_PRBRESP_PROMISC;
2839
2840         changed &= FIF_PROMISC_IN_BSS |
2841                    FIF_ALLMULTI |
2842                    FIF_FCSFAIL |
2843                    FIF_PLCPFAIL |
2844                    FIF_CONTROL |
2845                    FIF_OTHER_BSS |
2846                    FIF_BCN_PRBRESP_PROMISC;
2847
2848         wl->filter_flags = *fflags;
2849
2850         if (changed && b43legacy_status(dev) >= B43legacy_STAT_INITIALIZED)
2851                 b43legacy_adjust_opmode(dev);
2852         spin_unlock_irqrestore(&wl->irq_lock, flags);
2853 }
2854
2855 /* Locking: wl->mutex */
2856 static void b43legacy_wireless_core_stop(struct b43legacy_wldev *dev)
2857 {
2858         struct b43legacy_wl *wl = dev->wl;
2859         unsigned long flags;
2860
2861         if (b43legacy_status(dev) < B43legacy_STAT_STARTED)
2862                 return;
2863
2864         /* Disable and sync interrupts. We must do this before than
2865          * setting the status to INITIALIZED, as the interrupt handler
2866          * won't care about IRQs then. */
2867         spin_lock_irqsave(&wl->irq_lock, flags);
2868         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, 0);
2869         b43legacy_read32(dev, B43legacy_MMIO_GEN_IRQ_MASK); /* flush */
2870         spin_unlock_irqrestore(&wl->irq_lock, flags);
2871         b43legacy_synchronize_irq(dev);
2872
2873         b43legacy_set_status(dev, B43legacy_STAT_INITIALIZED);
2874
2875         mutex_unlock(&wl->mutex);
2876         /* Must unlock as it would otherwise deadlock. No races here.
2877          * Cancel the possibly running self-rearming periodic work. */
2878         cancel_delayed_work_sync(&dev->periodic_work);
2879         mutex_lock(&wl->mutex);
2880
2881         ieee80211_stop_queues(wl->hw); /* FIXME this could cause a deadlock */
2882
2883         b43legacy_mac_suspend(dev);
2884         free_irq(dev->dev->irq, dev);
2885         b43legacydbg(wl, "Wireless interface stopped\n");
2886 }
2887
2888 /* Locking: wl->mutex */
2889 static int b43legacy_wireless_core_start(struct b43legacy_wldev *dev)
2890 {
2891         int err;
2892
2893         B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_INITIALIZED);
2894
2895         drain_txstatus_queue(dev);
2896         err = request_irq(dev->dev->irq, b43legacy_interrupt_handler,
2897                           IRQF_SHARED, KBUILD_MODNAME, dev);
2898         if (err) {
2899                 b43legacyerr(dev->wl, "Cannot request IRQ-%d\n",
2900                        dev->dev->irq);
2901                 goto out;
2902         }
2903         /* We are ready to run. */
2904         ieee80211_wake_queues(dev->wl->hw);
2905         b43legacy_set_status(dev, B43legacy_STAT_STARTED);
2906
2907         /* Start data flow (TX/RX) */
2908         b43legacy_mac_enable(dev);
2909         b43legacy_write32(dev, B43legacy_MMIO_GEN_IRQ_MASK, dev->irq_mask);
2910
2911         /* Start maintenance work */
2912         b43legacy_periodic_tasks_setup(dev);
2913
2914         b43legacydbg(dev->wl, "Wireless interface started\n");
2915 out:
2916         return err;
2917 }
2918
2919 /* Get PHY and RADIO versioning numbers */
2920 static int b43legacy_phy_versioning(struct b43legacy_wldev *dev)
2921 {
2922         struct b43legacy_phy *phy = &dev->phy;
2923         u32 tmp;
2924         u8 analog_type;
2925         u8 phy_type;
2926         u8 phy_rev;
2927         u16 radio_manuf;
2928         u16 radio_ver;
2929         u16 radio_rev;
2930         int unsupported = 0;
2931
2932         /* Get PHY versioning */
2933         tmp = b43legacy_read16(dev, B43legacy_MMIO_PHY_VER);
2934         analog_type = (tmp & B43legacy_PHYVER_ANALOG)
2935                       >> B43legacy_PHYVER_ANALOG_SHIFT;
2936         phy_type = (tmp & B43legacy_PHYVER_TYPE) >> B43legacy_PHYVER_TYPE_SHIFT;
2937         phy_rev = (tmp & B43legacy_PHYVER_VERSION);
2938         switch (phy_type) {
2939         case B43legacy_PHYTYPE_B:
2940                 if (phy_rev != 2 && phy_rev != 4
2941                     && phy_rev != 6 && phy_rev != 7)
2942                         unsupported = 1;
2943                 break;
2944         case B43legacy_PHYTYPE_G:
2945                 if (phy_rev > 8)
2946                         unsupported = 1;
2947                 break;
2948         default:
2949                 unsupported = 1;
2950         };
2951         if (unsupported) {
2952                 b43legacyerr(dev->wl, "FOUND UNSUPPORTED PHY "
2953                        "(Analog %u, Type %u, Revision %u)\n",
2954                        analog_type, phy_type, phy_rev);
2955                 return -EOPNOTSUPP;
2956         }
2957         b43legacydbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
2958                analog_type, phy_type, phy_rev);
2959
2960
2961         /* Get RADIO versioning */
2962         if (dev->dev->bus->chip_id == 0x4317) {
2963                 if (dev->dev->bus->chip_rev == 0)
2964                         tmp = 0x3205017F;
2965                 else if (dev->dev->bus->chip_rev == 1)
2966                         tmp = 0x4205017F;
2967                 else
2968                         tmp = 0x5205017F;
2969         } else {
2970                 b43legacy_write16(dev, B43legacy_MMIO_RADIO_CONTROL,
2971                                   B43legacy_RADIOCTL_ID);
2972                 tmp = b43legacy_read16(dev, B43legacy_MMIO_RADIO_DATA_HIGH);
2973                 tmp <<= 16;
2974                 b43legacy_write16(dev, B43legacy_MMIO_RADIO_CONTROL,
2975                                   B43legacy_RADIOCTL_ID);
2976                 tmp |= b43legacy_read16(dev, B43legacy_MMIO_RADIO_DATA_LOW);
2977         }
2978         radio_manuf = (tmp & 0x00000FFF);
2979         radio_ver = (tmp & 0x0FFFF000) >> 12;
2980         radio_rev = (tmp & 0xF0000000) >> 28;
2981         switch (phy_type) {
2982         case B43legacy_PHYTYPE_B:
2983                 if ((radio_ver & 0xFFF0) != 0x2050)
2984                         unsupported = 1;
2985                 break;
2986         case B43legacy_PHYTYPE_G:
2987                 if (radio_ver != 0x2050)
2988                         unsupported = 1;
2989                 break;
2990         default:
2991                 B43legacy_BUG_ON(1);
2992         }
2993         if (unsupported) {
2994                 b43legacyerr(dev->wl, "FOUND UNSUPPORTED RADIO "
2995                        "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
2996                        radio_manuf, radio_ver, radio_rev);
2997                 return -EOPNOTSUPP;
2998         }
2999         b43legacydbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X,"
3000                      " Revision %u\n", radio_manuf, radio_ver, radio_rev);
3001
3002
3003         phy->radio_manuf = radio_manuf;
3004         phy->radio_ver = radio_ver;
3005         phy->radio_rev = radio_rev;
3006
3007         phy->analog = analog_type;
3008         phy->type = phy_type;
3009         phy->rev = phy_rev;
3010
3011         return 0;
3012 }
3013
3014 static void setup_struct_phy_for_init(struct b43legacy_wldev *dev,
3015                                       struct b43legacy_phy *phy)
3016 {
3017         struct b43legacy_lopair *lo;
3018         int i;
3019
3020         memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3021         memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3022
3023         /* Assume the radio is enabled. If it's not enabled, the state will
3024          * immediately get fixed on the first periodic work run. */
3025         dev->radio_hw_enable = 1;
3026
3027         phy->savedpctlreg = 0xFFFF;
3028         phy->aci_enable = 0;
3029         phy->aci_wlan_automatic = 0;
3030         phy->aci_hw_rssi = 0;
3031
3032         lo = phy->_lo_pairs;
3033         if (lo)
3034                 memset(lo, 0, sizeof(struct b43legacy_lopair) *
3035                                      B43legacy_LO_COUNT);
3036         phy->max_lb_gain = 0;
3037         phy->trsw_rx_gain = 0;
3038
3039         /* Set default attenuation values. */
3040         phy->bbatt = b43legacy_default_baseband_attenuation(dev);
3041         phy->rfatt = b43legacy_default_radio_attenuation(dev);
3042         phy->txctl1 = b43legacy_default_txctl1(dev);
3043         phy->txpwr_offset = 0;
3044
3045         /* NRSSI */
3046         phy->nrssislope = 0;
3047         for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3048                 phy->nrssi[i] = -1000;
3049         for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3050                 phy->nrssi_lt[i] = i;
3051
3052         phy->lofcal = 0xFFFF;
3053         phy->initval = 0xFFFF;
3054
3055         phy->interfmode = B43legacy_INTERFMODE_NONE;
3056         phy->channel = 0xFF;
3057 }
3058
3059 static void setup_struct_wldev_for_init(struct b43legacy_wldev *dev)
3060 {
3061         /* Flags */
3062         dev->dfq_valid = 0;
3063
3064         /* Stats */
3065         memset(&dev->stats, 0, sizeof(dev->stats));
3066
3067         setup_struct_phy_for_init(dev, &dev->phy);
3068
3069         /* IRQ related flags */
3070         dev->irq_reason = 0;
3071         memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3072         dev->irq_mask = B43legacy_IRQ_MASKTEMPLATE;
3073
3074         dev->mac_suspended = 1;
3075
3076         /* Noise calculation context */
3077         memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3078 }
3079
3080 static void b43legacy_imcfglo_timeouts_workaround(struct b43legacy_wldev *dev)
3081 {
3082 #ifdef CONFIG_SSB_DRIVER_PCICORE
3083         struct ssb_bus *bus = dev->dev->bus;
3084         u32 tmp;
3085
3086         if (bus->pcicore.dev &&
3087             bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
3088             bus->pcicore.dev->id.revision <= 5) {
3089                 /* IMCFGLO timeouts workaround. */
3090                 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
3091                 switch (bus->bustype) {
3092                 case SSB_BUSTYPE_PCI:
3093                 case SSB_BUSTYPE_PCMCIA:
3094                         tmp &= ~SSB_IMCFGLO_REQTO;
3095                         tmp &= ~SSB_IMCFGLO_SERTO;
3096                         tmp |= 0x32;
3097                         break;
3098                 case SSB_BUSTYPE_SSB:
3099                         tmp &= ~SSB_IMCFGLO_REQTO;
3100                         tmp &= ~SSB_IMCFGLO_SERTO;
3101                         tmp |= 0x53;
3102                         break;
3103                 default:
3104                         break;
3105                 }
3106                 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
3107         }
3108 #endif /* CONFIG_SSB_DRIVER_PCICORE */
3109 }
3110
3111 static void b43legacy_set_synth_pu_delay(struct b43legacy_wldev *dev,
3112                                           bool idle) {
3113         u16 pu_delay = 1050;
3114
3115         if (b43legacy_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
3116                 pu_delay = 500;
3117         if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
3118                 pu_delay = max(pu_delay, (u16)2400);
3119
3120         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3121                               B43legacy_SHM_SH_SPUWKUP, pu_delay);
3122 }
3123
3124 /* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
3125 static void b43legacy_set_pretbtt(struct b43legacy_wldev *dev)
3126 {
3127         u16 pretbtt;
3128
3129         /* The time value is in microseconds. */
3130         if (b43legacy_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
3131                 pretbtt = 2;
3132         else
3133                 pretbtt = 250;
3134         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3135                               B43legacy_SHM_SH_PRETBTT, pretbtt);
3136         b43legacy_write16(dev, B43legacy_MMIO_TSF_CFP_PRETBTT, pretbtt);
3137 }
3138
3139 /* Shutdown a wireless core */
3140 /* Locking: wl->mutex */
3141 static void b43legacy_wireless_core_exit(struct b43legacy_wldev *dev)
3142 {
3143         struct b43legacy_phy *phy = &dev->phy;
3144         u32 macctl;
3145
3146         B43legacy_WARN_ON(b43legacy_status(dev) > B43legacy_STAT_INITIALIZED);
3147         if (b43legacy_status(dev) != B43legacy_STAT_INITIALIZED)
3148                 return;
3149         b43legacy_set_status(dev, B43legacy_STAT_UNINIT);
3150
3151         /* Stop the microcode PSM. */
3152         macctl = b43legacy_read32(dev, B43legacy_MMIO_MACCTL);
3153         macctl &= ~B43legacy_MACCTL_PSM_RUN;
3154         macctl |= B43legacy_MACCTL_PSM_JMP0;
3155         b43legacy_write32(dev, B43legacy_MMIO_MACCTL, macctl);
3156
3157         b43legacy_leds_exit(dev);
3158         b43legacy_rng_exit(dev->wl);
3159         b43legacy_pio_free(dev);
3160         b43legacy_dma_free(dev);
3161         b43legacy_chip_exit(dev);
3162         b43legacy_radio_turn_off(dev, 1);
3163         b43legacy_switch_analog(dev, 0);
3164         if (phy->dyn_tssi_tbl)
3165                 kfree(phy->tssi2dbm);
3166         kfree(phy->lo_control);
3167         phy->lo_control = NULL;
3168         if (dev->wl->current_beacon) {
3169                 dev_kfree_skb_any(dev->wl->current_beacon);
3170                 dev->wl->current_beacon = NULL;
3171         }
3172
3173         ssb_device_disable(dev->dev, 0);
3174         ssb_bus_may_powerdown(dev->dev->bus);
3175 }
3176
3177 static void prepare_phy_data_for_init(struct b43legacy_wldev *dev)
3178 {
3179         struct b43legacy_phy *phy = &dev->phy;
3180         int i;
3181
3182         /* Set default attenuation values. */
3183         phy->bbatt = b43legacy_default_baseband_attenuation(dev);
3184         phy->rfatt = b43legacy_default_radio_attenuation(dev);
3185         phy->txctl1 = b43legacy_default_txctl1(dev);
3186         phy->txctl2 = 0xFFFF;
3187         phy->txpwr_offset = 0;
3188
3189         /* NRSSI */
3190         phy->nrssislope = 0;
3191         for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3192                 phy->nrssi[i] = -1000;
3193         for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3194                 phy->nrssi_lt[i] = i;
3195
3196         phy->lofcal = 0xFFFF;
3197         phy->initval = 0xFFFF;
3198
3199         phy->aci_enable = 0;
3200         phy->aci_wlan_automatic = 0;
3201         phy->aci_hw_rssi = 0;
3202
3203         phy->antenna_diversity = 0xFFFF;
3204         memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3205         memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3206
3207         /* Flags */
3208         phy->calibrated = 0;
3209
3210         if (phy->_lo_pairs)
3211                 memset(phy->_lo_pairs, 0,
3212                        sizeof(struct b43legacy_lopair) * B43legacy_LO_COUNT);
3213         memset(phy->loopback_gain, 0, sizeof(phy->loopback_gain));
3214 }
3215
3216 /* Initialize a wireless core */
3217 static int b43legacy_wireless_core_init(struct b43legacy_wldev *dev)
3218 {
3219         struct b43legacy_wl *wl = dev->wl;
3220         struct ssb_bus *bus = dev->dev->bus;
3221         struct b43legacy_phy *phy = &dev->phy;
3222         struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3223         int err;
3224         u32 hf;
3225         u32 tmp;
3226
3227         B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_UNINIT);
3228
3229         err = ssb_bus_powerup(bus, 0);
3230         if (err)
3231                 goto out;
3232         if (!ssb_device_is_enabled(dev->dev)) {
3233                 tmp = phy->gmode ? B43legacy_TMSLOW_GMODE : 0;
3234                 b43legacy_wireless_core_reset(dev, tmp);
3235         }
3236
3237         if ((phy->type == B43legacy_PHYTYPE_B) ||
3238             (phy->type == B43legacy_PHYTYPE_G)) {
3239                 phy->_lo_pairs = kzalloc(sizeof(struct b43legacy_lopair)
3240                                          * B43legacy_LO_COUNT,
3241                                          GFP_KERNEL);
3242                 if (!phy->_lo_pairs)
3243                         return -ENOMEM;
3244         }
3245         setup_struct_wldev_for_init(dev);
3246
3247         err = b43legacy_phy_init_tssi2dbm_table(dev);
3248         if (err)
3249                 goto err_kfree_lo_control;
3250
3251         /* Enable IRQ routing to this device. */
3252         ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3253
3254         b43legacy_imcfglo_timeouts_workaround(dev);
3255         prepare_phy_data_for_init(dev);
3256         b43legacy_phy_calibrate(dev);
3257         err = b43legacy_chip_init(dev);
3258         if (err)
3259                 goto err_kfree_tssitbl;
3260         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3261                               B43legacy_SHM_SH_WLCOREREV,
3262                               dev->dev->id.revision);
3263         hf = b43legacy_hf_read(dev);
3264         if (phy->type == B43legacy_PHYTYPE_G) {
3265                 hf |= B43legacy_HF_SYMW;
3266                 if (phy->rev == 1)
3267                         hf |= B43legacy_HF_GDCW;
3268                 if (sprom->boardflags_lo & B43legacy_BFL_PACTRL)
3269                         hf |= B43legacy_HF_OFDMPABOOST;
3270         } else if (phy->type == B43legacy_PHYTYPE_B) {
3271                 hf |= B43legacy_HF_SYMW;
3272                 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
3273                         hf &= ~B43legacy_HF_GDCW;
3274         }
3275         b43legacy_hf_write(dev, hf);
3276
3277         b43legacy_set_retry_limits(dev,
3278                                    B43legacy_DEFAULT_SHORT_RETRY_LIMIT,
3279                                    B43legacy_DEFAULT_LONG_RETRY_LIMIT);
3280
3281         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3282                               0x0044, 3);
3283         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3284                               0x0046, 2);
3285
3286         /* Disable sending probe responses from firmware.
3287          * Setting the MaxTime to one usec will always trigger
3288          * a timeout, so we never send any probe resp.
3289          * A timeout of zero is infinite. */
3290         b43legacy_shm_write16(dev, B43legacy_SHM_SHARED,
3291                               B43legacy_SHM_SH_PRMAXTIME, 1);
3292
3293         b43legacy_rate_memory_init(dev);
3294
3295         /* Minimum Contention Window */
3296         if (phy->type == B43legacy_PHYTYPE_B)
3297                 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
3298                                       0x0003, 31);
3299         else
3300                 b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
3301                                       0x0003, 15);
3302         /* Maximum Contention Window */
3303         b43legacy_shm_write16(dev, B43legacy_SHM_WIRELESS,
3304                               0x0004, 1023);
3305
3306         do {
3307                 if (b43legacy_using_pio(dev))
3308                         err = b43legacy_pio_init(dev);
3309                 else {
3310                         err = b43legacy_dma_init(dev);
3311                         if (!err)
3312                                 b43legacy_qos_init(dev);
3313                 }
3314         } while (err == -EAGAIN);
3315         if (err)
3316                 goto err_chip_exit;
3317
3318         b43legacy_set_synth_pu_delay(dev, 1);
3319
3320         ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
3321         b43legacy_upload_card_macaddress(dev);
3322         b43legacy_security_init(dev);
3323         b43legacy_rng_init(wl);
3324
3325         ieee80211_wake_queues(dev->wl->hw);
3326         b43legacy_set_status(dev, B43legacy_STAT_INITIALIZED);
3327
3328         b43legacy_leds_init(dev);
3329 out:
3330         return err;
3331
3332 err_chip_exit:
3333         b43legacy_chip_exit(dev);
3334 err_kfree_tssitbl:
3335         if (phy->dyn_tssi_tbl)
3336                 kfree(phy->tssi2dbm);
3337 err_kfree_lo_control:
3338         kfree(phy->lo_control);
3339         phy->lo_control = NULL;
3340         ssb_bus_may_powerdown(bus);
3341         B43legacy_WARN_ON(b43legacy_status(dev) != B43legacy_STAT_UNINIT);
3342         return err;
3343 }
3344
3345 static int b43legacy_op_add_interface(struct ieee80211_hw *hw,
3346                                       struct ieee80211_vif *vif)
3347 {
3348         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3349         struct b43legacy_wldev *dev;
3350         unsigned long flags;
3351         int err = -EOPNOTSUPP;
3352
3353         /* TODO: allow WDS/AP devices to coexist */
3354
3355         if (vif->type != NL80211_IFTYPE_AP &&
3356             vif->type != NL80211_IFTYPE_STATION &&
3357             vif->type != NL80211_IFTYPE_WDS &&
3358             vif->type != NL80211_IFTYPE_ADHOC)
3359                 return -EOPNOTSUPP;
3360
3361         mutex_lock(&wl->mutex);
3362         if (wl->operating)
3363                 goto out_mutex_unlock;
3364
3365         b43legacydbg(wl, "Adding Interface type %d\n", vif->type);
3366
3367         dev = wl->current_dev;
3368         wl->operating = 1;
3369         wl->vif = vif;
3370         wl->if_type = vif->type;
3371         memcpy(wl->mac_addr, vif->addr, ETH_ALEN);
3372
3373         spin_lock_irqsave(&wl->irq_lock, flags);
3374         b43legacy_adjust_opmode(dev);
3375         b43legacy_set_pretbtt(dev);
3376         b43legacy_set_synth_pu_delay(dev, 0);
3377         b43legacy_upload_card_macaddress(dev);
3378         spin_unlock_irqrestore(&wl->irq_lock, flags);
3379
3380         err = 0;
3381  out_mutex_unlock:
3382         mutex_unlock(&wl->mutex);
3383
3384         return err;
3385 }
3386
3387 static void b43legacy_op_remove_interface(struct ieee80211_hw *hw,
3388                                           struct ieee80211_vif *vif)
3389 {
3390         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3391         struct b43legacy_wldev *dev = wl->current_dev;
3392         unsigned long flags;
3393
3394         b43legacydbg(wl, "Removing Interface type %d\n", vif->type);
3395
3396         mutex_lock(&wl->mutex);
3397
3398         B43legacy_WARN_ON(!wl->operating);
3399         B43legacy_WARN_ON(wl->vif != vif);
3400         wl->vif = NULL;
3401
3402         wl->operating = 0;
3403
3404         spin_lock_irqsave(&wl->irq_lock, flags);
3405         b43legacy_adjust_opmode(dev);
3406         memset(wl->mac_addr, 0, ETH_ALEN);
3407         b43legacy_upload_card_macaddress(dev);
3408         spin_unlock_irqrestore(&wl->irq_lock, flags);
3409
3410         mutex_unlock(&wl->mutex);
3411 }
3412
3413 static int b43legacy_op_start(struct ieee80211_hw *hw)
3414 {
3415         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3416         struct b43legacy_wldev *dev = wl->current_dev;
3417         int did_init = 0;
3418         int err = 0;
3419
3420         /* Kill all old instance specific information to make sure
3421          * the card won't use it in the short timeframe between start
3422          * and mac80211 reconfiguring it. */
3423         memset(wl->bssid, 0, ETH_ALEN);
3424         memset(wl->mac_addr, 0, ETH_ALEN);
3425         wl->filter_flags = 0;
3426         wl->beacon0_uploaded = 0;
3427         wl->beacon1_uploaded = 0;
3428         wl->beacon_templates_virgin = 1;
3429         wl->radio_enabled = 1;
3430
3431         mutex_lock(&wl->mutex);
3432
3433         if (b43legacy_status(dev) < B43legacy_STAT_INITIALIZED) {
3434                 err = b43legacy_wireless_core_init(dev);
3435                 if (err)
3436                         goto out_mutex_unlock;
3437                 did_init = 1;
3438         }
3439
3440         if (b43legacy_status(dev) < B43legacy_STAT_STARTED) {
3441                 err = b43legacy_wireless_core_start(dev);
3442                 if (err) {
3443                         if (did_init)
3444                                 b43legacy_wireless_core_exit(dev);
3445                         goto out_mutex_unlock;
3446                 }
3447         }
3448
3449         wiphy_rfkill_start_polling(hw->wiphy);
3450
3451 out_mutex_unlock:
3452         mutex_unlock(&wl->mutex);
3453
3454         return err;
3455 }
3456
3457 static void b43legacy_op_stop(struct ieee80211_hw *hw)
3458 {
3459         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3460         struct b43legacy_wldev *dev = wl->current_dev;
3461
3462         cancel_work_sync(&(wl->beacon_update_trigger));
3463
3464         mutex_lock(&wl->mutex);
3465         if (b43legacy_status(dev) >= B43legacy_STAT_STARTED)
3466                 b43legacy_wireless_core_stop(dev);
3467         b43legacy_wireless_core_exit(dev);
3468         wl->radio_enabled = 0;
3469         mutex_unlock(&wl->mutex);
3470 }
3471
3472 static int b43legacy_op_beacon_set_tim(struct ieee80211_hw *hw,
3473                                        struct ieee80211_sta *sta, bool set)
3474 {
3475         struct b43legacy_wl *wl = hw_to_b43legacy_wl(hw);
3476         unsigned long flags;
3477
3478         spin_lock_irqsave(&wl->irq_lock, flags);
3479         b43legacy_update_templates(wl);
3480         spin_unlock_irqrestore(&wl->irq_lock, flags);
3481
3482         return 0;
3483 }
3484
3485 static const struct ieee80211_ops b43legacy_hw_ops = {
3486         .tx                     = b43legacy_op_tx,
3487         .conf_tx                = b43legacy_op_conf_tx,
3488         .add_interface          = b43legacy_op_add_interface,
3489         .remove_interface       = b43legacy_op_remove_interface,
3490         .config                 = b43legacy_op_dev_config,
3491         .bss_info_changed       = b43legacy_op_bss_info_changed,
3492         .configure_filter       = b43legacy_op_configure_filter,
3493         .get_stats              = b43legacy_op_get_stats,
3494         .start                  = b43legacy_op_start,
3495         .stop                   = b43legacy_op_stop,
3496         .set_tim                = b43legacy_op_beacon_set_tim,
3497         .rfkill_poll            = b43legacy_rfkill_poll,
3498 };
3499
3500 /* Hard-reset the chip. Do not call this directly.
3501  * Use b43legacy_controller_restart()
3502  */
3503 static void b43legacy_chip_reset(struct work_struct *work)
3504 {
3505         struct b43legacy_wldev *dev =
3506                 container_of(work, struct b43legacy_wldev, restart_work);
3507         struct b43legacy_wl *wl = dev->wl;
3508         int err = 0;
3509         int prev_status;
3510
3511         mutex_lock(&wl->mutex);
3512
3513         prev_status = b43legacy_status(dev);
3514         /* Bring the device down... */
3515         if (prev_status >= B43legacy_STAT_STARTED)
3516                 b43legacy_wireless_core_stop(dev);
3517         if (prev_status >= B43legacy_STAT_INITIALIZED)
3518                 b43legacy_wireless_core_exit(dev);
3519
3520         /* ...and up again. */
3521         if (prev_status >= B43legacy_STAT_INITIALIZED) {
3522                 err = b43legacy_wireless_core_init(dev);
3523                 if (err)
3524                         goto out;
3525         }
3526         if (prev_status >= B43legacy_STAT_STARTED) {
3527                 err = b43legacy_wireless_core_start(dev);
3528                 if (err) {
3529                         b43legacy_wireless_core_exit(dev);
3530                         goto out;
3531                 }
3532         }
3533 out:
3534         if (err)
3535                 wl->current_dev = NULL; /* Failed to init the dev. */
3536         mutex_unlock(&wl->mutex);
3537         if (err)
3538                 b43legacyerr(wl, "Controller restart FAILED\n");
3539         else
3540                 b43legacyinfo(wl, "Controller restarted\n");
3541 }
3542
3543 static int b43legacy_setup_modes(struct b43legacy_wldev *dev,
3544                                  int have_bphy,
3545                                  int have_gphy)
3546 {
3547         struct ieee80211_hw *hw = dev->wl->hw;
3548         struct b43legacy_phy *phy = &dev->phy;
3549
3550         phy->possible_phymodes = 0;
3551         if (have_bphy) {
3552                 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3553                         &b43legacy_band_2GHz_BPHY;
3554                 phy->possible_phymodes |= B43legacy_PHYMODE_B;
3555         }
3556
3557         if (have_gphy) {
3558                 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
3559                         &b43legacy_band_2GHz_GPHY;
3560                 phy->possible_phymodes |= B43legacy_PHYMODE_G;
3561         }
3562
3563         return 0;
3564 }
3565
3566 static void b43legacy_wireless_core_detach(struct b43legacy_wldev *dev)
3567 {
3568         /* We release firmware that late to not be required to re-request
3569          * is all the time when we reinit the core. */
3570         b43legacy_release_firmware(dev);
3571 }
3572
3573 static int b43legacy_wireless_core_attach(struct b43legacy_wldev *dev)
3574 {
3575         struct b43legacy_wl *wl = dev->wl;
3576         struct ssb_bus *bus = dev->dev->bus;
3577         struct pci_dev *pdev = (bus->bustype == SSB_BUSTYPE_PCI) ? bus->host_pci : NULL;
3578         int err;
3579         int have_bphy = 0;
3580         int have_gphy = 0;
3581         u32 tmp;
3582
3583         /* Do NOT do any device initialization here.
3584          * Do it in wireless_core_init() instead.
3585          * This function is for gathering basic information about the HW, only.
3586          * Also some structs may be set up here. But most likely you want to
3587          * have that in core_init(), too.
3588          */
3589
3590         err = ssb_bus_powerup(bus, 0);
3591         if (err) {
3592                 b43legacyerr(wl, "Bus powerup failed\n");
3593                 goto out;
3594         }
3595         /* Get the PHY type. */
3596         if (dev->dev->id.revision >= 5) {
3597                 u32 tmshigh;
3598
3599                 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
3600                 have_gphy = !!(tmshigh & B43legacy_TMSHIGH_GPHY);
3601                 if (!have_gphy)
3602                         have_bphy = 1;
3603         } else if (dev->dev->id.revision == 4)
3604                 have_gphy = 1;
3605         else
3606                 have_bphy = 1;
3607
3608         dev->phy.gmode = (have_gphy || have_bphy);
3609         dev->phy.radio_on = 1;
3610         tmp = dev->phy.gmode ? B43legacy_TMSLOW_GMODE : 0;
3611         b43legacy_wireless_core_reset(dev, tmp);
3612
3613         err = b43legacy_phy_versioning(dev);
3614         if (err)
3615                 goto err_powerdown;
3616         /* Check if this device supports multiband. */
3617         if (!pdev ||
3618             (pdev->device != 0x4312 &&
3619              pdev->device != 0x4319 &&
3620              pdev->device != 0x4324)) {
3621                 /* No multiband support. */
3622                 have_bphy = 0;
3623                 have_gphy = 0;
3624                 switch (dev->phy.type) {
3625                 case B43legacy_PHYTYPE_B:
3626                         have_bphy = 1;
3627                         break;
3628                 case B43legacy_PHYTYPE_G:
3629                         have_gphy = 1;
3630                         break;
3631                 default:
3632                         B43legacy_BUG_ON(1);
3633                 }
3634         }
3635         dev->phy.gmode = (have_gphy || have_bphy);
3636         tmp = dev->phy.gmode ? B43legacy_TMSLOW_GMODE : 0;
3637         b43legacy_wireless_core_reset(dev, tmp);
3638
3639         err = b43legacy_validate_chipaccess(dev);
3640         if (err)
3641                 goto err_powerdown;
3642         err = b43legacy_setup_modes(dev, have_bphy, have_gphy);
3643         if (err)
3644                 goto err_powerdown;
3645
3646         /* Now set some default "current_dev" */
3647         if (!wl->current_dev)
3648                 wl->current_dev = dev;
3649         INIT_WORK(&dev->restart_work, b43legacy_chip_reset);
3650
3651         b43legacy_radio_turn_off(dev, 1);
3652         b43legacy_switch_analog(dev, 0);
3653         ssb_device_disable(dev->dev, 0);
3654         ssb_bus_may_powerdown(bus);
3655
3656 out:
3657         return err;
3658
3659 err_powerdown:
3660         ssb_bus_may_powerdown(bus);
3661         return err;
3662 }
3663
3664 static void b43legacy_one_core_detach(struct ssb_device *dev)
3665 {
3666         struct b43legacy_wldev *wldev;
3667         struct b43legacy_wl *wl;
3668
3669         /* Do not cancel ieee80211-workqueue based work here.
3670          * See comment in b43legacy_remove(). */
3671
3672         wldev = ssb_get_drvdata(dev);
3673         wl = wldev->wl;
3674         b43legacy_debugfs_remove_device(wldev);
3675         b43legacy_wireless_core_detach(wldev);
3676         list_del(&wldev->list);
3677         wl->nr_devs--;
3678         ssb_set_drvdata(dev, NULL);
3679         kfree(wldev);
3680 }
3681
3682 static int b43legacy_one_core_attach(struct ssb_device *dev,
3683                                      struct b43legacy_wl *wl)
3684 {
3685         struct b43legacy_wldev *wldev;
3686         struct pci_dev *pdev;
3687         int err = -ENOMEM;
3688
3689         if (!list_empty(&wl->devlist)) {
3690                 /* We are not the first core on this chip. */
3691                 pdev = (dev->bus->bustype == SSB_BUSTYPE_PCI) ? dev->bus->host_pci : NULL;
3692                 /* Only special chips support more than one wireless
3693                  * core, although some of the other chips have more than
3694                  * one wireless core as well. Check for this and
3695                  * bail out early.
3696                  */
3697                 if (!pdev ||
3698                     ((pdev->device != 0x4321) &&
3699                      (pdev->device != 0x4313) &&
3700                      (pdev->device != 0x431A))) {
3701                         b43legacydbg(wl, "Ignoring unconnected 802.11 core\n");
3702                         return -ENODEV;
3703                 }
3704         }
3705
3706         wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
3707         if (!wldev)
3708                 goto out;
3709
3710         wldev->dev = dev;
3711         wldev->wl = wl;
3712         b43legacy_set_status(wldev, B43legacy_STAT_UNINIT);
3713         wldev->bad_frames_preempt = modparam_bad_frames_preempt;
3714         tasklet_init(&wldev->isr_tasklet,
3715                      (void (*)(unsigned long))b43legacy_interrupt_tasklet,
3716                      (unsigned long)wldev);
3717         if (modparam_pio)
3718                 wldev->__using_pio = 1;
3719         INIT_LIST_HEAD(&wldev->list);
3720
3721         err = b43legacy_wireless_core_attach(wldev);
3722         if (err)
3723                 goto err_kfree_wldev;
3724
3725         list_add(&wldev->list, &wl->devlist);
3726         wl->nr_devs++;
3727         ssb_set_drvdata(dev, wldev);
3728         b43legacy_debugfs_add_device(wldev);
3729 out:
3730         return err;
3731
3732 err_kfree_wldev:
3733         kfree(wldev);
3734         return err;
3735 }
3736
3737 static void b43legacy_sprom_fixup(struct ssb_bus *bus)
3738 {
3739         /* boardflags workarounds */
3740         if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3741             bus->boardinfo.type == 0x4E &&
3742             bus->boardinfo.rev > 0x40)
3743                 bus->sprom.boardflags_lo |= B43legacy_BFL_PACTRL;
3744 }
3745
3746 static void b43legacy_wireless_exit(struct ssb_device *dev,
3747                                   struct b43legacy_wl *wl)
3748 {
3749         struct ieee80211_hw *hw = wl->hw;
3750
3751         ssb_set_devtypedata(dev, NULL);
3752         ieee80211_free_hw(hw);
3753 }
3754
3755 static int b43legacy_wireless_init(struct ssb_device *dev)
3756 {
3757         struct ssb_sprom *sprom = &dev->bus->sprom;
3758         struct ieee80211_hw *hw;
3759         struct b43legacy_wl *wl;
3760         int err = -ENOMEM;
3761
3762         b43legacy_sprom_fixup(dev->bus);
3763
3764         hw = ieee80211_alloc_hw(sizeof(*wl), &b43legacy_hw_ops);
3765         if (!hw) {
3766                 b43legacyerr(NULL, "Could not allocate ieee80211 device\n");
3767                 goto out;
3768         }
3769
3770         /* fill hw info */
3771         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
3772                     IEEE80211_HW_SIGNAL_DBM |
3773                     IEEE80211_HW_NOISE_DBM;
3774         hw->wiphy->interface_modes =
3775                 BIT(NL80211_IFTYPE_AP) |
3776                 BIT(NL80211_IFTYPE_STATION) |
3777                 BIT(NL80211_IFTYPE_WDS) |
3778                 BIT(NL80211_IFTYPE_ADHOC);
3779         hw->queues = 1; /* FIXME: hardware has more queues */
3780         hw->max_rates = 2;
3781         SET_IEEE80211_DEV(hw, dev->dev);
3782         if (is_valid_ether_addr(sprom->et1mac))
3783                 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
3784         else
3785                 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
3786
3787         /* Get and initialize struct b43legacy_wl */
3788         wl = hw_to_b43legacy_wl(hw);
3789         memset(wl, 0, sizeof(*wl));
3790         wl->hw = hw;
3791         spin_lock_init(&wl->irq_lock);
3792         spin_lock_init(&wl->leds_lock);
3793         mutex_init(&wl->mutex);
3794         INIT_LIST_HEAD(&wl->devlist);
3795         INIT_WORK(&wl->beacon_update_trigger, b43legacy_beacon_update_trigger_work);
3796
3797         ssb_set_devtypedata(dev, wl);
3798         b43legacyinfo(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
3799         err = 0;
3800 out:
3801         return err;
3802 }
3803
3804 static int b43legacy_probe(struct ssb_device *dev,
3805                          const struct ssb_device_id *id)
3806 {
3807         struct b43legacy_wl *wl;
3808         int err;
3809         int first = 0;
3810
3811         wl = ssb_get_devtypedata(dev);
3812         if (!wl) {
3813                 /* Probing the first core - setup common struct b43legacy_wl */
3814                 first = 1;
3815                 err = b43legacy_wireless_init(dev);
3816                 if (err)
3817                         goto out;
3818                 wl = ssb_get_devtypedata(dev);
3819                 B43legacy_WARN_ON(!wl);
3820         }
3821         err = b43legacy_one_core_attach(dev, wl);
3822         if (err)
3823                 goto err_wireless_exit;
3824
3825         if (first) {
3826                 err = ieee80211_register_hw(wl->hw);
3827                 if (err)
3828                         goto err_one_core_detach;
3829         }
3830
3831 out:
3832         return err;
3833
3834 err_one_core_detach:
3835         b43legacy_one_core_detach(dev);
3836 err_wireless_exit:
3837         if (first)
3838                 b43legacy_wireless_exit(dev, wl);
3839         return err;
3840 }
3841
3842 static void b43legacy_remove(struct ssb_device *dev)
3843 {
3844         struct b43legacy_wl *wl = ssb_get_devtypedata(dev);
3845         struct b43legacy_wldev *wldev = ssb_get_drvdata(dev);
3846
3847         /* We must cancel any work here before unregistering from ieee80211,
3848          * as the ieee80211 unreg will destroy the workqueue. */
3849         cancel_work_sync(&wldev->restart_work);
3850
3851         B43legacy_WARN_ON(!wl);
3852         if (wl->current_dev == wldev)
3853                 ieee80211_unregister_hw(wl->hw);
3854
3855         b43legacy_one_core_detach(dev);
3856
3857         if (list_empty(&wl->devlist))
3858                 /* Last core on the chip unregistered.
3859                  * We can destroy common struct b43legacy_wl.
3860                  */
3861                 b43legacy_wireless_exit(dev, wl);
3862 }
3863
3864 /* Perform a hardware reset. This can be called from any context. */
3865 void b43legacy_controller_restart(struct b43legacy_wldev *dev,
3866                                   const char *reason)
3867 {
3868         /* Must avoid requeueing, if we are in shutdown. */
3869         if (b43legacy_status(dev) < B43legacy_STAT_INITIALIZED)
3870                 return;
3871         b43legacyinfo(dev->wl, "Controller RESET (%s) ...\n", reason);
3872         ieee80211_queue_work(dev->wl->hw, &dev->restart_work);
3873 }
3874
3875 #ifdef CONFIG_PM
3876
3877 static int b43legacy_suspend(struct ssb_device *dev, pm_message_t state)
3878 {
3879         struct b43legacy_wldev *wldev = ssb_get_drvdata(dev);
3880         struct b43legacy_wl *wl = wldev->wl;
3881
3882         b43legacydbg(wl, "Suspending...\n");
3883
3884         mutex_lock(&wl->mutex);
3885         wldev->suspend_init_status = b43legacy_status(wldev);
3886         if (wldev->suspend_init_status >= B43legacy_STAT_STARTED)
3887                 b43legacy_wireless_core_stop(wldev);
3888         if (wldev->suspend_init_status >= B43legacy_STAT_INITIALIZED)
3889                 b43legacy_wireless_core_exit(wldev);
3890         mutex_unlock(&wl->mutex);
3891
3892         b43legacydbg(wl, "Device suspended.\n");
3893
3894         return 0;
3895 }
3896
3897 static int b43legacy_resume(struct ssb_device *dev)
3898 {
3899         struct b43legacy_wldev *wldev = ssb_get_drvdata(dev);
3900         struct b43legacy_wl *wl = wldev->wl;
3901         int err = 0;
3902
3903         b43legacydbg(wl, "Resuming...\n");
3904
3905         mutex_lock(&wl->mutex);
3906         if (wldev->suspend_init_status >= B43legacy_STAT_INITIALIZED) {
3907                 err = b43legacy_wireless_core_init(wldev);
3908                 if (err) {
3909                         b43legacyerr(wl, "Resume failed at core init\n");
3910                         goto out;
3911                 }
3912         }
3913         if (wldev->suspend_init_status >= B43legacy_STAT_STARTED) {
3914                 err = b43legacy_wireless_core_start(wldev);
3915                 if (err) {
3916                         b43legacy_wireless_core_exit(wldev);
3917                         b43legacyerr(wl, "Resume failed at core start\n");
3918                         goto out;
3919                 }
3920         }
3921
3922         b43legacydbg(wl, "Device resumed.\n");
3923 out:
3924         mutex_unlock(&wl->mutex);
3925         return err;
3926 }
3927
3928 #else   /* CONFIG_PM */
3929 # define b43legacy_suspend      NULL
3930 # define b43legacy_resume               NULL
3931 #endif  /* CONFIG_PM */
3932
3933 static struct ssb_driver b43legacy_ssb_driver = {
3934         .name           = KBUILD_MODNAME,
3935         .id_table       = b43legacy_ssb_tbl,
3936         .probe          = b43legacy_probe,
3937         .remove         = b43legacy_remove,
3938         .suspend        = b43legacy_suspend,
3939         .resume         = b43legacy_resume,
3940 };
3941
3942 static void b43legacy_print_driverinfo(void)
3943 {
3944         const char *feat_pci = "", *feat_leds = "",
3945                    *feat_pio = "", *feat_dma = "";
3946
3947 #ifdef CONFIG_B43LEGACY_PCI_AUTOSELECT
3948         feat_pci = "P";
3949 #endif
3950 #ifdef CONFIG_B43LEGACY_LEDS
3951         feat_leds = "L";
3952 #endif
3953 #ifdef CONFIG_B43LEGACY_PIO
3954         feat_pio = "I";
3955 #endif
3956 #ifdef CONFIG_B43LEGACY_DMA
3957         feat_dma = "D";
3958 #endif
3959         printk(KERN_INFO "Broadcom 43xx-legacy driver loaded "
3960                "[ Features: %s%s%s%s, Firmware-ID: "
3961                B43legacy_SUPPORTED_FIRMWARE_ID " ]\n",
3962                feat_pci, feat_leds, feat_pio, feat_dma);
3963 }
3964
3965 static int __init b43legacy_init(void)
3966 {
3967         int err;
3968
3969         b43legacy_debugfs_init();
3970
3971         err = ssb_driver_register(&b43legacy_ssb_driver);
3972         if (err)
3973                 goto err_dfs_exit;
3974
3975         b43legacy_print_driverinfo();
3976
3977         return err;
3978
3979 err_dfs_exit:
3980         b43legacy_debugfs_exit();
3981         return err;
3982 }
3983
3984 static void __exit b43legacy_exit(void)
3985 {
3986         ssb_driver_unregister(&b43legacy_ssb_driver);
3987         b43legacy_debugfs_exit();
3988 }
3989
3990 module_init(b43legacy_init)
3991 module_exit(b43legacy_exit)