4 #include <linux/hw_random.h>
5 #include <linux/kernel.h>
6 #include <linux/spinlock.h>
7 #include <linux/interrupt.h>
8 #include <linux/stringify.h>
9 #include <linux/netdevice.h>
10 #include <linux/pci.h>
11 #include <asm/atomic.h>
14 #include <linux/ssb/ssb.h>
15 #include <linux/ssb/ssb_driver_chipcommon.h>
17 #include <linux/wireless.h>
18 #include <net/mac80211.h>
26 /* The unique identifier of the firmware that's officially supported by this
28 #define B43legacy_SUPPORTED_FIRMWARE_ID "FW10"
30 #define B43legacy_IRQWAIT_MAX_RETRIES 20
32 #define B43legacy_RX_MAX_SSI 60 /* best guess at max ssi */
35 #define B43legacy_MMIO_DMA0_REASON 0x20
36 #define B43legacy_MMIO_DMA0_IRQ_MASK 0x24
37 #define B43legacy_MMIO_DMA1_REASON 0x28
38 #define B43legacy_MMIO_DMA1_IRQ_MASK 0x2C
39 #define B43legacy_MMIO_DMA2_REASON 0x30
40 #define B43legacy_MMIO_DMA2_IRQ_MASK 0x34
41 #define B43legacy_MMIO_DMA3_REASON 0x38
42 #define B43legacy_MMIO_DMA3_IRQ_MASK 0x3C
43 #define B43legacy_MMIO_DMA4_REASON 0x40
44 #define B43legacy_MMIO_DMA4_IRQ_MASK 0x44
45 #define B43legacy_MMIO_DMA5_REASON 0x48
46 #define B43legacy_MMIO_DMA5_IRQ_MASK 0x4C
47 #define B43legacy_MMIO_MACCTL 0x120 /* MAC control */
48 #define B43legacy_MMIO_MACCMD 0x124 /* MAC command */
49 #define B43legacy_MMIO_GEN_IRQ_REASON 0x128
50 #define B43legacy_MMIO_GEN_IRQ_MASK 0x12C
51 #define B43legacy_MMIO_RAM_CONTROL 0x130
52 #define B43legacy_MMIO_RAM_DATA 0x134
53 #define B43legacy_MMIO_PS_STATUS 0x140
54 #define B43legacy_MMIO_RADIO_HWENABLED_HI 0x158
55 #define B43legacy_MMIO_SHM_CONTROL 0x160
56 #define B43legacy_MMIO_SHM_DATA 0x164
57 #define B43legacy_MMIO_SHM_DATA_UNALIGNED 0x166
58 #define B43legacy_MMIO_XMITSTAT_0 0x170
59 #define B43legacy_MMIO_XMITSTAT_1 0x174
60 #define B43legacy_MMIO_REV3PLUS_TSF_LOW 0x180 /* core rev >= 3 only */
61 #define B43legacy_MMIO_REV3PLUS_TSF_HIGH 0x184 /* core rev >= 3 only */
64 #define B43legacy_MMIO_DMA32_BASE0 0x200
65 #define B43legacy_MMIO_DMA32_BASE1 0x220
66 #define B43legacy_MMIO_DMA32_BASE2 0x240
67 #define B43legacy_MMIO_DMA32_BASE3 0x260
68 #define B43legacy_MMIO_DMA32_BASE4 0x280
69 #define B43legacy_MMIO_DMA32_BASE5 0x2A0
71 #define B43legacy_MMIO_DMA64_BASE0 0x200
72 #define B43legacy_MMIO_DMA64_BASE1 0x240
73 #define B43legacy_MMIO_DMA64_BASE2 0x280
74 #define B43legacy_MMIO_DMA64_BASE3 0x2C0
75 #define B43legacy_MMIO_DMA64_BASE4 0x300
76 #define B43legacy_MMIO_DMA64_BASE5 0x340
78 #define B43legacy_MMIO_PIO1_BASE 0x300
79 #define B43legacy_MMIO_PIO2_BASE 0x310
80 #define B43legacy_MMIO_PIO3_BASE 0x320
81 #define B43legacy_MMIO_PIO4_BASE 0x330
83 #define B43legacy_MMIO_PHY_VER 0x3E0
84 #define B43legacy_MMIO_PHY_RADIO 0x3E2
85 #define B43legacy_MMIO_PHY0 0x3E6
86 #define B43legacy_MMIO_ANTENNA 0x3E8
87 #define B43legacy_MMIO_CHANNEL 0x3F0
88 #define B43legacy_MMIO_CHANNEL_EXT 0x3F4
89 #define B43legacy_MMIO_RADIO_CONTROL 0x3F6
90 #define B43legacy_MMIO_RADIO_DATA_HIGH 0x3F8
91 #define B43legacy_MMIO_RADIO_DATA_LOW 0x3FA
92 #define B43legacy_MMIO_PHY_CONTROL 0x3FC
93 #define B43legacy_MMIO_PHY_DATA 0x3FE
94 #define B43legacy_MMIO_MACFILTER_CONTROL 0x420
95 #define B43legacy_MMIO_MACFILTER_DATA 0x422
96 #define B43legacy_MMIO_RCMTA_COUNT 0x43C /* Receive Match Transmitter Addr */
97 #define B43legacy_MMIO_RADIO_HWENABLED_LO 0x49A
98 #define B43legacy_MMIO_GPIO_CONTROL 0x49C
99 #define B43legacy_MMIO_GPIO_MASK 0x49E
100 #define B43legacy_MMIO_TSF_0 0x632 /* core rev < 3 only */
101 #define B43legacy_MMIO_TSF_1 0x634 /* core rev < 3 only */
102 #define B43legacy_MMIO_TSF_2 0x636 /* core rev < 3 only */
103 #define B43legacy_MMIO_TSF_3 0x638 /* core rev < 3 only */
104 #define B43legacy_MMIO_RNG 0x65A
105 #define B43legacy_MMIO_POWERUP_DELAY 0x6A8
107 /* SPROM boardflags_lo values */
108 #define B43legacy_BFL_PACTRL 0x0002
109 #define B43legacy_BFL_RSSI 0x0008
110 #define B43legacy_BFL_EXTLNA 0x1000
112 /* GPIO register offset, in both ChipCommon and PCI core. */
113 #define B43legacy_GPIO_CONTROL 0x6c
116 #define B43legacy_SHM_SHARED 0x0001
117 #define B43legacy_SHM_WIRELESS 0x0002
118 #define B43legacy_SHM_HW 0x0004
119 #define B43legacy_SHM_UCODE 0x0300
121 /* SHM Routing modifiers */
122 #define B43legacy_SHM_AUTOINC_R 0x0200 /* Read Auto-increment */
123 #define B43legacy_SHM_AUTOINC_W 0x0100 /* Write Auto-increment */
124 #define B43legacy_SHM_AUTOINC_RW (B43legacy_SHM_AUTOINC_R | \
125 B43legacy_SHM_AUTOINC_W)
127 /* Misc SHM_SHARED offsets */
128 #define B43legacy_SHM_SH_WLCOREREV 0x0016 /* 802.11 core revision */
129 #define B43legacy_SHM_SH_HOSTFLO 0x005E /* Hostflags ucode opts (low) */
130 #define B43legacy_SHM_SH_HOSTFHI 0x0060 /* Hostflags ucode opts (high) */
131 /* SHM_SHARED crypto engine */
132 #define B43legacy_SHM_SH_KEYIDXBLOCK 0x05D4 /* Key index/algorithm block */
133 /* SHM_SHARED beacon/AP variables */
134 #define B43legacy_SHM_SH_DTIMP 0x0012 /* DTIM period */
135 #define B43legacy_SHM_SH_BTL0 0x0018 /* Beacon template length 0 */
136 #define B43legacy_SHM_SH_BTL1 0x001A /* Beacon template length 1 */
137 #define B43legacy_SHM_SH_BTSFOFF 0x001C /* Beacon TSF offset */
138 #define B43legacy_SHM_SH_TIMPOS 0x001E /* TIM position in beacon */
139 #define B43legacy_SHM_SH_BEACPHYCTL 0x0054 /* Beacon PHY TX control word */
140 /* SHM_SHARED ACK/CTS control */
141 #define B43legacy_SHM_SH_ACKCTSPHYCTL 0x0022 /* ACK/CTS PHY control word */
142 /* SHM_SHARED probe response variables */
143 #define B43legacy_SHM_SH_PRTLEN 0x004A /* Probe Response template length */
144 #define B43legacy_SHM_SH_PRMAXTIME 0x0074 /* Probe Response max time */
145 #define B43legacy_SHM_SH_PRPHYCTL 0x0188 /* Probe Resp PHY TX control */
146 /* SHM_SHARED rate tables */
147 /* SHM_SHARED microcode soft registers */
148 #define B43legacy_SHM_SH_UCODEREV 0x0000 /* Microcode revision */
149 #define B43legacy_SHM_SH_UCODEPATCH 0x0002 /* Microcode patchlevel */
150 #define B43legacy_SHM_SH_UCODEDATE 0x0004 /* Microcode date */
151 #define B43legacy_SHM_SH_UCODETIME 0x0006 /* Microcode time */
153 #define B43legacy_UCODEFLAGS_OFFSET 0x005E
155 /* Hardware Radio Enable masks */
156 #define B43legacy_MMIO_RADIO_HWENABLED_HI_MASK (1 << 16)
157 #define B43legacy_MMIO_RADIO_HWENABLED_LO_MASK (1 << 4)
159 /* HostFlags. See b43legacy_hf_read/write() */
160 #define B43legacy_HF_SYMW 0x00000002 /* G-PHY SYM workaround */
161 #define B43legacy_HF_GDCW 0x00000020 /* G-PHY DV cancel filter */
162 #define B43legacy_HF_OFDMPABOOST 0x00000040 /* Enable PA boost OFDM */
163 #define B43legacy_HF_EDCF 0x00000100 /* on if WME/MAC suspended */
165 /* MacFilter offsets. */
166 #define B43legacy_MACFILTER_SELF 0x0000
167 #define B43legacy_MACFILTER_BSSID 0x0003
168 #define B43legacy_MACFILTER_MAC 0x0010
171 #define B43legacy_PHYTYPE_B 0x01
172 #define B43legacy_PHYTYPE_G 0x02
175 #define B43legacy_PHY_G_LO_CONTROL 0x0810
176 #define B43legacy_PHY_ILT_G_CTRL 0x0472
177 #define B43legacy_PHY_ILT_G_DATA1 0x0473
178 #define B43legacy_PHY_ILT_G_DATA2 0x0474
179 #define B43legacy_PHY_G_PCTL 0x0029
180 #define B43legacy_PHY_RADIO_BITFIELD 0x0401
181 #define B43legacy_PHY_G_CRS 0x0429
182 #define B43legacy_PHY_NRSSILT_CTRL 0x0803
183 #define B43legacy_PHY_NRSSILT_DATA 0x0804
186 #define B43legacy_RADIOCTL_ID 0x01
188 /* MAC Control bitfield */
189 #define B43legacy_MACCTL_ENABLED 0x00000001 /* MAC Enabled */
190 #define B43legacy_MACCTL_PSM_RUN 0x00000002 /* Run Microcode */
191 #define B43legacy_MACCTL_PSM_JMP0 0x00000004 /* Microcode jump to 0 */
192 #define B43legacy_MACCTL_SHM_ENABLED 0x00000100 /* SHM Enabled */
193 #define B43legacy_MACCTL_IHR_ENABLED 0x00000400 /* IHR Region Enabled */
194 #define B43legacy_MACCTL_BE 0x00010000 /* Big Endian mode */
195 #define B43legacy_MACCTL_INFRA 0x00020000 /* Infrastructure mode */
196 #define B43legacy_MACCTL_AP 0x00040000 /* AccessPoint mode */
197 #define B43legacy_MACCTL_RADIOLOCK 0x00080000 /* Radio lock */
198 #define B43legacy_MACCTL_BEACPROMISC 0x00100000 /* Beacon Promiscuous */
199 #define B43legacy_MACCTL_KEEP_BADPLCP 0x00200000 /* Keep bad PLCP frames */
200 #define B43legacy_MACCTL_KEEP_CTL 0x00400000 /* Keep control frames */
201 #define B43legacy_MACCTL_KEEP_BAD 0x00800000 /* Keep bad frames (FCS) */
202 #define B43legacy_MACCTL_PROMISC 0x01000000 /* Promiscuous mode */
203 #define B43legacy_MACCTL_HWPS 0x02000000 /* Hardware Power Saving */
204 #define B43legacy_MACCTL_AWAKE 0x04000000 /* Device is awake */
205 #define B43legacy_MACCTL_TBTTHOLD 0x10000000 /* TBTT Hold */
206 #define B43legacy_MACCTL_GMODE 0x80000000 /* G Mode */
208 /* MAC Command bitfield */
209 #define B43legacy_MACCMD_BEACON0_VALID 0x00000001 /* Beacon 0 in template RAM is busy/valid */
210 #define B43legacy_MACCMD_BEACON1_VALID 0x00000002 /* Beacon 1 in template RAM is busy/valid */
211 #define B43legacy_MACCMD_DFQ_VALID 0x00000004 /* Directed frame queue valid (IBSS PS mode, ATIM) */
212 #define B43legacy_MACCMD_CCA 0x00000008 /* Clear channel assessment */
213 #define B43legacy_MACCMD_BGNOISE 0x00000010 /* Background noise */
215 /* 802.11 core specific TM State Low flags */
216 #define B43legacy_TMSLOW_GMODE 0x20000000 /* G Mode Enable */
217 #define B43legacy_TMSLOW_PLLREFSEL 0x00200000 /* PLL Freq Ref Select */
218 #define B43legacy_TMSLOW_MACPHYCLKEN 0x00100000 /* MAC PHY Clock Ctrl Enbl */
219 #define B43legacy_TMSLOW_PHYRESET 0x00080000 /* PHY Reset */
220 #define B43legacy_TMSLOW_PHYCLKEN 0x00040000 /* PHY Clock Enable */
222 /* 802.11 core specific TM State High flags */
223 #define B43legacy_TMSHIGH_FCLOCK 0x00040000 /* Fast Clock Available */
224 #define B43legacy_TMSHIGH_GPHY 0x00010000 /* G-PHY avail (rev >= 5) */
226 #define B43legacy_UCODEFLAG_AUTODIV 0x0001
228 /* Generic-Interrupt reasons. */
229 #define B43legacy_IRQ_MAC_SUSPENDED 0x00000001
230 #define B43legacy_IRQ_BEACON 0x00000002
231 #define B43legacy_IRQ_TBTT_INDI 0x00000004 /* Target Beacon Transmit Time */
232 #define B43legacy_IRQ_BEACON_TX_OK 0x00000008
233 #define B43legacy_IRQ_BEACON_CANCEL 0x00000010
234 #define B43legacy_IRQ_ATIM_END 0x00000020
235 #define B43legacy_IRQ_PMQ 0x00000040
236 #define B43legacy_IRQ_PIO_WORKAROUND 0x00000100
237 #define B43legacy_IRQ_MAC_TXERR 0x00000200
238 #define B43legacy_IRQ_PHY_TXERR 0x00000800
239 #define B43legacy_IRQ_PMEVENT 0x00001000
240 #define B43legacy_IRQ_TIMER0 0x00002000
241 #define B43legacy_IRQ_TIMER1 0x00004000
242 #define B43legacy_IRQ_DMA 0x00008000
243 #define B43legacy_IRQ_TXFIFO_FLUSH_OK 0x00010000
244 #define B43legacy_IRQ_CCA_MEASURE_OK 0x00020000
245 #define B43legacy_IRQ_NOISESAMPLE_OK 0x00040000
246 #define B43legacy_IRQ_UCODE_DEBUG 0x08000000
247 #define B43legacy_IRQ_RFKILL 0x10000000
248 #define B43legacy_IRQ_TX_OK 0x20000000
249 #define B43legacy_IRQ_PHY_G_CHANGED 0x40000000
250 #define B43legacy_IRQ_TIMEOUT 0x80000000
252 #define B43legacy_IRQ_ALL 0xFFFFFFFF
253 #define B43legacy_IRQ_MASKTEMPLATE (B43legacy_IRQ_MAC_SUSPENDED | \
254 B43legacy_IRQ_BEACON | \
255 B43legacy_IRQ_TBTT_INDI | \
256 B43legacy_IRQ_ATIM_END | \
257 B43legacy_IRQ_PMQ | \
258 B43legacy_IRQ_MAC_TXERR | \
259 B43legacy_IRQ_PHY_TXERR | \
260 B43legacy_IRQ_DMA | \
261 B43legacy_IRQ_TXFIFO_FLUSH_OK | \
262 B43legacy_IRQ_NOISESAMPLE_OK | \
263 B43legacy_IRQ_UCODE_DEBUG | \
264 B43legacy_IRQ_RFKILL | \
267 /* Device specific rate values.
268 * The actual values defined here are (rate_in_mbps * 2).
269 * Some code depends on this. Don't change it. */
270 #define B43legacy_CCK_RATE_1MB 2
271 #define B43legacy_CCK_RATE_2MB 4
272 #define B43legacy_CCK_RATE_5MB 11
273 #define B43legacy_CCK_RATE_11MB 22
274 #define B43legacy_OFDM_RATE_6MB 12
275 #define B43legacy_OFDM_RATE_9MB 18
276 #define B43legacy_OFDM_RATE_12MB 24
277 #define B43legacy_OFDM_RATE_18MB 36
278 #define B43legacy_OFDM_RATE_24MB 48
279 #define B43legacy_OFDM_RATE_36MB 72
280 #define B43legacy_OFDM_RATE_48MB 96
281 #define B43legacy_OFDM_RATE_54MB 108
282 /* Convert a b43legacy rate value to a rate in 100kbps */
283 #define B43legacy_RATE_TO_100KBPS(rate) (((rate) * 10) / 2)
286 #define B43legacy_DEFAULT_SHORT_RETRY_LIMIT 7
287 #define B43legacy_DEFAULT_LONG_RETRY_LIMIT 4
289 #define B43legacy_PHY_TX_BADNESS_LIMIT 1000
291 /* Max size of a security key */
292 #define B43legacy_SEC_KEYSIZE 16
293 /* Security algorithms. */
295 B43legacy_SEC_ALGO_NONE = 0, /* unencrypted, as of TX header. */
296 B43legacy_SEC_ALGO_WEP40,
297 B43legacy_SEC_ALGO_TKIP,
298 B43legacy_SEC_ALGO_AES,
299 B43legacy_SEC_ALGO_WEP104,
300 B43legacy_SEC_ALGO_AES_LEGACY,
303 /* Core Information Registers */
304 #define B43legacy_CIR_BASE 0xf00
305 #define B43legacy_CIR_SBTPSFLAG (B43legacy_CIR_BASE + 0x18)
306 #define B43legacy_CIR_SBIMSTATE (B43legacy_CIR_BASE + 0x90)
307 #define B43legacy_CIR_SBINTVEC (B43legacy_CIR_BASE + 0x94)
308 #define B43legacy_CIR_SBTMSTATELOW (B43legacy_CIR_BASE + 0x98)
309 #define B43legacy_CIR_SBTMSTATEHIGH (B43legacy_CIR_BASE + 0x9c)
310 #define B43legacy_CIR_SBIMCONFIGLOW (B43legacy_CIR_BASE + 0xa8)
311 #define B43legacy_CIR_SB_ID_HI (B43legacy_CIR_BASE + 0xfc)
313 /* sbtmstatehigh state flags */
314 #define B43legacy_SBTMSTATEHIGH_SERROR 0x00000001
315 #define B43legacy_SBTMSTATEHIGH_BUSY 0x00000004
316 #define B43legacy_SBTMSTATEHIGH_TIMEOUT 0x00000020
317 #define B43legacy_SBTMSTATEHIGH_G_PHY_AVAIL 0x00010000
318 #define B43legacy_SBTMSTATEHIGH_COREFLAGS 0x1FFF0000
319 #define B43legacy_SBTMSTATEHIGH_DMA64BIT 0x10000000
320 #define B43legacy_SBTMSTATEHIGH_GATEDCLK 0x20000000
321 #define B43legacy_SBTMSTATEHIGH_BISTFAILED 0x40000000
322 #define B43legacy_SBTMSTATEHIGH_BISTCOMPLETE 0x80000000
324 /* sbimstate flags */
325 #define B43legacy_SBIMSTATE_IB_ERROR 0x20000
326 #define B43legacy_SBIMSTATE_TIMEOUT 0x40000
328 #define PFX KBUILD_MODNAME ": "
332 #ifdef CONFIG_B43LEGACY_DEBUG
333 # define B43legacy_WARN_ON(expr) \
335 if (unlikely((expr))) { \
336 printk(KERN_INFO PFX "Test (%s) failed at:" \
339 __LINE__, __FUNCTION__); \
342 # define B43legacy_BUG_ON(expr) \
344 if (unlikely((expr))) { \
345 printk(KERN_INFO PFX "Test (%s) failed\n", \
350 # define B43legacy_DEBUG 1
352 # define B43legacy_WARN_ON(x) do { /* nothing */ } while (0)
353 # define B43legacy_BUG_ON(x) do { /* nothing */ } while (0)
354 # define B43legacy_DEBUG 0
360 struct b43legacy_dmaring;
361 struct b43legacy_pioqueue;
363 /* The firmware file header */
364 #define B43legacy_FW_TYPE_UCODE 'u'
365 #define B43legacy_FW_TYPE_PCM 'p'
366 #define B43legacy_FW_TYPE_IV 'i'
367 struct b43legacy_fw_header {
370 /* File format version */
373 /* Size of the data. For ucode and PCM this is in bytes.
374 * For IV this is number-of-ivs. */
376 } __attribute__((__packed__));
378 /* Initial Value file format */
379 #define B43legacy_IV_OFFSET_MASK 0x7FFF
380 #define B43legacy_IV_32BIT 0x8000
381 struct b43legacy_iv {
386 } data __attribute__((__packed__));
387 } __attribute__((__packed__));
389 #define B43legacy_PHYMODE(phytype) (1 << (phytype))
390 #define B43legacy_PHYMODE_B B43legacy_PHYMODE \
391 ((B43legacy_PHYTYPE_B))
392 #define B43legacy_PHYMODE_G B43legacy_PHYMODE \
393 ((B43legacy_PHYTYPE_G))
395 /* Value pair to measure the LocalOscillator. */
396 struct b43legacy_lopair {
401 #define B43legacy_LO_COUNT (14*4)
403 struct b43legacy_phy {
404 /* Possible PHYMODEs on this PHY */
405 u8 possible_phymodes;
406 /* GMODE bit enabled in MACCTL? */
411 /* B43legacy_PHYTYPE_ */
413 /* PHY revision number. */
416 u16 antenna_diversity;
418 /* Radio versioning */
419 u16 radio_manuf; /* Radio manufacturer */
420 u16 radio_ver; /* Radio version */
422 u8 radio_rev; /* Radio revision */
424 bool dyn_tssi_tbl; /* tssi2dbm is kmalloc()ed. */
426 /* ACI (adjacent channel interference) flags. */
428 bool aci_wlan_automatic;
431 /* Radio switched on/off */
434 /* Values saved when turning the radio off.
435 * They are needed when turning it on again. */
444 /* LO Measurement Data.
445 * Use b43legacy_get_lopair() to get a value.
447 struct b43legacy_lopair *_lo_pairs;
448 /* TSSI to dBm table in use */
450 /* idle TSSI value */
452 /* Target idle TSSI */
454 /* Current idle TSSI */
457 /* LocalOscillator control values. */
458 struct b43legacy_txpower_lo_control *lo_control;
459 /* Values from b43legacy_calc_loopback_gain() */
460 s16 max_lb_gain; /* Maximum Loopback gain in hdB */
461 s16 trsw_rx_gain; /* TRSW RX gain in hdB */
462 s16 lna_lod_gain; /* LNA lod */
463 s16 lna_gain; /* LNA */
464 s16 pga_gain; /* PGA */
466 /* Desired TX power level (in dBm). This is set by the user and
467 * adjusted in b43legacy_phy_xmitpower(). */
470 /* Values from b43legacy_calc_loopback_gain() */
471 u16 loopback_gain[2];
473 /* TX Power control values. */
476 /* Current Radio Attenuation for TXpower recalculation. */
478 /* Current Baseband Attenuation for TXpower recalculation. */
480 /* Current TXpower control value for TXpower recalculation. */
489 /* Current Interference Mitigation mode */
491 /* Stack of saved values from the Interference Mitigation code.
492 * Each value in the stack is layed out as follows:
494 * bit 12-15: register ID
496 * register ID is: 0x1 PHY, 0x2 Radio, 0x3 ILT
498 #define B43legacy_INTERFSTACK_SIZE 26
499 u32 interfstack[B43legacy_INTERFSTACK_SIZE];
501 /* Saved values from the NRSSI Slope calculation */
504 /* In memory nrssi lookup table. */
507 /* current channel */
514 /* PHY TX errors counter. */
518 /* Manual TX-power control enabled? */
519 bool manual_txpower_control;
520 /* PHY registers locked by b43legacy_phy_lock()? */
522 #endif /* B43legacy_DEBUG */
525 /* Data structures for DMA transmission, per 80211 core. */
526 struct b43legacy_dma {
527 struct b43legacy_dmaring *tx_ring0;
528 struct b43legacy_dmaring *tx_ring1;
529 struct b43legacy_dmaring *tx_ring2;
530 struct b43legacy_dmaring *tx_ring3;
531 struct b43legacy_dmaring *tx_ring4;
532 struct b43legacy_dmaring *tx_ring5;
534 struct b43legacy_dmaring *rx_ring0;
535 struct b43legacy_dmaring *rx_ring3; /* only on core.rev < 5 */
538 /* Data structures for PIO transmission, per 80211 core. */
539 struct b43legacy_pio {
540 struct b43legacy_pioqueue *queue0;
541 struct b43legacy_pioqueue *queue1;
542 struct b43legacy_pioqueue *queue2;
543 struct b43legacy_pioqueue *queue3;
546 /* Context information for a noise calculation (Link Quality). */
547 struct b43legacy_noise_calculation {
549 bool calculation_running;
554 struct b43legacy_stats {
556 /* Store the last TX/RX times here for updating the leds. */
557 unsigned long last_tx;
558 unsigned long last_rx;
561 struct b43legacy_key {
567 struct b43legacy_wldev;
569 /* Data structure for the WLAN parts (802.11 cores) of the b43legacy chip. */
570 struct b43legacy_wl {
571 /* Pointer to the active wireless device on this chip */
572 struct b43legacy_wldev *current_dev;
573 /* Pointer to the ieee80211 hardware data structure */
574 struct ieee80211_hw *hw;
576 spinlock_t irq_lock; /* locks IRQ */
577 struct mutex mutex; /* locks wireless core state */
578 spinlock_t leds_lock; /* lock for leds */
580 /* We can only have one operating interface (802.11 core)
581 * at a time. General information about this interface follows.
584 struct ieee80211_vif *vif;
585 /* MAC address (can be NULL). */
586 u8 mac_addr[ETH_ALEN];
587 /* Current BSSID (can be NULL). */
589 /* Interface type. (IEEE80211_IF_TYPE_XXX) */
591 /* Is the card operating in AP, STA or IBSS mode? */
594 unsigned int filter_flags;
595 /* Stats about the wireless interface */
596 struct ieee80211_low_level_stats ieee_stats;
600 char rng_name[30 + 1];
602 /* The RF-kill button */
603 struct b43legacy_rfkill rfkill;
605 /* List of all wireless devices on this chip */
606 struct list_head devlist;
609 bool radiotap_enabled;
611 /* The beacon we are currently using (AP or IBSS mode).
612 * This beacon stuff is protected by the irq_lock. */
613 struct sk_buff *current_beacon;
614 bool beacon0_uploaded;
615 bool beacon1_uploaded;
618 /* Pointers to the firmware data and meta information about it. */
619 struct b43legacy_firmware {
621 const struct firmware *ucode;
623 const struct firmware *pcm;
624 /* Initial MMIO values for the firmware */
625 const struct firmware *initvals;
626 /* Initial MMIO values for the firmware, band-specific */
627 const struct firmware *initvals_band;
628 /* Firmware revision */
630 /* Firmware patchlevel */
634 /* Device (802.11 core) initialization status. */
636 B43legacy_STAT_UNINIT = 0, /* Uninitialized. */
637 B43legacy_STAT_INITIALIZED = 1, /* Initialized, not yet started. */
638 B43legacy_STAT_STARTED = 2, /* Up and running. */
640 #define b43legacy_status(wldev) atomic_read(&(wldev)->__init_status)
641 #define b43legacy_set_status(wldev, stat) do { \
642 atomic_set(&(wldev)->__init_status, (stat)); \
646 /* *** --- HOW LOCKING WORKS IN B43legacy --- ***
648 * You should always acquire both, wl->mutex and wl->irq_lock unless:
649 * - You don't need to acquire wl->irq_lock, if the interface is stopped.
650 * - You don't need to acquire wl->mutex in the IRQ handler, IRQ tasklet
651 * and packet TX path (and _ONLY_ there.)
654 /* Data structure for one wireless device (802.11 core) */
655 struct b43legacy_wldev {
656 struct ssb_device *dev;
657 struct b43legacy_wl *wl;
659 /* The device initialization status.
660 * Use b43legacy_status() to query. */
661 atomic_t __init_status;
662 /* Saved init status for handling suspend. */
663 int suspend_init_status;
665 bool __using_pio; /* Using pio rather than dma. */
666 bool bad_frames_preempt;/* Use "Bad Frames Preemption". */
667 bool dfq_valid; /* Directed frame queue valid (IBSS PS mode, ATIM). */
668 bool short_preamble; /* TRUE if using short preamble. */
669 bool short_slot; /* TRUE if using short slot timing. */
670 bool radio_hw_enable; /* State of radio hardware enable bit. */
672 /* PHY/Radio device. */
673 struct b43legacy_phy phy;
676 struct b43legacy_dma dma;
678 struct b43legacy_pio pio;
681 /* Various statistics about the physical device. */
682 struct b43legacy_stats stats;
684 /* The device LEDs. */
685 struct b43legacy_led led_tx;
686 struct b43legacy_led led_rx;
687 struct b43legacy_led led_assoc;
688 struct b43legacy_led led_radio;
690 /* Reason code of the last interrupt. */
693 /* saved irq enable/disable state bitfield. */
695 /* Link Quality calculation context. */
696 struct b43legacy_noise_calculation noisecalc;
697 /* if > 0 MAC is suspended. if == 0 MAC is enabled. */
700 /* Interrupt Service Routine tasklet (bottom-half) */
701 struct tasklet_struct isr_tasklet;
704 struct delayed_work periodic_work;
705 unsigned int periodic_state;
707 struct work_struct restart_work;
709 /* encryption/decryption */
710 u16 ktp; /* Key table pointer */
712 struct b43legacy_key key[58];
715 struct b43legacy_firmware fw;
717 /* Devicelist in struct b43legacy_wl (all 802.11 cores) */
718 struct list_head list;
720 /* Debugging stuff follows. */
721 #ifdef CONFIG_B43LEGACY_DEBUG
722 struct b43legacy_dfsentry *dfsentry;
728 struct b43legacy_wl *hw_to_b43legacy_wl(struct ieee80211_hw *hw)
733 /* Helper function, which returns a boolean.
734 * TRUE, if PIO is used; FALSE, if DMA is used.
736 #if defined(CONFIG_B43LEGACY_DMA) && defined(CONFIG_B43LEGACY_PIO)
738 int b43legacy_using_pio(struct b43legacy_wldev *dev)
740 return dev->__using_pio;
742 #elif defined(CONFIG_B43LEGACY_DMA)
744 int b43legacy_using_pio(struct b43legacy_wldev *dev)
748 #elif defined(CONFIG_B43LEGACY_PIO)
750 int b43legacy_using_pio(struct b43legacy_wldev *dev)
755 # error "Using neither DMA nor PIO? Confused..."
760 struct b43legacy_wldev *dev_to_b43legacy_wldev(struct device *dev)
762 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
763 return ssb_get_drvdata(ssb_dev);
766 /* Is the device operating in a specified mode (IEEE80211_IF_TYPE_XXX). */
768 int b43legacy_is_mode(struct b43legacy_wl *wl, int type)
770 return (wl->operating &&
771 wl->if_type == type);
775 bool is_bcm_board_vendor(struct b43legacy_wldev *dev)
777 return (dev->dev->bus->boardinfo.vendor == PCI_VENDOR_ID_BROADCOM);
781 u16 b43legacy_read16(struct b43legacy_wldev *dev, u16 offset)
783 return ssb_read16(dev->dev, offset);
787 void b43legacy_write16(struct b43legacy_wldev *dev, u16 offset, u16 value)
789 ssb_write16(dev->dev, offset, value);
793 u32 b43legacy_read32(struct b43legacy_wldev *dev, u16 offset)
795 return ssb_read32(dev->dev, offset);
799 void b43legacy_write32(struct b43legacy_wldev *dev, u16 offset, u32 value)
801 ssb_write32(dev->dev, offset, value);
805 struct b43legacy_lopair *b43legacy_get_lopair(struct b43legacy_phy *phy,
806 u16 radio_attenuation,
807 u16 baseband_attenuation)
809 return phy->_lo_pairs + (radio_attenuation
810 + 14 * (baseband_attenuation / 2));
815 /* Message printing */
816 void b43legacyinfo(struct b43legacy_wl *wl, const char *fmt, ...)
817 __attribute__((format(printf, 2, 3)));
818 void b43legacyerr(struct b43legacy_wl *wl, const char *fmt, ...)
819 __attribute__((format(printf, 2, 3)));
820 void b43legacywarn(struct b43legacy_wl *wl, const char *fmt, ...)
821 __attribute__((format(printf, 2, 3)));
823 void b43legacydbg(struct b43legacy_wl *wl, const char *fmt, ...)
824 __attribute__((format(printf, 2, 3)));
826 # define b43legacydbg(wl, fmt...) do { /* nothing */ } while (0)
830 /** Limit a value between two limits */
834 #define limit_value(value, min, max) \
836 typeof(value) __value = (value); \
837 typeof(value) __min = (min); \
838 typeof(value) __max = (max); \
839 if (__value < __min) \
841 else if (__value > __max) \
846 /* Macros for printing a value in Q5.2 format */
847 #define Q52_FMT "%u.%u"
848 #define Q52_ARG(q52) ((q52) / 4), (((q52) & 3) * 100 / 4)
850 #endif /* B43legacy_H_ */