3 Broadcom B43 wireless driver
4 IEEE 802.11n PHY support
6 Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING. If not, write to
20 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
21 Boston, MA 02110-1301, USA.
25 #include <linux/delay.h>
26 #include <linux/types.h>
30 #include "tables_nphy.h"
40 struct nphy_iqcal_params {
58 enum b43_nphy_rf_sequence {
62 B43_RFSEQ_UPDATE_GAINH,
63 B43_RFSEQ_UPDATE_GAINL,
64 B43_RFSEQ_UPDATE_GAINU,
67 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
68 u8 *events, u8 *delays, u8 length);
69 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
70 enum b43_nphy_rf_sequence seq);
71 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
72 u16 value, u8 core, bool off);
73 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
76 void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
80 static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
84 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
87 return B43_TXPWR_RES_DONE;
90 static void b43_chantab_radio_upload(struct b43_wldev *dev,
91 const struct b43_nphy_channeltab_entry *e)
93 b43_radio_write16(dev, B2055_PLL_REF, e->radio_pll_ref);
94 b43_radio_write16(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
95 b43_radio_write16(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
96 b43_radio_write16(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
97 b43_radio_write16(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
98 b43_radio_write16(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
99 b43_radio_write16(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
100 b43_radio_write16(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
101 b43_radio_write16(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
102 b43_radio_write16(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
103 b43_radio_write16(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
104 b43_radio_write16(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
105 b43_radio_write16(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
106 b43_radio_write16(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
107 b43_radio_write16(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
108 b43_radio_write16(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
109 b43_radio_write16(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
110 b43_radio_write16(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
111 b43_radio_write16(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
112 b43_radio_write16(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
113 b43_radio_write16(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
114 b43_radio_write16(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
117 static void b43_chantab_phy_upload(struct b43_wldev *dev,
118 const struct b43_nphy_channeltab_entry *e)
120 b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
121 b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
122 b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
123 b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
124 b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
125 b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
128 static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
133 /* Tune the hardware to a new channel. */
134 static int nphy_channel_switch(struct b43_wldev *dev, unsigned int channel)
136 const struct b43_nphy_channeltab_entry *tabent;
138 tabent = b43_nphy_get_chantabent(dev, channel);
142 //FIXME enable/disable band select upper20 in RXCTL
143 if (0 /*FIXME 5Ghz*/)
144 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x20);
146 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x50);
147 b43_chantab_radio_upload(dev, tabent);
149 b43_radio_write16(dev, B2055_VCO_CAL10, 5);
150 b43_radio_write16(dev, B2055_VCO_CAL10, 45);
151 b43_radio_write16(dev, B2055_VCO_CAL10, 65);
153 if (0 /*FIXME 5Ghz*/)
154 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
156 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
157 b43_chantab_phy_upload(dev, tabent);
158 b43_nphy_tx_power_fix(dev);
163 static void b43_radio_init2055_pre(struct b43_wldev *dev)
165 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
166 ~B43_NPHY_RFCTL_CMD_PORFORCE);
167 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
168 B43_NPHY_RFCTL_CMD_CHIP0PU |
169 B43_NPHY_RFCTL_CMD_OEPORFORCE);
170 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
171 B43_NPHY_RFCTL_CMD_PORFORCE);
174 static void b43_radio_init2055_post(struct b43_wldev *dev)
176 struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
177 struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo);
181 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
183 if ((sprom->revision != 4) ||
184 !(sprom->boardflags_hi & B43_BFH_RSSIINV)) {
185 if ((binfo->vendor != PCI_VENDOR_ID_BROADCOM) ||
186 (binfo->type != 0x46D) ||
187 (binfo->rev < 0x41)) {
188 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
189 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
193 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0x3F, 0x2C);
195 b43_radio_write16(dev, B2055_CAL_MISC, 0x3C);
197 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
199 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
201 b43_radio_set(dev, B2055_CAL_MISC, 0x1);
203 b43_radio_set(dev, B2055_CAL_MISC, 0x40);
205 for (i = 0; i < 100; i++) {
206 val = b43_radio_read16(dev, B2055_CAL_COUT2);
212 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
214 nphy_channel_switch(dev, dev->phy.channel);
215 b43_radio_write16(dev, B2055_C1_RX_BB_LPF, 0x9);
216 b43_radio_write16(dev, B2055_C2_RX_BB_LPF, 0x9);
217 b43_radio_write16(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
218 b43_radio_write16(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
221 /* Initialize a Broadcom 2055 N-radio */
222 static void b43_radio_init2055(struct b43_wldev *dev)
224 b43_radio_init2055_pre(dev);
225 if (b43_status(dev) < B43_STAT_INITIALIZED)
226 b2055_upload_inittab(dev, 0, 1);
228 b2055_upload_inittab(dev, 0/*FIXME on 5ghz band*/, 0);
229 b43_radio_init2055_post(dev);
232 void b43_nphy_radio_turn_on(struct b43_wldev *dev)
234 b43_radio_init2055(dev);
237 void b43_nphy_radio_turn_off(struct b43_wldev *dev)
239 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
240 ~B43_NPHY_RFCTL_CMD_EN);
244 * Upload the N-PHY tables.
245 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
247 static void b43_nphy_tables_init(struct b43_wldev *dev)
249 if (dev->phy.rev < 3)
250 b43_nphy_rev0_1_2_tables_init(dev);
252 b43_nphy_rev3plus_tables_init(dev);
255 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
256 static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
258 struct b43_phy_n *nphy = dev->phy.n;
259 enum ieee80211_band band;
263 nphy->rfctrl_intc1_save = b43_phy_read(dev,
264 B43_NPHY_RFCTL_INTC1);
265 nphy->rfctrl_intc2_save = b43_phy_read(dev,
266 B43_NPHY_RFCTL_INTC2);
267 band = b43_current_band(dev->wl);
268 if (dev->phy.rev >= 3) {
269 if (band == IEEE80211_BAND_5GHZ)
274 if (band == IEEE80211_BAND_5GHZ)
279 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
280 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
282 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
283 nphy->rfctrl_intc1_save);
284 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
285 nphy->rfctrl_intc2_save);
289 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
290 static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
292 struct b43_phy_n *nphy = dev->phy.n;
294 enum ieee80211_band band = b43_current_band(dev->wl);
295 bool ipa = (nphy->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
296 (nphy->ipa5g_on && band == IEEE80211_BAND_5GHZ);
298 if (dev->phy.rev >= 3) {
301 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
302 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
306 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
307 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
311 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
312 static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force)
316 if (dev->phy.type != B43_PHYTYPE_N)
319 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
321 tmslow |= SSB_TMSLOW_FGC;
323 tmslow &= ~SSB_TMSLOW_FGC;
324 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
327 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
328 static void b43_nphy_reset_cca(struct b43_wldev *dev)
332 b43_nphy_bmac_clock_fgc(dev, 1);
333 bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
334 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
336 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
337 b43_nphy_bmac_clock_fgc(dev, 0);
338 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
341 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
342 static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
344 u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
346 mimocfg |= B43_NPHY_MIMOCFG_AUTO;
348 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
350 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
352 b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
355 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
356 static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
358 struct b43_phy_n *nphy = dev->phy.n;
360 bool override = false;
363 if (nphy->txrx_chain == 0) {
366 } else if (nphy->txrx_chain == 1) {
371 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
372 ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
376 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
377 B43_NPHY_RFSEQMODE_CAOVER);
379 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
380 ~B43_NPHY_RFSEQMODE_CAOVER);
383 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
384 static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
385 u16 samps, u8 time, bool wait)
390 b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
391 b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
393 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
395 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
397 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
399 for (i = 1000; i; i--) {
400 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
401 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
402 est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
403 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
404 est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
405 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
406 est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
407 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
409 est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
410 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
411 est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
412 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
413 est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
414 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
419 memset(est, 0, sizeof(*est));
422 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
423 static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
424 struct b43_phy_n_iq_comp *pcomp)
427 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
428 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
429 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
430 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
432 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
433 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
434 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
435 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
439 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
440 static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
442 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
444 b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
446 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
447 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
449 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
450 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
452 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
453 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
454 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
455 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
456 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
457 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
458 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
459 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
462 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
463 static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
466 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
468 regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
470 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
471 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
473 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
474 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
476 regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
477 regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
478 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
479 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
480 regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
481 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
482 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
483 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
485 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
486 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
488 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, (u16)~B43_NPHY_RFSEQCA_RXDIS,
489 ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
490 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
491 ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
492 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
493 (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
494 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
495 (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
498 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
499 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
501 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
502 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
505 b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
506 b43_nphy_rf_control_override(dev, 8, 0, 3, false);
507 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
516 b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
517 b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
520 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
521 static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
527 int iq_nbits, qq_nbits;
531 struct nphy_iq_est est;
532 struct b43_phy_n_iq_comp old;
533 struct b43_phy_n_iq_comp new = { };
539 b43_nphy_rx_iq_coeffs(dev, false, &old);
540 b43_nphy_rx_iq_coeffs(dev, true, &new);
541 b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
544 for (i = 0; i < 2; i++) {
545 if (i == 0 && (mask & 1)) {
549 } else if (i == 1 && (mask & 2)) {
563 iq_nbits = fls(abs(iq));
566 arsh = iq_nbits - 20;
568 a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
571 a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
580 brsh = qq_nbits - 11;
582 b = (qq << (31 - qq_nbits));
585 b = (qq << (31 - qq_nbits));
592 b = int_sqrt(b / tmp - a * a) - (1 << 10);
594 if (i == 0 && (mask & 0x1)) {
595 if (dev->phy.rev >= 3) {
602 } else if (i == 1 && (mask & 0x2)) {
603 if (dev->phy.rev >= 3) {
616 b43_nphy_rx_iq_coeffs(dev, true, &new);
619 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
620 static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
625 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C50);
626 for (i = 0; i < 4; i++)
627 array[i] = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
629 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
630 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
631 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
632 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
635 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
636 static void b43_nphy_write_clip_detection(struct b43_wldev *dev, u16 *clip_st)
638 b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
639 b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
642 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
643 static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
645 clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
646 clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
649 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
650 static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
654 if (dev->dev->id.revision == 16)
655 b43_mac_suspend(dev);
657 tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
658 tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
659 B43_NPHY_CLASSCTL_WAITEDEN);
662 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
664 if (dev->dev->id.revision == 16)
670 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
671 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
673 struct b43_phy *phy = &dev->phy;
674 struct b43_phy_n *nphy = phy->n;
677 u16 clip[] = { 0xFFFF, 0xFFFF };
678 if (nphy->deaf_count++ == 0) {
679 nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
680 b43_nphy_classifier(dev, 0x7, 0);
681 b43_nphy_read_clip_detection(dev, nphy->clip_state);
682 b43_nphy_write_clip_detection(dev, clip);
684 b43_nphy_reset_cca(dev);
686 if (--nphy->deaf_count == 0) {
687 b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
688 b43_nphy_write_clip_detection(dev, nphy->clip_state);
693 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
694 static void b43_nphy_stop_playback(struct b43_wldev *dev)
696 struct b43_phy_n *nphy = dev->phy.n;
699 if (nphy->hang_avoid)
700 b43_nphy_stay_in_carrier_search(dev, 1);
702 tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
704 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
706 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, (u16)~0x8000);
708 b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
710 if (nphy->bb_mult_save & 0x80000000) {
711 tmp = nphy->bb_mult_save & 0xFFFF;
712 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
713 nphy->bb_mult_save = 0;
716 if (nphy->hang_avoid)
717 b43_nphy_stay_in_carrier_search(dev, 0);
720 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
721 static void b43_nphy_gain_crtl_workarounds(struct b43_wldev *dev)
723 struct b43_phy_n *nphy = dev->phy.n;
727 /* TODO: for PHY >= 3
728 s8 *lna1_gain, *lna2_gain;
729 u8 *gain_db, *gain_bits;
731 u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
732 u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
735 u8 rfseq_events[3] = { 6, 8, 7 };
736 u8 rfseq_delays[3] = { 10, 30, 1 };
738 if (dev->phy.rev >= 3) {
741 /* Set Clip 2 detect */
742 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
743 B43_NPHY_C1_CGAINI_CL2DETECT);
744 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
745 B43_NPHY_C2_CGAINI_CL2DETECT);
747 /* Set narrowband clip threshold */
748 b43_phy_set(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
749 b43_phy_set(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
751 if (!dev->phy.is_40mhz) {
752 /* Set dwell lengths */
753 b43_phy_set(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
754 b43_phy_set(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
755 b43_phy_set(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
756 b43_phy_set(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
759 /* Set wideband clip 2 threshold */
760 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
761 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
763 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
764 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
767 if (!dev->phy.is_40mhz) {
768 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
769 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
770 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
771 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
772 b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
773 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
774 b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
775 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
778 b43_phy_set(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
780 if (nphy->gain_boost) {
781 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
787 code = dev->phy.is_40mhz ? 6 : 7;
790 /* Set HPVGA2 index */
791 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
792 ~B43_NPHY_C1_INITGAIN_HPVGA2,
793 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
794 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
795 ~B43_NPHY_C2_INITGAIN_HPVGA2,
796 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
798 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
799 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
801 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
804 /* TODO: b43_nphy_adjust_lna_gain_table(dev); */
806 if (nphy->elna_gain_config) {
807 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
808 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
809 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
810 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
811 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
813 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
814 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
815 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
816 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
817 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
819 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
820 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
822 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
826 if (dev->phy.rev == 2) {
827 for (i = 0; i < 4; i++) {
828 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
829 (0x0400 * i) + 0x0020);
830 for (j = 0; j < 21; j++)
832 B43_NPHY_TABLE_DATALO, 3 * j);
835 b43_nphy_set_rf_sequence(dev, 5,
836 rfseq_events, rfseq_delays, 3);
837 b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
838 (u16)~B43_NPHY_OVER_DGAIN_CCKDGECV,
839 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
841 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
842 b43_phy_maskset(dev, B43_PHY_N(0xC5D),
848 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
849 static void b43_nphy_workarounds(struct b43_wldev *dev)
851 struct ssb_bus *bus = dev->dev->bus;
852 struct b43_phy *phy = &dev->phy;
853 struct b43_phy_n *nphy = phy->n;
855 u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
856 u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
858 u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
859 u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
861 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
862 b43_nphy_classifier(dev, 1, 0);
864 b43_nphy_classifier(dev, 1, 1);
866 if (nphy->hang_avoid)
867 b43_nphy_stay_in_carrier_search(dev, 1);
869 b43_phy_set(dev, B43_NPHY_IQFLIP,
870 B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
872 if (dev->phy.rev >= 3) {
875 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
876 nphy->band5g_pwrgain) {
877 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
878 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
880 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
881 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
884 /* TODO: convert to b43_ntab_write? */
885 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2000);
886 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A);
887 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2010);
888 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A);
889 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2002);
890 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA);
891 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2012);
892 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA);
894 if (dev->phy.rev < 2) {
895 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2008);
896 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000);
897 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2018);
898 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000);
899 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2007);
900 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB);
901 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2017);
902 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB);
903 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2006);
904 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800);
905 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2016);
906 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800);
909 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
910 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
911 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
912 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
914 if (bus->sprom.boardflags2_lo & 0x100 &&
915 bus->boardinfo.type == 0x8B) {
919 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
920 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
922 b43_nphy_gain_crtl_workarounds(dev);
924 if (dev->phy.rev < 2) {
925 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
926 ; /*TODO: b43_mhf(dev, 2, 0x0010, 0x0010, 3);*/
927 } else if (dev->phy.rev == 2) {
928 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
929 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
932 if (dev->phy.rev < 2)
933 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
934 ~B43_NPHY_SCRAM_SIGCTL_SCM);
936 /* Set phase track alpha and beta */
937 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
938 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
939 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
940 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
941 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
942 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
944 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
945 (u16)~B43_NPHY_PIL_DW_64QAM);
946 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
947 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
948 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
950 if (dev->phy.rev == 2)
951 b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
952 B43_NPHY_FINERX2_CGC_DECGC);
955 if (nphy->hang_avoid)
956 b43_nphy_stay_in_carrier_search(dev, 0);
959 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
960 static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
964 u16 bw, len, rot, angle;
965 struct b43_c32 *samples;
968 bw = (dev->phy.is_40mhz) ? 40 : 20;
972 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
977 if (dev->phy.is_40mhz)
983 samples = kzalloc(len * sizeof(struct b43_c32), GFP_KERNEL);
984 rot = (((freq * 36) / bw) << 16) / 100;
987 for (i = 0; i < len; i++) {
988 samples[i] = b43_cordic(angle);
990 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
991 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
994 /* TODO: Call N PHY Load Sample Table with buffer, len as arguments */
999 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
1000 static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1001 u16 wait, bool iqmode, bool dac_test)
1003 struct b43_phy_n *nphy = dev->phy.n;
1008 if (nphy->hang_avoid)
1009 b43_nphy_stay_in_carrier_search(dev, true);
1011 if ((nphy->bb_mult_save & 0x80000000) == 0) {
1012 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1013 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1016 if (!dev->phy.is_40mhz)
1020 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1022 if (nphy->hang_avoid)
1023 b43_nphy_stay_in_carrier_search(dev, false);
1025 b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
1027 if (loops != 0xFFFF)
1028 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1030 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
1032 b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
1034 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1036 b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1038 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1039 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1042 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
1044 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
1046 for (i = 0; i < 100; i++) {
1047 if (b43_phy_read(dev, B43_NPHY_RFSEQST) & 1) {
1054 b43err(dev->wl, "run samples timeout\n");
1056 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1060 * Transmits a known value for LO calibration
1061 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
1063 static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
1064 bool iqmode, bool dac_test)
1066 u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
1069 b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
1073 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
1074 static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
1076 struct b43_phy_n *nphy = dev->phy.n;
1079 u32 cur_real, cur_imag, real_part, imag_part;
1083 if (nphy->hang_avoid)
1084 b43_nphy_stay_in_carrier_search(dev, true);
1086 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
1088 for (i = 0; i < 2; i++) {
1089 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
1090 (buffer[i * 2 + 1] & 0x3FF);
1091 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1092 (((i + 26) << 10) | 320));
1093 for (j = 0; j < 128; j++) {
1094 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1095 ((tmp >> 16) & 0xFFFF));
1096 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1101 for (i = 0; i < 2; i++) {
1102 tmp = buffer[5 + i];
1103 real_part = (tmp >> 8) & 0xFF;
1104 imag_part = (tmp & 0xFF);
1105 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1106 (((i + 26) << 10) | 448));
1108 if (dev->phy.rev >= 3) {
1109 cur_real = real_part;
1110 cur_imag = imag_part;
1111 tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
1114 for (j = 0; j < 128; j++) {
1115 if (dev->phy.rev < 3) {
1116 cur_real = (real_part * loscale[j] + 128) >> 8;
1117 cur_imag = (imag_part * loscale[j] + 128) >> 8;
1118 tmp = ((cur_real & 0xFF) << 8) |
1121 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1122 ((tmp >> 16) & 0xFFFF));
1123 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1128 if (dev->phy.rev >= 3) {
1129 b43_shm_write16(dev, B43_SHM_SHARED,
1130 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
1131 b43_shm_write16(dev, B43_SHM_SHARED,
1132 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
1135 if (nphy->hang_avoid)
1136 b43_nphy_stay_in_carrier_search(dev, false);
1139 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
1140 static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
1141 u8 *events, u8 *delays, u8 length)
1143 struct b43_phy_n *nphy = dev->phy.n;
1145 u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
1146 u16 offset1 = cmd << 4;
1147 u16 offset2 = offset1 + 0x80;
1149 if (nphy->hang_avoid)
1150 b43_nphy_stay_in_carrier_search(dev, true);
1152 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
1153 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
1155 for (i = length; i < 16; i++) {
1156 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
1157 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
1160 if (nphy->hang_avoid)
1161 b43_nphy_stay_in_carrier_search(dev, false);
1164 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
1165 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
1166 enum b43_nphy_rf_sequence seq)
1168 static const u16 trigger[] = {
1169 [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
1170 [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
1171 [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
1172 [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
1173 [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
1174 [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
1177 u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1179 B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
1181 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
1182 B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
1183 b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
1184 for (i = 0; i < 200; i++) {
1185 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
1189 b43err(dev->wl, "RF sequence status timeout\n");
1191 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1194 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
1195 static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
1196 u16 value, u8 core, bool off)
1199 u8 index = fls(field);
1200 u8 addr, en_addr, val_addr;
1201 /* we expect only one bit set */
1202 B43_WARN_ON(field & (~(1 << (index - 1))));
1204 if (dev->phy.rev >= 3) {
1205 const struct nphy_rf_control_override_rev3 *rf_ctrl;
1206 for (i = 0; i < 2; i++) {
1207 if (index == 0 || index == 16) {
1209 "Unsupported RF Ctrl Override call\n");
1213 rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
1214 en_addr = B43_PHY_N((i == 0) ?
1215 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
1216 val_addr = B43_PHY_N((i == 0) ?
1217 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
1220 b43_phy_mask(dev, en_addr, ~(field));
1221 b43_phy_mask(dev, val_addr,
1222 ~(rf_ctrl->val_mask));
1224 if (core == 0 || ((1 << core) & i) != 0) {
1225 b43_phy_set(dev, en_addr, field);
1226 b43_phy_maskset(dev, val_addr,
1227 ~(rf_ctrl->val_mask),
1228 (value << rf_ctrl->val_shift));
1233 const struct nphy_rf_control_override_rev2 *rf_ctrl;
1235 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
1238 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
1241 for (i = 0; i < 2; i++) {
1242 if (index <= 1 || index == 16) {
1244 "Unsupported RF Ctrl Override call\n");
1248 if (index == 2 || index == 10 ||
1249 (index >= 13 && index <= 15)) {
1253 rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
1254 addr = B43_PHY_N((i == 0) ?
1255 rf_ctrl->addr0 : rf_ctrl->addr1);
1257 if ((core & (1 << i)) != 0)
1258 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
1259 (value << rf_ctrl->shift));
1261 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
1262 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1263 B43_NPHY_RFCTL_CMD_START);
1265 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
1270 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
1271 static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
1277 B43_WARN_ON(dev->phy.rev < 3);
1278 B43_WARN_ON(field > 4);
1280 for (i = 0; i < 2; i++) {
1281 if ((core == 1 && i == 1) || (core == 2 && !i))
1285 B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
1286 b43_phy_mask(dev, reg, 0xFBFF);
1290 b43_phy_write(dev, reg, 0);
1291 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
1295 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
1296 0xFC3F, (value << 6));
1297 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
1299 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1300 B43_NPHY_RFCTL_CMD_START);
1301 for (j = 0; j < 100; j++) {
1302 if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START) {
1310 "intc override timeout\n");
1311 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
1314 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
1315 0xFC3F, (value << 6));
1316 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1318 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1319 B43_NPHY_RFCTL_CMD_RXTX);
1320 for (j = 0; j < 100; j++) {
1321 if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX) {
1329 "intc override timeout\n");
1330 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1335 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1342 b43_phy_maskset(dev, reg, ~tmp, val);
1345 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1352 b43_phy_maskset(dev, reg, ~tmp, val);
1355 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1362 b43_phy_maskset(dev, reg, ~tmp, val);
1368 static void b43_nphy_bphy_init(struct b43_wldev *dev)
1374 for (i = 0; i < 14; i++) {
1375 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
1379 for (i = 0; i < 16; i++) {
1380 b43_phy_write(dev, B43_PHY_N_BMODE(0x97 + i), val);
1383 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
1386 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
1387 static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
1388 s8 offset, u8 core, u8 rail, u8 type)
1391 bool core1or5 = (core == 1) || (core == 5);
1392 bool core2or5 = (core == 2) || (core == 5);
1394 offset = clamp_val(offset, -32, 31);
1395 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
1397 if (core1or5 && (rail == 0) && (type == 2))
1398 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
1399 if (core1or5 && (rail == 1) && (type == 2))
1400 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
1401 if (core2or5 && (rail == 0) && (type == 2))
1402 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
1403 if (core2or5 && (rail == 1) && (type == 2))
1404 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
1405 if (core1or5 && (rail == 0) && (type == 0))
1406 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
1407 if (core1or5 && (rail == 1) && (type == 0))
1408 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
1409 if (core2or5 && (rail == 0) && (type == 0))
1410 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
1411 if (core2or5 && (rail == 1) && (type == 0))
1412 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
1413 if (core1or5 && (rail == 0) && (type == 1))
1414 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
1415 if (core1or5 && (rail == 1) && (type == 1))
1416 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
1417 if (core2or5 && (rail == 0) && (type == 1))
1418 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1419 if (core2or5 && (rail == 1) && (type == 1))
1420 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
1421 if (core1or5 && (rail == 0) && (type == 6))
1422 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
1423 if (core1or5 && (rail == 1) && (type == 6))
1424 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
1425 if (core2or5 && (rail == 0) && (type == 6))
1426 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
1427 if (core2or5 && (rail == 1) && (type == 6))
1428 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
1429 if (core1or5 && (rail == 0) && (type == 3))
1430 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
1431 if (core1or5 && (rail == 1) && (type == 3))
1432 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
1433 if (core2or5 && (rail == 0) && (type == 3))
1434 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
1435 if (core2or5 && (rail == 1) && (type == 3))
1436 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
1437 if (core1or5 && (type == 4))
1438 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
1439 if (core2or5 && (type == 4))
1440 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
1441 if (core1or5 && (type == 5))
1442 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
1443 if (core2or5 && (type == 5))
1444 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
1447 static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1460 val = (val << 12) | (val << 14);
1461 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1462 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
1465 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
1467 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
1471 /* TODO use some definitions */
1473 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF, 0);
1475 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFEC7, 0);
1476 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xEFDC, 0);
1477 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFFFE, 0);
1479 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xFFFE, 0);
1482 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF,
1485 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1487 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1488 0xEFDC, (code << 1 | 0x1021));
1489 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFFFE, 0x1);
1491 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xFFFE, 0);
1496 static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1498 struct b43_phy_n *nphy = dev->phy.n;
1503 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
1504 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
1505 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
1506 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
1507 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
1508 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
1509 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
1510 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
1512 for (i = 0; i < 2; i++) {
1513 if ((code == 1 && i == 1) || (code == 2 && !i))
1517 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
1518 b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
1522 B43_NPHY_AFECTL_C1 :
1524 b43_phy_maskset(dev, reg, 0xFCFF, 0);
1527 B43_NPHY_RFCTL_LUT_TRSW_UP1 :
1528 B43_NPHY_RFCTL_LUT_TRSW_UP2;
1529 b43_phy_maskset(dev, reg, 0xFFC3, 0);
1532 val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
1537 b43_phy_set(dev, reg, val);
1540 B43_NPHY_TXF_40CO_B1S0 :
1541 B43_NPHY_TXF_40CO_B32S1;
1542 b43_phy_set(dev, reg, 0x0020);
1552 B43_NPHY_AFECTL_C1 :
1555 b43_phy_maskset(dev, reg, 0xFCFF, val);
1556 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
1558 if (type != 3 && type != 6) {
1559 enum ieee80211_band band =
1560 b43_current_band(dev->wl);
1562 if ((nphy->ipa2g_on &&
1563 band == IEEE80211_BAND_2GHZ) ||
1565 band == IEEE80211_BAND_5GHZ))
1566 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
1569 reg = (i == 0) ? 0x2000 : 0x3000;
1570 reg |= B2055_PADDRV;
1571 b43_radio_write16(dev, reg, val);
1574 B43_NPHY_AFECTL_OVER1 :
1575 B43_NPHY_AFECTL_OVER;
1576 b43_phy_set(dev, reg, 0x0200);
1583 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
1584 static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1586 if (dev->phy.rev >= 3)
1587 b43_nphy_rev3_rssi_select(dev, code, type);
1589 b43_nphy_rev2_rssi_select(dev, code, type);
1592 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
1593 static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
1596 for (i = 0; i < 2; i++) {
1599 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1601 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1604 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
1606 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1607 0xFC, buf[2 * i + 1]);
1611 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1614 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1615 0xF3, buf[2 * i + 1] << 2);
1620 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
1621 static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
1626 u16 save_regs_phy[9];
1629 if (dev->phy.rev >= 3) {
1630 save_regs_phy[0] = b43_phy_read(dev,
1631 B43_NPHY_RFCTL_LUT_TRSW_UP1);
1632 save_regs_phy[1] = b43_phy_read(dev,
1633 B43_NPHY_RFCTL_LUT_TRSW_UP2);
1634 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1635 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1636 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1637 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1638 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
1639 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
1642 b43_nphy_rssi_select(dev, 5, type);
1644 if (dev->phy.rev < 2) {
1645 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
1646 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
1649 for (i = 0; i < 4; i++)
1652 for (i = 0; i < nsamp; i++) {
1653 if (dev->phy.rev < 2) {
1654 s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
1655 s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
1657 s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
1658 s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
1661 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
1662 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
1663 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
1664 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
1666 out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
1667 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
1669 if (dev->phy.rev < 2)
1670 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
1672 if (dev->phy.rev >= 3) {
1673 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
1675 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1677 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
1678 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
1679 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
1680 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
1681 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
1682 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
1688 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
1689 static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
1694 u16 class, override;
1695 u8 regs_save_radio[2];
1696 u16 regs_save_phy[2];
1700 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1701 s32 results_min[4] = { };
1702 u8 vcm_final[4] = { };
1703 s32 results[4][4] = { };
1704 s32 miniq[4][2] = { };
1709 } else if (type < 2) {
1717 class = b43_nphy_classifier(dev, 0, 0);
1718 b43_nphy_classifier(dev, 7, 4);
1719 b43_nphy_read_clip_detection(dev, clip_state);
1720 b43_nphy_write_clip_detection(dev, clip_off);
1722 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1727 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1728 regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
1729 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
1730 b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
1732 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1733 regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
1734 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
1735 b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
1737 state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
1738 state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
1739 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
1740 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
1741 state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
1742 state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
1744 b43_nphy_rssi_select(dev, 5, type);
1745 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
1746 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
1748 for (i = 0; i < 4; i++) {
1750 for (j = 0; j < 4; j++)
1753 b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
1754 b43_nphy_poll_rssi(dev, type, results[i], 8);
1756 for (j = 0; j < 2; j++)
1757 miniq[i][j] = min(results[i][2 * j],
1758 results[i][2 * j + 1]);
1761 for (i = 0; i < 4; i++) {
1766 for (j = 0; j < 4; j++) {
1768 curr = abs(results[j][i]);
1770 curr = abs(miniq[j][i / 2] - code * 8);
1777 if (results[j][i] < minpoll)
1778 minpoll = results[j][i];
1780 results_min[i] = minpoll;
1781 vcm_final[i] = minvcm;
1785 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
1787 for (i = 0; i < 4; i++) {
1788 offset[i] = (code * 8) - results[vcm_final[i]][i];
1791 offset[i] = -((abs(offset[i]) + 4) / 8);
1793 offset[i] = (offset[i] + 4) / 8;
1795 if (results_min[i] == 248)
1796 offset[i] = code - 32;
1799 b43_nphy_scale_offset_rssi(dev, 0, offset[i], 1, 0,
1802 b43_nphy_scale_offset_rssi(dev, 0, offset[i], 2, 1,
1806 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
1807 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[1]);
1811 b43_nphy_rssi_select(dev, 1, 2);
1814 b43_nphy_rssi_select(dev, 1, 0);
1817 b43_nphy_rssi_select(dev, 1, 1);
1820 b43_nphy_rssi_select(dev, 1, 1);
1826 b43_nphy_rssi_select(dev, 2, 2);
1829 b43_nphy_rssi_select(dev, 2, 0);
1832 b43_nphy_rssi_select(dev, 2, 1);
1836 b43_nphy_rssi_select(dev, 0, type);
1838 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
1839 b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
1840 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
1841 b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
1843 b43_nphy_classifier(dev, 7, class);
1844 b43_nphy_write_clip_detection(dev, clip_state);
1847 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
1848 static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
1855 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
1857 static void b43_nphy_rssi_cal(struct b43_wldev *dev)
1859 if (dev->phy.rev >= 3) {
1860 b43_nphy_rev3_rssi_cal(dev);
1862 b43_nphy_rev2_rssi_cal(dev, 2);
1863 b43_nphy_rev2_rssi_cal(dev, 0);
1864 b43_nphy_rev2_rssi_cal(dev, 1);
1869 * Restore RSSI Calibration
1870 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
1872 static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
1874 struct b43_phy_n *nphy = dev->phy.n;
1876 u16 *rssical_radio_regs = NULL;
1877 u16 *rssical_phy_regs = NULL;
1879 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1880 if (!nphy->rssical_chanspec_2G)
1882 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
1883 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
1885 if (!nphy->rssical_chanspec_5G)
1887 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
1888 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
1891 /* TODO use some definitions */
1892 b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
1893 b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
1895 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
1896 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
1897 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
1898 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
1900 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
1901 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
1902 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
1903 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
1905 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
1906 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
1907 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
1908 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
1911 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
1912 static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
1914 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1915 if (dev->phy.rev >= 6) {
1916 /* TODO If the chip is 47162
1917 return txpwrctrl_tx_gain_ipa_rev5 */
1918 return txpwrctrl_tx_gain_ipa_rev6;
1919 } else if (dev->phy.rev >= 5) {
1920 return txpwrctrl_tx_gain_ipa_rev5;
1922 return txpwrctrl_tx_gain_ipa;
1925 return txpwrctrl_tx_gain_ipa_5g;
1929 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
1930 static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
1932 struct b43_phy_n *nphy = dev->phy.n;
1933 u16 *save = nphy->tx_rx_cal_radio_saveregs;
1937 if (dev->phy.rev >= 3) {
1938 for (i = 0; i < 2; i++) {
1939 tmp = (i == 0) ? 0x2000 : 0x3000;
1942 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL);
1943 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL);
1944 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS);
1945 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS);
1946 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS);
1947 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV);
1948 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1);
1949 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2);
1950 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL);
1951 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC);
1952 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1);
1954 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1955 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
1956 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
1957 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
1958 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
1959 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
1960 if (nphy->ipa5g_on) {
1961 b43_radio_write16(dev, tmp | B2055_PADDRV, 4);
1962 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1);
1964 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
1965 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F);
1967 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
1969 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06);
1970 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
1971 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
1972 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
1973 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
1974 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0);
1975 if (nphy->ipa2g_on) {
1976 b43_radio_write16(dev, tmp | B2055_PADDRV, 6);
1977 b43_radio_write16(dev, tmp | B2055_XOCTL2,
1978 (dev->phy.rev < 5) ? 0x11 : 0x01);
1980 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
1981 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
1984 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0);
1985 b43_radio_write16(dev, tmp | B2055_XOMISC, 0);
1986 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0);
1989 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
1990 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
1992 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
1993 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
1995 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
1996 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
1998 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
1999 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
2001 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
2002 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
2004 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
2005 B43_NPHY_BANDCTL_5GHZ)) {
2006 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
2007 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
2009 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
2010 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
2013 if (dev->phy.rev < 2) {
2014 b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
2015 b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
2017 b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
2018 b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
2023 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
2024 static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
2025 struct nphy_txgains target,
2026 struct nphy_iqcal_params *params)
2031 if (dev->phy.rev >= 3) {
2032 params->txgm = target.txgm[core];
2033 params->pga = target.pga[core];
2034 params->pad = target.pad[core];
2035 params->ipa = target.ipa[core];
2036 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
2037 (params->pad << 4) | (params->ipa);
2038 for (j = 0; j < 5; j++)
2039 params->ncorr[j] = 0x79;
2041 gain = (target.pad[core]) | (target.pga[core] << 4) |
2042 (target.txgm[core] << 8);
2044 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
2046 for (i = 0; i < 9; i++)
2047 if (tbl_iqcal_gainparams[indx][i][0] == gain)
2051 params->txgm = tbl_iqcal_gainparams[indx][i][1];
2052 params->pga = tbl_iqcal_gainparams[indx][i][2];
2053 params->pad = tbl_iqcal_gainparams[indx][i][3];
2054 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
2056 for (j = 0; j < 4; j++)
2057 params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
2061 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
2062 static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
2064 struct b43_phy_n *nphy = dev->phy.n;
2068 u16 tmp = nphy->txcal_bbmult;
2073 for (i = 0; i < 18; i++) {
2074 scale = (ladder_lo[i].percent * tmp) / 100;
2075 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
2076 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
2078 scale = (ladder_iq[i].percent * tmp) / 100;
2079 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
2080 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
2084 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
2085 static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
2088 for (i = 0; i < 15; i++)
2089 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
2090 tbl_tx_filter_coef_rev4[2][i]);
2093 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
2094 static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
2097 /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
2098 u16 offset[] = { 0x186, 0x195, 0x2C5 };
2100 for (i = 0; i < 3; i++)
2101 for (j = 0; j < 15; j++)
2102 b43_phy_write(dev, B43_PHY_N(offset[i] + j),
2103 tbl_tx_filter_coef_rev4[i][j]);
2105 if (dev->phy.is_40mhz) {
2106 for (j = 0; j < 15; j++)
2107 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2108 tbl_tx_filter_coef_rev4[3][j]);
2109 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2110 for (j = 0; j < 15; j++)
2111 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2112 tbl_tx_filter_coef_rev4[5][j]);
2115 if (dev->phy.channel == 14)
2116 for (j = 0; j < 15; j++)
2117 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2118 tbl_tx_filter_coef_rev4[6][j]);
2121 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
2122 static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
2124 struct b43_phy_n *nphy = dev->phy.n;
2127 struct nphy_txgains target;
2128 const u32 *table = NULL;
2130 if (nphy->txpwrctrl == 0) {
2133 if (nphy->hang_avoid)
2134 b43_nphy_stay_in_carrier_search(dev, true);
2135 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
2136 if (nphy->hang_avoid)
2137 b43_nphy_stay_in_carrier_search(dev, false);
2139 for (i = 0; i < 2; ++i) {
2140 if (dev->phy.rev >= 3) {
2141 target.ipa[i] = curr_gain[i] & 0x000F;
2142 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
2143 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
2144 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
2146 target.ipa[i] = curr_gain[i] & 0x0003;
2147 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
2148 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
2149 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
2155 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
2156 B43_NPHY_TXPCTL_STAT_BIDX) >>
2157 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2158 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
2159 B43_NPHY_TXPCTL_STAT_BIDX) >>
2160 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2162 for (i = 0; i < 2; ++i) {
2163 if (dev->phy.rev >= 3) {
2164 enum ieee80211_band band =
2165 b43_current_band(dev->wl);
2167 if ((nphy->ipa2g_on &&
2168 band == IEEE80211_BAND_2GHZ) ||
2170 band == IEEE80211_BAND_5GHZ)) {
2171 table = b43_nphy_get_ipa_gain_table(dev);
2173 if (band == IEEE80211_BAND_5GHZ) {
2174 if (dev->phy.rev == 3)
2175 table = b43_ntab_tx_gain_rev3_5ghz;
2176 else if (dev->phy.rev == 4)
2177 table = b43_ntab_tx_gain_rev4_5ghz;
2179 table = b43_ntab_tx_gain_rev5plus_5ghz;
2181 table = b43_ntab_tx_gain_rev3plus_2ghz;
2185 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
2186 target.pad[i] = (table[index[i]] >> 20) & 0xF;
2187 target.pga[i] = (table[index[i]] >> 24) & 0xF;
2188 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
2190 table = b43_ntab_tx_gain_rev0_1_2;
2192 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
2193 target.pad[i] = (table[index[i]] >> 18) & 0x3;
2194 target.pga[i] = (table[index[i]] >> 20) & 0x7;
2195 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
2203 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
2204 static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
2206 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2208 if (dev->phy.rev >= 3) {
2209 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
2210 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
2211 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
2212 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
2213 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
2214 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
2215 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
2216 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
2217 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
2218 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
2219 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
2220 b43_nphy_reset_cca(dev);
2222 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
2223 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
2224 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
2225 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
2226 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
2227 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
2228 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
2232 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
2233 static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
2235 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2238 regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2239 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2240 if (dev->phy.rev >= 3) {
2241 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
2242 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
2244 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2246 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
2248 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2250 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
2252 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
2253 b43_phy_mask(dev, B43_NPHY_BBCFG, (u16)~B43_NPHY_BBCFG_RSTRX);
2255 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
2257 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
2259 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
2261 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
2262 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2263 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2265 b43_nphy_rf_control_intc_override(dev, 2, 1, 3);
2266 b43_nphy_rf_control_intc_override(dev, 1, 2, 1);
2267 b43_nphy_rf_control_intc_override(dev, 1, 8, 2);
2269 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
2270 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
2271 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
2272 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
2274 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
2275 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
2276 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2278 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
2279 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
2282 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
2283 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
2286 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
2287 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2288 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2289 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2293 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
2294 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
2298 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
2299 static void b43_nphy_save_cal(struct b43_wldev *dev)
2301 struct b43_phy_n *nphy = dev->phy.n;
2303 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
2304 u16 *txcal_radio_regs = NULL;
2308 if (nphy->hang_avoid)
2309 b43_nphy_stay_in_carrier_search(dev, 1);
2311 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2312 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
2313 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
2314 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
2315 table = nphy->cal_cache.txcal_coeffs_2G;
2317 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
2318 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
2319 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
2320 table = nphy->cal_cache.txcal_coeffs_5G;
2323 b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
2324 /* TODO use some definitions */
2325 if (dev->phy.rev >= 3) {
2326 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
2327 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
2328 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
2329 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
2330 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
2331 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
2332 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
2333 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
2335 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
2336 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
2337 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
2338 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
2340 *iqcal_chanspec = nphy->radio_chanspec;
2341 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 8, table);
2343 if (nphy->hang_avoid)
2344 b43_nphy_stay_in_carrier_search(dev, 0);
2347 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
2348 static void b43_nphy_restore_cal(struct b43_wldev *dev)
2350 struct b43_phy_n *nphy = dev->phy.n;
2357 u16 *txcal_radio_regs = NULL;
2358 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
2360 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2361 if (nphy->iqcal_chanspec_2G == 0)
2363 table = nphy->cal_cache.txcal_coeffs_2G;
2364 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
2366 if (nphy->iqcal_chanspec_5G == 0)
2368 table = nphy->cal_cache.txcal_coeffs_5G;
2369 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
2372 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
2374 for (i = 0; i < 4; i++) {
2375 if (dev->phy.rev >= 3)
2381 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
2382 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
2383 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
2385 if (dev->phy.rev < 2)
2386 b43_nphy_tx_iq_workaround(dev);
2388 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2389 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
2390 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
2392 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
2393 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
2396 /* TODO use some definitions */
2397 if (dev->phy.rev >= 3) {
2398 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
2399 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
2400 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
2401 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
2402 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
2403 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
2404 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
2405 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
2407 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
2408 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
2409 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
2410 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
2412 b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
2415 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
2416 static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
2417 struct nphy_txgains target,
2418 bool full, bool mphase)
2420 struct b43_phy_n *nphy = dev->phy.n;
2426 u16 tmp, core, type, count, max, numb, last, cmd;
2434 struct nphy_iqcal_params params[2];
2435 bool updated[2] = { };
2437 b43_nphy_stay_in_carrier_search(dev, true);
2439 if (dev->phy.rev >= 4) {
2440 avoid = nphy->hang_avoid;
2441 nphy->hang_avoid = 0;
2444 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
2446 for (i = 0; i < 2; i++) {
2447 b43_nphy_iq_cal_gain_params(dev, i, target, ¶ms[i]);
2448 gain[i] = params[i].cal_gain;
2451 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
2453 b43_nphy_tx_cal_radio_setup(dev);
2454 b43_nphy_tx_cal_phy_setup(dev);
2456 phy6or5x = dev->phy.rev >= 6 ||
2457 (dev->phy.rev == 5 && nphy->ipa2g_on &&
2458 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
2460 if (dev->phy.is_40mhz) {
2461 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
2462 tbl_tx_iqlo_cal_loft_ladder_40);
2463 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
2464 tbl_tx_iqlo_cal_iqimb_ladder_40);
2466 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
2467 tbl_tx_iqlo_cal_loft_ladder_20);
2468 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
2469 tbl_tx_iqlo_cal_iqimb_ladder_20);
2473 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
2475 if (!dev->phy.is_40mhz)
2480 if (nphy->mphase_cal_phase_id > 2)
2481 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
2482 0xFFFF, 0, true, false);
2484 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
2487 if (nphy->mphase_cal_phase_id > 2) {
2488 table = nphy->mphase_txcal_bestcoeffs;
2490 if (dev->phy.rev < 3)
2493 if (!full && nphy->txiqlocal_coeffsvalid) {
2494 table = nphy->txiqlocal_bestc;
2496 if (dev->phy.rev < 3)
2500 if (dev->phy.rev >= 3) {
2501 table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
2502 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
2504 table = tbl_tx_iqlo_cal_startcoefs;
2505 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
2510 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
2513 if (dev->phy.rev >= 3)
2514 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
2516 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
2518 if (dev->phy.rev >= 3)
2519 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
2521 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
2525 count = nphy->mphase_txcal_cmdidx;
2527 (u16)(count + nphy->mphase_txcal_numcmds));
2533 for (; count < numb; count++) {
2535 if (dev->phy.rev >= 3)
2536 cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
2538 cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
2540 if (dev->phy.rev >= 3)
2541 cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
2543 cmd = tbl_tx_iqlo_cal_cmds_recal[count];
2546 core = (cmd & 0x3000) >> 12;
2547 type = (cmd & 0x0F00) >> 8;
2549 if (phy6or5x && updated[core] == 0) {
2550 b43_nphy_update_tx_cal_ladder(dev, core);
2554 tmp = (params[core].ncorr[type] << 8) | 0x66;
2555 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
2557 if (type == 1 || type == 3 || type == 4) {
2558 buffer[0] = b43_ntab_read(dev,
2559 B43_NTAB16(15, 69 + core));
2560 diq_start = buffer[0];
2562 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
2566 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
2567 for (i = 0; i < 2000; i++) {
2568 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
2574 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2576 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
2579 if (type == 1 || type == 3 || type == 4)
2580 buffer[0] = diq_start;
2584 nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
2586 last = (dev->phy.rev < 3) ? 6 : 7;
2588 if (!mphase || nphy->mphase_cal_phase_id == last) {
2589 b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
2590 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
2591 if (dev->phy.rev < 3) {
2597 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
2599 b43_ntab_write_bulk(dev, B43_NTAB16(15, 101), 2,
2601 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
2603 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
2606 if (dev->phy.rev < 3)
2608 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2609 nphy->txiqlocal_bestc);
2610 nphy->txiqlocal_coeffsvalid = true;
2611 /* TODO: Set nphy->txiqlocal_chanspec to
2612 the current channel */
2615 if (dev->phy.rev < 3)
2617 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2618 nphy->mphase_txcal_bestcoeffs);
2621 b43_nphy_stop_playback(dev);
2622 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
2625 b43_nphy_tx_cal_phy_cleanup(dev);
2626 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
2628 if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
2629 b43_nphy_tx_iq_workaround(dev);
2631 if (dev->phy.rev >= 4)
2632 nphy->hang_avoid = avoid;
2634 b43_nphy_stay_in_carrier_search(dev, false);
2639 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
2640 static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
2642 struct b43_phy_n *nphy = dev->phy.n;
2647 if (!nphy->txiqlocal_coeffsvalid || 1 /* FIXME */)
2650 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
2651 for (i = 0; i < 4; i++) {
2652 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
2659 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
2660 nphy->txiqlocal_bestc);
2661 for (i = 0; i < 4; i++)
2663 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
2665 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
2666 &nphy->txiqlocal_bestc[5]);
2667 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
2668 &nphy->txiqlocal_bestc[5]);
2672 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
2673 static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
2674 struct nphy_txgains target, u8 type, bool debug)
2676 struct b43_phy_n *nphy = dev->phy.n;
2681 u16 cur_hpf1, cur_hpf2, cur_lna;
2683 enum ieee80211_band band;
2687 u16 lna[3] = { 3, 3, 1 };
2688 u16 hpf1[3] = { 7, 2, 0 };
2689 u16 hpf2[3] = { 2, 0, 0 };
2693 struct nphy_iqcal_params cal_params[2];
2694 struct nphy_iq_est est;
2696 bool playtone = true;
2699 b43_nphy_stay_in_carrier_search(dev, 1);
2701 if (dev->phy.rev < 2)
2702 b43_nphy_reapply_tx_cal_coeffs(dev);
2703 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
2704 for (i = 0; i < 2; i++) {
2705 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
2706 cal_gain[i] = cal_params[i].cal_gain;
2708 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
2710 for (i = 0; i < 2; i++) {
2712 rfctl[0] = B43_NPHY_RFCTL_INTC1;
2713 rfctl[1] = B43_NPHY_RFCTL_INTC2;
2714 afectl_core = B43_NPHY_AFECTL_C1;
2716 rfctl[0] = B43_NPHY_RFCTL_INTC2;
2717 rfctl[1] = B43_NPHY_RFCTL_INTC1;
2718 afectl_core = B43_NPHY_AFECTL_C2;
2721 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
2722 tmp[2] = b43_phy_read(dev, afectl_core);
2723 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2724 tmp[4] = b43_phy_read(dev, rfctl[0]);
2725 tmp[5] = b43_phy_read(dev, rfctl[1]);
2727 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
2728 (u16)~B43_NPHY_RFSEQCA_RXDIS,
2729 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
2730 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
2732 b43_phy_set(dev, afectl_core, 0x0006);
2733 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
2735 band = b43_current_band(dev->wl);
2737 if (nphy->rxcalparams & 0xFF000000) {
2738 if (band == IEEE80211_BAND_5GHZ)
2739 b43_phy_write(dev, rfctl[0], 0x140);
2741 b43_phy_write(dev, rfctl[0], 0x110);
2743 if (band == IEEE80211_BAND_5GHZ)
2744 b43_phy_write(dev, rfctl[0], 0x180);
2746 b43_phy_write(dev, rfctl[0], 0x120);
2749 if (band == IEEE80211_BAND_5GHZ)
2750 b43_phy_write(dev, rfctl[1], 0x148);
2752 b43_phy_write(dev, rfctl[1], 0x114);
2754 if (nphy->rxcalparams & 0x10000) {
2755 b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
2757 b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
2761 for (j = 0; i < 4; j++) {
2767 if (power[1] > 10000) {
2772 if (power[0] > 10000) {
2782 cur_lna = lna[index];
2783 cur_hpf1 = hpf1[index];
2784 cur_hpf2 = hpf2[index];
2785 cur_hpf += desired - hweight32(power[index]);
2786 cur_hpf = clamp_val(cur_hpf, 0, 10);
2793 tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
2795 b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
2797 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
2798 b43_nphy_stop_playback(dev);
2801 ret = b43_nphy_tx_tone(dev, 4000,
2802 (nphy->rxcalparams & 0xFFFF),
2806 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
2812 b43_nphy_rx_iq_est(dev, &est, 1024, 32,
2821 power[i] = ((real + imag) / 1024) + 1;
2823 b43_nphy_calc_rx_iq_comp(dev, 1 << i);
2825 b43_nphy_stop_playback(dev);
2832 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
2833 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
2834 b43_phy_write(dev, rfctl[1], tmp[5]);
2835 b43_phy_write(dev, rfctl[0], tmp[4]);
2836 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
2837 b43_phy_write(dev, afectl_core, tmp[2]);
2838 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
2844 b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
2845 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
2846 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
2848 b43_nphy_stay_in_carrier_search(dev, 0);
2853 static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
2854 struct nphy_txgains target, u8 type, bool debug)
2859 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
2860 static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
2861 struct nphy_txgains target, u8 type, bool debug)
2863 if (dev->phy.rev >= 3)
2864 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
2866 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
2871 * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
2873 int b43_phy_initn(struct b43_wldev *dev)
2875 struct ssb_bus *bus = dev->dev->bus;
2876 struct b43_phy *phy = &dev->phy;
2877 struct b43_phy_n *nphy = phy->n;
2879 struct nphy_txgains target;
2881 enum ieee80211_band tmp2;
2885 bool do_cal = false;
2887 if ((dev->phy.rev >= 3) &&
2888 (bus->sprom.boardflags_lo & B43_BFL_EXTLNA) &&
2889 (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
2890 chipco_set32(&dev->dev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40);
2892 nphy->deaf_count = 0;
2893 b43_nphy_tables_init(dev);
2894 nphy->crsminpwr_adjusted = false;
2895 nphy->noisevars_adjusted = false;
2897 /* Clear all overrides */
2898 if (dev->phy.rev >= 3) {
2899 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
2900 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
2901 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
2902 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
2904 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
2906 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
2907 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
2908 if (dev->phy.rev < 6) {
2909 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
2910 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
2912 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
2913 ~(B43_NPHY_RFSEQMODE_CAOVER |
2914 B43_NPHY_RFSEQMODE_TROVER));
2915 if (dev->phy.rev >= 3)
2916 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
2917 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
2919 if (dev->phy.rev <= 2) {
2920 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
2921 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
2922 ~B43_NPHY_BPHY_CTL3_SCALE,
2923 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
2925 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
2926 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
2928 if (bus->sprom.boardflags2_lo & 0x100 ||
2929 (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
2930 bus->boardinfo.type == 0x8B))
2931 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
2933 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
2934 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
2935 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
2936 b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
2938 b43_nphy_update_mimo_config(dev, nphy->preamble_override);
2939 b43_nphy_update_txrx_chain(dev);
2942 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
2943 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
2946 tmp2 = b43_current_band(dev->wl);
2947 if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) ||
2948 (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) {
2949 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
2950 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
2951 nphy->papd_epsilon_offset[0] << 7);
2952 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
2953 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
2954 nphy->papd_epsilon_offset[1] << 7);
2955 b43_nphy_int_pa_set_tx_dig_filters(dev);
2956 } else if (phy->rev >= 5) {
2957 b43_nphy_ext_pa_set_tx_dig_filters(dev);
2960 b43_nphy_workarounds(dev);
2962 /* Reset CCA, in init code it differs a little from standard way */
2963 b43_nphy_bmac_clock_fgc(dev, 1);
2964 tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
2965 b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
2966 b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
2967 b43_nphy_bmac_clock_fgc(dev, 0);
2969 /* TODO N PHY MAC PHY Clock Set with argument 1 */
2971 b43_nphy_pa_override(dev, false);
2972 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
2973 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
2974 b43_nphy_pa_override(dev, true);
2976 b43_nphy_classifier(dev, 0, 0);
2977 b43_nphy_read_clip_detection(dev, clip);
2978 tx_pwr_state = nphy->txpwrctrl;
2979 /* TODO N PHY TX power control with argument 0
2980 (turning off power control) */
2981 /* TODO Fix the TX Power Settings */
2982 /* TODO N PHY TX Power Control Idle TSSI */
2983 /* TODO N PHY TX Power Control Setup */
2985 if (phy->rev >= 3) {
2988 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128,
2989 b43_ntab_tx_gain_rev0_1_2);
2990 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128,
2991 b43_ntab_tx_gain_rev0_1_2);
2994 if (nphy->phyrxchain != 3)
2995 ;/* TODO N PHY RX Core Set State with phyrxchain as argument */
2996 if (nphy->mphase_cal_phase_id > 0)
2997 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
2999 do_rssi_cal = false;
3000 if (phy->rev >= 3) {
3001 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3002 do_rssi_cal = (nphy->rssical_chanspec_2G == 0);
3004 do_rssi_cal = (nphy->rssical_chanspec_5G == 0);
3007 b43_nphy_rssi_cal(dev);
3009 b43_nphy_restore_rssi_cal(dev);
3011 b43_nphy_rssi_cal(dev);
3014 if (!((nphy->measure_hold & 0x6) != 0)) {
3015 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3016 do_cal = (nphy->iqcal_chanspec_2G == 0);
3018 do_cal = (nphy->iqcal_chanspec_5G == 0);
3024 target = b43_nphy_get_tx_gains(dev);
3026 if (nphy->antsel_type == 2)
3027 ;/*TODO NPHY Superswitch Init with argument 1*/
3028 if (nphy->perical != 2) {
3029 b43_nphy_rssi_cal(dev);
3030 if (phy->rev >= 3) {
3031 nphy->cal_orig_pwr_idx[0] =
3032 nphy->txpwrindex[0].index_internal;
3033 nphy->cal_orig_pwr_idx[1] =
3034 nphy->txpwrindex[1].index_internal;
3035 /* TODO N PHY Pre Calibrate TX Gain */
3036 target = b43_nphy_get_tx_gains(dev);
3042 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false)) {
3043 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
3044 b43_nphy_save_cal(dev);
3045 else if (nphy->mphase_cal_phase_id == 0)
3046 ;/* N PHY Periodic Calibration with argument 3 */
3048 b43_nphy_restore_cal(dev);
3051 b43_nphy_tx_pwr_ctrl_coef_setup(dev);
3052 /* TODO N PHY TX Power Control Enable with argument tx_pwr_state */
3053 b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
3054 b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
3055 if (phy->rev >= 3 && phy->rev <= 6)
3056 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
3057 b43_nphy_tx_lp_fbw(dev);
3058 /* TODO N PHY Spur Workaround */
3060 b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n");
3064 static int b43_nphy_op_allocate(struct b43_wldev *dev)
3066 struct b43_phy_n *nphy;
3068 nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
3076 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
3078 struct b43_phy *phy = &dev->phy;
3079 struct b43_phy_n *nphy = phy->n;
3081 memset(nphy, 0, sizeof(*nphy));
3083 //TODO init struct b43_phy_n
3086 static void b43_nphy_op_free(struct b43_wldev *dev)
3088 struct b43_phy *phy = &dev->phy;
3089 struct b43_phy_n *nphy = phy->n;
3095 static int b43_nphy_op_init(struct b43_wldev *dev)
3097 return b43_phy_initn(dev);
3100 static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
3103 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
3104 /* OFDM registers are onnly available on A/G-PHYs */
3105 b43err(dev->wl, "Invalid OFDM PHY access at "
3106 "0x%04X on N-PHY\n", offset);
3109 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
3110 /* Ext-G registers are only available on G-PHYs */
3111 b43err(dev->wl, "Invalid EXT-G PHY access at "
3112 "0x%04X on N-PHY\n", offset);
3115 #endif /* B43_DEBUG */
3118 static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
3120 check_phyreg(dev, reg);
3121 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3122 return b43_read16(dev, B43_MMIO_PHY_DATA);
3125 static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
3127 check_phyreg(dev, reg);
3128 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3129 b43_write16(dev, B43_MMIO_PHY_DATA, value);
3132 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
3134 /* Register 1 is a 32-bit register. */
3135 B43_WARN_ON(reg == 1);
3136 /* N-PHY needs 0x100 for read access */
3139 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
3140 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3143 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
3145 /* Register 1 is a 32-bit register. */
3146 B43_WARN_ON(reg == 1);
3148 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
3149 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
3152 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
3157 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
3159 b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
3163 static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
3164 unsigned int new_channel)
3166 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3167 if ((new_channel < 1) || (new_channel > 14))
3170 if (new_channel > 200)
3174 return nphy_channel_switch(dev, new_channel);
3177 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
3179 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3184 const struct b43_phy_operations b43_phyops_n = {
3185 .allocate = b43_nphy_op_allocate,
3186 .free = b43_nphy_op_free,
3187 .prepare_structs = b43_nphy_op_prepare_structs,
3188 .init = b43_nphy_op_init,
3189 .phy_read = b43_nphy_op_read,
3190 .phy_write = b43_nphy_op_write,
3191 .radio_read = b43_nphy_op_radio_read,
3192 .radio_write = b43_nphy_op_radio_write,
3193 .software_rfkill = b43_nphy_op_software_rfkill,
3194 .switch_analog = b43_nphy_op_switch_analog,
3195 .switch_channel = b43_nphy_op_switch_channel,
3196 .get_default_chan = b43_nphy_op_get_default_chan,
3197 .recalc_txpower = b43_nphy_op_recalc_txpower,
3198 .adjust_txpower = b43_nphy_op_adjust_txpower,