SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/b43/phy_n.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4   IEEE 802.11n PHY support
   5
   6   Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>
   7
   8   This program is free software; you can redistribute it and/or modify
   9   it under the terms of the GNU General Public License as published by
  10   the Free Software Foundation; either version 2 of the License, or
  11   (at your option) any later version.
  12
  13   This program is distributed in the hope that it will be useful,
  14   but WITHOUT ANY WARRANTY; without even the implied warranty of
  15   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16   GNU General Public License for more details.
  17
  18   You should have received a copy of the GNU General Public License
  19   along with this program; see the file COPYING.  If not, write to
  20   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  21   Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #include <linux/delay.h>
  26 #include <linux/types.h>
  27
  28 #include "b43.h"
  29 #include "phy_n.h"
  30 #include "tables_nphy.h"
  31 #include "main.h"
  32
  33 struct nphy_txgains {
  34         u16 txgm[2];
  35         u16 pga[2];
  36         u16 pad[2];
  37         u16 ipa[2];
  38 };
  39
  40 struct nphy_iqcal_params {
  41         u16 txgm;
  42         u16 pga;
  43         u16 pad;
  44         u16 ipa;
  45         u16 cal_gain;
  46         u16 ncorr[5];
  47 };
  48
  49 struct nphy_iq_est {
  50         s32 iq0_prod;
  51         u32 i0_pwr;
  52         u32 q0_pwr;
  53         s32 iq1_prod;
  54         u32 i1_pwr;
  55         u32 q1_pwr;
  56 };
  57
  58 void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
  59 {//TODO
  60 }
  61
  62 static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
  63 {//TODO
  64 }
  65
  66 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
  67                                                         bool ignore_tssi)
  68 {//TODO
  69         return B43_TXPWR_RES_DONE;
  70 }
  71
  72 static void b43_chantab_radio_upload(struct b43_wldev *dev,
  73                                      const struct b43_nphy_channeltab_entry *e)
  74 {
  75         b43_radio_write16(dev, B2055_PLL_REF, e->radio_pll_ref);
  76         b43_radio_write16(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
  77         b43_radio_write16(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
  78         b43_radio_write16(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
  79         b43_radio_write16(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
  80         b43_radio_write16(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
  81         b43_radio_write16(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
  82         b43_radio_write16(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
  83         b43_radio_write16(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
  84         b43_radio_write16(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
  85         b43_radio_write16(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
  86         b43_radio_write16(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
  87         b43_radio_write16(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
  88         b43_radio_write16(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
  89         b43_radio_write16(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
  90         b43_radio_write16(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
  91         b43_radio_write16(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
  92         b43_radio_write16(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
  93         b43_radio_write16(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
  94         b43_radio_write16(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
  95         b43_radio_write16(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
  96         b43_radio_write16(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
  97 }
  98
  99 static void b43_chantab_phy_upload(struct b43_wldev *dev,
 100                                    const struct b43_nphy_channeltab_entry *e)
 101 {
 102         b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
 103         b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
 104         b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
 105         b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
 106         b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
 107         b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
 108 }
 109
 110 static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
 111 {
 112         //TODO
 113 }
 114
 115 /* Tune the hardware to a new channel. */
 116 static int nphy_channel_switch(struct b43_wldev *dev, unsigned int channel)
 117 {
 118         const struct b43_nphy_channeltab_entry *tabent;
 119
 120         tabent = b43_nphy_get_chantabent(dev, channel);
 121         if (!tabent)
 122                 return -ESRCH;
 123
 124         //FIXME enable/disable band select upper20 in RXCTL
 125         if (0 /*FIXME 5Ghz*/)
 126                 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x20);
 127         else
 128                 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x50);
 129         b43_chantab_radio_upload(dev, tabent);
 130         udelay(50);
 131         b43_radio_write16(dev, B2055_VCO_CAL10, 5);
 132         b43_radio_write16(dev, B2055_VCO_CAL10, 45);
 133         b43_radio_write16(dev, B2055_VCO_CAL10, 65);
 134         udelay(300);
 135         if (0 /*FIXME 5Ghz*/)
 136                 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
 137         else
 138                 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
 139         b43_chantab_phy_upload(dev, tabent);
 140         b43_nphy_tx_power_fix(dev);
 141
 142         return 0;
 143 }
 144
 145 static void b43_radio_init2055_pre(struct b43_wldev *dev)
 146 {
 147         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 148                      ~B43_NPHY_RFCTL_CMD_PORFORCE);
 149         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 150                     B43_NPHY_RFCTL_CMD_CHIP0PU |
 151                     B43_NPHY_RFCTL_CMD_OEPORFORCE);
 152         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 153                     B43_NPHY_RFCTL_CMD_PORFORCE);
 154 }
 155
 156 static void b43_radio_init2055_post(struct b43_wldev *dev)
 157 {
 158         struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
 159         struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo);
 160         int i;
 161         u16 val;
 162
 163         b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
 164         msleep(1);
 165         if ((sprom->revision != 4) ||
 166            !(sprom->boardflags_hi & B43_BFH_RSSIINV)) {
 167                 if ((binfo->vendor != PCI_VENDOR_ID_BROADCOM) ||
 168                     (binfo->type != 0x46D) ||
 169                     (binfo->rev < 0x41)) {
 170                         b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
 171                         b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
 172                         msleep(1);
 173                 }
 174         }
 175         b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0x3F, 0x2C);
 176         msleep(1);
 177         b43_radio_write16(dev, B2055_CAL_MISC, 0x3C);
 178         msleep(1);
 179         b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
 180         msleep(1);
 181         b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
 182         msleep(1);
 183         b43_radio_set(dev, B2055_CAL_MISC, 0x1);
 184         msleep(1);
 185         b43_radio_set(dev, B2055_CAL_MISC, 0x40);
 186         msleep(1);
 187         for (i = 0; i < 100; i++) {
 188                 val = b43_radio_read16(dev, B2055_CAL_COUT2);
 189                 if (val & 0x80)
 190                         break;
 191                 udelay(10);
 192         }
 193         msleep(1);
 194         b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
 195         msleep(1);
 196         nphy_channel_switch(dev, dev->phy.channel);
 197         b43_radio_write16(dev, B2055_C1_RX_BB_LPF, 0x9);
 198         b43_radio_write16(dev, B2055_C2_RX_BB_LPF, 0x9);
 199         b43_radio_write16(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
 200         b43_radio_write16(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
 201 }
 202
 203 /* Initialize a Broadcom 2055 N-radio */
 204 static void b43_radio_init2055(struct b43_wldev *dev)
 205 {
 206         b43_radio_init2055_pre(dev);
 207         if (b43_status(dev) < B43_STAT_INITIALIZED)
 208                 b2055_upload_inittab(dev, 0, 1);
 209         else
 210                 b2055_upload_inittab(dev, 0/*FIXME on 5ghz band*/, 0);
 211         b43_radio_init2055_post(dev);
 212 }
 213
 214 void b43_nphy_radio_turn_on(struct b43_wldev *dev)
 215 {
 216         b43_radio_init2055(dev);
 217 }
 218
 219 void b43_nphy_radio_turn_off(struct b43_wldev *dev)
 220 {
 221         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 222                      ~B43_NPHY_RFCTL_CMD_EN);
 223 }
 224
 225 /*
 226  * Upload the N-PHY tables.
 227  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
 228  */
 229 static void b43_nphy_tables_init(struct b43_wldev *dev)
 230 {
 231         if (dev->phy.rev < 3)
 232                 b43_nphy_rev0_1_2_tables_init(dev);
 233         else
 234                 b43_nphy_rev3plus_tables_init(dev);
 235 }
 236
 237 static void b43_nphy_workarounds(struct b43_wldev *dev)
 238 {
 239         struct b43_phy *phy = &dev->phy;
 240         unsigned int i;
 241
 242         b43_phy_set(dev, B43_NPHY_IQFLIP,
 243                     B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
 244         if (1 /* FIXME band is 2.4GHz */) {
 245                 b43_phy_set(dev, B43_NPHY_CLASSCTL,
 246                             B43_NPHY_CLASSCTL_CCKEN);
 247         } else {
 248                 b43_phy_mask(dev, B43_NPHY_CLASSCTL,
 249                              ~B43_NPHY_CLASSCTL_CCKEN);
 250         }
 251         b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
 252         b43_phy_write(dev, B43_NPHY_TXFRAMEDELAY, 8);
 253
 254         /* Fixup some tables */
 255         b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0xA);
 256         b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0xA);
 257         b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
 258         b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
 259         b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0);
 260         b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0);
 261         b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
 262         b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
 263         b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x800);
 264         b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x800);
 265
 266         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
 267         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
 268         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
 269         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
 270
 271         //TODO set RF sequence
 272
 273         /* Set narrowband clip threshold */
 274         b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 66);
 275         b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 66);
 276
 277         /* Set wideband clip 2 threshold */
 278         b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
 279                         ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
 280                         21 << B43_NPHY_C1_CLIPWBTHRES_CLIP2_SHIFT);
 281         b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
 282                         ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
 283                         21 << B43_NPHY_C2_CLIPWBTHRES_CLIP2_SHIFT);
 284
 285         /* Set Clip 2 detect */
 286         b43_phy_set(dev, B43_NPHY_C1_CGAINI,
 287                     B43_NPHY_C1_CGAINI_CL2DETECT);
 288         b43_phy_set(dev, B43_NPHY_C2_CGAINI,
 289                     B43_NPHY_C2_CGAINI_CL2DETECT);
 290
 291         if (0 /*FIXME*/) {
 292                 /* Set dwell lengths */
 293                 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 43);
 294                 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 43);
 295                 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 9);
 296                 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 9);
 297
 298                 /* Set gain backoff */
 299                 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
 300                                 ~B43_NPHY_C1_CGAINI_GAINBKOFF,
 301                                 1 << B43_NPHY_C1_CGAINI_GAINBKOFF_SHIFT);
 302                 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
 303                                 ~B43_NPHY_C2_CGAINI_GAINBKOFF,
 304                                 1 << B43_NPHY_C2_CGAINI_GAINBKOFF_SHIFT);
 305
 306                 /* Set HPVGA2 index */
 307                 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
 308                                 ~B43_NPHY_C1_INITGAIN_HPVGA2,
 309                                 6 << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
 310                 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
 311                                 ~B43_NPHY_C2_INITGAIN_HPVGA2,
 312                                 6 << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
 313
 314                 //FIXME verify that the specs really mean to use autoinc here.
 315                 for (i = 0; i < 3; i++)
 316                         b43_ntab_write(dev, B43_NTAB16(7, 0x106) + i, 0x673);
 317         }
 318
 319         /* Set minimum gain value */
 320         b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN,
 321                         ~B43_NPHY_C1_MINGAIN,
 322                         23 << B43_NPHY_C1_MINGAIN_SHIFT);
 323         b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN,
 324                         ~B43_NPHY_C2_MINGAIN,
 325                         23 << B43_NPHY_C2_MINGAIN_SHIFT);
 326
 327         if (phy->rev < 2) {
 328                 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
 329                              ~B43_NPHY_SCRAM_SIGCTL_SCM);
 330         }
 331
 332         /* Set phase track alpha and beta */
 333         b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
 334         b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
 335         b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
 336         b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
 337         b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
 338         b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
 339 }
 340
 341 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
 342 static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
 343 {
 344         struct b43_phy_n *nphy = dev->phy.n;
 345         enum ieee80211_band band;
 346         u16 tmp;
 347
 348         if (!enable) {
 349                 nphy->rfctrl_intc1_save = b43_phy_read(dev,
 350                                                        B43_NPHY_RFCTL_INTC1);
 351                 nphy->rfctrl_intc2_save = b43_phy_read(dev,
 352                                                        B43_NPHY_RFCTL_INTC2);
 353                 band = b43_current_band(dev->wl);
 354                 if (dev->phy.rev >= 3) {
 355                         if (band == IEEE80211_BAND_5GHZ)
 356                                 tmp = 0x600;
 357                         else
 358                                 tmp = 0x480;
 359                 } else {
 360                         if (band == IEEE80211_BAND_5GHZ)
 361                                 tmp = 0x180;
 362                         else
 363                                 tmp = 0x120;
 364                 }
 365                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
 366                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
 367         } else {
 368                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
 369                                 nphy->rfctrl_intc1_save);
 370                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
 371                                 nphy->rfctrl_intc2_save);
 372         }
 373 }
 374
 375 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
 376 static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
 377 {
 378         struct b43_phy_n *nphy = dev->phy.n;
 379         u16 tmp;
 380         enum ieee80211_band band = b43_current_band(dev->wl);
 381         bool ipa = (nphy->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
 382                         (nphy->ipa5g_on && band == IEEE80211_BAND_5GHZ);
 383
 384         if (dev->phy.rev >= 3) {
 385                 if (ipa) {
 386                         tmp = 4;
 387                         b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
 388                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
 389                 }
 390
 391                 tmp = 1;
 392                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
 393                               (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
 394         }
 395 }
 396
 397 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
 398 static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force)
 399 {
 400         u32 tmslow;
 401
 402         if (dev->phy.type != B43_PHYTYPE_N)
 403                 return;
 404
 405         tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
 406         if (force)
 407                 tmslow |= SSB_TMSLOW_FGC;
 408         else
 409                 tmslow &= ~SSB_TMSLOW_FGC;
 410         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
 411 }
 412
 413 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
 414 static void b43_nphy_reset_cca(struct b43_wldev *dev)
 415 {
 416         u16 bbcfg;
 417
 418         b43_nphy_bmac_clock_fgc(dev, 1);
 419         bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
 420         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
 421         udelay(1);
 422         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
 423         b43_nphy_bmac_clock_fgc(dev, 0);
 424         /* TODO: N PHY Force RF Seq with argument 2 */
 425 }
 426
 427 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
 428 static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
 429 {
 430         u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
 431
 432         mimocfg |= B43_NPHY_MIMOCFG_AUTO;
 433         if (preamble == 1)
 434                 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
 435         else
 436                 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
 437
 438         b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
 439 }
 440
 441 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
 442 static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
 443 {
 444         struct b43_phy_n *nphy = dev->phy.n;
 445
 446         bool override = false;
 447         u16 chain = 0x33;
 448
 449         if (nphy->txrx_chain == 0) {
 450                 chain = 0x11;
 451                 override = true;
 452         } else if (nphy->txrx_chain == 1) {
 453                 chain = 0x22;
 454                 override = true;
 455         }
 456
 457         b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
 458                         ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
 459                         chain);
 460
 461         if (override)
 462                 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
 463                                 B43_NPHY_RFSEQMODE_CAOVER);
 464         else
 465                 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
 466                                 ~B43_NPHY_RFSEQMODE_CAOVER);
 467 }
 468
 469 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
 470 static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
 471                                 u16 samps, u8 time, bool wait)
 472 {
 473         int i;
 474         u16 tmp;
 475
 476         b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
 477         b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
 478         if (wait)
 479                 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
 480         else
 481                 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
 482
 483         b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
 484
 485         for (i = 1000; i; i--) {
 486                 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
 487                 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
 488                         est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
 489                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
 490                         est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
 491                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
 492                         est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
 493                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
 494
 495                         est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
 496                                         b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
 497                         est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
 498                                         b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
 499                         est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
 500                                         b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
 501                         return;
 502                 }
 503                 udelay(10);
 504         }
 505         memset(est, 0, sizeof(*est));
 506 }
 507
 508 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
 509 static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
 510                                         struct b43_phy_n_iq_comp *pcomp)
 511 {
 512         if (write) {
 513                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
 514                 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
 515                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
 516                 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
 517         } else {
 518                 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
 519                 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
 520                 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
 521                 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
 522         }
 523 }
 524
 525 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
 526 static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
 527 {
 528         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
 529
 530         b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
 531         if (core == 0) {
 532                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
 533                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
 534         } else {
 535                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
 536                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
 537         }
 538         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
 539         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
 540         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
 541         b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
 542         b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
 543         b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
 544         b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
 545         b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
 546 }
 547
 548 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
 549 static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
 550 {
 551         u8 rxval, txval;
 552         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
 553
 554         regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
 555         if (core == 0) {
 556                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
 557                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
 558         } else {
 559                 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
 560                 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
 561         }
 562         regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
 563         regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
 564         regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
 565         regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
 566         regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
 567         regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
 568         regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
 569         regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
 570
 571         b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
 572         b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
 573
 574         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, (u16)~B43_NPHY_RFSEQCA_RXDIS,
 575                         ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
 576         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
 577                         ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
 578         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
 579                         (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
 580         b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
 581                         (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
 582
 583         if (core == 0) {
 584                 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
 585                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
 586         } else {
 587                 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
 588                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
 589         }
 590
 591         /* TODO: Call N PHY RF Ctrl Intc Override with 2, 0, 3 as arguments */
 592         /* TODO: Call N PHY RF Intc Override with 8, 0, 3, 0 as arguments */
 593         /* TODO: Call N PHY RF Seq with 0 as argument */
 594
 595         if (core == 0) {
 596                 rxval = 1;
 597                 txval = 8;
 598         } else {
 599                 rxval = 4;
 600                 txval = 2;
 601         }
 602
 603         /* TODO: Call N PHY RF Ctrl Intc Override with 1, rxval, (core + 1) */
 604         /* TODO: Call N PHY RF Ctrl Intc Override with 1, txval, (2 - core) */
 605 }
 606
 607 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
 608 static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
 609 {
 610         int i;
 611         s32 iq;
 612         u32 ii;
 613         u32 qq;
 614         int iq_nbits, qq_nbits;
 615         int arsh, brsh;
 616         u16 tmp, a, b;
 617
 618         struct nphy_iq_est est;
 619         struct b43_phy_n_iq_comp old;
 620         struct b43_phy_n_iq_comp new = { };
 621         bool error = false;
 622
 623         if (mask == 0)
 624                 return;
 625
 626         b43_nphy_rx_iq_coeffs(dev, false, &old);
 627         b43_nphy_rx_iq_coeffs(dev, true, &new);
 628         b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
 629         new = old;
 630
 631         for (i = 0; i < 2; i++) {
 632                 if (i == 0 && (mask & 1)) {
 633                         iq = est.iq0_prod;
 634                         ii = est.i0_pwr;
 635                         qq = est.q0_pwr;
 636                 } else if (i == 1 && (mask & 2)) {
 637                         iq = est.iq1_prod;
 638                         ii = est.i1_pwr;
 639                         qq = est.q1_pwr;
 640                 } else {
 641                         B43_WARN_ON(1);
 642                         continue;
 643                 }
 644
 645                 if (ii + qq < 2) {
 646                         error = true;
 647                         break;
 648                 }
 649
 650                 iq_nbits = fls(abs(iq));
 651                 qq_nbits = fls(qq);
 652
 653                 arsh = iq_nbits - 20;
 654                 if (arsh >= 0) {
 655                         a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
 656                         tmp = ii >> arsh;
 657                 } else {
 658                         a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
 659                         tmp = ii << -arsh;
 660                 }
 661                 if (tmp == 0) {
 662                         error = true;
 663                         break;
 664                 }
 665                 a /= tmp;
 666
 667                 brsh = qq_nbits - 11;
 668                 if (brsh >= 0) {
 669                         b = (qq << (31 - qq_nbits));
 670                         tmp = ii >> brsh;
 671                 } else {
 672                         b = (qq << (31 - qq_nbits));
 673                         tmp = ii << -brsh;
 674                 }
 675                 if (tmp == 0) {
 676                         error = true;
 677                         break;
 678                 }
 679                 b = int_sqrt(b / tmp - a * a) - (1 << 10);
 680
 681                 if (i == 0 && (mask & 0x1)) {
 682                         if (dev->phy.rev >= 3) {
 683                                 new.a0 = a & 0x3FF;
 684                                 new.b0 = b & 0x3FF;
 685                         } else {
 686                                 new.a0 = b & 0x3FF;
 687                                 new.b0 = a & 0x3FF;
 688                         }
 689                 } else if (i == 1 && (mask & 0x2)) {
 690                         if (dev->phy.rev >= 3) {
 691                                 new.a1 = a & 0x3FF;
 692                                 new.b1 = b & 0x3FF;
 693                         } else {
 694                                 new.a1 = b & 0x3FF;
 695                                 new.b1 = a & 0x3FF;
 696                         }
 697                 }
 698         }
 699
 700         if (error)
 701                 new = old;
 702
 703         b43_nphy_rx_iq_coeffs(dev, true, &new);
 704 }
 705
 706 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
 707 static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
 708 {
 709         u16 array[4];
 710         int i;
 711
 712         b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C50);
 713         for (i = 0; i < 4; i++)
 714                 array[i] = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
 715
 716         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
 717         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
 718         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
 719         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
 720 }
 721
 722 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 723 static void b43_nphy_write_clip_detection(struct b43_wldev *dev, u16 *clip_st)
 724 {
 725         b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
 726         b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
 727 }
 728
 729 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 730 static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
 731 {
 732         clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
 733         clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
 734 }
 735
 736 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
 737 static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
 738 {
 739         u16 tmp;
 740
 741         if (dev->dev->id.revision == 16)
 742                 b43_mac_suspend(dev);
 743
 744         tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
 745         tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
 746                 B43_NPHY_CLASSCTL_WAITEDEN);
 747         tmp &= ~mask;
 748         tmp |= (val & mask);
 749         b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
 750
 751         if (dev->dev->id.revision == 16)
 752                 b43_mac_enable(dev);
 753
 754         return tmp;
 755 }
 756
 757 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
 758 static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
 759 {
 760         struct b43_phy *phy = &dev->phy;
 761         struct b43_phy_n *nphy = phy->n;
 762
 763         if (enable) {
 764                 u16 clip[] = { 0xFFFF, 0xFFFF };
 765                 if (nphy->deaf_count++ == 0) {
 766                         nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
 767                         b43_nphy_classifier(dev, 0x7, 0);
 768                         b43_nphy_read_clip_detection(dev, nphy->clip_state);
 769                         b43_nphy_write_clip_detection(dev, clip);
 770                 }
 771                 b43_nphy_reset_cca(dev);
 772         } else {
 773                 if (--nphy->deaf_count == 0) {
 774                         b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
 775                         b43_nphy_write_clip_detection(dev, nphy->clip_state);
 776                 }
 777         }
 778 }
 779
 780 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
 781 static void b43_nphy_stop_playback(struct b43_wldev *dev)
 782 {
 783         struct b43_phy_n *nphy = dev->phy.n;
 784         u16 tmp;
 785
 786         if (nphy->hang_avoid)
 787                 b43_nphy_stay_in_carrier_search(dev, 1);
 788
 789         tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
 790         if (tmp & 0x1)
 791                 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
 792         else if (tmp & 0x2)
 793                 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, (u16)~0x8000);
 794
 795         b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
 796
 797         if (nphy->bb_mult_save & 0x80000000) {
 798                 tmp = nphy->bb_mult_save & 0xFFFF;
 799                 /* TODO: Write an N PHY Table with ID 15, length 1, offset 87,
 800                         width 16 and data from tmp */
 801                 nphy->bb_mult_save = 0;
 802         }
 803
 804         if (nphy->hang_avoid)
 805                 b43_nphy_stay_in_carrier_search(dev, 0);
 806 }
 807
 808 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
 809 static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
 810 {
 811         struct b43_phy_n *nphy = dev->phy.n;
 812         int i, j;
 813         u32 tmp;
 814         u32 cur_real, cur_imag, real_part, imag_part;
 815
 816         u16 buffer[7];
 817
 818         if (nphy->hang_avoid)
 819                 b43_nphy_stay_in_carrier_search(dev, true);
 820
 821         /* TODO: Read an N PHY Table with ID 15, length 7, offset 80,
 822                 width 16, and data pointer buffer */
 823
 824         for (i = 0; i < 2; i++) {
 825                 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
 826                         (buffer[i * 2 + 1] & 0x3FF);
 827                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
 828                                 (((i + 26) << 10) | 320));
 829                 for (j = 0; j < 128; j++) {
 830                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
 831                                         ((tmp >> 16) & 0xFFFF));
 832                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
 833                                         (tmp & 0xFFFF));
 834                 }
 835         }
 836
 837         for (i = 0; i < 2; i++) {
 838                 tmp = buffer[5 + i];
 839                 real_part = (tmp >> 8) & 0xFF;
 840                 imag_part = (tmp & 0xFF);
 841                 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
 842                                 (((i + 26) << 10) | 448));
 843
 844                 if (dev->phy.rev >= 3) {
 845                         cur_real = real_part;
 846                         cur_imag = imag_part;
 847                         tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
 848                 }
 849
 850                 for (j = 0; j < 128; j++) {
 851                         if (dev->phy.rev < 3) {
 852                                 cur_real = (real_part * loscale[j] + 128) >> 8;
 853                                 cur_imag = (imag_part * loscale[j] + 128) >> 8;
 854                                 tmp = ((cur_real & 0xFF) << 8) |
 855                                         (cur_imag & 0xFF);
 856                         }
 857                         b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
 858                                         ((tmp >> 16) & 0xFFFF));
 859                         b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
 860                                         (tmp & 0xFFFF));
 861                 }
 862         }
 863
 864         if (dev->phy.rev >= 3) {
 865                 b43_shm_write16(dev, B43_SHM_SHARED,
 866                                 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
 867                 b43_shm_write16(dev, B43_SHM_SHARED,
 868                                 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
 869         }
 870
 871         if (nphy->hang_avoid)
 872                 b43_nphy_stay_in_carrier_search(dev, false);
 873 }
 874
 875 enum b43_nphy_rf_sequence {
 876         B43_RFSEQ_RX2TX,
 877         B43_RFSEQ_TX2RX,
 878         B43_RFSEQ_RESET2RX,
 879         B43_RFSEQ_UPDATE_GAINH,
 880         B43_RFSEQ_UPDATE_GAINL,
 881         B43_RFSEQ_UPDATE_GAINU,
 882 };
 883
 884 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
 885                                        enum b43_nphy_rf_sequence seq)
 886 {
 887         static const u16 trigger[] = {
 888                 [B43_RFSEQ_RX2TX]               = B43_NPHY_RFSEQTR_RX2TX,
 889                 [B43_RFSEQ_TX2RX]               = B43_NPHY_RFSEQTR_TX2RX,
 890                 [B43_RFSEQ_RESET2RX]            = B43_NPHY_RFSEQTR_RST2RX,
 891                 [B43_RFSEQ_UPDATE_GAINH]        = B43_NPHY_RFSEQTR_UPGH,
 892                 [B43_RFSEQ_UPDATE_GAINL]        = B43_NPHY_RFSEQTR_UPGL,
 893                 [B43_RFSEQ_UPDATE_GAINU]        = B43_NPHY_RFSEQTR_UPGU,
 894         };
 895         int i;
 896
 897         B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
 898
 899         b43_phy_set(dev, B43_NPHY_RFSEQMODE,
 900                     B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
 901         b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
 902         for (i = 0; i < 200; i++) {
 903                 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
 904                         goto ok;
 905                 msleep(1);
 906         }
 907         b43err(dev->wl, "RF sequence status timeout\n");
 908 ok:
 909         b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
 910                      ~(B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER));
 911 }
 912
 913 static void b43_nphy_bphy_init(struct b43_wldev *dev)
 914 {
 915         unsigned int i;
 916         u16 val;
 917
 918         val = 0x1E1F;
 919         for (i = 0; i < 14; i++) {
 920                 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
 921                 val -= 0x202;
 922         }
 923         val = 0x3E3F;
 924         for (i = 0; i < 16; i++) {
 925                 b43_phy_write(dev, B43_PHY_N_BMODE(0x97 + i), val);
 926                 val -= 0x202;
 927         }
 928         b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
 929 }
 930
 931 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
 932 static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
 933                                        s8 offset, u8 core, u8 rail, u8 type)
 934 {
 935         u16 tmp;
 936         bool core1or5 = (core == 1) || (core == 5);
 937         bool core2or5 = (core == 2) || (core == 5);
 938
 939         offset = clamp_val(offset, -32, 31);
 940         tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
 941
 942         if (core1or5 && (rail == 0) && (type == 2))
 943                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
 944         if (core1or5 && (rail == 1) && (type == 2))
 945                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
 946         if (core2or5 && (rail == 0) && (type == 2))
 947                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
 948         if (core2or5 && (rail == 1) && (type == 2))
 949                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
 950         if (core1or5 && (rail == 0) && (type == 0))
 951                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
 952         if (core1or5 && (rail == 1) && (type == 0))
 953                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
 954         if (core2or5 && (rail == 0) && (type == 0))
 955                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
 956         if (core2or5 && (rail == 1) && (type == 0))
 957                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
 958         if (core1or5 && (rail == 0) && (type == 1))
 959                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
 960         if (core1or5 && (rail == 1) && (type == 1))
 961                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
 962         if (core2or5 && (rail == 0) && (type == 1))
 963                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
 964         if (core2or5 && (rail == 1) && (type == 1))
 965                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
 966         if (core1or5 && (rail == 0) && (type == 6))
 967                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
 968         if (core1or5 && (rail == 1) && (type == 6))
 969                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
 970         if (core2or5 && (rail == 0) && (type == 6))
 971                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
 972         if (core2or5 && (rail == 1) && (type == 6))
 973                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
 974         if (core1or5 && (rail == 0) && (type == 3))
 975                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
 976         if (core1or5 && (rail == 1) && (type == 3))
 977                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
 978         if (core2or5 && (rail == 0) && (type == 3))
 979                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
 980         if (core2or5 && (rail == 1) && (type == 3))
 981                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
 982         if (core1or5 && (type == 4))
 983                 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
 984         if (core2or5 && (type == 4))
 985                 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
 986         if (core1or5 && (type == 5))
 987                 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
 988         if (core2or5 && (type == 5))
 989                 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
 990 }
 991
 992 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
 993 static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
 994 {
 995         u16 val;
 996
 997         if (dev->phy.rev >= 3) {
 998                 /* TODO */
 999         } else {
1000                 if (type < 3)
1001                         val = 0;
1002                 else if (type == 6)
1003                         val = 1;
1004                 else if (type == 3)
1005                         val = 2;
1006                 else
1007                         val = 3;
1008
1009                 val = (val << 12) | (val << 14);
1010                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1011                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
1012
1013                 if (type < 3) {
1014                         b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
1015                                         (type + 1) << 4);
1016                         b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
1017                                         (type + 1) << 4);
1018                 }
1019
1020                 /* TODO use some definitions */
1021                 if (code == 0) {
1022                         b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF, 0);
1023                         if (type < 3) {
1024                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1025                                                 0xFEC7, 0);
1026                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1027                                                 0xEFDC, 0);
1028                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1029                                                 0xFFFE, 0);
1030                                 udelay(20);
1031                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1032                                                 0xFFFE, 0);
1033                         }
1034                 } else {
1035                         b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF,
1036                                         0x3000);
1037                         if (type < 3) {
1038                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1039                                                 0xFEC7, 0x0180);
1040                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1041                                                 0xEFDC, (code << 1 | 0x1021));
1042                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1043                                                 0xFFFE, 0x0001);
1044                                 udelay(20);
1045                                 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1046                                                 0xFFFE, 0);
1047                         }
1048                 }
1049         }
1050 }
1051
1052 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
1053 static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
1054 {
1055         int i;
1056         for (i = 0; i < 2; i++) {
1057                 if (type == 2) {
1058                         if (i == 0) {
1059                                 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1060                                                   0xFC, buf[0]);
1061                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1062                                                   0xFC, buf[1]);
1063                         } else {
1064                                 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
1065                                                   0xFC, buf[2 * i]);
1066                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1067                                                   0xFC, buf[2 * i + 1]);
1068                         }
1069                 } else {
1070                         if (i == 0)
1071                                 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1072                                                   0xF3, buf[0] << 2);
1073                         else
1074                                 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1075                                                   0xF3, buf[2 * i + 1] << 2);
1076                 }
1077         }
1078 }
1079
1080 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
1081 static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
1082                                 u8 nsamp)
1083 {
1084         int i;
1085         int out;
1086         u16 save_regs_phy[9];
1087         u16 s[2];
1088
1089         if (dev->phy.rev >= 3) {
1090                 save_regs_phy[0] = b43_phy_read(dev,
1091                                                 B43_NPHY_RFCTL_LUT_TRSW_UP1);
1092                 save_regs_phy[1] = b43_phy_read(dev,
1093                                                 B43_NPHY_RFCTL_LUT_TRSW_UP2);
1094                 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1095                 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1096                 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1097                 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1098                 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
1099                 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
1100         }
1101
1102         b43_nphy_rssi_select(dev, 5, type);
1103
1104         if (dev->phy.rev < 2) {
1105                 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
1106                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
1107         }
1108
1109         for (i = 0; i < 4; i++)
1110                 buf[i] = 0;
1111
1112         for (i = 0; i < nsamp; i++) {
1113                 if (dev->phy.rev < 2) {
1114                         s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
1115                         s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
1116                 } else {
1117                         s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
1118                         s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
1119                 }
1120
1121                 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
1122                 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
1123                 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
1124                 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
1125         }
1126         out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
1127                 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
1128
1129         if (dev->phy.rev < 2)
1130                 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
1131
1132         if (dev->phy.rev >= 3) {
1133                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
1134                                 save_regs_phy[0]);
1135                 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1136                                 save_regs_phy[1]);
1137                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
1138                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
1139                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
1140                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
1141                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
1142                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
1143         }
1144
1145         return out;
1146 }
1147
1148 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
1149 static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
1150 {
1151         int i, j;
1152         u8 state[4];
1153         u8 code, val;
1154         u16 class, override;
1155         u8 regs_save_radio[2];
1156         u16 regs_save_phy[2];
1157         s8 offset[4];
1158
1159         u16 clip_state[2];
1160         u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1161         s32 results_min[4] = { };
1162         u8 vcm_final[4] = { };
1163         s32 results[4][4] = { };
1164         s32 miniq[4][2] = { };
1165
1166         if (type == 2) {
1167                 code = 0;
1168                 val = 6;
1169         } else if (type < 2) {
1170                 code = 25;
1171                 val = 4;
1172         } else {
1173                 B43_WARN_ON(1);
1174                 return;
1175         }
1176
1177         class = b43_nphy_classifier(dev, 0, 0);
1178         b43_nphy_classifier(dev, 7, 4);
1179         b43_nphy_read_clip_detection(dev, clip_state);
1180         b43_nphy_write_clip_detection(dev, clip_off);
1181
1182         if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1183                 override = 0x140;
1184         else
1185                 override = 0x110;
1186
1187         regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1188         regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
1189         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
1190         b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
1191
1192         regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1193         regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
1194         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
1195         b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
1196
1197         state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
1198         state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
1199         b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
1200         b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
1201         state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
1202         state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
1203
1204         b43_nphy_rssi_select(dev, 5, type);
1205         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
1206         b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
1207
1208         for (i = 0; i < 4; i++) {
1209                 u8 tmp[4];
1210                 for (j = 0; j < 4; j++)
1211                         tmp[j] = i;
1212                 if (type != 1)
1213                         b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
1214                 b43_nphy_poll_rssi(dev, type, results[i], 8);
1215                 if (type < 2)
1216                         for (j = 0; j < 2; j++)
1217                                 miniq[i][j] = min(results[i][2 * j],
1218                                                 results[i][2 * j + 1]);
1219         }
1220
1221         for (i = 0; i < 4; i++) {
1222                 s32 mind = 40;
1223                 u8 minvcm = 0;
1224                 s32 minpoll = 249;
1225                 s32 curr;
1226                 for (j = 0; j < 4; j++) {
1227                         if (type == 2)
1228                                 curr = abs(results[j][i]);
1229                         else
1230                                 curr = abs(miniq[j][i / 2] - code * 8);
1231
1232                         if (curr < mind) {
1233                                 mind = curr;
1234                                 minvcm = j;
1235                         }
1236
1237                         if (results[j][i] < minpoll)
1238                                 minpoll = results[j][i];
1239                 }
1240                 results_min[i] = minpoll;
1241                 vcm_final[i] = minvcm;
1242         }
1243
1244         if (type != 1)
1245                 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
1246
1247         for (i = 0; i < 4; i++) {
1248                 offset[i] = (code * 8) - results[vcm_final[i]][i];
1249
1250                 if (offset[i] < 0)
1251                         offset[i] = -((abs(offset[i]) + 4) / 8);
1252                 else
1253                         offset[i] = (offset[i] + 4) / 8;
1254
1255                 if (results_min[i] == 248)
1256                         offset[i] = code - 32;
1257
1258                 if (i % 2 == 0)
1259                         b43_nphy_scale_offset_rssi(dev, 0, offset[i], 1, 0,
1260                                                         type);
1261                 else
1262                         b43_nphy_scale_offset_rssi(dev, 0, offset[i], 2, 1,
1263                                                         type);
1264         }
1265
1266         b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
1267         b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[1]);
1268
1269         switch (state[2]) {
1270         case 1:
1271                 b43_nphy_rssi_select(dev, 1, 2);
1272                 break;
1273         case 4:
1274                 b43_nphy_rssi_select(dev, 1, 0);
1275                 break;
1276         case 2:
1277                 b43_nphy_rssi_select(dev, 1, 1);
1278                 break;
1279         default:
1280                 b43_nphy_rssi_select(dev, 1, 1);
1281                 break;
1282         }
1283
1284         switch (state[3]) {
1285         case 1:
1286                 b43_nphy_rssi_select(dev, 2, 2);
1287                 break;
1288         case 4:
1289                 b43_nphy_rssi_select(dev, 2, 0);
1290                 break;
1291         default:
1292                 b43_nphy_rssi_select(dev, 2, 1);
1293                 break;
1294         }
1295
1296         b43_nphy_rssi_select(dev, 0, type);
1297
1298         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
1299         b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
1300         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
1301         b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
1302
1303         b43_nphy_classifier(dev, 7, class);
1304         b43_nphy_write_clip_detection(dev, clip_state);
1305 }
1306
1307 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
1308 static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
1309 {
1310         /* TODO */
1311 }
1312
1313 /*
1314  * RSSI Calibration
1315  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
1316  */
1317 static void b43_nphy_rssi_cal(struct b43_wldev *dev)
1318 {
1319         if (dev->phy.rev >= 3) {
1320                 b43_nphy_rev3_rssi_cal(dev);
1321         } else {
1322                 b43_nphy_rev2_rssi_cal(dev, 2);
1323                 b43_nphy_rev2_rssi_cal(dev, 0);
1324                 b43_nphy_rev2_rssi_cal(dev, 1);
1325         }
1326 }
1327
1328 /*
1329  * Restore RSSI Calibration
1330  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
1331  */
1332 static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
1333 {
1334         struct b43_phy_n *nphy = dev->phy.n;
1335
1336         u16 *rssical_radio_regs = NULL;
1337         u16 *rssical_phy_regs = NULL;
1338
1339         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1340                 if (!nphy->rssical_chanspec_2G)
1341                         return;
1342                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
1343                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
1344         } else {
1345                 if (!nphy->rssical_chanspec_5G)
1346                         return;
1347                 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
1348                 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
1349         }
1350
1351         /* TODO use some definitions */
1352         b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
1353         b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
1354
1355         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
1356         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
1357         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
1358         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
1359
1360         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
1361         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
1362         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
1363         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
1364
1365         b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
1366         b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
1367         b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
1368         b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
1369 }
1370
1371 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
1372 static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
1373 {
1374         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1375                 if (dev->phy.rev >= 6) {
1376                         /* TODO If the chip is 47162
1377                                 return txpwrctrl_tx_gain_ipa_rev5 */
1378                         return txpwrctrl_tx_gain_ipa_rev6;
1379                 } else if (dev->phy.rev >= 5) {
1380                         return txpwrctrl_tx_gain_ipa_rev5;
1381                 } else {
1382                         return txpwrctrl_tx_gain_ipa;
1383                 }
1384         } else {
1385                 return txpwrctrl_tx_gain_ipa_5g;
1386         }
1387 }
1388
1389 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
1390 static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
1391 {
1392         struct b43_phy_n *nphy = dev->phy.n;
1393         u16 *save = nphy->tx_rx_cal_radio_saveregs;
1394
1395         if (dev->phy.rev >= 3) {
1396                 /* TODO */
1397         } else {
1398                 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
1399                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
1400
1401                 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
1402                 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
1403
1404                 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
1405                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
1406
1407                 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
1408                 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
1409
1410                 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
1411                 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
1412
1413                 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
1414                     B43_NPHY_BANDCTL_5GHZ)) {
1415                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
1416                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
1417                 } else {
1418                         b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
1419                         b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
1420                 }
1421
1422                 if (dev->phy.rev < 2) {
1423                         b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
1424                         b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
1425                 } else {
1426                         b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
1427                         b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
1428                 }
1429         }
1430 }
1431
1432 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
1433 static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
1434                                         struct nphy_txgains target,
1435                                         struct nphy_iqcal_params *params)
1436 {
1437         int i, j, indx;
1438         u16 gain;
1439
1440         if (dev->phy.rev >= 3) {
1441                 params->txgm = target.txgm[core];
1442                 params->pga = target.pga[core];
1443                 params->pad = target.pad[core];
1444                 params->ipa = target.ipa[core];
1445                 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
1446                                         (params->pad << 4) | (params->ipa);
1447                 for (j = 0; j < 5; j++)
1448                         params->ncorr[j] = 0x79;
1449         } else {
1450                 gain = (target.pad[core]) | (target.pga[core] << 4) |
1451                         (target.txgm[core] << 8);
1452
1453                 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
1454                         1 : 0;
1455                 for (i = 0; i < 9; i++)
1456                         if (tbl_iqcal_gainparams[indx][i][0] == gain)
1457                                 break;
1458                 i = min(i, 8);
1459
1460                 params->txgm = tbl_iqcal_gainparams[indx][i][1];
1461                 params->pga = tbl_iqcal_gainparams[indx][i][2];
1462                 params->pad = tbl_iqcal_gainparams[indx][i][3];
1463                 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
1464                                         (params->pad << 2);
1465                 for (j = 0; j < 4; j++)
1466                         params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
1467         }
1468 }
1469
1470 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
1471 static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
1472 {
1473         struct b43_phy_n *nphy = dev->phy.n;
1474         int i;
1475         u16 scale, entry;
1476
1477         u16 tmp = nphy->txcal_bbmult;
1478         if (core == 0)
1479                 tmp >>= 8;
1480         tmp &= 0xff;
1481
1482         for (i = 0; i < 18; i++) {
1483                 scale = (ladder_lo[i].percent * tmp) / 100;
1484                 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
1485                 /* TODO: Write an N PHY Table with ID 15, length 1,
1486                         offset i, width 16, and data entry */
1487
1488                 scale = (ladder_iq[i].percent * tmp) / 100;
1489                 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
1490                 /* TODO: Write an N PHY Table with ID 15, length 1,
1491                         offset i + 32, width 16, and data entry */
1492         }
1493 }
1494
1495 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
1496 static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
1497 {
1498         struct b43_phy_n *nphy = dev->phy.n;
1499
1500         u16 curr_gain[2];
1501         struct nphy_txgains target;
1502         const u32 *table = NULL;
1503
1504         if (nphy->txpwrctrl == 0) {
1505                 int i;
1506
1507                 if (nphy->hang_avoid)
1508                         b43_nphy_stay_in_carrier_search(dev, true);
1509                 /* TODO: Read an N PHY Table with ID 7, length 2,
1510                         offset 0x110, width 16, and curr_gain */
1511                 if (nphy->hang_avoid)
1512                         b43_nphy_stay_in_carrier_search(dev, false);
1513
1514                 for (i = 0; i < 2; ++i) {
1515                         if (dev->phy.rev >= 3) {
1516                                 target.ipa[i] = curr_gain[i] & 0x000F;
1517                                 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
1518                                 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
1519                                 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
1520                         } else {
1521                                 target.ipa[i] = curr_gain[i] & 0x0003;
1522                                 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
1523                                 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
1524                                 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
1525                         }
1526                 }
1527         } else {
1528                 int i;
1529                 u16 index[2];
1530                 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
1531                         B43_NPHY_TXPCTL_STAT_BIDX) >>
1532                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
1533                 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
1534                         B43_NPHY_TXPCTL_STAT_BIDX) >>
1535                         B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
1536
1537                 for (i = 0; i < 2; ++i) {
1538                         if (dev->phy.rev >= 3) {
1539                                 enum ieee80211_band band =
1540                                         b43_current_band(dev->wl);
1541
1542                                 if ((nphy->ipa2g_on &&
1543                                      band == IEEE80211_BAND_2GHZ) ||
1544                                     (nphy->ipa5g_on &&
1545                                      band == IEEE80211_BAND_5GHZ)) {
1546                                         table = b43_nphy_get_ipa_gain_table(dev);
1547                                 } else {
1548                                         if (band == IEEE80211_BAND_5GHZ) {
1549                                                 if (dev->phy.rev == 3)
1550                                                         table = b43_ntab_tx_gain_rev3_5ghz;
1551                                                 else if (dev->phy.rev == 4)
1552                                                         table = b43_ntab_tx_gain_rev4_5ghz;
1553                                                 else
1554                                                         table = b43_ntab_tx_gain_rev5plus_5ghz;
1555                                         } else {
1556                                                 table = b43_ntab_tx_gain_rev3plus_2ghz;
1557                                         }
1558                                 }
1559
1560                                 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
1561                                 target.pad[i] = (table[index[i]] >> 20) & 0xF;
1562                                 target.pga[i] = (table[index[i]] >> 24) & 0xF;
1563                                 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
1564                         } else {
1565                                 table = b43_ntab_tx_gain_rev0_1_2;
1566
1567                                 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
1568                                 target.pad[i] = (table[index[i]] >> 18) & 0x3;
1569                                 target.pga[i] = (table[index[i]] >> 20) & 0x7;
1570                                 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
1571                         }
1572                 }
1573         }
1574
1575         return target;
1576 }
1577
1578 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
1579 static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
1580 {
1581         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
1582
1583         if (dev->phy.rev >= 3) {
1584                 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
1585                 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
1586                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
1587                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
1588                 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
1589                 /* TODO: Write an N PHY Table with ID 8, length 1, offset 3,
1590                         width 16, and data from regs[5] */
1591                 /* TODO: Write an N PHY Table with ID 8, length 1, offset 19,
1592                         width 16, and data from regs[6] */
1593                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
1594                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
1595                 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
1596                 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
1597                 b43_nphy_reset_cca(dev);
1598         } else {
1599                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
1600                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
1601                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
1602                 /* TODO: Write an N PHY Table with ID 8, length 1, offset 2,
1603                         width 16, and data from regs[3] */
1604                 /* TODO: Write an N PHY Table with ID 8, length 1, offset 18,
1605                         width 16, and data from regs[4] */
1606                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
1607                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
1608         }
1609 }
1610
1611 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
1612 static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
1613 {
1614         u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
1615         u16 tmp;
1616
1617         regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1618         regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1619         if (dev->phy.rev >= 3) {
1620                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
1621                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
1622
1623                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1624                 regs[2] = tmp;
1625                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
1626
1627                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1628                 regs[3] = tmp;
1629                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
1630
1631                 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
1632                 b43_phy_mask(dev, B43_NPHY_BBCFG, ~B43_NPHY_BBCFG_RSTRX);
1633
1634                 /* TODO: Read an N PHY Table with ID 8, length 1, offset 3,
1635                         width 16, and data pointing to tmp */
1636                 regs[5] = tmp;
1637
1638                 /* TODO: Write an N PHY Table with ID 8, length 1, offset 3,
1639                         width 16, and data 0 */
1640                 /* TODO: Read an N PHY Table with ID 8, length 1, offset 19,
1641                         width 16, and data pointing to tmp */
1642                 regs[6] = tmp;
1643
1644                 /* TODO: Write an N PHY Table with ID 8, length 1, offset 19,
1645                         width 16, and data 0 */
1646                 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1647                 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1648
1649                 /* TODO: Call N PHY RF Ctrl Intc Override with 2, 1, 3 */
1650                 /* TODO: Call N PHY RF Ctrl Intc Override with 1, 2, 1 */
1651                 /* TODO: Call N PHY RF Ctrl Intc Override with 1, 8, 2 */
1652
1653                 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
1654                 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
1655                 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
1656                 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
1657         } else {
1658                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
1659                 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
1660                 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1661                 regs[2] = tmp;
1662                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
1663                 /* TODO: Read an N PHY Table with ID 8, length 1, offset 2,
1664                         width 16, and data pointing to tmp */
1665                 regs[3] = tmp;
1666                 tmp |= 0x2000;
1667                 /* TODO: Write an N PHY Table with ID 8, length 1, offset 2,
1668                         width 16, and data pointer tmp */
1669                 /* TODO: Read an N PHY Table with ID 8, length 1, offset 18,
1670                         width 16, and data pointer tmp */
1671                 regs[4] = tmp;
1672                 tmp |= 0x2000;
1673                 /* TODO: Write an N PHY Table with ID 8, length 1, offset 18,
1674                         width 16, and data pointer tmp */
1675                 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1676                 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1677                 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1678                         tmp = 0x0180;
1679                 else
1680                         tmp = 0x0120;
1681                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
1682                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
1683         }
1684 }
1685
1686 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
1687 static void b43_nphy_restore_cal(struct b43_wldev *dev)
1688 {
1689         struct b43_phy_n *nphy = dev->phy.n;
1690
1691         u16 coef[4];
1692         u16 *loft = NULL;
1693         u16 *table = NULL;
1694
1695         int i;
1696         u16 *txcal_radio_regs = NULL;
1697         struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
1698
1699         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1700                 if (nphy->iqcal_chanspec_2G == 0)
1701                         return;
1702                 table = nphy->cal_cache.txcal_coeffs_2G;
1703                 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
1704         } else {
1705                 if (nphy->iqcal_chanspec_5G == 0)
1706                         return;
1707                 table = nphy->cal_cache.txcal_coeffs_5G;
1708                 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
1709         }
1710
1711         /* TODO: Write an N PHY table with ID 15, length 4, offset 80,
1712                 width 16, and data from table */
1713
1714         for (i = 0; i < 4; i++) {
1715                 if (dev->phy.rev >= 3)
1716                         table[i] = coef[i];
1717                 else
1718                         coef[i] = 0;
1719         }
1720
1721         /* TODO: Write an N PHY table with ID 15, length 4, offset 88,
1722                 width 16, and data from coef */
1723         /* TODO: Write an N PHY table with ID 15, length 2, offset 85,
1724                 width 16 and data from loft */
1725         /* TODO: Write an N PHY table with ID 15, length 2, offset 93,
1726                 width 16 and data from loft */
1727
1728         if (dev->phy.rev < 2)
1729                 b43_nphy_tx_iq_workaround(dev);
1730
1731         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1732                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
1733                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
1734         } else {
1735                 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
1736                 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
1737         }
1738
1739         /* TODO use some definitions */
1740         if (dev->phy.rev >= 3) {
1741                 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
1742                 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
1743                 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
1744                 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
1745                 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
1746                 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
1747                 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
1748                 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
1749         } else {
1750                 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
1751                 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
1752                 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
1753                 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
1754         }
1755         b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
1756 }
1757
1758 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
1759 static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
1760                                 struct nphy_txgains target,
1761                                 bool full, bool mphase)
1762 {
1763         struct b43_phy_n *nphy = dev->phy.n;
1764         int i;
1765         int error = 0;
1766         int freq;
1767         bool avoid = false;
1768         u8 length;
1769         u16 tmp, core, type, count, max, numb, last, cmd;
1770         const u16 *table;
1771         bool phy6or5x;
1772
1773         u16 buffer[11];
1774         u16 diq_start = 0;
1775         u16 save[2];
1776         u16 gain[2];
1777         struct nphy_iqcal_params params[2];
1778         bool updated[2] = { };
1779
1780         b43_nphy_stay_in_carrier_search(dev, true);
1781
1782         if (dev->phy.rev >= 4) {
1783                 avoid = nphy->hang_avoid;
1784                 nphy->hang_avoid = 0;
1785         }
1786
1787         /* TODO: Read an N PHY Table with ID 7, length 2, offset 0x110,
1788                 width 16, and data pointer save */
1789
1790         for (i = 0; i < 2; i++) {
1791                 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
1792                 gain[i] = params[i].cal_gain;
1793         }
1794         /* TODO: Write an N PHY Table with ID 7, length 2, offset 0x110,
1795                 width 16, and data pointer gain */
1796
1797         b43_nphy_tx_cal_radio_setup(dev);
1798         b43_nphy_tx_cal_phy_setup(dev);
1799
1800         phy6or5x = dev->phy.rev >= 6 ||
1801                 (dev->phy.rev == 5 && nphy->ipa2g_on &&
1802                 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
1803         if (phy6or5x) {
1804                 /* TODO */
1805         }
1806
1807         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
1808
1809         if (1 /* FIXME: the band width is 20 MHz */)
1810                 freq = 2500;
1811         else
1812                 freq = 5000;
1813
1814         if (nphy->mphase_cal_phase_id > 2)
1815                 ;/* TODO: Call N PHY Run Samples with (band width * 8),
1816                         0xFFFF, 0, 1, 0 as arguments */
1817         else
1818                 ;/* TODO: Call N PHY TX Tone with freq, 250, 1, 0 as arguments
1819                         and save result as error */
1820
1821         if (error == 0) {
1822                 if (nphy->mphase_cal_phase_id > 2) {
1823                         table = nphy->mphase_txcal_bestcoeffs;
1824                         length = 11;
1825                         if (dev->phy.rev < 3)
1826                                 length -= 2;
1827                 } else {
1828                         if (!full && nphy->txiqlocal_coeffsvalid) {
1829                                 table = nphy->txiqlocal_bestc;
1830                                 length = 11;
1831                                 if (dev->phy.rev < 3)
1832                                         length -= 2;
1833                         } else {
1834                                 full = true;
1835                                 if (dev->phy.rev >= 3) {
1836                                         table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
1837                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
1838                                 } else {
1839                                         table = tbl_tx_iqlo_cal_startcoefs;
1840                                         length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
1841                                 }
1842                         }
1843                 }
1844
1845                 /* TODO: Write an N PHY Table with ID 15, length from above,
1846                         offset 64, width 16, and the data pointer from above */
1847
1848                 if (full) {
1849                         if (dev->phy.rev >= 3)
1850                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
1851                         else
1852                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
1853                 } else {
1854                         if (dev->phy.rev >= 3)
1855                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
1856                         else
1857                                 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
1858                 }
1859
1860                 if (mphase) {
1861                         count = nphy->mphase_txcal_cmdidx;
1862                         numb = min(max,
1863                                 (u16)(count + nphy->mphase_txcal_numcmds));
1864                 } else {
1865                         count = 0;
1866                         numb = max;
1867                 }
1868
1869                 for (; count < numb; count++) {
1870                         if (full) {
1871                                 if (dev->phy.rev >= 3)
1872                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
1873                                 else
1874                                         cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
1875                         } else {
1876                                 if (dev->phy.rev >= 3)
1877                                         cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
1878                                 else
1879                                         cmd = tbl_tx_iqlo_cal_cmds_recal[count];
1880                         }
1881
1882                         core = (cmd & 0x3000) >> 12;
1883                         type = (cmd & 0x0F00) >> 8;
1884
1885                         if (phy6or5x && updated[core] == 0) {
1886                                 b43_nphy_update_tx_cal_ladder(dev, core);
1887                                 updated[core] = 1;
1888                         }
1889
1890                         tmp = (params[core].ncorr[type] << 8) | 0x66;
1891                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
1892
1893                         if (type == 1 || type == 3 || type == 4) {
1894                                 /* TODO: Read an N PHY Table with ID 15,
1895                                         length 1, offset 69 + core,
1896                                         width 16, and data pointer buffer */
1897                                 diq_start = buffer[0];
1898                                 buffer[0] = 0;
1899                                 /* TODO: Write an N PHY Table with ID 15,
1900                                         length 1, offset 69 + core, width 16,
1901                                         and data of 0 */
1902                         }
1903
1904                         b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
1905                         for (i = 0; i < 2000; i++) {
1906                                 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
1907                                 if (tmp & 0xC000)
1908                                         break;
1909                                 udelay(10);
1910                         }
1911
1912                         /* TODO: Read an N PHY Table with ID 15,
1913                                 length table_length, offset 96, width 16,
1914                                 and data pointer buffer */
1915                         /* TODO: Write an N PHY Table with ID 15,
1916                                 length table_length, offset 64, width 16,
1917                                 and data pointer buffer */
1918
1919                         if (type == 1 || type == 3 || type == 4)
1920                                 buffer[0] = diq_start;
1921                 }
1922
1923                 if (mphase)
1924                         nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
1925
1926                 last = (dev->phy.rev < 3) ? 6 : 7;
1927
1928                 if (!mphase || nphy->mphase_cal_phase_id == last) {
1929                         /* TODO: Write an N PHY Table with ID 15, length 4,
1930                                 offset 96, width 16, and data pointer buffer */
1931                         /* TODO: Read an N PHY Table with ID 15, length 4,
1932                                 offset 80, width 16, and data pointer buffer */
1933                         if (dev->phy.rev < 3) {
1934                                 buffer[0] = 0;
1935                                 buffer[1] = 0;
1936                                 buffer[2] = 0;
1937                                 buffer[3] = 0;
1938                         }
1939                         /* TODO: Write an N PHY Table with ID 15, length 4,
1940                                 offset 88, width 16, and data pointer buffer */
1941                         /* TODO: Read an N PHY Table with ID 15, length 2,
1942                                 offset 101, width 16, and data pointer buffer*/
1943                         /* TODO: Write an N PHY Table with ID 15, length 2,
1944                                 offset 85, width 16, and data pointer buffer */
1945                         /* TODO: Write an N PHY Table with ID 15, length 2,
1946                                 offset 93, width 16, and data pointer buffer */
1947                         length = 11;
1948                         if (dev->phy.rev < 3)
1949                                 length -= 2;
1950                         /* TODO: Read an N PHY Table with ID 15, length length,
1951                                 offset 96, width 16, and data pointer
1952                                 nphy->txiqlocal_bestc */
1953                         nphy->txiqlocal_coeffsvalid = true;
1954                         /* TODO: Set nphy->txiqlocal_chanspec to
1955                                 the current channel */
1956                 } else {
1957                         length = 11;
1958                         if (dev->phy.rev < 3)
1959                                 length -= 2;
1960                         /* TODO: Read an N PHY Table with ID 5, length length,
1961                                 offset 96, width 16, and data pointer
1962                                 nphy->mphase_txcal_bestcoeffs */
1963                 }
1964
1965                 b43_nphy_stop_playback(dev);
1966                 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
1967         }
1968
1969         b43_nphy_tx_cal_phy_cleanup(dev);
1970         /* TODO: Write an N PHY Table with ID 7, length 2, offset 0x110,
1971                 width 16, and data from save */
1972
1973         if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
1974                 b43_nphy_tx_iq_workaround(dev);
1975
1976         if (dev->phy.rev >= 4)
1977                 nphy->hang_avoid = avoid;
1978
1979         b43_nphy_stay_in_carrier_search(dev, false);
1980
1981         return error;
1982 }
1983
1984 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
1985 static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
1986                         struct nphy_txgains target, u8 type, bool debug)
1987 {
1988         struct b43_phy_n *nphy = dev->phy.n;
1989         int i, j, index;
1990         u8 rfctl[2];
1991         u8 afectl_core;
1992         u16 tmp[6];
1993         u16 cur_hpf1, cur_hpf2, cur_lna;
1994         u32 real, imag;
1995         enum ieee80211_band band;
1996
1997         u8 use;
1998         u16 cur_hpf;
1999         u16 lna[3] = { 3, 3, 1 };
2000         u16 hpf1[3] = { 7, 2, 0 };
2001         u16 hpf2[3] = { 2, 0, 0 };
2002         u32 power[3];
2003         u16 gain_save[2];
2004         u16 cal_gain[2];
2005         struct nphy_iqcal_params cal_params[2];
2006         struct nphy_iq_est est;
2007         int ret = 0;
2008         bool playtone = true;
2009         int desired = 13;
2010
2011         b43_nphy_stay_in_carrier_search(dev, 1);
2012
2013         if (dev->phy.rev < 2)
2014                 ;/* TODO: Call N PHY Reapply TX Cal Coeffs */
2015         /* TODO: Read an N PHY Table with ID 7, length 2, offset 0x110,
2016                 width 16, and data gain_save */
2017         for (i = 0; i < 2; i++) {
2018                 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
2019                 cal_gain[i] = cal_params[i].cal_gain;
2020         }
2021         /* TODO: Write an N PHY Table with ID 7, length 2, offset 0x110,
2022                 width 16, and data from cal_gain */
2023
2024         for (i = 0; i < 2; i++) {
2025                 if (i == 0) {
2026                         rfctl[0] = B43_NPHY_RFCTL_INTC1;
2027                         rfctl[1] = B43_NPHY_RFCTL_INTC2;
2028                         afectl_core = B43_NPHY_AFECTL_C1;
2029                 } else {
2030                         rfctl[0] = B43_NPHY_RFCTL_INTC2;
2031                         rfctl[1] = B43_NPHY_RFCTL_INTC1;
2032                         afectl_core = B43_NPHY_AFECTL_C2;
2033                 }
2034
2035                 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
2036                 tmp[2] = b43_phy_read(dev, afectl_core);
2037                 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2038                 tmp[4] = b43_phy_read(dev, rfctl[0]);
2039                 tmp[5] = b43_phy_read(dev, rfctl[1]);
2040
2041                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
2042                                 (u16)~B43_NPHY_RFSEQCA_RXDIS,
2043                                 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
2044                 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
2045                                 (1 - i));
2046                 b43_phy_set(dev, afectl_core, 0x0006);
2047                 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
2048
2049                 band = b43_current_band(dev->wl);
2050
2051                 if (nphy->rxcalparams & 0xFF000000) {
2052                         if (band == IEEE80211_BAND_5GHZ)
2053                                 b43_phy_write(dev, rfctl[0], 0x140);
2054                         else
2055                                 b43_phy_write(dev, rfctl[0], 0x110);
2056                 } else {
2057                         if (band == IEEE80211_BAND_5GHZ)
2058                                 b43_phy_write(dev, rfctl[0], 0x180);
2059                         else
2060                                 b43_phy_write(dev, rfctl[0], 0x120);
2061                 }
2062
2063                 if (band == IEEE80211_BAND_5GHZ)
2064                         b43_phy_write(dev, rfctl[1], 0x148);
2065                 else
2066                         b43_phy_write(dev, rfctl[1], 0x114);
2067
2068                 if (nphy->rxcalparams & 0x10000) {
2069                         b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
2070                                         (i + 1));
2071                         b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
2072                                         (2 - i));
2073                 }
2074
2075                 for (j = 0; i < 4; j++) {
2076                         if (j < 3) {
2077                                 cur_lna = lna[j];
2078                                 cur_hpf1 = hpf1[j];
2079                                 cur_hpf2 = hpf2[j];
2080                         } else {
2081                                 if (power[1] > 10000) {
2082                                         use = 1;
2083                                         cur_hpf = cur_hpf1;
2084                                         index = 2;
2085                                 } else {
2086                                         if (power[0] > 10000) {
2087                                                 use = 1;
2088                                                 cur_hpf = cur_hpf1;
2089                                                 index = 1;
2090                                         } else {
2091                                                 index = 0;
2092                                                 use = 2;
2093                                                 cur_hpf = cur_hpf2;
2094                                         }
2095                                 }
2096                                 cur_lna = lna[index];
2097                                 cur_hpf1 = hpf1[index];
2098                                 cur_hpf2 = hpf2[index];
2099                                 cur_hpf += desired - hweight32(power[index]);
2100                                 cur_hpf = clamp_val(cur_hpf, 0, 10);
2101                                 if (use == 1)
2102                                         cur_hpf1 = cur_hpf;
2103                                 else
2104                                         cur_hpf2 = cur_hpf;
2105                         }
2106
2107                         tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
2108                                         (cur_lna << 2));
2109                         /* TODO:Call N PHY RF Ctrl Override with 0x400, tmp[0],
2110                                 3, 0 as arguments */
2111                         /* TODO: Call N PHY Force RF Seq with 2 as argument */
2112                         b43_nphy_stop_playback(dev);
2113
2114                         if (playtone) {
2115                                 /* TODO: Call N PHY TX Tone with 4000,
2116                                         (nphy_rxcalparams & 0xffff), 0, 0
2117                                         as arguments and save result as ret */
2118                                 playtone = false;
2119                         } else {
2120                                 /* TODO: Call N PHY Run Samples with 160,
2121                                         0xFFFF, 0, 0, 0 as arguments */
2122                         }
2123
2124                         if (ret == 0) {
2125                                 if (j < 3) {
2126                                         b43_nphy_rx_iq_est(dev, &est, 1024, 32,
2127                                                                         false);
2128                                         if (i == 0) {
2129                                                 real = est.i0_pwr;
2130                                                 imag = est.q0_pwr;
2131                                         } else {
2132                                                 real = est.i1_pwr;
2133                                                 imag = est.q1_pwr;
2134                                         }
2135                                         power[i] = ((real + imag) / 1024) + 1;
2136                                 } else {
2137                                         b43_nphy_calc_rx_iq_comp(dev, 1 << i);
2138                                 }
2139                                 b43_nphy_stop_playback(dev);
2140                         }
2141
2142                         if (ret != 0)
2143                                 break;
2144                 }
2145
2146                 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
2147                 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
2148                 b43_phy_write(dev, rfctl[1], tmp[5]);
2149                 b43_phy_write(dev, rfctl[0], tmp[4]);
2150                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
2151                 b43_phy_write(dev, afectl_core, tmp[2]);
2152                 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
2153
2154                 if (ret != 0)
2155                         break;
2156         }
2157
2158         /* TODO: Call N PHY RF Ctrl Override with 0x400, 0, 3, 1 as arguments*/
2159         /* TODO: Call N PHY Force RF Seq with 2 as argument */
2160         /* TODO: Write an N PHY Table with ID 7, length 2, offset 0x110,
2161                 width 16, and data from gain_save */
2162
2163         b43_nphy_stay_in_carrier_search(dev, 0);
2164
2165         return ret;
2166 }
2167
2168 static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
2169                         struct nphy_txgains target, u8 type, bool debug)
2170 {
2171         return -1;
2172 }
2173
2174 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
2175 static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
2176                         struct nphy_txgains target, u8 type, bool debug)
2177 {
2178         if (dev->phy.rev >= 3)
2179                 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
2180         else
2181                 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
2182 }
2183
2184 /*
2185  * Init N-PHY
2186  * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
2187  */
2188 int b43_phy_initn(struct b43_wldev *dev)
2189 {
2190         struct ssb_bus *bus = dev->dev->bus;
2191         struct b43_phy *phy = &dev->phy;
2192         struct b43_phy_n *nphy = phy->n;
2193         u8 tx_pwr_state;
2194         struct nphy_txgains target;
2195         u16 tmp;
2196         enum ieee80211_band tmp2;
2197         bool do_rssi_cal;
2198
2199         u16 clip[2];
2200         bool do_cal = false;
2201
2202         if ((dev->phy.rev >= 3) &&
2203            (bus->sprom.boardflags_lo & B43_BFL_EXTLNA) &&
2204            (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
2205                 chipco_set32(&dev->dev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40);
2206         }
2207         nphy->deaf_count = 0;
2208         b43_nphy_tables_init(dev);
2209         nphy->crsminpwr_adjusted = false;
2210         nphy->noisevars_adjusted = false;
2211
2212         /* Clear all overrides */
2213         if (dev->phy.rev >= 3) {
2214                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
2215                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
2216                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
2217                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
2218         } else {
2219                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
2220         }
2221         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
2222         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
2223         if (dev->phy.rev < 6) {
2224                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
2225                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
2226         }
2227         b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
2228                      ~(B43_NPHY_RFSEQMODE_CAOVER |
2229                        B43_NPHY_RFSEQMODE_TROVER));
2230         if (dev->phy.rev >= 3)
2231                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
2232         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
2233
2234         if (dev->phy.rev <= 2) {
2235                 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
2236                 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
2237                                 ~B43_NPHY_BPHY_CTL3_SCALE,
2238                                 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
2239         }
2240         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
2241         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
2242
2243         if (bus->sprom.boardflags2_lo & 0x100 ||
2244             (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
2245              bus->boardinfo.type == 0x8B))
2246                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
2247         else
2248                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
2249         b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
2250         b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
2251         b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
2252
2253         b43_nphy_update_mimo_config(dev, nphy->preamble_override);
2254         b43_nphy_update_txrx_chain(dev);
2255
2256         if (phy->rev < 2) {
2257                 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
2258                 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
2259         }
2260
2261         tmp2 = b43_current_band(dev->wl);
2262         if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) ||
2263             (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) {
2264                 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
2265                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
2266                                 nphy->papd_epsilon_offset[0] << 7);
2267                 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
2268                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
2269                                 nphy->papd_epsilon_offset[1] << 7);
2270                 /* TODO N PHY IPA Set TX Dig Filters */
2271         } else if (phy->rev >= 5) {
2272                 /* TODO N PHY Ext PA Set TX Dig Filters */
2273         }
2274
2275         b43_nphy_workarounds(dev);
2276
2277         /* Reset CCA, in init code it differs a little from standard way */
2278         b43_nphy_bmac_clock_fgc(dev, 1);
2279         tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
2280         b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
2281         b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
2282         b43_nphy_bmac_clock_fgc(dev, 0);
2283
2284         /* TODO N PHY MAC PHY Clock Set with argument 1 */
2285
2286         b43_nphy_pa_override(dev, false);
2287         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
2288         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
2289         b43_nphy_pa_override(dev, true);
2290
2291         b43_nphy_classifier(dev, 0, 0);
2292         b43_nphy_read_clip_detection(dev, clip);
2293         tx_pwr_state = nphy->txpwrctrl;
2294         /* TODO N PHY TX power control with argument 0
2295                 (turning off power control) */
2296         /* TODO Fix the TX Power Settings */
2297         /* TODO N PHY TX Power Control Idle TSSI */
2298         /* TODO N PHY TX Power Control Setup */
2299
2300         if (phy->rev >= 3) {
2301                 /* TODO */
2302         } else {
2303                 /* TODO Write an N PHY table with ID 26, length 128, offset 192, width 32, and the data from Rev 2 TX Power Control Table */
2304                 /* TODO Write an N PHY table with ID 27, length 128, offset 192, width 32, and the data from Rev 2 TX Power Control Table */
2305         }
2306
2307         if (nphy->phyrxchain != 3)
2308                 ;/* TODO N PHY RX Core Set State with phyrxchain as argument */
2309         if (nphy->mphase_cal_phase_id > 0)
2310                 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
2311
2312         do_rssi_cal = false;
2313         if (phy->rev >= 3) {
2314                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2315                         do_rssi_cal = (nphy->rssical_chanspec_2G == 0);
2316                 else
2317                         do_rssi_cal = (nphy->rssical_chanspec_5G == 0);
2318
2319                 if (do_rssi_cal)
2320                         b43_nphy_rssi_cal(dev);
2321                 else
2322                         b43_nphy_restore_rssi_cal(dev);
2323         } else {
2324                 b43_nphy_rssi_cal(dev);
2325         }
2326
2327         if (!((nphy->measure_hold & 0x6) != 0)) {
2328                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2329                         do_cal = (nphy->iqcal_chanspec_2G == 0);
2330                 else
2331                         do_cal = (nphy->iqcal_chanspec_5G == 0);
2332
2333                 if (nphy->mute)
2334                         do_cal = false;
2335
2336                 if (do_cal) {
2337                         target = b43_nphy_get_tx_gains(dev);
2338
2339                         if (nphy->antsel_type == 2)
2340                                 ;/*TODO NPHY Superswitch Init with argument 1*/
2341                         if (nphy->perical != 2) {
2342                                 b43_nphy_rssi_cal(dev);
2343                                 if (phy->rev >= 3) {
2344                                         nphy->cal_orig_pwr_idx[0] =
2345                                             nphy->txpwrindex[0].index_internal;
2346                                         nphy->cal_orig_pwr_idx[1] =
2347                                             nphy->txpwrindex[1].index_internal;
2348                                         /* TODO N PHY Pre Calibrate TX Gain */
2349                                         target = b43_nphy_get_tx_gains(dev);
2350                                 }
2351                         }
2352                 }
2353         }
2354
2355         if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false)) {
2356                 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
2357                         ;/* Call N PHY Save Cal */
2358                 else if (nphy->mphase_cal_phase_id == 0)
2359                         ;/* N PHY Periodic Calibration with argument 3 */
2360         } else {
2361                 b43_nphy_restore_cal(dev);
2362         }
2363
2364         b43_nphy_tx_pwr_ctrl_coef_setup(dev);
2365         /* TODO N PHY TX Power Control Enable with argument tx_pwr_state */
2366         b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
2367         b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
2368         if (phy->rev >= 3 && phy->rev <= 6)
2369                 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
2370         b43_nphy_tx_lp_fbw(dev);
2371         /* TODO N PHY Spur Workaround */
2372
2373         b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n");
2374         return 0;
2375 }
2376
2377 static int b43_nphy_op_allocate(struct b43_wldev *dev)
2378 {
2379         struct b43_phy_n *nphy;
2380
2381         nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
2382         if (!nphy)
2383                 return -ENOMEM;
2384         dev->phy.n = nphy;
2385
2386         return 0;
2387 }
2388
2389 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
2390 {
2391         struct b43_phy *phy = &dev->phy;
2392         struct b43_phy_n *nphy = phy->n;
2393
2394         memset(nphy, 0, sizeof(*nphy));
2395
2396         //TODO init struct b43_phy_n
2397 }
2398
2399 static void b43_nphy_op_free(struct b43_wldev *dev)
2400 {
2401         struct b43_phy *phy = &dev->phy;
2402         struct b43_phy_n *nphy = phy->n;
2403
2404         kfree(nphy);
2405         phy->n = NULL;
2406 }
2407
2408 static int b43_nphy_op_init(struct b43_wldev *dev)
2409 {
2410         return b43_phy_initn(dev);
2411 }
2412
2413 static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
2414 {
2415 #if B43_DEBUG
2416         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
2417                 /* OFDM registers are onnly available on A/G-PHYs */
2418                 b43err(dev->wl, "Invalid OFDM PHY access at "
2419                        "0x%04X on N-PHY\n", offset);
2420                 dump_stack();
2421         }
2422         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
2423                 /* Ext-G registers are only available on G-PHYs */
2424                 b43err(dev->wl, "Invalid EXT-G PHY access at "
2425                        "0x%04X on N-PHY\n", offset);
2426                 dump_stack();
2427         }
2428 #endif /* B43_DEBUG */
2429 }
2430
2431 static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
2432 {
2433         check_phyreg(dev, reg);
2434         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
2435         return b43_read16(dev, B43_MMIO_PHY_DATA);
2436 }
2437
2438 static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
2439 {
2440         check_phyreg(dev, reg);
2441         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
2442         b43_write16(dev, B43_MMIO_PHY_DATA, value);
2443 }
2444
2445 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
2446 {
2447         /* Register 1 is a 32-bit register. */
2448         B43_WARN_ON(reg == 1);
2449         /* N-PHY needs 0x100 for read access */
2450         reg |= 0x100;
2451
2452         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
2453         return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
2454 }
2455
2456 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
2457 {
2458         /* Register 1 is a 32-bit register. */
2459         B43_WARN_ON(reg == 1);
2460
2461         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
2462         b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
2463 }
2464
2465 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
2466                                         bool blocked)
2467 {//TODO
2468 }
2469
2470 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
2471 {
2472         b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
2473                       on ? 0 : 0x7FFF);
2474 }
2475
2476 static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
2477                                       unsigned int new_channel)
2478 {
2479         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2480                 if ((new_channel < 1) || (new_channel > 14))
2481                         return -EINVAL;
2482         } else {
2483                 if (new_channel > 200)
2484                         return -EINVAL;
2485         }
2486
2487         return nphy_channel_switch(dev, new_channel);
2488 }
2489
2490 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
2491 {
2492         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
2493                 return 1;
2494         return 36;
2495 }
2496
2497 const struct b43_phy_operations b43_phyops_n = {
2498         .allocate               = b43_nphy_op_allocate,
2499         .free                   = b43_nphy_op_free,
2500         .prepare_structs        = b43_nphy_op_prepare_structs,
2501         .init                   = b43_nphy_op_init,
2502         .phy_read               = b43_nphy_op_read,
2503         .phy_write              = b43_nphy_op_write,
2504         .radio_read             = b43_nphy_op_radio_read,
2505         .radio_write            = b43_nphy_op_radio_write,
2506         .software_rfkill        = b43_nphy_op_software_rfkill,
2507         .switch_analog          = b43_nphy_op_switch_analog,
2508         .switch_channel         = b43_nphy_op_switch_channel,
2509         .get_default_chan       = b43_nphy_op_get_default_chan,
2510         .recalc_txpower         = b43_nphy_op_recalc_txpower,
2511         .adjust_txpower         = b43_nphy_op_adjust_txpower,
2512 };