SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/b43/phy_n.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4   IEEE 802.11n PHY support
   5
   6   Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>
   7
   8   This program is free software; you can redistribute it and/or modify
   9   it under the terms of the GNU General Public License as published by
  10   the Free Software Foundation; either version 2 of the License, or
  11   (at your option) any later version.
  12
  13   This program is distributed in the hope that it will be useful,
  14   but WITHOUT ANY WARRANTY; without even the implied warranty of
  15   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16   GNU General Public License for more details.
  17
  18   You should have received a copy of the GNU General Public License
  19   along with this program; see the file COPYING.  If not, write to
  20   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  21   Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #include <linux/delay.h>
  26 #include <linux/types.h>
  27
  28 #include "b43.h"
  29 #include "phy_n.h"
  30 #include "tables_nphy.h"
  31 #include "main.h"
  32
  33 struct nphy_txgains {
  34         u16 txgm[2];
  35         u16 pga[2];
  36         u16 pad[2];
  37         u16 ipa[2];
  38 };
  39
  40 struct nphy_iqcal_params {
  41         u16 txgm;
  42         u16 pga;
  43         u16 pad;
  44         u16 ipa;
  45         u16 cal_gain;
  46         u16 ncorr[5];
  47 };
  48
  49 struct nphy_iq_est {
  50         s32 iq0_prod;
  51         u32 i0_pwr;
  52         u32 q0_pwr;
  53         s32 iq1_prod;
  54         u32 i1_pwr;
  55         u32 q1_pwr;
  56 };
  57
  58 void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
  59 {//TODO
  60 }
  61
  62 static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
  63 {//TODO
  64 }
  65
  66 static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
  67                                                         bool ignore_tssi)
  68 {//TODO
  69         return B43_TXPWR_RES_DONE;
  70 }
  71
  72 static void b43_chantab_radio_upload(struct b43_wldev *dev,
  73                                      const struct b43_nphy_channeltab_entry *e)
  74 {
  75         b43_radio_write16(dev, B2055_PLL_REF, e->radio_pll_ref);
  76         b43_radio_write16(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
  77         b43_radio_write16(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
  78         b43_radio_write16(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
  79         b43_radio_write16(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
  80         b43_radio_write16(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
  81         b43_radio_write16(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
  82         b43_radio_write16(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
  83         b43_radio_write16(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
  84         b43_radio_write16(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
  85         b43_radio_write16(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
  86         b43_radio_write16(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
  87         b43_radio_write16(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
  88         b43_radio_write16(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
  89         b43_radio_write16(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
  90         b43_radio_write16(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
  91         b43_radio_write16(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
  92         b43_radio_write16(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
  93         b43_radio_write16(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
  94         b43_radio_write16(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
  95         b43_radio_write16(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
  96         b43_radio_write16(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
  97 }
  98
  99 static void b43_chantab_phy_upload(struct b43_wldev *dev,
 100                                    const struct b43_nphy_channeltab_entry *e)
 101 {
 102         b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
 103         b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
 104         b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
 105         b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
 106         b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
 107         b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
 108 }
 109
 110 static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
 111 {
 112         //TODO
 113 }
 114
 115 /* Tune the hardware to a new channel. */
 116 static int nphy_channel_switch(struct b43_wldev *dev, unsigned int channel)
 117 {
 118         const struct b43_nphy_channeltab_entry *tabent;
 119
 120         tabent = b43_nphy_get_chantabent(dev, channel);
 121         if (!tabent)
 122                 return -ESRCH;
 123
 124         //FIXME enable/disable band select upper20 in RXCTL
 125         if (0 /*FIXME 5Ghz*/)
 126                 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x20);
 127         else
 128                 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, 0x50);
 129         b43_chantab_radio_upload(dev, tabent);
 130         udelay(50);
 131         b43_radio_write16(dev, B2055_VCO_CAL10, 5);
 132         b43_radio_write16(dev, B2055_VCO_CAL10, 45);
 133         b43_radio_write16(dev, B2055_VCO_CAL10, 65);
 134         udelay(300);
 135         if (0 /*FIXME 5Ghz*/)
 136                 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
 137         else
 138                 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
 139         b43_chantab_phy_upload(dev, tabent);
 140         b43_nphy_tx_power_fix(dev);
 141
 142         return 0;
 143 }
 144
 145 static void b43_radio_init2055_pre(struct b43_wldev *dev)
 146 {
 147         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 148                      ~B43_NPHY_RFCTL_CMD_PORFORCE);
 149         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 150                     B43_NPHY_RFCTL_CMD_CHIP0PU |
 151                     B43_NPHY_RFCTL_CMD_OEPORFORCE);
 152         b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
 153                     B43_NPHY_RFCTL_CMD_PORFORCE);
 154 }
 155
 156 static void b43_radio_init2055_post(struct b43_wldev *dev)
 157 {
 158         struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
 159         struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo);
 160         int i;
 161         u16 val;
 162
 163         b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
 164         msleep(1);
 165         if ((sprom->revision != 4) ||
 166            !(sprom->boardflags_hi & B43_BFH_RSSIINV)) {
 167                 if ((binfo->vendor != PCI_VENDOR_ID_BROADCOM) ||
 168                     (binfo->type != 0x46D) ||
 169                     (binfo->rev < 0x41)) {
 170                         b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
 171                         b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
 172                         msleep(1);
 173                 }
 174         }
 175         b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0x3F, 0x2C);
 176         msleep(1);
 177         b43_radio_write16(dev, B2055_CAL_MISC, 0x3C);
 178         msleep(1);
 179         b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
 180         msleep(1);
 181         b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
 182         msleep(1);
 183         b43_radio_set(dev, B2055_CAL_MISC, 0x1);
 184         msleep(1);
 185         b43_radio_set(dev, B2055_CAL_MISC, 0x40);
 186         msleep(1);
 187         for (i = 0; i < 100; i++) {
 188                 val = b43_radio_read16(dev, B2055_CAL_COUT2);
 189                 if (val & 0x80)
 190                         break;
 191                 udelay(10);
 192         }
 193         msleep(1);
 194         b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
 195         msleep(1);
 196         nphy_channel_switch(dev, dev->phy.channel);
 197         b43_radio_write16(dev, B2055_C1_RX_BB_LPF, 0x9);
 198         b43_radio_write16(dev, B2055_C2_RX_BB_LPF, 0x9);
 199         b43_radio_write16(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
 200         b43_radio_write16(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
 201 }
 202
 203 /* Initialize a Broadcom 2055 N-radio */
 204 static void b43_radio_init2055(struct b43_wldev *dev)
 205 {
 206         b43_radio_init2055_pre(dev);
 207         if (b43_status(dev) < B43_STAT_INITIALIZED)
 208                 b2055_upload_inittab(dev, 0, 1);
 209         else
 210                 b2055_upload_inittab(dev, 0/*FIXME on 5ghz band*/, 0);
 211         b43_radio_init2055_post(dev);
 212 }
 213
 214 void b43_nphy_radio_turn_on(struct b43_wldev *dev)
 215 {
 216         b43_radio_init2055(dev);
 217 }
 218
 219 void b43_nphy_radio_turn_off(struct b43_wldev *dev)
 220 {
 221         b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
 222                      ~B43_NPHY_RFCTL_CMD_EN);
 223 }
 224
 225 #define ntab_upload(dev, offset, data) do { \
 226                 unsigned int i;                                         \
 227                 for (i = 0; i < (offset##_SIZE); i++)                   \
 228                         b43_ntab_write(dev, (offset) + i, (data)[i]);   \
 229         } while (0)
 230
 231 /*
 232  * Upload the N-PHY tables.
 233  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
 234  */
 235 static void b43_nphy_tables_init(struct b43_wldev *dev)
 236 {
 237         if (dev->phy.rev < 3)
 238                 b43_nphy_rev0_1_2_tables_init(dev);
 239         else
 240                 b43_nphy_rev3plus_tables_init(dev);
 241 }
 242
 243 static void b43_nphy_workarounds(struct b43_wldev *dev)
 244 {
 245         struct b43_phy *phy = &dev->phy;
 246         unsigned int i;
 247
 248         b43_phy_set(dev, B43_NPHY_IQFLIP,
 249                     B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
 250         if (1 /* FIXME band is 2.4GHz */) {
 251                 b43_phy_set(dev, B43_NPHY_CLASSCTL,
 252                             B43_NPHY_CLASSCTL_CCKEN);
 253         } else {
 254                 b43_phy_mask(dev, B43_NPHY_CLASSCTL,
 255                              ~B43_NPHY_CLASSCTL_CCKEN);
 256         }
 257         b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
 258         b43_phy_write(dev, B43_NPHY_TXFRAMEDELAY, 8);
 259
 260         /* Fixup some tables */
 261         b43_ntab_write(dev, B43_NTAB16(8, 0x00), 0xA);
 262         b43_ntab_write(dev, B43_NTAB16(8, 0x10), 0xA);
 263         b43_ntab_write(dev, B43_NTAB16(8, 0x02), 0xCDAA);
 264         b43_ntab_write(dev, B43_NTAB16(8, 0x12), 0xCDAA);
 265         b43_ntab_write(dev, B43_NTAB16(8, 0x08), 0);
 266         b43_ntab_write(dev, B43_NTAB16(8, 0x18), 0);
 267         b43_ntab_write(dev, B43_NTAB16(8, 0x07), 0x7AAB);
 268         b43_ntab_write(dev, B43_NTAB16(8, 0x17), 0x7AAB);
 269         b43_ntab_write(dev, B43_NTAB16(8, 0x06), 0x800);
 270         b43_ntab_write(dev, B43_NTAB16(8, 0x16), 0x800);
 271
 272         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
 273         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
 274         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
 275         b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
 276
 277         //TODO set RF sequence
 278
 279         /* Set narrowband clip threshold */
 280         b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 66);
 281         b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 66);
 282
 283         /* Set wideband clip 2 threshold */
 284         b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
 285                         ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
 286                         21 << B43_NPHY_C1_CLIPWBTHRES_CLIP2_SHIFT);
 287         b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
 288                         ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
 289                         21 << B43_NPHY_C2_CLIPWBTHRES_CLIP2_SHIFT);
 290
 291         /* Set Clip 2 detect */
 292         b43_phy_set(dev, B43_NPHY_C1_CGAINI,
 293                     B43_NPHY_C1_CGAINI_CL2DETECT);
 294         b43_phy_set(dev, B43_NPHY_C2_CGAINI,
 295                     B43_NPHY_C2_CGAINI_CL2DETECT);
 296
 297         if (0 /*FIXME*/) {
 298                 /* Set dwell lengths */
 299                 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 43);
 300                 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 43);
 301                 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 9);
 302                 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 9);
 303
 304                 /* Set gain backoff */
 305                 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
 306                                 ~B43_NPHY_C1_CGAINI_GAINBKOFF,
 307                                 1 << B43_NPHY_C1_CGAINI_GAINBKOFF_SHIFT);
 308                 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
 309                                 ~B43_NPHY_C2_CGAINI_GAINBKOFF,
 310                                 1 << B43_NPHY_C2_CGAINI_GAINBKOFF_SHIFT);
 311
 312                 /* Set HPVGA2 index */
 313                 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
 314                                 ~B43_NPHY_C1_INITGAIN_HPVGA2,
 315                                 6 << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
 316                 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
 317                                 ~B43_NPHY_C2_INITGAIN_HPVGA2,
 318                                 6 << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
 319
 320                 //FIXME verify that the specs really mean to use autoinc here.
 321                 for (i = 0; i < 3; i++)
 322                         b43_ntab_write(dev, B43_NTAB16(7, 0x106) + i, 0x673);
 323         }
 324
 325         /* Set minimum gain value */
 326         b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN,
 327                         ~B43_NPHY_C1_MINGAIN,
 328                         23 << B43_NPHY_C1_MINGAIN_SHIFT);
 329         b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN,
 330                         ~B43_NPHY_C2_MINGAIN,
 331                         23 << B43_NPHY_C2_MINGAIN_SHIFT);
 332
 333         if (phy->rev < 2) {
 334                 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
 335                              ~B43_NPHY_SCRAM_SIGCTL_SCM);
 336         }
 337
 338         /* Set phase track alpha and beta */
 339         b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
 340         b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
 341         b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
 342         b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
 343         b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
 344         b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
 345 }
 346
 347 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
 348 static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force)
 349 {
 350         u32 tmslow;
 351
 352         if (dev->phy.type != B43_PHYTYPE_N)
 353                 return;
 354
 355         tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
 356         if (force)
 357                 tmslow |= SSB_TMSLOW_FGC;
 358         else
 359                 tmslow &= ~SSB_TMSLOW_FGC;
 360         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
 361 }
 362
 363 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
 364 static void b43_nphy_reset_cca(struct b43_wldev *dev)
 365 {
 366         u16 bbcfg;
 367
 368         b43_nphy_bmac_clock_fgc(dev, 1);
 369         bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
 370         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
 371         udelay(1);
 372         b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
 373         b43_nphy_bmac_clock_fgc(dev, 0);
 374         /* TODO: N PHY Force RF Seq with argument 2 */
 375 }
 376
 377 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 378 static void b43_nphy_write_clip_detection(struct b43_wldev *dev, u16 *clip_st)
 379 {
 380         b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
 381         b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
 382 }
 383
 384 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
 385 static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
 386 {
 387         clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
 388         clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
 389 }
 390
 391 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
 392 static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
 393 {
 394         u16 tmp;
 395
 396         if (dev->dev->id.revision == 16)
 397                 b43_mac_suspend(dev);
 398
 399         tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
 400         tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
 401                 B43_NPHY_CLASSCTL_WAITEDEN);
 402         tmp &= ~mask;
 403         tmp |= (val & mask);
 404         b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
 405
 406         if (dev->dev->id.revision == 16)
 407                 b43_mac_enable(dev);
 408
 409         return tmp;
 410 }
 411
 412 enum b43_nphy_rf_sequence {
 413         B43_RFSEQ_RX2TX,
 414         B43_RFSEQ_TX2RX,
 415         B43_RFSEQ_RESET2RX,
 416         B43_RFSEQ_UPDATE_GAINH,
 417         B43_RFSEQ_UPDATE_GAINL,
 418         B43_RFSEQ_UPDATE_GAINU,
 419 };
 420
 421 static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
 422                                        enum b43_nphy_rf_sequence seq)
 423 {
 424         static const u16 trigger[] = {
 425                 [B43_RFSEQ_RX2TX]               = B43_NPHY_RFSEQTR_RX2TX,
 426                 [B43_RFSEQ_TX2RX]               = B43_NPHY_RFSEQTR_TX2RX,
 427                 [B43_RFSEQ_RESET2RX]            = B43_NPHY_RFSEQTR_RST2RX,
 428                 [B43_RFSEQ_UPDATE_GAINH]        = B43_NPHY_RFSEQTR_UPGH,
 429                 [B43_RFSEQ_UPDATE_GAINL]        = B43_NPHY_RFSEQTR_UPGL,
 430                 [B43_RFSEQ_UPDATE_GAINU]        = B43_NPHY_RFSEQTR_UPGU,
 431         };
 432         int i;
 433
 434         B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
 435
 436         b43_phy_set(dev, B43_NPHY_RFSEQMODE,
 437                     B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
 438         b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
 439         for (i = 0; i < 200; i++) {
 440                 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
 441                         goto ok;
 442                 msleep(1);
 443         }
 444         b43err(dev->wl, "RF sequence status timeout\n");
 445 ok:
 446         b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
 447                      ~(B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER));
 448 }
 449
 450 static void b43_nphy_bphy_init(struct b43_wldev *dev)
 451 {
 452         unsigned int i;
 453         u16 val;
 454
 455         val = 0x1E1F;
 456         for (i = 0; i < 14; i++) {
 457                 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
 458                 val -= 0x202;
 459         }
 460         val = 0x3E3F;
 461         for (i = 0; i < 16; i++) {
 462                 b43_phy_write(dev, B43_PHY_N_BMODE(0x97 + i), val);
 463                 val -= 0x202;
 464         }
 465         b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
 466 }
 467
 468 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
 469 static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
 470 {
 471         /* TODO */
 472 }
 473
 474 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
 475 static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
 476 {
 477         /* TODO */
 478 }
 479
 480 /*
 481  * RSSI Calibration
 482  * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
 483  */
 484 static void b43_nphy_rssi_cal(struct b43_wldev *dev)
 485 {
 486         if (dev->phy.rev >= 3) {
 487                 b43_nphy_rev3_rssi_cal(dev);
 488         } else {
 489                 b43_nphy_rev2_rssi_cal(dev, 2);
 490                 b43_nphy_rev2_rssi_cal(dev, 0);
 491                 b43_nphy_rev2_rssi_cal(dev, 1);
 492         }
 493 }
 494
 495 /*
 496  * Init N-PHY
 497  * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
 498  */
 499 int b43_phy_initn(struct b43_wldev *dev)
 500 {
 501         struct ssb_bus *bus = dev->dev->bus;
 502         struct b43_phy *phy = &dev->phy;
 503         struct b43_phy_n *nphy = phy->n;
 504         u8 tx_pwr_state;
 505         struct nphy_txgains target;
 506         u16 tmp;
 507         enum ieee80211_band tmp2;
 508         bool do_rssi_cal;
 509
 510         u16 clip[2];
 511         bool do_cal = false;
 512
 513         if ((dev->phy.rev >= 3) &&
 514            (bus->sprom.boardflags_lo & B43_BFL_EXTLNA) &&
 515            (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
 516                 chipco_set32(&dev->dev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40);
 517         }
 518         nphy->deaf_count = 0;
 519         b43_nphy_tables_init(dev);
 520         nphy->crsminpwr_adjusted = false;
 521         nphy->noisevars_adjusted = false;
 522
 523         /* Clear all overrides */
 524         if (dev->phy.rev >= 3) {
 525                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
 526                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
 527                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
 528                 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
 529         } else {
 530                 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
 531         }
 532         b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
 533         b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
 534         if (dev->phy.rev < 6) {
 535                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
 536                 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
 537         }
 538         b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
 539                      ~(B43_NPHY_RFSEQMODE_CAOVER |
 540                        B43_NPHY_RFSEQMODE_TROVER));
 541         if (dev->phy.rev >= 3)
 542                 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
 543         b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
 544
 545         if (dev->phy.rev <= 2) {
 546                 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
 547                 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
 548                                 ~B43_NPHY_BPHY_CTL3_SCALE,
 549                                 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
 550         }
 551         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
 552         b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
 553
 554         if (bus->sprom.boardflags2_lo & 0x100 ||
 555             (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
 556              bus->boardinfo.type == 0x8B))
 557                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
 558         else
 559                 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
 560         b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
 561         b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
 562         b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
 563
 564         /* TODO MIMO-Config */
 565         /* TODO Update TX/RX chain */
 566
 567         if (phy->rev < 2) {
 568                 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
 569                 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
 570         }
 571
 572         tmp2 = b43_current_band(dev->wl);
 573         if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) ||
 574             (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) {
 575                 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
 576                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
 577                                 nphy->papd_epsilon_offset[0] << 7);
 578                 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
 579                 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
 580                                 nphy->papd_epsilon_offset[1] << 7);
 581                 /* TODO N PHY IPA Set TX Dig Filters */
 582         } else if (phy->rev >= 5) {
 583                 /* TODO N PHY Ext PA Set TX Dig Filters */
 584         }
 585
 586         b43_nphy_workarounds(dev);
 587
 588         /* Reset CCA, in init code it differs a little from standard way */
 589         /* b43_nphy_bmac_clock_fgc(dev, 1); */
 590         tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
 591         b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
 592         b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
 593         /* b43_nphy_bmac_clock_fgc(dev, 0); */
 594
 595         /* TODO N PHY MAC PHY Clock Set with argument 1 */
 596
 597         /* b43_nphy_pa_override(dev, false); */
 598         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
 599         b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
 600         /* b43_nphy_pa_override(dev, true); */
 601
 602         b43_nphy_classifier(dev, 0, 0);
 603         b43_nphy_read_clip_detection(dev, clip);
 604         tx_pwr_state = nphy->txpwrctrl;
 605         /* TODO N PHY TX power control with argument 0
 606                 (turning off power control) */
 607         /* TODO Fix the TX Power Settings */
 608         /* TODO N PHY TX Power Control Idle TSSI */
 609         /* TODO N PHY TX Power Control Setup */
 610
 611         if (phy->rev >= 3) {
 612                 /* TODO */
 613         } else {
 614                 /* TODO Write an N PHY table with ID 26, length 128, offset 192, width 32, and the data from Rev 2 TX Power Control Table */
 615                 /* TODO Write an N PHY table with ID 27, length 128, offset 192, width 32, and the data from Rev 2 TX Power Control Table */
 616         }
 617
 618         if (nphy->phyrxchain != 3)
 619                 ;/* TODO N PHY RX Core Set State with phyrxchain as argument */
 620         if (nphy->mphase_cal_phase_id > 0)
 621                 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
 622
 623         do_rssi_cal = false;
 624         if (phy->rev >= 3) {
 625                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
 626                         do_rssi_cal = (nphy->rssical_chanspec_2G == 0);
 627                 else
 628                         do_rssi_cal = (nphy->rssical_chanspec_5G == 0);
 629
 630                 if (do_rssi_cal)
 631                         b43_nphy_rssi_cal(dev);
 632                 else
 633                         ;/* b43_nphy_restore_rssi_cal(dev); */
 634         } else {
 635                 b43_nphy_rssi_cal(dev);
 636         }
 637
 638         if (!((nphy->measure_hold & 0x6) != 0)) {
 639                 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
 640                         do_cal = (nphy->iqcal_chanspec_2G == 0);
 641                 else
 642                         do_cal = (nphy->iqcal_chanspec_5G == 0);
 643
 644                 if (nphy->mute)
 645                         do_cal = false;
 646
 647                 if (do_cal) {
 648                         /* target = b43_nphy_get_tx_gains(dev); */
 649
 650                         if (nphy->antsel_type == 2)
 651                                 ;/*TODO NPHY Superswitch Init with argument 1*/
 652                         if (nphy->perical != 2) {
 653                                 /* b43_nphy_rssi_cal(dev); */
 654                                 if (phy->rev >= 3) {
 655                                         nphy->cal_orig_pwr_idx[0] =
 656                                             nphy->txpwrindex[0].index_internal;
 657                                         nphy->cal_orig_pwr_idx[1] =
 658                                             nphy->txpwrindex[1].index_internal;
 659                                         /* TODO N PHY Pre Calibrate TX Gain */
 660                                         /*target = b43_nphy_get_tx_gains(dev)*/
 661                                 }
 662                         }
 663                 }
 664         }
 665
 666         /*
 667         if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false)) {
 668                 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
 669                         Call N PHY Save Cal
 670                 else if (nphy->mphase_cal_phase_id == 0)
 671                         N PHY Periodic Calibration with argument 3
 672         } else {
 673                 b43_nphy_restore_cal(dev);
 674         }
 675         */
 676
 677         /* b43_nphy_tx_pwr_ctrl_coef_setup(dev); */
 678         /* TODO N PHY TX Power Control Enable with argument tx_pwr_state */
 679         b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
 680         b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
 681         if (phy->rev >= 3 && phy->rev <= 6)
 682                 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
 683         /* b43_nphy_tx_lp_fbw(dev); */
 684         /* TODO N PHY Spur Workaround */
 685
 686         b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n");
 687         return 0;
 688 }
 689
 690 static int b43_nphy_op_allocate(struct b43_wldev *dev)
 691 {
 692         struct b43_phy_n *nphy;
 693
 694         nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
 695         if (!nphy)
 696                 return -ENOMEM;
 697         dev->phy.n = nphy;
 698
 699         return 0;
 700 }
 701
 702 static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
 703 {
 704         struct b43_phy *phy = &dev->phy;
 705         struct b43_phy_n *nphy = phy->n;
 706
 707         memset(nphy, 0, sizeof(*nphy));
 708
 709         //TODO init struct b43_phy_n
 710 }
 711
 712 static void b43_nphy_op_free(struct b43_wldev *dev)
 713 {
 714         struct b43_phy *phy = &dev->phy;
 715         struct b43_phy_n *nphy = phy->n;
 716
 717         kfree(nphy);
 718         phy->n = NULL;
 719 }
 720
 721 static int b43_nphy_op_init(struct b43_wldev *dev)
 722 {
 723         return b43_phy_initn(dev);
 724 }
 725
 726 static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
 727 {
 728 #if B43_DEBUG
 729         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
 730                 /* OFDM registers are onnly available on A/G-PHYs */
 731                 b43err(dev->wl, "Invalid OFDM PHY access at "
 732                        "0x%04X on N-PHY\n", offset);
 733                 dump_stack();
 734         }
 735         if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
 736                 /* Ext-G registers are only available on G-PHYs */
 737                 b43err(dev->wl, "Invalid EXT-G PHY access at "
 738                        "0x%04X on N-PHY\n", offset);
 739                 dump_stack();
 740         }
 741 #endif /* B43_DEBUG */
 742 }
 743
 744 static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
 745 {
 746         check_phyreg(dev, reg);
 747         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
 748         return b43_read16(dev, B43_MMIO_PHY_DATA);
 749 }
 750
 751 static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
 752 {
 753         check_phyreg(dev, reg);
 754         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
 755         b43_write16(dev, B43_MMIO_PHY_DATA, value);
 756 }
 757
 758 static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
 759 {
 760         /* Register 1 is a 32-bit register. */
 761         B43_WARN_ON(reg == 1);
 762         /* N-PHY needs 0x100 for read access */
 763         reg |= 0x100;
 764
 765         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
 766         return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
 767 }
 768
 769 static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
 770 {
 771         /* Register 1 is a 32-bit register. */
 772         B43_WARN_ON(reg == 1);
 773
 774         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
 775         b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
 776 }
 777
 778 static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
 779                                         bool blocked)
 780 {//TODO
 781 }
 782
 783 static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
 784 {
 785         b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
 786                       on ? 0 : 0x7FFF);
 787 }
 788
 789 static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
 790                                       unsigned int new_channel)
 791 {
 792         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
 793                 if ((new_channel < 1) || (new_channel > 14))
 794                         return -EINVAL;
 795         } else {
 796                 if (new_channel > 200)
 797                         return -EINVAL;
 798         }
 799
 800         return nphy_channel_switch(dev, new_channel);
 801 }
 802
 803 static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
 804 {
 805         if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
 806                 return 1;
 807         return 36;
 808 }
 809
 810 const struct b43_phy_operations b43_phyops_n = {
 811         .allocate               = b43_nphy_op_allocate,
 812         .free                   = b43_nphy_op_free,
 813         .prepare_structs        = b43_nphy_op_prepare_structs,
 814         .init                   = b43_nphy_op_init,
 815         .phy_read               = b43_nphy_op_read,
 816         .phy_write              = b43_nphy_op_write,
 817         .radio_read             = b43_nphy_op_radio_read,
 818         .radio_write            = b43_nphy_op_radio_write,
 819         .software_rfkill        = b43_nphy_op_software_rfkill,
 820         .switch_analog          = b43_nphy_op_switch_analog,
 821         .switch_channel         = b43_nphy_op_switch_channel,
 822         .get_default_chan       = b43_nphy_op_get_default_chan,
 823         .recalc_txpower         = b43_nphy_op_recalc_txpower,
 824         .adjust_txpower         = b43_nphy_op_adjust_txpower,
 825 };