3 Broadcom B43 wireless driver
4 IEEE 802.11g LP-PHY driver
6 Copyright (c) 2008-2009 Michael Buesch <mb@bu3sch.de>
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING. If not, write to
20 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
21 Boston, MA 02110-1301, USA.
28 #include "phy_common.h"
29 #include "tables_lpphy.h"
32 static inline u16 channel2freq_lp(u8 channel)
35 return (2407 + 5 * channel);
36 else if (channel == 14)
38 else if (channel < 184)
39 return (5000 + 5 * channel);
41 return (4000 + 5 * channel);
44 static unsigned int b43_lpphy_op_get_default_chan(struct b43_wldev *dev)
46 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
51 static int b43_lpphy_op_allocate(struct b43_wldev *dev)
53 struct b43_phy_lp *lpphy;
55 lpphy = kzalloc(sizeof(*lpphy), GFP_KERNEL);
63 static void b43_lpphy_op_prepare_structs(struct b43_wldev *dev)
65 struct b43_phy *phy = &dev->phy;
66 struct b43_phy_lp *lpphy = phy->lp;
68 memset(lpphy, 0, sizeof(*lpphy));
73 static void b43_lpphy_op_free(struct b43_wldev *dev)
75 struct b43_phy_lp *lpphy = dev->phy.lp;
81 static void lpphy_read_band_sprom(struct b43_wldev *dev)
83 struct b43_phy_lp *lpphy = dev->phy.lp;
84 struct ssb_bus *bus = dev->dev->bus;
89 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
90 lpphy->tx_isolation_med_band = bus->sprom.tri2g;
91 lpphy->bx_arch = bus->sprom.bxa2g;
92 lpphy->rx_pwr_offset = bus->sprom.rxpo2g;
93 lpphy->rssi_vf = bus->sprom.rssismf2g;
94 lpphy->rssi_vc = bus->sprom.rssismc2g;
95 lpphy->rssi_gs = bus->sprom.rssisav2g;
96 lpphy->txpa[0] = bus->sprom.pa0b0;
97 lpphy->txpa[1] = bus->sprom.pa0b1;
98 lpphy->txpa[2] = bus->sprom.pa0b2;
99 maxpwr = bus->sprom.maxpwr_bg;
100 lpphy->max_tx_pwr_med_band = maxpwr;
101 cckpo = bus->sprom.cck2gpo;
102 ofdmpo = bus->sprom.ofdm2gpo;
104 for (i = 0; i < 4; i++) {
105 lpphy->tx_max_rate[i] =
106 maxpwr - (ofdmpo & 0xF) * 2;
109 ofdmpo = bus->sprom.ofdm2gpo;
110 for (i = 4; i < 15; i++) {
111 lpphy->tx_max_rate[i] =
112 maxpwr - (ofdmpo & 0xF) * 2;
117 for (i = 0; i < 4; i++)
118 lpphy->tx_max_rate[i] = maxpwr;
119 for (i = 4; i < 15; i++)
120 lpphy->tx_max_rate[i] = maxpwr - ofdmpo;
123 lpphy->tx_isolation_low_band = bus->sprom.tri5gl;
124 lpphy->tx_isolation_med_band = bus->sprom.tri5g;
125 lpphy->tx_isolation_hi_band = bus->sprom.tri5gh;
126 lpphy->bx_arch = bus->sprom.bxa5g;
127 lpphy->rx_pwr_offset = bus->sprom.rxpo5g;
128 lpphy->rssi_vf = bus->sprom.rssismf5g;
129 lpphy->rssi_vc = bus->sprom.rssismc5g;
130 lpphy->rssi_gs = bus->sprom.rssisav5g;
131 lpphy->txpa[0] = bus->sprom.pa1b0;
132 lpphy->txpa[1] = bus->sprom.pa1b1;
133 lpphy->txpa[2] = bus->sprom.pa1b2;
134 lpphy->txpal[0] = bus->sprom.pa1lob0;
135 lpphy->txpal[1] = bus->sprom.pa1lob1;
136 lpphy->txpal[2] = bus->sprom.pa1lob2;
137 lpphy->txpah[0] = bus->sprom.pa1hib0;
138 lpphy->txpah[1] = bus->sprom.pa1hib1;
139 lpphy->txpah[2] = bus->sprom.pa1hib2;
140 maxpwr = bus->sprom.maxpwr_al;
141 ofdmpo = bus->sprom.ofdm5glpo;
142 lpphy->max_tx_pwr_low_band = maxpwr;
143 for (i = 4; i < 12; i++) {
144 lpphy->tx_max_ratel[i] = maxpwr - (ofdmpo & 0xF) * 2;
147 maxpwr = bus->sprom.maxpwr_a;
148 ofdmpo = bus->sprom.ofdm5gpo;
149 lpphy->max_tx_pwr_med_band = maxpwr;
150 for (i = 4; i < 12; i++) {
151 lpphy->tx_max_rate[i] = maxpwr - (ofdmpo & 0xF) * 2;
154 maxpwr = bus->sprom.maxpwr_ah;
155 ofdmpo = bus->sprom.ofdm5ghpo;
156 lpphy->max_tx_pwr_hi_band = maxpwr;
157 for (i = 4; i < 12; i++) {
158 lpphy->tx_max_rateh[i] = maxpwr - (ofdmpo & 0xF) * 2;
164 static void lpphy_adjust_gain_table(struct b43_wldev *dev, u32 freq)
166 struct b43_phy_lp *lpphy = dev->phy.lp;
170 B43_WARN_ON(dev->phy.rev >= 2);
172 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
173 isolation = lpphy->tx_isolation_med_band;
174 else if (freq <= 5320)
175 isolation = lpphy->tx_isolation_low_band;
176 else if (freq <= 5700)
177 isolation = lpphy->tx_isolation_med_band;
179 isolation = lpphy->tx_isolation_hi_band;
181 temp[0] = ((isolation - 26) / 12) << 12;
182 temp[1] = temp[0] + 0x1000;
183 temp[2] = temp[0] + 0x2000;
185 b43_lptab_write_bulk(dev, B43_LPTAB16(13, 0), 3, temp);
186 b43_lptab_write_bulk(dev, B43_LPTAB16(12, 0), 3, temp);
189 static void lpphy_table_init(struct b43_wldev *dev)
191 u32 freq = channel2freq_lp(b43_lpphy_op_get_default_chan(dev));
193 if (dev->phy.rev < 2)
194 lpphy_rev0_1_table_init(dev);
196 lpphy_rev2plus_table_init(dev);
198 lpphy_init_tx_gain_table(dev);
200 if (dev->phy.rev < 2)
201 lpphy_adjust_gain_table(dev, freq);
204 static void lpphy_baseband_rev0_1_init(struct b43_wldev *dev)
206 struct ssb_bus *bus = dev->dev->bus;
207 struct b43_phy_lp *lpphy = dev->phy.lp;
210 b43_phy_mask(dev, B43_LPPHY_AFE_DAC_CTL, 0xF7FF);
211 b43_phy_write(dev, B43_LPPHY_AFE_CTL, 0);
212 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, 0);
213 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, 0);
214 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0);
215 b43_phy_set(dev, B43_LPPHY_AFE_DAC_CTL, 0x0004);
216 b43_phy_maskset(dev, B43_LPPHY_OFDMSYNCTHRESH0, 0xFF00, 0x0078);
217 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0x83FF, 0x5800);
218 b43_phy_write(dev, B43_LPPHY_ADC_COMPENSATION_CTL, 0x0016);
219 b43_phy_maskset(dev, B43_LPPHY_AFE_ADC_CTL_0, 0xFFF8, 0x0004);
220 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0x00FF, 0x5400);
221 b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0x00FF, 0x2400);
222 b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x2100);
223 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0x0006);
224 b43_phy_mask(dev, B43_LPPHY_RX_RADIO_CTL, 0xFFFE);
225 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFFE0, 0x0005);
226 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFC1F, 0x0180);
227 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0x83FF, 0x3C00);
228 b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xFFF0, 0x0005);
229 b43_phy_maskset(dev, B43_LPPHY_GAIN_MISMATCH_LIMIT, 0xFFC0, 0x001A);
230 b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0xFF00, 0x00B3);
231 b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0x00FF, 0xAD00);
232 b43_phy_maskset(dev, B43_LPPHY_INPUT_PWRDB,
233 0xFF00, lpphy->rx_pwr_offset);
234 if ((bus->sprom.boardflags_lo & B43_BFL_FEM) &&
235 ((b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ||
236 (bus->sprom.boardflags_hi & B43_BFH_PAREF))) {
237 ssb_pmu_set_ldo_voltage(&bus->chipco, LDO_PAREF, 0x28);
238 ssb_pmu_set_ldo_paref(&bus->chipco, true);
239 if (dev->phy.rev == 0) {
240 b43_phy_maskset(dev, B43_LPPHY_LP_RF_SIGNAL_LUT,
243 b43_lptab_write(dev, B43_LPTAB16(11, 7), 60);
245 ssb_pmu_set_ldo_paref(&bus->chipco, false);
246 b43_phy_maskset(dev, B43_LPPHY_LP_RF_SIGNAL_LUT,
248 b43_lptab_write(dev, B43_LPTAB16(11, 7), 100);
250 tmp = lpphy->rssi_vf | lpphy->rssi_vc << 4 | 0xA000;
251 b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_0, tmp);
252 if (bus->sprom.boardflags_hi & B43_BFH_RSSIINV)
253 b43_phy_maskset(dev, B43_LPPHY_AFE_RSSI_CTL_1, 0xF000, 0x0AAA);
255 b43_phy_maskset(dev, B43_LPPHY_AFE_RSSI_CTL_1, 0xF000, 0x02AA);
256 b43_lptab_write(dev, B43_LPTAB16(11, 1), 24);
257 b43_phy_maskset(dev, B43_LPPHY_RX_RADIO_CTL,
258 0xFFF9, (lpphy->bx_arch << 1));
259 if (dev->phy.rev == 1 &&
260 (bus->sprom.boardflags_hi & B43_BFH_FEM_BT)) {
261 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x000A);
262 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0x3F00, 0x0900);
263 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x000A);
264 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0B00);
265 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x000A);
266 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0400);
267 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x000A);
268 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0B00);
269 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_5, 0xFFC0, 0x000A);
270 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_5, 0xC0FF, 0x0900);
271 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_6, 0xFFC0, 0x000A);
272 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_6, 0xC0FF, 0x0B00);
273 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_7, 0xFFC0, 0x000A);
274 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_7, 0xC0FF, 0x0900);
275 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xFFC0, 0x000A);
276 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_8, 0xC0FF, 0x0B00);
277 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ ||
278 (bus->boardinfo.type == 0x048A) || ((dev->phy.rev == 0) &&
279 (bus->sprom.boardflags_lo & B43_BFL_FEM))) {
280 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0001);
281 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0400);
282 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0001);
283 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0500);
284 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0002);
285 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0800);
286 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0002);
287 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0A00);
288 } else if (dev->phy.rev == 1 ||
289 (bus->sprom.boardflags_lo & B43_BFL_FEM)) {
290 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x0004);
291 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0800);
292 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x0004);
293 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0C00);
294 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0002);
295 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0100);
296 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0002);
297 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0300);
299 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xFFC0, 0x000A);
300 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_1, 0xC0FF, 0x0900);
301 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xFFC0, 0x000A);
302 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_2, 0xC0FF, 0x0B00);
303 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xFFC0, 0x0006);
304 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_3, 0xC0FF, 0x0500);
305 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xFFC0, 0x0006);
306 b43_phy_maskset(dev, B43_LPPHY_TR_LOOKUP_4, 0xC0FF, 0x0700);
308 if (dev->phy.rev == 1 && (bus->sprom.boardflags_hi & B43_BFH_PAREF)) {
309 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_5, B43_LPPHY_TR_LOOKUP_1);
310 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_6, B43_LPPHY_TR_LOOKUP_2);
311 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_7, B43_LPPHY_TR_LOOKUP_3);
312 b43_phy_copy(dev, B43_LPPHY_TR_LOOKUP_8, B43_LPPHY_TR_LOOKUP_4);
314 if ((bus->sprom.boardflags_hi & B43_BFH_FEM_BT) &&
315 (bus->chip_id == 0x5354) &&
316 (bus->chip_package == SSB_CHIPPACK_BCM4712S)) {
317 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x0006);
318 b43_phy_write(dev, B43_LPPHY_GPIO_SELECT, 0x0005);
319 b43_phy_write(dev, B43_LPPHY_GPIO_OUTEN, 0xFFFF);
320 //FIXME the Broadcom driver caches & delays this HF write!
321 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_PR45960W);
323 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
324 b43_phy_set(dev, B43_LPPHY_LP_PHY_CTL, 0x8000);
325 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x0040);
326 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0x00FF, 0xA400);
327 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xF0FF, 0x0B00);
328 b43_phy_maskset(dev, B43_LPPHY_SYNCPEAKCNT, 0xFFF8, 0x0007);
329 b43_phy_maskset(dev, B43_LPPHY_DSSS_CONFIRM_CNT, 0xFFF8, 0x0003);
330 b43_phy_maskset(dev, B43_LPPHY_DSSS_CONFIRM_CNT, 0xFFC7, 0x0020);
331 b43_phy_mask(dev, B43_LPPHY_IDLEAFTERPKTRXTO, 0x00FF);
333 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0x7FFF);
334 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFBF);
336 if (dev->phy.rev == 1) {
337 tmp = b43_phy_read(dev, B43_LPPHY_CLIPCTRTHRESH);
338 tmp2 = (tmp & 0x03E0) >> 5;
340 b43_phy_write(dev, B43_LPPHY_4C3, tmp2);
341 tmp = b43_phy_read(dev, B43_LPPHY_GAINDIRECTMISMATCH);
342 tmp2 = (tmp & 0x1F00) >> 8;
344 b43_phy_write(dev, B43_LPPHY_4C4, tmp2);
345 tmp = b43_phy_read(dev, B43_LPPHY_VERYLOWGAINDB);
348 b43_phy_write(dev, B43_LPPHY_4C5, tmp2);
352 static void lpphy_save_dig_flt_state(struct b43_wldev *dev)
354 static const u16 addr[] = {
366 static const u16 coefs[] = {
367 0xDE5E, 0xE832, 0xE331, 0x4D26,
368 0x0026, 0x1420, 0x0020, 0xFE08,
372 struct b43_phy_lp *lpphy = dev->phy.lp;
375 for (i = 0; i < ARRAY_SIZE(addr); i++) {
376 lpphy->dig_flt_state[i] = b43_phy_read(dev, addr[i]);
377 b43_phy_write(dev, addr[i], coefs[i]);
381 static void lpphy_restore_dig_flt_state(struct b43_wldev *dev)
383 static const u16 addr[] = {
395 struct b43_phy_lp *lpphy = dev->phy.lp;
398 for (i = 0; i < ARRAY_SIZE(addr); i++)
399 b43_phy_write(dev, addr[i], lpphy->dig_flt_state[i]);
402 static void lpphy_baseband_rev2plus_init(struct b43_wldev *dev)
404 struct ssb_bus *bus = dev->dev->bus;
405 struct b43_phy_lp *lpphy = dev->phy.lp;
407 b43_phy_write(dev, B43_LPPHY_AFE_DAC_CTL, 0x50);
408 b43_phy_write(dev, B43_LPPHY_AFE_CTL, 0x8800);
409 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, 0);
410 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0);
411 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, 0);
412 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0);
413 b43_phy_write(dev, B43_PHY_OFDM(0xF9), 0);
414 b43_phy_write(dev, B43_LPPHY_TR_LOOKUP_1, 0);
415 b43_phy_set(dev, B43_LPPHY_ADC_COMPENSATION_CTL, 0x10);
416 b43_phy_maskset(dev, B43_LPPHY_OFDMSYNCTHRESH0, 0xFF00, 0xB4);
417 b43_phy_maskset(dev, B43_LPPHY_DCOFFSETTRANSIENT, 0xF8FF, 0x200);
418 b43_phy_maskset(dev, B43_LPPHY_DCOFFSETTRANSIENT, 0xFF00, 0x7F);
419 b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xFF0F, 0x40);
420 b43_phy_maskset(dev, B43_LPPHY_PREAMBLECONFIRMTO, 0xFF00, 0x2);
421 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x4000);
422 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x2000);
423 b43_phy_set(dev, B43_PHY_OFDM(0x10A), 0x1);
424 if (bus->boardinfo.rev >= 0x18) {
425 b43_lptab_write(dev, B43_LPTAB32(17, 65), 0xEC);
426 b43_phy_maskset(dev, B43_PHY_OFDM(0x10A), 0xFF01, 0x14);
428 b43_phy_maskset(dev, B43_PHY_OFDM(0x10A), 0xFF01, 0x10);
430 b43_phy_maskset(dev, B43_PHY_OFDM(0xDF), 0xFF00, 0xF4);
431 b43_phy_maskset(dev, B43_PHY_OFDM(0xDF), 0x00FF, 0xF100);
432 b43_phy_write(dev, B43_LPPHY_CLIPTHRESH, 0x48);
433 b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0xFF00, 0x46);
434 b43_phy_maskset(dev, B43_PHY_OFDM(0xE4), 0xFF00, 0x10);
435 b43_phy_maskset(dev, B43_LPPHY_PWR_THRESH1, 0xFFF0, 0x9);
436 b43_phy_mask(dev, B43_LPPHY_GAINDIRECTMISMATCH, ~0xF);
437 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0x00FF, 0x5500);
438 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFC1F, 0xA0);
439 b43_phy_maskset(dev, B43_LPPHY_GAINDIRECTMISMATCH, 0xE0FF, 0x300);
440 b43_phy_maskset(dev, B43_LPPHY_HIGAINDB, 0x00FF, 0x2A00);
441 if ((bus->chip_id == 0x4325) && (bus->chip_rev == 0)) {
442 b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x2100);
443 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0xA);
445 b43_phy_maskset(dev, B43_LPPHY_LOWGAINDB, 0x00FF, 0x1E00);
446 b43_phy_maskset(dev, B43_LPPHY_VERYLOWGAINDB, 0xFF00, 0xD);
448 b43_phy_maskset(dev, B43_PHY_OFDM(0xFE), 0xFFE0, 0x1F);
449 b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0xFFE0, 0xC);
450 b43_phy_maskset(dev, B43_PHY_OFDM(0x100), 0xFF00, 0x19);
451 b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0x03FF, 0x3C00);
452 b43_phy_maskset(dev, B43_PHY_OFDM(0xFE), 0xFC1F, 0x3E0);
453 b43_phy_maskset(dev, B43_PHY_OFDM(0xFF), 0xFFE0, 0xC);
454 b43_phy_maskset(dev, B43_PHY_OFDM(0x100), 0x00FF, 0x1900);
455 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0x83FF, 0x5800);
456 b43_phy_maskset(dev, B43_LPPHY_CLIPCTRTHRESH, 0xFFE0, 0x12);
457 b43_phy_maskset(dev, B43_LPPHY_GAINMISMATCH, 0x0FFF, 0x9000);
459 if ((bus->chip_id == 0x4325) && (bus->chip_rev == 0)) {
460 b43_lptab_write(dev, B43_LPTAB16(0x08, 0x14), 0);
461 b43_lptab_write(dev, B43_LPTAB16(0x08, 0x12), 0x40);
464 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
465 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x40);
466 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xF0FF, 0xB00);
467 b43_phy_maskset(dev, B43_LPPHY_SYNCPEAKCNT, 0xFFF8, 0x6);
468 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0x00FF, 0x9D00);
469 b43_phy_maskset(dev, B43_LPPHY_MINPWR_LEVEL, 0xFF00, 0xA1);
470 b43_phy_mask(dev, B43_LPPHY_IDLEAFTERPKTRXTO, 0x00FF);
472 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, ~0x40);
474 b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0xFF00, 0xB3);
475 b43_phy_maskset(dev, B43_LPPHY_CRS_ED_THRESH, 0x00FF, 0xAD00);
476 b43_phy_maskset(dev, B43_LPPHY_INPUT_PWRDB, 0xFF00, lpphy->rx_pwr_offset);
477 b43_phy_set(dev, B43_LPPHY_RESET_CTL, 0x44);
478 b43_phy_write(dev, B43_LPPHY_RESET_CTL, 0x80);
479 b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_0, 0xA954);
480 b43_phy_write(dev, B43_LPPHY_AFE_RSSI_CTL_1,
481 0x2000 | ((u16)lpphy->rssi_gs << 10) |
482 ((u16)lpphy->rssi_vc << 4) | lpphy->rssi_vf);
484 if ((bus->chip_id == 0x4325) && (bus->chip_rev == 0)) {
485 b43_phy_set(dev, B43_LPPHY_AFE_ADC_CTL_0, 0x1C);
486 b43_phy_maskset(dev, B43_LPPHY_AFE_CTL, 0x00FF, 0x8800);
487 b43_phy_maskset(dev, B43_LPPHY_AFE_ADC_CTL_1, 0xFC3C, 0x0400);
490 lpphy_save_dig_flt_state(dev);
493 static void lpphy_baseband_init(struct b43_wldev *dev)
495 lpphy_table_init(dev);
496 if (dev->phy.rev >= 2)
497 lpphy_baseband_rev2plus_init(dev);
499 lpphy_baseband_rev0_1_init(dev);
502 struct b2062_freqdata {
507 /* Initialize the 2062 radio. */
508 static void lpphy_2062_init(struct b43_wldev *dev)
510 struct b43_phy_lp *lpphy = dev->phy.lp;
511 struct ssb_bus *bus = dev->dev->bus;
512 u32 crystalfreq, tmp, ref;
514 const struct b2062_freqdata *fd = NULL;
516 static const struct b2062_freqdata freqdata_tab[] = {
517 { .freq = 12000, .data[0] = 6, .data[1] = 6, .data[2] = 6,
518 .data[3] = 6, .data[4] = 10, .data[5] = 6, },
519 { .freq = 13000, .data[0] = 4, .data[1] = 4, .data[2] = 4,
520 .data[3] = 4, .data[4] = 11, .data[5] = 7, },
521 { .freq = 14400, .data[0] = 3, .data[1] = 3, .data[2] = 3,
522 .data[3] = 3, .data[4] = 12, .data[5] = 7, },
523 { .freq = 16200, .data[0] = 3, .data[1] = 3, .data[2] = 3,
524 .data[3] = 3, .data[4] = 13, .data[5] = 8, },
525 { .freq = 18000, .data[0] = 2, .data[1] = 2, .data[2] = 2,
526 .data[3] = 2, .data[4] = 14, .data[5] = 8, },
527 { .freq = 19200, .data[0] = 1, .data[1] = 1, .data[2] = 1,
528 .data[3] = 1, .data[4] = 14, .data[5] = 9, },
531 b2062_upload_init_table(dev);
533 b43_radio_write(dev, B2062_N_TX_CTL3, 0);
534 b43_radio_write(dev, B2062_N_TX_CTL4, 0);
535 b43_radio_write(dev, B2062_N_TX_CTL5, 0);
536 b43_radio_write(dev, B2062_N_TX_CTL6, 0);
537 b43_radio_write(dev, B2062_N_PDN_CTL0, 0x40);
538 b43_radio_write(dev, B2062_N_PDN_CTL0, 0);
539 b43_radio_write(dev, B2062_N_CALIB_TS, 0x10);
540 b43_radio_write(dev, B2062_N_CALIB_TS, 0);
541 if (dev->phy.rev > 0) {
542 b43_radio_write(dev, B2062_S_BG_CTL1,
543 (b43_radio_read(dev, B2062_N_COMM2) >> 1) | 0x80);
545 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
546 b43_radio_set(dev, B2062_N_TSSI_CTL0, 0x1);
548 b43_radio_mask(dev, B2062_N_TSSI_CTL0, ~0x1);
550 /* Get the crystal freq, in Hz. */
551 crystalfreq = bus->chipco.pmu.crystalfreq * 1000;
553 B43_WARN_ON(!(bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU));
554 B43_WARN_ON(crystalfreq == 0);
556 if (crystalfreq <= 30000000) {
558 b43_radio_mask(dev, B2062_S_RFPLL_CTL1, 0xFFFB);
561 b43_radio_set(dev, B2062_S_RFPLL_CTL1, 0x4);
564 tmp = (((800000000 * lpphy->pdiv + crystalfreq) /
565 (2 * crystalfreq)) - 8) & 0xFF;
566 b43_radio_write(dev, B2062_S_RFPLL_CTL7, tmp);
568 tmp = (((100 * crystalfreq + 16000000 * lpphy->pdiv) /
569 (32000000 * lpphy->pdiv)) - 1) & 0xFF;
570 b43_radio_write(dev, B2062_S_RFPLL_CTL18, tmp);
572 tmp = (((2 * crystalfreq + 1000000 * lpphy->pdiv) /
573 (2000000 * lpphy->pdiv)) - 1) & 0xFF;
574 b43_radio_write(dev, B2062_S_RFPLL_CTL19, tmp);
576 ref = (1000 * lpphy->pdiv + 2 * crystalfreq) / (2000 * lpphy->pdiv);
578 for (i = 0; i < ARRAY_SIZE(freqdata_tab); i++) {
579 if (ref < freqdata_tab[i].freq) {
580 fd = &freqdata_tab[i];
585 fd = &freqdata_tab[ARRAY_SIZE(freqdata_tab) - 1];
586 b43dbg(dev->wl, "b2062: Using crystal tab entry %u kHz.\n",
587 fd->freq); /* FIXME: Keep this printk until the code is fully debugged. */
589 b43_radio_write(dev, B2062_S_RFPLL_CTL8,
590 ((u16)(fd->data[1]) << 4) | fd->data[0]);
591 b43_radio_write(dev, B2062_S_RFPLL_CTL9,
592 ((u16)(fd->data[3]) << 4) | fd->data[2]);
593 b43_radio_write(dev, B2062_S_RFPLL_CTL10, fd->data[4]);
594 b43_radio_write(dev, B2062_S_RFPLL_CTL11, fd->data[5]);
597 /* Initialize the 2063 radio. */
598 static void lpphy_2063_init(struct b43_wldev *dev)
600 b2063_upload_init_table(dev);
601 b43_radio_write(dev, B2063_LOGEN_SP5, 0);
602 b43_radio_set(dev, B2063_COMM8, 0x38);
603 b43_radio_write(dev, B2063_REG_SP1, 0x56);
604 b43_radio_mask(dev, B2063_RX_BB_CTL2, ~0x2);
605 b43_radio_write(dev, B2063_PA_SP7, 0);
606 b43_radio_write(dev, B2063_TX_RF_SP6, 0x20);
607 b43_radio_write(dev, B2063_TX_RF_SP9, 0x40);
608 if (dev->phy.rev == 2) {
609 b43_radio_write(dev, B2063_PA_SP3, 0xa0);
610 b43_radio_write(dev, B2063_PA_SP4, 0xa0);
611 b43_radio_write(dev, B2063_PA_SP2, 0x18);
613 b43_radio_write(dev, B2063_PA_SP3, 0x20);
614 b43_radio_write(dev, B2063_PA_SP2, 0x20);
618 struct lpphy_stx_table_entry {
626 static const struct lpphy_stx_table_entry lpphy_stx_table[] = {
627 { .phy_offset = 2, .phy_shift = 6, .rf_addr = 0x3d, .rf_shift = 3, .mask = 0x01, },
628 { .phy_offset = 1, .phy_shift = 12, .rf_addr = 0x4c, .rf_shift = 1, .mask = 0x01, },
629 { .phy_offset = 1, .phy_shift = 8, .rf_addr = 0x50, .rf_shift = 0, .mask = 0x7f, },
630 { .phy_offset = 0, .phy_shift = 8, .rf_addr = 0x44, .rf_shift = 0, .mask = 0xff, },
631 { .phy_offset = 1, .phy_shift = 0, .rf_addr = 0x4a, .rf_shift = 0, .mask = 0xff, },
632 { .phy_offset = 0, .phy_shift = 4, .rf_addr = 0x4d, .rf_shift = 0, .mask = 0xff, },
633 { .phy_offset = 1, .phy_shift = 4, .rf_addr = 0x4e, .rf_shift = 0, .mask = 0xff, },
634 { .phy_offset = 0, .phy_shift = 12, .rf_addr = 0x4f, .rf_shift = 0, .mask = 0x0f, },
635 { .phy_offset = 1, .phy_shift = 0, .rf_addr = 0x4f, .rf_shift = 4, .mask = 0x0f, },
636 { .phy_offset = 3, .phy_shift = 0, .rf_addr = 0x49, .rf_shift = 0, .mask = 0x0f, },
637 { .phy_offset = 4, .phy_shift = 3, .rf_addr = 0x46, .rf_shift = 4, .mask = 0x07, },
638 { .phy_offset = 3, .phy_shift = 15, .rf_addr = 0x46, .rf_shift = 0, .mask = 0x01, },
639 { .phy_offset = 4, .phy_shift = 0, .rf_addr = 0x46, .rf_shift = 1, .mask = 0x07, },
640 { .phy_offset = 3, .phy_shift = 8, .rf_addr = 0x48, .rf_shift = 4, .mask = 0x07, },
641 { .phy_offset = 3, .phy_shift = 11, .rf_addr = 0x48, .rf_shift = 0, .mask = 0x0f, },
642 { .phy_offset = 3, .phy_shift = 4, .rf_addr = 0x49, .rf_shift = 4, .mask = 0x0f, },
643 { .phy_offset = 2, .phy_shift = 15, .rf_addr = 0x45, .rf_shift = 0, .mask = 0x01, },
644 { .phy_offset = 5, .phy_shift = 13, .rf_addr = 0x52, .rf_shift = 4, .mask = 0x07, },
645 { .phy_offset = 6, .phy_shift = 0, .rf_addr = 0x52, .rf_shift = 7, .mask = 0x01, },
646 { .phy_offset = 5, .phy_shift = 3, .rf_addr = 0x41, .rf_shift = 5, .mask = 0x07, },
647 { .phy_offset = 5, .phy_shift = 6, .rf_addr = 0x41, .rf_shift = 0, .mask = 0x0f, },
648 { .phy_offset = 5, .phy_shift = 10, .rf_addr = 0x42, .rf_shift = 5, .mask = 0x07, },
649 { .phy_offset = 4, .phy_shift = 15, .rf_addr = 0x42, .rf_shift = 0, .mask = 0x01, },
650 { .phy_offset = 5, .phy_shift = 0, .rf_addr = 0x42, .rf_shift = 1, .mask = 0x07, },
651 { .phy_offset = 4, .phy_shift = 11, .rf_addr = 0x43, .rf_shift = 4, .mask = 0x0f, },
652 { .phy_offset = 4, .phy_shift = 7, .rf_addr = 0x43, .rf_shift = 0, .mask = 0x0f, },
653 { .phy_offset = 4, .phy_shift = 6, .rf_addr = 0x45, .rf_shift = 1, .mask = 0x01, },
654 { .phy_offset = 2, .phy_shift = 7, .rf_addr = 0x40, .rf_shift = 4, .mask = 0x0f, },
655 { .phy_offset = 2, .phy_shift = 11, .rf_addr = 0x40, .rf_shift = 0, .mask = 0x0f, },
658 static void lpphy_sync_stx(struct b43_wldev *dev)
660 const struct lpphy_stx_table_entry *e;
664 for (i = 0; i < ARRAY_SIZE(lpphy_stx_table); i++) {
665 e = &lpphy_stx_table[i];
666 tmp = b43_radio_read(dev, e->rf_addr);
668 tmp <<= e->phy_shift;
669 b43_phy_maskset(dev, B43_PHY_OFDM(0xF2 + e->phy_offset),
670 ~(e->mask << e->phy_shift), tmp);
674 static void lpphy_radio_init(struct b43_wldev *dev)
676 /* The radio is attached through the 4wire bus. */
677 b43_phy_set(dev, B43_LPPHY_FOURWIRE_CTL, 0x2);
679 b43_phy_mask(dev, B43_LPPHY_FOURWIRE_CTL, 0xFFFD);
682 if (dev->phy.radio_ver == 0x2062) {
683 lpphy_2062_init(dev);
685 lpphy_2063_init(dev);
687 b43_phy_write(dev, B43_PHY_OFDM(0xF0), 0x5F80);
688 b43_phy_write(dev, B43_PHY_OFDM(0xF1), 0);
689 if (dev->dev->bus->chip_id == 0x4325) {
690 // TODO SSB PMU recalibration
695 struct lpphy_iq_est { u32 iq_prod, i_pwr, q_pwr; };
697 static void lpphy_set_rc_cap(struct b43_wldev *dev)
699 struct b43_phy_lp *lpphy = dev->phy.lp;
701 u8 rc_cap = (lpphy->rc_cap & 0x1F) >> 1;
703 if (dev->phy.rev == 1) //FIXME check channel 14!
704 rc_cap = min_t(u8, rc_cap + 5, 15);
706 b43_radio_write(dev, B2062_N_RXBB_CALIB2,
707 max_t(u8, lpphy->rc_cap - 4, 0x80));
708 b43_radio_write(dev, B2062_N_TX_CTL_A, rc_cap | 0x80);
709 b43_radio_write(dev, B2062_S_RXG_CNT16,
710 ((lpphy->rc_cap & 0x1F) >> 2) | 0x80);
713 static u8 lpphy_get_bb_mult(struct b43_wldev *dev)
715 return (b43_lptab_read(dev, B43_LPTAB16(0, 87)) & 0xFF00) >> 8;
718 static void lpphy_set_bb_mult(struct b43_wldev *dev, u8 bb_mult)
720 b43_lptab_write(dev, B43_LPTAB16(0, 87), (u16)bb_mult << 8);
723 static void lpphy_set_deaf(struct b43_wldev *dev, bool user)
725 struct b43_phy_lp *lpphy = dev->phy.lp;
728 lpphy->crs_usr_disable = 1;
730 lpphy->crs_sys_disable = 1;
731 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL, 0xFF1F, 0x80);
734 static void lpphy_clear_deaf(struct b43_wldev *dev, bool user)
736 struct b43_phy_lp *lpphy = dev->phy.lp;
739 lpphy->crs_usr_disable = 0;
741 lpphy->crs_sys_disable = 0;
743 if (!lpphy->crs_usr_disable && !lpphy->crs_sys_disable) {
744 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
745 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL,
748 b43_phy_maskset(dev, B43_LPPHY_CRSGAIN_CTL,
753 static void lpphy_disable_crs(struct b43_wldev *dev, bool user)
755 lpphy_set_deaf(dev, user);
756 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFC, 0x1);
757 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x3);
758 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFB);
759 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x4);
760 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFF7);
761 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x8);
762 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x10);
763 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x10);
764 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFDF);
765 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x20);
766 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFBF);
767 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x40);
768 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0x7);
769 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0x38);
770 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFF3F);
771 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0x100);
772 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFDFF);
773 b43_phy_write(dev, B43_LPPHY_PS_CTL_OVERRIDE_VAL0, 0);
774 b43_phy_write(dev, B43_LPPHY_PS_CTL_OVERRIDE_VAL1, 1);
775 b43_phy_write(dev, B43_LPPHY_PS_CTL_OVERRIDE_VAL2, 0x20);
776 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFBFF);
777 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xF7FF);
778 b43_phy_write(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL, 0);
779 b43_phy_write(dev, B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL, 0x45AF);
780 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, 0x3FF);
783 static void lpphy_restore_crs(struct b43_wldev *dev, bool user)
785 lpphy_clear_deaf(dev, user);
786 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFF80);
787 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFC00);
790 struct lpphy_tx_gains { u16 gm, pga, pad, dac; };
792 static struct lpphy_tx_gains lpphy_get_tx_gains(struct b43_wldev *dev)
794 struct lpphy_tx_gains gains;
797 gains.dac = (b43_phy_read(dev, B43_LPPHY_AFE_DAC_CTL) & 0x380) >> 7;
798 if (dev->phy.rev < 2) {
799 tmp = b43_phy_read(dev,
800 B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL) & 0x7FF;
801 gains.gm = tmp & 0x0007;
802 gains.pga = (tmp & 0x0078) >> 3;
803 gains.pad = (tmp & 0x780) >> 7;
805 tmp = b43_phy_read(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL);
806 gains.pad = b43_phy_read(dev, B43_PHY_OFDM(0xFB)) & 0xFF;
807 gains.gm = tmp & 0xFF;
808 gains.pga = (tmp >> 8) & 0xFF;
814 static void lpphy_set_dac_gain(struct b43_wldev *dev, u16 dac)
816 u16 ctl = b43_phy_read(dev, B43_LPPHY_AFE_DAC_CTL) & 0xC7F;
818 b43_phy_maskset(dev, B43_LPPHY_AFE_DAC_CTL, 0xF000, ctl);
821 static void lpphy_set_tx_gains(struct b43_wldev *dev,
822 struct lpphy_tx_gains gains)
824 u16 rf_gain, pa_gain;
826 if (dev->phy.rev < 2) {
827 rf_gain = (gains.pad << 7) | (gains.pga << 3) | gains.gm;
828 b43_phy_maskset(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL,
831 pa_gain = b43_phy_read(dev, B43_PHY_OFDM(0xFB)) & 0x1FC0;
833 b43_phy_write(dev, B43_LPPHY_TX_GAIN_CTL_OVERRIDE_VAL,
834 (gains.pga << 8) | gains.gm);
835 b43_phy_maskset(dev, B43_PHY_OFDM(0xFB),
836 0x8000, gains.pad | pa_gain);
837 b43_phy_write(dev, B43_PHY_OFDM(0xFC),
838 (gains.pga << 8) | gains.gm);
839 b43_phy_maskset(dev, B43_PHY_OFDM(0xFD),
840 0x8000, gains.pad | pa_gain);
842 lpphy_set_dac_gain(dev, gains.dac);
843 if (dev->phy.rev < 2) {
844 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF, 1 << 8);
846 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFF7F, 1 << 7);
847 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2, 0xBFFF, 1 << 14);
849 b43_phy_maskset(dev, B43_LPPHY_AFE_CTL_OVR, 0xFFBF, 1 << 6);
852 static void lpphy_rev0_1_set_rx_gain(struct b43_wldev *dev, u32 gain)
854 u16 trsw = gain & 0x1;
855 u16 lna = (gain & 0xFFFC) | ((gain & 0xC) >> 2);
856 u16 ext_lna = (gain & 2) >> 1;
858 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFE, trsw);
859 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
860 0xFBFF, ext_lna << 10);
861 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
862 0xF7FF, ext_lna << 11);
863 b43_phy_write(dev, B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL, lna);
866 static void lpphy_rev2plus_set_rx_gain(struct b43_wldev *dev, u32 gain)
868 u16 low_gain = gain & 0xFFFF;
869 u16 high_gain = (gain >> 16) & 0xF;
870 u16 ext_lna = (gain >> 21) & 0x1;
871 u16 trsw = ~(gain >> 20) & 0x1;
874 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFE, trsw);
875 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
876 0xFDFF, ext_lna << 9);
877 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
878 0xFBFF, ext_lna << 10);
879 b43_phy_write(dev, B43_LPPHY_RX_GAIN_CTL_OVERRIDE_VAL, low_gain);
880 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFFF0, high_gain);
881 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
882 tmp = (gain >> 2) & 0x3;
883 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL,
885 b43_phy_maskset(dev, B43_PHY_OFDM(0xE6), 0xFFE7, tmp << 3);
889 static void lpphy_disable_rx_gain_override(struct b43_wldev *dev)
891 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFFE);
892 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFEF);
893 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xFFBF);
894 if (dev->phy.rev >= 2) {
895 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFEFF);
896 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
897 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFBFF);
898 b43_phy_mask(dev, B43_PHY_OFDM(0xE5), 0xFFF7);
901 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_2, 0xFDFF);
905 static void lpphy_enable_rx_gain_override(struct b43_wldev *dev)
907 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x1);
908 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x10);
909 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x40);
910 if (dev->phy.rev >= 2) {
911 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x100);
912 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
913 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x400);
914 b43_phy_set(dev, B43_PHY_OFDM(0xE5), 0x8);
917 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_2, 0x200);
921 static void lpphy_set_rx_gain(struct b43_wldev *dev, u32 gain)
923 if (dev->phy.rev < 2)
924 lpphy_rev0_1_set_rx_gain(dev, gain);
926 lpphy_rev2plus_set_rx_gain(dev, gain);
927 lpphy_enable_rx_gain_override(dev);
930 static void lpphy_set_rx_gain_by_index(struct b43_wldev *dev, u16 idx)
932 u32 gain = b43_lptab_read(dev, B43_LPTAB16(12, idx));
933 lpphy_set_rx_gain(dev, gain);
936 static void lpphy_stop_ddfs(struct b43_wldev *dev)
938 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS, 0xFFFD);
939 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0xFFDF);
942 static void lpphy_run_ddfs(struct b43_wldev *dev, int i_on, int q_on,
943 int incr1, int incr2, int scale_idx)
945 lpphy_stop_ddfs(dev);
946 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS_POINTER_INIT, 0xFF80);
947 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS_POINTER_INIT, 0x80FF);
948 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS_INCR_INIT, 0xFF80, incr1);
949 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS_INCR_INIT, 0x80FF, incr2 << 8);
950 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFFF7, i_on << 3);
951 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFFEF, q_on << 4);
952 b43_phy_maskset(dev, B43_LPPHY_AFE_DDFS, 0xFF9F, scale_idx << 5);
953 b43_phy_mask(dev, B43_LPPHY_AFE_DDFS, 0xFFFB);
954 b43_phy_set(dev, B43_LPPHY_AFE_DDFS, 0x2);
955 b43_phy_set(dev, B43_LPPHY_LP_PHY_CTL, 0x20);
958 static bool lpphy_rx_iq_est(struct b43_wldev *dev, u16 samples, u8 time,
959 struct lpphy_iq_est *iq_est)
963 b43_phy_mask(dev, B43_LPPHY_CRSGAIN_CTL, 0xFFF7);
964 b43_phy_write(dev, B43_LPPHY_IQ_NUM_SMPLS_ADDR, samples);
965 b43_phy_maskset(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0xFF00, time);
966 b43_phy_mask(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0xFEFF);
967 b43_phy_set(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR, 0x200);
969 for (i = 0; i < 500; i++) {
970 if (!(b43_phy_read(dev,
971 B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR) & 0x200))
976 if ((b43_phy_read(dev, B43_LPPHY_IQ_ENABLE_WAIT_TIME_ADDR) & 0x200)) {
977 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x8);
981 iq_est->iq_prod = b43_phy_read(dev, B43_LPPHY_IQ_ACC_HI_ADDR);
982 iq_est->iq_prod <<= 16;
983 iq_est->iq_prod |= b43_phy_read(dev, B43_LPPHY_IQ_ACC_LO_ADDR);
985 iq_est->i_pwr = b43_phy_read(dev, B43_LPPHY_IQ_I_PWR_ACC_HI_ADDR);
986 iq_est->i_pwr <<= 16;
987 iq_est->i_pwr |= b43_phy_read(dev, B43_LPPHY_IQ_I_PWR_ACC_LO_ADDR);
989 iq_est->q_pwr = b43_phy_read(dev, B43_LPPHY_IQ_Q_PWR_ACC_HI_ADDR);
990 iq_est->q_pwr <<= 16;
991 iq_est->q_pwr |= b43_phy_read(dev, B43_LPPHY_IQ_Q_PWR_ACC_LO_ADDR);
993 b43_phy_set(dev, B43_LPPHY_CRSGAIN_CTL, 0x8);
997 static int lpphy_loopback(struct b43_wldev *dev)
999 struct lpphy_iq_est iq_est;
1003 memset(&iq_est, 0, sizeof(iq_est));
1005 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xFFFC, 0x3);
1006 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x3);
1007 b43_phy_set(dev, B43_LPPHY_AFE_CTL_OVR, 1);
1008 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xFFFE);
1009 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x800);
1010 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x800);
1011 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x8);
1012 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x8);
1013 b43_radio_write(dev, B2062_N_TX_CTL_A, 0x80);
1014 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_0, 0x80);
1015 b43_phy_set(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0x80);
1016 for (i = 0; i < 32; i++) {
1017 lpphy_set_rx_gain_by_index(dev, i);
1018 lpphy_run_ddfs(dev, 1, 1, 5, 5, 0);
1019 if (!(lpphy_rx_iq_est(dev, 1000, 32, &iq_est)))
1021 tmp = (iq_est.i_pwr + iq_est.q_pwr) / 1000;
1022 if ((tmp > 4000) && (tmp < 10000)) {
1027 lpphy_stop_ddfs(dev);
1031 /* Fixed-point division algorithm using only integer math. */
1032 static u32 lpphy_qdiv_roundup(u32 dividend, u32 divisor, u8 precision)
1034 u32 quotient, remainder;
1039 quotient = dividend / divisor;
1040 remainder = dividend % divisor;
1042 while (precision > 0) {
1044 if (remainder << 1 >= divisor) {
1046 remainder = (remainder << 1) - divisor;
1051 if (remainder << 1 >= divisor)
1057 /* Read the TX power control mode from hardware. */
1058 static void lpphy_read_tx_pctl_mode_from_hardware(struct b43_wldev *dev)
1060 struct b43_phy_lp *lpphy = dev->phy.lp;
1063 ctl = b43_phy_read(dev, B43_LPPHY_TX_PWR_CTL_CMD);
1064 switch (ctl & B43_LPPHY_TX_PWR_CTL_CMD_MODE) {
1065 case B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF:
1066 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_OFF;
1068 case B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW:
1069 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_SW;
1071 case B43_LPPHY_TX_PWR_CTL_CMD_MODE_HW:
1072 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_HW;
1075 lpphy->txpctl_mode = B43_LPPHY_TXPCTL_UNKNOWN;
1081 /* Set the TX power control mode in hardware. */
1082 static void lpphy_write_tx_pctl_mode_to_hardware(struct b43_wldev *dev)
1084 struct b43_phy_lp *lpphy = dev->phy.lp;
1087 switch (lpphy->txpctl_mode) {
1088 case B43_LPPHY_TXPCTL_OFF:
1089 ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF;
1091 case B43_LPPHY_TXPCTL_HW:
1092 ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_HW;
1094 case B43_LPPHY_TXPCTL_SW:
1095 ctl = B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW;
1101 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
1102 (u16)~B43_LPPHY_TX_PWR_CTL_CMD_MODE, ctl);
1105 static void lpphy_set_tx_power_control(struct b43_wldev *dev,
1106 enum b43_lpphy_txpctl_mode mode)
1108 struct b43_phy_lp *lpphy = dev->phy.lp;
1109 enum b43_lpphy_txpctl_mode oldmode;
1111 lpphy_read_tx_pctl_mode_from_hardware(dev);
1112 oldmode = lpphy->txpctl_mode;
1113 if (oldmode == mode)
1115 lpphy->txpctl_mode = mode;
1117 if (oldmode == B43_LPPHY_TXPCTL_HW) {
1118 //TODO Update TX Power NPT
1119 //TODO Clear all TX Power offsets
1121 if (mode == B43_LPPHY_TXPCTL_HW) {
1122 //TODO Recalculate target TX power
1123 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
1124 0xFF80, lpphy->tssi_idx);
1125 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_NNUM,
1126 0x8FFF, ((u16)lpphy->tssi_npt << 16));
1127 //TODO Set "TSSI Transmit Count" variable to total transmitted frame count
1128 //TODO Disable TX gain override
1129 lpphy->tx_pwr_idx_over = -1;
1132 if (dev->phy.rev >= 2) {
1133 if (mode == B43_LPPHY_TXPCTL_HW)
1134 b43_phy_set(dev, B43_PHY_OFDM(0xD0), 0x2);
1136 b43_phy_mask(dev, B43_PHY_OFDM(0xD0), 0xFFFD);
1138 lpphy_write_tx_pctl_mode_to_hardware(dev);
1141 static int b43_lpphy_op_switch_channel(struct b43_wldev *dev,
1142 unsigned int new_channel);
1144 static void lpphy_rev0_1_rc_calib(struct b43_wldev *dev)
1146 struct b43_phy_lp *lpphy = dev->phy.lp;
1147 struct lpphy_iq_est iq_est;
1148 struct lpphy_tx_gains tx_gains;
1149 static const u32 ideal_pwr_table[21] = {
1150 0x10000, 0x10557, 0x10e2d, 0x113e0, 0x10f22, 0x0ff64,
1151 0x0eda2, 0x0e5d4, 0x0efd1, 0x0fbe8, 0x0b7b8, 0x04b35,
1152 0x01a5e, 0x00a0b, 0x00444, 0x001fd, 0x000ff, 0x00088,
1153 0x0004c, 0x0002c, 0x0001a,
1157 u16 old_rf_ovr, old_rf_ovrval, old_afe_ovr, old_afe_ovrval,
1158 old_rf2_ovr, old_rf2_ovrval, old_phy_ctl;
1159 enum b43_lpphy_txpctl_mode old_txpctl;
1160 u32 normal_pwr, ideal_pwr, mean_sq_pwr, tmp = 0, mean_sq_pwr_min = 0;
1161 int loopback, i, j, inner_sum, err;
1163 memset(&iq_est, 0, sizeof(iq_est));
1165 err = b43_lpphy_op_switch_channel(dev, 7);
1168 "RC calib: Failed to switch to channel 7, error = %d\n",
1171 old_txg_ovr = !!(b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVR) & 0x40);
1172 old_bbmult = lpphy_get_bb_mult(dev);
1174 tx_gains = lpphy_get_tx_gains(dev);
1175 old_rf_ovr = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_0);
1176 old_rf_ovrval = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_VAL_0);
1177 old_afe_ovr = b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVR);
1178 old_afe_ovrval = b43_phy_read(dev, B43_LPPHY_AFE_CTL_OVRVAL);
1179 old_rf2_ovr = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_2);
1180 old_rf2_ovrval = b43_phy_read(dev, B43_LPPHY_RF_OVERRIDE_2_VAL);
1181 old_phy_ctl = b43_phy_read(dev, B43_LPPHY_LP_PHY_CTL);
1182 lpphy_read_tx_pctl_mode_from_hardware(dev);
1183 old_txpctl = lpphy->txpctl_mode;
1185 lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF);
1186 lpphy_disable_crs(dev, true);
1187 loopback = lpphy_loopback(dev);
1190 lpphy_set_rx_gain_by_index(dev, loopback);
1191 b43_phy_maskset(dev, B43_LPPHY_LP_PHY_CTL, 0xFFBF, 0x40);
1192 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFFF8, 0x1);
1193 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFFC7, 0x8);
1194 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, 0xFF3F, 0xC0);
1195 for (i = 128; i <= 159; i++) {
1196 b43_radio_write(dev, B2062_N_RXBB_CALIB2, i);
1198 for (j = 5; j <= 25; j++) {
1199 lpphy_run_ddfs(dev, 1, 1, j, j, 0);
1200 if (!(lpphy_rx_iq_est(dev, 1000, 32, &iq_est)))
1202 mean_sq_pwr = iq_est.i_pwr + iq_est.q_pwr;
1205 ideal_pwr = ((ideal_pwr_table[j-5] >> 3) + 1) >> 1;
1206 normal_pwr = lpphy_qdiv_roundup(mean_sq_pwr, tmp, 12);
1207 mean_sq_pwr = ideal_pwr - normal_pwr;
1208 mean_sq_pwr *= mean_sq_pwr;
1209 inner_sum += mean_sq_pwr;
1210 if ((i == 128) || (inner_sum < mean_sq_pwr_min)) {
1212 mean_sq_pwr_min = inner_sum;
1216 lpphy_stop_ddfs(dev);
1219 lpphy_restore_crs(dev, true);
1220 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, old_rf_ovrval);
1221 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_0, old_rf_ovr);
1222 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVRVAL, old_afe_ovrval);
1223 b43_phy_write(dev, B43_LPPHY_AFE_CTL_OVR, old_afe_ovr);
1224 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2_VAL, old_rf2_ovrval);
1225 b43_phy_write(dev, B43_LPPHY_RF_OVERRIDE_2, old_rf2_ovr);
1226 b43_phy_write(dev, B43_LPPHY_LP_PHY_CTL, old_phy_ctl);
1228 lpphy_set_bb_mult(dev, old_bbmult);
1231 * SPEC FIXME: The specs say "get_tx_gains" here, which is
1232 * illogical. According to lwfinger, vendor driver v4.150.10.5
1233 * has a Set here, while v4.174.64.19 has a Get - regression in
1234 * the vendor driver? This should be tested this once the code
1237 lpphy_set_tx_gains(dev, tx_gains);
1239 lpphy_set_tx_power_control(dev, old_txpctl);
1241 lpphy_set_rc_cap(dev);
1244 static void lpphy_rev2plus_rc_calib(struct b43_wldev *dev)
1246 struct ssb_bus *bus = dev->dev->bus;
1247 u32 crystal_freq = bus->chipco.pmu.crystalfreq * 1000;
1248 u8 tmp = b43_radio_read(dev, B2063_RX_BB_SP8) & 0xFF;
1251 b43_radio_write(dev, B2063_RX_BB_SP8, 0x0);
1252 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7E);
1253 b43_radio_mask(dev, B2063_PLL_SP1, 0xF7);
1254 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7C);
1255 b43_radio_write(dev, B2063_RC_CALIB_CTL2, 0x15);
1256 b43_radio_write(dev, B2063_RC_CALIB_CTL3, 0x70);
1257 b43_radio_write(dev, B2063_RC_CALIB_CTL4, 0x52);
1258 b43_radio_write(dev, B2063_RC_CALIB_CTL5, 0x1);
1259 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7D);
1261 for (i = 0; i < 10000; i++) {
1262 if (b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2)
1267 if (!(b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2))
1268 b43_radio_write(dev, B2063_RX_BB_SP8, tmp);
1270 tmp = b43_radio_read(dev, B2063_TX_BB_SP3) & 0xFF;
1272 b43_radio_write(dev, B2063_TX_BB_SP3, 0x0);
1273 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7E);
1274 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7C);
1275 b43_radio_write(dev, B2063_RC_CALIB_CTL2, 0x55);
1276 b43_radio_write(dev, B2063_RC_CALIB_CTL3, 0x76);
1278 if (crystal_freq == 24000000) {
1279 b43_radio_write(dev, B2063_RC_CALIB_CTL4, 0xFC);
1280 b43_radio_write(dev, B2063_RC_CALIB_CTL5, 0x0);
1282 b43_radio_write(dev, B2063_RC_CALIB_CTL4, 0x13);
1283 b43_radio_write(dev, B2063_RC_CALIB_CTL5, 0x1);
1286 b43_radio_write(dev, B2063_PA_SP7, 0x7D);
1288 for (i = 0; i < 10000; i++) {
1289 if (b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2)
1294 if (!(b43_radio_read(dev, B2063_RC_CALIB_CTL6) & 0x2))
1295 b43_radio_write(dev, B2063_TX_BB_SP3, tmp);
1297 b43_radio_write(dev, B2063_RC_CALIB_CTL1, 0x7E);
1300 static void lpphy_calibrate_rc(struct b43_wldev *dev)
1302 struct b43_phy_lp *lpphy = dev->phy.lp;
1304 if (dev->phy.rev >= 2) {
1305 lpphy_rev2plus_rc_calib(dev);
1306 } else if (!lpphy->rc_cap) {
1307 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1308 lpphy_rev0_1_rc_calib(dev);
1310 lpphy_set_rc_cap(dev);
1314 static void lpphy_set_tx_power_by_index(struct b43_wldev *dev, u8 index)
1316 struct b43_phy_lp *lpphy = dev->phy.lp;
1318 lpphy->tx_pwr_idx_over = index;
1319 if (lpphy->txpctl_mode != B43_LPPHY_TXPCTL_OFF)
1320 lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_SW);
1325 static void lpphy_btcoex_override(struct b43_wldev *dev)
1327 b43_write16(dev, B43_MMIO_BTCOEX_CTL, 0x3);
1328 b43_write16(dev, B43_MMIO_BTCOEX_TXCTL, 0xFF);
1331 static void lpphy_pr41573_workaround(struct b43_wldev *dev)
1333 struct b43_phy_lp *lpphy = dev->phy.lp;
1335 const unsigned int saved_tab_size = 256;
1336 enum b43_lpphy_txpctl_mode txpctl_mode;
1338 u16 tssi_npt, tssi_idx;
1340 saved_tab = kcalloc(saved_tab_size, sizeof(saved_tab[0]), GFP_KERNEL);
1342 b43err(dev->wl, "PR41573 failed. Out of memory!\n");
1346 lpphy_read_tx_pctl_mode_from_hardware(dev);
1347 txpctl_mode = lpphy->txpctl_mode;
1348 tx_pwr_idx_over = lpphy->tx_pwr_idx_over;
1349 tssi_npt = lpphy->tssi_npt;
1350 tssi_idx = lpphy->tssi_idx;
1352 if (dev->phy.rev < 2) {
1353 b43_lptab_read_bulk(dev, B43_LPTAB32(10, 0x140),
1354 saved_tab_size, saved_tab);
1356 b43_lptab_read_bulk(dev, B43_LPTAB32(7, 0x140),
1357 saved_tab_size, saved_tab);
1364 static void lpphy_calibration(struct b43_wldev *dev)
1366 struct b43_phy_lp *lpphy = dev->phy.lp;
1367 enum b43_lpphy_txpctl_mode saved_pctl_mode;
1369 b43_mac_suspend(dev);
1371 lpphy_btcoex_override(dev);
1372 lpphy_read_tx_pctl_mode_from_hardware(dev);
1373 saved_pctl_mode = lpphy->txpctl_mode;
1374 lpphy_set_tx_power_control(dev, B43_LPPHY_TXPCTL_OFF);
1375 //TODO Perform transmit power table I/Q LO calibration
1376 if ((dev->phy.rev == 0) && (saved_pctl_mode != B43_LPPHY_TXPCTL_OFF))
1377 lpphy_pr41573_workaround(dev);
1378 //TODO If a full calibration has not been performed on this channel yet, perform PAPD TX-power calibration
1379 lpphy_set_tx_power_control(dev, saved_pctl_mode);
1380 //TODO Perform I/Q calibration with a single control value set
1382 b43_mac_enable(dev);
1385 static void lpphy_set_tssi_mux(struct b43_wldev *dev, enum tssi_mux_mode mode)
1387 if (mode != TSSI_MUX_EXT) {
1388 b43_radio_set(dev, B2063_PA_SP1, 0x2);
1389 b43_phy_set(dev, B43_PHY_OFDM(0xF3), 0x1000);
1390 b43_radio_write(dev, B2063_PA_CTL10, 0x51);
1391 if (mode == TSSI_MUX_POSTPA) {
1392 b43_radio_mask(dev, B2063_PA_SP1, 0xFFFE);
1393 b43_phy_mask(dev, B43_LPPHY_AFE_CTL_OVRVAL, 0xFFC7);
1395 b43_radio_maskset(dev, B2063_PA_SP1, 0xFFFE, 0x1);
1396 b43_phy_maskset(dev, B43_LPPHY_AFE_CTL_OVRVAL,
1404 static void lpphy_tx_pctl_init_hw(struct b43_wldev *dev)
1409 //SPEC TODO Call LP PHY Clear TX Power offsets
1410 for (i = 0; i < 64; i++) {
1411 if (dev->phy.rev >= 2)
1412 b43_lptab_write(dev, B43_LPTAB32(7, i + 1), i);
1414 b43_lptab_write(dev, B43_LPTAB32(10, i + 1), i);
1417 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_NNUM, 0xFF00, 0xFF);
1418 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_NNUM, 0x8FFF, 0x5000);
1419 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_IDLETSSI, 0xFFC0, 0x1F);
1420 if (dev->phy.rev < 2) {
1421 b43_phy_mask(dev, B43_LPPHY_LP_PHY_CTL, 0xEFFF);
1422 b43_phy_maskset(dev, B43_LPPHY_LP_PHY_CTL, 0xDFFF, 0x2000);
1424 b43_phy_mask(dev, B43_PHY_OFDM(0x103), 0xFFFE);
1425 b43_phy_maskset(dev, B43_PHY_OFDM(0x103), 0xFFFB, 0x4);
1426 b43_phy_maskset(dev, B43_PHY_OFDM(0x103), 0xFFEF, 0x10);
1427 b43_radio_maskset(dev, B2063_IQ_CALIB_CTL2, 0xF3, 0x1);
1428 lpphy_set_tssi_mux(dev, TSSI_MUX_POSTPA);
1430 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_IDLETSSI, 0x7FFF, 0x8000);
1431 b43_phy_mask(dev, B43_LPPHY_TX_PWR_CTL_DELTAPWR_LIMIT, 0xFF);
1432 b43_phy_write(dev, B43_LPPHY_TX_PWR_CTL_DELTAPWR_LIMIT, 0xA);
1433 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
1434 (u16)~B43_LPPHY_TX_PWR_CTL_CMD_MODE,
1435 B43_LPPHY_TX_PWR_CTL_CMD_MODE_OFF);
1436 b43_phy_mask(dev, B43_LPPHY_TX_PWR_CTL_NNUM, 0xF8FF);
1437 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_CMD,
1438 (u16)~B43_LPPHY_TX_PWR_CTL_CMD_MODE,
1439 B43_LPPHY_TX_PWR_CTL_CMD_MODE_SW);
1441 if (dev->phy.rev < 2) {
1442 b43_phy_maskset(dev, B43_LPPHY_RF_OVERRIDE_0, 0xEFFF, 0x1000);
1443 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_VAL_0, 0xEFFF);
1445 lpphy_set_tx_power_by_index(dev, 0x7F);
1448 b43_dummy_transmission(dev, true, true);
1450 tmp = b43_phy_read(dev, B43_LPPHY_TX_PWR_CTL_STAT);
1452 b43_phy_maskset(dev, B43_LPPHY_TX_PWR_CTL_IDLETSSI,
1453 0xFFC0, (tmp & 0xFF) - 32);
1456 b43_phy_mask(dev, B43_LPPHY_RF_OVERRIDE_0, 0xEFFF);
1458 // (SPEC?) TODO Set "Target TX frequency" variable to 0
1459 // SPEC FIXME "Set BB Multiplier to 0xE000" impossible - bb_mult is u8!
1462 static void lpphy_tx_pctl_init_sw(struct b43_wldev *dev)
1464 struct lpphy_tx_gains gains;
1466 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
1477 lpphy_set_tx_gains(dev, gains);
1478 lpphy_set_bb_mult(dev, 150);
1481 /* Initialize TX power control */
1482 static void lpphy_tx_pctl_init(struct b43_wldev *dev)
1484 if (0/*FIXME HWPCTL capable */) {
1485 lpphy_tx_pctl_init_hw(dev);
1486 } else { /* This device is only software TX power control capable. */
1487 lpphy_tx_pctl_init_sw(dev);
1491 static u16 b43_lpphy_op_read(struct b43_wldev *dev, u16 reg)
1493 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
1494 return b43_read16(dev, B43_MMIO_PHY_DATA);
1497 static void b43_lpphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
1499 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
1500 b43_write16(dev, B43_MMIO_PHY_DATA, value);
1503 static void b43_lpphy_op_maskset(struct b43_wldev *dev, u16 reg, u16 mask,
1506 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
1507 b43_write16(dev, B43_MMIO_PHY_DATA,
1508 (b43_read16(dev, B43_MMIO_PHY_DATA) & mask) | set);
1511 static u16 b43_lpphy_op_radio_read(struct b43_wldev *dev, u16 reg)
1513 /* Register 1 is a 32-bit register. */
1514 B43_WARN_ON(reg == 1);
1515 /* LP-PHY needs a special bit set for read access */
1516 if (dev->phy.rev < 2) {
1522 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
1523 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
1526 static void b43_lpphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
1528 /* Register 1 is a 32-bit register. */
1529 B43_WARN_ON(reg == 1);
1531 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
1532 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
1535 static void b43_lpphy_op_software_rfkill(struct b43_wldev *dev,
1541 struct b206x_channel {
1547 static const struct b206x_channel b2062_chantbl[] = {
1548 { .channel = 1, .freq = 2412, .data[0] = 0xFF, .data[1] = 0xFF,
1549 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1550 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1551 { .channel = 2, .freq = 2417, .data[0] = 0xFF, .data[1] = 0xFF,
1552 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1553 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1554 { .channel = 3, .freq = 2422, .data[0] = 0xFF, .data[1] = 0xFF,
1555 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1556 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1557 { .channel = 4, .freq = 2427, .data[0] = 0xFF, .data[1] = 0xFF,
1558 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1559 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1560 { .channel = 5, .freq = 2432, .data[0] = 0xFF, .data[1] = 0xFF,
1561 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1562 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1563 { .channel = 6, .freq = 2437, .data[0] = 0xFF, .data[1] = 0xFF,
1564 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1565 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1566 { .channel = 7, .freq = 2442, .data[0] = 0xFF, .data[1] = 0xFF,
1567 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1568 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1569 { .channel = 8, .freq = 2447, .data[0] = 0xFF, .data[1] = 0xFF,
1570 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1571 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1572 { .channel = 9, .freq = 2452, .data[0] = 0xFF, .data[1] = 0xFF,
1573 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1574 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1575 { .channel = 10, .freq = 2457, .data[0] = 0xFF, .data[1] = 0xFF,
1576 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1577 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1578 { .channel = 11, .freq = 2462, .data[0] = 0xFF, .data[1] = 0xFF,
1579 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1580 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1581 { .channel = 12, .freq = 2467, .data[0] = 0xFF, .data[1] = 0xFF,
1582 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1583 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1584 { .channel = 13, .freq = 2472, .data[0] = 0xFF, .data[1] = 0xFF,
1585 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1586 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1587 { .channel = 14, .freq = 2484, .data[0] = 0xFF, .data[1] = 0xFF,
1588 .data[2] = 0xB5, .data[3] = 0x1B, .data[4] = 0x24, .data[5] = 0x32,
1589 .data[6] = 0x32, .data[7] = 0x88, .data[8] = 0x88, },
1590 { .channel = 34, .freq = 5170, .data[0] = 0x00, .data[1] = 0x22,
1591 .data[2] = 0x20, .data[3] = 0x84, .data[4] = 0x3C, .data[5] = 0x77,
1592 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1593 { .channel = 38, .freq = 5190, .data[0] = 0x00, .data[1] = 0x11,
1594 .data[2] = 0x10, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1595 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1596 { .channel = 42, .freq = 5210, .data[0] = 0x00, .data[1] = 0x11,
1597 .data[2] = 0x10, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1598 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1599 { .channel = 46, .freq = 5230, .data[0] = 0x00, .data[1] = 0x00,
1600 .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1601 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1602 { .channel = 36, .freq = 5180, .data[0] = 0x00, .data[1] = 0x11,
1603 .data[2] = 0x20, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1604 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1605 { .channel = 40, .freq = 5200, .data[0] = 0x00, .data[1] = 0x11,
1606 .data[2] = 0x10, .data[3] = 0x84, .data[4] = 0x3C, .data[5] = 0x77,
1607 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1608 { .channel = 44, .freq = 5220, .data[0] = 0x00, .data[1] = 0x11,
1609 .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1610 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1611 { .channel = 48, .freq = 5240, .data[0] = 0x00, .data[1] = 0x00,
1612 .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1613 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1614 { .channel = 52, .freq = 5260, .data[0] = 0x00, .data[1] = 0x00,
1615 .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1616 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1617 { .channel = 56, .freq = 5280, .data[0] = 0x00, .data[1] = 0x00,
1618 .data[2] = 0x00, .data[3] = 0x83, .data[4] = 0x3C, .data[5] = 0x77,
1619 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1620 { .channel = 60, .freq = 5300, .data[0] = 0x00, .data[1] = 0x00,
1621 .data[2] = 0x00, .data[3] = 0x63, .data[4] = 0x3C, .data[5] = 0x77,
1622 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1623 { .channel = 64, .freq = 5320, .data[0] = 0x00, .data[1] = 0x00,
1624 .data[2] = 0x00, .data[3] = 0x62, .data[4] = 0x3C, .data[5] = 0x77,
1625 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1626 { .channel = 100, .freq = 5500, .data[0] = 0x00, .data[1] = 0x00,
1627 .data[2] = 0x00, .data[3] = 0x30, .data[4] = 0x3C, .data[5] = 0x77,
1628 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1629 { .channel = 104, .freq = 5520, .data[0] = 0x00, .data[1] = 0x00,
1630 .data[2] = 0x00, .data[3] = 0x20, .data[4] = 0x3C, .data[5] = 0x77,
1631 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1632 { .channel = 108, .freq = 5540, .data[0] = 0x00, .data[1] = 0x00,
1633 .data[2] = 0x00, .data[3] = 0x20, .data[4] = 0x3C, .data[5] = 0x77,
1634 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1635 { .channel = 112, .freq = 5560, .data[0] = 0x00, .data[1] = 0x00,
1636 .data[2] = 0x00, .data[3] = 0x20, .data[4] = 0x3C, .data[5] = 0x77,
1637 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1638 { .channel = 116, .freq = 5580, .data[0] = 0x00, .data[1] = 0x00,
1639 .data[2] = 0x00, .data[3] = 0x10, .data[4] = 0x3C, .data[5] = 0x77,
1640 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1641 { .channel = 120, .freq = 5600, .data[0] = 0x00, .data[1] = 0x00,
1642 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1643 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1644 { .channel = 124, .freq = 5620, .data[0] = 0x00, .data[1] = 0x00,
1645 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1646 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1647 { .channel = 128, .freq = 5640, .data[0] = 0x00, .data[1] = 0x00,
1648 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1649 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1650 { .channel = 132, .freq = 5660, .data[0] = 0x00, .data[1] = 0x00,
1651 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1652 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1653 { .channel = 136, .freq = 5680, .data[0] = 0x00, .data[1] = 0x00,
1654 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1655 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1656 { .channel = 140, .freq = 5700, .data[0] = 0x00, .data[1] = 0x00,
1657 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1658 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1659 { .channel = 149, .freq = 5745, .data[0] = 0x00, .data[1] = 0x00,
1660 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1661 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1662 { .channel = 153, .freq = 5765, .data[0] = 0x00, .data[1] = 0x00,
1663 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1664 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1665 { .channel = 157, .freq = 5785, .data[0] = 0x00, .data[1] = 0x00,
1666 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1667 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1668 { .channel = 161, .freq = 5805, .data[0] = 0x00, .data[1] = 0x00,
1669 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1670 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1671 { .channel = 165, .freq = 5825, .data[0] = 0x00, .data[1] = 0x00,
1672 .data[2] = 0x00, .data[3] = 0x00, .data[4] = 0x3C, .data[5] = 0x77,
1673 .data[6] = 0x37, .data[7] = 0xFF, .data[8] = 0x88, },
1674 { .channel = 184, .freq = 4920, .data[0] = 0x55, .data[1] = 0x77,
1675 .data[2] = 0x90, .data[3] = 0xF7, .data[4] = 0x3C, .data[5] = 0x77,
1676 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1677 { .channel = 188, .freq = 4940, .data[0] = 0x44, .data[1] = 0x77,
1678 .data[2] = 0x80, .data[3] = 0xE7, .data[4] = 0x3C, .data[5] = 0x77,
1679 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1680 { .channel = 192, .freq = 4960, .data[0] = 0x44, .data[1] = 0x66,
1681 .data[2] = 0x80, .data[3] = 0xE7, .data[4] = 0x3C, .data[5] = 0x77,
1682 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1683 { .channel = 196, .freq = 4980, .data[0] = 0x33, .data[1] = 0x66,
1684 .data[2] = 0x70, .data[3] = 0xC7, .data[4] = 0x3C, .data[5] = 0x77,
1685 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1686 { .channel = 200, .freq = 5000, .data[0] = 0x22, .data[1] = 0x55,
1687 .data[2] = 0x60, .data[3] = 0xD7, .data[4] = 0x3C, .data[5] = 0x77,
1688 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1689 { .channel = 204, .freq = 5020, .data[0] = 0x22, .data[1] = 0x55,
1690 .data[2] = 0x60, .data[3] = 0xC7, .data[4] = 0x3C, .data[5] = 0x77,
1691 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1692 { .channel = 208, .freq = 5040, .data[0] = 0x22, .data[1] = 0x44,
1693 .data[2] = 0x50, .data[3] = 0xC7, .data[4] = 0x3C, .data[5] = 0x77,
1694 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0xFF, },
1695 { .channel = 212, .freq = 5060, .data[0] = 0x11, .data[1] = 0x44,
1696 .data[2] = 0x50, .data[3] = 0xA5, .data[4] = 0x3C, .data[5] = 0x77,
1697 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1698 { .channel = 216, .freq = 5080, .data[0] = 0x00, .data[1] = 0x44,
1699 .data[2] = 0x40, .data[3] = 0xB6, .data[4] = 0x3C, .data[5] = 0x77,
1700 .data[6] = 0x35, .data[7] = 0xFF, .data[8] = 0x88, },
1703 static const struct b206x_channel b2063_chantbl[] = {
1704 { .channel = 1, .freq = 2412, .data[0] = 0x6F, .data[1] = 0x3C,
1705 .data[2] = 0x3C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1706 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1707 .data[10] = 0x80, .data[11] = 0x70, },
1708 { .channel = 2, .freq = 2417, .data[0] = 0x6F, .data[1] = 0x3C,
1709 .data[2] = 0x3C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1710 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1711 .data[10] = 0x80, .data[11] = 0x70, },
1712 { .channel = 3, .freq = 2422, .data[0] = 0x6F, .data[1] = 0x3C,
1713 .data[2] = 0x3C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1714 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1715 .data[10] = 0x80, .data[11] = 0x70, },
1716 { .channel = 4, .freq = 2427, .data[0] = 0x6F, .data[1] = 0x2C,
1717 .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1718 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1719 .data[10] = 0x80, .data[11] = 0x70, },
1720 { .channel = 5, .freq = 2432, .data[0] = 0x6F, .data[1] = 0x2C,
1721 .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1722 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1723 .data[10] = 0x80, .data[11] = 0x70, },
1724 { .channel = 6, .freq = 2437, .data[0] = 0x6F, .data[1] = 0x2C,
1725 .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1726 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1727 .data[10] = 0x80, .data[11] = 0x70, },
1728 { .channel = 7, .freq = 2442, .data[0] = 0x6F, .data[1] = 0x2C,
1729 .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1730 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1731 .data[10] = 0x80, .data[11] = 0x70, },
1732 { .channel = 8, .freq = 2447, .data[0] = 0x6F, .data[1] = 0x2C,
1733 .data[2] = 0x2C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1734 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1735 .data[10] = 0x80, .data[11] = 0x70, },
1736 { .channel = 9, .freq = 2452, .data[0] = 0x6F, .data[1] = 0x1C,
1737 .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1738 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1739 .data[10] = 0x80, .data[11] = 0x70, },
1740 { .channel = 10, .freq = 2457, .data[0] = 0x6F, .data[1] = 0x1C,
1741 .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1742 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1743 .data[10] = 0x80, .data[11] = 0x70, },
1744 { .channel = 11, .freq = 2462, .data[0] = 0x6E, .data[1] = 0x1C,
1745 .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1746 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1747 .data[10] = 0x80, .data[11] = 0x70, },
1748 { .channel = 12, .freq = 2467, .data[0] = 0x6E, .data[1] = 0x1C,
1749 .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1750 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1751 .data[10] = 0x80, .data[11] = 0x70, },
1752 { .channel = 13, .freq = 2472, .data[0] = 0x6E, .data[1] = 0x1C,
1753 .data[2] = 0x1C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1754 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1755 .data[10] = 0x80, .data[11] = 0x70, },
1756 { .channel = 14, .freq = 2484, .data[0] = 0x6E, .data[1] = 0x0C,
1757 .data[2] = 0x0C, .data[3] = 0x04, .data[4] = 0x05, .data[5] = 0x05,
1758 .data[6] = 0x05, .data[7] = 0x05, .data[8] = 0x77, .data[9] = 0x80,
1759 .data[10] = 0x80, .data[11] = 0x70, },
1760 { .channel = 34, .freq = 5170, .data[0] = 0x6A, .data[1] = 0x0C,
1761 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x02, .data[5] = 0x05,
1762 .data[6] = 0x0D, .data[7] = 0x0D, .data[8] = 0x77, .data[9] = 0x80,
1763 .data[10] = 0x20, .data[11] = 0x00, },
1764 { .channel = 36, .freq = 5180, .data[0] = 0x6A, .data[1] = 0x0C,
1765 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x01, .data[5] = 0x05,
1766 .data[6] = 0x0D, .data[7] = 0x0C, .data[8] = 0x77, .data[9] = 0x80,
1767 .data[10] = 0x20, .data[11] = 0x00, },
1768 { .channel = 38, .freq = 5190, .data[0] = 0x6A, .data[1] = 0x0C,
1769 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x01, .data[5] = 0x04,
1770 .data[6] = 0x0C, .data[7] = 0x0C, .data[8] = 0x77, .data[9] = 0x80,
1771 .data[10] = 0x20, .data[11] = 0x00, },
1772 { .channel = 40, .freq = 5200, .data[0] = 0x69, .data[1] = 0x0C,
1773 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x01, .data[5] = 0x04,
1774 .data[6] = 0x0C, .data[7] = 0x0C, .data[8] = 0x77, .data[9] = 0x70,
1775 .data[10] = 0x20, .data[11] = 0x00, },
1776 { .channel = 42, .freq = 5210, .data[0] = 0x69, .data[1] = 0x0C,
1777 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x01, .data[5] = 0x04,
1778 .data[6] = 0x0B, .data[7] = 0x0C, .data[8] = 0x77, .data[9] = 0x70,
1779 .data[10] = 0x20, .data[11] = 0x00, },
1780 { .channel = 44, .freq = 5220, .data[0] = 0x69, .data[1] = 0x0C,
1781 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x04,
1782 .data[6] = 0x0B, .data[7] = 0x0B, .data[8] = 0x77, .data[9] = 0x60,
1783 .data[10] = 0x20, .data[11] = 0x00, },
1784 { .channel = 46, .freq = 5230, .data[0] = 0x69, .data[1] = 0x0C,
1785 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x03,
1786 .data[6] = 0x0A, .data[7] = 0x0B, .data[8] = 0x77, .data[9] = 0x60,
1787 .data[10] = 0x20, .data[11] = 0x00, },
1788 { .channel = 48, .freq = 5240, .data[0] = 0x69, .data[1] = 0x0C,
1789 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x03,
1790 .data[6] = 0x0A, .data[7] = 0x0A, .data[8] = 0x77, .data[9] = 0x60,
1791 .data[10] = 0x20, .data[11] = 0x00, },
1792 { .channel = 52, .freq = 5260, .data[0] = 0x68, .data[1] = 0x0C,
1793 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x02,
1794 .data[6] = 0x09, .data[7] = 0x09, .data[8] = 0x77, .data[9] = 0x60,
1795 .data[10] = 0x20, .data[11] = 0x00, },
1796 { .channel = 56, .freq = 5280, .data[0] = 0x68, .data[1] = 0x0C,
1797 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x01,
1798 .data[6] = 0x08, .data[7] = 0x08, .data[8] = 0x77, .data[9] = 0x50,
1799 .data[10] = 0x10, .data[11] = 0x00, },
1800 { .channel = 60, .freq = 5300, .data[0] = 0x68, .data[1] = 0x0C,
1801 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x01,
1802 .data[6] = 0x08, .data[7] = 0x08, .data[8] = 0x77, .data[9] = 0x50,
1803 .data[10] = 0x10, .data[11] = 0x00, },
1804 { .channel = 64, .freq = 5320, .data[0] = 0x67, .data[1] = 0x0C,
1805 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1806 .data[6] = 0x08, .data[7] = 0x08, .data[8] = 0x77, .data[9] = 0x50,
1807 .data[10] = 0x10, .data[11] = 0x00, },
1808 { .channel = 100, .freq = 5500, .data[0] = 0x64, .data[1] = 0x0C,
1809 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1810 .data[6] = 0x02, .data[7] = 0x01, .data[8] = 0x77, .data[9] = 0x20,
1811 .data[10] = 0x00, .data[11] = 0x00, },
1812 { .channel = 104, .freq = 5520, .data[0] = 0x64, .data[1] = 0x0C,
1813 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1814 .data[6] = 0x01, .data[7] = 0x01, .data[8] = 0x77, .data[9] = 0x20,
1815 .data[10] = 0x00, .data[11] = 0x00, },
1816 { .channel = 108, .freq = 5540, .data[0] = 0x63, .data[1] = 0x0C,
1817 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1818 .data[6] = 0x01, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x10,
1819 .data[10] = 0x00, .data[11] = 0x00, },
1820 { .channel = 112, .freq = 5560, .data[0] = 0x63, .data[1] = 0x0C,
1821 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1822 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x10,
1823 .data[10] = 0x00, .data[11] = 0x00, },
1824 { .channel = 116, .freq = 5580, .data[0] = 0x62, .data[1] = 0x0C,
1825 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1826 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x10,
1827 .data[10] = 0x00, .data[11] = 0x00, },
1828 { .channel = 120, .freq = 5600, .data[0] = 0x62, .data[1] = 0x0C,
1829 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1830 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1831 .data[10] = 0x00, .data[11] = 0x00, },
1832 { .channel = 124, .freq = 5620, .data[0] = 0x62, .data[1] = 0x0C,
1833 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1834 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1835 .data[10] = 0x00, .data[11] = 0x00, },
1836 { .channel = 128, .freq = 5640, .data[0] = 0x61, .data[1] = 0x0C,
1837 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1838 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1839 .data[10] = 0x00, .data[11] = 0x00, },
1840 { .channel = 132, .freq = 5660, .data[0] = 0x61, .data[1] = 0x0C,
1841 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1842 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1843 .data[10] = 0x00, .data[11] = 0x00, },
1844 { .channel = 136, .freq = 5680, .data[0] = 0x61, .data[1] = 0x0C,
1845 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1846 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1847 .data[10] = 0x00, .data[11] = 0x00, },
1848 { .channel = 140, .freq = 5700, .data[0] = 0x60, .data[1] = 0x0C,
1849 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1850 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1851 .data[10] = 0x00, .data[11] = 0x00, },
1852 { .channel = 149, .freq = 5745, .data[0] = 0x60, .data[1] = 0x0C,
1853 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1854 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1855 .data[10] = 0x00, .data[11] = 0x00, },
1856 { .channel = 153, .freq = 5765, .data[0] = 0x60, .data[1] = 0x0C,
1857 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1858 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1859 .data[10] = 0x00, .data[11] = 0x00, },
1860 { .channel = 157, .freq = 5785, .data[0] = 0x60, .data[1] = 0x0C,
1861 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1862 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1863 .data[10] = 0x00, .data[11] = 0x00, },
1864 { .channel = 161, .freq = 5805, .data[0] = 0x60, .data[1] = 0x0C,
1865 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1866 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1867 .data[10] = 0x00, .data[11] = 0x00, },
1868 { .channel = 165, .freq = 5825, .data[0] = 0x60, .data[1] = 0x0C,
1869 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x00, .data[5] = 0x00,
1870 .data[6] = 0x00, .data[7] = 0x00, .data[8] = 0x77, .data[9] = 0x00,
1871 .data[10] = 0x00, .data[11] = 0x00, },
1872 { .channel = 184, .freq = 4920, .data[0] = 0x6E, .data[1] = 0x0C,
1873 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x09, .data[5] = 0x0E,
1874 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xC0,
1875 .data[10] = 0x50, .data[11] = 0x00, },
1876 { .channel = 188, .freq = 4940, .data[0] = 0x6E, .data[1] = 0x0C,
1877 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x09, .data[5] = 0x0D,
1878 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xB0,
1879 .data[10] = 0x50, .data[11] = 0x00, },
1880 { .channel = 192, .freq = 4960, .data[0] = 0x6E, .data[1] = 0x0C,
1881 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x08, .data[5] = 0x0C,
1882 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xB0,
1883 .data[10] = 0x50, .data[11] = 0x00, },
1884 { .channel = 196, .freq = 4980, .data[0] = 0x6D, .data[1] = 0x0C,
1885 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x08, .data[5] = 0x0C,
1886 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xA0,
1887 .data[10] = 0x40, .data[11] = 0x00, },
1888 { .channel = 200, .freq = 5000, .data[0] = 0x6D, .data[1] = 0x0C,
1889 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x08, .data[5] = 0x0B,
1890 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xA0,
1891 .data[10] = 0x40, .data[11] = 0x00, },
1892 { .channel = 204, .freq = 5020, .data[0] = 0x6D, .data[1] = 0x0C,
1893 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x08, .data[5] = 0x0A,
1894 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0xA0,
1895 .data[10] = 0x40, .data[11] = 0x00, },
1896 { .channel = 208, .freq = 5040, .data[0] = 0x6C, .data[1] = 0x0C,
1897 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x07, .data[5] = 0x09,
1898 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0x90,
1899 .data[10] = 0x40, .data[11] = 0x00, },
1900 { .channel = 212, .freq = 5060, .data[0] = 0x6C, .data[1] = 0x0C,
1901 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x06, .data[5] = 0x08,
1902 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0x90,
1903 .data[10] = 0x40, .data[11] = 0x00, },
1904 { .channel = 216, .freq = 5080, .data[0] = 0x6C, .data[1] = 0x0C,
1905 .data[2] = 0x0C, .data[3] = 0x00, .data[4] = 0x05, .data[5] = 0x08,
1906 .data[6] = 0x0F, .data[7] = 0x0F, .data[8] = 0x77, .data[9] = 0x90,
1907 .data[10] = 0x40, .data[11] = 0x00, },
1910 static void lpphy_b2062_reset_pll_bias(struct b43_wldev *dev)
1912 struct ssb_bus *bus = dev->dev->bus;
1914 b43_radio_write(dev, B2062_S_RFPLL_CTL2, 0xFF);
1916 if (bus->chip_id == 0x5354) {
1917 b43_radio_write(dev, B2062_N_COMM1, 4);
1918 b43_radio_write(dev, B2062_S_RFPLL_CTL2, 4);
1920 b43_radio_write(dev, B2062_S_RFPLL_CTL2, 0);
1925 static void lpphy_b2062_vco_calib(struct b43_wldev *dev)
1927 b43_radio_write(dev, B2062_S_RFPLL_CTL21, 0x42);
1928 b43_radio_write(dev, B2062_S_RFPLL_CTL21, 0x62);
1932 static int lpphy_b2062_tune(struct b43_wldev *dev,
1933 unsigned int channel)
1935 struct b43_phy_lp *lpphy = dev->phy.lp;
1936 struct ssb_bus *bus = dev->dev->bus;
1937 const struct b206x_channel *chandata = NULL;
1938 u32 crystal_freq = bus->chipco.pmu.crystalfreq * 1000;
1939 u32 tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7, tmp8, tmp9;
1942 for (i = 0; i < ARRAY_SIZE(b2062_chantbl); i++) {
1943 if (b2062_chantbl[i].channel == channel) {
1944 chandata = &b2062_chantbl[i];
1949 if (B43_WARN_ON(!chandata))
1952 b43_radio_set(dev, B2062_S_RFPLL_CTL14, 0x04);
1953 b43_radio_write(dev, B2062_N_LGENA_TUNE0, chandata->data[0]);
1954 b43_radio_write(dev, B2062_N_LGENA_TUNE2, chandata->data[1]);
1955 b43_radio_write(dev, B2062_N_LGENA_TUNE3, chandata->data[2]);
1956 b43_radio_write(dev, B2062_N_TX_TUNE, chandata->data[3]);
1957 b43_radio_write(dev, B2062_S_LGENG_CTL1, chandata->data[4]);
1958 b43_radio_write(dev, B2062_N_LGENA_CTL5, chandata->data[5]);
1959 b43_radio_write(dev, B2062_N_LGENA_CTL6, chandata->data[6]);
1960 b43_radio_write(dev, B2062_N_TX_PGA, chandata->data[7]);
1961 b43_radio_write(dev, B2062_N_TX_PAD, chandata->data[8]);
1963 tmp1 = crystal_freq / 1000;
1964 tmp2 = lpphy->pdiv * 1000;
1965 b43_radio_write(dev, B2062_S_RFPLL_CTL33, 0xCC);
1966 b43_radio_write(dev, B2062_S_RFPLL_CTL34, 0x07);
1967 lpphy_b2062_reset_pll_bias(dev);
1968 tmp3 = tmp2 * channel2freq_lp(channel);
1969 if (channel2freq_lp(channel) < 4000)
1974 b43_radio_write(dev, B2062_S_RFPLL_CTL26, tmp6);
1975 tmp5 = tmp7 * 0x100;
1978 b43_radio_write(dev, B2062_S_RFPLL_CTL27, tmp6);
1979 tmp5 = tmp7 * 0x100;
1982 b43_radio_write(dev, B2062_S_RFPLL_CTL28, tmp6);
1983 tmp5 = tmp7 * 0x100;
1986 b43_radio_write(dev, B2062_S_RFPLL_CTL29, tmp6 + ((2 * tmp7) / tmp4));
1987 tmp8 = b43_radio_read(dev, B2062_S_RFPLL_CTL19);
1988 tmp9 = ((2 * tmp3 * (tmp8 + 1)) + (3 * tmp1)) / (6 * tmp1);
1989 b43_radio_write(dev, B2062_S_RFPLL_CTL23, (tmp9 >> 8) + 16);
1990 b43_radio_write(dev, B2062_S_RFPLL_CTL24, tmp9 & 0xFF);
1992 lpphy_b2062_vco_calib(dev);
1993 if (b43_radio_read(dev, B2062_S_RFPLL_CTL3) & 0x10) {
1994 b43_radio_write(dev, B2062_S_RFPLL_CTL33, 0xFC);
1995 b43_radio_write(dev, B2062_S_RFPLL_CTL34, 0);
1996 lpphy_b2062_reset_pll_bias(dev);
1997 lpphy_b2062_vco_calib(dev);
1998 if (b43_radio_read(dev, B2062_S_RFPLL_CTL3) & 0x10)
2002 b43_radio_mask(dev, B2062_S_RFPLL_CTL14, ~0x04);
2007 /* This was previously called lpphy_japan_filter */
2008 static void lpphy_set_analog_filter(struct b43_wldev *dev, int channel)
2010 struct b43_phy_lp *lpphy = dev->phy.lp;
2011 u16 tmp = (channel == 14); //SPEC FIXME check japanwidefilter!
2013 if (dev->phy.rev < 2) { //SPEC FIXME Isn't this rev0/1-specific?
2014 b43_phy_maskset(dev, B43_LPPHY_LP_PHY_CTL, 0xFCFF, tmp << 9);
2015 if ((dev->phy.rev == 1) && (lpphy->rc_cap))
2016 lpphy_set_rc_cap(dev);
2018 b43_radio_write(dev, B2063_TX_BB_SP3, 0x3F);
2022 static void lpphy_b2063_vco_calib(struct b43_wldev *dev)
2026 b43_radio_mask(dev, B2063_PLL_SP1, ~0x40);
2027 tmp = b43_radio_read(dev, B2063_PLL_JTAG_CALNRST) & 0xF8;
2028 b43_radio_write(dev, B2063_PLL_JTAG_CALNRST, tmp);
2030 b43_radio_write(dev, B2063_PLL_JTAG_CALNRST, tmp | 0x4);
2032 b43_radio_write(dev, B2063_PLL_JTAG_CALNRST, tmp | 0x6);
2034 b43_radio_write(dev, B2063_PLL_JTAG_CALNRST, tmp | 0x7);
2036 b43_radio_set(dev, B2063_PLL_SP1, 0x40);
2039 static int lpphy_b2063_tune(struct b43_wldev *dev,
2040 unsigned int channel)
2042 struct ssb_bus *bus = dev->dev->bus;
2044 static const struct b206x_channel *chandata = NULL;
2045 u32 crystal_freq = bus->chipco.pmu.crystalfreq * 1000;
2046 u32 freqref, vco_freq, val1, val2, val3, timeout, timeoutref, count;
2047 u16 old_comm15, scale;
2048 u32 tmp1, tmp2, tmp3, tmp4, tmp5, tmp6;
2049 int i, div = (crystal_freq <= 26000000 ? 1 : 2);
2051 for (i = 0; i < ARRAY_SIZE(b2063_chantbl); i++) {
2052 if (b2063_chantbl[i].channel == channel) {
2053 chandata = &b2063_chantbl[i];
2058 if (B43_WARN_ON(!chandata))
2061 b43_radio_write(dev, B2063_LOGEN_VCOBUF1, chandata->data[0]);
2062 b43_radio_write(dev, B2063_LOGEN_MIXER2, chandata->data[1]);
2063 b43_radio_write(dev, B2063_LOGEN_BUF2, chandata->data[2]);
2064 b43_radio_write(dev, B2063_LOGEN_RCCR1, chandata->data[3]);
2065 b43_radio_write(dev, B2063_A_RX_1ST3, chandata->data[4]);
2066 b43_radio_write(dev, B2063_A_RX_2ND1, chandata->data[5]);
2067 b43_radio_write(dev, B2063_A_RX_2ND4, chandata->data[6]);
2068 b43_radio_write(dev, B2063_A_RX_2ND7, chandata->data[7]);
2069 b43_radio_write(dev, B2063_A_RX_PS6, chandata->data[8]);
2070 b43_radio_write(dev, B2063_TX_RF_CTL2, chandata->data[9]);
2071 b43_radio_write(dev, B2063_TX_RF_CTL5, chandata->data[10]);
2072 b43_radio_write(dev, B2063_PA_CTL11, chandata->data[11]);
2074 old_comm15 = b43_radio_read(dev, B2063_COMM15);
2075 b43_radio_set(dev, B2063_COMM15, 0x1E);
2077 if (chandata->freq > 4000) /* spec says 2484, but 4000 is safer */
2078 vco_freq = chandata->freq << 1;
2080 vco_freq = chandata->freq << 2;
2082 freqref = crystal_freq * 3;
2083 val1 = lpphy_qdiv_roundup(crystal_freq, 1000000, 16);
2084 val2 = lpphy_qdiv_roundup(crystal_freq, 1000000 * div, 16);
2085 val3 = lpphy_qdiv_roundup(vco_freq, 3, 16);
2086 timeout = ((((8 * crystal_freq) / (div * 5000000)) + 1) >> 1) - 1;
2087 b43_radio_write(dev, B2063_PLL_JTAG_PLL_VCO_CALIB3, 0x2);
2088 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_VCO_CALIB6,
2089 0xFFF8, timeout >> 2);
2090 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_VCO_CALIB7,
2091 0xFF9F,timeout << 5);
2093 timeoutref = ((((8 * crystal_freq) / (div * (timeout + 1))) +
2094 999999) / 1000000) + 1;
2095 b43_radio_write(dev, B2063_PLL_JTAG_PLL_VCO_CALIB5, timeoutref);
2097 count = lpphy_qdiv_roundup(val3, val2 + 16, 16);
2098 count *= (timeout + 1) * (timeoutref + 1);
2100 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_VCO_CALIB7,
2102 b43_radio_write(dev, B2063_PLL_JTAG_PLL_VCO_CALIB8, count & 0xFF);
2104 tmp1 = ((val3 * 62500) / freqref) << 4;
2105 tmp2 = ((val3 * 62500) % freqref) << 4;
2106 while (tmp2 >= freqref) {
2110 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_SG1, 0xFFE0, tmp1 >> 4);
2111 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_SG2, 0xFE0F, tmp1 << 4);
2112 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_SG2, 0xFFF0, tmp1 >> 16);
2113 b43_radio_write(dev, B2063_PLL_JTAG_PLL_SG3, (tmp2 >> 8) & 0xFF);
2114 b43_radio_write(dev, B2063_PLL_JTAG_PLL_SG4, tmp2 & 0xFF);
2116 b43_radio_write(dev, B2063_PLL_JTAG_PLL_LF1, 0xB9);
2117 b43_radio_write(dev, B2063_PLL_JTAG_PLL_LF2, 0x88);
2118 b43_radio_write(dev, B2063_PLL_JTAG_PLL_LF3, 0x28);
2119 b43_radio_write(dev, B2063_PLL_JTAG_PLL_LF4, 0x63);
2121 tmp3 = ((41 * (val3 - 3000)) /1200) + 27;
2122 tmp4 = lpphy_qdiv_roundup(132000 * tmp1, 8451, 16);
2124 if ((tmp4 + tmp3 - 1) / tmp3 > 60) {
2126 tmp5 = ((tmp4 + tmp3) / (tmp3 << 1)) - 8;
2129 tmp5 = ((tmp4 + (tmp3 >> 1)) / tmp3) - 8;
2131 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_CP2, 0xFFC0, tmp5);
2132 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_CP2, 0xFFBF, scale << 6);
2134 tmp6 = lpphy_qdiv_roundup(100 * val1, val3, 16);
2135 tmp6 *= (tmp5 * 8) * (scale + 1);
2139 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_CP3, 0xFFE0, tmp6);
2140 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_CP3, 0xFFDF, scale << 5);
2142 b43_radio_maskset(dev, B2063_PLL_JTAG_PLL_XTAL_12, 0xFFFB, 0x4);
2143 if (crystal_freq > 26000000)
2144 b43_radio_set(dev, B2063_PLL_JTAG_PLL_XTAL_12, 0x2);
2146 b43_radio_mask(dev, B2063_PLL_JTAG_PLL_XTAL_12, 0xFD);
2149 b43_radio_set(dev, B2063_PLL_JTAG_PLL_VCO1, 0x2);
2151 b43_radio_mask(dev, B2063_PLL_JTAG_PLL_VCO1, 0xFD);
2153 b43_radio_set(dev, B2063_PLL_SP2, 0x3);
2155 b43_radio_mask(dev, B2063_PLL_SP2, 0xFFFC);
2156 lpphy_b2063_vco_calib(dev);
2157 b43_radio_write(dev, B2063_COMM15, old_comm15);
2162 static int b43_lpphy_op_switch_channel(struct b43_wldev *dev,
2163 unsigned int new_channel)
2165 struct b43_phy_lp *lpphy = dev->phy.lp;
2168 if (dev->phy.radio_ver == 0x2063) {
2169 err = lpphy_b2063_tune(dev, new_channel);
2173 err = lpphy_b2062_tune(dev, new_channel);
2176 lpphy_set_analog_filter(dev, new_channel);
2177 lpphy_adjust_gain_table(dev, channel2freq_lp(new_channel));
2180 lpphy->channel = new_channel;
2181 b43_write16(dev, B43_MMIO_CHANNEL, new_channel);
2186 static int b43_lpphy_op_init(struct b43_wldev *dev)
2190 lpphy_read_band_sprom(dev); //FIXME should this be in prepare_structs?
2191 lpphy_baseband_init(dev);
2192 lpphy_radio_init(dev);
2193 lpphy_calibrate_rc(dev);
2194 err = b43_lpphy_op_switch_channel(dev, 7);
2196 b43dbg(dev->wl, "Switch to channel 7 failed, error = %d.\n",
2199 lpphy_tx_pctl_init(dev);
2200 lpphy_calibration(dev);
2206 static void b43_lpphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna)
2211 static void b43_lpphy_op_adjust_txpower(struct b43_wldev *dev)
2216 static enum b43_txpwr_result b43_lpphy_op_recalc_txpower(struct b43_wldev *dev,
2220 return B43_TXPWR_RES_DONE;
2223 const struct b43_phy_operations b43_phyops_lp = {
2224 .allocate = b43_lpphy_op_allocate,
2225 .free = b43_lpphy_op_free,
2226 .prepare_structs = b43_lpphy_op_prepare_structs,
2227 .init = b43_lpphy_op_init,
2228 .phy_read = b43_lpphy_op_read,
2229 .phy_write = b43_lpphy_op_write,
2230 .phy_maskset = b43_lpphy_op_maskset,
2231 .radio_read = b43_lpphy_op_radio_read,
2232 .radio_write = b43_lpphy_op_radio_write,
2233 .software_rfkill = b43_lpphy_op_software_rfkill,
2234 .switch_analog = b43_phyop_switch_analog_generic,
2235 .switch_channel = b43_lpphy_op_switch_channel,
2236 .get_default_chan = b43_lpphy_op_get_default_chan,
2237 .set_rx_antenna = b43_lpphy_op_set_rx_antenna,
2238 .recalc_txpower = b43_lpphy_op_recalc_txpower,
2239 .adjust_txpower = b43_lpphy_op_adjust_txpower,