SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/b43/phy_g.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4   IEEE 802.11g PHY driver
   5
   6   Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
   7   Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
   8   Copyright (c) 2005-2008 Michael Buesch <mb@bu3sch.de>
   9   Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
  10   Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>
  11
  12   This program is free software; you can redistribute it and/or modify
  13   it under the terms of the GNU General Public License as published by
  14   the Free Software Foundation; either version 2 of the License, or
  15   (at your option) any later version.
  16
  17   This program is distributed in the hope that it will be useful,
  18   but WITHOUT ANY WARRANTY; without even the implied warranty of
  19   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20   GNU General Public License for more details.
  21
  22   You should have received a copy of the GNU General Public License
  23   along with this program; see the file COPYING.  If not, write to
  24   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  25   Boston, MA 02110-1301, USA.
  26
  27 */
  28
  29 #include "b43.h"
  30 #include "phy_g.h"
  31 #include "phy_common.h"
  32 #include "lo.h"
  33 #include "main.h"
  34
  35 #include <linux/bitrev.h>
  36
  37
  38 static const s8 b43_tssi2dbm_g_table[] = {
  39         77, 77, 77, 76,
  40         76, 76, 75, 75,
  41         74, 74, 73, 73,
  42         73, 72, 72, 71,
  43         71, 70, 70, 69,
  44         68, 68, 67, 67,
  45         66, 65, 65, 64,
  46         63, 63, 62, 61,
  47         60, 59, 58, 57,
  48         56, 55, 54, 53,
  49         52, 50, 49, 47,
  50         45, 43, 40, 37,
  51         33, 28, 22, 14,
  52         5, -7, -20, -20,
  53         -20, -20, -20, -20,
  54         -20, -20, -20, -20,
  55 };
  56
  57 static const u8 b43_radio_channel_codes_bg[] = {
  58         12, 17, 22, 27,
  59         32, 37, 42, 47,
  60         52, 57, 62, 67,
  61         72, 84,
  62 };
  63
  64
  65 static void b43_calc_nrssi_threshold(struct b43_wldev *dev);
  66
  67
  68 #define bitrev4(tmp) (bitrev8(tmp) >> 4)
  69
  70
  71 /* Get the freq, as it has to be written to the device. */
  72 static inline u16 channel2freq_bg(u8 channel)
  73 {
  74         B43_WARN_ON(!(channel >= 1 && channel <= 14));
  75
  76         return b43_radio_channel_codes_bg[channel - 1];
  77 }
  78
  79 static void generate_rfatt_list(struct b43_wldev *dev,
  80                                 struct b43_rfatt_list *list)
  81 {
  82         struct b43_phy *phy = &dev->phy;
  83
  84         /* APHY.rev < 5 || GPHY.rev < 6 */
  85         static const struct b43_rfatt rfatt_0[] = {
  86                 {.att = 3,.with_padmix = 0,},
  87                 {.att = 1,.with_padmix = 0,},
  88                 {.att = 5,.with_padmix = 0,},
  89                 {.att = 7,.with_padmix = 0,},
  90                 {.att = 9,.with_padmix = 0,},
  91                 {.att = 2,.with_padmix = 0,},
  92                 {.att = 0,.with_padmix = 0,},
  93                 {.att = 4,.with_padmix = 0,},
  94                 {.att = 6,.with_padmix = 0,},
  95                 {.att = 8,.with_padmix = 0,},
  96                 {.att = 1,.with_padmix = 1,},
  97                 {.att = 2,.with_padmix = 1,},
  98                 {.att = 3,.with_padmix = 1,},
  99                 {.att = 4,.with_padmix = 1,},
 100         };
 101         /* Radio.rev == 8 && Radio.version == 0x2050 */
 102         static const struct b43_rfatt rfatt_1[] = {
 103                 {.att = 2,.with_padmix = 1,},
 104                 {.att = 4,.with_padmix = 1,},
 105                 {.att = 6,.with_padmix = 1,},
 106                 {.att = 8,.with_padmix = 1,},
 107                 {.att = 10,.with_padmix = 1,},
 108                 {.att = 12,.with_padmix = 1,},
 109                 {.att = 14,.with_padmix = 1,},
 110         };
 111         /* Otherwise */
 112         static const struct b43_rfatt rfatt_2[] = {
 113                 {.att = 0,.with_padmix = 1,},
 114                 {.att = 2,.with_padmix = 1,},
 115                 {.att = 4,.with_padmix = 1,},
 116                 {.att = 6,.with_padmix = 1,},
 117                 {.att = 8,.with_padmix = 1,},
 118                 {.att = 9,.with_padmix = 1,},
 119                 {.att = 9,.with_padmix = 1,},
 120         };
 121
 122         if (!b43_has_hardware_pctl(dev)) {
 123                 /* Software pctl */
 124                 list->list = rfatt_0;
 125                 list->len = ARRAY_SIZE(rfatt_0);
 126                 list->min_val = 0;
 127                 list->max_val = 9;
 128                 return;
 129         }
 130         if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
 131                 /* Hardware pctl */
 132                 list->list = rfatt_1;
 133                 list->len = ARRAY_SIZE(rfatt_1);
 134                 list->min_val = 0;
 135                 list->max_val = 14;
 136                 return;
 137         }
 138         /* Hardware pctl */
 139         list->list = rfatt_2;
 140         list->len = ARRAY_SIZE(rfatt_2);
 141         list->min_val = 0;
 142         list->max_val = 9;
 143 }
 144
 145 static void generate_bbatt_list(struct b43_wldev *dev,
 146                                 struct b43_bbatt_list *list)
 147 {
 148         static const struct b43_bbatt bbatt_0[] = {
 149                 {.att = 0,},
 150                 {.att = 1,},
 151                 {.att = 2,},
 152                 {.att = 3,},
 153                 {.att = 4,},
 154                 {.att = 5,},
 155                 {.att = 6,},
 156                 {.att = 7,},
 157                 {.att = 8,},
 158         };
 159
 160         list->list = bbatt_0;
 161         list->len = ARRAY_SIZE(bbatt_0);
 162         list->min_val = 0;
 163         list->max_val = 8;
 164 }
 165
 166 static void b43_shm_clear_tssi(struct b43_wldev *dev)
 167 {
 168         b43_shm_write16(dev, B43_SHM_SHARED, 0x0058, 0x7F7F);
 169         b43_shm_write16(dev, B43_SHM_SHARED, 0x005a, 0x7F7F);
 170         b43_shm_write16(dev, B43_SHM_SHARED, 0x0070, 0x7F7F);
 171         b43_shm_write16(dev, B43_SHM_SHARED, 0x0072, 0x7F7F);
 172 }
 173
 174 /* Synthetic PU workaround */
 175 static void b43_synth_pu_workaround(struct b43_wldev *dev, u8 channel)
 176 {
 177         struct b43_phy *phy = &dev->phy;
 178
 179         might_sleep();
 180
 181         if (phy->radio_ver != 0x2050 || phy->radio_rev >= 6) {
 182                 /* We do not need the workaround. */
 183                 return;
 184         }
 185
 186         if (channel <= 10) {
 187                 b43_write16(dev, B43_MMIO_CHANNEL,
 188                             channel2freq_bg(channel + 4));
 189         } else {
 190                 b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(1));
 191         }
 192         msleep(1);
 193         b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(channel));
 194 }
 195
 196 /* Set the baseband attenuation value on chip. */
 197 void b43_gphy_set_baseband_attenuation(struct b43_wldev *dev,
 198                                        u16 baseband_attenuation)
 199 {
 200         struct b43_phy *phy = &dev->phy;
 201
 202         if (phy->analog == 0) {
 203                 b43_write16(dev, B43_MMIO_PHY0, (b43_read16(dev, B43_MMIO_PHY0)
 204                                                  & 0xFFF0) |
 205                             baseband_attenuation);
 206         } else if (phy->analog > 1) {
 207                 b43_phy_maskset(dev, B43_PHY_DACCTL, 0xFFC3, (baseband_attenuation << 2));
 208         } else {
 209                 b43_phy_maskset(dev, B43_PHY_DACCTL, 0xFF87, (baseband_attenuation << 3));
 210         }
 211 }
 212
 213 /* Adjust the transmission power output (G-PHY) */
 214 static void b43_set_txpower_g(struct b43_wldev *dev,
 215                               const struct b43_bbatt *bbatt,
 216                               const struct b43_rfatt *rfatt, u8 tx_control)
 217 {
 218         struct b43_phy *phy = &dev->phy;
 219         struct b43_phy_g *gphy = phy->g;
 220         struct b43_txpower_lo_control *lo = gphy->lo_control;
 221         u16 bb, rf;
 222         u16 tx_bias, tx_magn;
 223
 224         bb = bbatt->att;
 225         rf = rfatt->att;
 226         tx_bias = lo->tx_bias;
 227         tx_magn = lo->tx_magn;
 228         if (unlikely(tx_bias == 0xFF))
 229                 tx_bias = 0;
 230
 231         /* Save the values for later. Use memmove, because it's valid
 232          * to pass &gphy->rfatt as rfatt pointer argument. Same for bbatt. */
 233         gphy->tx_control = tx_control;
 234         memmove(&gphy->rfatt, rfatt, sizeof(*rfatt));
 235         gphy->rfatt.with_padmix = !!(tx_control & B43_TXCTL_TXMIX);
 236         memmove(&gphy->bbatt, bbatt, sizeof(*bbatt));
 237
 238         if (b43_debug(dev, B43_DBG_XMITPOWER)) {
 239                 b43dbg(dev->wl, "Tuning TX-power to bbatt(%u), "
 240                        "rfatt(%u), tx_control(0x%02X), "
 241                        "tx_bias(0x%02X), tx_magn(0x%02X)\n",
 242                        bb, rf, tx_control, tx_bias, tx_magn);
 243         }
 244
 245         b43_gphy_set_baseband_attenuation(dev, bb);
 246         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_RFATT, rf);
 247         if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
 248                 b43_radio_write16(dev, 0x43,
 249                                   (rf & 0x000F) | (tx_control & 0x0070));
 250         } else {
 251                 b43_radio_write16(dev, 0x43, (b43_radio_read16(dev, 0x43)
 252                                               & 0xFFF0) | (rf & 0x000F));
 253                 b43_radio_write16(dev, 0x52, (b43_radio_read16(dev, 0x52)
 254                                               & ~0x0070) | (tx_control &
 255                                                             0x0070));
 256         }
 257         if (has_tx_magnification(phy)) {
 258                 b43_radio_write16(dev, 0x52, tx_magn | tx_bias);
 259         } else {
 260                 b43_radio_write16(dev, 0x52, (b43_radio_read16(dev, 0x52)
 261                                               & 0xFFF0) | (tx_bias & 0x000F));
 262         }
 263         b43_lo_g_adjust(dev);
 264 }
 265
 266 /* GPHY_TSSI_Power_Lookup_Table_Init */
 267 static void b43_gphy_tssi_power_lt_init(struct b43_wldev *dev)
 268 {
 269         struct b43_phy_g *gphy = dev->phy.g;
 270         int i;
 271         u16 value;
 272
 273         for (i = 0; i < 32; i++)
 274                 b43_ofdmtab_write16(dev, 0x3C20, i, gphy->tssi2dbm[i]);
 275         for (i = 32; i < 64; i++)
 276                 b43_ofdmtab_write16(dev, 0x3C00, i - 32, gphy->tssi2dbm[i]);
 277         for (i = 0; i < 64; i += 2) {
 278                 value = (u16) gphy->tssi2dbm[i];
 279                 value |= ((u16) gphy->tssi2dbm[i + 1]) << 8;
 280                 b43_phy_write(dev, 0x380 + (i / 2), value);
 281         }
 282 }
 283
 284 /* GPHY_Gain_Lookup_Table_Init */
 285 static void b43_gphy_gain_lt_init(struct b43_wldev *dev)
 286 {
 287         struct b43_phy *phy = &dev->phy;
 288         struct b43_phy_g *gphy = phy->g;
 289         struct b43_txpower_lo_control *lo = gphy->lo_control;
 290         u16 nr_written = 0;
 291         u16 tmp;
 292         u8 rf, bb;
 293
 294         for (rf = 0; rf < lo->rfatt_list.len; rf++) {
 295                 for (bb = 0; bb < lo->bbatt_list.len; bb++) {
 296                         if (nr_written >= 0x40)
 297                                 return;
 298                         tmp = lo->bbatt_list.list[bb].att;
 299                         tmp <<= 8;
 300                         if (phy->radio_rev == 8)
 301                                 tmp |= 0x50;
 302                         else
 303                                 tmp |= 0x40;
 304                         tmp |= lo->rfatt_list.list[rf].att;
 305                         b43_phy_write(dev, 0x3C0 + nr_written, tmp);
 306                         nr_written++;
 307                 }
 308         }
 309 }
 310
 311 static void b43_set_all_gains(struct b43_wldev *dev,
 312                               s16 first, s16 second, s16 third)
 313 {
 314         struct b43_phy *phy = &dev->phy;
 315         u16 i;
 316         u16 start = 0x08, end = 0x18;
 317         u16 tmp;
 318         u16 table;
 319
 320         if (phy->rev <= 1) {
 321                 start = 0x10;
 322                 end = 0x20;
 323         }
 324
 325         table = B43_OFDMTAB_GAINX;
 326         if (phy->rev <= 1)
 327                 table = B43_OFDMTAB_GAINX_R1;
 328         for (i = 0; i < 4; i++)
 329                 b43_ofdmtab_write16(dev, table, i, first);
 330
 331         for (i = start; i < end; i++)
 332                 b43_ofdmtab_write16(dev, table, i, second);
 333
 334         if (third != -1) {
 335                 tmp = ((u16) third << 14) | ((u16) third << 6);
 336                 b43_phy_maskset(dev, 0x04A0, 0xBFBF, tmp);
 337                 b43_phy_maskset(dev, 0x04A1, 0xBFBF, tmp);
 338                 b43_phy_maskset(dev, 0x04A2, 0xBFBF, tmp);
 339         }
 340         b43_dummy_transmission(dev);
 341 }
 342
 343 static void b43_set_original_gains(struct b43_wldev *dev)
 344 {
 345         struct b43_phy *phy = &dev->phy;
 346         u16 i, tmp;
 347         u16 table;
 348         u16 start = 0x0008, end = 0x0018;
 349
 350         if (phy->rev <= 1) {
 351                 start = 0x0010;
 352                 end = 0x0020;
 353         }
 354
 355         table = B43_OFDMTAB_GAINX;
 356         if (phy->rev <= 1)
 357                 table = B43_OFDMTAB_GAINX_R1;
 358         for (i = 0; i < 4; i++) {
 359                 tmp = (i & 0xFFFC);
 360                 tmp |= (i & 0x0001) << 1;
 361                 tmp |= (i & 0x0002) >> 1;
 362
 363                 b43_ofdmtab_write16(dev, table, i, tmp);
 364         }
 365
 366         for (i = start; i < end; i++)
 367                 b43_ofdmtab_write16(dev, table, i, i - start);
 368
 369         b43_phy_maskset(dev, 0x04A0, 0xBFBF, 0x4040);
 370         b43_phy_maskset(dev, 0x04A1, 0xBFBF, 0x4040);
 371         b43_phy_maskset(dev, 0x04A2, 0xBFBF, 0x4000);
 372         b43_dummy_transmission(dev);
 373 }
 374
 375 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
 376 static void b43_nrssi_hw_write(struct b43_wldev *dev, u16 offset, s16 val)
 377 {
 378         b43_phy_write(dev, B43_PHY_NRSSILT_CTRL, offset);
 379         b43_phy_write(dev, B43_PHY_NRSSILT_DATA, (u16) val);
 380 }
 381
 382 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
 383 static s16 b43_nrssi_hw_read(struct b43_wldev *dev, u16 offset)
 384 {
 385         u16 val;
 386
 387         b43_phy_write(dev, B43_PHY_NRSSILT_CTRL, offset);
 388         val = b43_phy_read(dev, B43_PHY_NRSSILT_DATA);
 389
 390         return (s16) val;
 391 }
 392
 393 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
 394 static void b43_nrssi_hw_update(struct b43_wldev *dev, u16 val)
 395 {
 396         u16 i;
 397         s16 tmp;
 398
 399         for (i = 0; i < 64; i++) {
 400                 tmp = b43_nrssi_hw_read(dev, i);
 401                 tmp -= val;
 402                 tmp = clamp_val(tmp, -32, 31);
 403                 b43_nrssi_hw_write(dev, i, tmp);
 404         }
 405 }
 406
 407 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
 408 static void b43_nrssi_mem_update(struct b43_wldev *dev)
 409 {
 410         struct b43_phy_g *gphy = dev->phy.g;
 411         s16 i, delta;
 412         s32 tmp;
 413
 414         delta = 0x1F - gphy->nrssi[0];
 415         for (i = 0; i < 64; i++) {
 416                 tmp = (i - delta) * gphy->nrssislope;
 417                 tmp /= 0x10000;
 418                 tmp += 0x3A;
 419                 tmp = clamp_val(tmp, 0, 0x3F);
 420                 gphy->nrssi_lt[i] = tmp;
 421         }
 422 }
 423
 424 static void b43_calc_nrssi_offset(struct b43_wldev *dev)
 425 {
 426         struct b43_phy *phy = &dev->phy;
 427         u16 backup[20] = { 0 };
 428         s16 v47F;
 429         u16 i;
 430         u16 saved = 0xFFFF;
 431
 432         backup[0] = b43_phy_read(dev, 0x0001);
 433         backup[1] = b43_phy_read(dev, 0x0811);
 434         backup[2] = b43_phy_read(dev, 0x0812);
 435         if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
 436                 backup[3] = b43_phy_read(dev, 0x0814);
 437                 backup[4] = b43_phy_read(dev, 0x0815);
 438         }
 439         backup[5] = b43_phy_read(dev, 0x005A);
 440         backup[6] = b43_phy_read(dev, 0x0059);
 441         backup[7] = b43_phy_read(dev, 0x0058);
 442         backup[8] = b43_phy_read(dev, 0x000A);
 443         backup[9] = b43_phy_read(dev, 0x0003);
 444         backup[10] = b43_radio_read16(dev, 0x007A);
 445         backup[11] = b43_radio_read16(dev, 0x0043);
 446
 447         b43_phy_mask(dev, 0x0429, 0x7FFF);
 448         b43_phy_maskset(dev, 0x0001, 0x3FFF, 0x4000);
 449         b43_phy_set(dev, 0x0811, 0x000C);
 450         b43_phy_maskset(dev, 0x0812, 0xFFF3, 0x0004);
 451         b43_phy_mask(dev, 0x0802, ~(0x1 | 0x2));
 452         if (phy->rev >= 6) {
 453                 backup[12] = b43_phy_read(dev, 0x002E);
 454                 backup[13] = b43_phy_read(dev, 0x002F);
 455                 backup[14] = b43_phy_read(dev, 0x080F);
 456                 backup[15] = b43_phy_read(dev, 0x0810);
 457                 backup[16] = b43_phy_read(dev, 0x0801);
 458                 backup[17] = b43_phy_read(dev, 0x0060);
 459                 backup[18] = b43_phy_read(dev, 0x0014);
 460                 backup[19] = b43_phy_read(dev, 0x0478);
 461
 462                 b43_phy_write(dev, 0x002E, 0);
 463                 b43_phy_write(dev, 0x002F, 0);
 464                 b43_phy_write(dev, 0x080F, 0);
 465                 b43_phy_write(dev, 0x0810, 0);
 466                 b43_phy_set(dev, 0x0478, 0x0100);
 467                 b43_phy_set(dev, 0x0801, 0x0040);
 468                 b43_phy_set(dev, 0x0060, 0x0040);
 469                 b43_phy_set(dev, 0x0014, 0x0200);
 470         }
 471         b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A) | 0x0070);
 472         b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A) | 0x0080);
 473         udelay(30);
 474
 475         v47F = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
 476         if (v47F >= 0x20)
 477                 v47F -= 0x40;
 478         if (v47F == 31) {
 479                 for (i = 7; i >= 4; i--) {
 480                         b43_radio_write16(dev, 0x007B, i);
 481                         udelay(20);
 482                         v47F =
 483                             (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
 484                         if (v47F >= 0x20)
 485                                 v47F -= 0x40;
 486                         if (v47F < 31 && saved == 0xFFFF)
 487                                 saved = i;
 488                 }
 489                 if (saved == 0xFFFF)
 490                         saved = 4;
 491         } else {
 492                 b43_radio_write16(dev, 0x007A,
 493                                   b43_radio_read16(dev, 0x007A) & 0x007F);
 494                 if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
 495                         b43_phy_set(dev, 0x0814, 0x0001);
 496                         b43_phy_mask(dev, 0x0815, 0xFFFE);
 497                 }
 498                 b43_phy_set(dev, 0x0811, 0x000C);
 499                 b43_phy_set(dev, 0x0812, 0x000C);
 500                 b43_phy_set(dev, 0x0811, 0x0030);
 501                 b43_phy_set(dev, 0x0812, 0x0030);
 502                 b43_phy_write(dev, 0x005A, 0x0480);
 503                 b43_phy_write(dev, 0x0059, 0x0810);
 504                 b43_phy_write(dev, 0x0058, 0x000D);
 505                 if (phy->rev == 0) {
 506                         b43_phy_write(dev, 0x0003, 0x0122);
 507                 } else {
 508                         b43_phy_set(dev, 0x000A, 0x2000);
 509                 }
 510                 if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
 511                         b43_phy_set(dev, 0x0814, 0x0004);
 512                         b43_phy_mask(dev, 0x0815, 0xFFFB);
 513                 }
 514                 b43_phy_maskset(dev, 0x0003, 0xFF9F, 0x0040);
 515                 b43_radio_write16(dev, 0x007A,
 516                                   b43_radio_read16(dev, 0x007A) | 0x000F);
 517                 b43_set_all_gains(dev, 3, 0, 1);
 518                 b43_radio_write16(dev, 0x0043, (b43_radio_read16(dev, 0x0043)
 519                                                 & 0x00F0) | 0x000F);
 520                 udelay(30);
 521                 v47F = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
 522                 if (v47F >= 0x20)
 523                         v47F -= 0x40;
 524                 if (v47F == -32) {
 525                         for (i = 0; i < 4; i++) {
 526                                 b43_radio_write16(dev, 0x007B, i);
 527                                 udelay(20);
 528                                 v47F =
 529                                     (s16) ((b43_phy_read(dev, 0x047F) >> 8) &
 530                                            0x003F);
 531                                 if (v47F >= 0x20)
 532                                         v47F -= 0x40;
 533                                 if (v47F > -31 && saved == 0xFFFF)
 534                                         saved = i;
 535                         }
 536                         if (saved == 0xFFFF)
 537                                 saved = 3;
 538                 } else
 539                         saved = 0;
 540         }
 541         b43_radio_write16(dev, 0x007B, saved);
 542
 543         if (phy->rev >= 6) {
 544                 b43_phy_write(dev, 0x002E, backup[12]);
 545                 b43_phy_write(dev, 0x002F, backup[13]);
 546                 b43_phy_write(dev, 0x080F, backup[14]);
 547                 b43_phy_write(dev, 0x0810, backup[15]);
 548         }
 549         if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
 550                 b43_phy_write(dev, 0x0814, backup[3]);
 551                 b43_phy_write(dev, 0x0815, backup[4]);
 552         }
 553         b43_phy_write(dev, 0x005A, backup[5]);
 554         b43_phy_write(dev, 0x0059, backup[6]);
 555         b43_phy_write(dev, 0x0058, backup[7]);
 556         b43_phy_write(dev, 0x000A, backup[8]);
 557         b43_phy_write(dev, 0x0003, backup[9]);
 558         b43_radio_write16(dev, 0x0043, backup[11]);
 559         b43_radio_write16(dev, 0x007A, backup[10]);
 560         b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) | 0x1 | 0x2);
 561         b43_phy_set(dev, 0x0429, 0x8000);
 562         b43_set_original_gains(dev);
 563         if (phy->rev >= 6) {
 564                 b43_phy_write(dev, 0x0801, backup[16]);
 565                 b43_phy_write(dev, 0x0060, backup[17]);
 566                 b43_phy_write(dev, 0x0014, backup[18]);
 567                 b43_phy_write(dev, 0x0478, backup[19]);
 568         }
 569         b43_phy_write(dev, 0x0001, backup[0]);
 570         b43_phy_write(dev, 0x0812, backup[2]);
 571         b43_phy_write(dev, 0x0811, backup[1]);
 572 }
 573
 574 static void b43_calc_nrssi_slope(struct b43_wldev *dev)
 575 {
 576         struct b43_phy *phy = &dev->phy;
 577         struct b43_phy_g *gphy = phy->g;
 578         u16 backup[18] = { 0 };
 579         u16 tmp;
 580         s16 nrssi0, nrssi1;
 581
 582         B43_WARN_ON(phy->type != B43_PHYTYPE_G);
 583
 584         if (phy->radio_rev >= 9)
 585                 return;
 586         if (phy->radio_rev == 8)
 587                 b43_calc_nrssi_offset(dev);
 588
 589         b43_phy_mask(dev, B43_PHY_G_CRS, 0x7FFF);
 590         b43_phy_mask(dev, 0x0802, 0xFFFC);
 591         backup[7] = b43_read16(dev, 0x03E2);
 592         b43_write16(dev, 0x03E2, b43_read16(dev, 0x03E2) | 0x8000);
 593         backup[0] = b43_radio_read16(dev, 0x007A);
 594         backup[1] = b43_radio_read16(dev, 0x0052);
 595         backup[2] = b43_radio_read16(dev, 0x0043);
 596         backup[3] = b43_phy_read(dev, 0x0015);
 597         backup[4] = b43_phy_read(dev, 0x005A);
 598         backup[5] = b43_phy_read(dev, 0x0059);
 599         backup[6] = b43_phy_read(dev, 0x0058);
 600         backup[8] = b43_read16(dev, 0x03E6);
 601         backup[9] = b43_read16(dev, B43_MMIO_CHANNEL_EXT);
 602         if (phy->rev >= 3) {
 603                 backup[10] = b43_phy_read(dev, 0x002E);
 604                 backup[11] = b43_phy_read(dev, 0x002F);
 605                 backup[12] = b43_phy_read(dev, 0x080F);
 606                 backup[13] = b43_phy_read(dev, B43_PHY_G_LO_CONTROL);
 607                 backup[14] = b43_phy_read(dev, 0x0801);
 608                 backup[15] = b43_phy_read(dev, 0x0060);
 609                 backup[16] = b43_phy_read(dev, 0x0014);
 610                 backup[17] = b43_phy_read(dev, 0x0478);
 611                 b43_phy_write(dev, 0x002E, 0);
 612                 b43_phy_write(dev, B43_PHY_G_LO_CONTROL, 0);
 613                 switch (phy->rev) {
 614                 case 4:
 615                 case 6:
 616                 case 7:
 617                         b43_phy_set(dev, 0x0478, 0x0100);
 618                         b43_phy_set(dev, 0x0801, 0x0040);
 619                         break;
 620                 case 3:
 621                 case 5:
 622                         b43_phy_mask(dev, 0x0801, 0xFFBF);
 623                         break;
 624                 }
 625                 b43_phy_set(dev, 0x0060, 0x0040);
 626                 b43_phy_set(dev, 0x0014, 0x0200);
 627         }
 628         b43_radio_write16(dev, 0x007A,
 629                           b43_radio_read16(dev, 0x007A) | 0x0070);
 630         b43_set_all_gains(dev, 0, 8, 0);
 631         b43_radio_write16(dev, 0x007A,
 632                           b43_radio_read16(dev, 0x007A) & 0x00F7);
 633         if (phy->rev >= 2) {
 634                 b43_phy_maskset(dev, 0x0811, 0xFFCF, 0x0030);
 635                 b43_phy_maskset(dev, 0x0812, 0xFFCF, 0x0010);
 636         }
 637         b43_radio_write16(dev, 0x007A,
 638                           b43_radio_read16(dev, 0x007A) | 0x0080);
 639         udelay(20);
 640
 641         nrssi0 = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
 642         if (nrssi0 >= 0x0020)
 643                 nrssi0 -= 0x0040;
 644
 645         b43_radio_write16(dev, 0x007A,
 646                           b43_radio_read16(dev, 0x007A) & 0x007F);
 647         if (phy->rev >= 2) {
 648                 b43_phy_maskset(dev, 0x0003, 0xFF9F, 0x0040);
 649         }
 650
 651         b43_write16(dev, B43_MMIO_CHANNEL_EXT,
 652                     b43_read16(dev, B43_MMIO_CHANNEL_EXT)
 653                     | 0x2000);
 654         b43_radio_write16(dev, 0x007A,
 655                           b43_radio_read16(dev, 0x007A) | 0x000F);
 656         b43_phy_write(dev, 0x0015, 0xF330);
 657         if (phy->rev >= 2) {
 658                 b43_phy_maskset(dev, 0x0812, 0xFFCF, 0x0020);
 659                 b43_phy_maskset(dev, 0x0811, 0xFFCF, 0x0020);
 660         }
 661
 662         b43_set_all_gains(dev, 3, 0, 1);
 663         if (phy->radio_rev == 8) {
 664                 b43_radio_write16(dev, 0x0043, 0x001F);
 665         } else {
 666                 tmp = b43_radio_read16(dev, 0x0052) & 0xFF0F;
 667                 b43_radio_write16(dev, 0x0052, tmp | 0x0060);
 668                 tmp = b43_radio_read16(dev, 0x0043) & 0xFFF0;
 669                 b43_radio_write16(dev, 0x0043, tmp | 0x0009);
 670         }
 671         b43_phy_write(dev, 0x005A, 0x0480);
 672         b43_phy_write(dev, 0x0059, 0x0810);
 673         b43_phy_write(dev, 0x0058, 0x000D);
 674         udelay(20);
 675         nrssi1 = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
 676         if (nrssi1 >= 0x0020)
 677                 nrssi1 -= 0x0040;
 678         if (nrssi0 == nrssi1)
 679                 gphy->nrssislope = 0x00010000;
 680         else
 681                 gphy->nrssislope = 0x00400000 / (nrssi0 - nrssi1);
 682         if (nrssi0 >= -4) {
 683                 gphy->nrssi[0] = nrssi1;
 684                 gphy->nrssi[1] = nrssi0;
 685         }
 686         if (phy->rev >= 3) {
 687                 b43_phy_write(dev, 0x002E, backup[10]);
 688                 b43_phy_write(dev, 0x002F, backup[11]);
 689                 b43_phy_write(dev, 0x080F, backup[12]);
 690                 b43_phy_write(dev, B43_PHY_G_LO_CONTROL, backup[13]);
 691         }
 692         if (phy->rev >= 2) {
 693                 b43_phy_mask(dev, 0x0812, 0xFFCF);
 694                 b43_phy_mask(dev, 0x0811, 0xFFCF);
 695         }
 696
 697         b43_radio_write16(dev, 0x007A, backup[0]);
 698         b43_radio_write16(dev, 0x0052, backup[1]);
 699         b43_radio_write16(dev, 0x0043, backup[2]);
 700         b43_write16(dev, 0x03E2, backup[7]);
 701         b43_write16(dev, 0x03E6, backup[8]);
 702         b43_write16(dev, B43_MMIO_CHANNEL_EXT, backup[9]);
 703         b43_phy_write(dev, 0x0015, backup[3]);
 704         b43_phy_write(dev, 0x005A, backup[4]);
 705         b43_phy_write(dev, 0x0059, backup[5]);
 706         b43_phy_write(dev, 0x0058, backup[6]);
 707         b43_synth_pu_workaround(dev, phy->channel);
 708         b43_phy_set(dev, 0x0802, (0x0001 | 0x0002));
 709         b43_set_original_gains(dev);
 710         b43_phy_set(dev, B43_PHY_G_CRS, 0x8000);
 711         if (phy->rev >= 3) {
 712                 b43_phy_write(dev, 0x0801, backup[14]);
 713                 b43_phy_write(dev, 0x0060, backup[15]);
 714                 b43_phy_write(dev, 0x0014, backup[16]);
 715                 b43_phy_write(dev, 0x0478, backup[17]);
 716         }
 717         b43_nrssi_mem_update(dev);
 718         b43_calc_nrssi_threshold(dev);
 719 }
 720
 721 static void b43_calc_nrssi_threshold(struct b43_wldev *dev)
 722 {
 723         struct b43_phy *phy = &dev->phy;
 724         struct b43_phy_g *gphy = phy->g;
 725         s32 a, b;
 726         s16 tmp16;
 727         u16 tmp_u16;
 728
 729         B43_WARN_ON(phy->type != B43_PHYTYPE_G);
 730
 731         if (!phy->gmode ||
 732             !(dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI)) {
 733                 tmp16 = b43_nrssi_hw_read(dev, 0x20);
 734                 if (tmp16 >= 0x20)
 735                         tmp16 -= 0x40;
 736                 if (tmp16 < 3) {
 737                         b43_phy_maskset(dev, 0x048A, 0xF000, 0x09EB);
 738                 } else {
 739                         b43_phy_maskset(dev, 0x048A, 0xF000, 0x0AED);
 740                 }
 741         } else {
 742                 if (gphy->interfmode == B43_INTERFMODE_NONWLAN) {
 743                         a = 0xE;
 744                         b = 0xA;
 745                 } else if (!gphy->aci_wlan_automatic && gphy->aci_enable) {
 746                         a = 0x13;
 747                         b = 0x12;
 748                 } else {
 749                         a = 0xE;
 750                         b = 0x11;
 751                 }
 752
 753                 a = a * (gphy->nrssi[1] - gphy->nrssi[0]);
 754                 a += (gphy->nrssi[0] << 6);
 755                 if (a < 32)
 756                         a += 31;
 757                 else
 758                         a += 32;
 759                 a = a >> 6;
 760                 a = clamp_val(a, -31, 31);
 761
 762                 b = b * (gphy->nrssi[1] - gphy->nrssi[0]);
 763                 b += (gphy->nrssi[0] << 6);
 764                 if (b < 32)
 765                         b += 31;
 766                 else
 767                         b += 32;
 768                 b = b >> 6;
 769                 b = clamp_val(b, -31, 31);
 770
 771                 tmp_u16 = b43_phy_read(dev, 0x048A) & 0xF000;
 772                 tmp_u16 |= ((u32) b & 0x0000003F);
 773                 tmp_u16 |= (((u32) a & 0x0000003F) << 6);
 774                 b43_phy_write(dev, 0x048A, tmp_u16);
 775         }
 776 }
 777
 778 /* Stack implementation to save/restore values from the
 779  * interference mitigation code.
 780  * It is save to restore values in random order.
 781  */
 782 static void _stack_save(u32 * _stackptr, size_t * stackidx,
 783                         u8 id, u16 offset, u16 value)
 784 {
 785         u32 *stackptr = &(_stackptr[*stackidx]);
 786
 787         B43_WARN_ON(offset & 0xF000);
 788         B43_WARN_ON(id & 0xF0);
 789         *stackptr = offset;
 790         *stackptr |= ((u32) id) << 12;
 791         *stackptr |= ((u32) value) << 16;
 792         (*stackidx)++;
 793         B43_WARN_ON(*stackidx >= B43_INTERFSTACK_SIZE);
 794 }
 795
 796 static u16 _stack_restore(u32 * stackptr, u8 id, u16 offset)
 797 {
 798         size_t i;
 799
 800         B43_WARN_ON(offset & 0xF000);
 801         B43_WARN_ON(id & 0xF0);
 802         for (i = 0; i < B43_INTERFSTACK_SIZE; i++, stackptr++) {
 803                 if ((*stackptr & 0x00000FFF) != offset)
 804                         continue;
 805                 if (((*stackptr & 0x0000F000) >> 12) != id)
 806                         continue;
 807                 return ((*stackptr & 0xFFFF0000) >> 16);
 808         }
 809         B43_WARN_ON(1);
 810
 811         return 0;
 812 }
 813
 814 #define phy_stacksave(offset)                                   \
 815         do {                                                    \
 816                 _stack_save(stack, &stackidx, 0x1, (offset),    \
 817                             b43_phy_read(dev, (offset)));       \
 818         } while (0)
 819 #define phy_stackrestore(offset)                                \
 820         do {                                                    \
 821                 b43_phy_write(dev, (offset),            \
 822                                   _stack_restore(stack, 0x1,    \
 823                                                  (offset)));    \
 824         } while (0)
 825 #define radio_stacksave(offset)                                         \
 826         do {                                                            \
 827                 _stack_save(stack, &stackidx, 0x2, (offset),            \
 828                             b43_radio_read16(dev, (offset)));   \
 829         } while (0)
 830 #define radio_stackrestore(offset)                                      \
 831         do {                                                            \
 832                 b43_radio_write16(dev, (offset),                        \
 833                                       _stack_restore(stack, 0x2,        \
 834                                                      (offset)));        \
 835         } while (0)
 836 #define ofdmtab_stacksave(table, offset)                        \
 837         do {                                                    \
 838                 _stack_save(stack, &stackidx, 0x3, (offset)|(table),    \
 839                             b43_ofdmtab_read16(dev, (table), (offset)));        \
 840         } while (0)
 841 #define ofdmtab_stackrestore(table, offset)                     \
 842         do {                                                    \
 843                 b43_ofdmtab_write16(dev, (table),       (offset),       \
 844                                   _stack_restore(stack, 0x3,    \
 845                                                  (offset)|(table)));    \
 846         } while (0)
 847
 848 static void
 849 b43_radio_interference_mitigation_enable(struct b43_wldev *dev, int mode)
 850 {
 851         struct b43_phy *phy = &dev->phy;
 852         struct b43_phy_g *gphy = phy->g;
 853         u16 tmp, flipped;
 854         size_t stackidx = 0;
 855         u32 *stack = gphy->interfstack;
 856
 857         switch (mode) {
 858         case B43_INTERFMODE_NONWLAN:
 859                 if (phy->rev != 1) {
 860                         b43_phy_set(dev, 0x042B, 0x0800);
 861                         b43_phy_mask(dev, B43_PHY_G_CRS, ~0x4000);
 862                         break;
 863                 }
 864                 radio_stacksave(0x0078);
 865                 tmp = (b43_radio_read16(dev, 0x0078) & 0x001E);
 866                 B43_WARN_ON(tmp > 15);
 867                 flipped = bitrev4(tmp);
 868                 if (flipped < 10 && flipped >= 8)
 869                         flipped = 7;
 870                 else if (flipped >= 10)
 871                         flipped -= 3;
 872                 flipped = (bitrev4(flipped) << 1) | 0x0020;
 873                 b43_radio_write16(dev, 0x0078, flipped);
 874
 875                 b43_calc_nrssi_threshold(dev);
 876
 877                 phy_stacksave(0x0406);
 878                 b43_phy_write(dev, 0x0406, 0x7E28);
 879
 880                 b43_phy_set(dev, 0x042B, 0x0800);
 881                 b43_phy_set(dev, B43_PHY_RADIO_BITFIELD, 0x1000);
 882
 883                 phy_stacksave(0x04A0);
 884                 b43_phy_maskset(dev, 0x04A0, 0xC0C0, 0x0008);
 885                 phy_stacksave(0x04A1);
 886                 b43_phy_maskset(dev, 0x04A1, 0xC0C0, 0x0605);
 887                 phy_stacksave(0x04A2);
 888                 b43_phy_maskset(dev, 0x04A2, 0xC0C0, 0x0204);
 889                 phy_stacksave(0x04A8);
 890                 b43_phy_maskset(dev, 0x04A8, 0xC0C0, 0x0803);
 891                 phy_stacksave(0x04AB);
 892                 b43_phy_maskset(dev, 0x04AB, 0xC0C0, 0x0605);
 893
 894                 phy_stacksave(0x04A7);
 895                 b43_phy_write(dev, 0x04A7, 0x0002);
 896                 phy_stacksave(0x04A3);
 897                 b43_phy_write(dev, 0x04A3, 0x287A);
 898                 phy_stacksave(0x04A9);
 899                 b43_phy_write(dev, 0x04A9, 0x2027);
 900                 phy_stacksave(0x0493);
 901                 b43_phy_write(dev, 0x0493, 0x32F5);
 902                 phy_stacksave(0x04AA);
 903                 b43_phy_write(dev, 0x04AA, 0x2027);
 904                 phy_stacksave(0x04AC);
 905                 b43_phy_write(dev, 0x04AC, 0x32F5);
 906                 break;
 907         case B43_INTERFMODE_MANUALWLAN:
 908                 if (b43_phy_read(dev, 0x0033) & 0x0800)
 909                         break;
 910
 911                 gphy->aci_enable = 1;
 912
 913                 phy_stacksave(B43_PHY_RADIO_BITFIELD);
 914                 phy_stacksave(B43_PHY_G_CRS);
 915                 if (phy->rev < 2) {
 916                         phy_stacksave(0x0406);
 917                 } else {
 918                         phy_stacksave(0x04C0);
 919                         phy_stacksave(0x04C1);
 920                 }
 921                 phy_stacksave(0x0033);
 922                 phy_stacksave(0x04A7);
 923                 phy_stacksave(0x04A3);
 924                 phy_stacksave(0x04A9);
 925                 phy_stacksave(0x04AA);
 926                 phy_stacksave(0x04AC);
 927                 phy_stacksave(0x0493);
 928                 phy_stacksave(0x04A1);
 929                 phy_stacksave(0x04A0);
 930                 phy_stacksave(0x04A2);
 931                 phy_stacksave(0x048A);
 932                 phy_stacksave(0x04A8);
 933                 phy_stacksave(0x04AB);
 934                 if (phy->rev == 2) {
 935                         phy_stacksave(0x04AD);
 936                         phy_stacksave(0x04AE);
 937                 } else if (phy->rev >= 3) {
 938                         phy_stacksave(0x04AD);
 939                         phy_stacksave(0x0415);
 940                         phy_stacksave(0x0416);
 941                         phy_stacksave(0x0417);
 942                         ofdmtab_stacksave(0x1A00, 0x2);
 943                         ofdmtab_stacksave(0x1A00, 0x3);
 944                 }
 945                 phy_stacksave(0x042B);
 946                 phy_stacksave(0x048C);
 947
 948                 b43_phy_mask(dev, B43_PHY_RADIO_BITFIELD, ~0x1000);
 949                 b43_phy_maskset(dev, B43_PHY_G_CRS, 0xFFFC, 0x0002);
 950
 951                 b43_phy_write(dev, 0x0033, 0x0800);
 952                 b43_phy_write(dev, 0x04A3, 0x2027);
 953                 b43_phy_write(dev, 0x04A9, 0x1CA8);
 954                 b43_phy_write(dev, 0x0493, 0x287A);
 955                 b43_phy_write(dev, 0x04AA, 0x1CA8);
 956                 b43_phy_write(dev, 0x04AC, 0x287A);
 957
 958                 b43_phy_maskset(dev, 0x04A0, 0xFFC0, 0x001A);
 959                 b43_phy_write(dev, 0x04A7, 0x000D);
 960
 961                 if (phy->rev < 2) {
 962                         b43_phy_write(dev, 0x0406, 0xFF0D);
 963                 } else if (phy->rev == 2) {
 964                         b43_phy_write(dev, 0x04C0, 0xFFFF);
 965                         b43_phy_write(dev, 0x04C1, 0x00A9);
 966                 } else {
 967                         b43_phy_write(dev, 0x04C0, 0x00C1);
 968                         b43_phy_write(dev, 0x04C1, 0x0059);
 969                 }
 970
 971                 b43_phy_maskset(dev, 0x04A1, 0xC0FF, 0x1800);
 972                 b43_phy_maskset(dev, 0x04A1, 0xFFC0, 0x0015);
 973                 b43_phy_maskset(dev, 0x04A8, 0xCFFF, 0x1000);
 974                 b43_phy_maskset(dev, 0x04A8, 0xF0FF, 0x0A00);
 975                 b43_phy_maskset(dev, 0x04AB, 0xCFFF, 0x1000);
 976                 b43_phy_maskset(dev, 0x04AB, 0xF0FF, 0x0800);
 977                 b43_phy_maskset(dev, 0x04AB, 0xFFCF, 0x0010);
 978                 b43_phy_maskset(dev, 0x04AB, 0xFFF0, 0x0005);
 979                 b43_phy_maskset(dev, 0x04A8, 0xFFCF, 0x0010);
 980                 b43_phy_maskset(dev, 0x04A8, 0xFFF0, 0x0006);
 981                 b43_phy_maskset(dev, 0x04A2, 0xF0FF, 0x0800);
 982                 b43_phy_maskset(dev, 0x04A0, 0xF0FF, 0x0500);
 983                 b43_phy_maskset(dev, 0x04A2, 0xFFF0, 0x000B);
 984
 985                 if (phy->rev >= 3) {
 986                         b43_phy_mask(dev, 0x048A, ~0x8000);
 987                         b43_phy_maskset(dev, 0x0415, 0x8000, 0x36D8);
 988                         b43_phy_maskset(dev, 0x0416, 0x8000, 0x36D8);
 989                         b43_phy_maskset(dev, 0x0417, 0xFE00, 0x016D);
 990                 } else {
 991                         b43_phy_set(dev, 0x048A, 0x1000);
 992                         b43_phy_maskset(dev, 0x048A, 0x9FFF, 0x2000);
 993                         b43_hf_write(dev, b43_hf_read(dev) | B43_HF_ACIW);
 994                 }
 995                 if (phy->rev >= 2) {
 996                         b43_phy_set(dev, 0x042B, 0x0800);
 997                 }
 998                 b43_phy_maskset(dev, 0x048C, 0xF0FF, 0x0200);
 999                 if (phy->rev == 2) {
1000                         b43_phy_maskset(dev, 0x04AE, 0xFF00, 0x007F);
1001                         b43_phy_maskset(dev, 0x04AD, 0x00FF, 0x1300);
1002                 } else if (phy->rev >= 6) {
1003                         b43_ofdmtab_write16(dev, 0x1A00, 0x3, 0x007F);
1004                         b43_ofdmtab_write16(dev, 0x1A00, 0x2, 0x007F);
1005                         b43_phy_mask(dev, 0x04AD, 0x00FF);
1006                 }
1007                 b43_calc_nrssi_slope(dev);
1008                 break;
1009         default:
1010                 B43_WARN_ON(1);
1011         }
1012 }
1013
1014 static void
1015 b43_radio_interference_mitigation_disable(struct b43_wldev *dev, int mode)
1016 {
1017         struct b43_phy *phy = &dev->phy;
1018         struct b43_phy_g *gphy = phy->g;
1019         u32 *stack = gphy->interfstack;
1020
1021         switch (mode) {
1022         case B43_INTERFMODE_NONWLAN:
1023                 if (phy->rev != 1) {
1024                         b43_phy_mask(dev, 0x042B, ~0x0800);
1025                         b43_phy_set(dev, B43_PHY_G_CRS, 0x4000);
1026                         break;
1027                 }
1028                 radio_stackrestore(0x0078);
1029                 b43_calc_nrssi_threshold(dev);
1030                 phy_stackrestore(0x0406);
1031                 b43_phy_mask(dev, 0x042B, ~0x0800);
1032                 if (!dev->bad_frames_preempt) {
1033                         b43_phy_mask(dev, B43_PHY_RADIO_BITFIELD, ~(1 << 11));
1034                 }
1035                 b43_phy_set(dev, B43_PHY_G_CRS, 0x4000);
1036                 phy_stackrestore(0x04A0);
1037                 phy_stackrestore(0x04A1);
1038                 phy_stackrestore(0x04A2);
1039                 phy_stackrestore(0x04A8);
1040                 phy_stackrestore(0x04AB);
1041                 phy_stackrestore(0x04A7);
1042                 phy_stackrestore(0x04A3);
1043                 phy_stackrestore(0x04A9);
1044                 phy_stackrestore(0x0493);
1045                 phy_stackrestore(0x04AA);
1046                 phy_stackrestore(0x04AC);
1047                 break;
1048         case B43_INTERFMODE_MANUALWLAN:
1049                 if (!(b43_phy_read(dev, 0x0033) & 0x0800))
1050                         break;
1051
1052                 gphy->aci_enable = 0;
1053
1054                 phy_stackrestore(B43_PHY_RADIO_BITFIELD);
1055                 phy_stackrestore(B43_PHY_G_CRS);
1056                 phy_stackrestore(0x0033);
1057                 phy_stackrestore(0x04A3);
1058                 phy_stackrestore(0x04A9);
1059                 phy_stackrestore(0x0493);
1060                 phy_stackrestore(0x04AA);
1061                 phy_stackrestore(0x04AC);
1062                 phy_stackrestore(0x04A0);
1063                 phy_stackrestore(0x04A7);
1064                 if (phy->rev >= 2) {
1065                         phy_stackrestore(0x04C0);
1066                         phy_stackrestore(0x04C1);
1067                 } else
1068                         phy_stackrestore(0x0406);
1069                 phy_stackrestore(0x04A1);
1070                 phy_stackrestore(0x04AB);
1071                 phy_stackrestore(0x04A8);
1072                 if (phy->rev == 2) {
1073                         phy_stackrestore(0x04AD);
1074                         phy_stackrestore(0x04AE);
1075                 } else if (phy->rev >= 3) {
1076                         phy_stackrestore(0x04AD);
1077                         phy_stackrestore(0x0415);
1078                         phy_stackrestore(0x0416);
1079                         phy_stackrestore(0x0417);
1080                         ofdmtab_stackrestore(0x1A00, 0x2);
1081                         ofdmtab_stackrestore(0x1A00, 0x3);
1082                 }
1083                 phy_stackrestore(0x04A2);
1084                 phy_stackrestore(0x048A);
1085                 phy_stackrestore(0x042B);
1086                 phy_stackrestore(0x048C);
1087                 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_ACIW);
1088                 b43_calc_nrssi_slope(dev);
1089                 break;
1090         default:
1091                 B43_WARN_ON(1);
1092         }
1093 }
1094
1095 #undef phy_stacksave
1096 #undef phy_stackrestore
1097 #undef radio_stacksave
1098 #undef radio_stackrestore
1099 #undef ofdmtab_stacksave
1100 #undef ofdmtab_stackrestore
1101
1102 static u16 b43_radio_core_calibration_value(struct b43_wldev *dev)
1103 {
1104         u16 reg, index, ret;
1105
1106         static const u8 rcc_table[] = {
1107                 0x02, 0x03, 0x01, 0x0F,
1108                 0x06, 0x07, 0x05, 0x0F,
1109                 0x0A, 0x0B, 0x09, 0x0F,
1110                 0x0E, 0x0F, 0x0D, 0x0F,
1111         };
1112
1113         reg = b43_radio_read16(dev, 0x60);
1114         index = (reg & 0x001E) >> 1;
1115         ret = rcc_table[index] << 1;
1116         ret |= (reg & 0x0001);
1117         ret |= 0x0020;
1118
1119         return ret;
1120 }
1121
1122 #define LPD(L, P, D)    (((L) << 2) | ((P) << 1) | ((D) << 0))
1123 static u16 radio2050_rfover_val(struct b43_wldev *dev,
1124                                 u16 phy_register, unsigned int lpd)
1125 {
1126         struct b43_phy *phy = &dev->phy;
1127         struct b43_phy_g *gphy = phy->g;
1128         struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
1129
1130         if (!phy->gmode)
1131                 return 0;
1132
1133         if (has_loopback_gain(phy)) {
1134                 int max_lb_gain = gphy->max_lb_gain;
1135                 u16 extlna;
1136                 u16 i;
1137
1138                 if (phy->radio_rev == 8)
1139                         max_lb_gain += 0x3E;
1140                 else
1141                         max_lb_gain += 0x26;
1142                 if (max_lb_gain >= 0x46) {
1143                         extlna = 0x3000;
1144                         max_lb_gain -= 0x46;
1145                 } else if (max_lb_gain >= 0x3A) {
1146                         extlna = 0x1000;
1147                         max_lb_gain -= 0x3A;
1148                 } else if (max_lb_gain >= 0x2E) {
1149                         extlna = 0x2000;
1150                         max_lb_gain -= 0x2E;
1151                 } else {
1152                         extlna = 0;
1153                         max_lb_gain -= 0x10;
1154                 }
1155
1156                 for (i = 0; i < 16; i++) {
1157                         max_lb_gain -= (i * 6);
1158                         if (max_lb_gain < 6)
1159                                 break;
1160                 }
1161
1162                 if ((phy->rev < 7) ||
1163                     !(sprom->boardflags_lo & B43_BFL_EXTLNA)) {
1164                         if (phy_register == B43_PHY_RFOVER) {
1165                                 return 0x1B3;
1166                         } else if (phy_register == B43_PHY_RFOVERVAL) {
1167                                 extlna |= (i << 8);
1168                                 switch (lpd) {
1169                                 case LPD(0, 1, 1):
1170                                         return 0x0F92;
1171                                 case LPD(0, 0, 1):
1172                                 case LPD(1, 0, 1):
1173                                         return (0x0092 | extlna);
1174                                 case LPD(1, 0, 0):
1175                                         return (0x0093 | extlna);
1176                                 }
1177                                 B43_WARN_ON(1);
1178                         }
1179                         B43_WARN_ON(1);
1180                 } else {
1181                         if (phy_register == B43_PHY_RFOVER) {
1182                                 return 0x9B3;
1183                         } else if (phy_register == B43_PHY_RFOVERVAL) {
1184                                 if (extlna)
1185                                         extlna |= 0x8000;
1186                                 extlna |= (i << 8);
1187                                 switch (lpd) {
1188                                 case LPD(0, 1, 1):
1189                                         return 0x8F92;
1190                                 case LPD(0, 0, 1):
1191                                         return (0x8092 | extlna);
1192                                 case LPD(1, 0, 1):
1193                                         return (0x2092 | extlna);
1194                                 case LPD(1, 0, 0):
1195                                         return (0x2093 | extlna);
1196                                 }
1197                                 B43_WARN_ON(1);
1198                         }
1199                         B43_WARN_ON(1);
1200                 }
1201         } else {
1202                 if ((phy->rev < 7) ||
1203                     !(sprom->boardflags_lo & B43_BFL_EXTLNA)) {
1204                         if (phy_register == B43_PHY_RFOVER) {
1205                                 return 0x1B3;
1206                         } else if (phy_register == B43_PHY_RFOVERVAL) {
1207                                 switch (lpd) {
1208                                 case LPD(0, 1, 1):
1209                                         return 0x0FB2;
1210                                 case LPD(0, 0, 1):
1211                                         return 0x00B2;
1212                                 case LPD(1, 0, 1):
1213                                         return 0x30B2;
1214                                 case LPD(1, 0, 0):
1215                                         return 0x30B3;
1216                                 }
1217                                 B43_WARN_ON(1);
1218                         }
1219                         B43_WARN_ON(1);
1220                 } else {
1221                         if (phy_register == B43_PHY_RFOVER) {
1222                                 return 0x9B3;
1223                         } else if (phy_register == B43_PHY_RFOVERVAL) {
1224                                 switch (lpd) {
1225                                 case LPD(0, 1, 1):
1226                                         return 0x8FB2;
1227                                 case LPD(0, 0, 1):
1228                                         return 0x80B2;
1229                                 case LPD(1, 0, 1):
1230                                         return 0x20B2;
1231                                 case LPD(1, 0, 0):
1232                                         return 0x20B3;
1233                                 }
1234                                 B43_WARN_ON(1);
1235                         }
1236                         B43_WARN_ON(1);
1237                 }
1238         }
1239         return 0;
1240 }
1241
1242 struct init2050_saved_values {
1243         /* Core registers */
1244         u16 reg_3EC;
1245         u16 reg_3E6;
1246         u16 reg_3F4;
1247         /* Radio registers */
1248         u16 radio_43;
1249         u16 radio_51;
1250         u16 radio_52;
1251         /* PHY registers */
1252         u16 phy_pgactl;
1253         u16 phy_cck_5A;
1254         u16 phy_cck_59;
1255         u16 phy_cck_58;
1256         u16 phy_cck_30;
1257         u16 phy_rfover;
1258         u16 phy_rfoverval;
1259         u16 phy_analogover;
1260         u16 phy_analogoverval;
1261         u16 phy_crs0;
1262         u16 phy_classctl;
1263         u16 phy_lo_mask;
1264         u16 phy_lo_ctl;
1265         u16 phy_syncctl;
1266 };
1267
1268 static u16 b43_radio_init2050(struct b43_wldev *dev)
1269 {
1270         struct b43_phy *phy = &dev->phy;
1271         struct init2050_saved_values sav;
1272         u16 rcc;
1273         u16 radio78;
1274         u16 ret;
1275         u16 i, j;
1276         u32 tmp1 = 0, tmp2 = 0;
1277
1278         memset(&sav, 0, sizeof(sav));   /* get rid of "may be used uninitialized..." */
1279
1280         sav.radio_43 = b43_radio_read16(dev, 0x43);
1281         sav.radio_51 = b43_radio_read16(dev, 0x51);
1282         sav.radio_52 = b43_radio_read16(dev, 0x52);
1283         sav.phy_pgactl = b43_phy_read(dev, B43_PHY_PGACTL);
1284         sav.phy_cck_5A = b43_phy_read(dev, B43_PHY_CCK(0x5A));
1285         sav.phy_cck_59 = b43_phy_read(dev, B43_PHY_CCK(0x59));
1286         sav.phy_cck_58 = b43_phy_read(dev, B43_PHY_CCK(0x58));
1287
1288         if (phy->type == B43_PHYTYPE_B) {
1289                 sav.phy_cck_30 = b43_phy_read(dev, B43_PHY_CCK(0x30));
1290                 sav.reg_3EC = b43_read16(dev, 0x3EC);
1291
1292                 b43_phy_write(dev, B43_PHY_CCK(0x30), 0xFF);
1293                 b43_write16(dev, 0x3EC, 0x3F3F);
1294         } else if (phy->gmode || phy->rev >= 2) {
1295                 sav.phy_rfover = b43_phy_read(dev, B43_PHY_RFOVER);
1296                 sav.phy_rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL);
1297                 sav.phy_analogover = b43_phy_read(dev, B43_PHY_ANALOGOVER);
1298                 sav.phy_analogoverval =
1299                     b43_phy_read(dev, B43_PHY_ANALOGOVERVAL);
1300                 sav.phy_crs0 = b43_phy_read(dev, B43_PHY_CRS0);
1301                 sav.phy_classctl = b43_phy_read(dev, B43_PHY_CLASSCTL);
1302
1303                 b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0003);
1304                 b43_phy_mask(dev, B43_PHY_ANALOGOVERVAL, 0xFFFC);
1305                 b43_phy_mask(dev, B43_PHY_CRS0, 0x7FFF);
1306                 b43_phy_mask(dev, B43_PHY_CLASSCTL, 0xFFFC);
1307                 if (has_loopback_gain(phy)) {
1308                         sav.phy_lo_mask = b43_phy_read(dev, B43_PHY_LO_MASK);
1309                         sav.phy_lo_ctl = b43_phy_read(dev, B43_PHY_LO_CTL);
1310
1311                         if (phy->rev >= 3)
1312                                 b43_phy_write(dev, B43_PHY_LO_MASK, 0xC020);
1313                         else
1314                                 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8020);
1315                         b43_phy_write(dev, B43_PHY_LO_CTL, 0);
1316                 }
1317
1318                 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1319                               radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
1320                                                    LPD(0, 1, 1)));
1321                 b43_phy_write(dev, B43_PHY_RFOVER,
1322                               radio2050_rfover_val(dev, B43_PHY_RFOVER, 0));
1323         }
1324         b43_write16(dev, 0x3E2, b43_read16(dev, 0x3E2) | 0x8000);
1325
1326         sav.phy_syncctl = b43_phy_read(dev, B43_PHY_SYNCCTL);
1327         b43_phy_mask(dev, B43_PHY_SYNCCTL, 0xFF7F);
1328         sav.reg_3E6 = b43_read16(dev, 0x3E6);
1329         sav.reg_3F4 = b43_read16(dev, 0x3F4);
1330
1331         if (phy->analog == 0) {
1332                 b43_write16(dev, 0x03E6, 0x0122);
1333         } else {
1334                 if (phy->analog >= 2) {
1335                         b43_phy_maskset(dev, B43_PHY_CCK(0x03), 0xFFBF, 0x40);
1336                 }
1337                 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
1338                             (b43_read16(dev, B43_MMIO_CHANNEL_EXT) | 0x2000));
1339         }
1340
1341         rcc = b43_radio_core_calibration_value(dev);
1342
1343         if (phy->type == B43_PHYTYPE_B)
1344                 b43_radio_write16(dev, 0x78, 0x26);
1345         if (phy->gmode || phy->rev >= 2) {
1346                 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1347                               radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
1348                                                    LPD(0, 1, 1)));
1349         }
1350         b43_phy_write(dev, B43_PHY_PGACTL, 0xBFAF);
1351         b43_phy_write(dev, B43_PHY_CCK(0x2B), 0x1403);
1352         if (phy->gmode || phy->rev >= 2) {
1353                 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1354                               radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
1355                                                    LPD(0, 0, 1)));
1356         }
1357         b43_phy_write(dev, B43_PHY_PGACTL, 0xBFA0);
1358         b43_radio_write16(dev, 0x51, b43_radio_read16(dev, 0x51)
1359                           | 0x0004);
1360         if (phy->radio_rev == 8) {
1361                 b43_radio_write16(dev, 0x43, 0x1F);
1362         } else {
1363                 b43_radio_write16(dev, 0x52, 0);
1364                 b43_radio_write16(dev, 0x43, (b43_radio_read16(dev, 0x43)
1365                                               & 0xFFF0) | 0x0009);
1366         }
1367         b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
1368
1369         for (i = 0; i < 16; i++) {
1370                 b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0480);
1371                 b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810);
1372                 b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D);
1373                 if (phy->gmode || phy->rev >= 2) {
1374                         b43_phy_write(dev, B43_PHY_RFOVERVAL,
1375                                       radio2050_rfover_val(dev,
1376                                                            B43_PHY_RFOVERVAL,
1377                                                            LPD(1, 0, 1)));
1378                 }
1379                 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
1380                 udelay(10);
1381                 if (phy->gmode || phy->rev >= 2) {
1382                         b43_phy_write(dev, B43_PHY_RFOVERVAL,
1383                                       radio2050_rfover_val(dev,
1384                                                            B43_PHY_RFOVERVAL,
1385                                                            LPD(1, 0, 1)));
1386                 }
1387                 b43_phy_write(dev, B43_PHY_PGACTL, 0xEFB0);
1388                 udelay(10);
1389                 if (phy->gmode || phy->rev >= 2) {
1390                         b43_phy_write(dev, B43_PHY_RFOVERVAL,
1391                                       radio2050_rfover_val(dev,
1392                                                            B43_PHY_RFOVERVAL,
1393                                                            LPD(1, 0, 0)));
1394                 }
1395                 b43_phy_write(dev, B43_PHY_PGACTL, 0xFFF0);
1396                 udelay(20);
1397                 tmp1 += b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
1398                 b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
1399                 if (phy->gmode || phy->rev >= 2) {
1400                         b43_phy_write(dev, B43_PHY_RFOVERVAL,
1401                                       radio2050_rfover_val(dev,
1402                                                            B43_PHY_RFOVERVAL,
1403                                                            LPD(1, 0, 1)));
1404                 }
1405                 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
1406         }
1407         udelay(10);
1408
1409         b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
1410         tmp1++;
1411         tmp1 >>= 9;
1412
1413         for (i = 0; i < 16; i++) {
1414                 radio78 = (bitrev4(i) << 1) | 0x0020;
1415                 b43_radio_write16(dev, 0x78, radio78);
1416                 udelay(10);
1417                 for (j = 0; j < 16; j++) {
1418                         b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0D80);
1419                         b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810);
1420                         b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D);
1421                         if (phy->gmode || phy->rev >= 2) {
1422                                 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1423                                               radio2050_rfover_val(dev,
1424                                                                    B43_PHY_RFOVERVAL,
1425                                                                    LPD(1, 0,
1426                                                                        1)));
1427                         }
1428                         b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
1429                         udelay(10);
1430                         if (phy->gmode || phy->rev >= 2) {
1431                                 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1432                                               radio2050_rfover_val(dev,
1433                                                                    B43_PHY_RFOVERVAL,
1434                                                                    LPD(1, 0,
1435                                                                        1)));
1436                         }
1437                         b43_phy_write(dev, B43_PHY_PGACTL, 0xEFB0);
1438                         udelay(10);
1439                         if (phy->gmode || phy->rev >= 2) {
1440                                 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1441                                               radio2050_rfover_val(dev,
1442                                                                    B43_PHY_RFOVERVAL,
1443                                                                    LPD(1, 0,
1444                                                                        0)));
1445                         }
1446                         b43_phy_write(dev, B43_PHY_PGACTL, 0xFFF0);
1447                         udelay(10);
1448                         tmp2 += b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
1449                         b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
1450                         if (phy->gmode || phy->rev >= 2) {
1451                                 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1452                                               radio2050_rfover_val(dev,
1453                                                                    B43_PHY_RFOVERVAL,
1454                                                                    LPD(1, 0,
1455                                                                        1)));
1456                         }
1457                         b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
1458                 }
1459                 tmp2++;
1460                 tmp2 >>= 8;
1461                 if (tmp1 < tmp2)
1462                         break;
1463         }
1464
1465         /* Restore the registers */
1466         b43_phy_write(dev, B43_PHY_PGACTL, sav.phy_pgactl);
1467         b43_radio_write16(dev, 0x51, sav.radio_51);
1468         b43_radio_write16(dev, 0x52, sav.radio_52);
1469         b43_radio_write16(dev, 0x43, sav.radio_43);
1470         b43_phy_write(dev, B43_PHY_CCK(0x5A), sav.phy_cck_5A);
1471         b43_phy_write(dev, B43_PHY_CCK(0x59), sav.phy_cck_59);
1472         b43_phy_write(dev, B43_PHY_CCK(0x58), sav.phy_cck_58);
1473         b43_write16(dev, 0x3E6, sav.reg_3E6);
1474         if (phy->analog != 0)
1475                 b43_write16(dev, 0x3F4, sav.reg_3F4);
1476         b43_phy_write(dev, B43_PHY_SYNCCTL, sav.phy_syncctl);
1477         b43_synth_pu_workaround(dev, phy->channel);
1478         if (phy->type == B43_PHYTYPE_B) {
1479                 b43_phy_write(dev, B43_PHY_CCK(0x30), sav.phy_cck_30);
1480                 b43_write16(dev, 0x3EC, sav.reg_3EC);
1481         } else if (phy->gmode) {
1482                 b43_write16(dev, B43_MMIO_PHY_RADIO,
1483                             b43_read16(dev, B43_MMIO_PHY_RADIO)
1484                             & 0x7FFF);
1485                 b43_phy_write(dev, B43_PHY_RFOVER, sav.phy_rfover);
1486                 b43_phy_write(dev, B43_PHY_RFOVERVAL, sav.phy_rfoverval);
1487                 b43_phy_write(dev, B43_PHY_ANALOGOVER, sav.phy_analogover);
1488                 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
1489                               sav.phy_analogoverval);
1490                 b43_phy_write(dev, B43_PHY_CRS0, sav.phy_crs0);
1491                 b43_phy_write(dev, B43_PHY_CLASSCTL, sav.phy_classctl);
1492                 if (has_loopback_gain(phy)) {
1493                         b43_phy_write(dev, B43_PHY_LO_MASK, sav.phy_lo_mask);
1494                         b43_phy_write(dev, B43_PHY_LO_CTL, sav.phy_lo_ctl);
1495                 }
1496         }
1497         if (i > 15)
1498                 ret = radio78;
1499         else
1500                 ret = rcc;
1501
1502         return ret;
1503 }
1504
1505 static void b43_phy_initb5(struct b43_wldev *dev)
1506 {
1507         struct ssb_bus *bus = dev->dev->bus;
1508         struct b43_phy *phy = &dev->phy;
1509         struct b43_phy_g *gphy = phy->g;
1510         u16 offset, value;
1511         u8 old_channel;
1512
1513         if (phy->analog == 1) {
1514                 b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A)
1515                                   | 0x0050);
1516         }
1517         if ((bus->boardinfo.vendor != SSB_BOARDVENDOR_BCM) &&
1518             (bus->boardinfo.type != SSB_BOARD_BU4306)) {
1519                 value = 0x2120;
1520                 for (offset = 0x00A8; offset < 0x00C7; offset++) {
1521                         b43_phy_write(dev, offset, value);
1522                         value += 0x202;
1523                 }
1524         }
1525         b43_phy_maskset(dev, 0x0035, 0xF0FF, 0x0700);
1526         if (phy->radio_ver == 0x2050)
1527                 b43_phy_write(dev, 0x0038, 0x0667);
1528
1529         if (phy->gmode || phy->rev >= 2) {
1530                 if (phy->radio_ver == 0x2050) {
1531                         b43_radio_write16(dev, 0x007A,
1532                                           b43_radio_read16(dev, 0x007A)
1533                                           | 0x0020);
1534                         b43_radio_write16(dev, 0x0051,
1535                                           b43_radio_read16(dev, 0x0051)
1536                                           | 0x0004);
1537                 }
1538                 b43_write16(dev, B43_MMIO_PHY_RADIO, 0x0000);
1539
1540                 b43_phy_set(dev, 0x0802, 0x0100);
1541                 b43_phy_set(dev, 0x042B, 0x2000);
1542
1543                 b43_phy_write(dev, 0x001C, 0x186A);
1544
1545                 b43_phy_maskset(dev, 0x0013, 0x00FF, 0x1900);
1546                 b43_phy_maskset(dev, 0x0035, 0xFFC0, 0x0064);
1547                 b43_phy_maskset(dev, 0x005D, 0xFF80, 0x000A);
1548         }
1549
1550         if (dev->bad_frames_preempt) {
1551                 b43_phy_set(dev, B43_PHY_RADIO_BITFIELD, (1 << 11));
1552         }
1553
1554         if (phy->analog == 1) {
1555                 b43_phy_write(dev, 0x0026, 0xCE00);
1556                 b43_phy_write(dev, 0x0021, 0x3763);
1557                 b43_phy_write(dev, 0x0022, 0x1BC3);
1558                 b43_phy_write(dev, 0x0023, 0x06F9);
1559                 b43_phy_write(dev, 0x0024, 0x037E);
1560         } else
1561                 b43_phy_write(dev, 0x0026, 0xCC00);
1562         b43_phy_write(dev, 0x0030, 0x00C6);
1563         b43_write16(dev, 0x03EC, 0x3F22);
1564
1565         if (phy->analog == 1)
1566                 b43_phy_write(dev, 0x0020, 0x3E1C);
1567         else
1568                 b43_phy_write(dev, 0x0020, 0x301C);
1569
1570         if (phy->analog == 0)
1571                 b43_write16(dev, 0x03E4, 0x3000);
1572
1573         old_channel = phy->channel;
1574         /* Force to channel 7, even if not supported. */
1575         b43_gphy_channel_switch(dev, 7, 0);
1576
1577         if (phy->radio_ver != 0x2050) {
1578                 b43_radio_write16(dev, 0x0075, 0x0080);
1579                 b43_radio_write16(dev, 0x0079, 0x0081);
1580         }
1581
1582         b43_radio_write16(dev, 0x0050, 0x0020);
1583         b43_radio_write16(dev, 0x0050, 0x0023);
1584
1585         if (phy->radio_ver == 0x2050) {
1586                 b43_radio_write16(dev, 0x0050, 0x0020);
1587                 b43_radio_write16(dev, 0x005A, 0x0070);
1588         }
1589
1590         b43_radio_write16(dev, 0x005B, 0x007B);
1591         b43_radio_write16(dev, 0x005C, 0x00B0);
1592
1593         b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A) | 0x0007);
1594
1595         b43_gphy_channel_switch(dev, old_channel, 0);
1596
1597         b43_phy_write(dev, 0x0014, 0x0080);
1598         b43_phy_write(dev, 0x0032, 0x00CA);
1599         b43_phy_write(dev, 0x002A, 0x88A3);
1600
1601         b43_set_txpower_g(dev, &gphy->bbatt, &gphy->rfatt, gphy->tx_control);
1602
1603         if (phy->radio_ver == 0x2050)
1604                 b43_radio_write16(dev, 0x005D, 0x000D);
1605
1606         b43_write16(dev, 0x03E4, (b43_read16(dev, 0x03E4) & 0xFFC0) | 0x0004);
1607 }
1608
1609 static void b43_phy_initb6(struct b43_wldev *dev)
1610 {
1611         struct b43_phy *phy = &dev->phy;
1612         struct b43_phy_g *gphy = phy->g;
1613         u16 offset, val;
1614         u8 old_channel;
1615
1616         b43_phy_write(dev, 0x003E, 0x817A);
1617         b43_radio_write16(dev, 0x007A,
1618                           (b43_radio_read16(dev, 0x007A) | 0x0058));
1619         if (phy->radio_rev == 4 || phy->radio_rev == 5) {
1620                 b43_radio_write16(dev, 0x51, 0x37);
1621                 b43_radio_write16(dev, 0x52, 0x70);
1622                 b43_radio_write16(dev, 0x53, 0xB3);
1623                 b43_radio_write16(dev, 0x54, 0x9B);
1624                 b43_radio_write16(dev, 0x5A, 0x88);
1625                 b43_radio_write16(dev, 0x5B, 0x88);
1626                 b43_radio_write16(dev, 0x5D, 0x88);
1627                 b43_radio_write16(dev, 0x5E, 0x88);
1628                 b43_radio_write16(dev, 0x7D, 0x88);
1629                 b43_hf_write(dev, b43_hf_read(dev)
1630                              | B43_HF_TSSIRPSMW);
1631         }
1632         B43_WARN_ON(phy->radio_rev == 6 || phy->radio_rev == 7);        /* We had code for these revs here... */
1633         if (phy->radio_rev == 8) {
1634                 b43_radio_write16(dev, 0x51, 0);
1635                 b43_radio_write16(dev, 0x52, 0x40);
1636                 b43_radio_write16(dev, 0x53, 0xB7);
1637                 b43_radio_write16(dev, 0x54, 0x98);
1638                 b43_radio_write16(dev, 0x5A, 0x88);
1639                 b43_radio_write16(dev, 0x5B, 0x6B);
1640                 b43_radio_write16(dev, 0x5C, 0x0F);
1641                 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_ALTIQ) {
1642                         b43_radio_write16(dev, 0x5D, 0xFA);
1643                         b43_radio_write16(dev, 0x5E, 0xD8);
1644                 } else {
1645                         b43_radio_write16(dev, 0x5D, 0xF5);
1646                         b43_radio_write16(dev, 0x5E, 0xB8);
1647                 }
1648                 b43_radio_write16(dev, 0x0073, 0x0003);
1649                 b43_radio_write16(dev, 0x007D, 0x00A8);
1650                 b43_radio_write16(dev, 0x007C, 0x0001);
1651                 b43_radio_write16(dev, 0x007E, 0x0008);
1652         }
1653         val = 0x1E1F;
1654         for (offset = 0x0088; offset < 0x0098; offset++) {
1655                 b43_phy_write(dev, offset, val);
1656                 val -= 0x0202;
1657         }
1658         val = 0x3E3F;
1659         for (offset = 0x0098; offset < 0x00A8; offset++) {
1660                 b43_phy_write(dev, offset, val);
1661                 val -= 0x0202;
1662         }
1663         val = 0x2120;
1664         for (offset = 0x00A8; offset < 0x00C8; offset++) {
1665                 b43_phy_write(dev, offset, (val & 0x3F3F));
1666                 val += 0x0202;
1667         }
1668         if (phy->type == B43_PHYTYPE_G) {
1669                 b43_radio_write16(dev, 0x007A,
1670                                   b43_radio_read16(dev, 0x007A) | 0x0020);
1671                 b43_radio_write16(dev, 0x0051,
1672                                   b43_radio_read16(dev, 0x0051) | 0x0004);
1673                 b43_phy_set(dev, 0x0802, 0x0100);
1674                 b43_phy_set(dev, 0x042B, 0x2000);
1675                 b43_phy_write(dev, 0x5B, 0);
1676                 b43_phy_write(dev, 0x5C, 0);
1677         }
1678
1679         old_channel = phy->channel;
1680         if (old_channel >= 8)
1681                 b43_gphy_channel_switch(dev, 1, 0);
1682         else
1683                 b43_gphy_channel_switch(dev, 13, 0);
1684
1685         b43_radio_write16(dev, 0x0050, 0x0020);
1686         b43_radio_write16(dev, 0x0050, 0x0023);
1687         udelay(40);
1688         if (phy->radio_rev < 6 || phy->radio_rev == 8) {
1689                 b43_radio_write16(dev, 0x7C, (b43_radio_read16(dev, 0x7C)
1690                                               | 0x0002));
1691                 b43_radio_write16(dev, 0x50, 0x20);
1692         }
1693         if (phy->radio_rev <= 2) {
1694                 b43_radio_write16(dev, 0x7C, 0x20);
1695                 b43_radio_write16(dev, 0x5A, 0x70);
1696                 b43_radio_write16(dev, 0x5B, 0x7B);
1697                 b43_radio_write16(dev, 0x5C, 0xB0);
1698         }
1699         b43_radio_write16(dev, 0x007A,
1700                           (b43_radio_read16(dev, 0x007A) & 0x00F8) | 0x0007);
1701
1702         b43_gphy_channel_switch(dev, old_channel, 0);
1703
1704         b43_phy_write(dev, 0x0014, 0x0200);
1705         if (phy->radio_rev >= 6)
1706                 b43_phy_write(dev, 0x2A, 0x88C2);
1707         else
1708                 b43_phy_write(dev, 0x2A, 0x8AC0);
1709         b43_phy_write(dev, 0x0038, 0x0668);
1710         b43_set_txpower_g(dev, &gphy->bbatt, &gphy->rfatt, gphy->tx_control);
1711         if (phy->radio_rev <= 5) {
1712                 b43_phy_maskset(dev, 0x5D, 0xFF80, 0x0003);
1713         }
1714         if (phy->radio_rev <= 2)
1715                 b43_radio_write16(dev, 0x005D, 0x000D);
1716
1717         if (phy->analog == 4) {
1718                 b43_write16(dev, 0x3E4, 9);
1719                 b43_phy_mask(dev, 0x61, 0x0FFF);
1720         } else {
1721                 b43_phy_maskset(dev, 0x0002, 0xFFC0, 0x0004);
1722         }
1723         if (phy->type == B43_PHYTYPE_B)
1724                 B43_WARN_ON(1);
1725         else if (phy->type == B43_PHYTYPE_G)
1726                 b43_write16(dev, 0x03E6, 0x0);
1727 }
1728
1729 static void b43_calc_loopback_gain(struct b43_wldev *dev)
1730 {
1731         struct b43_phy *phy = &dev->phy;
1732         struct b43_phy_g *gphy = phy->g;
1733         u16 backup_phy[16] = { 0 };
1734         u16 backup_radio[3];
1735         u16 backup_bband;
1736         u16 i, j, loop_i_max;
1737         u16 trsw_rx;
1738         u16 loop1_outer_done, loop1_inner_done;
1739
1740         backup_phy[0] = b43_phy_read(dev, B43_PHY_CRS0);
1741         backup_phy[1] = b43_phy_read(dev, B43_PHY_CCKBBANDCFG);
1742         backup_phy[2] = b43_phy_read(dev, B43_PHY_RFOVER);
1743         backup_phy[3] = b43_phy_read(dev, B43_PHY_RFOVERVAL);
1744         if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
1745                 backup_phy[4] = b43_phy_read(dev, B43_PHY_ANALOGOVER);
1746                 backup_phy[5] = b43_phy_read(dev, B43_PHY_ANALOGOVERVAL);
1747         }
1748         backup_phy[6] = b43_phy_read(dev, B43_PHY_CCK(0x5A));
1749         backup_phy[7] = b43_phy_read(dev, B43_PHY_CCK(0x59));
1750         backup_phy[8] = b43_phy_read(dev, B43_PHY_CCK(0x58));
1751         backup_phy[9] = b43_phy_read(dev, B43_PHY_CCK(0x0A));
1752         backup_phy[10] = b43_phy_read(dev, B43_PHY_CCK(0x03));
1753         backup_phy[11] = b43_phy_read(dev, B43_PHY_LO_MASK);
1754         backup_phy[12] = b43_phy_read(dev, B43_PHY_LO_CTL);
1755         backup_phy[13] = b43_phy_read(dev, B43_PHY_CCK(0x2B));
1756         backup_phy[14] = b43_phy_read(dev, B43_PHY_PGACTL);
1757         backup_phy[15] = b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
1758         backup_bband = gphy->bbatt.att;
1759         backup_radio[0] = b43_radio_read16(dev, 0x52);
1760         backup_radio[1] = b43_radio_read16(dev, 0x43);
1761         backup_radio[2] = b43_radio_read16(dev, 0x7A);
1762
1763         b43_phy_mask(dev, B43_PHY_CRS0, 0x3FFF);
1764         b43_phy_set(dev, B43_PHY_CCKBBANDCFG, 0x8000);
1765         b43_phy_set(dev, B43_PHY_RFOVER, 0x0002);
1766         b43_phy_mask(dev, B43_PHY_RFOVERVAL, 0xFFFD);
1767         b43_phy_set(dev, B43_PHY_RFOVER, 0x0001);
1768         b43_phy_mask(dev, B43_PHY_RFOVERVAL, 0xFFFE);
1769         if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
1770                 b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0001);
1771                 b43_phy_mask(dev, B43_PHY_ANALOGOVERVAL, 0xFFFE);
1772                 b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0002);
1773                 b43_phy_mask(dev, B43_PHY_ANALOGOVERVAL, 0xFFFD);
1774         }
1775         b43_phy_set(dev, B43_PHY_RFOVER, 0x000C);
1776         b43_phy_set(dev, B43_PHY_RFOVERVAL, 0x000C);
1777         b43_phy_set(dev, B43_PHY_RFOVER, 0x0030);
1778         b43_phy_maskset(dev, B43_PHY_RFOVERVAL, 0xFFCF, 0x10);
1779
1780         b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0780);
1781         b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810);
1782         b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D);
1783
1784         b43_phy_set(dev, B43_PHY_CCK(0x0A), 0x2000);
1785         if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
1786                 b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0004);
1787                 b43_phy_mask(dev, B43_PHY_ANALOGOVERVAL, 0xFFFB);
1788         }
1789         b43_phy_maskset(dev, B43_PHY_CCK(0x03), 0xFF9F, 0x40);
1790
1791         if (phy->radio_rev == 8) {
1792                 b43_radio_write16(dev, 0x43, 0x000F);
1793         } else {
1794                 b43_radio_write16(dev, 0x52, 0);
1795                 b43_radio_write16(dev, 0x43, (b43_radio_read16(dev, 0x43)
1796                                               & 0xFFF0) | 0x9);
1797         }
1798         b43_gphy_set_baseband_attenuation(dev, 11);
1799
1800         if (phy->rev >= 3)
1801                 b43_phy_write(dev, B43_PHY_LO_MASK, 0xC020);
1802         else
1803                 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8020);
1804         b43_phy_write(dev, B43_PHY_LO_CTL, 0);
1805
1806         b43_phy_maskset(dev, B43_PHY_CCK(0x2B), 0xFFC0, 0x01);
1807         b43_phy_maskset(dev, B43_PHY_CCK(0x2B), 0xC0FF, 0x800);
1808
1809         b43_phy_set(dev, B43_PHY_RFOVER, 0x0100);
1810         b43_phy_mask(dev, B43_PHY_RFOVERVAL, 0xCFFF);
1811
1812         if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_EXTLNA) {
1813                 if (phy->rev >= 7) {
1814                         b43_phy_set(dev, B43_PHY_RFOVER, 0x0800);
1815                         b43_phy_set(dev, B43_PHY_RFOVERVAL, 0x8000);
1816                 }
1817         }
1818         b43_radio_write16(dev, 0x7A, b43_radio_read16(dev, 0x7A)
1819                           & 0x00F7);
1820
1821         j = 0;
1822         loop_i_max = (phy->radio_rev == 8) ? 15 : 9;
1823         for (i = 0; i < loop_i_max; i++) {
1824                 for (j = 0; j < 16; j++) {
1825                         b43_radio_write16(dev, 0x43, i);
1826                         b43_phy_maskset(dev, B43_PHY_RFOVERVAL, 0xF0FF, (j << 8));
1827                         b43_phy_maskset(dev, B43_PHY_PGACTL, 0x0FFF, 0xA000);
1828                         b43_phy_set(dev, B43_PHY_PGACTL, 0xF000);
1829                         udelay(20);
1830                         if (b43_phy_read(dev, B43_PHY_LO_LEAKAGE) >= 0xDFC)
1831                                 goto exit_loop1;
1832                 }
1833         }
1834       exit_loop1:
1835         loop1_outer_done = i;
1836         loop1_inner_done = j;
1837         if (j >= 8) {
1838                 b43_phy_set(dev, B43_PHY_RFOVERVAL, 0x30);
1839                 trsw_rx = 0x1B;
1840                 for (j = j - 8; j < 16; j++) {
1841                         b43_phy_maskset(dev, B43_PHY_RFOVERVAL, 0xF0FF, (j << 8));
1842                         b43_phy_maskset(dev, B43_PHY_PGACTL, 0x0FFF, 0xA000);
1843                         b43_phy_set(dev, B43_PHY_PGACTL, 0xF000);
1844                         udelay(20);
1845                         trsw_rx -= 3;
1846                         if (b43_phy_read(dev, B43_PHY_LO_LEAKAGE) >= 0xDFC)
1847                                 goto exit_loop2;
1848                 }
1849         } else
1850                 trsw_rx = 0x18;
1851       exit_loop2:
1852
1853         if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
1854                 b43_phy_write(dev, B43_PHY_ANALOGOVER, backup_phy[4]);
1855                 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, backup_phy[5]);
1856         }
1857         b43_phy_write(dev, B43_PHY_CCK(0x5A), backup_phy[6]);
1858         b43_phy_write(dev, B43_PHY_CCK(0x59), backup_phy[7]);
1859         b43_phy_write(dev, B43_PHY_CCK(0x58), backup_phy[8]);
1860         b43_phy_write(dev, B43_PHY_CCK(0x0A), backup_phy[9]);
1861         b43_phy_write(dev, B43_PHY_CCK(0x03), backup_phy[10]);
1862         b43_phy_write(dev, B43_PHY_LO_MASK, backup_phy[11]);
1863         b43_phy_write(dev, B43_PHY_LO_CTL, backup_phy[12]);
1864         b43_phy_write(dev, B43_PHY_CCK(0x2B), backup_phy[13]);
1865         b43_phy_write(dev, B43_PHY_PGACTL, backup_phy[14]);
1866
1867         b43_gphy_set_baseband_attenuation(dev, backup_bband);
1868
1869         b43_radio_write16(dev, 0x52, backup_radio[0]);
1870         b43_radio_write16(dev, 0x43, backup_radio[1]);
1871         b43_radio_write16(dev, 0x7A, backup_radio[2]);
1872
1873         b43_phy_write(dev, B43_PHY_RFOVER, backup_phy[2] | 0x0003);
1874         udelay(10);
1875         b43_phy_write(dev, B43_PHY_RFOVER, backup_phy[2]);
1876         b43_phy_write(dev, B43_PHY_RFOVERVAL, backup_phy[3]);
1877         b43_phy_write(dev, B43_PHY_CRS0, backup_phy[0]);
1878         b43_phy_write(dev, B43_PHY_CCKBBANDCFG, backup_phy[1]);
1879
1880         gphy->max_lb_gain =
1881             ((loop1_inner_done * 6) - (loop1_outer_done * 4)) - 11;
1882         gphy->trsw_rx_gain = trsw_rx * 2;
1883 }
1884
1885 static void b43_hardware_pctl_early_init(struct b43_wldev *dev)
1886 {
1887         struct b43_phy *phy = &dev->phy;
1888
1889         if (!b43_has_hardware_pctl(dev)) {
1890                 b43_phy_write(dev, 0x047A, 0xC111);
1891                 return;
1892         }
1893
1894         b43_phy_mask(dev, 0x0036, 0xFEFF);
1895         b43_phy_write(dev, 0x002F, 0x0202);
1896         b43_phy_set(dev, 0x047C, 0x0002);
1897         b43_phy_set(dev, 0x047A, 0xF000);
1898         if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
1899                 b43_phy_maskset(dev, 0x047A, 0xFF0F, 0x0010);
1900                 b43_phy_set(dev, 0x005D, 0x8000);
1901                 b43_phy_maskset(dev, 0x004E, 0xFFC0, 0x0010);
1902                 b43_phy_write(dev, 0x002E, 0xC07F);
1903                 b43_phy_set(dev, 0x0036, 0x0400);
1904         } else {
1905                 b43_phy_set(dev, 0x0036, 0x0200);
1906                 b43_phy_set(dev, 0x0036, 0x0400);
1907                 b43_phy_mask(dev, 0x005D, 0x7FFF);
1908                 b43_phy_mask(dev, 0x004F, 0xFFFE);
1909                 b43_phy_maskset(dev, 0x004E, 0xFFC0, 0x0010);
1910                 b43_phy_write(dev, 0x002E, 0xC07F);
1911                 b43_phy_maskset(dev, 0x047A, 0xFF0F, 0x0010);
1912         }
1913 }
1914
1915 /* Hardware power control for G-PHY */
1916 static void b43_hardware_pctl_init_gphy(struct b43_wldev *dev)
1917 {
1918         struct b43_phy *phy = &dev->phy;
1919         struct b43_phy_g *gphy = phy->g;
1920
1921         if (!b43_has_hardware_pctl(dev)) {
1922                 /* No hardware power control */
1923                 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_HWPCTL);
1924                 return;
1925         }
1926
1927         b43_phy_maskset(dev, 0x0036, 0xFFC0, (gphy->tgt_idle_tssi - gphy->cur_idle_tssi));
1928         b43_phy_maskset(dev, 0x0478, 0xFF00, (gphy->tgt_idle_tssi - gphy->cur_idle_tssi));
1929         b43_gphy_tssi_power_lt_init(dev);
1930         b43_gphy_gain_lt_init(dev);
1931         b43_phy_mask(dev, 0x0060, 0xFFBF);
1932         b43_phy_write(dev, 0x0014, 0x0000);
1933
1934         B43_WARN_ON(phy->rev < 6);
1935         b43_phy_set(dev, 0x0478, 0x0800);
1936         b43_phy_mask(dev, 0x0478, 0xFEFF);
1937         b43_phy_mask(dev, 0x0801, 0xFFBF);
1938
1939         b43_gphy_dc_lt_init(dev, 1);
1940
1941         /* Enable hardware pctl in firmware. */
1942         b43_hf_write(dev, b43_hf_read(dev) | B43_HF_HWPCTL);
1943 }
1944
1945 /* Intialize B/G PHY power control */
1946 static void b43_phy_init_pctl(struct b43_wldev *dev)
1947 {
1948         struct ssb_bus *bus = dev->dev->bus;
1949         struct b43_phy *phy = &dev->phy;
1950         struct b43_phy_g *gphy = phy->g;
1951         struct b43_rfatt old_rfatt;
1952         struct b43_bbatt old_bbatt;
1953         u8 old_tx_control = 0;
1954
1955         B43_WARN_ON(phy->type != B43_PHYTYPE_G);
1956
1957         if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
1958             (bus->boardinfo.type == SSB_BOARD_BU4306))
1959                 return;
1960
1961         b43_phy_write(dev, 0x0028, 0x8018);
1962
1963         /* This does something with the Analog... */
1964         b43_write16(dev, B43_MMIO_PHY0, b43_read16(dev, B43_MMIO_PHY0)
1965                     & 0xFFDF);
1966
1967         if (!phy->gmode)
1968                 return;
1969         b43_hardware_pctl_early_init(dev);
1970         if (gphy->cur_idle_tssi == 0) {
1971                 if (phy->radio_ver == 0x2050 && phy->analog == 0) {
1972                         b43_radio_write16(dev, 0x0076,
1973                                           (b43_radio_read16(dev, 0x0076)
1974                                            & 0x00F7) | 0x0084);
1975                 } else {
1976                         struct b43_rfatt rfatt;
1977                         struct b43_bbatt bbatt;
1978
1979                         memcpy(&old_rfatt, &gphy->rfatt, sizeof(old_rfatt));
1980                         memcpy(&old_bbatt, &gphy->bbatt, sizeof(old_bbatt));
1981                         old_tx_control = gphy->tx_control;
1982
1983                         bbatt.att = 11;
1984                         if (phy->radio_rev == 8) {
1985                                 rfatt.att = 15;
1986                                 rfatt.with_padmix = 1;
1987                         } else {
1988                                 rfatt.att = 9;
1989                                 rfatt.with_padmix = 0;
1990                         }
1991                         b43_set_txpower_g(dev, &bbatt, &rfatt, 0);
1992                 }
1993                 b43_dummy_transmission(dev);
1994                 gphy->cur_idle_tssi = b43_phy_read(dev, B43_PHY_ITSSI);
1995                 if (B43_DEBUG) {
1996                         /* Current-Idle-TSSI sanity check. */
1997                         if (abs(gphy->cur_idle_tssi - gphy->tgt_idle_tssi) >= 20) {
1998                                 b43dbg(dev->wl,
1999                                        "!WARNING! Idle-TSSI phy->cur_idle_tssi "
2000                                        "measuring failed. (cur=%d, tgt=%d). Disabling TX power "
2001                                        "adjustment.\n", gphy->cur_idle_tssi,
2002                                        gphy->tgt_idle_tssi);
2003                                 gphy->cur_idle_tssi = 0;
2004                         }
2005                 }
2006                 if (phy->radio_ver == 0x2050 && phy->analog == 0) {
2007                         b43_radio_write16(dev, 0x0076,
2008                                           b43_radio_read16(dev, 0x0076)
2009                                           & 0xFF7B);
2010                 } else {
2011                         b43_set_txpower_g(dev, &old_bbatt,
2012                                           &old_rfatt, old_tx_control);
2013                 }
2014         }
2015         b43_hardware_pctl_init_gphy(dev);
2016         b43_shm_clear_tssi(dev);
2017 }
2018
2019 static void b43_phy_initg(struct b43_wldev *dev)
2020 {
2021         struct b43_phy *phy = &dev->phy;
2022         struct b43_phy_g *gphy = phy->g;
2023         u16 tmp;
2024
2025         if (phy->rev == 1)
2026                 b43_phy_initb5(dev);
2027         else
2028                 b43_phy_initb6(dev);
2029
2030         if (phy->rev >= 2 || phy->gmode)
2031                 b43_phy_inita(dev);
2032
2033         if (phy->rev >= 2) {
2034                 b43_phy_write(dev, B43_PHY_ANALOGOVER, 0);
2035                 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, 0);
2036         }
2037         if (phy->rev == 2) {
2038                 b43_phy_write(dev, B43_PHY_RFOVER, 0);
2039                 b43_phy_write(dev, B43_PHY_PGACTL, 0xC0);
2040         }
2041         if (phy->rev > 5) {
2042                 b43_phy_write(dev, B43_PHY_RFOVER, 0x400);
2043                 b43_phy_write(dev, B43_PHY_PGACTL, 0xC0);
2044         }
2045         if (phy->gmode || phy->rev >= 2) {
2046                 tmp = b43_phy_read(dev, B43_PHY_VERSION_OFDM);
2047                 tmp &= B43_PHYVER_VERSION;
2048                 if (tmp == 3 || tmp == 5) {
2049                         b43_phy_write(dev, B43_PHY_OFDM(0xC2), 0x1816);
2050                         b43_phy_write(dev, B43_PHY_OFDM(0xC3), 0x8006);
2051                 }
2052                 if (tmp == 5) {
2053                         b43_phy_maskset(dev, B43_PHY_OFDM(0xCC), 0x00FF, 0x1F00);
2054                 }
2055         }
2056         if ((phy->rev <= 2 && phy->gmode) || phy->rev >= 2)
2057                 b43_phy_write(dev, B43_PHY_OFDM(0x7E), 0x78);
2058         if (phy->radio_rev == 8) {
2059                 b43_phy_set(dev, B43_PHY_EXTG(0x01), 0x80);
2060                 b43_phy_set(dev, B43_PHY_OFDM(0x3E), 0x4);
2061         }
2062         if (has_loopback_gain(phy))
2063                 b43_calc_loopback_gain(dev);
2064
2065         if (phy->radio_rev != 8) {
2066                 if (gphy->initval == 0xFFFF)
2067                         gphy->initval = b43_radio_init2050(dev);
2068                 else
2069                         b43_radio_write16(dev, 0x0078, gphy->initval);
2070         }
2071         b43_lo_g_init(dev);
2072         if (has_tx_magnification(phy)) {
2073                 b43_radio_write16(dev, 0x52,
2074                                   (b43_radio_read16(dev, 0x52) & 0xFF00)
2075                                   | gphy->lo_control->tx_bias | gphy->
2076                                   lo_control->tx_magn);
2077         } else {
2078                 b43_radio_write16(dev, 0x52,
2079                                   (b43_radio_read16(dev, 0x52) & 0xFFF0)
2080                                   | gphy->lo_control->tx_bias);
2081         }
2082         if (phy->rev >= 6) {
2083                 b43_phy_maskset(dev, B43_PHY_CCK(0x36), 0x0FFF, (gphy->lo_control->tx_bias << 12));
2084         }
2085         if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL)
2086                 b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x8075);
2087         else
2088                 b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x807F);
2089         if (phy->rev < 2)
2090                 b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x101);
2091         else
2092                 b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x202);
2093         if (phy->gmode || phy->rev >= 2) {
2094                 b43_lo_g_adjust(dev);
2095                 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8078);
2096         }
2097
2098         if (!(dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI)) {
2099                 /* The specs state to update the NRSSI LT with
2100                  * the value 0x7FFFFFFF here. I think that is some weird
2101                  * compiler optimization in the original driver.
2102                  * Essentially, what we do here is resetting all NRSSI LT
2103                  * entries to -32 (see the clamp_val() in nrssi_hw_update())
2104                  */
2105                 b43_nrssi_hw_update(dev, 0xFFFF);       //FIXME?
2106                 b43_calc_nrssi_threshold(dev);
2107         } else if (phy->gmode || phy->rev >= 2) {
2108                 if (gphy->nrssi[0] == -1000) {
2109                         B43_WARN_ON(gphy->nrssi[1] != -1000);
2110                         b43_calc_nrssi_slope(dev);
2111                 } else
2112                         b43_calc_nrssi_threshold(dev);
2113         }
2114         if (phy->radio_rev == 8)
2115                 b43_phy_write(dev, B43_PHY_EXTG(0x05), 0x3230);
2116         b43_phy_init_pctl(dev);
2117         /* FIXME: The spec says in the following if, the 0 should be replaced
2118            'if OFDM may not be used in the current locale'
2119            but OFDM is legal everywhere */
2120         if ((dev->dev->bus->chip_id == 0x4306
2121              && dev->dev->bus->chip_package == 2) || 0) {
2122                 b43_phy_mask(dev, B43_PHY_CRS0, 0xBFFF);
2123                 b43_phy_mask(dev, B43_PHY_OFDM(0xC3), 0x7FFF);
2124         }
2125 }
2126
2127 void b43_gphy_channel_switch(struct b43_wldev *dev,
2128                              unsigned int channel,
2129                              bool synthetic_pu_workaround)
2130 {
2131         if (synthetic_pu_workaround)
2132                 b43_synth_pu_workaround(dev, channel);
2133
2134         b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(channel));
2135
2136         if (channel == 14) {
2137                 if (dev->dev->bus->sprom.country_code ==
2138                     SSB_SPROM1CCODE_JAPAN)
2139                         b43_hf_write(dev,
2140                                      b43_hf_read(dev) & ~B43_HF_ACPR);
2141                 else
2142                         b43_hf_write(dev,
2143                                      b43_hf_read(dev) | B43_HF_ACPR);
2144                 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
2145                             b43_read16(dev, B43_MMIO_CHANNEL_EXT)
2146                             | (1 << 11));
2147         } else {
2148                 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
2149                             b43_read16(dev, B43_MMIO_CHANNEL_EXT)
2150                             & 0xF7BF);
2151         }
2152 }
2153
2154 static void default_baseband_attenuation(struct b43_wldev *dev,
2155                                          struct b43_bbatt *bb)
2156 {
2157         struct b43_phy *phy = &dev->phy;
2158
2159         if (phy->radio_ver == 0x2050 && phy->radio_rev < 6)
2160                 bb->att = 0;
2161         else
2162                 bb->att = 2;
2163 }
2164
2165 static void default_radio_attenuation(struct b43_wldev *dev,
2166                                       struct b43_rfatt *rf)
2167 {
2168         struct ssb_bus *bus = dev->dev->bus;
2169         struct b43_phy *phy = &dev->phy;
2170
2171         rf->with_padmix = 0;
2172
2173         if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM &&
2174             bus->boardinfo.type == SSB_BOARD_BCM4309G) {
2175                 if (bus->boardinfo.rev < 0x43) {
2176                         rf->att = 2;
2177                         return;
2178                 } else if (bus->boardinfo.rev < 0x51) {
2179                         rf->att = 3;
2180                         return;
2181                 }
2182         }
2183
2184         if (phy->type == B43_PHYTYPE_A) {
2185                 rf->att = 0x60;
2186                 return;
2187         }
2188
2189         switch (phy->radio_ver) {
2190         case 0x2053:
2191                 switch (phy->radio_rev) {
2192                 case 1:
2193                         rf->att = 6;
2194                         return;
2195                 }
2196                 break;
2197         case 0x2050:
2198                 switch (phy->radio_rev) {
2199                 case 0:
2200                         rf->att = 5;
2201                         return;
2202                 case 1:
2203                         if (phy->type == B43_PHYTYPE_G) {
2204                                 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM
2205                                     && bus->boardinfo.type == SSB_BOARD_BCM4309G
2206                                     && bus->boardinfo.rev >= 30)
2207                                         rf->att = 3;
2208                                 else if (bus->boardinfo.vendor ==
2209                                          SSB_BOARDVENDOR_BCM
2210                                          && bus->boardinfo.type ==
2211                                          SSB_BOARD_BU4306)
2212                                         rf->att = 3;
2213                                 else
2214                                         rf->att = 1;
2215                         } else {
2216                                 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM
2217                                     && bus->boardinfo.type == SSB_BOARD_BCM4309G
2218                                     && bus->boardinfo.rev >= 30)
2219                                         rf->att = 7;
2220                                 else
2221                                         rf->att = 6;
2222                         }
2223                         return;
2224                 case 2:
2225                         if (phy->type == B43_PHYTYPE_G) {
2226                                 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM
2227                                     && bus->boardinfo.type == SSB_BOARD_BCM4309G
2228                                     && bus->boardinfo.rev >= 30)
2229                                         rf->att = 3;
2230                                 else if (bus->boardinfo.vendor ==
2231                                          SSB_BOARDVENDOR_BCM
2232                                          && bus->boardinfo.type ==
2233                                          SSB_BOARD_BU4306)
2234                                         rf->att = 5;
2235                                 else if (bus->chip_id == 0x4320)
2236                                         rf->att = 4;
2237                                 else
2238                                         rf->att = 3;
2239                         } else
2240                                 rf->att = 6;
2241                         return;
2242                 case 3:
2243                         rf->att = 5;
2244                         return;
2245                 case 4:
2246                 case 5:
2247                         rf->att = 1;
2248                         return;
2249                 case 6:
2250                 case 7:
2251                         rf->att = 5;
2252                         return;
2253                 case 8:
2254                         rf->att = 0xA;
2255                         rf->with_padmix = 1;
2256                         return;
2257                 case 9:
2258                 default:
2259                         rf->att = 5;
2260                         return;
2261                 }
2262         }
2263         rf->att = 5;
2264 }
2265
2266 static u16 default_tx_control(struct b43_wldev *dev)
2267 {
2268         struct b43_phy *phy = &dev->phy;
2269
2270         if (phy->radio_ver != 0x2050)
2271                 return 0;
2272         if (phy->radio_rev == 1)
2273                 return B43_TXCTL_PA2DB | B43_TXCTL_TXMIX;
2274         if (phy->radio_rev < 6)
2275                 return B43_TXCTL_PA2DB;
2276         if (phy->radio_rev == 8)
2277                 return B43_TXCTL_TXMIX;
2278         return 0;
2279 }
2280
2281 static u8 b43_gphy_aci_detect(struct b43_wldev *dev, u8 channel)
2282 {
2283         struct b43_phy *phy = &dev->phy;
2284         struct b43_phy_g *gphy = phy->g;
2285         u8 ret = 0;
2286         u16 saved, rssi, temp;
2287         int i, j = 0;
2288
2289         saved = b43_phy_read(dev, 0x0403);
2290         b43_switch_channel(dev, channel);
2291         b43_phy_write(dev, 0x0403, (saved & 0xFFF8) | 5);
2292         if (gphy->aci_hw_rssi)
2293                 rssi = b43_phy_read(dev, 0x048A) & 0x3F;
2294         else
2295                 rssi = saved & 0x3F;
2296         /* clamp temp to signed 5bit */
2297         if (rssi > 32)
2298                 rssi -= 64;
2299         for (i = 0; i < 100; i++) {
2300                 temp = (b43_phy_read(dev, 0x047F) >> 8) & 0x3F;
2301                 if (temp > 32)
2302                         temp -= 64;
2303                 if (temp < rssi)
2304                         j++;
2305                 if (j >= 20)
2306                         ret = 1;
2307         }
2308         b43_phy_write(dev, 0x0403, saved);
2309
2310         return ret;
2311 }
2312
2313 static u8 b43_gphy_aci_scan(struct b43_wldev *dev)
2314 {
2315         struct b43_phy *phy = &dev->phy;
2316         u8 ret[13];
2317         unsigned int channel = phy->channel;
2318         unsigned int i, j, start, end;
2319
2320         if (!((phy->type == B43_PHYTYPE_G) && (phy->rev > 0)))
2321                 return 0;
2322
2323         b43_phy_lock(dev);
2324         b43_radio_lock(dev);
2325         b43_phy_mask(dev, 0x0802, 0xFFFC);
2326         b43_phy_mask(dev, B43_PHY_G_CRS, 0x7FFF);
2327         b43_set_all_gains(dev, 3, 8, 1);
2328
2329         start = (channel - 5 > 0) ? channel - 5 : 1;
2330         end = (channel + 5 < 14) ? channel + 5 : 13;
2331
2332         for (i = start; i <= end; i++) {
2333                 if (abs(channel - i) > 2)
2334                         ret[i - 1] = b43_gphy_aci_detect(dev, i);
2335         }
2336         b43_switch_channel(dev, channel);
2337         b43_phy_maskset(dev, 0x0802, 0xFFFC, 0x0003);
2338         b43_phy_mask(dev, 0x0403, 0xFFF8);
2339         b43_phy_set(dev, B43_PHY_G_CRS, 0x8000);
2340         b43_set_original_gains(dev);
2341         for (i = 0; i < 13; i++) {
2342                 if (!ret[i])
2343                         continue;
2344                 end = (i + 5 < 13) ? i + 5 : 13;
2345                 for (j = i; j < end; j++)
2346                         ret[j] = 1;
2347         }
2348         b43_radio_unlock(dev);
2349         b43_phy_unlock(dev);
2350
2351         return ret[channel - 1];
2352 }
2353
2354 static s32 b43_tssi2dbm_ad(s32 num, s32 den)
2355 {
2356         if (num < 0)
2357                 return num / den;
2358         else
2359                 return (num + den / 2) / den;
2360 }
2361
2362 static s8 b43_tssi2dbm_entry(s8 entry[], u8 index,
2363                              s16 pab0, s16 pab1, s16 pab2)
2364 {
2365         s32 m1, m2, f = 256, q, delta;
2366         s8 i = 0;
2367
2368         m1 = b43_tssi2dbm_ad(16 * pab0 + index * pab1, 32);
2369         m2 = max(b43_tssi2dbm_ad(32768 + index * pab2, 256), 1);
2370         do {
2371                 if (i > 15)
2372                         return -EINVAL;
2373                 q = b43_tssi2dbm_ad(f * 4096 -
2374                                     b43_tssi2dbm_ad(m2 * f, 16) * f, 2048);
2375                 delta = abs(q - f);
2376                 f = q;
2377                 i++;
2378         } while (delta >= 2);
2379         entry[index] = clamp_val(b43_tssi2dbm_ad(m1 * f, 8192), -127, 128);
2380         return 0;
2381 }
2382
2383 u8 * b43_generate_dyn_tssi2dbm_tab(struct b43_wldev *dev,
2384                                    s16 pab0, s16 pab1, s16 pab2)
2385 {
2386         unsigned int i;
2387         u8 *tab;
2388         int err;
2389
2390         tab = kmalloc(64, GFP_KERNEL);
2391         if (!tab) {
2392                 b43err(dev->wl, "Could not allocate memory "
2393                        "for tssi2dbm table\n");
2394                 return NULL;
2395         }
2396         for (i = 0; i < 64; i++) {
2397                 err = b43_tssi2dbm_entry(tab, i, pab0, pab1, pab2);
2398                 if (err) {
2399                         b43err(dev->wl, "Could not generate "
2400                                "tssi2dBm table\n");
2401                         kfree(tab);
2402                         return NULL;
2403                 }
2404         }
2405
2406         return tab;
2407 }
2408
2409 /* Initialise the TSSI->dBm lookup table */
2410 static int b43_gphy_init_tssi2dbm_table(struct b43_wldev *dev)
2411 {
2412         struct b43_phy *phy = &dev->phy;
2413         struct b43_phy_g *gphy = phy->g;
2414         s16 pab0, pab1, pab2;
2415
2416         pab0 = (s16) (dev->dev->bus->sprom.pa0b0);
2417         pab1 = (s16) (dev->dev->bus->sprom.pa0b1);
2418         pab2 = (s16) (dev->dev->bus->sprom.pa0b2);
2419
2420         B43_WARN_ON((dev->dev->bus->chip_id == 0x4301) &&
2421                     (phy->radio_ver != 0x2050)); /* Not supported anymore */
2422
2423         gphy->dyn_tssi_tbl = 0;
2424
2425         if (pab0 != 0 && pab1 != 0 && pab2 != 0 &&
2426             pab0 != -1 && pab1 != -1 && pab2 != -1) {
2427                 /* The pabX values are set in SPROM. Use them. */
2428                 if ((s8) dev->dev->bus->sprom.itssi_bg != 0 &&
2429                     (s8) dev->dev->bus->sprom.itssi_bg != -1) {
2430                         gphy->tgt_idle_tssi =
2431                                 (s8) (dev->dev->bus->sprom.itssi_bg);
2432                 } else
2433                         gphy->tgt_idle_tssi = 62;
2434                 gphy->tssi2dbm = b43_generate_dyn_tssi2dbm_tab(dev, pab0,
2435                                                                pab1, pab2);
2436                 if (!gphy->tssi2dbm)
2437                         return -ENOMEM;
2438                 gphy->dyn_tssi_tbl = 1;
2439         } else {
2440                 /* pabX values not set in SPROM. */
2441                 gphy->tgt_idle_tssi = 52;
2442                 gphy->tssi2dbm = b43_tssi2dbm_g_table;
2443         }
2444
2445         return 0;
2446 }
2447
2448 static int b43_gphy_op_allocate(struct b43_wldev *dev)
2449 {
2450         struct b43_phy_g *gphy;
2451         struct b43_txpower_lo_control *lo;
2452         int err;
2453
2454         gphy = kzalloc(sizeof(*gphy), GFP_KERNEL);
2455         if (!gphy) {
2456                 err = -ENOMEM;
2457                 goto error;
2458         }
2459         dev->phy.g = gphy;
2460
2461         lo = kzalloc(sizeof(*lo), GFP_KERNEL);
2462         if (!lo) {
2463                 err = -ENOMEM;
2464                 goto err_free_gphy;
2465         }
2466         gphy->lo_control = lo;
2467
2468         err = b43_gphy_init_tssi2dbm_table(dev);
2469         if (err)
2470                 goto err_free_lo;
2471
2472         return 0;
2473
2474 err_free_lo:
2475         kfree(lo);
2476 err_free_gphy:
2477         kfree(gphy);
2478 error:
2479         return err;
2480 }
2481
2482 static void b43_gphy_op_prepare_structs(struct b43_wldev *dev)
2483 {
2484         struct b43_phy *phy = &dev->phy;
2485         struct b43_phy_g *gphy = phy->g;
2486         const void *tssi2dbm;
2487         int tgt_idle_tssi;
2488         struct b43_txpower_lo_control *lo;
2489         unsigned int i;
2490
2491         /* tssi2dbm table is constant, so it is initialized at alloc time.
2492          * Save a copy of the pointer. */
2493         tssi2dbm = gphy->tssi2dbm;
2494         tgt_idle_tssi = gphy->tgt_idle_tssi;
2495         /* Save the LO pointer. */
2496         lo = gphy->lo_control;
2497
2498         /* Zero out the whole PHY structure. */
2499         memset(gphy, 0, sizeof(*gphy));
2500
2501         /* Restore pointers. */
2502         gphy->tssi2dbm = tssi2dbm;
2503         gphy->tgt_idle_tssi = tgt_idle_tssi;
2504         gphy->lo_control = lo;
2505
2506         memset(gphy->minlowsig, 0xFF, sizeof(gphy->minlowsig));
2507
2508         /* NRSSI */
2509         for (i = 0; i < ARRAY_SIZE(gphy->nrssi); i++)
2510                 gphy->nrssi[i] = -1000;
2511         for (i = 0; i < ARRAY_SIZE(gphy->nrssi_lt); i++)
2512                 gphy->nrssi_lt[i] = i;
2513
2514         gphy->lofcal = 0xFFFF;
2515         gphy->initval = 0xFFFF;
2516
2517         gphy->interfmode = B43_INTERFMODE_NONE;
2518
2519         /* OFDM-table address caching. */
2520         gphy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_UNKNOWN;
2521
2522         gphy->average_tssi = 0xFF;
2523
2524         /* Local Osciallator structure */
2525         lo->tx_bias = 0xFF;
2526         INIT_LIST_HEAD(&lo->calib_list);
2527 }
2528
2529 static void b43_gphy_op_free(struct b43_wldev *dev)
2530 {
2531         struct b43_phy *phy = &dev->phy;
2532         struct b43_phy_g *gphy = phy->g;
2533
2534         kfree(gphy->lo_control);
2535
2536         if (gphy->dyn_tssi_tbl)
2537                 kfree(gphy->tssi2dbm);
2538         gphy->dyn_tssi_tbl = 0;
2539         gphy->tssi2dbm = NULL;
2540
2541         kfree(gphy);
2542         dev->phy.g = NULL;
2543 }
2544
2545 static int b43_gphy_op_prepare_hardware(struct b43_wldev *dev)
2546 {
2547         struct b43_phy *phy = &dev->phy;
2548         struct b43_phy_g *gphy = phy->g;
2549         struct b43_txpower_lo_control *lo = gphy->lo_control;
2550
2551         B43_WARN_ON(phy->type != B43_PHYTYPE_G);
2552
2553         default_baseband_attenuation(dev, &gphy->bbatt);
2554         default_radio_attenuation(dev, &gphy->rfatt);
2555         gphy->tx_control = (default_tx_control(dev) << 4);
2556         generate_rfatt_list(dev, &lo->rfatt_list);
2557         generate_bbatt_list(dev, &lo->bbatt_list);
2558
2559         /* Commit previous writes */
2560         b43_read32(dev, B43_MMIO_MACCTL);
2561
2562         if (phy->rev == 1) {
2563                 /* Workaround: Temporarly disable gmode through the early init
2564                  * phase, as the gmode stuff is not needed for phy rev 1 */
2565                 phy->gmode = 0;
2566                 b43_wireless_core_reset(dev, 0);
2567                 b43_phy_initg(dev);
2568                 phy->gmode = 1;
2569                 b43_wireless_core_reset(dev, B43_TMSLOW_GMODE);
2570         }
2571
2572         return 0;
2573 }
2574
2575 static int b43_gphy_op_init(struct b43_wldev *dev)
2576 {
2577         b43_phy_initg(dev);
2578
2579         return 0;
2580 }
2581
2582 static void b43_gphy_op_exit(struct b43_wldev *dev)
2583 {
2584         b43_lo_g_cleanup(dev);
2585 }
2586
2587 static u16 b43_gphy_op_read(struct b43_wldev *dev, u16 reg)
2588 {
2589         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
2590         return b43_read16(dev, B43_MMIO_PHY_DATA);
2591 }
2592
2593 static void b43_gphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
2594 {
2595         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
2596         b43_write16(dev, B43_MMIO_PHY_DATA, value);
2597 }
2598
2599 static u16 b43_gphy_op_radio_read(struct b43_wldev *dev, u16 reg)
2600 {
2601         /* Register 1 is a 32-bit register. */
2602         B43_WARN_ON(reg == 1);
2603         /* G-PHY needs 0x80 for read access. */
2604         reg |= 0x80;
2605
2606         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
2607         return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
2608 }
2609
2610 static void b43_gphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
2611 {
2612         /* Register 1 is a 32-bit register. */
2613         B43_WARN_ON(reg == 1);
2614
2615         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
2616         b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
2617 }
2618
2619 static bool b43_gphy_op_supports_hwpctl(struct b43_wldev *dev)
2620 {
2621         return (dev->phy.rev >= 6);
2622 }
2623
2624 static void b43_gphy_op_software_rfkill(struct b43_wldev *dev,
2625                                         enum rfkill_state state)
2626 {
2627         struct b43_phy *phy = &dev->phy;
2628         struct b43_phy_g *gphy = phy->g;
2629         unsigned int channel;
2630
2631         might_sleep();
2632
2633         if (state == RFKILL_STATE_UNBLOCKED) {
2634                 /* Turn radio ON */
2635                 if (phy->radio_on)
2636                         return;
2637
2638                 b43_phy_write(dev, 0x0015, 0x8000);
2639                 b43_phy_write(dev, 0x0015, 0xCC00);
2640                 b43_phy_write(dev, 0x0015, (phy->gmode ? 0x00C0 : 0x0000));
2641                 if (gphy->radio_off_context.valid) {
2642                         /* Restore the RFover values. */
2643                         b43_phy_write(dev, B43_PHY_RFOVER,
2644                                       gphy->radio_off_context.rfover);
2645                         b43_phy_write(dev, B43_PHY_RFOVERVAL,
2646                                       gphy->radio_off_context.rfoverval);
2647                         gphy->radio_off_context.valid = 0;
2648                 }
2649                 channel = phy->channel;
2650                 b43_gphy_channel_switch(dev, 6, 1);
2651                 b43_gphy_channel_switch(dev, channel, 0);
2652         } else {
2653                 /* Turn radio OFF */
2654                 u16 rfover, rfoverval;
2655
2656                 rfover = b43_phy_read(dev, B43_PHY_RFOVER);
2657                 rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL);
2658                 gphy->radio_off_context.rfover = rfover;
2659                 gphy->radio_off_context.rfoverval = rfoverval;
2660                 gphy->radio_off_context.valid = 1;
2661                 b43_phy_write(dev, B43_PHY_RFOVER, rfover | 0x008C);
2662                 b43_phy_write(dev, B43_PHY_RFOVERVAL, rfoverval & 0xFF73);
2663         }
2664 }
2665
2666 static int b43_gphy_op_switch_channel(struct b43_wldev *dev,
2667                                       unsigned int new_channel)
2668 {
2669         if ((new_channel < 1) || (new_channel > 14))
2670                 return -EINVAL;
2671         b43_gphy_channel_switch(dev, new_channel, 0);
2672
2673         return 0;
2674 }
2675
2676 static unsigned int b43_gphy_op_get_default_chan(struct b43_wldev *dev)
2677 {
2678         return 1; /* Default to channel 1 */
2679 }
2680
2681 static void b43_gphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna)
2682 {
2683         struct b43_phy *phy = &dev->phy;
2684         u64 hf;
2685         u16 tmp;
2686         int autodiv = 0;
2687
2688         if (antenna == B43_ANTENNA_AUTO0 || antenna == B43_ANTENNA_AUTO1)
2689                 autodiv = 1;
2690
2691         hf = b43_hf_read(dev);
2692         hf &= ~B43_HF_ANTDIVHELP;
2693         b43_hf_write(dev, hf);
2694
2695         tmp = b43_phy_read(dev, B43_PHY_BBANDCFG);
2696         tmp &= ~B43_PHY_BBANDCFG_RXANT;
2697         tmp |= (autodiv ? B43_ANTENNA_AUTO0 : antenna)
2698                         << B43_PHY_BBANDCFG_RXANT_SHIFT;
2699         b43_phy_write(dev, B43_PHY_BBANDCFG, tmp);
2700
2701         if (autodiv) {
2702                 tmp = b43_phy_read(dev, B43_PHY_ANTDWELL);
2703                 if (antenna == B43_ANTENNA_AUTO0)
2704                         tmp &= ~B43_PHY_ANTDWELL_AUTODIV1;
2705                 else
2706                         tmp |= B43_PHY_ANTDWELL_AUTODIV1;
2707                 b43_phy_write(dev, B43_PHY_ANTDWELL, tmp);
2708         }
2709         tmp = b43_phy_read(dev, B43_PHY_ANTWRSETT);
2710         if (autodiv)
2711                 tmp |= B43_PHY_ANTWRSETT_ARXDIV;
2712         else
2713                 tmp &= ~B43_PHY_ANTWRSETT_ARXDIV;
2714         b43_phy_write(dev, B43_PHY_ANTWRSETT, tmp);
2715         if (phy->rev >= 2) {
2716                 tmp = b43_phy_read(dev, B43_PHY_OFDM61);
2717                 tmp |= B43_PHY_OFDM61_10;
2718                 b43_phy_write(dev, B43_PHY_OFDM61, tmp);
2719
2720                 tmp =
2721                     b43_phy_read(dev, B43_PHY_DIVSRCHGAINBACK);
2722                 tmp = (tmp & 0xFF00) | 0x15;
2723                 b43_phy_write(dev, B43_PHY_DIVSRCHGAINBACK,
2724                               tmp);
2725
2726                 if (phy->rev == 2) {
2727                         b43_phy_write(dev, B43_PHY_ADIVRELATED,
2728                                       8);
2729                 } else {
2730                         tmp =
2731                             b43_phy_read(dev,
2732                                          B43_PHY_ADIVRELATED);
2733                         tmp = (tmp & 0xFF00) | 8;
2734                         b43_phy_write(dev, B43_PHY_ADIVRELATED,
2735                                       tmp);
2736                 }
2737         }
2738         if (phy->rev >= 6)
2739                 b43_phy_write(dev, B43_PHY_OFDM9B, 0xDC);
2740
2741         hf |= B43_HF_ANTDIVHELP;
2742         b43_hf_write(dev, hf);
2743 }
2744
2745 static int b43_gphy_op_interf_mitigation(struct b43_wldev *dev,
2746                                          enum b43_interference_mitigation mode)
2747 {
2748         struct b43_phy *phy = &dev->phy;
2749         struct b43_phy_g *gphy = phy->g;
2750         int currentmode;
2751
2752         B43_WARN_ON(phy->type != B43_PHYTYPE_G);
2753         if ((phy->rev == 0) || (!phy->gmode))
2754                 return -ENODEV;
2755
2756         gphy->aci_wlan_automatic = 0;
2757         switch (mode) {
2758         case B43_INTERFMODE_AUTOWLAN:
2759                 gphy->aci_wlan_automatic = 1;
2760                 if (gphy->aci_enable)
2761                         mode = B43_INTERFMODE_MANUALWLAN;
2762                 else
2763                         mode = B43_INTERFMODE_NONE;
2764                 break;
2765         case B43_INTERFMODE_NONE:
2766         case B43_INTERFMODE_NONWLAN:
2767         case B43_INTERFMODE_MANUALWLAN:
2768                 break;
2769         default:
2770                 return -EINVAL;
2771         }
2772
2773         currentmode = gphy->interfmode;
2774         if (currentmode == mode)
2775                 return 0;
2776         if (currentmode != B43_INTERFMODE_NONE)
2777                 b43_radio_interference_mitigation_disable(dev, currentmode);
2778
2779         if (mode == B43_INTERFMODE_NONE) {
2780                 gphy->aci_enable = 0;
2781                 gphy->aci_hw_rssi = 0;
2782         } else
2783                 b43_radio_interference_mitigation_enable(dev, mode);
2784         gphy->interfmode = mode;
2785
2786         return 0;
2787 }
2788
2789 /* http://bcm-specs.sipsolutions.net/EstimatePowerOut
2790  * This function converts a TSSI value to dBm in Q5.2
2791  */
2792 static s8 b43_gphy_estimate_power_out(struct b43_wldev *dev, s8 tssi)
2793 {
2794         struct b43_phy_g *gphy = dev->phy.g;
2795         s8 dbm;
2796         s32 tmp;
2797
2798         tmp = (gphy->tgt_idle_tssi - gphy->cur_idle_tssi + tssi);
2799         tmp = clamp_val(tmp, 0x00, 0x3F);
2800         dbm = gphy->tssi2dbm[tmp];
2801
2802         return dbm;
2803 }
2804
2805 static void b43_put_attenuation_into_ranges(struct b43_wldev *dev,
2806                                             int *_bbatt, int *_rfatt)
2807 {
2808         int rfatt = *_rfatt;
2809         int bbatt = *_bbatt;
2810         struct b43_txpower_lo_control *lo = dev->phy.g->lo_control;
2811
2812         /* Get baseband and radio attenuation values into their permitted ranges.
2813          * Radio attenuation affects power level 4 times as much as baseband. */
2814
2815         /* Range constants */
2816         const int rf_min = lo->rfatt_list.min_val;
2817         const int rf_max = lo->rfatt_list.max_val;
2818         const int bb_min = lo->bbatt_list.min_val;
2819         const int bb_max = lo->bbatt_list.max_val;
2820
2821         while (1) {
2822                 if (rfatt > rf_max && bbatt > bb_max - 4)
2823                         break;  /* Can not get it into ranges */
2824                 if (rfatt < rf_min && bbatt < bb_min + 4)
2825                         break;  /* Can not get it into ranges */
2826                 if (bbatt > bb_max && rfatt > rf_max - 1)
2827                         break;  /* Can not get it into ranges */
2828                 if (bbatt < bb_min && rfatt < rf_min + 1)
2829                         break;  /* Can not get it into ranges */
2830
2831                 if (bbatt > bb_max) {
2832                         bbatt -= 4;
2833                         rfatt += 1;
2834                         continue;
2835                 }
2836                 if (bbatt < bb_min) {
2837                         bbatt += 4;
2838                         rfatt -= 1;
2839                         continue;
2840                 }
2841                 if (rfatt > rf_max) {
2842                         rfatt -= 1;
2843                         bbatt += 4;
2844                         continue;
2845                 }
2846                 if (rfatt < rf_min) {
2847                         rfatt += 1;
2848                         bbatt -= 4;
2849                         continue;
2850                 }
2851                 break;
2852         }
2853
2854         *_rfatt = clamp_val(rfatt, rf_min, rf_max);
2855         *_bbatt = clamp_val(bbatt, bb_min, bb_max);
2856 }
2857
2858 static void b43_gphy_op_adjust_txpower(struct b43_wldev *dev)
2859 {
2860         struct b43_phy *phy = &dev->phy;
2861         struct b43_phy_g *gphy = phy->g;
2862         int rfatt, bbatt;
2863         u8 tx_control;
2864
2865         b43_mac_suspend(dev);
2866
2867         spin_lock_irq(&dev->wl->irq_lock);
2868
2869         /* Calculate the new attenuation values. */
2870         bbatt = gphy->bbatt.att;
2871         bbatt += gphy->bbatt_delta;
2872         rfatt = gphy->rfatt.att;
2873         rfatt += gphy->rfatt_delta;
2874
2875         b43_put_attenuation_into_ranges(dev, &bbatt, &rfatt);
2876         tx_control = gphy->tx_control;
2877         if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 2)) {
2878                 if (rfatt <= 1) {
2879                         if (tx_control == 0) {
2880                                 tx_control =
2881                                     B43_TXCTL_PA2DB |
2882                                     B43_TXCTL_TXMIX;
2883                                 rfatt += 2;
2884                                 bbatt += 2;
2885                         } else if (dev->dev->bus->sprom.
2886                                    boardflags_lo &
2887                                    B43_BFL_PACTRL) {
2888                                 bbatt += 4 * (rfatt - 2);
2889                                 rfatt = 2;
2890                         }
2891                 } else if (rfatt > 4 && tx_control) {
2892                         tx_control = 0;
2893                         if (bbatt < 3) {
2894                                 rfatt -= 3;
2895                                 bbatt += 2;
2896                         } else {
2897                                 rfatt -= 2;
2898                                 bbatt -= 2;
2899                         }
2900                 }
2901         }
2902         /* Save the control values */
2903         gphy->tx_control = tx_control;
2904         b43_put_attenuation_into_ranges(dev, &bbatt, &rfatt);
2905         gphy->rfatt.att = rfatt;
2906         gphy->bbatt.att = bbatt;
2907
2908         /* We drop the lock early, so we can sleep during hardware
2909          * adjustment. Possible races with op_recalc_txpower are harmless,
2910          * as we will be called once again in case we raced. */
2911         spin_unlock_irq(&dev->wl->irq_lock);
2912
2913         if (b43_debug(dev, B43_DBG_XMITPOWER))
2914                 b43dbg(dev->wl, "Adjusting TX power\n");
2915
2916         /* Adjust the hardware */
2917         b43_phy_lock(dev);
2918         b43_radio_lock(dev);
2919         b43_set_txpower_g(dev, &gphy->bbatt, &gphy->rfatt,
2920                           gphy->tx_control);
2921         b43_radio_unlock(dev);
2922         b43_phy_unlock(dev);
2923
2924         b43_mac_enable(dev);
2925 }
2926
2927 static enum b43_txpwr_result b43_gphy_op_recalc_txpower(struct b43_wldev *dev,
2928                                                         bool ignore_tssi)
2929 {
2930         struct b43_phy *phy = &dev->phy;
2931         struct b43_phy_g *gphy = phy->g;
2932         unsigned int average_tssi;
2933         int cck_result, ofdm_result;
2934         int estimated_pwr, desired_pwr, pwr_adjust;
2935         int rfatt_delta, bbatt_delta;
2936         unsigned int max_pwr;
2937
2938         /* First get the average TSSI */
2939         cck_result = b43_phy_shm_tssi_read(dev, B43_SHM_SH_TSSI_CCK);
2940         ofdm_result = b43_phy_shm_tssi_read(dev, B43_SHM_SH_TSSI_OFDM_G);
2941         if ((cck_result < 0) && (ofdm_result < 0)) {
2942                 /* No TSSI information available */
2943                 if (!ignore_tssi)
2944                         goto no_adjustment_needed;
2945                 cck_result = 0;
2946                 ofdm_result = 0;
2947         }
2948         if (cck_result < 0)
2949                 average_tssi = ofdm_result;
2950         else if (ofdm_result < 0)
2951                 average_tssi = cck_result;
2952         else
2953                 average_tssi = (cck_result + ofdm_result) / 2;
2954         /* Merge the average with the stored value. */
2955         if (likely(gphy->average_tssi != 0xFF))
2956                 average_tssi = (average_tssi + gphy->average_tssi) / 2;
2957         gphy->average_tssi = average_tssi;
2958         B43_WARN_ON(average_tssi >= B43_TSSI_MAX);
2959
2960         /* Estimate the TX power emission based on the TSSI */
2961         estimated_pwr = b43_gphy_estimate_power_out(dev, average_tssi);
2962
2963         B43_WARN_ON(phy->type != B43_PHYTYPE_G);
2964         max_pwr = dev->dev->bus->sprom.maxpwr_bg;
2965         if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL)
2966                 max_pwr -= 3; /* minus 0.75 */
2967         if (unlikely(max_pwr >= INT_TO_Q52(30/*dBm*/))) {
2968                 b43warn(dev->wl,
2969                         "Invalid max-TX-power value in SPROM.\n");
2970                 max_pwr = INT_TO_Q52(20); /* fake it */
2971                 dev->dev->bus->sprom.maxpwr_bg = max_pwr;
2972         }
2973
2974         /* Get desired power (in Q5.2) */
2975         if (phy->desired_txpower < 0)
2976                 desired_pwr = INT_TO_Q52(0);
2977         else
2978                 desired_pwr = INT_TO_Q52(phy->desired_txpower);
2979         /* And limit it. max_pwr already is Q5.2 */
2980         desired_pwr = clamp_val(desired_pwr, 0, max_pwr);
2981         if (b43_debug(dev, B43_DBG_XMITPOWER)) {
2982                 b43dbg(dev->wl,
2983                        "[TX power]  current = " Q52_FMT
2984                        " dBm,  desired = " Q52_FMT
2985                        " dBm,  max = " Q52_FMT "\n",
2986                        Q52_ARG(estimated_pwr),
2987                        Q52_ARG(desired_pwr),
2988                        Q52_ARG(max_pwr));
2989         }
2990
2991         /* Calculate the adjustment delta. */
2992         pwr_adjust = desired_pwr - estimated_pwr;
2993         if (pwr_adjust == 0)
2994                 goto no_adjustment_needed;
2995
2996         /* RF attenuation delta. */
2997         rfatt_delta = ((pwr_adjust + 7) / 8);
2998         /* Lower attenuation => Bigger power output. Negate it. */
2999         rfatt_delta = -rfatt_delta;
3000
3001         /* Baseband attenuation delta. */
3002         bbatt_delta = pwr_adjust / 2;
3003         /* Lower attenuation => Bigger power output. Negate it. */
3004         bbatt_delta = -bbatt_delta;
3005         /* RF att affects power level 4 times as much as
3006          * Baseband attennuation. Subtract it. */
3007         bbatt_delta -= 4 * rfatt_delta;
3008
3009 #if B43_DEBUG
3010         if (b43_debug(dev, B43_DBG_XMITPOWER)) {
3011                 int dbm = pwr_adjust < 0 ? -pwr_adjust : pwr_adjust;
3012                 b43dbg(dev->wl,
3013                        "[TX power deltas]  %s" Q52_FMT " dBm   =>   "
3014                        "bbatt-delta = %d,  rfatt-delta = %d\n",
3015                        (pwr_adjust < 0 ? "-" : ""), Q52_ARG(dbm),
3016                        bbatt_delta, rfatt_delta);
3017         }
3018 #endif /* DEBUG */
3019
3020         /* So do we finally need to adjust something in hardware? */
3021         if ((rfatt_delta == 0) && (bbatt_delta == 0))
3022                 goto no_adjustment_needed;
3023
3024         /* Save the deltas for later when we adjust the power. */
3025         gphy->bbatt_delta = bbatt_delta;
3026         gphy->rfatt_delta = rfatt_delta;
3027
3028         /* We need to adjust the TX power on the device. */
3029         return B43_TXPWR_RES_NEED_ADJUST;
3030
3031 no_adjustment_needed:
3032         return B43_TXPWR_RES_DONE;
3033 }
3034
3035 static void b43_gphy_op_pwork_15sec(struct b43_wldev *dev)
3036 {
3037         struct b43_phy *phy = &dev->phy;
3038         struct b43_phy_g *gphy = phy->g;
3039
3040         b43_mac_suspend(dev);
3041         //TODO: update_aci_moving_average
3042         if (gphy->aci_enable && gphy->aci_wlan_automatic) {
3043                 if (!gphy->aci_enable && 1 /*TODO: not scanning? */ ) {
3044                         if (0 /*TODO: bunch of conditions */ ) {
3045                                 phy->ops->interf_mitigation(dev,
3046                                         B43_INTERFMODE_MANUALWLAN);
3047                         }
3048                 } else if (0 /*TODO*/) {
3049                            if (/*(aci_average > 1000) &&*/ !b43_gphy_aci_scan(dev))
3050                                 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
3051                 }
3052         } else if (gphy->interfmode == B43_INTERFMODE_NONWLAN &&
3053                    phy->rev == 1) {
3054                 //TODO: implement rev1 workaround
3055         }
3056         b43_lo_g_maintanance_work(dev);
3057         b43_mac_enable(dev);
3058 }
3059
3060 static void b43_gphy_op_pwork_60sec(struct b43_wldev *dev)
3061 {
3062         struct b43_phy *phy = &dev->phy;
3063
3064         if (!(dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI))
3065                 return;
3066
3067         b43_mac_suspend(dev);
3068         b43_calc_nrssi_slope(dev);
3069         if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) {
3070                 u8 old_chan = phy->channel;
3071
3072                 /* VCO Calibration */
3073                 if (old_chan >= 8)
3074                         b43_switch_channel(dev, 1);
3075                 else
3076                         b43_switch_channel(dev, 13);
3077                 b43_switch_channel(dev, old_chan);
3078         }
3079         b43_mac_enable(dev);
3080 }
3081
3082 const struct b43_phy_operations b43_phyops_g = {
3083         .allocate               = b43_gphy_op_allocate,
3084         .free                   = b43_gphy_op_free,
3085         .prepare_structs        = b43_gphy_op_prepare_structs,
3086         .prepare_hardware       = b43_gphy_op_prepare_hardware,
3087         .init                   = b43_gphy_op_init,
3088         .exit                   = b43_gphy_op_exit,
3089         .phy_read               = b43_gphy_op_read,
3090         .phy_write              = b43_gphy_op_write,
3091         .radio_read             = b43_gphy_op_radio_read,
3092         .radio_write            = b43_gphy_op_radio_write,
3093         .supports_hwpctl        = b43_gphy_op_supports_hwpctl,
3094         .software_rfkill        = b43_gphy_op_software_rfkill,
3095         .switch_analog          = b43_phyop_switch_analog_generic,
3096         .switch_channel         = b43_gphy_op_switch_channel,
3097         .get_default_chan       = b43_gphy_op_get_default_chan,
3098         .set_rx_antenna         = b43_gphy_op_set_rx_antenna,
3099         .interf_mitigation      = b43_gphy_op_interf_mitigation,
3100         .recalc_txpower         = b43_gphy_op_recalc_txpower,
3101         .adjust_txpower         = b43_gphy_op_adjust_txpower,
3102         .pwork_15sec            = b43_gphy_op_pwork_15sec,
3103         .pwork_60sec            = b43_gphy_op_pwork_60sec,
3104 };