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   1 /*
   2
   3   Broadcom B43 wireless driver
   4   IEEE 802.11g PHY driver
   5
   6   Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
   7   Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
   8   Copyright (c) 2005-2008 Michael Buesch <mb@bu3sch.de>
   9   Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
  10   Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>
  11
  12   This program is free software; you can redistribute it and/or modify
  13   it under the terms of the GNU General Public License as published by
  14   the Free Software Foundation; either version 2 of the License, or
  15   (at your option) any later version.
  16
  17   This program is distributed in the hope that it will be useful,
  18   but WITHOUT ANY WARRANTY; without even the implied warranty of
  19   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20   GNU General Public License for more details.
  21
  22   You should have received a copy of the GNU General Public License
  23   along with this program; see the file COPYING.  If not, write to
  24   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  25   Boston, MA 02110-1301, USA.
  26
  27 */
  28
  29 #include "b43.h"
  30 #include "phy_g.h"
  31 #include "phy_common.h"
  32 #include "lo.h"
  33 #include "main.h"
  34
  35 #include <linux/bitrev.h>
  36
  37
  38 static const s8 b43_tssi2dbm_g_table[] = {
  39         77, 77, 77, 76,
  40         76, 76, 75, 75,
  41         74, 74, 73, 73,
  42         73, 72, 72, 71,
  43         71, 70, 70, 69,
  44         68, 68, 67, 67,
  45         66, 65, 65, 64,
  46         63, 63, 62, 61,
  47         60, 59, 58, 57,
  48         56, 55, 54, 53,
  49         52, 50, 49, 47,
  50         45, 43, 40, 37,
  51         33, 28, 22, 14,
  52         5, -7, -20, -20,
  53         -20, -20, -20, -20,
  54         -20, -20, -20, -20,
  55 };
  56
  57 static const u8 b43_radio_channel_codes_bg[] = {
  58         12, 17, 22, 27,
  59         32, 37, 42, 47,
  60         52, 57, 62, 67,
  61         72, 84,
  62 };
  63
  64
  65 static void b43_calc_nrssi_threshold(struct b43_wldev *dev);
  66
  67
  68 #define bitrev4(tmp) (bitrev8(tmp) >> 4)
  69
  70
  71 /* Get the freq, as it has to be written to the device. */
  72 static inline u16 channel2freq_bg(u8 channel)
  73 {
  74         B43_WARN_ON(!(channel >= 1 && channel <= 14));
  75
  76         return b43_radio_channel_codes_bg[channel - 1];
  77 }
  78
  79 static void generate_rfatt_list(struct b43_wldev *dev,
  80                                 struct b43_rfatt_list *list)
  81 {
  82         struct b43_phy *phy = &dev->phy;
  83
  84         /* APHY.rev < 5 || GPHY.rev < 6 */
  85         static const struct b43_rfatt rfatt_0[] = {
  86                 {.att = 3,.with_padmix = 0,},
  87                 {.att = 1,.with_padmix = 0,},
  88                 {.att = 5,.with_padmix = 0,},
  89                 {.att = 7,.with_padmix = 0,},
  90                 {.att = 9,.with_padmix = 0,},
  91                 {.att = 2,.with_padmix = 0,},
  92                 {.att = 0,.with_padmix = 0,},
  93                 {.att = 4,.with_padmix = 0,},
  94                 {.att = 6,.with_padmix = 0,},
  95                 {.att = 8,.with_padmix = 0,},
  96                 {.att = 1,.with_padmix = 1,},
  97                 {.att = 2,.with_padmix = 1,},
  98                 {.att = 3,.with_padmix = 1,},
  99                 {.att = 4,.with_padmix = 1,},
 100         };
 101         /* Radio.rev == 8 && Radio.version == 0x2050 */
 102         static const struct b43_rfatt rfatt_1[] = {
 103                 {.att = 2,.with_padmix = 1,},
 104                 {.att = 4,.with_padmix = 1,},
 105                 {.att = 6,.with_padmix = 1,},
 106                 {.att = 8,.with_padmix = 1,},
 107                 {.att = 10,.with_padmix = 1,},
 108                 {.att = 12,.with_padmix = 1,},
 109                 {.att = 14,.with_padmix = 1,},
 110         };
 111         /* Otherwise */
 112         static const struct b43_rfatt rfatt_2[] = {
 113                 {.att = 0,.with_padmix = 1,},
 114                 {.att = 2,.with_padmix = 1,},
 115                 {.att = 4,.with_padmix = 1,},
 116                 {.att = 6,.with_padmix = 1,},
 117                 {.att = 8,.with_padmix = 1,},
 118                 {.att = 9,.with_padmix = 1,},
 119                 {.att = 9,.with_padmix = 1,},
 120         };
 121
 122         if (!b43_has_hardware_pctl(dev)) {
 123                 /* Software pctl */
 124                 list->list = rfatt_0;
 125                 list->len = ARRAY_SIZE(rfatt_0);
 126                 list->min_val = 0;
 127                 list->max_val = 9;
 128                 return;
 129         }
 130         if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
 131                 /* Hardware pctl */
 132                 list->list = rfatt_1;
 133                 list->len = ARRAY_SIZE(rfatt_1);
 134                 list->min_val = 0;
 135                 list->max_val = 14;
 136                 return;
 137         }
 138         /* Hardware pctl */
 139         list->list = rfatt_2;
 140         list->len = ARRAY_SIZE(rfatt_2);
 141         list->min_val = 0;
 142         list->max_val = 9;
 143 }
 144
 145 static void generate_bbatt_list(struct b43_wldev *dev,
 146                                 struct b43_bbatt_list *list)
 147 {
 148         static const struct b43_bbatt bbatt_0[] = {
 149                 {.att = 0,},
 150                 {.att = 1,},
 151                 {.att = 2,},
 152                 {.att = 3,},
 153                 {.att = 4,},
 154                 {.att = 5,},
 155                 {.att = 6,},
 156                 {.att = 7,},
 157                 {.att = 8,},
 158         };
 159
 160         list->list = bbatt_0;
 161         list->len = ARRAY_SIZE(bbatt_0);
 162         list->min_val = 0;
 163         list->max_val = 8;
 164 }
 165
 166 static void b43_shm_clear_tssi(struct b43_wldev *dev)
 167 {
 168         b43_shm_write16(dev, B43_SHM_SHARED, 0x0058, 0x7F7F);
 169         b43_shm_write16(dev, B43_SHM_SHARED, 0x005a, 0x7F7F);
 170         b43_shm_write16(dev, B43_SHM_SHARED, 0x0070, 0x7F7F);
 171         b43_shm_write16(dev, B43_SHM_SHARED, 0x0072, 0x7F7F);
 172 }
 173
 174 /* Synthetic PU workaround */
 175 static void b43_synth_pu_workaround(struct b43_wldev *dev, u8 channel)
 176 {
 177         struct b43_phy *phy = &dev->phy;
 178
 179         might_sleep();
 180
 181         if (phy->radio_ver != 0x2050 || phy->radio_rev >= 6) {
 182                 /* We do not need the workaround. */
 183                 return;
 184         }
 185
 186         if (channel <= 10) {
 187                 b43_write16(dev, B43_MMIO_CHANNEL,
 188                             channel2freq_bg(channel + 4));
 189         } else {
 190                 b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(1));
 191         }
 192         msleep(1);
 193         b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(channel));
 194 }
 195
 196 /* Set the baseband attenuation value on chip. */
 197 void b43_gphy_set_baseband_attenuation(struct b43_wldev *dev,
 198                                        u16 baseband_attenuation)
 199 {
 200         struct b43_phy *phy = &dev->phy;
 201
 202         if (phy->analog == 0) {
 203                 b43_write16(dev, B43_MMIO_PHY0, (b43_read16(dev, B43_MMIO_PHY0)
 204                                                  & 0xFFF0) |
 205                             baseband_attenuation);
 206         } else if (phy->analog > 1) {
 207                 b43_phy_write(dev, B43_PHY_DACCTL,
 208                               (b43_phy_read(dev, B43_PHY_DACCTL)
 209                                & 0xFFC3) | (baseband_attenuation << 2));
 210         } else {
 211                 b43_phy_write(dev, B43_PHY_DACCTL,
 212                               (b43_phy_read(dev, B43_PHY_DACCTL)
 213                                & 0xFF87) | (baseband_attenuation << 3));
 214         }
 215 }
 216
 217 /* Adjust the transmission power output (G-PHY) */
 218 static void b43_set_txpower_g(struct b43_wldev *dev,
 219                               const struct b43_bbatt *bbatt,
 220                               const struct b43_rfatt *rfatt, u8 tx_control)
 221 {
 222         struct b43_phy *phy = &dev->phy;
 223         struct b43_phy_g *gphy = phy->g;
 224         struct b43_txpower_lo_control *lo = gphy->lo_control;
 225         u16 bb, rf;
 226         u16 tx_bias, tx_magn;
 227
 228         bb = bbatt->att;
 229         rf = rfatt->att;
 230         tx_bias = lo->tx_bias;
 231         tx_magn = lo->tx_magn;
 232         if (unlikely(tx_bias == 0xFF))
 233                 tx_bias = 0;
 234
 235         /* Save the values for later. Use memmove, because it's valid
 236          * to pass &gphy->rfatt as rfatt pointer argument. Same for bbatt. */
 237         gphy->tx_control = tx_control;
 238         memmove(&gphy->rfatt, rfatt, sizeof(*rfatt));
 239         gphy->rfatt.with_padmix = !!(tx_control & B43_TXCTL_TXMIX);
 240         memmove(&gphy->bbatt, bbatt, sizeof(*bbatt));
 241
 242         if (b43_debug(dev, B43_DBG_XMITPOWER)) {
 243                 b43dbg(dev->wl, "Tuning TX-power to bbatt(%u), "
 244                        "rfatt(%u), tx_control(0x%02X), "
 245                        "tx_bias(0x%02X), tx_magn(0x%02X)\n",
 246                        bb, rf, tx_control, tx_bias, tx_magn);
 247         }
 248
 249         b43_gphy_set_baseband_attenuation(dev, bb);
 250         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_RFATT, rf);
 251         if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
 252                 b43_radio_write16(dev, 0x43,
 253                                   (rf & 0x000F) | (tx_control & 0x0070));
 254         } else {
 255                 b43_radio_write16(dev, 0x43, (b43_radio_read16(dev, 0x43)
 256                                               & 0xFFF0) | (rf & 0x000F));
 257                 b43_radio_write16(dev, 0x52, (b43_radio_read16(dev, 0x52)
 258                                               & ~0x0070) | (tx_control &
 259                                                             0x0070));
 260         }
 261         if (has_tx_magnification(phy)) {
 262                 b43_radio_write16(dev, 0x52, tx_magn | tx_bias);
 263         } else {
 264                 b43_radio_write16(dev, 0x52, (b43_radio_read16(dev, 0x52)
 265                                               & 0xFFF0) | (tx_bias & 0x000F));
 266         }
 267         b43_lo_g_adjust(dev);
 268 }
 269
 270 /* GPHY_TSSI_Power_Lookup_Table_Init */
 271 static void b43_gphy_tssi_power_lt_init(struct b43_wldev *dev)
 272 {
 273         struct b43_phy_g *gphy = dev->phy.g;
 274         int i;
 275         u16 value;
 276
 277         for (i = 0; i < 32; i++)
 278                 b43_ofdmtab_write16(dev, 0x3C20, i, gphy->tssi2dbm[i]);
 279         for (i = 32; i < 64; i++)
 280                 b43_ofdmtab_write16(dev, 0x3C00, i - 32, gphy->tssi2dbm[i]);
 281         for (i = 0; i < 64; i += 2) {
 282                 value = (u16) gphy->tssi2dbm[i];
 283                 value |= ((u16) gphy->tssi2dbm[i + 1]) << 8;
 284                 b43_phy_write(dev, 0x380 + (i / 2), value);
 285         }
 286 }
 287
 288 /* GPHY_Gain_Lookup_Table_Init */
 289 static void b43_gphy_gain_lt_init(struct b43_wldev *dev)
 290 {
 291         struct b43_phy *phy = &dev->phy;
 292         struct b43_phy_g *gphy = phy->g;
 293         struct b43_txpower_lo_control *lo = gphy->lo_control;
 294         u16 nr_written = 0;
 295         u16 tmp;
 296         u8 rf, bb;
 297
 298         for (rf = 0; rf < lo->rfatt_list.len; rf++) {
 299                 for (bb = 0; bb < lo->bbatt_list.len; bb++) {
 300                         if (nr_written >= 0x40)
 301                                 return;
 302                         tmp = lo->bbatt_list.list[bb].att;
 303                         tmp <<= 8;
 304                         if (phy->radio_rev == 8)
 305                                 tmp |= 0x50;
 306                         else
 307                                 tmp |= 0x40;
 308                         tmp |= lo->rfatt_list.list[rf].att;
 309                         b43_phy_write(dev, 0x3C0 + nr_written, tmp);
 310                         nr_written++;
 311                 }
 312         }
 313 }
 314
 315 static void b43_set_all_gains(struct b43_wldev *dev,
 316                               s16 first, s16 second, s16 third)
 317 {
 318         struct b43_phy *phy = &dev->phy;
 319         u16 i;
 320         u16 start = 0x08, end = 0x18;
 321         u16 tmp;
 322         u16 table;
 323
 324         if (phy->rev <= 1) {
 325                 start = 0x10;
 326                 end = 0x20;
 327         }
 328
 329         table = B43_OFDMTAB_GAINX;
 330         if (phy->rev <= 1)
 331                 table = B43_OFDMTAB_GAINX_R1;
 332         for (i = 0; i < 4; i++)
 333                 b43_ofdmtab_write16(dev, table, i, first);
 334
 335         for (i = start; i < end; i++)
 336                 b43_ofdmtab_write16(dev, table, i, second);
 337
 338         if (third != -1) {
 339                 tmp = ((u16) third << 14) | ((u16) third << 6);
 340                 b43_phy_write(dev, 0x04A0,
 341                               (b43_phy_read(dev, 0x04A0) & 0xBFBF) | tmp);
 342                 b43_phy_write(dev, 0x04A1,
 343                               (b43_phy_read(dev, 0x04A1) & 0xBFBF) | tmp);
 344                 b43_phy_write(dev, 0x04A2,
 345                               (b43_phy_read(dev, 0x04A2) & 0xBFBF) | tmp);
 346         }
 347         b43_dummy_transmission(dev);
 348 }
 349
 350 static void b43_set_original_gains(struct b43_wldev *dev)
 351 {
 352         struct b43_phy *phy = &dev->phy;
 353         u16 i, tmp;
 354         u16 table;
 355         u16 start = 0x0008, end = 0x0018;
 356
 357         if (phy->rev <= 1) {
 358                 start = 0x0010;
 359                 end = 0x0020;
 360         }
 361
 362         table = B43_OFDMTAB_GAINX;
 363         if (phy->rev <= 1)
 364                 table = B43_OFDMTAB_GAINX_R1;
 365         for (i = 0; i < 4; i++) {
 366                 tmp = (i & 0xFFFC);
 367                 tmp |= (i & 0x0001) << 1;
 368                 tmp |= (i & 0x0002) >> 1;
 369
 370                 b43_ofdmtab_write16(dev, table, i, tmp);
 371         }
 372
 373         for (i = start; i < end; i++)
 374                 b43_ofdmtab_write16(dev, table, i, i - start);
 375
 376         b43_phy_write(dev, 0x04A0,
 377                       (b43_phy_read(dev, 0x04A0) & 0xBFBF) | 0x4040);
 378         b43_phy_write(dev, 0x04A1,
 379                       (b43_phy_read(dev, 0x04A1) & 0xBFBF) | 0x4040);
 380         b43_phy_write(dev, 0x04A2,
 381                       (b43_phy_read(dev, 0x04A2) & 0xBFBF) | 0x4000);
 382         b43_dummy_transmission(dev);
 383 }
 384
 385 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
 386 static void b43_nrssi_hw_write(struct b43_wldev *dev, u16 offset, s16 val)
 387 {
 388         b43_phy_write(dev, B43_PHY_NRSSILT_CTRL, offset);
 389         b43_phy_write(dev, B43_PHY_NRSSILT_DATA, (u16) val);
 390 }
 391
 392 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
 393 static s16 b43_nrssi_hw_read(struct b43_wldev *dev, u16 offset)
 394 {
 395         u16 val;
 396
 397         b43_phy_write(dev, B43_PHY_NRSSILT_CTRL, offset);
 398         val = b43_phy_read(dev, B43_PHY_NRSSILT_DATA);
 399
 400         return (s16) val;
 401 }
 402
 403 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
 404 static void b43_nrssi_hw_update(struct b43_wldev *dev, u16 val)
 405 {
 406         u16 i;
 407         s16 tmp;
 408
 409         for (i = 0; i < 64; i++) {
 410                 tmp = b43_nrssi_hw_read(dev, i);
 411                 tmp -= val;
 412                 tmp = clamp_val(tmp, -32, 31);
 413                 b43_nrssi_hw_write(dev, i, tmp);
 414         }
 415 }
 416
 417 /* http://bcm-specs.sipsolutions.net/NRSSILookupTable */
 418 static void b43_nrssi_mem_update(struct b43_wldev *dev)
 419 {
 420         struct b43_phy_g *gphy = dev->phy.g;
 421         s16 i, delta;
 422         s32 tmp;
 423
 424         delta = 0x1F - gphy->nrssi[0];
 425         for (i = 0; i < 64; i++) {
 426                 tmp = (i - delta) * gphy->nrssislope;
 427                 tmp /= 0x10000;
 428                 tmp += 0x3A;
 429                 tmp = clamp_val(tmp, 0, 0x3F);
 430                 gphy->nrssi_lt[i] = tmp;
 431         }
 432 }
 433
 434 static void b43_calc_nrssi_offset(struct b43_wldev *dev)
 435 {
 436         struct b43_phy *phy = &dev->phy;
 437         u16 backup[20] = { 0 };
 438         s16 v47F;
 439         u16 i;
 440         u16 saved = 0xFFFF;
 441
 442         backup[0] = b43_phy_read(dev, 0x0001);
 443         backup[1] = b43_phy_read(dev, 0x0811);
 444         backup[2] = b43_phy_read(dev, 0x0812);
 445         if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
 446                 backup[3] = b43_phy_read(dev, 0x0814);
 447                 backup[4] = b43_phy_read(dev, 0x0815);
 448         }
 449         backup[5] = b43_phy_read(dev, 0x005A);
 450         backup[6] = b43_phy_read(dev, 0x0059);
 451         backup[7] = b43_phy_read(dev, 0x0058);
 452         backup[8] = b43_phy_read(dev, 0x000A);
 453         backup[9] = b43_phy_read(dev, 0x0003);
 454         backup[10] = b43_radio_read16(dev, 0x007A);
 455         backup[11] = b43_radio_read16(dev, 0x0043);
 456
 457         b43_phy_mask(dev, 0x0429, 0x7FFF);
 458         b43_phy_write(dev, 0x0001,
 459                       (b43_phy_read(dev, 0x0001) & 0x3FFF) | 0x4000);
 460         b43_phy_set(dev, 0x0811, 0x000C);
 461         b43_phy_write(dev, 0x0812,
 462                       (b43_phy_read(dev, 0x0812) & 0xFFF3) | 0x0004);
 463         b43_phy_mask(dev, 0x0802, ~(0x1 | 0x2));
 464         if (phy->rev >= 6) {
 465                 backup[12] = b43_phy_read(dev, 0x002E);
 466                 backup[13] = b43_phy_read(dev, 0x002F);
 467                 backup[14] = b43_phy_read(dev, 0x080F);
 468                 backup[15] = b43_phy_read(dev, 0x0810);
 469                 backup[16] = b43_phy_read(dev, 0x0801);
 470                 backup[17] = b43_phy_read(dev, 0x0060);
 471                 backup[18] = b43_phy_read(dev, 0x0014);
 472                 backup[19] = b43_phy_read(dev, 0x0478);
 473
 474                 b43_phy_write(dev, 0x002E, 0);
 475                 b43_phy_write(dev, 0x002F, 0);
 476                 b43_phy_write(dev, 0x080F, 0);
 477                 b43_phy_write(dev, 0x0810, 0);
 478                 b43_phy_set(dev, 0x0478, 0x0100);
 479                 b43_phy_set(dev, 0x0801, 0x0040);
 480                 b43_phy_set(dev, 0x0060, 0x0040);
 481                 b43_phy_set(dev, 0x0014, 0x0200);
 482         }
 483         b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A) | 0x0070);
 484         b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A) | 0x0080);
 485         udelay(30);
 486
 487         v47F = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
 488         if (v47F >= 0x20)
 489                 v47F -= 0x40;
 490         if (v47F == 31) {
 491                 for (i = 7; i >= 4; i--) {
 492                         b43_radio_write16(dev, 0x007B, i);
 493                         udelay(20);
 494                         v47F =
 495                             (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
 496                         if (v47F >= 0x20)
 497                                 v47F -= 0x40;
 498                         if (v47F < 31 && saved == 0xFFFF)
 499                                 saved = i;
 500                 }
 501                 if (saved == 0xFFFF)
 502                         saved = 4;
 503         } else {
 504                 b43_radio_write16(dev, 0x007A,
 505                                   b43_radio_read16(dev, 0x007A) & 0x007F);
 506                 if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
 507                         b43_phy_set(dev, 0x0814, 0x0001);
 508                         b43_phy_mask(dev, 0x0815, 0xFFFE);
 509                 }
 510                 b43_phy_set(dev, 0x0811, 0x000C);
 511                 b43_phy_set(dev, 0x0812, 0x000C);
 512                 b43_phy_set(dev, 0x0811, 0x0030);
 513                 b43_phy_set(dev, 0x0812, 0x0030);
 514                 b43_phy_write(dev, 0x005A, 0x0480);
 515                 b43_phy_write(dev, 0x0059, 0x0810);
 516                 b43_phy_write(dev, 0x0058, 0x000D);
 517                 if (phy->rev == 0) {
 518                         b43_phy_write(dev, 0x0003, 0x0122);
 519                 } else {
 520                         b43_phy_set(dev, 0x000A, 0x2000);
 521                 }
 522                 if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
 523                         b43_phy_set(dev, 0x0814, 0x0004);
 524                         b43_phy_mask(dev, 0x0815, 0xFFFB);
 525                 }
 526                 b43_phy_write(dev, 0x0003, (b43_phy_read(dev, 0x0003) & 0xFF9F)
 527                               | 0x0040);
 528                 b43_radio_write16(dev, 0x007A,
 529                                   b43_radio_read16(dev, 0x007A) | 0x000F);
 530                 b43_set_all_gains(dev, 3, 0, 1);
 531                 b43_radio_write16(dev, 0x0043, (b43_radio_read16(dev, 0x0043)
 532                                                 & 0x00F0) | 0x000F);
 533                 udelay(30);
 534                 v47F = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
 535                 if (v47F >= 0x20)
 536                         v47F -= 0x40;
 537                 if (v47F == -32) {
 538                         for (i = 0; i < 4; i++) {
 539                                 b43_radio_write16(dev, 0x007B, i);
 540                                 udelay(20);
 541                                 v47F =
 542                                     (s16) ((b43_phy_read(dev, 0x047F) >> 8) &
 543                                            0x003F);
 544                                 if (v47F >= 0x20)
 545                                         v47F -= 0x40;
 546                                 if (v47F > -31 && saved == 0xFFFF)
 547                                         saved = i;
 548                         }
 549                         if (saved == 0xFFFF)
 550                                 saved = 3;
 551                 } else
 552                         saved = 0;
 553         }
 554         b43_radio_write16(dev, 0x007B, saved);
 555
 556         if (phy->rev >= 6) {
 557                 b43_phy_write(dev, 0x002E, backup[12]);
 558                 b43_phy_write(dev, 0x002F, backup[13]);
 559                 b43_phy_write(dev, 0x080F, backup[14]);
 560                 b43_phy_write(dev, 0x0810, backup[15]);
 561         }
 562         if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
 563                 b43_phy_write(dev, 0x0814, backup[3]);
 564                 b43_phy_write(dev, 0x0815, backup[4]);
 565         }
 566         b43_phy_write(dev, 0x005A, backup[5]);
 567         b43_phy_write(dev, 0x0059, backup[6]);
 568         b43_phy_write(dev, 0x0058, backup[7]);
 569         b43_phy_write(dev, 0x000A, backup[8]);
 570         b43_phy_write(dev, 0x0003, backup[9]);
 571         b43_radio_write16(dev, 0x0043, backup[11]);
 572         b43_radio_write16(dev, 0x007A, backup[10]);
 573         b43_phy_write(dev, 0x0802, b43_phy_read(dev, 0x0802) | 0x1 | 0x2);
 574         b43_phy_set(dev, 0x0429, 0x8000);
 575         b43_set_original_gains(dev);
 576         if (phy->rev >= 6) {
 577                 b43_phy_write(dev, 0x0801, backup[16]);
 578                 b43_phy_write(dev, 0x0060, backup[17]);
 579                 b43_phy_write(dev, 0x0014, backup[18]);
 580                 b43_phy_write(dev, 0x0478, backup[19]);
 581         }
 582         b43_phy_write(dev, 0x0001, backup[0]);
 583         b43_phy_write(dev, 0x0812, backup[2]);
 584         b43_phy_write(dev, 0x0811, backup[1]);
 585 }
 586
 587 static void b43_calc_nrssi_slope(struct b43_wldev *dev)
 588 {
 589         struct b43_phy *phy = &dev->phy;
 590         struct b43_phy_g *gphy = phy->g;
 591         u16 backup[18] = { 0 };
 592         u16 tmp;
 593         s16 nrssi0, nrssi1;
 594
 595         B43_WARN_ON(phy->type != B43_PHYTYPE_G);
 596
 597         if (phy->radio_rev >= 9)
 598                 return;
 599         if (phy->radio_rev == 8)
 600                 b43_calc_nrssi_offset(dev);
 601
 602         b43_phy_mask(dev, B43_PHY_G_CRS, 0x7FFF);
 603         b43_phy_mask(dev, 0x0802, 0xFFFC);
 604         backup[7] = b43_read16(dev, 0x03E2);
 605         b43_write16(dev, 0x03E2, b43_read16(dev, 0x03E2) | 0x8000);
 606         backup[0] = b43_radio_read16(dev, 0x007A);
 607         backup[1] = b43_radio_read16(dev, 0x0052);
 608         backup[2] = b43_radio_read16(dev, 0x0043);
 609         backup[3] = b43_phy_read(dev, 0x0015);
 610         backup[4] = b43_phy_read(dev, 0x005A);
 611         backup[5] = b43_phy_read(dev, 0x0059);
 612         backup[6] = b43_phy_read(dev, 0x0058);
 613         backup[8] = b43_read16(dev, 0x03E6);
 614         backup[9] = b43_read16(dev, B43_MMIO_CHANNEL_EXT);
 615         if (phy->rev >= 3) {
 616                 backup[10] = b43_phy_read(dev, 0x002E);
 617                 backup[11] = b43_phy_read(dev, 0x002F);
 618                 backup[12] = b43_phy_read(dev, 0x080F);
 619                 backup[13] = b43_phy_read(dev, B43_PHY_G_LO_CONTROL);
 620                 backup[14] = b43_phy_read(dev, 0x0801);
 621                 backup[15] = b43_phy_read(dev, 0x0060);
 622                 backup[16] = b43_phy_read(dev, 0x0014);
 623                 backup[17] = b43_phy_read(dev, 0x0478);
 624                 b43_phy_write(dev, 0x002E, 0);
 625                 b43_phy_write(dev, B43_PHY_G_LO_CONTROL, 0);
 626                 switch (phy->rev) {
 627                 case 4:
 628                 case 6:
 629                 case 7:
 630                         b43_phy_set(dev, 0x0478, 0x0100);
 631                         b43_phy_set(dev, 0x0801, 0x0040);
 632                         break;
 633                 case 3:
 634                 case 5:
 635                         b43_phy_mask(dev, 0x0801, 0xFFBF);
 636                         break;
 637                 }
 638                 b43_phy_set(dev, 0x0060, 0x0040);
 639                 b43_phy_set(dev, 0x0014, 0x0200);
 640         }
 641         b43_radio_write16(dev, 0x007A,
 642                           b43_radio_read16(dev, 0x007A) | 0x0070);
 643         b43_set_all_gains(dev, 0, 8, 0);
 644         b43_radio_write16(dev, 0x007A,
 645                           b43_radio_read16(dev, 0x007A) & 0x00F7);
 646         if (phy->rev >= 2) {
 647                 b43_phy_write(dev, 0x0811,
 648                               (b43_phy_read(dev, 0x0811) & 0xFFCF) |
 649                               0x0030);
 650                 b43_phy_write(dev, 0x0812,
 651                               (b43_phy_read(dev, 0x0812) & 0xFFCF) |
 652                               0x0010);
 653         }
 654         b43_radio_write16(dev, 0x007A,
 655                           b43_radio_read16(dev, 0x007A) | 0x0080);
 656         udelay(20);
 657
 658         nrssi0 = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
 659         if (nrssi0 >= 0x0020)
 660                 nrssi0 -= 0x0040;
 661
 662         b43_radio_write16(dev, 0x007A,
 663                           b43_radio_read16(dev, 0x007A) & 0x007F);
 664         if (phy->rev >= 2) {
 665                 b43_phy_write(dev, 0x0003, (b43_phy_read(dev, 0x0003)
 666                                             & 0xFF9F) | 0x0040);
 667         }
 668
 669         b43_write16(dev, B43_MMIO_CHANNEL_EXT,
 670                     b43_read16(dev, B43_MMIO_CHANNEL_EXT)
 671                     | 0x2000);
 672         b43_radio_write16(dev, 0x007A,
 673                           b43_radio_read16(dev, 0x007A) | 0x000F);
 674         b43_phy_write(dev, 0x0015, 0xF330);
 675         if (phy->rev >= 2) {
 676                 b43_phy_write(dev, 0x0812,
 677                               (b43_phy_read(dev, 0x0812) & 0xFFCF) |
 678                               0x0020);
 679                 b43_phy_write(dev, 0x0811,
 680                               (b43_phy_read(dev, 0x0811) & 0xFFCF) |
 681                               0x0020);
 682         }
 683
 684         b43_set_all_gains(dev, 3, 0, 1);
 685         if (phy->radio_rev == 8) {
 686                 b43_radio_write16(dev, 0x0043, 0x001F);
 687         } else {
 688                 tmp = b43_radio_read16(dev, 0x0052) & 0xFF0F;
 689                 b43_radio_write16(dev, 0x0052, tmp | 0x0060);
 690                 tmp = b43_radio_read16(dev, 0x0043) & 0xFFF0;
 691                 b43_radio_write16(dev, 0x0043, tmp | 0x0009);
 692         }
 693         b43_phy_write(dev, 0x005A, 0x0480);
 694         b43_phy_write(dev, 0x0059, 0x0810);
 695         b43_phy_write(dev, 0x0058, 0x000D);
 696         udelay(20);
 697         nrssi1 = (s16) ((b43_phy_read(dev, 0x047F) >> 8) & 0x003F);
 698         if (nrssi1 >= 0x0020)
 699                 nrssi1 -= 0x0040;
 700         if (nrssi0 == nrssi1)
 701                 gphy->nrssislope = 0x00010000;
 702         else
 703                 gphy->nrssislope = 0x00400000 / (nrssi0 - nrssi1);
 704         if (nrssi0 >= -4) {
 705                 gphy->nrssi[0] = nrssi1;
 706                 gphy->nrssi[1] = nrssi0;
 707         }
 708         if (phy->rev >= 3) {
 709                 b43_phy_write(dev, 0x002E, backup[10]);
 710                 b43_phy_write(dev, 0x002F, backup[11]);
 711                 b43_phy_write(dev, 0x080F, backup[12]);
 712                 b43_phy_write(dev, B43_PHY_G_LO_CONTROL, backup[13]);
 713         }
 714         if (phy->rev >= 2) {
 715                 b43_phy_mask(dev, 0x0812, 0xFFCF);
 716                 b43_phy_mask(dev, 0x0811, 0xFFCF);
 717         }
 718
 719         b43_radio_write16(dev, 0x007A, backup[0]);
 720         b43_radio_write16(dev, 0x0052, backup[1]);
 721         b43_radio_write16(dev, 0x0043, backup[2]);
 722         b43_write16(dev, 0x03E2, backup[7]);
 723         b43_write16(dev, 0x03E6, backup[8]);
 724         b43_write16(dev, B43_MMIO_CHANNEL_EXT, backup[9]);
 725         b43_phy_write(dev, 0x0015, backup[3]);
 726         b43_phy_write(dev, 0x005A, backup[4]);
 727         b43_phy_write(dev, 0x0059, backup[5]);
 728         b43_phy_write(dev, 0x0058, backup[6]);
 729         b43_synth_pu_workaround(dev, phy->channel);
 730         b43_phy_set(dev, 0x0802, (0x0001 | 0x0002));
 731         b43_set_original_gains(dev);
 732         b43_phy_set(dev, B43_PHY_G_CRS, 0x8000);
 733         if (phy->rev >= 3) {
 734                 b43_phy_write(dev, 0x0801, backup[14]);
 735                 b43_phy_write(dev, 0x0060, backup[15]);
 736                 b43_phy_write(dev, 0x0014, backup[16]);
 737                 b43_phy_write(dev, 0x0478, backup[17]);
 738         }
 739         b43_nrssi_mem_update(dev);
 740         b43_calc_nrssi_threshold(dev);
 741 }
 742
 743 static void b43_calc_nrssi_threshold(struct b43_wldev *dev)
 744 {
 745         struct b43_phy *phy = &dev->phy;
 746         struct b43_phy_g *gphy = phy->g;
 747         s32 a, b;
 748         s16 tmp16;
 749         u16 tmp_u16;
 750
 751         B43_WARN_ON(phy->type != B43_PHYTYPE_G);
 752
 753         if (!phy->gmode ||
 754             !(dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI)) {
 755                 tmp16 = b43_nrssi_hw_read(dev, 0x20);
 756                 if (tmp16 >= 0x20)
 757                         tmp16 -= 0x40;
 758                 if (tmp16 < 3) {
 759                         b43_phy_write(dev, 0x048A,
 760                                       (b43_phy_read(dev, 0x048A)
 761                                        & 0xF000) | 0x09EB);
 762                 } else {
 763                         b43_phy_write(dev, 0x048A,
 764                                       (b43_phy_read(dev, 0x048A)
 765                                        & 0xF000) | 0x0AED);
 766                 }
 767         } else {
 768                 if (gphy->interfmode == B43_INTERFMODE_NONWLAN) {
 769                         a = 0xE;
 770                         b = 0xA;
 771                 } else if (!gphy->aci_wlan_automatic && gphy->aci_enable) {
 772                         a = 0x13;
 773                         b = 0x12;
 774                 } else {
 775                         a = 0xE;
 776                         b = 0x11;
 777                 }
 778
 779                 a = a * (gphy->nrssi[1] - gphy->nrssi[0]);
 780                 a += (gphy->nrssi[0] << 6);
 781                 if (a < 32)
 782                         a += 31;
 783                 else
 784                         a += 32;
 785                 a = a >> 6;
 786                 a = clamp_val(a, -31, 31);
 787
 788                 b = b * (gphy->nrssi[1] - gphy->nrssi[0]);
 789                 b += (gphy->nrssi[0] << 6);
 790                 if (b < 32)
 791                         b += 31;
 792                 else
 793                         b += 32;
 794                 b = b >> 6;
 795                 b = clamp_val(b, -31, 31);
 796
 797                 tmp_u16 = b43_phy_read(dev, 0x048A) & 0xF000;
 798                 tmp_u16 |= ((u32) b & 0x0000003F);
 799                 tmp_u16 |= (((u32) a & 0x0000003F) << 6);
 800                 b43_phy_write(dev, 0x048A, tmp_u16);
 801         }
 802 }
 803
 804 /* Stack implementation to save/restore values from the
 805  * interference mitigation code.
 806  * It is save to restore values in random order.
 807  */
 808 static void _stack_save(u32 * _stackptr, size_t * stackidx,
 809                         u8 id, u16 offset, u16 value)
 810 {
 811         u32 *stackptr = &(_stackptr[*stackidx]);
 812
 813         B43_WARN_ON(offset & 0xF000);
 814         B43_WARN_ON(id & 0xF0);
 815         *stackptr = offset;
 816         *stackptr |= ((u32) id) << 12;
 817         *stackptr |= ((u32) value) << 16;
 818         (*stackidx)++;
 819         B43_WARN_ON(*stackidx >= B43_INTERFSTACK_SIZE);
 820 }
 821
 822 static u16 _stack_restore(u32 * stackptr, u8 id, u16 offset)
 823 {
 824         size_t i;
 825
 826         B43_WARN_ON(offset & 0xF000);
 827         B43_WARN_ON(id & 0xF0);
 828         for (i = 0; i < B43_INTERFSTACK_SIZE; i++, stackptr++) {
 829                 if ((*stackptr & 0x00000FFF) != offset)
 830                         continue;
 831                 if (((*stackptr & 0x0000F000) >> 12) != id)
 832                         continue;
 833                 return ((*stackptr & 0xFFFF0000) >> 16);
 834         }
 835         B43_WARN_ON(1);
 836
 837         return 0;
 838 }
 839
 840 #define phy_stacksave(offset)                                   \
 841         do {                                                    \
 842                 _stack_save(stack, &stackidx, 0x1, (offset),    \
 843                             b43_phy_read(dev, (offset)));       \
 844         } while (0)
 845 #define phy_stackrestore(offset)                                \
 846         do {                                                    \
 847                 b43_phy_write(dev, (offset),            \
 848                                   _stack_restore(stack, 0x1,    \
 849                                                  (offset)));    \
 850         } while (0)
 851 #define radio_stacksave(offset)                                         \
 852         do {                                                            \
 853                 _stack_save(stack, &stackidx, 0x2, (offset),            \
 854                             b43_radio_read16(dev, (offset)));   \
 855         } while (0)
 856 #define radio_stackrestore(offset)                                      \
 857         do {                                                            \
 858                 b43_radio_write16(dev, (offset),                        \
 859                                       _stack_restore(stack, 0x2,        \
 860                                                      (offset)));        \
 861         } while (0)
 862 #define ofdmtab_stacksave(table, offset)                        \
 863         do {                                                    \
 864                 _stack_save(stack, &stackidx, 0x3, (offset)|(table),    \
 865                             b43_ofdmtab_read16(dev, (table), (offset)));        \
 866         } while (0)
 867 #define ofdmtab_stackrestore(table, offset)                     \
 868         do {                                                    \
 869                 b43_ofdmtab_write16(dev, (table),       (offset),       \
 870                                   _stack_restore(stack, 0x3,    \
 871                                                  (offset)|(table)));    \
 872         } while (0)
 873
 874 static void
 875 b43_radio_interference_mitigation_enable(struct b43_wldev *dev, int mode)
 876 {
 877         struct b43_phy *phy = &dev->phy;
 878         struct b43_phy_g *gphy = phy->g;
 879         u16 tmp, flipped;
 880         size_t stackidx = 0;
 881         u32 *stack = gphy->interfstack;
 882
 883         switch (mode) {
 884         case B43_INTERFMODE_NONWLAN:
 885                 if (phy->rev != 1) {
 886                         b43_phy_set(dev, 0x042B, 0x0800);
 887                         b43_phy_mask(dev, B43_PHY_G_CRS, ~0x4000);
 888                         break;
 889                 }
 890                 radio_stacksave(0x0078);
 891                 tmp = (b43_radio_read16(dev, 0x0078) & 0x001E);
 892                 B43_WARN_ON(tmp > 15);
 893                 flipped = bitrev4(tmp);
 894                 if (flipped < 10 && flipped >= 8)
 895                         flipped = 7;
 896                 else if (flipped >= 10)
 897                         flipped -= 3;
 898                 flipped = (bitrev4(flipped) << 1) | 0x0020;
 899                 b43_radio_write16(dev, 0x0078, flipped);
 900
 901                 b43_calc_nrssi_threshold(dev);
 902
 903                 phy_stacksave(0x0406);
 904                 b43_phy_write(dev, 0x0406, 0x7E28);
 905
 906                 b43_phy_set(dev, 0x042B, 0x0800);
 907                 b43_phy_set(dev, B43_PHY_RADIO_BITFIELD, 0x1000);
 908
 909                 phy_stacksave(0x04A0);
 910                 b43_phy_write(dev, 0x04A0,
 911                               (b43_phy_read(dev, 0x04A0) & 0xC0C0) | 0x0008);
 912                 phy_stacksave(0x04A1);
 913                 b43_phy_write(dev, 0x04A1,
 914                               (b43_phy_read(dev, 0x04A1) & 0xC0C0) | 0x0605);
 915                 phy_stacksave(0x04A2);
 916                 b43_phy_write(dev, 0x04A2,
 917                               (b43_phy_read(dev, 0x04A2) & 0xC0C0) | 0x0204);
 918                 phy_stacksave(0x04A8);
 919                 b43_phy_write(dev, 0x04A8,
 920                               (b43_phy_read(dev, 0x04A8) & 0xC0C0) | 0x0803);
 921                 phy_stacksave(0x04AB);
 922                 b43_phy_write(dev, 0x04AB,
 923                               (b43_phy_read(dev, 0x04AB) & 0xC0C0) | 0x0605);
 924
 925                 phy_stacksave(0x04A7);
 926                 b43_phy_write(dev, 0x04A7, 0x0002);
 927                 phy_stacksave(0x04A3);
 928                 b43_phy_write(dev, 0x04A3, 0x287A);
 929                 phy_stacksave(0x04A9);
 930                 b43_phy_write(dev, 0x04A9, 0x2027);
 931                 phy_stacksave(0x0493);
 932                 b43_phy_write(dev, 0x0493, 0x32F5);
 933                 phy_stacksave(0x04AA);
 934                 b43_phy_write(dev, 0x04AA, 0x2027);
 935                 phy_stacksave(0x04AC);
 936                 b43_phy_write(dev, 0x04AC, 0x32F5);
 937                 break;
 938         case B43_INTERFMODE_MANUALWLAN:
 939                 if (b43_phy_read(dev, 0x0033) & 0x0800)
 940                         break;
 941
 942                 gphy->aci_enable = 1;
 943
 944                 phy_stacksave(B43_PHY_RADIO_BITFIELD);
 945                 phy_stacksave(B43_PHY_G_CRS);
 946                 if (phy->rev < 2) {
 947                         phy_stacksave(0x0406);
 948                 } else {
 949                         phy_stacksave(0x04C0);
 950                         phy_stacksave(0x04C1);
 951                 }
 952                 phy_stacksave(0x0033);
 953                 phy_stacksave(0x04A7);
 954                 phy_stacksave(0x04A3);
 955                 phy_stacksave(0x04A9);
 956                 phy_stacksave(0x04AA);
 957                 phy_stacksave(0x04AC);
 958                 phy_stacksave(0x0493);
 959                 phy_stacksave(0x04A1);
 960                 phy_stacksave(0x04A0);
 961                 phy_stacksave(0x04A2);
 962                 phy_stacksave(0x048A);
 963                 phy_stacksave(0x04A8);
 964                 phy_stacksave(0x04AB);
 965                 if (phy->rev == 2) {
 966                         phy_stacksave(0x04AD);
 967                         phy_stacksave(0x04AE);
 968                 } else if (phy->rev >= 3) {
 969                         phy_stacksave(0x04AD);
 970                         phy_stacksave(0x0415);
 971                         phy_stacksave(0x0416);
 972                         phy_stacksave(0x0417);
 973                         ofdmtab_stacksave(0x1A00, 0x2);
 974                         ofdmtab_stacksave(0x1A00, 0x3);
 975                 }
 976                 phy_stacksave(0x042B);
 977                 phy_stacksave(0x048C);
 978
 979                 b43_phy_mask(dev, B43_PHY_RADIO_BITFIELD, ~0x1000);
 980                 b43_phy_write(dev, B43_PHY_G_CRS,
 981                               (b43_phy_read(dev, B43_PHY_G_CRS)
 982                                & 0xFFFC) | 0x0002);
 983
 984                 b43_phy_write(dev, 0x0033, 0x0800);
 985                 b43_phy_write(dev, 0x04A3, 0x2027);
 986                 b43_phy_write(dev, 0x04A9, 0x1CA8);
 987                 b43_phy_write(dev, 0x0493, 0x287A);
 988                 b43_phy_write(dev, 0x04AA, 0x1CA8);
 989                 b43_phy_write(dev, 0x04AC, 0x287A);
 990
 991                 b43_phy_write(dev, 0x04A0, (b43_phy_read(dev, 0x04A0)
 992                                             & 0xFFC0) | 0x001A);
 993                 b43_phy_write(dev, 0x04A7, 0x000D);
 994
 995                 if (phy->rev < 2) {
 996                         b43_phy_write(dev, 0x0406, 0xFF0D);
 997                 } else if (phy->rev == 2) {
 998                         b43_phy_write(dev, 0x04C0, 0xFFFF);
 999                         b43_phy_write(dev, 0x04C1, 0x00A9);
1000                 } else {
1001                         b43_phy_write(dev, 0x04C0, 0x00C1);
1002                         b43_phy_write(dev, 0x04C1, 0x0059);
1003                 }
1004
1005                 b43_phy_write(dev, 0x04A1, (b43_phy_read(dev, 0x04A1)
1006                                             & 0xC0FF) | 0x1800);
1007                 b43_phy_write(dev, 0x04A1, (b43_phy_read(dev, 0x04A1)
1008                                             & 0xFFC0) | 0x0015);
1009                 b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
1010                                             & 0xCFFF) | 0x1000);
1011                 b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
1012                                             & 0xF0FF) | 0x0A00);
1013                 b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
1014                                             & 0xCFFF) | 0x1000);
1015                 b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
1016                                             & 0xF0FF) | 0x0800);
1017                 b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
1018                                             & 0xFFCF) | 0x0010);
1019                 b43_phy_write(dev, 0x04AB, (b43_phy_read(dev, 0x04AB)
1020                                             & 0xFFF0) | 0x0005);
1021                 b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
1022                                             & 0xFFCF) | 0x0010);
1023                 b43_phy_write(dev, 0x04A8, (b43_phy_read(dev, 0x04A8)
1024                                             & 0xFFF0) | 0x0006);
1025                 b43_phy_write(dev, 0x04A2, (b43_phy_read(dev, 0x04A2)
1026                                             & 0xF0FF) | 0x0800);
1027                 b43_phy_write(dev, 0x04A0, (b43_phy_read(dev, 0x04A0)
1028                                             & 0xF0FF) | 0x0500);
1029                 b43_phy_write(dev, 0x04A2, (b43_phy_read(dev, 0x04A2)
1030                                             & 0xFFF0) | 0x000B);
1031
1032                 if (phy->rev >= 3) {
1033                         b43_phy_mask(dev, 0x048A, ~0x8000);
1034                         b43_phy_write(dev, 0x0415, (b43_phy_read(dev, 0x0415)
1035                                                     & 0x8000) | 0x36D8);
1036                         b43_phy_write(dev, 0x0416, (b43_phy_read(dev, 0x0416)
1037                                                     & 0x8000) | 0x36D8);
1038                         b43_phy_write(dev, 0x0417, (b43_phy_read(dev, 0x0417)
1039                                                     & 0xFE00) | 0x016D);
1040                 } else {
1041                         b43_phy_set(dev, 0x048A, 0x1000);
1042                         b43_phy_write(dev, 0x048A, (b43_phy_read(dev, 0x048A)
1043                                                     & 0x9FFF) | 0x2000);
1044                         b43_hf_write(dev, b43_hf_read(dev) | B43_HF_ACIW);
1045                 }
1046                 if (phy->rev >= 2) {
1047                         b43_phy_set(dev, 0x042B, 0x0800);
1048                 }
1049                 b43_phy_write(dev, 0x048C, (b43_phy_read(dev, 0x048C)
1050                                             & 0xF0FF) | 0x0200);
1051                 if (phy->rev == 2) {
1052                         b43_phy_write(dev, 0x04AE, (b43_phy_read(dev, 0x04AE)
1053                                                     & 0xFF00) | 0x007F);
1054                         b43_phy_write(dev, 0x04AD, (b43_phy_read(dev, 0x04AD)
1055                                                     & 0x00FF) | 0x1300);
1056                 } else if (phy->rev >= 6) {
1057                         b43_ofdmtab_write16(dev, 0x1A00, 0x3, 0x007F);
1058                         b43_ofdmtab_write16(dev, 0x1A00, 0x2, 0x007F);
1059                         b43_phy_mask(dev, 0x04AD, 0x00FF);
1060                 }
1061                 b43_calc_nrssi_slope(dev);
1062                 break;
1063         default:
1064                 B43_WARN_ON(1);
1065         }
1066 }
1067
1068 static void
1069 b43_radio_interference_mitigation_disable(struct b43_wldev *dev, int mode)
1070 {
1071         struct b43_phy *phy = &dev->phy;
1072         struct b43_phy_g *gphy = phy->g;
1073         u32 *stack = gphy->interfstack;
1074
1075         switch (mode) {
1076         case B43_INTERFMODE_NONWLAN:
1077                 if (phy->rev != 1) {
1078                         b43_phy_mask(dev, 0x042B, ~0x0800);
1079                         b43_phy_set(dev, B43_PHY_G_CRS, 0x4000);
1080                         break;
1081                 }
1082                 radio_stackrestore(0x0078);
1083                 b43_calc_nrssi_threshold(dev);
1084                 phy_stackrestore(0x0406);
1085                 b43_phy_mask(dev, 0x042B, ~0x0800);
1086                 if (!dev->bad_frames_preempt) {
1087                         b43_phy_mask(dev, B43_PHY_RADIO_BITFIELD, ~(1 << 11));
1088                 }
1089                 b43_phy_set(dev, B43_PHY_G_CRS, 0x4000);
1090                 phy_stackrestore(0x04A0);
1091                 phy_stackrestore(0x04A1);
1092                 phy_stackrestore(0x04A2);
1093                 phy_stackrestore(0x04A8);
1094                 phy_stackrestore(0x04AB);
1095                 phy_stackrestore(0x04A7);
1096                 phy_stackrestore(0x04A3);
1097                 phy_stackrestore(0x04A9);
1098                 phy_stackrestore(0x0493);
1099                 phy_stackrestore(0x04AA);
1100                 phy_stackrestore(0x04AC);
1101                 break;
1102         case B43_INTERFMODE_MANUALWLAN:
1103                 if (!(b43_phy_read(dev, 0x0033) & 0x0800))
1104                         break;
1105
1106                 gphy->aci_enable = 0;
1107
1108                 phy_stackrestore(B43_PHY_RADIO_BITFIELD);
1109                 phy_stackrestore(B43_PHY_G_CRS);
1110                 phy_stackrestore(0x0033);
1111                 phy_stackrestore(0x04A3);
1112                 phy_stackrestore(0x04A9);
1113                 phy_stackrestore(0x0493);
1114                 phy_stackrestore(0x04AA);
1115                 phy_stackrestore(0x04AC);
1116                 phy_stackrestore(0x04A0);
1117                 phy_stackrestore(0x04A7);
1118                 if (phy->rev >= 2) {
1119                         phy_stackrestore(0x04C0);
1120                         phy_stackrestore(0x04C1);
1121                 } else
1122                         phy_stackrestore(0x0406);
1123                 phy_stackrestore(0x04A1);
1124                 phy_stackrestore(0x04AB);
1125                 phy_stackrestore(0x04A8);
1126                 if (phy->rev == 2) {
1127                         phy_stackrestore(0x04AD);
1128                         phy_stackrestore(0x04AE);
1129                 } else if (phy->rev >= 3) {
1130                         phy_stackrestore(0x04AD);
1131                         phy_stackrestore(0x0415);
1132                         phy_stackrestore(0x0416);
1133                         phy_stackrestore(0x0417);
1134                         ofdmtab_stackrestore(0x1A00, 0x2);
1135                         ofdmtab_stackrestore(0x1A00, 0x3);
1136                 }
1137                 phy_stackrestore(0x04A2);
1138                 phy_stackrestore(0x048A);
1139                 phy_stackrestore(0x042B);
1140                 phy_stackrestore(0x048C);
1141                 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_ACIW);
1142                 b43_calc_nrssi_slope(dev);
1143                 break;
1144         default:
1145                 B43_WARN_ON(1);
1146         }
1147 }
1148
1149 #undef phy_stacksave
1150 #undef phy_stackrestore
1151 #undef radio_stacksave
1152 #undef radio_stackrestore
1153 #undef ofdmtab_stacksave
1154 #undef ofdmtab_stackrestore
1155
1156 static u16 b43_radio_core_calibration_value(struct b43_wldev *dev)
1157 {
1158         u16 reg, index, ret;
1159
1160         static const u8 rcc_table[] = {
1161                 0x02, 0x03, 0x01, 0x0F,
1162                 0x06, 0x07, 0x05, 0x0F,
1163                 0x0A, 0x0B, 0x09, 0x0F,
1164                 0x0E, 0x0F, 0x0D, 0x0F,
1165         };
1166
1167         reg = b43_radio_read16(dev, 0x60);
1168         index = (reg & 0x001E) >> 1;
1169         ret = rcc_table[index] << 1;
1170         ret |= (reg & 0x0001);
1171         ret |= 0x0020;
1172
1173         return ret;
1174 }
1175
1176 #define LPD(L, P, D)    (((L) << 2) | ((P) << 1) | ((D) << 0))
1177 static u16 radio2050_rfover_val(struct b43_wldev *dev,
1178                                 u16 phy_register, unsigned int lpd)
1179 {
1180         struct b43_phy *phy = &dev->phy;
1181         struct b43_phy_g *gphy = phy->g;
1182         struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
1183
1184         if (!phy->gmode)
1185                 return 0;
1186
1187         if (has_loopback_gain(phy)) {
1188                 int max_lb_gain = gphy->max_lb_gain;
1189                 u16 extlna;
1190                 u16 i;
1191
1192                 if (phy->radio_rev == 8)
1193                         max_lb_gain += 0x3E;
1194                 else
1195                         max_lb_gain += 0x26;
1196                 if (max_lb_gain >= 0x46) {
1197                         extlna = 0x3000;
1198                         max_lb_gain -= 0x46;
1199                 } else if (max_lb_gain >= 0x3A) {
1200                         extlna = 0x1000;
1201                         max_lb_gain -= 0x3A;
1202                 } else if (max_lb_gain >= 0x2E) {
1203                         extlna = 0x2000;
1204                         max_lb_gain -= 0x2E;
1205                 } else {
1206                         extlna = 0;
1207                         max_lb_gain -= 0x10;
1208                 }
1209
1210                 for (i = 0; i < 16; i++) {
1211                         max_lb_gain -= (i * 6);
1212                         if (max_lb_gain < 6)
1213                                 break;
1214                 }
1215
1216                 if ((phy->rev < 7) ||
1217                     !(sprom->boardflags_lo & B43_BFL_EXTLNA)) {
1218                         if (phy_register == B43_PHY_RFOVER) {
1219                                 return 0x1B3;
1220                         } else if (phy_register == B43_PHY_RFOVERVAL) {
1221                                 extlna |= (i << 8);
1222                                 switch (lpd) {
1223                                 case LPD(0, 1, 1):
1224                                         return 0x0F92;
1225                                 case LPD(0, 0, 1):
1226                                 case LPD(1, 0, 1):
1227                                         return (0x0092 | extlna);
1228                                 case LPD(1, 0, 0):
1229                                         return (0x0093 | extlna);
1230                                 }
1231                                 B43_WARN_ON(1);
1232                         }
1233                         B43_WARN_ON(1);
1234                 } else {
1235                         if (phy_register == B43_PHY_RFOVER) {
1236                                 return 0x9B3;
1237                         } else if (phy_register == B43_PHY_RFOVERVAL) {
1238                                 if (extlna)
1239                                         extlna |= 0x8000;
1240                                 extlna |= (i << 8);
1241                                 switch (lpd) {
1242                                 case LPD(0, 1, 1):
1243                                         return 0x8F92;
1244                                 case LPD(0, 0, 1):
1245                                         return (0x8092 | extlna);
1246                                 case LPD(1, 0, 1):
1247                                         return (0x2092 | extlna);
1248                                 case LPD(1, 0, 0):
1249                                         return (0x2093 | extlna);
1250                                 }
1251                                 B43_WARN_ON(1);
1252                         }
1253                         B43_WARN_ON(1);
1254                 }
1255         } else {
1256                 if ((phy->rev < 7) ||
1257                     !(sprom->boardflags_lo & B43_BFL_EXTLNA)) {
1258                         if (phy_register == B43_PHY_RFOVER) {
1259                                 return 0x1B3;
1260                         } else if (phy_register == B43_PHY_RFOVERVAL) {
1261                                 switch (lpd) {
1262                                 case LPD(0, 1, 1):
1263                                         return 0x0FB2;
1264                                 case LPD(0, 0, 1):
1265                                         return 0x00B2;
1266                                 case LPD(1, 0, 1):
1267                                         return 0x30B2;
1268                                 case LPD(1, 0, 0):
1269                                         return 0x30B3;
1270                                 }
1271                                 B43_WARN_ON(1);
1272                         }
1273                         B43_WARN_ON(1);
1274                 } else {
1275                         if (phy_register == B43_PHY_RFOVER) {
1276                                 return 0x9B3;
1277                         } else if (phy_register == B43_PHY_RFOVERVAL) {
1278                                 switch (lpd) {
1279                                 case LPD(0, 1, 1):
1280                                         return 0x8FB2;
1281                                 case LPD(0, 0, 1):
1282                                         return 0x80B2;
1283                                 case LPD(1, 0, 1):
1284                                         return 0x20B2;
1285                                 case LPD(1, 0, 0):
1286                                         return 0x20B3;
1287                                 }
1288                                 B43_WARN_ON(1);
1289                         }
1290                         B43_WARN_ON(1);
1291                 }
1292         }
1293         return 0;
1294 }
1295
1296 struct init2050_saved_values {
1297         /* Core registers */
1298         u16 reg_3EC;
1299         u16 reg_3E6;
1300         u16 reg_3F4;
1301         /* Radio registers */
1302         u16 radio_43;
1303         u16 radio_51;
1304         u16 radio_52;
1305         /* PHY registers */
1306         u16 phy_pgactl;
1307         u16 phy_cck_5A;
1308         u16 phy_cck_59;
1309         u16 phy_cck_58;
1310         u16 phy_cck_30;
1311         u16 phy_rfover;
1312         u16 phy_rfoverval;
1313         u16 phy_analogover;
1314         u16 phy_analogoverval;
1315         u16 phy_crs0;
1316         u16 phy_classctl;
1317         u16 phy_lo_mask;
1318         u16 phy_lo_ctl;
1319         u16 phy_syncctl;
1320 };
1321
1322 static u16 b43_radio_init2050(struct b43_wldev *dev)
1323 {
1324         struct b43_phy *phy = &dev->phy;
1325         struct init2050_saved_values sav;
1326         u16 rcc;
1327         u16 radio78;
1328         u16 ret;
1329         u16 i, j;
1330         u32 tmp1 = 0, tmp2 = 0;
1331
1332         memset(&sav, 0, sizeof(sav));   /* get rid of "may be used uninitialized..." */
1333
1334         sav.radio_43 = b43_radio_read16(dev, 0x43);
1335         sav.radio_51 = b43_radio_read16(dev, 0x51);
1336         sav.radio_52 = b43_radio_read16(dev, 0x52);
1337         sav.phy_pgactl = b43_phy_read(dev, B43_PHY_PGACTL);
1338         sav.phy_cck_5A = b43_phy_read(dev, B43_PHY_CCK(0x5A));
1339         sav.phy_cck_59 = b43_phy_read(dev, B43_PHY_CCK(0x59));
1340         sav.phy_cck_58 = b43_phy_read(dev, B43_PHY_CCK(0x58));
1341
1342         if (phy->type == B43_PHYTYPE_B) {
1343                 sav.phy_cck_30 = b43_phy_read(dev, B43_PHY_CCK(0x30));
1344                 sav.reg_3EC = b43_read16(dev, 0x3EC);
1345
1346                 b43_phy_write(dev, B43_PHY_CCK(0x30), 0xFF);
1347                 b43_write16(dev, 0x3EC, 0x3F3F);
1348         } else if (phy->gmode || phy->rev >= 2) {
1349                 sav.phy_rfover = b43_phy_read(dev, B43_PHY_RFOVER);
1350                 sav.phy_rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL);
1351                 sav.phy_analogover = b43_phy_read(dev, B43_PHY_ANALOGOVER);
1352                 sav.phy_analogoverval =
1353                     b43_phy_read(dev, B43_PHY_ANALOGOVERVAL);
1354                 sav.phy_crs0 = b43_phy_read(dev, B43_PHY_CRS0);
1355                 sav.phy_classctl = b43_phy_read(dev, B43_PHY_CLASSCTL);
1356
1357                 b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0003);
1358                 b43_phy_mask(dev, B43_PHY_ANALOGOVERVAL, 0xFFFC);
1359                 b43_phy_mask(dev, B43_PHY_CRS0, 0x7FFF);
1360                 b43_phy_mask(dev, B43_PHY_CLASSCTL, 0xFFFC);
1361                 if (has_loopback_gain(phy)) {
1362                         sav.phy_lo_mask = b43_phy_read(dev, B43_PHY_LO_MASK);
1363                         sav.phy_lo_ctl = b43_phy_read(dev, B43_PHY_LO_CTL);
1364
1365                         if (phy->rev >= 3)
1366                                 b43_phy_write(dev, B43_PHY_LO_MASK, 0xC020);
1367                         else
1368                                 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8020);
1369                         b43_phy_write(dev, B43_PHY_LO_CTL, 0);
1370                 }
1371
1372                 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1373                               radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
1374                                                    LPD(0, 1, 1)));
1375                 b43_phy_write(dev, B43_PHY_RFOVER,
1376                               radio2050_rfover_val(dev, B43_PHY_RFOVER, 0));
1377         }
1378         b43_write16(dev, 0x3E2, b43_read16(dev, 0x3E2) | 0x8000);
1379
1380         sav.phy_syncctl = b43_phy_read(dev, B43_PHY_SYNCCTL);
1381         b43_phy_mask(dev, B43_PHY_SYNCCTL, 0xFF7F);
1382         sav.reg_3E6 = b43_read16(dev, 0x3E6);
1383         sav.reg_3F4 = b43_read16(dev, 0x3F4);
1384
1385         if (phy->analog == 0) {
1386                 b43_write16(dev, 0x03E6, 0x0122);
1387         } else {
1388                 if (phy->analog >= 2) {
1389                         b43_phy_write(dev, B43_PHY_CCK(0x03),
1390                                       (b43_phy_read(dev, B43_PHY_CCK(0x03))
1391                                        & 0xFFBF) | 0x40);
1392                 }
1393                 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
1394                             (b43_read16(dev, B43_MMIO_CHANNEL_EXT) | 0x2000));
1395         }
1396
1397         rcc = b43_radio_core_calibration_value(dev);
1398
1399         if (phy->type == B43_PHYTYPE_B)
1400                 b43_radio_write16(dev, 0x78, 0x26);
1401         if (phy->gmode || phy->rev >= 2) {
1402                 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1403                               radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
1404                                                    LPD(0, 1, 1)));
1405         }
1406         b43_phy_write(dev, B43_PHY_PGACTL, 0xBFAF);
1407         b43_phy_write(dev, B43_PHY_CCK(0x2B), 0x1403);
1408         if (phy->gmode || phy->rev >= 2) {
1409                 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1410                               radio2050_rfover_val(dev, B43_PHY_RFOVERVAL,
1411                                                    LPD(0, 0, 1)));
1412         }
1413         b43_phy_write(dev, B43_PHY_PGACTL, 0xBFA0);
1414         b43_radio_write16(dev, 0x51, b43_radio_read16(dev, 0x51)
1415                           | 0x0004);
1416         if (phy->radio_rev == 8) {
1417                 b43_radio_write16(dev, 0x43, 0x1F);
1418         } else {
1419                 b43_radio_write16(dev, 0x52, 0);
1420                 b43_radio_write16(dev, 0x43, (b43_radio_read16(dev, 0x43)
1421                                               & 0xFFF0) | 0x0009);
1422         }
1423         b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
1424
1425         for (i = 0; i < 16; i++) {
1426                 b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0480);
1427                 b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810);
1428                 b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D);
1429                 if (phy->gmode || phy->rev >= 2) {
1430                         b43_phy_write(dev, B43_PHY_RFOVERVAL,
1431                                       radio2050_rfover_val(dev,
1432                                                            B43_PHY_RFOVERVAL,
1433                                                            LPD(1, 0, 1)));
1434                 }
1435                 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
1436                 udelay(10);
1437                 if (phy->gmode || phy->rev >= 2) {
1438                         b43_phy_write(dev, B43_PHY_RFOVERVAL,
1439                                       radio2050_rfover_val(dev,
1440                                                            B43_PHY_RFOVERVAL,
1441                                                            LPD(1, 0, 1)));
1442                 }
1443                 b43_phy_write(dev, B43_PHY_PGACTL, 0xEFB0);
1444                 udelay(10);
1445                 if (phy->gmode || phy->rev >= 2) {
1446                         b43_phy_write(dev, B43_PHY_RFOVERVAL,
1447                                       radio2050_rfover_val(dev,
1448                                                            B43_PHY_RFOVERVAL,
1449                                                            LPD(1, 0, 0)));
1450                 }
1451                 b43_phy_write(dev, B43_PHY_PGACTL, 0xFFF0);
1452                 udelay(20);
1453                 tmp1 += b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
1454                 b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
1455                 if (phy->gmode || phy->rev >= 2) {
1456                         b43_phy_write(dev, B43_PHY_RFOVERVAL,
1457                                       radio2050_rfover_val(dev,
1458                                                            B43_PHY_RFOVERVAL,
1459                                                            LPD(1, 0, 1)));
1460                 }
1461                 b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
1462         }
1463         udelay(10);
1464
1465         b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
1466         tmp1++;
1467         tmp1 >>= 9;
1468
1469         for (i = 0; i < 16; i++) {
1470                 radio78 = (bitrev4(i) << 1) | 0x0020;
1471                 b43_radio_write16(dev, 0x78, radio78);
1472                 udelay(10);
1473                 for (j = 0; j < 16; j++) {
1474                         b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0D80);
1475                         b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810);
1476                         b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D);
1477                         if (phy->gmode || phy->rev >= 2) {
1478                                 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1479                                               radio2050_rfover_val(dev,
1480                                                                    B43_PHY_RFOVERVAL,
1481                                                                    LPD(1, 0,
1482                                                                        1)));
1483                         }
1484                         b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
1485                         udelay(10);
1486                         if (phy->gmode || phy->rev >= 2) {
1487                                 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1488                                               radio2050_rfover_val(dev,
1489                                                                    B43_PHY_RFOVERVAL,
1490                                                                    LPD(1, 0,
1491                                                                        1)));
1492                         }
1493                         b43_phy_write(dev, B43_PHY_PGACTL, 0xEFB0);
1494                         udelay(10);
1495                         if (phy->gmode || phy->rev >= 2) {
1496                                 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1497                                               radio2050_rfover_val(dev,
1498                                                                    B43_PHY_RFOVERVAL,
1499                                                                    LPD(1, 0,
1500                                                                        0)));
1501                         }
1502                         b43_phy_write(dev, B43_PHY_PGACTL, 0xFFF0);
1503                         udelay(10);
1504                         tmp2 += b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
1505                         b43_phy_write(dev, B43_PHY_CCK(0x58), 0);
1506                         if (phy->gmode || phy->rev >= 2) {
1507                                 b43_phy_write(dev, B43_PHY_RFOVERVAL,
1508                                               radio2050_rfover_val(dev,
1509                                                                    B43_PHY_RFOVERVAL,
1510                                                                    LPD(1, 0,
1511                                                                        1)));
1512                         }
1513                         b43_phy_write(dev, B43_PHY_PGACTL, 0xAFB0);
1514                 }
1515                 tmp2++;
1516                 tmp2 >>= 8;
1517                 if (tmp1 < tmp2)
1518                         break;
1519         }
1520
1521         /* Restore the registers */
1522         b43_phy_write(dev, B43_PHY_PGACTL, sav.phy_pgactl);
1523         b43_radio_write16(dev, 0x51, sav.radio_51);
1524         b43_radio_write16(dev, 0x52, sav.radio_52);
1525         b43_radio_write16(dev, 0x43, sav.radio_43);
1526         b43_phy_write(dev, B43_PHY_CCK(0x5A), sav.phy_cck_5A);
1527         b43_phy_write(dev, B43_PHY_CCK(0x59), sav.phy_cck_59);
1528         b43_phy_write(dev, B43_PHY_CCK(0x58), sav.phy_cck_58);
1529         b43_write16(dev, 0x3E6, sav.reg_3E6);
1530         if (phy->analog != 0)
1531                 b43_write16(dev, 0x3F4, sav.reg_3F4);
1532         b43_phy_write(dev, B43_PHY_SYNCCTL, sav.phy_syncctl);
1533         b43_synth_pu_workaround(dev, phy->channel);
1534         if (phy->type == B43_PHYTYPE_B) {
1535                 b43_phy_write(dev, B43_PHY_CCK(0x30), sav.phy_cck_30);
1536                 b43_write16(dev, 0x3EC, sav.reg_3EC);
1537         } else if (phy->gmode) {
1538                 b43_write16(dev, B43_MMIO_PHY_RADIO,
1539                             b43_read16(dev, B43_MMIO_PHY_RADIO)
1540                             & 0x7FFF);
1541                 b43_phy_write(dev, B43_PHY_RFOVER, sav.phy_rfover);
1542                 b43_phy_write(dev, B43_PHY_RFOVERVAL, sav.phy_rfoverval);
1543                 b43_phy_write(dev, B43_PHY_ANALOGOVER, sav.phy_analogover);
1544                 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL,
1545                               sav.phy_analogoverval);
1546                 b43_phy_write(dev, B43_PHY_CRS0, sav.phy_crs0);
1547                 b43_phy_write(dev, B43_PHY_CLASSCTL, sav.phy_classctl);
1548                 if (has_loopback_gain(phy)) {
1549                         b43_phy_write(dev, B43_PHY_LO_MASK, sav.phy_lo_mask);
1550                         b43_phy_write(dev, B43_PHY_LO_CTL, sav.phy_lo_ctl);
1551                 }
1552         }
1553         if (i > 15)
1554                 ret = radio78;
1555         else
1556                 ret = rcc;
1557
1558         return ret;
1559 }
1560
1561 static void b43_phy_initb5(struct b43_wldev *dev)
1562 {
1563         struct ssb_bus *bus = dev->dev->bus;
1564         struct b43_phy *phy = &dev->phy;
1565         struct b43_phy_g *gphy = phy->g;
1566         u16 offset, value;
1567         u8 old_channel;
1568
1569         if (phy->analog == 1) {
1570                 b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A)
1571                                   | 0x0050);
1572         }
1573         if ((bus->boardinfo.vendor != SSB_BOARDVENDOR_BCM) &&
1574             (bus->boardinfo.type != SSB_BOARD_BU4306)) {
1575                 value = 0x2120;
1576                 for (offset = 0x00A8; offset < 0x00C7; offset++) {
1577                         b43_phy_write(dev, offset, value);
1578                         value += 0x202;
1579                 }
1580         }
1581         b43_phy_write(dev, 0x0035, (b43_phy_read(dev, 0x0035) & 0xF0FF)
1582                       | 0x0700);
1583         if (phy->radio_ver == 0x2050)
1584                 b43_phy_write(dev, 0x0038, 0x0667);
1585
1586         if (phy->gmode || phy->rev >= 2) {
1587                 if (phy->radio_ver == 0x2050) {
1588                         b43_radio_write16(dev, 0x007A,
1589                                           b43_radio_read16(dev, 0x007A)
1590                                           | 0x0020);
1591                         b43_radio_write16(dev, 0x0051,
1592                                           b43_radio_read16(dev, 0x0051)
1593                                           | 0x0004);
1594                 }
1595                 b43_write16(dev, B43_MMIO_PHY_RADIO, 0x0000);
1596
1597                 b43_phy_set(dev, 0x0802, 0x0100);
1598                 b43_phy_set(dev, 0x042B, 0x2000);
1599
1600                 b43_phy_write(dev, 0x001C, 0x186A);
1601
1602                 b43_phy_write(dev, 0x0013,
1603                               (b43_phy_read(dev, 0x0013) & 0x00FF) | 0x1900);
1604                 b43_phy_write(dev, 0x0035,
1605                               (b43_phy_read(dev, 0x0035) & 0xFFC0) | 0x0064);
1606                 b43_phy_write(dev, 0x005D,
1607                               (b43_phy_read(dev, 0x005D) & 0xFF80) | 0x000A);
1608         }
1609
1610         if (dev->bad_frames_preempt) {
1611                 b43_phy_set(dev, B43_PHY_RADIO_BITFIELD, (1 << 11));
1612         }
1613
1614         if (phy->analog == 1) {
1615                 b43_phy_write(dev, 0x0026, 0xCE00);
1616                 b43_phy_write(dev, 0x0021, 0x3763);
1617                 b43_phy_write(dev, 0x0022, 0x1BC3);
1618                 b43_phy_write(dev, 0x0023, 0x06F9);
1619                 b43_phy_write(dev, 0x0024, 0x037E);
1620         } else
1621                 b43_phy_write(dev, 0x0026, 0xCC00);
1622         b43_phy_write(dev, 0x0030, 0x00C6);
1623         b43_write16(dev, 0x03EC, 0x3F22);
1624
1625         if (phy->analog == 1)
1626                 b43_phy_write(dev, 0x0020, 0x3E1C);
1627         else
1628                 b43_phy_write(dev, 0x0020, 0x301C);
1629
1630         if (phy->analog == 0)
1631                 b43_write16(dev, 0x03E4, 0x3000);
1632
1633         old_channel = phy->channel;
1634         /* Force to channel 7, even if not supported. */
1635         b43_gphy_channel_switch(dev, 7, 0);
1636
1637         if (phy->radio_ver != 0x2050) {
1638                 b43_radio_write16(dev, 0x0075, 0x0080);
1639                 b43_radio_write16(dev, 0x0079, 0x0081);
1640         }
1641
1642         b43_radio_write16(dev, 0x0050, 0x0020);
1643         b43_radio_write16(dev, 0x0050, 0x0023);
1644
1645         if (phy->radio_ver == 0x2050) {
1646                 b43_radio_write16(dev, 0x0050, 0x0020);
1647                 b43_radio_write16(dev, 0x005A, 0x0070);
1648         }
1649
1650         b43_radio_write16(dev, 0x005B, 0x007B);
1651         b43_radio_write16(dev, 0x005C, 0x00B0);
1652
1653         b43_radio_write16(dev, 0x007A, b43_radio_read16(dev, 0x007A) | 0x0007);
1654
1655         b43_gphy_channel_switch(dev, old_channel, 0);
1656
1657         b43_phy_write(dev, 0x0014, 0x0080);
1658         b43_phy_write(dev, 0x0032, 0x00CA);
1659         b43_phy_write(dev, 0x002A, 0x88A3);
1660
1661         b43_set_txpower_g(dev, &gphy->bbatt, &gphy->rfatt, gphy->tx_control);
1662
1663         if (phy->radio_ver == 0x2050)
1664                 b43_radio_write16(dev, 0x005D, 0x000D);
1665
1666         b43_write16(dev, 0x03E4, (b43_read16(dev, 0x03E4) & 0xFFC0) | 0x0004);
1667 }
1668
1669 static void b43_phy_initb6(struct b43_wldev *dev)
1670 {
1671         struct b43_phy *phy = &dev->phy;
1672         struct b43_phy_g *gphy = phy->g;
1673         u16 offset, val;
1674         u8 old_channel;
1675
1676         b43_phy_write(dev, 0x003E, 0x817A);
1677         b43_radio_write16(dev, 0x007A,
1678                           (b43_radio_read16(dev, 0x007A) | 0x0058));
1679         if (phy->radio_rev == 4 || phy->radio_rev == 5) {
1680                 b43_radio_write16(dev, 0x51, 0x37);
1681                 b43_radio_write16(dev, 0x52, 0x70);
1682                 b43_radio_write16(dev, 0x53, 0xB3);
1683                 b43_radio_write16(dev, 0x54, 0x9B);
1684                 b43_radio_write16(dev, 0x5A, 0x88);
1685                 b43_radio_write16(dev, 0x5B, 0x88);
1686                 b43_radio_write16(dev, 0x5D, 0x88);
1687                 b43_radio_write16(dev, 0x5E, 0x88);
1688                 b43_radio_write16(dev, 0x7D, 0x88);
1689                 b43_hf_write(dev, b43_hf_read(dev)
1690                              | B43_HF_TSSIRPSMW);
1691         }
1692         B43_WARN_ON(phy->radio_rev == 6 || phy->radio_rev == 7);        /* We had code for these revs here... */
1693         if (phy->radio_rev == 8) {
1694                 b43_radio_write16(dev, 0x51, 0);
1695                 b43_radio_write16(dev, 0x52, 0x40);
1696                 b43_radio_write16(dev, 0x53, 0xB7);
1697                 b43_radio_write16(dev, 0x54, 0x98);
1698                 b43_radio_write16(dev, 0x5A, 0x88);
1699                 b43_radio_write16(dev, 0x5B, 0x6B);
1700                 b43_radio_write16(dev, 0x5C, 0x0F);
1701                 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_ALTIQ) {
1702                         b43_radio_write16(dev, 0x5D, 0xFA);
1703                         b43_radio_write16(dev, 0x5E, 0xD8);
1704                 } else {
1705                         b43_radio_write16(dev, 0x5D, 0xF5);
1706                         b43_radio_write16(dev, 0x5E, 0xB8);
1707                 }
1708                 b43_radio_write16(dev, 0x0073, 0x0003);
1709                 b43_radio_write16(dev, 0x007D, 0x00A8);
1710                 b43_radio_write16(dev, 0x007C, 0x0001);
1711                 b43_radio_write16(dev, 0x007E, 0x0008);
1712         }
1713         val = 0x1E1F;
1714         for (offset = 0x0088; offset < 0x0098; offset++) {
1715                 b43_phy_write(dev, offset, val);
1716                 val -= 0x0202;
1717         }
1718         val = 0x3E3F;
1719         for (offset = 0x0098; offset < 0x00A8; offset++) {
1720                 b43_phy_write(dev, offset, val);
1721                 val -= 0x0202;
1722         }
1723         val = 0x2120;
1724         for (offset = 0x00A8; offset < 0x00C8; offset++) {
1725                 b43_phy_write(dev, offset, (val & 0x3F3F));
1726                 val += 0x0202;
1727         }
1728         if (phy->type == B43_PHYTYPE_G) {
1729                 b43_radio_write16(dev, 0x007A,
1730                                   b43_radio_read16(dev, 0x007A) | 0x0020);
1731                 b43_radio_write16(dev, 0x0051,
1732                                   b43_radio_read16(dev, 0x0051) | 0x0004);
1733                 b43_phy_set(dev, 0x0802, 0x0100);
1734                 b43_phy_set(dev, 0x042B, 0x2000);
1735                 b43_phy_write(dev, 0x5B, 0);
1736                 b43_phy_write(dev, 0x5C, 0);
1737         }
1738
1739         old_channel = phy->channel;
1740         if (old_channel >= 8)
1741                 b43_gphy_channel_switch(dev, 1, 0);
1742         else
1743                 b43_gphy_channel_switch(dev, 13, 0);
1744
1745         b43_radio_write16(dev, 0x0050, 0x0020);
1746         b43_radio_write16(dev, 0x0050, 0x0023);
1747         udelay(40);
1748         if (phy->radio_rev < 6 || phy->radio_rev == 8) {
1749                 b43_radio_write16(dev, 0x7C, (b43_radio_read16(dev, 0x7C)
1750                                               | 0x0002));
1751                 b43_radio_write16(dev, 0x50, 0x20);
1752         }
1753         if (phy->radio_rev <= 2) {
1754                 b43_radio_write16(dev, 0x7C, 0x20);
1755                 b43_radio_write16(dev, 0x5A, 0x70);
1756                 b43_radio_write16(dev, 0x5B, 0x7B);
1757                 b43_radio_write16(dev, 0x5C, 0xB0);
1758         }
1759         b43_radio_write16(dev, 0x007A,
1760                           (b43_radio_read16(dev, 0x007A) & 0x00F8) | 0x0007);
1761
1762         b43_gphy_channel_switch(dev, old_channel, 0);
1763
1764         b43_phy_write(dev, 0x0014, 0x0200);
1765         if (phy->radio_rev >= 6)
1766                 b43_phy_write(dev, 0x2A, 0x88C2);
1767         else
1768                 b43_phy_write(dev, 0x2A, 0x8AC0);
1769         b43_phy_write(dev, 0x0038, 0x0668);
1770         b43_set_txpower_g(dev, &gphy->bbatt, &gphy->rfatt, gphy->tx_control);
1771         if (phy->radio_rev <= 5) {
1772                 b43_phy_write(dev, 0x5D, (b43_phy_read(dev, 0x5D)
1773                                           & 0xFF80) | 0x0003);
1774         }
1775         if (phy->radio_rev <= 2)
1776                 b43_radio_write16(dev, 0x005D, 0x000D);
1777
1778         if (phy->analog == 4) {
1779                 b43_write16(dev, 0x3E4, 9);
1780                 b43_phy_mask(dev, 0x61, 0x0FFF);
1781         } else {
1782                 b43_phy_write(dev, 0x0002, (b43_phy_read(dev, 0x0002) & 0xFFC0)
1783                               | 0x0004);
1784         }
1785         if (phy->type == B43_PHYTYPE_B)
1786                 B43_WARN_ON(1);
1787         else if (phy->type == B43_PHYTYPE_G)
1788                 b43_write16(dev, 0x03E6, 0x0);
1789 }
1790
1791 static void b43_calc_loopback_gain(struct b43_wldev *dev)
1792 {
1793         struct b43_phy *phy = &dev->phy;
1794         struct b43_phy_g *gphy = phy->g;
1795         u16 backup_phy[16] = { 0 };
1796         u16 backup_radio[3];
1797         u16 backup_bband;
1798         u16 i, j, loop_i_max;
1799         u16 trsw_rx;
1800         u16 loop1_outer_done, loop1_inner_done;
1801
1802         backup_phy[0] = b43_phy_read(dev, B43_PHY_CRS0);
1803         backup_phy[1] = b43_phy_read(dev, B43_PHY_CCKBBANDCFG);
1804         backup_phy[2] = b43_phy_read(dev, B43_PHY_RFOVER);
1805         backup_phy[3] = b43_phy_read(dev, B43_PHY_RFOVERVAL);
1806         if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
1807                 backup_phy[4] = b43_phy_read(dev, B43_PHY_ANALOGOVER);
1808                 backup_phy[5] = b43_phy_read(dev, B43_PHY_ANALOGOVERVAL);
1809         }
1810         backup_phy[6] = b43_phy_read(dev, B43_PHY_CCK(0x5A));
1811         backup_phy[7] = b43_phy_read(dev, B43_PHY_CCK(0x59));
1812         backup_phy[8] = b43_phy_read(dev, B43_PHY_CCK(0x58));
1813         backup_phy[9] = b43_phy_read(dev, B43_PHY_CCK(0x0A));
1814         backup_phy[10] = b43_phy_read(dev, B43_PHY_CCK(0x03));
1815         backup_phy[11] = b43_phy_read(dev, B43_PHY_LO_MASK);
1816         backup_phy[12] = b43_phy_read(dev, B43_PHY_LO_CTL);
1817         backup_phy[13] = b43_phy_read(dev, B43_PHY_CCK(0x2B));
1818         backup_phy[14] = b43_phy_read(dev, B43_PHY_PGACTL);
1819         backup_phy[15] = b43_phy_read(dev, B43_PHY_LO_LEAKAGE);
1820         backup_bband = gphy->bbatt.att;
1821         backup_radio[0] = b43_radio_read16(dev, 0x52);
1822         backup_radio[1] = b43_radio_read16(dev, 0x43);
1823         backup_radio[2] = b43_radio_read16(dev, 0x7A);
1824
1825         b43_phy_mask(dev, B43_PHY_CRS0, 0x3FFF);
1826         b43_phy_set(dev, B43_PHY_CCKBBANDCFG, 0x8000);
1827         b43_phy_set(dev, B43_PHY_RFOVER, 0x0002);
1828         b43_phy_mask(dev, B43_PHY_RFOVERVAL, 0xFFFD);
1829         b43_phy_set(dev, B43_PHY_RFOVER, 0x0001);
1830         b43_phy_mask(dev, B43_PHY_RFOVERVAL, 0xFFFE);
1831         if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
1832                 b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0001);
1833                 b43_phy_mask(dev, B43_PHY_ANALOGOVERVAL, 0xFFFE);
1834                 b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0002);
1835                 b43_phy_mask(dev, B43_PHY_ANALOGOVERVAL, 0xFFFD);
1836         }
1837         b43_phy_set(dev, B43_PHY_RFOVER, 0x000C);
1838         b43_phy_set(dev, B43_PHY_RFOVERVAL, 0x000C);
1839         b43_phy_set(dev, B43_PHY_RFOVER, 0x0030);
1840         b43_phy_write(dev, B43_PHY_RFOVERVAL,
1841                       (b43_phy_read(dev, B43_PHY_RFOVERVAL)
1842                        & 0xFFCF) | 0x10);
1843
1844         b43_phy_write(dev, B43_PHY_CCK(0x5A), 0x0780);
1845         b43_phy_write(dev, B43_PHY_CCK(0x59), 0xC810);
1846         b43_phy_write(dev, B43_PHY_CCK(0x58), 0x000D);
1847
1848         b43_phy_set(dev, B43_PHY_CCK(0x0A), 0x2000);
1849         if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
1850                 b43_phy_set(dev, B43_PHY_ANALOGOVER, 0x0004);
1851                 b43_phy_mask(dev, B43_PHY_ANALOGOVERVAL, 0xFFFB);
1852         }
1853         b43_phy_write(dev, B43_PHY_CCK(0x03),
1854                       (b43_phy_read(dev, B43_PHY_CCK(0x03))
1855                        & 0xFF9F) | 0x40);
1856
1857         if (phy->radio_rev == 8) {
1858                 b43_radio_write16(dev, 0x43, 0x000F);
1859         } else {
1860                 b43_radio_write16(dev, 0x52, 0);
1861                 b43_radio_write16(dev, 0x43, (b43_radio_read16(dev, 0x43)
1862                                               & 0xFFF0) | 0x9);
1863         }
1864         b43_gphy_set_baseband_attenuation(dev, 11);
1865
1866         if (phy->rev >= 3)
1867                 b43_phy_write(dev, B43_PHY_LO_MASK, 0xC020);
1868         else
1869                 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8020);
1870         b43_phy_write(dev, B43_PHY_LO_CTL, 0);
1871
1872         b43_phy_write(dev, B43_PHY_CCK(0x2B),
1873                       (b43_phy_read(dev, B43_PHY_CCK(0x2B))
1874                        & 0xFFC0) | 0x01);
1875         b43_phy_write(dev, B43_PHY_CCK(0x2B),
1876                       (b43_phy_read(dev, B43_PHY_CCK(0x2B))
1877                        & 0xC0FF) | 0x800);
1878
1879         b43_phy_set(dev, B43_PHY_RFOVER, 0x0100);
1880         b43_phy_mask(dev, B43_PHY_RFOVERVAL, 0xCFFF);
1881
1882         if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_EXTLNA) {
1883                 if (phy->rev >= 7) {
1884                         b43_phy_set(dev, B43_PHY_RFOVER, 0x0800);
1885                         b43_phy_set(dev, B43_PHY_RFOVERVAL, 0x8000);
1886                 }
1887         }
1888         b43_radio_write16(dev, 0x7A, b43_radio_read16(dev, 0x7A)
1889                           & 0x00F7);
1890
1891         j = 0;
1892         loop_i_max = (phy->radio_rev == 8) ? 15 : 9;
1893         for (i = 0; i < loop_i_max; i++) {
1894                 for (j = 0; j < 16; j++) {
1895                         b43_radio_write16(dev, 0x43, i);
1896                         b43_phy_write(dev, B43_PHY_RFOVERVAL,
1897                                       (b43_phy_read(dev, B43_PHY_RFOVERVAL)
1898                                        & 0xF0FF) | (j << 8));
1899                         b43_phy_write(dev, B43_PHY_PGACTL,
1900                                       (b43_phy_read(dev, B43_PHY_PGACTL)
1901                                        & 0x0FFF) | 0xA000);
1902                         b43_phy_set(dev, B43_PHY_PGACTL, 0xF000);
1903                         udelay(20);
1904                         if (b43_phy_read(dev, B43_PHY_LO_LEAKAGE) >= 0xDFC)
1905                                 goto exit_loop1;
1906                 }
1907         }
1908       exit_loop1:
1909         loop1_outer_done = i;
1910         loop1_inner_done = j;
1911         if (j >= 8) {
1912                 b43_phy_set(dev, B43_PHY_RFOVERVAL, 0x30);
1913                 trsw_rx = 0x1B;
1914                 for (j = j - 8; j < 16; j++) {
1915                         b43_phy_write(dev, B43_PHY_RFOVERVAL,
1916                                       (b43_phy_read(dev, B43_PHY_RFOVERVAL)
1917                                        & 0xF0FF) | (j << 8));
1918                         b43_phy_write(dev, B43_PHY_PGACTL,
1919                                       (b43_phy_read(dev, B43_PHY_PGACTL)
1920                                        & 0x0FFF) | 0xA000);
1921                         b43_phy_set(dev, B43_PHY_PGACTL, 0xF000);
1922                         udelay(20);
1923                         trsw_rx -= 3;
1924                         if (b43_phy_read(dev, B43_PHY_LO_LEAKAGE) >= 0xDFC)
1925                                 goto exit_loop2;
1926                 }
1927         } else
1928                 trsw_rx = 0x18;
1929       exit_loop2:
1930
1931         if (phy->rev != 1) {    /* Not in specs, but needed to prevent PPC machine check */
1932                 b43_phy_write(dev, B43_PHY_ANALOGOVER, backup_phy[4]);
1933                 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, backup_phy[5]);
1934         }
1935         b43_phy_write(dev, B43_PHY_CCK(0x5A), backup_phy[6]);
1936         b43_phy_write(dev, B43_PHY_CCK(0x59), backup_phy[7]);
1937         b43_phy_write(dev, B43_PHY_CCK(0x58), backup_phy[8]);
1938         b43_phy_write(dev, B43_PHY_CCK(0x0A), backup_phy[9]);
1939         b43_phy_write(dev, B43_PHY_CCK(0x03), backup_phy[10]);
1940         b43_phy_write(dev, B43_PHY_LO_MASK, backup_phy[11]);
1941         b43_phy_write(dev, B43_PHY_LO_CTL, backup_phy[12]);
1942         b43_phy_write(dev, B43_PHY_CCK(0x2B), backup_phy[13]);
1943         b43_phy_write(dev, B43_PHY_PGACTL, backup_phy[14]);
1944
1945         b43_gphy_set_baseband_attenuation(dev, backup_bband);
1946
1947         b43_radio_write16(dev, 0x52, backup_radio[0]);
1948         b43_radio_write16(dev, 0x43, backup_radio[1]);
1949         b43_radio_write16(dev, 0x7A, backup_radio[2]);
1950
1951         b43_phy_write(dev, B43_PHY_RFOVER, backup_phy[2] | 0x0003);
1952         udelay(10);
1953         b43_phy_write(dev, B43_PHY_RFOVER, backup_phy[2]);
1954         b43_phy_write(dev, B43_PHY_RFOVERVAL, backup_phy[3]);
1955         b43_phy_write(dev, B43_PHY_CRS0, backup_phy[0]);
1956         b43_phy_write(dev, B43_PHY_CCKBBANDCFG, backup_phy[1]);
1957
1958         gphy->max_lb_gain =
1959             ((loop1_inner_done * 6) - (loop1_outer_done * 4)) - 11;
1960         gphy->trsw_rx_gain = trsw_rx * 2;
1961 }
1962
1963 static void b43_hardware_pctl_early_init(struct b43_wldev *dev)
1964 {
1965         struct b43_phy *phy = &dev->phy;
1966
1967         if (!b43_has_hardware_pctl(dev)) {
1968                 b43_phy_write(dev, 0x047A, 0xC111);
1969                 return;
1970         }
1971
1972         b43_phy_mask(dev, 0x0036, 0xFEFF);
1973         b43_phy_write(dev, 0x002F, 0x0202);
1974         b43_phy_set(dev, 0x047C, 0x0002);
1975         b43_phy_set(dev, 0x047A, 0xF000);
1976         if (phy->radio_ver == 0x2050 && phy->radio_rev == 8) {
1977                 b43_phy_write(dev, 0x047A, (b43_phy_read(dev, 0x047A)
1978                                             & 0xFF0F) | 0x0010);
1979                 b43_phy_set(dev, 0x005D, 0x8000);
1980                 b43_phy_write(dev, 0x004E, (b43_phy_read(dev, 0x004E)
1981                                             & 0xFFC0) | 0x0010);
1982                 b43_phy_write(dev, 0x002E, 0xC07F);
1983                 b43_phy_set(dev, 0x0036, 0x0400);
1984         } else {
1985                 b43_phy_set(dev, 0x0036, 0x0200);
1986                 b43_phy_set(dev, 0x0036, 0x0400);
1987                 b43_phy_mask(dev, 0x005D, 0x7FFF);
1988                 b43_phy_mask(dev, 0x004F, 0xFFFE);
1989                 b43_phy_write(dev, 0x004E, (b43_phy_read(dev, 0x004E)
1990                                             & 0xFFC0) | 0x0010);
1991                 b43_phy_write(dev, 0x002E, 0xC07F);
1992                 b43_phy_write(dev, 0x047A, (b43_phy_read(dev, 0x047A)
1993                                             & 0xFF0F) | 0x0010);
1994         }
1995 }
1996
1997 /* Hardware power control for G-PHY */
1998 static void b43_hardware_pctl_init_gphy(struct b43_wldev *dev)
1999 {
2000         struct b43_phy *phy = &dev->phy;
2001         struct b43_phy_g *gphy = phy->g;
2002
2003         if (!b43_has_hardware_pctl(dev)) {
2004                 /* No hardware power control */
2005                 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_HWPCTL);
2006                 return;
2007         }
2008
2009         b43_phy_write(dev, 0x0036, (b43_phy_read(dev, 0x0036) & 0xFFC0)
2010                       | (gphy->tgt_idle_tssi - gphy->cur_idle_tssi));
2011         b43_phy_write(dev, 0x0478, (b43_phy_read(dev, 0x0478) & 0xFF00)
2012                       | (gphy->tgt_idle_tssi - gphy->cur_idle_tssi));
2013         b43_gphy_tssi_power_lt_init(dev);
2014         b43_gphy_gain_lt_init(dev);
2015         b43_phy_mask(dev, 0x0060, 0xFFBF);
2016         b43_phy_write(dev, 0x0014, 0x0000);
2017
2018         B43_WARN_ON(phy->rev < 6);
2019         b43_phy_set(dev, 0x0478, 0x0800);
2020         b43_phy_mask(dev, 0x0478, 0xFEFF);
2021         b43_phy_mask(dev, 0x0801, 0xFFBF);
2022
2023         b43_gphy_dc_lt_init(dev, 1);
2024
2025         /* Enable hardware pctl in firmware. */
2026         b43_hf_write(dev, b43_hf_read(dev) | B43_HF_HWPCTL);
2027 }
2028
2029 /* Intialize B/G PHY power control */
2030 static void b43_phy_init_pctl(struct b43_wldev *dev)
2031 {
2032         struct ssb_bus *bus = dev->dev->bus;
2033         struct b43_phy *phy = &dev->phy;
2034         struct b43_phy_g *gphy = phy->g;
2035         struct b43_rfatt old_rfatt;
2036         struct b43_bbatt old_bbatt;
2037         u8 old_tx_control = 0;
2038
2039         B43_WARN_ON(phy->type != B43_PHYTYPE_G);
2040
2041         if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
2042             (bus->boardinfo.type == SSB_BOARD_BU4306))
2043                 return;
2044
2045         b43_phy_write(dev, 0x0028, 0x8018);
2046
2047         /* This does something with the Analog... */
2048         b43_write16(dev, B43_MMIO_PHY0, b43_read16(dev, B43_MMIO_PHY0)
2049                     & 0xFFDF);
2050
2051         if (!phy->gmode)
2052                 return;
2053         b43_hardware_pctl_early_init(dev);
2054         if (gphy->cur_idle_tssi == 0) {
2055                 if (phy->radio_ver == 0x2050 && phy->analog == 0) {
2056                         b43_radio_write16(dev, 0x0076,
2057                                           (b43_radio_read16(dev, 0x0076)
2058                                            & 0x00F7) | 0x0084);
2059                 } else {
2060                         struct b43_rfatt rfatt;
2061                         struct b43_bbatt bbatt;
2062
2063                         memcpy(&old_rfatt, &gphy->rfatt, sizeof(old_rfatt));
2064                         memcpy(&old_bbatt, &gphy->bbatt, sizeof(old_bbatt));
2065                         old_tx_control = gphy->tx_control;
2066
2067                         bbatt.att = 11;
2068                         if (phy->radio_rev == 8) {
2069                                 rfatt.att = 15;
2070                                 rfatt.with_padmix = 1;
2071                         } else {
2072                                 rfatt.att = 9;
2073                                 rfatt.with_padmix = 0;
2074                         }
2075                         b43_set_txpower_g(dev, &bbatt, &rfatt, 0);
2076                 }
2077                 b43_dummy_transmission(dev);
2078                 gphy->cur_idle_tssi = b43_phy_read(dev, B43_PHY_ITSSI);
2079                 if (B43_DEBUG) {
2080                         /* Current-Idle-TSSI sanity check. */
2081                         if (abs(gphy->cur_idle_tssi - gphy->tgt_idle_tssi) >= 20) {
2082                                 b43dbg(dev->wl,
2083                                        "!WARNING! Idle-TSSI phy->cur_idle_tssi "
2084                                        "measuring failed. (cur=%d, tgt=%d). Disabling TX power "
2085                                        "adjustment.\n", gphy->cur_idle_tssi,
2086                                        gphy->tgt_idle_tssi);
2087                                 gphy->cur_idle_tssi = 0;
2088                         }
2089                 }
2090                 if (phy->radio_ver == 0x2050 && phy->analog == 0) {
2091                         b43_radio_write16(dev, 0x0076,
2092                                           b43_radio_read16(dev, 0x0076)
2093                                           & 0xFF7B);
2094                 } else {
2095                         b43_set_txpower_g(dev, &old_bbatt,
2096                                           &old_rfatt, old_tx_control);
2097                 }
2098         }
2099         b43_hardware_pctl_init_gphy(dev);
2100         b43_shm_clear_tssi(dev);
2101 }
2102
2103 static void b43_phy_initg(struct b43_wldev *dev)
2104 {
2105         struct b43_phy *phy = &dev->phy;
2106         struct b43_phy_g *gphy = phy->g;
2107         u16 tmp;
2108
2109         if (phy->rev == 1)
2110                 b43_phy_initb5(dev);
2111         else
2112                 b43_phy_initb6(dev);
2113
2114         if (phy->rev >= 2 || phy->gmode)
2115                 b43_phy_inita(dev);
2116
2117         if (phy->rev >= 2) {
2118                 b43_phy_write(dev, B43_PHY_ANALOGOVER, 0);
2119                 b43_phy_write(dev, B43_PHY_ANALOGOVERVAL, 0);
2120         }
2121         if (phy->rev == 2) {
2122                 b43_phy_write(dev, B43_PHY_RFOVER, 0);
2123                 b43_phy_write(dev, B43_PHY_PGACTL, 0xC0);
2124         }
2125         if (phy->rev > 5) {
2126                 b43_phy_write(dev, B43_PHY_RFOVER, 0x400);
2127                 b43_phy_write(dev, B43_PHY_PGACTL, 0xC0);
2128         }
2129         if (phy->gmode || phy->rev >= 2) {
2130                 tmp = b43_phy_read(dev, B43_PHY_VERSION_OFDM);
2131                 tmp &= B43_PHYVER_VERSION;
2132                 if (tmp == 3 || tmp == 5) {
2133                         b43_phy_write(dev, B43_PHY_OFDM(0xC2), 0x1816);
2134                         b43_phy_write(dev, B43_PHY_OFDM(0xC3), 0x8006);
2135                 }
2136                 if (tmp == 5) {
2137                         b43_phy_write(dev, B43_PHY_OFDM(0xCC),
2138                                       (b43_phy_read(dev, B43_PHY_OFDM(0xCC))
2139                                        & 0x00FF) | 0x1F00);
2140                 }
2141         }
2142         if ((phy->rev <= 2 && phy->gmode) || phy->rev >= 2)
2143                 b43_phy_write(dev, B43_PHY_OFDM(0x7E), 0x78);
2144         if (phy->radio_rev == 8) {
2145                 b43_phy_set(dev, B43_PHY_EXTG(0x01), 0x80);
2146                 b43_phy_set(dev, B43_PHY_OFDM(0x3E), 0x4);
2147         }
2148         if (has_loopback_gain(phy))
2149                 b43_calc_loopback_gain(dev);
2150
2151         if (phy->radio_rev != 8) {
2152                 if (gphy->initval == 0xFFFF)
2153                         gphy->initval = b43_radio_init2050(dev);
2154                 else
2155                         b43_radio_write16(dev, 0x0078, gphy->initval);
2156         }
2157         b43_lo_g_init(dev);
2158         if (has_tx_magnification(phy)) {
2159                 b43_radio_write16(dev, 0x52,
2160                                   (b43_radio_read16(dev, 0x52) & 0xFF00)
2161                                   | gphy->lo_control->tx_bias | gphy->
2162                                   lo_control->tx_magn);
2163         } else {
2164                 b43_radio_write16(dev, 0x52,
2165                                   (b43_radio_read16(dev, 0x52) & 0xFFF0)
2166                                   | gphy->lo_control->tx_bias);
2167         }
2168         if (phy->rev >= 6) {
2169                 b43_phy_write(dev, B43_PHY_CCK(0x36),
2170                               (b43_phy_read(dev, B43_PHY_CCK(0x36))
2171                                & 0x0FFF) | (gphy->lo_control->
2172                                             tx_bias << 12));
2173         }
2174         if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL)
2175                 b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x8075);
2176         else
2177                 b43_phy_write(dev, B43_PHY_CCK(0x2E), 0x807F);
2178         if (phy->rev < 2)
2179                 b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x101);
2180         else
2181                 b43_phy_write(dev, B43_PHY_CCK(0x2F), 0x202);
2182         if (phy->gmode || phy->rev >= 2) {
2183                 b43_lo_g_adjust(dev);
2184                 b43_phy_write(dev, B43_PHY_LO_MASK, 0x8078);
2185         }
2186
2187         if (!(dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI)) {
2188                 /* The specs state to update the NRSSI LT with
2189                  * the value 0x7FFFFFFF here. I think that is some weird
2190                  * compiler optimization in the original driver.
2191                  * Essentially, what we do here is resetting all NRSSI LT
2192                  * entries to -32 (see the clamp_val() in nrssi_hw_update())
2193                  */
2194                 b43_nrssi_hw_update(dev, 0xFFFF);       //FIXME?
2195                 b43_calc_nrssi_threshold(dev);
2196         } else if (phy->gmode || phy->rev >= 2) {
2197                 if (gphy->nrssi[0] == -1000) {
2198                         B43_WARN_ON(gphy->nrssi[1] != -1000);
2199                         b43_calc_nrssi_slope(dev);
2200                 } else
2201                         b43_calc_nrssi_threshold(dev);
2202         }
2203         if (phy->radio_rev == 8)
2204                 b43_phy_write(dev, B43_PHY_EXTG(0x05), 0x3230);
2205         b43_phy_init_pctl(dev);
2206         /* FIXME: The spec says in the following if, the 0 should be replaced
2207            'if OFDM may not be used in the current locale'
2208            but OFDM is legal everywhere */
2209         if ((dev->dev->bus->chip_id == 0x4306
2210              && dev->dev->bus->chip_package == 2) || 0) {
2211                 b43_phy_mask(dev, B43_PHY_CRS0, 0xBFFF);
2212                 b43_phy_mask(dev, B43_PHY_OFDM(0xC3), 0x7FFF);
2213         }
2214 }
2215
2216 void b43_gphy_channel_switch(struct b43_wldev *dev,
2217                              unsigned int channel,
2218                              bool synthetic_pu_workaround)
2219 {
2220         if (synthetic_pu_workaround)
2221                 b43_synth_pu_workaround(dev, channel);
2222
2223         b43_write16(dev, B43_MMIO_CHANNEL, channel2freq_bg(channel));
2224
2225         if (channel == 14) {
2226                 if (dev->dev->bus->sprom.country_code ==
2227                     SSB_SPROM1CCODE_JAPAN)
2228                         b43_hf_write(dev,
2229                                      b43_hf_read(dev) & ~B43_HF_ACPR);
2230                 else
2231                         b43_hf_write(dev,
2232                                      b43_hf_read(dev) | B43_HF_ACPR);
2233                 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
2234                             b43_read16(dev, B43_MMIO_CHANNEL_EXT)
2235                             | (1 << 11));
2236         } else {
2237                 b43_write16(dev, B43_MMIO_CHANNEL_EXT,
2238                             b43_read16(dev, B43_MMIO_CHANNEL_EXT)
2239                             & 0xF7BF);
2240         }
2241 }
2242
2243 static void default_baseband_attenuation(struct b43_wldev *dev,
2244                                          struct b43_bbatt *bb)
2245 {
2246         struct b43_phy *phy = &dev->phy;
2247
2248         if (phy->radio_ver == 0x2050 && phy->radio_rev < 6)
2249                 bb->att = 0;
2250         else
2251                 bb->att = 2;
2252 }
2253
2254 static void default_radio_attenuation(struct b43_wldev *dev,
2255                                       struct b43_rfatt *rf)
2256 {
2257         struct ssb_bus *bus = dev->dev->bus;
2258         struct b43_phy *phy = &dev->phy;
2259
2260         rf->with_padmix = 0;
2261
2262         if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM &&
2263             bus->boardinfo.type == SSB_BOARD_BCM4309G) {
2264                 if (bus->boardinfo.rev < 0x43) {
2265                         rf->att = 2;
2266                         return;
2267                 } else if (bus->boardinfo.rev < 0x51) {
2268                         rf->att = 3;
2269                         return;
2270                 }
2271         }
2272
2273         if (phy->type == B43_PHYTYPE_A) {
2274                 rf->att = 0x60;
2275                 return;
2276         }
2277
2278         switch (phy->radio_ver) {
2279         case 0x2053:
2280                 switch (phy->radio_rev) {
2281                 case 1:
2282                         rf->att = 6;
2283                         return;
2284                 }
2285                 break;
2286         case 0x2050:
2287                 switch (phy->radio_rev) {
2288                 case 0:
2289                         rf->att = 5;
2290                         return;
2291                 case 1:
2292                         if (phy->type == B43_PHYTYPE_G) {
2293                                 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM
2294                                     && bus->boardinfo.type == SSB_BOARD_BCM4309G
2295                                     && bus->boardinfo.rev >= 30)
2296                                         rf->att = 3;
2297                                 else if (bus->boardinfo.vendor ==
2298                                          SSB_BOARDVENDOR_BCM
2299                                          && bus->boardinfo.type ==
2300                                          SSB_BOARD_BU4306)
2301                                         rf->att = 3;
2302                                 else
2303                                         rf->att = 1;
2304                         } else {
2305                                 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM
2306                                     && bus->boardinfo.type == SSB_BOARD_BCM4309G
2307                                     && bus->boardinfo.rev >= 30)
2308                                         rf->att = 7;
2309                                 else
2310                                         rf->att = 6;
2311                         }
2312                         return;
2313                 case 2:
2314                         if (phy->type == B43_PHYTYPE_G) {
2315                                 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM
2316                                     && bus->boardinfo.type == SSB_BOARD_BCM4309G
2317                                     && bus->boardinfo.rev >= 30)
2318                                         rf->att = 3;
2319                                 else if (bus->boardinfo.vendor ==
2320                                          SSB_BOARDVENDOR_BCM
2321                                          && bus->boardinfo.type ==
2322                                          SSB_BOARD_BU4306)
2323                                         rf->att = 5;
2324                                 else if (bus->chip_id == 0x4320)
2325                                         rf->att = 4;
2326                                 else
2327                                         rf->att = 3;
2328                         } else
2329                                 rf->att = 6;
2330                         return;
2331                 case 3:
2332                         rf->att = 5;
2333                         return;
2334                 case 4:
2335                 case 5:
2336                         rf->att = 1;
2337                         return;
2338                 case 6:
2339                 case 7:
2340                         rf->att = 5;
2341                         return;
2342                 case 8:
2343                         rf->att = 0xA;
2344                         rf->with_padmix = 1;
2345                         return;
2346                 case 9:
2347                 default:
2348                         rf->att = 5;
2349                         return;
2350                 }
2351         }
2352         rf->att = 5;
2353 }
2354
2355 static u16 default_tx_control(struct b43_wldev *dev)
2356 {
2357         struct b43_phy *phy = &dev->phy;
2358
2359         if (phy->radio_ver != 0x2050)
2360                 return 0;
2361         if (phy->radio_rev == 1)
2362                 return B43_TXCTL_PA2DB | B43_TXCTL_TXMIX;
2363         if (phy->radio_rev < 6)
2364                 return B43_TXCTL_PA2DB;
2365         if (phy->radio_rev == 8)
2366                 return B43_TXCTL_TXMIX;
2367         return 0;
2368 }
2369
2370 static u8 b43_gphy_aci_detect(struct b43_wldev *dev, u8 channel)
2371 {
2372         struct b43_phy *phy = &dev->phy;
2373         struct b43_phy_g *gphy = phy->g;
2374         u8 ret = 0;
2375         u16 saved, rssi, temp;
2376         int i, j = 0;
2377
2378         saved = b43_phy_read(dev, 0x0403);
2379         b43_switch_channel(dev, channel);
2380         b43_phy_write(dev, 0x0403, (saved & 0xFFF8) | 5);
2381         if (gphy->aci_hw_rssi)
2382                 rssi = b43_phy_read(dev, 0x048A) & 0x3F;
2383         else
2384                 rssi = saved & 0x3F;
2385         /* clamp temp to signed 5bit */
2386         if (rssi > 32)
2387                 rssi -= 64;
2388         for (i = 0; i < 100; i++) {
2389                 temp = (b43_phy_read(dev, 0x047F) >> 8) & 0x3F;
2390                 if (temp > 32)
2391                         temp -= 64;
2392                 if (temp < rssi)
2393                         j++;
2394                 if (j >= 20)
2395                         ret = 1;
2396         }
2397         b43_phy_write(dev, 0x0403, saved);
2398
2399         return ret;
2400 }
2401
2402 static u8 b43_gphy_aci_scan(struct b43_wldev *dev)
2403 {
2404         struct b43_phy *phy = &dev->phy;
2405         u8 ret[13];
2406         unsigned int channel = phy->channel;
2407         unsigned int i, j, start, end;
2408
2409         if (!((phy->type == B43_PHYTYPE_G) && (phy->rev > 0)))
2410                 return 0;
2411
2412         b43_phy_lock(dev);
2413         b43_radio_lock(dev);
2414         b43_phy_mask(dev, 0x0802, 0xFFFC);
2415         b43_phy_mask(dev, B43_PHY_G_CRS, 0x7FFF);
2416         b43_set_all_gains(dev, 3, 8, 1);
2417
2418         start = (channel - 5 > 0) ? channel - 5 : 1;
2419         end = (channel + 5 < 14) ? channel + 5 : 13;
2420
2421         for (i = start; i <= end; i++) {
2422                 if (abs(channel - i) > 2)
2423                         ret[i - 1] = b43_gphy_aci_detect(dev, i);
2424         }
2425         b43_switch_channel(dev, channel);
2426         b43_phy_write(dev, 0x0802,
2427                       (b43_phy_read(dev, 0x0802) & 0xFFFC) | 0x0003);
2428         b43_phy_mask(dev, 0x0403, 0xFFF8);
2429         b43_phy_set(dev, B43_PHY_G_CRS, 0x8000);
2430         b43_set_original_gains(dev);
2431         for (i = 0; i < 13; i++) {
2432                 if (!ret[i])
2433                         continue;
2434                 end = (i + 5 < 13) ? i + 5 : 13;
2435                 for (j = i; j < end; j++)
2436                         ret[j] = 1;
2437         }
2438         b43_radio_unlock(dev);
2439         b43_phy_unlock(dev);
2440
2441         return ret[channel - 1];
2442 }
2443
2444 static s32 b43_tssi2dbm_ad(s32 num, s32 den)
2445 {
2446         if (num < 0)
2447                 return num / den;
2448         else
2449                 return (num + den / 2) / den;
2450 }
2451
2452 static s8 b43_tssi2dbm_entry(s8 entry[], u8 index,
2453                              s16 pab0, s16 pab1, s16 pab2)
2454 {
2455         s32 m1, m2, f = 256, q, delta;
2456         s8 i = 0;
2457
2458         m1 = b43_tssi2dbm_ad(16 * pab0 + index * pab1, 32);
2459         m2 = max(b43_tssi2dbm_ad(32768 + index * pab2, 256), 1);
2460         do {
2461                 if (i > 15)
2462                         return -EINVAL;
2463                 q = b43_tssi2dbm_ad(f * 4096 -
2464                                     b43_tssi2dbm_ad(m2 * f, 16) * f, 2048);
2465                 delta = abs(q - f);
2466                 f = q;
2467                 i++;
2468         } while (delta >= 2);
2469         entry[index] = clamp_val(b43_tssi2dbm_ad(m1 * f, 8192), -127, 128);
2470         return 0;
2471 }
2472
2473 u8 * b43_generate_dyn_tssi2dbm_tab(struct b43_wldev *dev,
2474                                    s16 pab0, s16 pab1, s16 pab2)
2475 {
2476         unsigned int i;
2477         u8 *tab;
2478         int err;
2479
2480         tab = kmalloc(64, GFP_KERNEL);
2481         if (!tab) {
2482                 b43err(dev->wl, "Could not allocate memory "
2483                        "for tssi2dbm table\n");
2484                 return NULL;
2485         }
2486         for (i = 0; i < 64; i++) {
2487                 err = b43_tssi2dbm_entry(tab, i, pab0, pab1, pab2);
2488                 if (err) {
2489                         b43err(dev->wl, "Could not generate "
2490                                "tssi2dBm table\n");
2491                         kfree(tab);
2492                         return NULL;
2493                 }
2494         }
2495
2496         return tab;
2497 }
2498
2499 /* Initialise the TSSI->dBm lookup table */
2500 static int b43_gphy_init_tssi2dbm_table(struct b43_wldev *dev)
2501 {
2502         struct b43_phy *phy = &dev->phy;
2503         struct b43_phy_g *gphy = phy->g;
2504         s16 pab0, pab1, pab2;
2505
2506         pab0 = (s16) (dev->dev->bus->sprom.pa0b0);
2507         pab1 = (s16) (dev->dev->bus->sprom.pa0b1);
2508         pab2 = (s16) (dev->dev->bus->sprom.pa0b2);
2509
2510         B43_WARN_ON((dev->dev->bus->chip_id == 0x4301) &&
2511                     (phy->radio_ver != 0x2050)); /* Not supported anymore */
2512
2513         gphy->dyn_tssi_tbl = 0;
2514
2515         if (pab0 != 0 && pab1 != 0 && pab2 != 0 &&
2516             pab0 != -1 && pab1 != -1 && pab2 != -1) {
2517                 /* The pabX values are set in SPROM. Use them. */
2518                 if ((s8) dev->dev->bus->sprom.itssi_bg != 0 &&
2519                     (s8) dev->dev->bus->sprom.itssi_bg != -1) {
2520                         gphy->tgt_idle_tssi =
2521                                 (s8) (dev->dev->bus->sprom.itssi_bg);
2522                 } else
2523                         gphy->tgt_idle_tssi = 62;
2524                 gphy->tssi2dbm = b43_generate_dyn_tssi2dbm_tab(dev, pab0,
2525                                                                pab1, pab2);
2526                 if (!gphy->tssi2dbm)
2527                         return -ENOMEM;
2528                 gphy->dyn_tssi_tbl = 1;
2529         } else {
2530                 /* pabX values not set in SPROM. */
2531                 gphy->tgt_idle_tssi = 52;
2532                 gphy->tssi2dbm = b43_tssi2dbm_g_table;
2533         }
2534
2535         return 0;
2536 }
2537
2538 static int b43_gphy_op_allocate(struct b43_wldev *dev)
2539 {
2540         struct b43_phy_g *gphy;
2541         struct b43_txpower_lo_control *lo;
2542         int err;
2543
2544         gphy = kzalloc(sizeof(*gphy), GFP_KERNEL);
2545         if (!gphy) {
2546                 err = -ENOMEM;
2547                 goto error;
2548         }
2549         dev->phy.g = gphy;
2550
2551         lo = kzalloc(sizeof(*lo), GFP_KERNEL);
2552         if (!lo) {
2553                 err = -ENOMEM;
2554                 goto err_free_gphy;
2555         }
2556         gphy->lo_control = lo;
2557
2558         err = b43_gphy_init_tssi2dbm_table(dev);
2559         if (err)
2560                 goto err_free_lo;
2561
2562         return 0;
2563
2564 err_free_lo:
2565         kfree(lo);
2566 err_free_gphy:
2567         kfree(gphy);
2568 error:
2569         return err;
2570 }
2571
2572 static void b43_gphy_op_prepare_structs(struct b43_wldev *dev)
2573 {
2574         struct b43_phy *phy = &dev->phy;
2575         struct b43_phy_g *gphy = phy->g;
2576         const void *tssi2dbm;
2577         int tgt_idle_tssi;
2578         struct b43_txpower_lo_control *lo;
2579         unsigned int i;
2580
2581         /* tssi2dbm table is constant, so it is initialized at alloc time.
2582          * Save a copy of the pointer. */
2583         tssi2dbm = gphy->tssi2dbm;
2584         tgt_idle_tssi = gphy->tgt_idle_tssi;
2585         /* Save the LO pointer. */
2586         lo = gphy->lo_control;
2587
2588         /* Zero out the whole PHY structure. */
2589         memset(gphy, 0, sizeof(*gphy));
2590
2591         /* Restore pointers. */
2592         gphy->tssi2dbm = tssi2dbm;
2593         gphy->tgt_idle_tssi = tgt_idle_tssi;
2594         gphy->lo_control = lo;
2595
2596         memset(gphy->minlowsig, 0xFF, sizeof(gphy->minlowsig));
2597
2598         /* NRSSI */
2599         for (i = 0; i < ARRAY_SIZE(gphy->nrssi); i++)
2600                 gphy->nrssi[i] = -1000;
2601         for (i = 0; i < ARRAY_SIZE(gphy->nrssi_lt); i++)
2602                 gphy->nrssi_lt[i] = i;
2603
2604         gphy->lofcal = 0xFFFF;
2605         gphy->initval = 0xFFFF;
2606
2607         gphy->interfmode = B43_INTERFMODE_NONE;
2608
2609         /* OFDM-table address caching. */
2610         gphy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_UNKNOWN;
2611
2612         gphy->average_tssi = 0xFF;
2613
2614         /* Local Osciallator structure */
2615         lo->tx_bias = 0xFF;
2616         INIT_LIST_HEAD(&lo->calib_list);
2617 }
2618
2619 static void b43_gphy_op_free(struct b43_wldev *dev)
2620 {
2621         struct b43_phy *phy = &dev->phy;
2622         struct b43_phy_g *gphy = phy->g;
2623
2624         kfree(gphy->lo_control);
2625
2626         if (gphy->dyn_tssi_tbl)
2627                 kfree(gphy->tssi2dbm);
2628         gphy->dyn_tssi_tbl = 0;
2629         gphy->tssi2dbm = NULL;
2630
2631         kfree(gphy);
2632         dev->phy.g = NULL;
2633 }
2634
2635 static int b43_gphy_op_prepare_hardware(struct b43_wldev *dev)
2636 {
2637         struct b43_phy *phy = &dev->phy;
2638         struct b43_phy_g *gphy = phy->g;
2639         struct b43_txpower_lo_control *lo = gphy->lo_control;
2640
2641         B43_WARN_ON(phy->type != B43_PHYTYPE_G);
2642
2643         default_baseband_attenuation(dev, &gphy->bbatt);
2644         default_radio_attenuation(dev, &gphy->rfatt);
2645         gphy->tx_control = (default_tx_control(dev) << 4);
2646         generate_rfatt_list(dev, &lo->rfatt_list);
2647         generate_bbatt_list(dev, &lo->bbatt_list);
2648
2649         /* Commit previous writes */
2650         b43_read32(dev, B43_MMIO_MACCTL);
2651
2652         if (phy->rev == 1) {
2653                 /* Workaround: Temporarly disable gmode through the early init
2654                  * phase, as the gmode stuff is not needed for phy rev 1 */
2655                 phy->gmode = 0;
2656                 b43_wireless_core_reset(dev, 0);
2657                 b43_phy_initg(dev);
2658                 phy->gmode = 1;
2659                 b43_wireless_core_reset(dev, B43_TMSLOW_GMODE);
2660         }
2661
2662         return 0;
2663 }
2664
2665 static int b43_gphy_op_init(struct b43_wldev *dev)
2666 {
2667         b43_phy_initg(dev);
2668
2669         return 0;
2670 }
2671
2672 static void b43_gphy_op_exit(struct b43_wldev *dev)
2673 {
2674         b43_lo_g_cleanup(dev);
2675 }
2676
2677 static u16 b43_gphy_op_read(struct b43_wldev *dev, u16 reg)
2678 {
2679         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
2680         return b43_read16(dev, B43_MMIO_PHY_DATA);
2681 }
2682
2683 static void b43_gphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
2684 {
2685         b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
2686         b43_write16(dev, B43_MMIO_PHY_DATA, value);
2687 }
2688
2689 static u16 b43_gphy_op_radio_read(struct b43_wldev *dev, u16 reg)
2690 {
2691         /* Register 1 is a 32-bit register. */
2692         B43_WARN_ON(reg == 1);
2693         /* G-PHY needs 0x80 for read access. */
2694         reg |= 0x80;
2695
2696         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
2697         return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
2698 }
2699
2700 static void b43_gphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
2701 {
2702         /* Register 1 is a 32-bit register. */
2703         B43_WARN_ON(reg == 1);
2704
2705         b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
2706         b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
2707 }
2708
2709 static bool b43_gphy_op_supports_hwpctl(struct b43_wldev *dev)
2710 {
2711         return (dev->phy.rev >= 6);
2712 }
2713
2714 static void b43_gphy_op_software_rfkill(struct b43_wldev *dev,
2715                                         enum rfkill_state state)
2716 {
2717         struct b43_phy *phy = &dev->phy;
2718         struct b43_phy_g *gphy = phy->g;
2719         unsigned int channel;
2720
2721         might_sleep();
2722
2723         if (state == RFKILL_STATE_UNBLOCKED) {
2724                 /* Turn radio ON */
2725                 if (phy->radio_on)
2726                         return;
2727
2728                 b43_phy_write(dev, 0x0015, 0x8000);
2729                 b43_phy_write(dev, 0x0015, 0xCC00);
2730                 b43_phy_write(dev, 0x0015, (phy->gmode ? 0x00C0 : 0x0000));
2731                 if (gphy->radio_off_context.valid) {
2732                         /* Restore the RFover values. */
2733                         b43_phy_write(dev, B43_PHY_RFOVER,
2734                                       gphy->radio_off_context.rfover);
2735                         b43_phy_write(dev, B43_PHY_RFOVERVAL,
2736                                       gphy->radio_off_context.rfoverval);
2737                         gphy->radio_off_context.valid = 0;
2738                 }
2739                 channel = phy->channel;
2740                 b43_gphy_channel_switch(dev, 6, 1);
2741                 b43_gphy_channel_switch(dev, channel, 0);
2742         } else {
2743                 /* Turn radio OFF */
2744                 u16 rfover, rfoverval;
2745
2746                 rfover = b43_phy_read(dev, B43_PHY_RFOVER);
2747                 rfoverval = b43_phy_read(dev, B43_PHY_RFOVERVAL);
2748                 gphy->radio_off_context.rfover = rfover;
2749                 gphy->radio_off_context.rfoverval = rfoverval;
2750                 gphy->radio_off_context.valid = 1;
2751                 b43_phy_write(dev, B43_PHY_RFOVER, rfover | 0x008C);
2752                 b43_phy_write(dev, B43_PHY_RFOVERVAL, rfoverval & 0xFF73);
2753         }
2754 }
2755
2756 static int b43_gphy_op_switch_channel(struct b43_wldev *dev,
2757                                       unsigned int new_channel)
2758 {
2759         if ((new_channel < 1) || (new_channel > 14))
2760                 return -EINVAL;
2761         b43_gphy_channel_switch(dev, new_channel, 0);
2762
2763         return 0;
2764 }
2765
2766 static unsigned int b43_gphy_op_get_default_chan(struct b43_wldev *dev)
2767 {
2768         return 1; /* Default to channel 1 */
2769 }
2770
2771 static void b43_gphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna)
2772 {
2773         struct b43_phy *phy = &dev->phy;
2774         u64 hf;
2775         u16 tmp;
2776         int autodiv = 0;
2777
2778         if (antenna == B43_ANTENNA_AUTO0 || antenna == B43_ANTENNA_AUTO1)
2779                 autodiv = 1;
2780
2781         hf = b43_hf_read(dev);
2782         hf &= ~B43_HF_ANTDIVHELP;
2783         b43_hf_write(dev, hf);
2784
2785         tmp = b43_phy_read(dev, B43_PHY_BBANDCFG);
2786         tmp &= ~B43_PHY_BBANDCFG_RXANT;
2787         tmp |= (autodiv ? B43_ANTENNA_AUTO0 : antenna)
2788                         << B43_PHY_BBANDCFG_RXANT_SHIFT;
2789         b43_phy_write(dev, B43_PHY_BBANDCFG, tmp);
2790
2791         if (autodiv) {
2792                 tmp = b43_phy_read(dev, B43_PHY_ANTDWELL);
2793                 if (antenna == B43_ANTENNA_AUTO0)
2794                         tmp &= ~B43_PHY_ANTDWELL_AUTODIV1;
2795                 else
2796                         tmp |= B43_PHY_ANTDWELL_AUTODIV1;
2797                 b43_phy_write(dev, B43_PHY_ANTDWELL, tmp);
2798         }
2799         tmp = b43_phy_read(dev, B43_PHY_ANTWRSETT);
2800         if (autodiv)
2801                 tmp |= B43_PHY_ANTWRSETT_ARXDIV;
2802         else
2803                 tmp &= ~B43_PHY_ANTWRSETT_ARXDIV;
2804         b43_phy_write(dev, B43_PHY_ANTWRSETT, tmp);
2805         if (phy->rev >= 2) {
2806                 tmp = b43_phy_read(dev, B43_PHY_OFDM61);
2807                 tmp |= B43_PHY_OFDM61_10;
2808                 b43_phy_write(dev, B43_PHY_OFDM61, tmp);
2809
2810                 tmp =
2811                     b43_phy_read(dev, B43_PHY_DIVSRCHGAINBACK);
2812                 tmp = (tmp & 0xFF00) | 0x15;
2813                 b43_phy_write(dev, B43_PHY_DIVSRCHGAINBACK,
2814                               tmp);
2815
2816                 if (phy->rev == 2) {
2817                         b43_phy_write(dev, B43_PHY_ADIVRELATED,
2818                                       8);
2819                 } else {
2820                         tmp =
2821                             b43_phy_read(dev,
2822                                          B43_PHY_ADIVRELATED);
2823                         tmp = (tmp & 0xFF00) | 8;
2824                         b43_phy_write(dev, B43_PHY_ADIVRELATED,
2825                                       tmp);
2826                 }
2827         }
2828         if (phy->rev >= 6)
2829                 b43_phy_write(dev, B43_PHY_OFDM9B, 0xDC);
2830
2831         hf |= B43_HF_ANTDIVHELP;
2832         b43_hf_write(dev, hf);
2833 }
2834
2835 static int b43_gphy_op_interf_mitigation(struct b43_wldev *dev,
2836                                          enum b43_interference_mitigation mode)
2837 {
2838         struct b43_phy *phy = &dev->phy;
2839         struct b43_phy_g *gphy = phy->g;
2840         int currentmode;
2841
2842         B43_WARN_ON(phy->type != B43_PHYTYPE_G);
2843         if ((phy->rev == 0) || (!phy->gmode))
2844                 return -ENODEV;
2845
2846         gphy->aci_wlan_automatic = 0;
2847         switch (mode) {
2848         case B43_INTERFMODE_AUTOWLAN:
2849                 gphy->aci_wlan_automatic = 1;
2850                 if (gphy->aci_enable)
2851                         mode = B43_INTERFMODE_MANUALWLAN;
2852                 else
2853                         mode = B43_INTERFMODE_NONE;
2854                 break;
2855         case B43_INTERFMODE_NONE:
2856         case B43_INTERFMODE_NONWLAN:
2857         case B43_INTERFMODE_MANUALWLAN:
2858                 break;
2859         default:
2860                 return -EINVAL;
2861         }
2862
2863         currentmode = gphy->interfmode;
2864         if (currentmode == mode)
2865                 return 0;
2866         if (currentmode != B43_INTERFMODE_NONE)
2867                 b43_radio_interference_mitigation_disable(dev, currentmode);
2868
2869         if (mode == B43_INTERFMODE_NONE) {
2870                 gphy->aci_enable = 0;
2871                 gphy->aci_hw_rssi = 0;
2872         } else
2873                 b43_radio_interference_mitigation_enable(dev, mode);
2874         gphy->interfmode = mode;
2875
2876         return 0;
2877 }
2878
2879 /* http://bcm-specs.sipsolutions.net/EstimatePowerOut
2880  * This function converts a TSSI value to dBm in Q5.2
2881  */
2882 static s8 b43_gphy_estimate_power_out(struct b43_wldev *dev, s8 tssi)
2883 {
2884         struct b43_phy_g *gphy = dev->phy.g;
2885         s8 dbm;
2886         s32 tmp;
2887
2888         tmp = (gphy->tgt_idle_tssi - gphy->cur_idle_tssi + tssi);
2889         tmp = clamp_val(tmp, 0x00, 0x3F);
2890         dbm = gphy->tssi2dbm[tmp];
2891
2892         return dbm;
2893 }
2894
2895 static void b43_put_attenuation_into_ranges(struct b43_wldev *dev,
2896                                             int *_bbatt, int *_rfatt)
2897 {
2898         int rfatt = *_rfatt;
2899         int bbatt = *_bbatt;
2900         struct b43_txpower_lo_control *lo = dev->phy.g->lo_control;
2901
2902         /* Get baseband and radio attenuation values into their permitted ranges.
2903          * Radio attenuation affects power level 4 times as much as baseband. */
2904
2905         /* Range constants */
2906         const int rf_min = lo->rfatt_list.min_val;
2907         const int rf_max = lo->rfatt_list.max_val;
2908         const int bb_min = lo->bbatt_list.min_val;
2909         const int bb_max = lo->bbatt_list.max_val;
2910
2911         while (1) {
2912                 if (rfatt > rf_max && bbatt > bb_max - 4)
2913                         break;  /* Can not get it into ranges */
2914                 if (rfatt < rf_min && bbatt < bb_min + 4)
2915                         break;  /* Can not get it into ranges */
2916                 if (bbatt > bb_max && rfatt > rf_max - 1)
2917                         break;  /* Can not get it into ranges */
2918                 if (bbatt < bb_min && rfatt < rf_min + 1)
2919                         break;  /* Can not get it into ranges */
2920
2921                 if (bbatt > bb_max) {
2922                         bbatt -= 4;
2923                         rfatt += 1;
2924                         continue;
2925                 }
2926                 if (bbatt < bb_min) {
2927                         bbatt += 4;
2928                         rfatt -= 1;
2929                         continue;
2930                 }
2931                 if (rfatt > rf_max) {
2932                         rfatt -= 1;
2933                         bbatt += 4;
2934                         continue;
2935                 }
2936                 if (rfatt < rf_min) {
2937                         rfatt += 1;
2938                         bbatt -= 4;
2939                         continue;
2940                 }
2941                 break;
2942         }
2943
2944         *_rfatt = clamp_val(rfatt, rf_min, rf_max);
2945         *_bbatt = clamp_val(bbatt, bb_min, bb_max);
2946 }
2947
2948 static void b43_gphy_op_adjust_txpower(struct b43_wldev *dev)
2949 {
2950         struct b43_phy *phy = &dev->phy;
2951         struct b43_phy_g *gphy = phy->g;
2952         int rfatt, bbatt;
2953         u8 tx_control;
2954
2955         b43_mac_suspend(dev);
2956
2957         spin_lock_irq(&dev->wl->irq_lock);
2958
2959         /* Calculate the new attenuation values. */
2960         bbatt = gphy->bbatt.att;
2961         bbatt += gphy->bbatt_delta;
2962         rfatt = gphy->rfatt.att;
2963         rfatt += gphy->rfatt_delta;
2964
2965         b43_put_attenuation_into_ranges(dev, &bbatt, &rfatt);
2966         tx_control = gphy->tx_control;
2967         if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 2)) {
2968                 if (rfatt <= 1) {
2969                         if (tx_control == 0) {
2970                                 tx_control =
2971                                     B43_TXCTL_PA2DB |
2972                                     B43_TXCTL_TXMIX;
2973                                 rfatt += 2;
2974                                 bbatt += 2;
2975                         } else if (dev->dev->bus->sprom.
2976                                    boardflags_lo &
2977                                    B43_BFL_PACTRL) {
2978                                 bbatt += 4 * (rfatt - 2);
2979                                 rfatt = 2;
2980                         }
2981                 } else if (rfatt > 4 && tx_control) {
2982                         tx_control = 0;
2983                         if (bbatt < 3) {
2984                                 rfatt -= 3;
2985                                 bbatt += 2;
2986                         } else {
2987                                 rfatt -= 2;
2988                                 bbatt -= 2;
2989                         }
2990                 }
2991         }
2992         /* Save the control values */
2993         gphy->tx_control = tx_control;
2994         b43_put_attenuation_into_ranges(dev, &bbatt, &rfatt);
2995         gphy->rfatt.att = rfatt;
2996         gphy->bbatt.att = bbatt;
2997
2998         /* We drop the lock early, so we can sleep during hardware
2999          * adjustment. Possible races with op_recalc_txpower are harmless,
3000          * as we will be called once again in case we raced. */
3001         spin_unlock_irq(&dev->wl->irq_lock);
3002
3003         if (b43_debug(dev, B43_DBG_XMITPOWER))
3004                 b43dbg(dev->wl, "Adjusting TX power\n");
3005
3006         /* Adjust the hardware */
3007         b43_phy_lock(dev);
3008         b43_radio_lock(dev);
3009         b43_set_txpower_g(dev, &gphy->bbatt, &gphy->rfatt,
3010                           gphy->tx_control);
3011         b43_radio_unlock(dev);
3012         b43_phy_unlock(dev);
3013
3014         b43_mac_enable(dev);
3015 }
3016
3017 static enum b43_txpwr_result b43_gphy_op_recalc_txpower(struct b43_wldev *dev,
3018                                                         bool ignore_tssi)
3019 {
3020         struct b43_phy *phy = &dev->phy;
3021         struct b43_phy_g *gphy = phy->g;
3022         unsigned int average_tssi;
3023         int cck_result, ofdm_result;
3024         int estimated_pwr, desired_pwr, pwr_adjust;
3025         int rfatt_delta, bbatt_delta;
3026         unsigned int max_pwr;
3027
3028         /* First get the average TSSI */
3029         cck_result = b43_phy_shm_tssi_read(dev, B43_SHM_SH_TSSI_CCK);
3030         ofdm_result = b43_phy_shm_tssi_read(dev, B43_SHM_SH_TSSI_OFDM_G);
3031         if ((cck_result < 0) && (ofdm_result < 0)) {
3032                 /* No TSSI information available */
3033                 if (!ignore_tssi)
3034                         goto no_adjustment_needed;
3035                 cck_result = 0;
3036                 ofdm_result = 0;
3037         }
3038         if (cck_result < 0)
3039                 average_tssi = ofdm_result;
3040         else if (ofdm_result < 0)
3041                 average_tssi = cck_result;
3042         else
3043                 average_tssi = (cck_result + ofdm_result) / 2;
3044         /* Merge the average with the stored value. */
3045         if (likely(gphy->average_tssi != 0xFF))
3046                 average_tssi = (average_tssi + gphy->average_tssi) / 2;
3047         gphy->average_tssi = average_tssi;
3048         B43_WARN_ON(average_tssi >= B43_TSSI_MAX);
3049
3050         /* Estimate the TX power emission based on the TSSI */
3051         estimated_pwr = b43_gphy_estimate_power_out(dev, average_tssi);
3052
3053         B43_WARN_ON(phy->type != B43_PHYTYPE_G);
3054         max_pwr = dev->dev->bus->sprom.maxpwr_bg;
3055         if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL)
3056                 max_pwr -= 3; /* minus 0.75 */
3057         if (unlikely(max_pwr >= INT_TO_Q52(30/*dBm*/))) {
3058                 b43warn(dev->wl,
3059                         "Invalid max-TX-power value in SPROM.\n");
3060                 max_pwr = INT_TO_Q52(20); /* fake it */
3061                 dev->dev->bus->sprom.maxpwr_bg = max_pwr;
3062         }
3063
3064         /* Get desired power (in Q5.2) */
3065         if (phy->desired_txpower < 0)
3066                 desired_pwr = INT_TO_Q52(0);
3067         else
3068                 desired_pwr = INT_TO_Q52(phy->desired_txpower);
3069         /* And limit it. max_pwr already is Q5.2 */
3070         desired_pwr = clamp_val(desired_pwr, 0, max_pwr);
3071         if (b43_debug(dev, B43_DBG_XMITPOWER)) {
3072                 b43dbg(dev->wl,
3073                        "[TX power]  current = " Q52_FMT
3074                        " dBm,  desired = " Q52_FMT
3075                        " dBm,  max = " Q52_FMT "\n",
3076                        Q52_ARG(estimated_pwr),
3077                        Q52_ARG(desired_pwr),
3078                        Q52_ARG(max_pwr));
3079         }
3080
3081         /* Calculate the adjustment delta. */
3082         pwr_adjust = desired_pwr - estimated_pwr;
3083         if (pwr_adjust == 0)
3084                 goto no_adjustment_needed;
3085
3086         /* RF attenuation delta. */
3087         rfatt_delta = ((pwr_adjust + 7) / 8);
3088         /* Lower attenuation => Bigger power output. Negate it. */
3089         rfatt_delta = -rfatt_delta;
3090
3091         /* Baseband attenuation delta. */
3092         bbatt_delta = pwr_adjust / 2;
3093         /* Lower attenuation => Bigger power output. Negate it. */
3094         bbatt_delta = -bbatt_delta;
3095         /* RF att affects power level 4 times as much as
3096          * Baseband attennuation. Subtract it. */
3097         bbatt_delta -= 4 * rfatt_delta;
3098
3099 #if B43_DEBUG
3100         if (b43_debug(dev, B43_DBG_XMITPOWER)) {
3101                 int dbm = pwr_adjust < 0 ? -pwr_adjust : pwr_adjust;
3102                 b43dbg(dev->wl,
3103                        "[TX power deltas]  %s" Q52_FMT " dBm   =>   "
3104                        "bbatt-delta = %d,  rfatt-delta = %d\n",
3105                        (pwr_adjust < 0 ? "-" : ""), Q52_ARG(dbm),
3106                        bbatt_delta, rfatt_delta);
3107         }
3108 #endif /* DEBUG */
3109
3110         /* So do we finally need to adjust something in hardware? */
3111         if ((rfatt_delta == 0) && (bbatt_delta == 0))
3112                 goto no_adjustment_needed;
3113
3114         /* Save the deltas for later when we adjust the power. */
3115         gphy->bbatt_delta = bbatt_delta;
3116         gphy->rfatt_delta = rfatt_delta;
3117
3118         /* We need to adjust the TX power on the device. */
3119         return B43_TXPWR_RES_NEED_ADJUST;
3120
3121 no_adjustment_needed:
3122         return B43_TXPWR_RES_DONE;
3123 }
3124
3125 static void b43_gphy_op_pwork_15sec(struct b43_wldev *dev)
3126 {
3127         struct b43_phy *phy = &dev->phy;
3128         struct b43_phy_g *gphy = phy->g;
3129
3130         b43_mac_suspend(dev);
3131         //TODO: update_aci_moving_average
3132         if (gphy->aci_enable && gphy->aci_wlan_automatic) {
3133                 if (!gphy->aci_enable && 1 /*TODO: not scanning? */ ) {
3134                         if (0 /*TODO: bunch of conditions */ ) {
3135                                 phy->ops->interf_mitigation(dev,
3136                                         B43_INTERFMODE_MANUALWLAN);
3137                         }
3138                 } else if (0 /*TODO*/) {
3139                            if (/*(aci_average > 1000) &&*/ !b43_gphy_aci_scan(dev))
3140                                 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
3141                 }
3142         } else if (gphy->interfmode == B43_INTERFMODE_NONWLAN &&
3143                    phy->rev == 1) {
3144                 //TODO: implement rev1 workaround
3145         }
3146         b43_lo_g_maintanance_work(dev);
3147         b43_mac_enable(dev);
3148 }
3149
3150 static void b43_gphy_op_pwork_60sec(struct b43_wldev *dev)
3151 {
3152         struct b43_phy *phy = &dev->phy;
3153
3154         if (!(dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI))
3155                 return;
3156
3157         b43_mac_suspend(dev);
3158         b43_calc_nrssi_slope(dev);
3159         if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) {
3160                 u8 old_chan = phy->channel;
3161
3162                 /* VCO Calibration */
3163                 if (old_chan >= 8)
3164                         b43_switch_channel(dev, 1);
3165                 else
3166                         b43_switch_channel(dev, 13);
3167                 b43_switch_channel(dev, old_chan);
3168         }
3169         b43_mac_enable(dev);
3170 }
3171
3172 const struct b43_phy_operations b43_phyops_g = {
3173         .allocate               = b43_gphy_op_allocate,
3174         .free                   = b43_gphy_op_free,
3175         .prepare_structs        = b43_gphy_op_prepare_structs,
3176         .prepare_hardware       = b43_gphy_op_prepare_hardware,
3177         .init                   = b43_gphy_op_init,
3178         .exit                   = b43_gphy_op_exit,
3179         .phy_read               = b43_gphy_op_read,
3180         .phy_write              = b43_gphy_op_write,
3181         .radio_read             = b43_gphy_op_radio_read,
3182         .radio_write            = b43_gphy_op_radio_write,
3183         .supports_hwpctl        = b43_gphy_op_supports_hwpctl,
3184         .software_rfkill        = b43_gphy_op_software_rfkill,
3185         .switch_analog          = b43_phyop_switch_analog_generic,
3186         .switch_channel         = b43_gphy_op_switch_channel,
3187         .get_default_chan       = b43_gphy_op_get_default_chan,
3188         .set_rx_antenna         = b43_gphy_op_set_rx_antenna,
3189         .interf_mitigation      = b43_gphy_op_interf_mitigation,
3190         .recalc_txpower         = b43_gphy_op_recalc_txpower,
3191         .adjust_txpower         = b43_gphy_op_adjust_txpower,
3192         .pwork_15sec            = b43_gphy_op_pwork_15sec,
3193         .pwork_60sec            = b43_gphy_op_pwork_60sec,
3194 };