3 Broadcom B43 wireless driver
6 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
7 Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
8 Copyright (c) 2005-2008 Michael Buesch <mb@bu3sch.de>
9 Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
10 Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; see the file COPYING. If not, write to
24 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
25 Boston, MA 02110-1301, USA.
29 #include "phy_common.h"
37 int b43_phy_operations_setup(struct b43_wldev *dev)
39 struct b43_phy *phy = &(dev->phy);
46 phy->ops = &b43_phyops_a;
49 phy->ops = &b43_phyops_g;
52 #ifdef CONFIG_B43_NPHY
53 phy->ops = &b43_phyops_n;
60 if (B43_WARN_ON(!phy->ops))
63 err = phy->ops->allocate(dev);
70 int b43_phy_init(struct b43_wldev *dev)
72 struct b43_phy *phy = &dev->phy;
73 const struct b43_phy_operations *ops = phy->ops;
76 phy->channel = ops->get_default_chan(dev);
78 ops->software_rfkill(dev, RFKILL_STATE_UNBLOCKED);
81 b43err(dev->wl, "PHY init failed\n");
84 /* Make sure to switch hardware and firmware (SHM) to
85 * the default channel. */
86 err = b43_switch_channel(dev, ops->get_default_chan(dev));
88 b43err(dev->wl, "PHY init: Channel switch to default failed\n");
98 ops->software_rfkill(dev, RFKILL_STATE_SOFT_BLOCKED);
103 void b43_phy_exit(struct b43_wldev *dev)
105 const struct b43_phy_operations *ops = dev->phy.ops;
107 ops->software_rfkill(dev, RFKILL_STATE_SOFT_BLOCKED);
112 bool b43_has_hardware_pctl(struct b43_wldev *dev)
114 if (!dev->phy.hardware_power_control)
116 if (!dev->phy.ops->supports_hwpctl)
118 return dev->phy.ops->supports_hwpctl(dev);
121 void b43_radio_lock(struct b43_wldev *dev)
125 macctl = b43_read32(dev, B43_MMIO_MACCTL);
126 B43_WARN_ON(macctl & B43_MACCTL_RADIOLOCK);
127 macctl |= B43_MACCTL_RADIOLOCK;
128 b43_write32(dev, B43_MMIO_MACCTL, macctl);
129 /* Commit the write and wait for the device
130 * to exit any radio register access. */
131 b43_read32(dev, B43_MMIO_MACCTL);
135 void b43_radio_unlock(struct b43_wldev *dev)
139 /* Commit any write */
140 b43_read16(dev, B43_MMIO_PHY_VER);
142 macctl = b43_read32(dev, B43_MMIO_MACCTL);
143 B43_WARN_ON(!(macctl & B43_MACCTL_RADIOLOCK));
144 macctl &= ~B43_MACCTL_RADIOLOCK;
145 b43_write32(dev, B43_MMIO_MACCTL, macctl);
148 void b43_phy_lock(struct b43_wldev *dev)
151 B43_WARN_ON(dev->phy.phy_locked);
152 dev->phy.phy_locked = 1;
154 B43_WARN_ON(dev->dev->id.revision < 3);
156 if (!b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
157 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
160 void b43_phy_unlock(struct b43_wldev *dev)
163 B43_WARN_ON(!dev->phy.phy_locked);
164 dev->phy.phy_locked = 0;
166 B43_WARN_ON(dev->dev->id.revision < 3);
168 if (!b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
169 b43_power_saving_ctl_bits(dev, 0);
172 u16 b43_radio_read(struct b43_wldev *dev, u16 reg)
174 return dev->phy.ops->radio_read(dev, reg);
177 void b43_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
179 dev->phy.ops->radio_write(dev, reg, value);
182 void b43_radio_mask(struct b43_wldev *dev, u16 offset, u16 mask)
184 b43_radio_write16(dev, offset,
185 b43_radio_read16(dev, offset) & mask);
188 void b43_radio_set(struct b43_wldev *dev, u16 offset, u16 set)
190 b43_radio_write16(dev, offset,
191 b43_radio_read16(dev, offset) | set);
194 void b43_radio_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
196 b43_radio_write16(dev, offset,
197 (b43_radio_read16(dev, offset) & mask) | set);
200 u16 b43_phy_read(struct b43_wldev *dev, u16 reg)
202 return dev->phy.ops->phy_read(dev, reg);
205 void b43_phy_write(struct b43_wldev *dev, u16 reg, u16 value)
207 dev->phy.ops->phy_write(dev, reg, value);
210 void b43_phy_mask(struct b43_wldev *dev, u16 offset, u16 mask)
212 b43_phy_write(dev, offset,
213 b43_phy_read(dev, offset) & mask);
216 void b43_phy_set(struct b43_wldev *dev, u16 offset, u16 set)
218 b43_phy_write(dev, offset,
219 b43_phy_read(dev, offset) | set);
222 void b43_phy_maskset(struct b43_wldev *dev, u16 offset, u16 mask, u16 set)
224 b43_phy_write(dev, offset,
225 (b43_phy_read(dev, offset) & mask) | set);
228 int b43_switch_channel(struct b43_wldev *dev, unsigned int new_channel)
230 struct b43_phy *phy = &(dev->phy);
231 u16 channelcookie, savedcookie;
234 if (new_channel == B43_DEFAULT_CHANNEL)
235 new_channel = phy->ops->get_default_chan(dev);
237 /* First we set the channel radio code to prevent the
238 * firmware from sending ghost packets.
240 channelcookie = new_channel;
241 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
242 channelcookie |= 0x100;
243 //FIXME set 40Mhz flag if required
244 savedcookie = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN);
245 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_CHAN, channelcookie);
247 /* Now try to switch the PHY hardware channel. */
248 err = phy->ops->switch_channel(dev, new_channel);
250 goto err_restore_cookie;
252 dev->phy.channel = new_channel;
253 /* Wait for the radio to tune to the channel and stabilize. */
259 b43_shm_write16(dev, B43_SHM_SHARED,
260 B43_SHM_SH_CHAN, savedcookie);
265 void b43_software_rfkill(struct b43_wldev *dev, enum rfkill_state state)
267 struct b43_phy *phy = &dev->phy;
269 if (state == RFKILL_STATE_HARD_BLOCKED) {
270 /* We cannot hardware-block the device */
271 state = RFKILL_STATE_SOFT_BLOCKED;
274 phy->ops->software_rfkill(dev, state);
275 phy->radio_on = (state == RFKILL_STATE_UNBLOCKED);
279 * b43_phy_txpower_adjust_work - TX power workqueue.
281 * Workqueue for updating the TX power parameters in hardware.
283 void b43_phy_txpower_adjust_work(struct work_struct *work)
285 struct b43_wl *wl = container_of(work, struct b43_wl,
286 txpower_adjust_work);
287 struct b43_wldev *dev;
289 mutex_lock(&wl->mutex);
290 dev = wl->current_dev;
292 if (likely(dev && (b43_status(dev) >= B43_STAT_STARTED)))
293 dev->phy.ops->adjust_txpower(dev);
295 mutex_unlock(&wl->mutex);
298 /* Called with wl->irq_lock locked */
299 void b43_phy_txpower_check(struct b43_wldev *dev, unsigned int flags)
301 struct b43_phy *phy = &dev->phy;
302 unsigned long now = jiffies;
303 enum b43_txpwr_result result;
305 if (!(flags & B43_TXPWR_IGNORE_TIME)) {
306 /* Check if it's time for a TXpower check. */
307 if (time_before(now, phy->next_txpwr_check_time))
308 return; /* Not yet */
310 /* The next check will be needed in two seconds, or later. */
311 phy->next_txpwr_check_time = round_jiffies(now + (HZ * 2));
313 if ((dev->dev->bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
314 (dev->dev->bus->boardinfo.type == SSB_BOARD_BU4306))
315 return; /* No software txpower adjustment needed */
317 result = phy->ops->recalc_txpower(dev, !!(flags & B43_TXPWR_IGNORE_TSSI));
318 if (result == B43_TXPWR_RES_DONE)
319 return; /* We are done. */
320 B43_WARN_ON(result != B43_TXPWR_RES_NEED_ADJUST);
321 B43_WARN_ON(phy->ops->adjust_txpower == NULL);
323 /* We must adjust the transmission power in hardware.
324 * Schedule b43_phy_txpower_adjust_work(). */
325 queue_work(dev->wl->hw->workqueue, &dev->wl->txpower_adjust_work);
328 int b43_phy_shm_tssi_read(struct b43_wldev *dev, u16 shm_offset)
330 const bool is_ofdm = (shm_offset != B43_SHM_SH_TSSI_CCK);
331 unsigned int a, b, c, d;
332 unsigned int average;
335 tmp = b43_shm_read32(dev, B43_SHM_SHARED, shm_offset);
337 b = (tmp >> 8) & 0xFF;
338 c = (tmp >> 16) & 0xFF;
339 d = (tmp >> 24) & 0xFF;
340 if (a == 0 || a == B43_TSSI_MAX ||
341 b == 0 || b == B43_TSSI_MAX ||
342 c == 0 || c == B43_TSSI_MAX ||
343 d == 0 || d == B43_TSSI_MAX)
345 /* The values are OK. Clear them. */
346 tmp = B43_TSSI_MAX | (B43_TSSI_MAX << 8) |
347 (B43_TSSI_MAX << 16) | (B43_TSSI_MAX << 24);
348 b43_shm_write32(dev, B43_SHM_SHARED, shm_offset, tmp);
357 /* Get the average of the values with 0.5 added to each value. */
358 average = (a + b + c + d + 2) / 4;
360 /* Adjust for CCK-boost */
361 if (b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO)
363 average = (average >= 13) ? (average - 13) : 0;