3 Broadcom B43 wireless driver
4 IEEE 802.11a PHY driver
6 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>,
7 Copyright (c) 2005-2007 Stefano Brivio <stefano.brivio@polimi.it>
8 Copyright (c) 2005-2008 Michael Buesch <mb@bu3sch.de>
9 Copyright (c) 2005, 2006 Danny van Dyk <kugelfang@gentoo.org>
10 Copyright (c) 2005, 2006 Andreas Jaggi <andreas.jaggi@waterwave.ch>
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; see the file COPYING. If not, write to
24 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
25 Boston, MA 02110-1301, USA.
31 #include "phy_common.h"
37 /* Get the freq, as it has to be written to the device. */
38 static inline u16 channel2freq_a(u8 channel)
40 B43_WARN_ON(channel > 200);
42 return (5000 + 5 * channel);
45 static inline u16 freq_r3A_value(u16 frequency)
51 else if (frequency < 5321)
53 else if (frequency < 5806)
62 /* This function converts a TSSI value to dBm in Q5.2 */
63 static s8 b43_aphy_estimate_power_out(struct b43_wldev *dev, s8 tssi)
65 struct b43_phy *phy = &dev->phy;
66 struct b43_phy_a *aphy = phy->a;
70 tmp = (aphy->tgt_idle_tssi - aphy->cur_idle_tssi + tssi);
72 tmp = clamp_val(tmp, 0x00, 0xFF);
73 dbm = aphy->tssi2dbm[tmp];
74 //TODO: There's a FIXME on the specs
80 static void b43_radio_set_tx_iq(struct b43_wldev *dev)
82 static const u8 data_high[5] = { 0x00, 0x40, 0x80, 0x90, 0xD0 };
83 static const u8 data_low[5] = { 0x00, 0x01, 0x05, 0x06, 0x0A };
84 u16 tmp = b43_radio_read16(dev, 0x001E);
87 for (i = 0; i < 5; i++) {
88 for (j = 0; j < 5; j++) {
89 if (tmp == (data_high[i] << 4 | data_low[j])) {
90 b43_phy_write(dev, 0x0069,
91 (i - j) << 8 | 0x00C0);
98 static void aphy_channel_switch(struct b43_wldev *dev, unsigned int channel)
102 freq = channel2freq_a(channel);
104 r8 = b43_radio_read16(dev, 0x0008);
105 b43_write16(dev, 0x03F0, freq);
106 b43_radio_write16(dev, 0x0008, r8);
108 //TODO: write max channel TX power? to Radio 0x2D
109 tmp = b43_radio_read16(dev, 0x002E);
111 //TODO: OR tmp with the Power out estimation for this channel?
112 b43_radio_write16(dev, 0x002E, tmp);
114 if (freq >= 4920 && freq <= 5500) {
116 * r8 = (((freq * 15 * 0xE1FC780F) >> 32) / 29) & 0x0F;
117 * = (freq * 0.025862069
119 r8 = 3 * freq / 116; /* is equal to r8 = freq * 0.025862 */
121 b43_radio_write16(dev, 0x0007, (r8 << 4) | r8);
122 b43_radio_write16(dev, 0x0020, (r8 << 4) | r8);
123 b43_radio_write16(dev, 0x0021, (r8 << 4) | r8);
124 b43_radio_write16(dev, 0x0022, (b43_radio_read16(dev, 0x0022)
125 & 0x000F) | (r8 << 4));
126 b43_radio_write16(dev, 0x002A, (r8 << 4));
127 b43_radio_write16(dev, 0x002B, (r8 << 4));
128 b43_radio_write16(dev, 0x0008, (b43_radio_read16(dev, 0x0008)
129 & 0x00F0) | (r8 << 4));
130 b43_radio_write16(dev, 0x0029, (b43_radio_read16(dev, 0x0029)
132 b43_radio_write16(dev, 0x0035, 0x00AA);
133 b43_radio_write16(dev, 0x0036, 0x0085);
134 b43_radio_write16(dev, 0x003A, (b43_radio_read16(dev, 0x003A)
136 freq_r3A_value(freq));
137 b43_radio_write16(dev, 0x003D,
138 b43_radio_read16(dev, 0x003D) & 0x00FF);
139 b43_radio_write16(dev, 0x0081, (b43_radio_read16(dev, 0x0081)
141 b43_radio_write16(dev, 0x0035,
142 b43_radio_read16(dev, 0x0035) & 0xFFEF);
143 b43_radio_write16(dev, 0x0035, (b43_radio_read16(dev, 0x0035)
145 b43_radio_set_tx_iq(dev);
146 //TODO: TSSI2dbm workaround
147 //FIXME b43_phy_xmitpower(dev);
150 static void b43_radio_init2060(struct b43_wldev *dev)
152 b43_radio_write16(dev, 0x0004, 0x00C0);
153 b43_radio_write16(dev, 0x0005, 0x0008);
154 b43_radio_write16(dev, 0x0009, 0x0040);
155 b43_radio_write16(dev, 0x0005, 0x00AA);
156 b43_radio_write16(dev, 0x0032, 0x008F);
157 b43_radio_write16(dev, 0x0006, 0x008F);
158 b43_radio_write16(dev, 0x0034, 0x008F);
159 b43_radio_write16(dev, 0x002C, 0x0007);
160 b43_radio_write16(dev, 0x0082, 0x0080);
161 b43_radio_write16(dev, 0x0080, 0x0000);
162 b43_radio_write16(dev, 0x003F, 0x00DA);
163 b43_radio_write16(dev, 0x0005, b43_radio_read16(dev, 0x0005) & ~0x0008);
164 b43_radio_write16(dev, 0x0081, b43_radio_read16(dev, 0x0081) & ~0x0010);
165 b43_radio_write16(dev, 0x0081, b43_radio_read16(dev, 0x0081) & ~0x0020);
166 b43_radio_write16(dev, 0x0081, b43_radio_read16(dev, 0x0081) & ~0x0020);
167 msleep(1); /* delay 400usec */
169 b43_radio_write16(dev, 0x0081,
170 (b43_radio_read16(dev, 0x0081) & ~0x0020) | 0x0010);
171 msleep(1); /* delay 400usec */
173 b43_radio_write16(dev, 0x0005,
174 (b43_radio_read16(dev, 0x0005) & ~0x0008) | 0x0008);
175 b43_radio_write16(dev, 0x0085, b43_radio_read16(dev, 0x0085) & ~0x0010);
176 b43_radio_write16(dev, 0x0005, b43_radio_read16(dev, 0x0005) & ~0x0008);
177 b43_radio_write16(dev, 0x0081, b43_radio_read16(dev, 0x0081) & ~0x0040);
178 b43_radio_write16(dev, 0x0081,
179 (b43_radio_read16(dev, 0x0081) & ~0x0040) | 0x0040);
180 b43_radio_write16(dev, 0x0005,
181 (b43_radio_read16(dev, 0x0081) & ~0x0008) | 0x0008);
182 b43_phy_write(dev, 0x0063, 0xDDC6);
183 b43_phy_write(dev, 0x0069, 0x07BE);
184 b43_phy_write(dev, 0x006A, 0x0000);
186 aphy_channel_switch(dev, dev->phy.ops->get_default_chan(dev));
191 static void b43_phy_rssiagc(struct b43_wldev *dev, u8 enable)
195 if (dev->phy.rev < 3) {
197 for (i = 0; i < B43_TAB_RSSIAGC1_SIZE; i++) {
198 b43_ofdmtab_write16(dev,
199 B43_OFDMTAB_LNAHPFGAIN1, i, 0xFFF8);
200 b43_ofdmtab_write16(dev,
201 B43_OFDMTAB_WRSSI, i, 0xFFF8);
204 for (i = 0; i < B43_TAB_RSSIAGC1_SIZE; i++) {
205 b43_ofdmtab_write16(dev,
206 B43_OFDMTAB_LNAHPFGAIN1, i, b43_tab_rssiagc1[i]);
207 b43_ofdmtab_write16(dev,
208 B43_OFDMTAB_WRSSI, i, b43_tab_rssiagc1[i]);
212 for (i = 0; i < B43_TAB_RSSIAGC1_SIZE; i++)
213 b43_ofdmtab_write16(dev,
214 B43_OFDMTAB_WRSSI, i, 0x0820);
216 for (i = 0; i < B43_TAB_RSSIAGC2_SIZE; i++)
217 b43_ofdmtab_write16(dev,
218 B43_OFDMTAB_WRSSI, i, b43_tab_rssiagc2[i]);
222 static void b43_phy_ww(struct b43_wldev *dev)
224 u16 b, curr_s, best_s = 0xFFFF;
227 b43_phy_mask(dev, B43_PHY_CRS0, ~B43_PHY_CRS0_EN);
228 b43_phy_set(dev, B43_PHY_OFDM(0x1B), 0x1000);
229 b43_phy_write(dev, B43_PHY_OFDM(0x82),
230 (b43_phy_read(dev, B43_PHY_OFDM(0x82)) & 0xF0FF) | 0x0300);
231 b43_radio_write16(dev, 0x0009,
232 b43_radio_read16(dev, 0x0009) | 0x0080);
233 b43_radio_write16(dev, 0x0012,
234 (b43_radio_read16(dev, 0x0012) & 0xFFFC) | 0x0002);
235 b43_wa_initgains(dev);
236 b43_phy_write(dev, B43_PHY_OFDM(0xBA), 0x3ED5);
237 b = b43_phy_read(dev, B43_PHY_PWRDOWN);
238 b43_phy_write(dev, B43_PHY_PWRDOWN, (b & 0xFFF8) | 0x0005);
239 b43_radio_write16(dev, 0x0004,
240 b43_radio_read16(dev, 0x0004) | 0x0004);
241 for (i = 0x10; i <= 0x20; i++) {
242 b43_radio_write16(dev, 0x0013, i);
243 curr_s = b43_phy_read(dev, B43_PHY_OTABLEQ) & 0x00FF;
247 } else if (curr_s >= 0x0080)
248 curr_s = 0x0100 - curr_s;
252 b43_phy_write(dev, B43_PHY_PWRDOWN, b);
253 b43_radio_write16(dev, 0x0004,
254 b43_radio_read16(dev, 0x0004) & 0xFFFB);
255 b43_radio_write16(dev, 0x0013, best_s);
256 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1_R1, 0, 0xFFEC);
257 b43_phy_write(dev, B43_PHY_OFDM(0xB7), 0x1E80);
258 b43_phy_write(dev, B43_PHY_OFDM(0xB6), 0x1C00);
259 b43_phy_write(dev, B43_PHY_OFDM(0xB5), 0x0EC0);
260 b43_phy_write(dev, B43_PHY_OFDM(0xB2), 0x00C0);
261 b43_phy_write(dev, B43_PHY_OFDM(0xB9), 0x1FFF);
262 b43_phy_write(dev, B43_PHY_OFDM(0xBB),
263 (b43_phy_read(dev, B43_PHY_OFDM(0xBB)) & 0xF000) | 0x0053);
264 b43_phy_write(dev, B43_PHY_OFDM61,
265 (b43_phy_read(dev, B43_PHY_OFDM61) & 0xFE1F) | 0x0120);
266 b43_phy_write(dev, B43_PHY_OFDM(0x13),
267 (b43_phy_read(dev, B43_PHY_OFDM(0x13)) & 0x0FFF) | 0x3000);
268 b43_phy_write(dev, B43_PHY_OFDM(0x14),
269 (b43_phy_read(dev, B43_PHY_OFDM(0x14)) & 0x0FFF) | 0x3000);
270 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 6, 0x0017);
271 for (i = 0; i < 6; i++)
272 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, i, 0x000F);
273 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0D, 0x000E);
274 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0E, 0x0011);
275 b43_ofdmtab_write16(dev, B43_OFDMTAB_AGC1, 0x0F, 0x0013);
276 b43_phy_write(dev, B43_PHY_OFDM(0x33), 0x5030);
277 b43_phy_set(dev, B43_PHY_CRS0, B43_PHY_CRS0_EN);
280 static void hardware_pctl_init_aphy(struct b43_wldev *dev)
285 void b43_phy_inita(struct b43_wldev *dev)
287 struct ssb_bus *bus = dev->dev->bus;
288 struct b43_phy *phy = &dev->phy;
290 /* This lowlevel A-PHY init is also called from G-PHY init.
291 * So we must not access phy->a, if called from G-PHY code.
293 B43_WARN_ON((phy->type != B43_PHYTYPE_A) &&
294 (phy->type != B43_PHYTYPE_G));
299 if (phy->type == B43_PHYTYPE_A)
300 b43_phy_mask(dev, B43_PHY_OFDM(0x1B), ~0x1000);
301 if (b43_phy_read(dev, B43_PHY_ENCORE) & B43_PHY_ENCORE_EN)
302 b43_phy_set(dev, B43_PHY_ENCORE, 0x0010);
304 b43_phy_mask(dev, B43_PHY_ENCORE, ~0x1010);
309 if (phy->type == B43_PHYTYPE_A) {
310 if (phy->gmode && (phy->rev < 3))
311 b43_phy_set(dev, 0x0034, 0x0001);
312 b43_phy_rssiagc(dev, 0);
314 b43_phy_set(dev, B43_PHY_CRS0, B43_PHY_CRS0_EN);
316 b43_radio_init2060(dev);
318 if ((bus->boardinfo.vendor == SSB_BOARDVENDOR_BCM) &&
319 ((bus->boardinfo.type == SSB_BOARD_BU4306) ||
320 (bus->boardinfo.type == SSB_BOARD_BU4309))) {
327 hardware_pctl_init_aphy(dev);
329 //TODO: radar detection
332 if ((phy->type == B43_PHYTYPE_G) &&
333 (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL)) {
334 b43_phy_write(dev, B43_PHY_OFDM(0x6E),
335 (b43_phy_read(dev, B43_PHY_OFDM(0x6E))
340 /* Initialise the TSSI->dBm lookup table */
341 static int b43_aphy_init_tssi2dbm_table(struct b43_wldev *dev)
343 struct b43_phy *phy = &dev->phy;
344 struct b43_phy_a *aphy = phy->a;
345 s16 pab0, pab1, pab2;
347 pab0 = (s16) (dev->dev->bus->sprom.pa1b0);
348 pab1 = (s16) (dev->dev->bus->sprom.pa1b1);
349 pab2 = (s16) (dev->dev->bus->sprom.pa1b2);
351 if (pab0 != 0 && pab1 != 0 && pab2 != 0 &&
352 pab0 != -1 && pab1 != -1 && pab2 != -1) {
353 /* The pabX values are set in SPROM. Use them. */
354 if ((s8) dev->dev->bus->sprom.itssi_a != 0 &&
355 (s8) dev->dev->bus->sprom.itssi_a != -1)
356 aphy->tgt_idle_tssi =
357 (s8) (dev->dev->bus->sprom.itssi_a);
359 aphy->tgt_idle_tssi = 62;
360 aphy->tssi2dbm = b43_generate_dyn_tssi2dbm_tab(dev, pab0,
365 /* pabX values not set in SPROM,
366 * but APHY needs a generated table. */
367 aphy->tssi2dbm = NULL;
368 b43err(dev->wl, "Could not generate tssi2dBm "
369 "table (wrong SPROM info)!\n");
376 static int b43_aphy_op_allocate(struct b43_wldev *dev)
378 struct b43_phy_a *aphy;
381 aphy = kzalloc(sizeof(*aphy), GFP_KERNEL);
386 err = b43_aphy_init_tssi2dbm_table(dev);
399 static void b43_aphy_op_prepare_structs(struct b43_wldev *dev)
401 struct b43_phy *phy = &dev->phy;
402 struct b43_phy_a *aphy = phy->a;
403 const void *tssi2dbm;
406 /* tssi2dbm table is constant, so it is initialized at alloc time.
407 * Save a copy of the pointer. */
408 tssi2dbm = aphy->tssi2dbm;
409 tgt_idle_tssi = aphy->tgt_idle_tssi;
411 /* Zero out the whole PHY structure. */
412 memset(aphy, 0, sizeof(*aphy));
414 aphy->tssi2dbm = tssi2dbm;
415 aphy->tgt_idle_tssi = tgt_idle_tssi;
417 //TODO init struct b43_phy_a
421 static void b43_aphy_op_free(struct b43_wldev *dev)
423 struct b43_phy *phy = &dev->phy;
424 struct b43_phy_a *aphy = phy->a;
426 kfree(aphy->tssi2dbm);
427 aphy->tssi2dbm = NULL;
433 static int b43_aphy_op_init(struct b43_wldev *dev)
440 static inline u16 adjust_phyreg(struct b43_wldev *dev, u16 offset)
442 /* OFDM registers are base-registers for the A-PHY. */
443 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
444 offset &= ~B43_PHYROUTE;
445 offset |= B43_PHYROUTE_BASE;
449 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
450 /* Ext-G registers are only available on G-PHYs */
451 b43err(dev->wl, "Invalid EXT-G PHY access at "
452 "0x%04X on A-PHY\n", offset);
455 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_N_BMODE) {
456 /* N-BMODE registers are only available on N-PHYs */
457 b43err(dev->wl, "Invalid N-BMODE PHY access at "
458 "0x%04X on A-PHY\n", offset);
461 #endif /* B43_DEBUG */
466 static u16 b43_aphy_op_read(struct b43_wldev *dev, u16 reg)
468 reg = adjust_phyreg(dev, reg);
469 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
470 return b43_read16(dev, B43_MMIO_PHY_DATA);
473 static void b43_aphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
475 reg = adjust_phyreg(dev, reg);
476 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
477 b43_write16(dev, B43_MMIO_PHY_DATA, value);
480 static u16 b43_aphy_op_radio_read(struct b43_wldev *dev, u16 reg)
482 /* Register 1 is a 32-bit register. */
483 B43_WARN_ON(reg == 1);
484 /* A-PHY needs 0x40 for read access */
487 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
488 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
491 static void b43_aphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
493 /* Register 1 is a 32-bit register. */
494 B43_WARN_ON(reg == 1);
496 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
497 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
500 static bool b43_aphy_op_supports_hwpctl(struct b43_wldev *dev)
502 return (dev->phy.rev >= 5);
505 static void b43_aphy_op_software_rfkill(struct b43_wldev *dev,
506 enum rfkill_state state)
508 struct b43_phy *phy = &dev->phy;
510 if (state == RFKILL_STATE_UNBLOCKED) {
513 b43_radio_write16(dev, 0x0004, 0x00C0);
514 b43_radio_write16(dev, 0x0005, 0x0008);
515 b43_phy_mask(dev, 0x0010, 0xFFF7);
516 b43_phy_mask(dev, 0x0011, 0xFFF7);
517 b43_radio_init2060(dev);
519 b43_radio_write16(dev, 0x0004, 0x00FF);
520 b43_radio_write16(dev, 0x0005, 0x00FB);
521 b43_phy_set(dev, 0x0010, 0x0008);
522 b43_phy_set(dev, 0x0011, 0x0008);
526 static int b43_aphy_op_switch_channel(struct b43_wldev *dev,
527 unsigned int new_channel)
529 if (new_channel > 200)
531 aphy_channel_switch(dev, new_channel);
536 static unsigned int b43_aphy_op_get_default_chan(struct b43_wldev *dev)
538 return 36; /* Default to channel 36 */
541 static void b43_aphy_op_set_rx_antenna(struct b43_wldev *dev, int antenna)
543 struct b43_phy *phy = &dev->phy;
548 if (antenna == B43_ANTENNA_AUTO0 || antenna == B43_ANTENNA_AUTO1)
551 hf = b43_hf_read(dev);
552 hf &= ~B43_HF_ANTDIVHELP;
553 b43_hf_write(dev, hf);
555 tmp = b43_phy_read(dev, B43_PHY_BBANDCFG);
556 tmp &= ~B43_PHY_BBANDCFG_RXANT;
557 tmp |= (autodiv ? B43_ANTENNA_AUTO0 : antenna)
558 << B43_PHY_BBANDCFG_RXANT_SHIFT;
559 b43_phy_write(dev, B43_PHY_BBANDCFG, tmp);
562 tmp = b43_phy_read(dev, B43_PHY_ANTDWELL);
563 if (antenna == B43_ANTENNA_AUTO0)
564 tmp &= ~B43_PHY_ANTDWELL_AUTODIV1;
566 tmp |= B43_PHY_ANTDWELL_AUTODIV1;
567 b43_phy_write(dev, B43_PHY_ANTDWELL, tmp);
570 tmp = b43_phy_read(dev, B43_PHY_ANTDWELL);
571 tmp = (tmp & 0xFF00) | 0x24;
572 b43_phy_write(dev, B43_PHY_ANTDWELL, tmp);
574 tmp = b43_phy_read(dev, B43_PHY_OFDM61);
576 b43_phy_write(dev, B43_PHY_OFDM61, tmp);
577 if (phy->analog == 3) {
578 b43_phy_write(dev, B43_PHY_CLIPPWRDOWNT,
580 b43_phy_write(dev, B43_PHY_ADIVRELATED,
583 b43_phy_write(dev, B43_PHY_CLIPPWRDOWNT,
587 B43_PHY_ADIVRELATED);
588 tmp = (tmp & 0xFF00) | 8;
589 b43_phy_write(dev, B43_PHY_ADIVRELATED,
594 hf |= B43_HF_ANTDIVHELP;
595 b43_hf_write(dev, hf);
598 static void b43_aphy_op_adjust_txpower(struct b43_wldev *dev)
602 static enum b43_txpwr_result b43_aphy_op_recalc_txpower(struct b43_wldev *dev,
605 return B43_TXPWR_RES_DONE;
608 static void b43_aphy_op_pwork_15sec(struct b43_wldev *dev)
612 static void b43_aphy_op_pwork_60sec(struct b43_wldev *dev)
616 const struct b43_phy_operations b43_phyops_a = {
617 .allocate = b43_aphy_op_allocate,
618 .free = b43_aphy_op_free,
619 .prepare_structs = b43_aphy_op_prepare_structs,
620 .init = b43_aphy_op_init,
621 .phy_read = b43_aphy_op_read,
622 .phy_write = b43_aphy_op_write,
623 .radio_read = b43_aphy_op_radio_read,
624 .radio_write = b43_aphy_op_radio_write,
625 .supports_hwpctl = b43_aphy_op_supports_hwpctl,
626 .software_rfkill = b43_aphy_op_software_rfkill,
627 .switch_analog = b43_phyop_switch_analog_generic,
628 .switch_channel = b43_aphy_op_switch_channel,
629 .get_default_chan = b43_aphy_op_get_default_chan,
630 .set_rx_antenna = b43_aphy_op_set_rx_antenna,
631 .recalc_txpower = b43_aphy_op_recalc_txpower,
632 .adjust_txpower = b43_aphy_op_adjust_txpower,
633 .pwork_15sec = b43_aphy_op_pwork_15sec,
634 .pwork_60sec = b43_aphy_op_pwork_60sec,