3 Broadcom B43 wireless driver
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
31 #include <linux/delay.h>
32 #include <linux/init.h>
33 #include <linux/moduleparam.h>
34 #include <linux/if_arp.h>
35 #include <linux/etherdevice.h>
36 #include <linux/version.h>
37 #include <linux/firmware.h>
38 #include <linux/wireless.h>
39 #include <linux/workqueue.h>
40 #include <linux/skbuff.h>
41 #include <linux/dma-mapping.h>
42 #include <asm/unaligned.h>
54 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
55 MODULE_AUTHOR("Martin Langer");
56 MODULE_AUTHOR("Stefano Brivio");
57 MODULE_AUTHOR("Michael Buesch");
58 MODULE_LICENSE("GPL");
61 static int modparam_bad_frames_preempt;
62 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
63 MODULE_PARM_DESC(bad_frames_preempt,
64 "enable(1) / disable(0) Bad Frames Preemption");
66 static char modparam_fwpostfix[16];
67 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
68 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
70 static int modparam_hwpctl;
71 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
72 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
74 static int modparam_nohwcrypt;
75 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
76 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
78 static const struct ssb_device_id b43_ssb_tbl[] = {
79 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
80 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
81 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
82 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
83 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
84 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
85 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
89 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
91 /* Channel and ratetables are shared for all devices.
92 * They can't be const, because ieee80211 puts some precalculated
93 * data in there. This data is the same for all devices, so we don't
94 * get concurrency issues */
95 #define RATETAB_ENT(_rateid, _flags) \
97 .rate = B43_RATE_TO_BASE100KBPS(_rateid), \
102 static struct ieee80211_rate __b43_ratetable[] = {
103 RATETAB_ENT(B43_CCK_RATE_1MB, IEEE80211_RATE_CCK),
104 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_CCK_2),
105 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_CCK_2),
106 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_CCK_2),
107 RATETAB_ENT(B43_OFDM_RATE_6MB, IEEE80211_RATE_OFDM),
108 RATETAB_ENT(B43_OFDM_RATE_9MB, IEEE80211_RATE_OFDM),
109 RATETAB_ENT(B43_OFDM_RATE_12MB, IEEE80211_RATE_OFDM),
110 RATETAB_ENT(B43_OFDM_RATE_18MB, IEEE80211_RATE_OFDM),
111 RATETAB_ENT(B43_OFDM_RATE_24MB, IEEE80211_RATE_OFDM),
112 RATETAB_ENT(B43_OFDM_RATE_36MB, IEEE80211_RATE_OFDM),
113 RATETAB_ENT(B43_OFDM_RATE_48MB, IEEE80211_RATE_OFDM),
114 RATETAB_ENT(B43_OFDM_RATE_54MB, IEEE80211_RATE_OFDM),
117 #define b43_a_ratetable (__b43_ratetable + 4)
118 #define b43_a_ratetable_size 8
119 #define b43_b_ratetable (__b43_ratetable + 0)
120 #define b43_b_ratetable_size 4
121 #define b43_g_ratetable (__b43_ratetable + 0)
122 #define b43_g_ratetable_size 12
124 #define CHANTAB_ENT(_chanid, _freq) \
129 .flag = IEEE80211_CHAN_W_SCAN | \
130 IEEE80211_CHAN_W_ACTIVE_SCAN | \
131 IEEE80211_CHAN_W_IBSS, \
132 .power_level = 0xFF, \
133 .antenna_max = 0xFF, \
135 static struct ieee80211_channel b43_bg_chantable[] = {
136 CHANTAB_ENT(1, 2412),
137 CHANTAB_ENT(2, 2417),
138 CHANTAB_ENT(3, 2422),
139 CHANTAB_ENT(4, 2427),
140 CHANTAB_ENT(5, 2432),
141 CHANTAB_ENT(6, 2437),
142 CHANTAB_ENT(7, 2442),
143 CHANTAB_ENT(8, 2447),
144 CHANTAB_ENT(9, 2452),
145 CHANTAB_ENT(10, 2457),
146 CHANTAB_ENT(11, 2462),
147 CHANTAB_ENT(12, 2467),
148 CHANTAB_ENT(13, 2472),
149 CHANTAB_ENT(14, 2484),
152 #define b43_bg_chantable_size ARRAY_SIZE(b43_bg_chantable)
153 static struct ieee80211_channel b43_a_chantable[] = {
154 CHANTAB_ENT(36, 5180),
155 CHANTAB_ENT(40, 5200),
156 CHANTAB_ENT(44, 5220),
157 CHANTAB_ENT(48, 5240),
158 CHANTAB_ENT(52, 5260),
159 CHANTAB_ENT(56, 5280),
160 CHANTAB_ENT(60, 5300),
161 CHANTAB_ENT(64, 5320),
162 CHANTAB_ENT(149, 5745),
163 CHANTAB_ENT(153, 5765),
164 CHANTAB_ENT(157, 5785),
165 CHANTAB_ENT(161, 5805),
166 CHANTAB_ENT(165, 5825),
169 #define b43_a_chantable_size ARRAY_SIZE(b43_a_chantable)
171 static void b43_wireless_core_exit(struct b43_wldev *dev);
172 static int b43_wireless_core_init(struct b43_wldev *dev);
173 static void b43_wireless_core_stop(struct b43_wldev *dev);
174 static int b43_wireless_core_start(struct b43_wldev *dev);
176 static int b43_ratelimit(struct b43_wl *wl)
178 if (!wl || !wl->current_dev)
180 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
182 /* We are up and running.
183 * Ratelimit the messages to avoid DoS over the net. */
184 return net_ratelimit();
187 void b43info(struct b43_wl *wl, const char *fmt, ...)
191 if (!b43_ratelimit(wl))
194 printk(KERN_INFO "b43-%s: ",
195 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
200 void b43err(struct b43_wl *wl, const char *fmt, ...)
204 if (!b43_ratelimit(wl))
207 printk(KERN_ERR "b43-%s ERROR: ",
208 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
213 void b43warn(struct b43_wl *wl, const char *fmt, ...)
217 if (!b43_ratelimit(wl))
220 printk(KERN_WARNING "b43-%s warning: ",
221 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
227 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
232 printk(KERN_DEBUG "b43-%s debug: ",
233 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
239 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
243 B43_WARN_ON(offset % 4 != 0);
245 macctl = b43_read32(dev, B43_MMIO_MACCTL);
246 if (macctl & B43_MACCTL_BE)
249 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
251 b43_write32(dev, B43_MMIO_RAM_DATA, val);
255 void b43_shm_control_word(struct b43_wldev *dev, u16 routing, u16 offset)
259 /* "offset" is the WORD offset. */
264 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
267 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
271 if (routing == B43_SHM_SHARED) {
272 B43_WARN_ON(offset & 0x0001);
273 if (offset & 0x0003) {
274 /* Unaligned access */
275 b43_shm_control_word(dev, routing, offset >> 2);
276 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
278 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
279 ret |= b43_read16(dev, B43_MMIO_SHM_DATA);
285 b43_shm_control_word(dev, routing, offset);
286 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
291 u16 b43_shm_read16(struct b43_wldev * dev, u16 routing, u16 offset)
295 if (routing == B43_SHM_SHARED) {
296 B43_WARN_ON(offset & 0x0001);
297 if (offset & 0x0003) {
298 /* Unaligned access */
299 b43_shm_control_word(dev, routing, offset >> 2);
300 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
306 b43_shm_control_word(dev, routing, offset);
307 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
312 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
314 if (routing == B43_SHM_SHARED) {
315 B43_WARN_ON(offset & 0x0001);
316 if (offset & 0x0003) {
317 /* Unaligned access */
318 b43_shm_control_word(dev, routing, offset >> 2);
320 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
321 (value >> 16) & 0xffff);
323 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
325 b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
330 b43_shm_control_word(dev, routing, offset);
332 b43_write32(dev, B43_MMIO_SHM_DATA, value);
335 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
337 if (routing == B43_SHM_SHARED) {
338 B43_WARN_ON(offset & 0x0001);
339 if (offset & 0x0003) {
340 /* Unaligned access */
341 b43_shm_control_word(dev, routing, offset >> 2);
343 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
348 b43_shm_control_word(dev, routing, offset);
350 b43_write16(dev, B43_MMIO_SHM_DATA, value);
354 u32 b43_hf_read(struct b43_wldev * dev)
358 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
360 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
365 /* Write HostFlags */
366 void b43_hf_write(struct b43_wldev *dev, u32 value)
368 b43_shm_write16(dev, B43_SHM_SHARED,
369 B43_SHM_SH_HOSTFLO, (value & 0x0000FFFF));
370 b43_shm_write16(dev, B43_SHM_SHARED,
371 B43_SHM_SH_HOSTFHI, ((value & 0xFFFF0000) >> 16));
374 void b43_tsf_read(struct b43_wldev *dev, u64 * tsf)
376 /* We need to be careful. As we read the TSF from multiple
377 * registers, we should take care of register overflows.
378 * In theory, the whole tsf read process should be atomic.
379 * We try to be atomic here, by restaring the read process,
380 * if any of the high registers changed (overflew).
382 if (dev->dev->id.revision >= 3) {
383 u32 low, high, high2;
386 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
387 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
388 high2 = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
389 } while (unlikely(high != high2));
397 u16 test1, test2, test3;
400 v3 = b43_read16(dev, B43_MMIO_TSF_3);
401 v2 = b43_read16(dev, B43_MMIO_TSF_2);
402 v1 = b43_read16(dev, B43_MMIO_TSF_1);
403 v0 = b43_read16(dev, B43_MMIO_TSF_0);
405 test3 = b43_read16(dev, B43_MMIO_TSF_3);
406 test2 = b43_read16(dev, B43_MMIO_TSF_2);
407 test1 = b43_read16(dev, B43_MMIO_TSF_1);
408 } while (v3 != test3 || v2 != test2 || v1 != test1);
422 static void b43_time_lock(struct b43_wldev *dev)
426 macctl = b43_read32(dev, B43_MMIO_MACCTL);
427 macctl |= B43_MACCTL_TBTTHOLD;
428 b43_write32(dev, B43_MMIO_MACCTL, macctl);
429 /* Commit the write */
430 b43_read32(dev, B43_MMIO_MACCTL);
433 static void b43_time_unlock(struct b43_wldev *dev)
437 macctl = b43_read32(dev, B43_MMIO_MACCTL);
438 macctl &= ~B43_MACCTL_TBTTHOLD;
439 b43_write32(dev, B43_MMIO_MACCTL, macctl);
440 /* Commit the write */
441 b43_read32(dev, B43_MMIO_MACCTL);
444 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
446 /* Be careful with the in-progress timer.
447 * First zero out the low register, so we have a full
448 * register-overflow duration to complete the operation.
450 if (dev->dev->id.revision >= 3) {
451 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
452 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
454 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, 0);
456 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, hi);
458 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, lo);
460 u16 v0 = (tsf & 0x000000000000FFFFULL);
461 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
462 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
463 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
465 b43_write16(dev, B43_MMIO_TSF_0, 0);
467 b43_write16(dev, B43_MMIO_TSF_3, v3);
469 b43_write16(dev, B43_MMIO_TSF_2, v2);
471 b43_write16(dev, B43_MMIO_TSF_1, v1);
473 b43_write16(dev, B43_MMIO_TSF_0, v0);
477 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
480 b43_tsf_write_locked(dev, tsf);
481 b43_time_unlock(dev);
485 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac)
487 static const u8 zero_addr[ETH_ALEN] = { 0 };
494 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
498 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
501 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
504 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
507 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
511 u8 mac_bssid[ETH_ALEN * 2];
515 bssid = dev->wl->bssid;
516 mac = dev->wl->mac_addr;
518 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
520 memcpy(mac_bssid, mac, ETH_ALEN);
521 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
523 /* Write our MAC address and BSSID to template ram */
524 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
525 tmp = (u32) (mac_bssid[i + 0]);
526 tmp |= (u32) (mac_bssid[i + 1]) << 8;
527 tmp |= (u32) (mac_bssid[i + 2]) << 16;
528 tmp |= (u32) (mac_bssid[i + 3]) << 24;
529 b43_ram_write(dev, 0x20 + i, tmp);
533 static void b43_upload_card_macaddress(struct b43_wldev *dev)
535 b43_write_mac_bssid_templates(dev);
536 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
539 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
541 /* slot_time is in usec. */
542 if (dev->phy.type != B43_PHYTYPE_G)
544 b43_write16(dev, 0x684, 510 + slot_time);
545 b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
548 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
550 b43_set_slot_time(dev, 9);
554 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
556 b43_set_slot_time(dev, 20);
560 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
561 * Returns the _previously_ enabled IRQ mask.
563 static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask)
567 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
568 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask);
573 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
574 * Returns the _previously_ enabled IRQ mask.
576 static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask)
580 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
581 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
586 /* Synchronize IRQ top- and bottom-half.
587 * IRQs must be masked before calling this.
588 * This must not be called with the irq_lock held.
590 static void b43_synchronize_irq(struct b43_wldev *dev)
592 synchronize_irq(dev->dev->irq);
593 tasklet_kill(&dev->isr_tasklet);
596 /* DummyTransmission function, as documented on
597 * http://bcm-specs.sipsolutions.net/DummyTransmission
599 void b43_dummy_transmission(struct b43_wldev *dev)
601 struct b43_phy *phy = &dev->phy;
602 unsigned int i, max_loop;
615 buffer[0] = 0x000201CC;
620 buffer[0] = 0x000B846E;
627 for (i = 0; i < 5; i++)
628 b43_ram_write(dev, i * 4, buffer[i]);
631 b43_read32(dev, B43_MMIO_MACCTL);
633 b43_write16(dev, 0x0568, 0x0000);
634 b43_write16(dev, 0x07C0, 0x0000);
635 value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0);
636 b43_write16(dev, 0x050C, value);
637 b43_write16(dev, 0x0508, 0x0000);
638 b43_write16(dev, 0x050A, 0x0000);
639 b43_write16(dev, 0x054C, 0x0000);
640 b43_write16(dev, 0x056A, 0x0014);
641 b43_write16(dev, 0x0568, 0x0826);
642 b43_write16(dev, 0x0500, 0x0000);
643 b43_write16(dev, 0x0502, 0x0030);
645 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
646 b43_radio_write16(dev, 0x0051, 0x0017);
647 for (i = 0x00; i < max_loop; i++) {
648 value = b43_read16(dev, 0x050E);
653 for (i = 0x00; i < 0x0A; i++) {
654 value = b43_read16(dev, 0x050E);
659 for (i = 0x00; i < 0x0A; i++) {
660 value = b43_read16(dev, 0x0690);
661 if (!(value & 0x0100))
665 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
666 b43_radio_write16(dev, 0x0051, 0x0037);
669 static void key_write(struct b43_wldev *dev,
670 u8 index, u8 algorithm, const u8 * key)
677 /* Key index/algo block */
678 kidx = b43_kidx_to_fw(dev, index);
679 value = ((kidx << 4) | algorithm);
680 b43_shm_write16(dev, B43_SHM_SHARED,
681 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
683 /* Write the key to the Key Table Pointer offset */
684 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
685 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
687 value |= (u16) (key[i + 1]) << 8;
688 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
692 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr)
694 u32 addrtmp[2] = { 0, 0, };
695 u8 per_sta_keys_start = 8;
697 if (b43_new_kidx_api(dev))
698 per_sta_keys_start = 4;
700 B43_WARN_ON(index < per_sta_keys_start);
701 /* We have two default TX keys and possibly two default RX keys.
702 * Physical mac 0 is mapped to physical key 4 or 8, depending
703 * on the firmware version.
704 * So we must adjust the index here.
706 index -= per_sta_keys_start;
709 addrtmp[0] = addr[0];
710 addrtmp[0] |= ((u32) (addr[1]) << 8);
711 addrtmp[0] |= ((u32) (addr[2]) << 16);
712 addrtmp[0] |= ((u32) (addr[3]) << 24);
713 addrtmp[1] = addr[4];
714 addrtmp[1] |= ((u32) (addr[5]) << 8);
717 if (dev->dev->id.revision >= 5) {
718 /* Receive match transmitter address mechanism */
719 b43_shm_write32(dev, B43_SHM_RCMTA,
720 (index * 2) + 0, addrtmp[0]);
721 b43_shm_write16(dev, B43_SHM_RCMTA,
722 (index * 2) + 1, addrtmp[1]);
724 /* RXE (Receive Engine) and
725 * PSM (Programmable State Machine) mechanism
728 /* TODO write to RCM 16, 19, 22 and 25 */
730 b43_shm_write32(dev, B43_SHM_SHARED,
731 B43_SHM_SH_PSM + (index * 6) + 0,
733 b43_shm_write16(dev, B43_SHM_SHARED,
734 B43_SHM_SH_PSM + (index * 6) + 4,
740 static void do_key_write(struct b43_wldev *dev,
741 u8 index, u8 algorithm,
742 const u8 * key, size_t key_len, const u8 * mac_addr)
744 u8 buf[B43_SEC_KEYSIZE] = { 0, };
745 u8 per_sta_keys_start = 8;
747 if (b43_new_kidx_api(dev))
748 per_sta_keys_start = 4;
750 B43_WARN_ON(index >= dev->max_nr_keys);
751 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
753 if (index >= per_sta_keys_start)
754 keymac_write(dev, index, NULL); /* First zero out mac. */
756 memcpy(buf, key, key_len);
757 key_write(dev, index, algorithm, buf);
758 if (index >= per_sta_keys_start)
759 keymac_write(dev, index, mac_addr);
761 dev->key[index].algorithm = algorithm;
764 static int b43_key_write(struct b43_wldev *dev,
765 int index, u8 algorithm,
766 const u8 * key, size_t key_len,
768 struct ieee80211_key_conf *keyconf)
773 if (key_len > B43_SEC_KEYSIZE)
775 for (i = 0; i < dev->max_nr_keys; i++) {
776 /* Check that we don't already have this key. */
777 B43_WARN_ON(dev->key[i].keyconf == keyconf);
780 /* Either pairwise key or address is 00:00:00:00:00:00
781 * for transmit-only keys. Search the index. */
782 if (b43_new_kidx_api(dev))
786 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
787 if (!dev->key[i].keyconf) {
794 b43err(dev->wl, "Out of hardware key memory\n");
798 B43_WARN_ON(index > 3);
800 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
801 if ((index <= 3) && !b43_new_kidx_api(dev)) {
803 B43_WARN_ON(mac_addr);
804 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
806 keyconf->hw_key_idx = index;
807 dev->key[index].keyconf = keyconf;
812 static int b43_key_clear(struct b43_wldev *dev, int index)
814 if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys)))
816 do_key_write(dev, index, B43_SEC_ALGO_NONE,
817 NULL, B43_SEC_KEYSIZE, NULL);
818 if ((index <= 3) && !b43_new_kidx_api(dev)) {
819 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
820 NULL, B43_SEC_KEYSIZE, NULL);
822 dev->key[index].keyconf = NULL;
827 static void b43_clear_keys(struct b43_wldev *dev)
831 for (i = 0; i < dev->max_nr_keys; i++)
832 b43_key_clear(dev, i);
835 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
843 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
844 (ps_flags & B43_PS_DISABLED));
845 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
847 if (ps_flags & B43_PS_ENABLED) {
849 } else if (ps_flags & B43_PS_DISABLED) {
852 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
853 // and thus is not an AP and we are associated, set bit 25
855 if (ps_flags & B43_PS_AWAKE) {
857 } else if (ps_flags & B43_PS_ASLEEP) {
860 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
861 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
862 // successful, set bit26
865 /* FIXME: For now we force awake-on and hwps-off */
869 macctl = b43_read32(dev, B43_MMIO_MACCTL);
871 macctl |= B43_MACCTL_HWPS;
873 macctl &= ~B43_MACCTL_HWPS;
875 macctl |= B43_MACCTL_AWAKE;
877 macctl &= ~B43_MACCTL_AWAKE;
878 b43_write32(dev, B43_MMIO_MACCTL, macctl);
880 b43_read32(dev, B43_MMIO_MACCTL);
881 if (awake && dev->dev->id.revision >= 5) {
882 /* Wait for the microcode to wake up. */
883 for (i = 0; i < 100; i++) {
884 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
885 B43_SHM_SH_UCODESTAT);
886 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
893 /* Turn the Analog ON/OFF */
894 static void b43_switch_analog(struct b43_wldev *dev, int on)
896 b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
899 void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
904 flags |= B43_TMSLOW_PHYCLKEN;
905 flags |= B43_TMSLOW_PHYRESET;
906 ssb_device_enable(dev->dev, flags);
907 msleep(2); /* Wait for the PLL to turn on. */
909 /* Now take the PHY out of Reset again */
910 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
911 tmslow |= SSB_TMSLOW_FGC;
912 tmslow &= ~B43_TMSLOW_PHYRESET;
913 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
914 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
916 tmslow &= ~SSB_TMSLOW_FGC;
917 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
918 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
922 b43_switch_analog(dev, 1);
924 macctl = b43_read32(dev, B43_MMIO_MACCTL);
925 macctl &= ~B43_MACCTL_GMODE;
926 if (flags & B43_TMSLOW_GMODE)
927 macctl |= B43_MACCTL_GMODE;
928 macctl |= B43_MACCTL_IHR_ENABLED;
929 b43_write32(dev, B43_MMIO_MACCTL, macctl);
932 static void handle_irq_transmit_status(struct b43_wldev *dev)
936 struct b43_txstatus stat;
939 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
940 if (!(v0 & 0x00000001))
942 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
944 stat.cookie = (v0 >> 16);
945 stat.seq = (v1 & 0x0000FFFF);
946 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
947 tmp = (v0 & 0x0000FFFF);
948 stat.frame_count = ((tmp & 0xF000) >> 12);
949 stat.rts_count = ((tmp & 0x0F00) >> 8);
950 stat.supp_reason = ((tmp & 0x001C) >> 2);
951 stat.pm_indicated = !!(tmp & 0x0080);
952 stat.intermediate = !!(tmp & 0x0040);
953 stat.for_ampdu = !!(tmp & 0x0020);
954 stat.acked = !!(tmp & 0x0002);
956 b43_handle_txstatus(dev, &stat);
960 static void drain_txstatus_queue(struct b43_wldev *dev)
964 if (dev->dev->id.revision < 5)
966 /* Read all entries from the microcode TXstatus FIFO
967 * and throw them away.
970 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
971 if (!(dummy & 0x00000001))
973 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
977 static u32 b43_jssi_read(struct b43_wldev *dev)
981 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
983 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
988 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
990 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
991 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
994 static void b43_generate_noise_sample(struct b43_wldev *dev)
996 b43_jssi_write(dev, 0x7F7F7F7F);
997 b43_write32(dev, B43_MMIO_MACCMD,
998 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
999 B43_WARN_ON(dev->noisecalc.channel_at_start != dev->phy.channel);
1002 static void b43_calculate_link_quality(struct b43_wldev *dev)
1004 /* Top half of Link Quality calculation. */
1006 if (dev->noisecalc.calculation_running)
1008 dev->noisecalc.channel_at_start = dev->phy.channel;
1009 dev->noisecalc.calculation_running = 1;
1010 dev->noisecalc.nr_samples = 0;
1012 b43_generate_noise_sample(dev);
1015 static void handle_irq_noise(struct b43_wldev *dev)
1017 struct b43_phy *phy = &dev->phy;
1023 /* Bottom half of Link Quality calculation. */
1025 B43_WARN_ON(!dev->noisecalc.calculation_running);
1026 if (dev->noisecalc.channel_at_start != phy->channel)
1027 goto drop_calculation;
1028 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1029 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1030 noise[2] == 0x7F || noise[3] == 0x7F)
1033 /* Get the noise samples. */
1034 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1035 i = dev->noisecalc.nr_samples;
1036 noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1037 noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1038 noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1039 noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1040 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1041 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1042 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1043 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1044 dev->noisecalc.nr_samples++;
1045 if (dev->noisecalc.nr_samples == 8) {
1046 /* Calculate the Link Quality by the noise samples. */
1048 for (i = 0; i < 8; i++) {
1049 for (j = 0; j < 4; j++)
1050 average += dev->noisecalc.samples[i][j];
1056 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1057 tmp = (tmp / 128) & 0x1F;
1067 dev->stats.link_noise = average;
1069 dev->noisecalc.calculation_running = 0;
1073 b43_generate_noise_sample(dev);
1076 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1078 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
1081 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1082 b43_power_saving_ctl_bits(dev, 0);
1084 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
1088 static void handle_irq_atim_end(struct b43_wldev *dev)
1090 if (dev->dfq_valid) {
1091 b43_write32(dev, B43_MMIO_MACCMD,
1092 b43_read32(dev, B43_MMIO_MACCMD)
1093 | B43_MACCMD_DFQ_VALID);
1098 static void handle_irq_pmq(struct b43_wldev *dev)
1105 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1106 if (!(tmp & 0x00000008))
1109 /* 16bit write is odd, but correct. */
1110 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1113 static void b43_write_template_common(struct b43_wldev *dev,
1114 const u8 * data, u16 size,
1116 u16 shm_size_offset, u8 rate)
1119 struct b43_plcp_hdr4 plcp;
1122 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1123 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1124 ram_offset += sizeof(u32);
1125 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1126 * So leave the first two bytes of the next write blank.
1128 tmp = (u32) (data[0]) << 16;
1129 tmp |= (u32) (data[1]) << 24;
1130 b43_ram_write(dev, ram_offset, tmp);
1131 ram_offset += sizeof(u32);
1132 for (i = 2; i < size; i += sizeof(u32)) {
1133 tmp = (u32) (data[i + 0]);
1135 tmp |= (u32) (data[i + 1]) << 8;
1137 tmp |= (u32) (data[i + 2]) << 16;
1139 tmp |= (u32) (data[i + 3]) << 24;
1140 b43_ram_write(dev, ram_offset + i - 2, tmp);
1142 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1143 size + sizeof(struct b43_plcp_hdr6));
1146 static void b43_write_beacon_template(struct b43_wldev *dev,
1148 u16 shm_size_offset, u8 rate)
1153 B43_WARN_ON(!dev->cached_beacon);
1154 len = min((size_t) dev->cached_beacon->len,
1155 0x200 - sizeof(struct b43_plcp_hdr6));
1156 data = (const u8 *)(dev->cached_beacon->data);
1157 b43_write_template_common(dev, data,
1158 len, ram_offset, shm_size_offset, rate);
1161 static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
1162 u16 shm_offset, u16 size, u8 rate)
1164 struct b43_plcp_hdr4 plcp;
1169 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1170 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1171 dev->wl->if_id, size,
1172 B43_RATE_TO_BASE100KBPS(rate));
1173 /* Write PLCP in two parts and timing for packet transfer */
1174 tmp = le32_to_cpu(plcp.data);
1175 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF);
1176 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16);
1177 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur));
1180 /* Instead of using custom probe response template, this function
1181 * just patches custom beacon template by:
1182 * 1) Changing packet type
1183 * 2) Patching duration field
1186 static u8 *b43_generate_probe_resp(struct b43_wldev *dev,
1187 u16 * dest_size, u8 rate)
1191 u16 src_size, elem_size, src_pos, dest_pos;
1193 struct ieee80211_hdr *hdr;
1195 B43_WARN_ON(!dev->cached_beacon);
1196 src_size = dev->cached_beacon->len;
1197 src_data = (const u8 *)dev->cached_beacon->data;
1199 if (unlikely(src_size < 0x24)) {
1200 b43dbg(dev->wl, "b43_generate_probe_resp: " "invalid beacon\n");
1204 dest_data = kmalloc(src_size, GFP_ATOMIC);
1205 if (unlikely(!dest_data))
1208 /* 0x24 is offset of first variable-len Information-Element
1211 memcpy(dest_data, src_data, 0x24);
1212 src_pos = dest_pos = 0x24;
1213 for (; src_pos < src_size - 2; src_pos += elem_size) {
1214 elem_size = src_data[src_pos + 1] + 2;
1215 if (src_data[src_pos] != 0x05) { /* TIM */
1216 memcpy(dest_data + dest_pos, src_data + src_pos,
1218 dest_pos += elem_size;
1221 *dest_size = dest_pos;
1222 hdr = (struct ieee80211_hdr *)dest_data;
1224 /* Set the frame control. */
1225 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1226 IEEE80211_STYPE_PROBE_RESP);
1227 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1228 dev->wl->if_id, *dest_size,
1229 B43_RATE_TO_BASE100KBPS(rate));
1230 hdr->duration_id = dur;
1235 static void b43_write_probe_resp_template(struct b43_wldev *dev,
1237 u16 shm_size_offset, u8 rate)
1239 u8 *probe_resp_data;
1242 B43_WARN_ON(!dev->cached_beacon);
1243 size = dev->cached_beacon->len;
1244 probe_resp_data = b43_generate_probe_resp(dev, &size, rate);
1245 if (unlikely(!probe_resp_data))
1248 /* Looks like PLCP headers plus packet timings are stored for
1249 * all possible basic rates
1251 b43_write_probe_resp_plcp(dev, 0x31A, size, B43_CCK_RATE_1MB);
1252 b43_write_probe_resp_plcp(dev, 0x32C, size, B43_CCK_RATE_2MB);
1253 b43_write_probe_resp_plcp(dev, 0x33E, size, B43_CCK_RATE_5MB);
1254 b43_write_probe_resp_plcp(dev, 0x350, size, B43_CCK_RATE_11MB);
1256 size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6));
1257 b43_write_template_common(dev, probe_resp_data,
1258 size, ram_offset, shm_size_offset, rate);
1259 kfree(probe_resp_data);
1262 static int b43_refresh_cached_beacon(struct b43_wldev *dev,
1263 struct sk_buff *beacon)
1265 if (dev->cached_beacon)
1266 kfree_skb(dev->cached_beacon);
1267 dev->cached_beacon = beacon;
1272 static void b43_update_templates(struct b43_wldev *dev)
1276 B43_WARN_ON(!dev->cached_beacon);
1278 b43_write_beacon_template(dev, 0x68, 0x18, B43_CCK_RATE_1MB);
1279 b43_write_beacon_template(dev, 0x468, 0x1A, B43_CCK_RATE_1MB);
1280 b43_write_probe_resp_template(dev, 0x268, 0x4A, B43_CCK_RATE_11MB);
1282 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1283 cmd |= B43_MACCMD_BEACON0_VALID | B43_MACCMD_BEACON1_VALID;
1284 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1287 static void b43_refresh_templates(struct b43_wldev *dev, struct sk_buff *beacon)
1291 err = b43_refresh_cached_beacon(dev, beacon);
1294 b43_update_templates(dev);
1297 static void b43_set_ssid(struct b43_wldev *dev, const u8 * ssid, u8 ssid_len)
1302 len = min((u16) ssid_len, (u16) 0x100);
1303 for (i = 0; i < len; i += sizeof(u32)) {
1304 tmp = (u32) (ssid[i + 0]);
1306 tmp |= (u32) (ssid[i + 1]) << 8;
1308 tmp |= (u32) (ssid[i + 2]) << 16;
1310 tmp |= (u32) (ssid[i + 3]) << 24;
1311 b43_shm_write32(dev, B43_SHM_SHARED, 0x380 + i, tmp);
1313 b43_shm_write16(dev, B43_SHM_SHARED, 0x48, len);
1316 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1319 if (dev->dev->id.revision >= 3) {
1320 b43_write32(dev, 0x188, (beacon_int << 16));
1322 b43_write16(dev, 0x606, (beacon_int >> 6));
1323 b43_write16(dev, 0x610, beacon_int);
1325 b43_time_unlock(dev);
1328 static void handle_irq_beacon(struct b43_wldev *dev)
1332 if (!b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
1335 dev->irq_savedstate &= ~B43_IRQ_BEACON;
1336 status = b43_read32(dev, B43_MMIO_MACCMD);
1338 if (!dev->cached_beacon || ((status & 0x1) && (status & 0x2))) {
1339 /* ACK beacon IRQ. */
1340 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1341 dev->irq_savedstate |= B43_IRQ_BEACON;
1342 if (dev->cached_beacon)
1343 kfree_skb(dev->cached_beacon);
1344 dev->cached_beacon = NULL;
1347 if (!(status & 0x1)) {
1348 b43_write_beacon_template(dev, 0x68, 0x18, B43_CCK_RATE_1MB);
1350 b43_write32(dev, B43_MMIO_MACCMD, status);
1352 if (!(status & 0x2)) {
1353 b43_write_beacon_template(dev, 0x468, 0x1A, B43_CCK_RATE_1MB);
1355 b43_write32(dev, B43_MMIO_MACCMD, status);
1359 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1364 /* Interrupt handler bottom-half */
1365 static void b43_interrupt_tasklet(struct b43_wldev *dev)
1368 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1369 u32 merged_dma_reason = 0;
1371 unsigned long flags;
1373 spin_lock_irqsave(&dev->wl->irq_lock, flags);
1375 B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
1377 reason = dev->irq_reason;
1378 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1379 dma_reason[i] = dev->dma_reason[i];
1380 merged_dma_reason |= dma_reason[i];
1383 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1384 b43err(dev->wl, "MAC transmission error\n");
1386 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1387 b43err(dev->wl, "PHY transmission error\n");
1389 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1390 atomic_set(&dev->phy.txerr_cnt,
1391 B43_PHY_TX_BADNESS_LIMIT);
1392 b43err(dev->wl, "Too many PHY TX errors, "
1393 "restarting the controller\n");
1394 b43_controller_restart(dev, "PHY TX errors");
1398 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1399 B43_DMAIRQ_NONFATALMASK))) {
1400 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1401 b43err(dev->wl, "Fatal DMA error: "
1402 "0x%08X, 0x%08X, 0x%08X, "
1403 "0x%08X, 0x%08X, 0x%08X\n",
1404 dma_reason[0], dma_reason[1],
1405 dma_reason[2], dma_reason[3],
1406 dma_reason[4], dma_reason[5]);
1407 b43_controller_restart(dev, "DMA error");
1409 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1412 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1413 b43err(dev->wl, "DMA error: "
1414 "0x%08X, 0x%08X, 0x%08X, "
1415 "0x%08X, 0x%08X, 0x%08X\n",
1416 dma_reason[0], dma_reason[1],
1417 dma_reason[2], dma_reason[3],
1418 dma_reason[4], dma_reason[5]);
1422 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1423 handle_irq_ucode_debug(dev);
1424 if (reason & B43_IRQ_TBTT_INDI)
1425 handle_irq_tbtt_indication(dev);
1426 if (reason & B43_IRQ_ATIM_END)
1427 handle_irq_atim_end(dev);
1428 if (reason & B43_IRQ_BEACON)
1429 handle_irq_beacon(dev);
1430 if (reason & B43_IRQ_PMQ)
1431 handle_irq_pmq(dev);
1432 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1434 if (reason & B43_IRQ_NOISESAMPLE_OK)
1435 handle_irq_noise(dev);
1437 /* Check the DMA reason registers for received data. */
1438 if (dma_reason[0] & B43_DMAIRQ_RX_DONE)
1439 b43_dma_rx(dev->dma.rx_ring0);
1440 if (dma_reason[3] & B43_DMAIRQ_RX_DONE)
1441 b43_dma_rx(dev->dma.rx_ring3);
1442 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1443 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1444 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1445 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1447 if (reason & B43_IRQ_TX_OK)
1448 handle_irq_transmit_status(dev);
1450 b43_interrupt_enable(dev, dev->irq_savedstate);
1452 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1455 static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
1457 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1459 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1460 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1461 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1462 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1463 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1464 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1467 /* Interrupt handler top-half */
1468 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1470 irqreturn_t ret = IRQ_NONE;
1471 struct b43_wldev *dev = dev_id;
1477 spin_lock(&dev->wl->irq_lock);
1479 if (b43_status(dev) < B43_STAT_STARTED)
1481 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1482 if (reason == 0xffffffff) /* shared IRQ */
1485 reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1489 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1491 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1493 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1495 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1497 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1499 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1502 b43_interrupt_ack(dev, reason);
1503 /* disable all IRQs. They are enabled again in the bottom half. */
1504 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
1505 /* save the reason code and call our bottom half. */
1506 dev->irq_reason = reason;
1507 tasklet_schedule(&dev->isr_tasklet);
1510 spin_unlock(&dev->wl->irq_lock);
1515 static void b43_release_firmware(struct b43_wldev *dev)
1517 release_firmware(dev->fw.ucode);
1518 dev->fw.ucode = NULL;
1519 release_firmware(dev->fw.pcm);
1521 release_firmware(dev->fw.initvals);
1522 dev->fw.initvals = NULL;
1523 release_firmware(dev->fw.initvals_band);
1524 dev->fw.initvals_band = NULL;
1527 static void b43_print_fw_helptext(struct b43_wl *wl)
1529 b43err(wl, "You must go to "
1530 "http://linuxwireless.org/en/users/Drivers/b43#devicefirmware "
1531 "and download the correct firmware (version 4).\n");
1534 static int do_request_fw(struct b43_wldev *dev,
1536 const struct firmware **fw)
1538 char path[sizeof(modparam_fwpostfix) + 32];
1539 struct b43_fw_header *hdr;
1546 snprintf(path, ARRAY_SIZE(path),
1548 modparam_fwpostfix, name);
1549 err = request_firmware(fw, path, dev->dev->dev);
1551 b43err(dev->wl, "Firmware file \"%s\" not found "
1552 "or load failed.\n", path);
1555 if ((*fw)->size < sizeof(struct b43_fw_header))
1557 hdr = (struct b43_fw_header *)((*fw)->data);
1558 switch (hdr->type) {
1559 case B43_FW_TYPE_UCODE:
1560 case B43_FW_TYPE_PCM:
1561 size = be32_to_cpu(hdr->size);
1562 if (size != (*fw)->size - sizeof(struct b43_fw_header))
1565 case B43_FW_TYPE_IV:
1576 b43err(dev->wl, "Firmware file \"%s\" format error.\n", path);
1580 static int b43_request_firmware(struct b43_wldev *dev)
1582 struct b43_firmware *fw = &dev->fw;
1583 const u8 rev = dev->dev->id.revision;
1584 const char *filename;
1588 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
1590 if ((rev >= 5) && (rev <= 10))
1591 filename = "ucode5";
1592 else if ((rev >= 11) && (rev <= 12))
1593 filename = "ucode11";
1595 filename = "ucode13";
1598 err = do_request_fw(dev, filename, &fw->ucode);
1603 if ((rev >= 5) && (rev <= 10))
1609 err = do_request_fw(dev, filename, &fw->pcm);
1613 if (!fw->initvals) {
1614 switch (dev->phy.type) {
1616 if ((rev >= 5) && (rev <= 10)) {
1617 if (tmshigh & B43_TMSHIGH_GPHY)
1618 filename = "a0g1initvals5";
1620 filename = "a0g0initvals5";
1622 goto err_no_initvals;
1625 if ((rev >= 5) && (rev <= 10))
1626 filename = "b0g0initvals5";
1628 filename = "lp0initvals13";
1630 goto err_no_initvals;
1633 goto err_no_initvals;
1635 err = do_request_fw(dev, filename, &fw->initvals);
1639 if (!fw->initvals_band) {
1640 switch (dev->phy.type) {
1642 if ((rev >= 5) && (rev <= 10)) {
1643 if (tmshigh & B43_TMSHIGH_GPHY)
1644 filename = "a0g1bsinitvals5";
1646 filename = "a0g0bsinitvals5";
1647 } else if (rev >= 11)
1650 goto err_no_initvals;
1653 if ((rev >= 5) && (rev <= 10))
1654 filename = "b0g0bsinitvals5";
1658 goto err_no_initvals;
1661 goto err_no_initvals;
1663 err = do_request_fw(dev, filename, &fw->initvals_band);
1671 b43_print_fw_helptext(dev->wl);
1676 b43err(dev->wl, "No microcode available for core rev %u\n", rev);
1681 b43err(dev->wl, "No PCM available for core rev %u\n", rev);
1686 b43err(dev->wl, "No Initial Values firmware file for PHY %u, "
1687 "core rev %u\n", dev->phy.type, rev);
1691 b43_release_firmware(dev);
1695 static int b43_upload_microcode(struct b43_wldev *dev)
1697 const size_t hdr_len = sizeof(struct b43_fw_header);
1699 unsigned int i, len;
1700 u16 fwrev, fwpatch, fwdate, fwtime;
1704 /* Upload Microcode. */
1705 data = (__be32 *) (dev->fw.ucode->data + hdr_len);
1706 len = (dev->fw.ucode->size - hdr_len) / sizeof(__be32);
1707 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
1708 for (i = 0; i < len; i++) {
1709 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1714 /* Upload PCM data. */
1715 data = (__be32 *) (dev->fw.pcm->data + hdr_len);
1716 len = (dev->fw.pcm->size - hdr_len) / sizeof(__be32);
1717 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
1718 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
1719 /* No need for autoinc bit in SHM_HW */
1720 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
1721 for (i = 0; i < len; i++) {
1722 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1727 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1728 b43_write32(dev, B43_MMIO_MACCTL,
1729 B43_MACCTL_PSM_RUN |
1730 B43_MACCTL_IHR_ENABLED | B43_MACCTL_INFRA);
1732 /* Wait for the microcode to load and respond */
1735 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1736 if (tmp == B43_IRQ_MAC_SUSPENDED)
1740 b43err(dev->wl, "Microcode not responding\n");
1741 b43_print_fw_helptext(dev->wl);
1747 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
1749 /* Get and check the revisions. */
1750 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
1751 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
1752 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
1753 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
1755 if (fwrev <= 0x128) {
1756 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
1757 "binary drivers older than version 4.x is unsupported. "
1758 "You must upgrade your firmware files.\n");
1759 b43_print_fw_helptext(dev->wl);
1760 b43_write32(dev, B43_MMIO_MACCTL, 0);
1764 b43dbg(dev->wl, "Loading firmware version %u.%u "
1765 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
1767 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
1768 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
1770 dev->fw.rev = fwrev;
1771 dev->fw.patch = fwpatch;
1777 static int b43_write_initvals(struct b43_wldev *dev,
1778 const struct b43_iv *ivals,
1782 const struct b43_iv *iv;
1787 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
1789 for (i = 0; i < count; i++) {
1790 if (array_size < sizeof(iv->offset_size))
1792 array_size -= sizeof(iv->offset_size);
1793 offset = be16_to_cpu(iv->offset_size);
1794 bit32 = !!(offset & B43_IV_32BIT);
1795 offset &= B43_IV_OFFSET_MASK;
1796 if (offset >= 0x1000)
1801 if (array_size < sizeof(iv->data.d32))
1803 array_size -= sizeof(iv->data.d32);
1805 value = be32_to_cpu(get_unaligned(&iv->data.d32));
1806 b43_write32(dev, offset, value);
1808 iv = (const struct b43_iv *)((const uint8_t *)iv +
1814 if (array_size < sizeof(iv->data.d16))
1816 array_size -= sizeof(iv->data.d16);
1818 value = be16_to_cpu(iv->data.d16);
1819 b43_write16(dev, offset, value);
1821 iv = (const struct b43_iv *)((const uint8_t *)iv +
1832 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
1833 b43_print_fw_helptext(dev->wl);
1838 static int b43_upload_initvals(struct b43_wldev *dev)
1840 const size_t hdr_len = sizeof(struct b43_fw_header);
1841 const struct b43_fw_header *hdr;
1842 struct b43_firmware *fw = &dev->fw;
1843 const struct b43_iv *ivals;
1847 hdr = (const struct b43_fw_header *)(fw->initvals->data);
1848 ivals = (const struct b43_iv *)(fw->initvals->data + hdr_len);
1849 count = be32_to_cpu(hdr->size);
1850 err = b43_write_initvals(dev, ivals, count,
1851 fw->initvals->size - hdr_len);
1854 if (fw->initvals_band) {
1855 hdr = (const struct b43_fw_header *)(fw->initvals_band->data);
1856 ivals = (const struct b43_iv *)(fw->initvals_band->data + hdr_len);
1857 count = be32_to_cpu(hdr->size);
1858 err = b43_write_initvals(dev, ivals, count,
1859 fw->initvals_band->size - hdr_len);
1868 /* Initialize the GPIOs
1869 * http://bcm-specs.sipsolutions.net/GPIO
1871 static int b43_gpio_init(struct b43_wldev *dev)
1873 struct ssb_bus *bus = dev->dev->bus;
1874 struct ssb_device *gpiodev, *pcidev = NULL;
1877 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
1878 & ~B43_MACCTL_GPOUTSMSK);
1880 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
1885 if (dev->dev->bus->chip_id == 0x4301) {
1889 if (0 /* FIXME: conditional unknown */ ) {
1890 b43_write16(dev, B43_MMIO_GPIO_MASK,
1891 b43_read16(dev, B43_MMIO_GPIO_MASK)
1896 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
1897 b43_write16(dev, B43_MMIO_GPIO_MASK,
1898 b43_read16(dev, B43_MMIO_GPIO_MASK)
1903 if (dev->dev->id.revision >= 2)
1904 mask |= 0x0010; /* FIXME: This is redundant. */
1906 #ifdef CONFIG_SSB_DRIVER_PCICORE
1907 pcidev = bus->pcicore.dev;
1909 gpiodev = bus->chipco.dev ? : pcidev;
1912 ssb_write32(gpiodev, B43_GPIO_CONTROL,
1913 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
1919 /* Turn off all GPIO stuff. Call this on module unload, for example. */
1920 static void b43_gpio_cleanup(struct b43_wldev *dev)
1922 struct ssb_bus *bus = dev->dev->bus;
1923 struct ssb_device *gpiodev, *pcidev = NULL;
1925 #ifdef CONFIG_SSB_DRIVER_PCICORE
1926 pcidev = bus->pcicore.dev;
1928 gpiodev = bus->chipco.dev ? : pcidev;
1931 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
1934 /* http://bcm-specs.sipsolutions.net/EnableMac */
1935 void b43_mac_enable(struct b43_wldev *dev)
1937 dev->mac_suspended--;
1938 B43_WARN_ON(dev->mac_suspended < 0);
1939 B43_WARN_ON(irqs_disabled());
1940 if (dev->mac_suspended == 0) {
1941 b43_write32(dev, B43_MMIO_MACCTL,
1942 b43_read32(dev, B43_MMIO_MACCTL)
1943 | B43_MACCTL_ENABLED);
1944 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
1945 B43_IRQ_MAC_SUSPENDED);
1947 b43_read32(dev, B43_MMIO_MACCTL);
1948 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1949 b43_power_saving_ctl_bits(dev, 0);
1951 /* Re-enable IRQs. */
1952 spin_lock_irq(&dev->wl->irq_lock);
1953 b43_interrupt_enable(dev, dev->irq_savedstate);
1954 spin_unlock_irq(&dev->wl->irq_lock);
1958 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
1959 void b43_mac_suspend(struct b43_wldev *dev)
1965 B43_WARN_ON(irqs_disabled());
1966 B43_WARN_ON(dev->mac_suspended < 0);
1968 if (dev->mac_suspended == 0) {
1969 /* Mask IRQs before suspending MAC. Otherwise
1970 * the MAC stays busy and won't suspend. */
1971 spin_lock_irq(&dev->wl->irq_lock);
1972 tmp = b43_interrupt_disable(dev, B43_IRQ_ALL);
1973 spin_unlock_irq(&dev->wl->irq_lock);
1974 b43_synchronize_irq(dev);
1975 dev->irq_savedstate = tmp;
1977 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
1978 b43_write32(dev, B43_MMIO_MACCTL,
1979 b43_read32(dev, B43_MMIO_MACCTL)
1980 & ~B43_MACCTL_ENABLED);
1981 /* force pci to flush the write */
1982 b43_read32(dev, B43_MMIO_MACCTL);
1983 for (i = 40; i; i--) {
1984 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1985 if (tmp & B43_IRQ_MAC_SUSPENDED)
1989 b43err(dev->wl, "MAC suspend failed\n");
1992 dev->mac_suspended++;
1995 static void b43_adjust_opmode(struct b43_wldev *dev)
1997 struct b43_wl *wl = dev->wl;
2001 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2002 /* Reset status to STA infrastructure mode. */
2003 ctl &= ~B43_MACCTL_AP;
2004 ctl &= ~B43_MACCTL_KEEP_CTL;
2005 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2006 ctl &= ~B43_MACCTL_KEEP_BAD;
2007 ctl &= ~B43_MACCTL_PROMISC;
2008 ctl &= ~B43_MACCTL_BEACPROMISC;
2009 ctl |= B43_MACCTL_INFRA;
2011 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2012 ctl |= B43_MACCTL_AP;
2013 else if (b43_is_mode(wl, IEEE80211_IF_TYPE_IBSS))
2014 ctl &= ~B43_MACCTL_INFRA;
2016 if (wl->filter_flags & FIF_CONTROL)
2017 ctl |= B43_MACCTL_KEEP_CTL;
2018 if (wl->filter_flags & FIF_FCSFAIL)
2019 ctl |= B43_MACCTL_KEEP_BAD;
2020 if (wl->filter_flags & FIF_PLCPFAIL)
2021 ctl |= B43_MACCTL_KEEP_BADPLCP;
2022 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2023 ctl |= B43_MACCTL_PROMISC;
2024 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2025 ctl |= B43_MACCTL_BEACPROMISC;
2027 /* Workaround: On old hardware the HW-MAC-address-filter
2028 * doesn't work properly, so always run promisc in filter
2029 * it in software. */
2030 if (dev->dev->id.revision <= 4)
2031 ctl |= B43_MACCTL_PROMISC;
2033 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2036 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2037 if (dev->dev->bus->chip_id == 0x4306 &&
2038 dev->dev->bus->chip_rev == 3)
2043 b43_write16(dev, 0x612, cfp_pretbtt);
2046 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2052 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2055 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2057 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2058 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2061 static void b43_rate_memory_init(struct b43_wldev *dev)
2063 switch (dev->phy.type) {
2066 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2067 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2068 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2069 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2070 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2071 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2072 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2073 if (dev->phy.type == B43_PHYTYPE_A)
2077 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2078 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2079 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2080 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2087 /* Set the TX-Antenna for management frames sent by firmware. */
2088 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2095 ant |= B43_TX4_PHY_ANT0;
2098 ant |= B43_TX4_PHY_ANT1;
2100 case B43_ANTENNA_AUTO:
2101 ant |= B43_TX4_PHY_ANTLAST;
2107 /* FIXME We also need to set the other flags of the PHY control field somewhere. */
2110 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
2111 tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2112 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, tmp);
2114 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
2115 tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2116 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2117 /* For Probe Resposes */
2118 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
2119 tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2120 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2123 /* This is the opposite of b43_chip_init() */
2124 static void b43_chip_exit(struct b43_wldev *dev)
2126 b43_radio_turn_off(dev, 1);
2127 b43_gpio_cleanup(dev);
2128 /* firmware is released later */
2131 /* Initialize the chip
2132 * http://bcm-specs.sipsolutions.net/ChipInit
2134 static int b43_chip_init(struct b43_wldev *dev)
2136 struct b43_phy *phy = &dev->phy;
2141 b43_write32(dev, B43_MMIO_MACCTL,
2142 B43_MACCTL_PSM_JMP0 | B43_MACCTL_IHR_ENABLED);
2144 err = b43_request_firmware(dev);
2147 err = b43_upload_microcode(dev);
2149 goto out; /* firmware is released later */
2151 err = b43_gpio_init(dev);
2153 goto out; /* firmware is released later */
2155 err = b43_upload_initvals(dev);
2157 goto err_gpio_clean;
2158 b43_radio_turn_on(dev);
2160 b43_write16(dev, 0x03E6, 0x0000);
2161 err = b43_phy_init(dev);
2165 /* Select initial Interference Mitigation. */
2166 tmp = phy->interfmode;
2167 phy->interfmode = B43_INTERFMODE_NONE;
2168 b43_radio_set_interference_mitigation(dev, tmp);
2170 b43_set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2171 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2173 if (phy->type == B43_PHYTYPE_B) {
2174 value16 = b43_read16(dev, 0x005E);
2176 b43_write16(dev, 0x005E, value16);
2178 b43_write32(dev, 0x0100, 0x01000000);
2179 if (dev->dev->id.revision < 5)
2180 b43_write32(dev, 0x010C, 0x01000000);
2182 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2183 & ~B43_MACCTL_INFRA);
2184 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2185 | B43_MACCTL_INFRA);
2187 /* Probe Response Timeout value */
2188 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2189 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2191 /* Initially set the wireless operation mode. */
2192 b43_adjust_opmode(dev);
2194 if (dev->dev->id.revision < 3) {
2195 b43_write16(dev, 0x060E, 0x0000);
2196 b43_write16(dev, 0x0610, 0x8000);
2197 b43_write16(dev, 0x0604, 0x0000);
2198 b43_write16(dev, 0x0606, 0x0200);
2200 b43_write32(dev, 0x0188, 0x80000000);
2201 b43_write32(dev, 0x018C, 0x02000000);
2203 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2204 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2205 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2206 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2207 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2208 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2209 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2211 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2212 value32 |= 0x00100000;
2213 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2215 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2216 dev->dev->bus->chipco.fast_pwrup_delay);
2219 b43dbg(dev->wl, "Chip initialized\n");
2224 b43_radio_turn_off(dev, 1);
2226 b43_gpio_cleanup(dev);
2230 static void b43_periodic_every120sec(struct b43_wldev *dev)
2232 struct b43_phy *phy = &dev->phy;
2234 if (phy->type != B43_PHYTYPE_G || phy->rev < 2)
2237 b43_mac_suspend(dev);
2238 b43_lo_g_measure(dev);
2239 b43_mac_enable(dev);
2240 if (b43_has_hardware_pctl(phy))
2241 b43_lo_g_ctl_mark_all_unused(dev);
2244 static void b43_periodic_every60sec(struct b43_wldev *dev)
2246 struct b43_phy *phy = &dev->phy;
2248 if (!b43_has_hardware_pctl(phy))
2249 b43_lo_g_ctl_mark_all_unused(dev);
2250 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI) {
2251 b43_mac_suspend(dev);
2252 b43_calc_nrssi_slope(dev);
2253 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) {
2254 u8 old_chan = phy->channel;
2256 /* VCO Calibration */
2258 b43_radio_selectchannel(dev, 1, 0);
2260 b43_radio_selectchannel(dev, 13, 0);
2261 b43_radio_selectchannel(dev, old_chan, 0);
2263 b43_mac_enable(dev);
2267 static void b43_periodic_every30sec(struct b43_wldev *dev)
2269 /* Update device statistics. */
2270 b43_calculate_link_quality(dev);
2273 static void b43_periodic_every15sec(struct b43_wldev *dev)
2275 struct b43_phy *phy = &dev->phy;
2277 if (phy->type == B43_PHYTYPE_G) {
2278 //TODO: update_aci_moving_average
2279 if (phy->aci_enable && phy->aci_wlan_automatic) {
2280 b43_mac_suspend(dev);
2281 if (!phy->aci_enable && 1 /*TODO: not scanning? */ ) {
2282 if (0 /*TODO: bunch of conditions */ ) {
2283 b43_radio_set_interference_mitigation
2284 (dev, B43_INTERFMODE_MANUALWLAN);
2286 } else if (1 /*TODO*/) {
2288 if ((aci_average > 1000) && !(b43_radio_aci_scan(dev))) {
2289 b43_radio_set_interference_mitigation(dev,
2290 B43_INTERFMODE_NONE);
2294 b43_mac_enable(dev);
2295 } else if (phy->interfmode == B43_INTERFMODE_NONWLAN &&
2297 //TODO: implement rev1 workaround
2300 b43_phy_xmitpower(dev); //FIXME: unless scanning?
2301 //TODO for APHY (temperature?)
2303 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2307 static void do_periodic_work(struct b43_wldev *dev)
2311 state = dev->periodic_state;
2313 b43_periodic_every120sec(dev);
2315 b43_periodic_every60sec(dev);
2317 b43_periodic_every30sec(dev);
2318 b43_periodic_every15sec(dev);
2321 /* Periodic work locking policy:
2322 * The whole periodic work handler is protected by
2323 * wl->mutex. If another lock is needed somewhere in the
2324 * pwork callchain, it's aquired in-place, where it's needed.
2326 static void b43_periodic_work_handler(struct work_struct *work)
2328 struct b43_wldev *dev = container_of(work, struct b43_wldev,
2329 periodic_work.work);
2330 struct b43_wl *wl = dev->wl;
2331 unsigned long delay;
2333 mutex_lock(&wl->mutex);
2335 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2337 if (b43_debug(dev, B43_DBG_PWORK_STOP))
2340 do_periodic_work(dev);
2342 dev->periodic_state++;
2344 if (b43_debug(dev, B43_DBG_PWORK_FAST))
2345 delay = msecs_to_jiffies(50);
2347 delay = round_jiffies_relative(HZ * 15);
2348 queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
2350 mutex_unlock(&wl->mutex);
2353 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2355 struct delayed_work *work = &dev->periodic_work;
2357 dev->periodic_state = 0;
2358 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
2359 queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2362 /* Check if communication with the device works correctly. */
2363 static int b43_validate_chipaccess(struct b43_wldev *dev)
2367 backup = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2369 /* Check for read/write and endianness problems. */
2370 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2371 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2373 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2374 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
2377 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup);
2379 if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
2380 /* The 32bit register shadows the two 16bit registers
2381 * with update sideeffects. Validate this. */
2382 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
2383 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
2384 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
2386 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
2389 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
2391 v = b43_read32(dev, B43_MMIO_MACCTL);
2392 v |= B43_MACCTL_GMODE;
2393 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
2398 b43err(dev->wl, "Failed to validate the chipaccess\n");
2402 static void b43_security_init(struct b43_wldev *dev)
2404 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2405 B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2406 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
2407 /* KTP is a word address, but we address SHM bytewise.
2408 * So multiply by two.
2411 if (dev->dev->id.revision >= 5) {
2412 /* Number of RCMTA address slots */
2413 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8);
2415 b43_clear_keys(dev);
2418 static int b43_rng_read(struct hwrng *rng, u32 * data)
2420 struct b43_wl *wl = (struct b43_wl *)rng->priv;
2421 unsigned long flags;
2423 /* Don't take wl->mutex here, as it could deadlock with
2424 * hwrng internal locking. It's not needed to take
2425 * wl->mutex here, anyway. */
2427 spin_lock_irqsave(&wl->irq_lock, flags);
2428 *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
2429 spin_unlock_irqrestore(&wl->irq_lock, flags);
2431 return (sizeof(u16));
2434 static void b43_rng_exit(struct b43_wl *wl)
2436 if (wl->rng_initialized)
2437 hwrng_unregister(&wl->rng);
2440 static int b43_rng_init(struct b43_wl *wl)
2444 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2445 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2446 wl->rng.name = wl->rng_name;
2447 wl->rng.data_read = b43_rng_read;
2448 wl->rng.priv = (unsigned long)wl;
2449 wl->rng_initialized = 1;
2450 err = hwrng_register(&wl->rng);
2452 wl->rng_initialized = 0;
2453 b43err(wl, "Failed to register the random "
2454 "number generator (%d)\n", err);
2460 static int b43_op_tx(struct ieee80211_hw *hw,
2461 struct sk_buff *skb,
2462 struct ieee80211_tx_control *ctl)
2464 struct b43_wl *wl = hw_to_b43_wl(hw);
2465 struct b43_wldev *dev = wl->current_dev;
2470 if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2472 /* DMA-TX is done without a global lock. */
2473 err = b43_dma_tx(dev, skb, ctl);
2476 return NETDEV_TX_BUSY;
2477 return NETDEV_TX_OK;
2480 static int b43_op_conf_tx(struct ieee80211_hw *hw,
2482 const struct ieee80211_tx_queue_params *params)
2487 static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
2488 struct ieee80211_tx_queue_stats *stats)
2490 struct b43_wl *wl = hw_to_b43_wl(hw);
2491 struct b43_wldev *dev = wl->current_dev;
2492 unsigned long flags;
2497 spin_lock_irqsave(&wl->irq_lock, flags);
2498 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
2499 b43_dma_get_tx_stats(dev, stats);
2502 spin_unlock_irqrestore(&wl->irq_lock, flags);
2507 static int b43_op_get_stats(struct ieee80211_hw *hw,
2508 struct ieee80211_low_level_stats *stats)
2510 struct b43_wl *wl = hw_to_b43_wl(hw);
2511 unsigned long flags;
2513 spin_lock_irqsave(&wl->irq_lock, flags);
2514 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
2515 spin_unlock_irqrestore(&wl->irq_lock, flags);
2520 static const char *phymode_to_string(unsigned int phymode)
2535 static int find_wldev_for_phymode(struct b43_wl *wl,
2536 unsigned int phymode,
2537 struct b43_wldev **dev, bool * gmode)
2539 struct b43_wldev *d;
2541 list_for_each_entry(d, &wl->devlist, list) {
2542 if (d->phy.possible_phymodes & phymode) {
2543 /* Ok, this device supports the PHY-mode.
2544 * Now figure out how the gmode bit has to be
2545 * set to support it. */
2546 if (phymode == B43_PHYMODE_A)
2559 static void b43_put_phy_into_reset(struct b43_wldev *dev)
2561 struct ssb_device *sdev = dev->dev;
2564 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2565 tmslow &= ~B43_TMSLOW_GMODE;
2566 tmslow |= B43_TMSLOW_PHYRESET;
2567 tmslow |= SSB_TMSLOW_FGC;
2568 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2571 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2572 tmslow &= ~SSB_TMSLOW_FGC;
2573 tmslow |= B43_TMSLOW_PHYRESET;
2574 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2578 /* Expects wl->mutex locked */
2579 static int b43_switch_phymode(struct b43_wl *wl, unsigned int new_mode)
2581 struct b43_wldev *up_dev;
2582 struct b43_wldev *down_dev;
2587 err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
2589 b43err(wl, "Could not find a device for %s-PHY mode\n",
2590 phymode_to_string(new_mode));
2593 if ((up_dev == wl->current_dev) &&
2594 (!!wl->current_dev->phy.gmode == !!gmode)) {
2595 /* This device is already running. */
2598 b43dbg(wl, "Reconfiguring PHYmode to %s-PHY\n",
2599 phymode_to_string(new_mode));
2600 down_dev = wl->current_dev;
2602 prev_status = b43_status(down_dev);
2603 /* Shutdown the currently running core. */
2604 if (prev_status >= B43_STAT_STARTED)
2605 b43_wireless_core_stop(down_dev);
2606 if (prev_status >= B43_STAT_INITIALIZED)
2607 b43_wireless_core_exit(down_dev);
2609 if (down_dev != up_dev) {
2610 /* We switch to a different core, so we put PHY into
2611 * RESET on the old core. */
2612 b43_put_phy_into_reset(down_dev);
2615 /* Now start the new core. */
2616 up_dev->phy.gmode = gmode;
2617 if (prev_status >= B43_STAT_INITIALIZED) {
2618 err = b43_wireless_core_init(up_dev);
2620 b43err(wl, "Fatal: Could not initialize device for "
2621 "newly selected %s-PHY mode\n",
2622 phymode_to_string(new_mode));
2626 if (prev_status >= B43_STAT_STARTED) {
2627 err = b43_wireless_core_start(up_dev);
2629 b43err(wl, "Fatal: Coult not start device for "
2630 "newly selected %s-PHY mode\n",
2631 phymode_to_string(new_mode));
2632 b43_wireless_core_exit(up_dev);
2636 B43_WARN_ON(b43_status(up_dev) != prev_status);
2638 wl->current_dev = up_dev;
2642 /* Whoops, failed to init the new core. No core is operating now. */
2643 wl->current_dev = NULL;
2647 /* Check if the use of the antenna that ieee80211 told us to
2648 * use is possible. This will fall back to DEFAULT.
2649 * "antenna_nr" is the antenna identifier we got from ieee80211. */
2650 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
2655 if (antenna_nr == 0) {
2656 /* Zero means "use default antenna". That's always OK. */
2660 /* Get the mask of available antennas. */
2662 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
2664 antenna_mask = dev->dev->bus->sprom.ant_available_a;
2666 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
2667 /* This antenna is not available. Fall back to default. */
2674 static int b43_antenna_from_ieee80211(struct b43_wldev *dev, u8 antenna)
2676 antenna = b43_ieee80211_antenna_sanitize(dev, antenna);
2678 case 0: /* default/diversity */
2679 return B43_ANTENNA_DEFAULT;
2680 case 1: /* Antenna 0 */
2681 return B43_ANTENNA0;
2682 case 2: /* Antenna 1 */
2683 return B43_ANTENNA1;
2685 return B43_ANTENNA_DEFAULT;
2689 static int b43_op_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
2691 struct b43_wl *wl = hw_to_b43_wl(hw);
2692 struct b43_wldev *dev;
2693 struct b43_phy *phy;
2694 unsigned long flags;
2695 unsigned int new_phymode = 0xFFFF;
2700 mutex_lock(&wl->mutex);
2702 /* Switch the PHY mode (if necessary). */
2703 switch (conf->phymode) {
2704 case MODE_IEEE80211A:
2705 new_phymode = B43_PHYMODE_A;
2707 case MODE_IEEE80211B:
2708 new_phymode = B43_PHYMODE_B;
2710 case MODE_IEEE80211G:
2711 new_phymode = B43_PHYMODE_G;
2716 err = b43_switch_phymode(wl, new_phymode);
2718 goto out_unlock_mutex;
2719 dev = wl->current_dev;
2722 /* Disable IRQs while reconfiguring the device.
2723 * This makes it possible to drop the spinlock throughout
2724 * the reconfiguration process. */
2725 spin_lock_irqsave(&wl->irq_lock, flags);
2726 if (b43_status(dev) < B43_STAT_STARTED) {
2727 spin_unlock_irqrestore(&wl->irq_lock, flags);
2728 goto out_unlock_mutex;
2730 savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL);
2731 spin_unlock_irqrestore(&wl->irq_lock, flags);
2732 b43_synchronize_irq(dev);
2734 /* Switch to the requested channel.
2735 * The firmware takes care of races with the TX handler. */
2736 if (conf->channel_val != phy->channel)
2737 b43_radio_selectchannel(dev, conf->channel_val, 0);
2739 /* Enable/Disable ShortSlot timing. */
2740 if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) !=
2742 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
2743 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
2744 b43_short_slot_timing_enable(dev);
2746 b43_short_slot_timing_disable(dev);
2749 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
2751 /* Adjust the desired TX power level. */
2752 if (conf->power_level != 0) {
2753 if (conf->power_level != phy->power_level) {
2754 phy->power_level = conf->power_level;
2755 b43_phy_xmitpower(dev);
2759 /* Antennas for RX and management frame TX. */
2760 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_tx);
2761 b43_mgmtframe_txantenna(dev, antenna);
2762 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_rx);
2763 b43_set_rx_antenna(dev, antenna);
2765 /* Update templates for AP mode. */
2766 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2767 b43_set_beacon_int(dev, conf->beacon_int);
2769 if (!!conf->radio_enabled != phy->radio_on) {
2770 if (conf->radio_enabled) {
2771 b43_radio_turn_on(dev);
2772 b43info(dev->wl, "Radio turned on by software\n");
2773 if (!dev->radio_hw_enable) {
2774 b43info(dev->wl, "The hardware RF-kill button "
2775 "still turns the radio physically off. "
2776 "Press the button to turn it on.\n");
2779 b43_radio_turn_off(dev, 0);
2780 b43info(dev->wl, "Radio turned off by software\n");
2784 spin_lock_irqsave(&wl->irq_lock, flags);
2785 b43_interrupt_enable(dev, savedirqs);
2787 spin_unlock_irqrestore(&wl->irq_lock, flags);
2789 mutex_unlock(&wl->mutex);
2794 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2795 const u8 *local_addr, const u8 *addr,
2796 struct ieee80211_key_conf *key)
2798 struct b43_wl *wl = hw_to_b43_wl(hw);
2799 struct b43_wldev *dev;
2800 unsigned long flags;
2804 DECLARE_MAC_BUF(mac);
2806 if (modparam_nohwcrypt)
2807 return -ENOSPC; /* User disabled HW-crypto */
2809 mutex_lock(&wl->mutex);
2810 spin_lock_irqsave(&wl->irq_lock, flags);
2812 dev = wl->current_dev;
2814 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
2820 if (key->keylen == 5)
2821 algorithm = B43_SEC_ALGO_WEP40;
2823 algorithm = B43_SEC_ALGO_WEP104;
2826 algorithm = B43_SEC_ALGO_TKIP;
2829 algorithm = B43_SEC_ALGO_AES;
2835 index = (u8) (key->keyidx);
2841 if (algorithm == B43_SEC_ALGO_TKIP) {
2842 /* FIXME: No TKIP hardware encryption for now. */
2847 if (is_broadcast_ether_addr(addr)) {
2848 /* addr is FF:FF:FF:FF:FF:FF for default keys */
2849 err = b43_key_write(dev, index, algorithm,
2850 key->key, key->keylen, NULL, key);
2853 * either pairwise key or address is 00:00:00:00:00:00
2854 * for transmit-only keys
2856 err = b43_key_write(dev, -1, algorithm,
2857 key->key, key->keylen, addr, key);
2862 if (algorithm == B43_SEC_ALGO_WEP40 ||
2863 algorithm == B43_SEC_ALGO_WEP104) {
2864 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
2867 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
2869 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2872 err = b43_key_clear(dev, key->hw_key_idx);
2881 spin_unlock_irqrestore(&wl->irq_lock, flags);
2882 mutex_unlock(&wl->mutex);
2884 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
2886 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
2887 print_mac(mac, addr));
2892 static void b43_op_configure_filter(struct ieee80211_hw *hw,
2893 unsigned int changed, unsigned int *fflags,
2894 int mc_count, struct dev_addr_list *mc_list)
2896 struct b43_wl *wl = hw_to_b43_wl(hw);
2897 struct b43_wldev *dev = wl->current_dev;
2898 unsigned long flags;
2905 spin_lock_irqsave(&wl->irq_lock, flags);
2906 *fflags &= FIF_PROMISC_IN_BSS |
2912 FIF_BCN_PRBRESP_PROMISC;
2914 changed &= FIF_PROMISC_IN_BSS |
2920 FIF_BCN_PRBRESP_PROMISC;
2922 wl->filter_flags = *fflags;
2924 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
2925 b43_adjust_opmode(dev);
2926 spin_unlock_irqrestore(&wl->irq_lock, flags);
2929 static int b43_op_config_interface(struct ieee80211_hw *hw,
2931 struct ieee80211_if_conf *conf)
2933 struct b43_wl *wl = hw_to_b43_wl(hw);
2934 struct b43_wldev *dev = wl->current_dev;
2935 unsigned long flags;
2939 mutex_lock(&wl->mutex);
2940 spin_lock_irqsave(&wl->irq_lock, flags);
2941 B43_WARN_ON(wl->if_id != if_id);
2943 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
2945 memset(wl->bssid, 0, ETH_ALEN);
2946 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
2947 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) {
2948 B43_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP);
2949 b43_set_ssid(dev, conf->ssid, conf->ssid_len);
2951 b43_refresh_templates(dev, conf->beacon);
2953 b43_write_mac_bssid_templates(dev);
2955 spin_unlock_irqrestore(&wl->irq_lock, flags);
2956 mutex_unlock(&wl->mutex);
2961 /* Locking: wl->mutex */
2962 static void b43_wireless_core_stop(struct b43_wldev *dev)
2964 struct b43_wl *wl = dev->wl;
2965 unsigned long flags;
2967 if (b43_status(dev) < B43_STAT_STARTED)
2970 /* Disable and sync interrupts. We must do this before than
2971 * setting the status to INITIALIZED, as the interrupt handler
2972 * won't care about IRQs then. */
2973 spin_lock_irqsave(&wl->irq_lock, flags);
2974 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
2975 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
2976 spin_unlock_irqrestore(&wl->irq_lock, flags);
2977 b43_synchronize_irq(dev);
2979 b43_set_status(dev, B43_STAT_INITIALIZED);
2981 mutex_unlock(&wl->mutex);
2982 /* Must unlock as it would otherwise deadlock. No races here.
2983 * Cancel the possibly running self-rearming periodic work. */
2984 cancel_delayed_work_sync(&dev->periodic_work);
2985 mutex_lock(&wl->mutex);
2987 ieee80211_stop_queues(wl->hw); //FIXME this could cause a deadlock, as mac80211 seems buggy.
2989 b43_mac_suspend(dev);
2990 free_irq(dev->dev->irq, dev);
2991 b43dbg(wl, "Wireless interface stopped\n");
2994 /* Locking: wl->mutex */
2995 static int b43_wireless_core_start(struct b43_wldev *dev)
2999 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3001 drain_txstatus_queue(dev);
3002 err = request_irq(dev->dev->irq, b43_interrupt_handler,
3003 IRQF_SHARED, KBUILD_MODNAME, dev);
3005 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3009 /* We are ready to run. */
3010 b43_set_status(dev, B43_STAT_STARTED);
3012 /* Start data flow (TX/RX). */
3013 b43_mac_enable(dev);
3014 b43_interrupt_enable(dev, dev->irq_savedstate);
3015 ieee80211_start_queues(dev->wl->hw);
3017 /* Start maintainance work */
3018 b43_periodic_tasks_setup(dev);
3020 b43dbg(dev->wl, "Wireless interface started\n");
3025 /* Get PHY and RADIO versioning numbers */
3026 static int b43_phy_versioning(struct b43_wldev *dev)
3028 struct b43_phy *phy = &dev->phy;
3036 int unsupported = 0;
3038 /* Get PHY versioning */
3039 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3040 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3041 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3042 phy_rev = (tmp & B43_PHYVER_VERSION);
3049 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3057 #ifdef CONFIG_B43_NPHY
3067 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3068 "(Analog %u, Type %u, Revision %u)\n",
3069 analog_type, phy_type, phy_rev);
3072 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3073 analog_type, phy_type, phy_rev);
3075 /* Get RADIO versioning */
3076 if (dev->dev->bus->chip_id == 0x4317) {
3077 if (dev->dev->bus->chip_rev == 0)
3079 else if (dev->dev->bus->chip_rev == 1)
3084 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3085 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH);
3087 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3088 tmp |= b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3090 radio_manuf = (tmp & 0x00000FFF);
3091 radio_ver = (tmp & 0x0FFFF000) >> 12;
3092 radio_rev = (tmp & 0xF0000000) >> 28;
3095 if (radio_ver != 0x2060)
3099 if (radio_manuf != 0x17F)
3103 if ((radio_ver & 0xFFF0) != 0x2050)
3107 if (radio_ver != 0x2050)
3114 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
3115 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3116 radio_manuf, radio_ver, radio_rev);
3119 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3120 radio_manuf, radio_ver, radio_rev);
3122 phy->radio_manuf = radio_manuf;
3123 phy->radio_ver = radio_ver;
3124 phy->radio_rev = radio_rev;
3126 phy->analog = analog_type;
3127 phy->type = phy_type;
3133 static void setup_struct_phy_for_init(struct b43_wldev *dev,
3134 struct b43_phy *phy)
3136 struct b43_txpower_lo_control *lo;
3139 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3140 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3145 phy->aci_enable = 0;
3146 phy->aci_wlan_automatic = 0;
3147 phy->aci_hw_rssi = 0;
3149 phy->radio_off_context.valid = 0;
3151 lo = phy->lo_control;
3153 memset(lo, 0, sizeof(*(phy->lo_control)));
3157 phy->max_lb_gain = 0;
3158 phy->trsw_rx_gain = 0;
3159 phy->txpwr_offset = 0;
3162 phy->nrssislope = 0;
3163 for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3164 phy->nrssi[i] = -1000;
3165 for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3166 phy->nrssi_lt[i] = i;
3168 phy->lofcal = 0xFFFF;
3169 phy->initval = 0xFFFF;
3171 spin_lock_init(&phy->lock);
3172 phy->interfmode = B43_INTERFMODE_NONE;
3173 phy->channel = 0xFF;
3175 phy->hardware_power_control = !!modparam_hwpctl;
3177 /* PHY TX errors counter. */
3178 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3180 /* OFDM-table address caching. */
3181 phy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_UNKNOWN;
3184 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
3188 /* Assume the radio is enabled. If it's not enabled, the state will
3189 * immediately get fixed on the first periodic work run. */
3190 dev->radio_hw_enable = 1;
3193 memset(&dev->stats, 0, sizeof(dev->stats));
3195 setup_struct_phy_for_init(dev, &dev->phy);
3197 /* IRQ related flags */
3198 dev->irq_reason = 0;
3199 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3200 dev->irq_savedstate = B43_IRQ_MASKTEMPLATE;
3202 dev->mac_suspended = 1;
3204 /* Noise calculation context */
3205 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3208 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
3210 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3213 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
3215 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
3218 hf = b43_hf_read(dev);
3219 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
3220 hf |= B43_HF_BTCOEXALT;
3222 hf |= B43_HF_BTCOEX;
3223 b43_hf_write(dev, hf);
3227 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
3231 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
3233 #ifdef CONFIG_SSB_DRIVER_PCICORE
3234 struct ssb_bus *bus = dev->dev->bus;
3237 if (bus->pcicore.dev &&
3238 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
3239 bus->pcicore.dev->id.revision <= 5) {
3240 /* IMCFGLO timeouts workaround. */
3241 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
3242 tmp &= ~SSB_IMCFGLO_REQTO;
3243 tmp &= ~SSB_IMCFGLO_SERTO;
3244 switch (bus->bustype) {
3245 case SSB_BUSTYPE_PCI:
3246 case SSB_BUSTYPE_PCMCIA:
3249 case SSB_BUSTYPE_SSB:
3253 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
3255 #endif /* CONFIG_SSB_DRIVER_PCICORE */
3258 /* Write the short and long frame retry limit values. */
3259 static void b43_set_retry_limits(struct b43_wldev *dev,
3260 unsigned int short_retry,
3261 unsigned int long_retry)
3263 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3264 * the chip-internal counter. */
3265 short_retry = min(short_retry, (unsigned int)0xF);
3266 long_retry = min(long_retry, (unsigned int)0xF);
3268 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3270 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3274 /* Shutdown a wireless core */
3275 /* Locking: wl->mutex */
3276 static void b43_wireless_core_exit(struct b43_wldev *dev)
3278 struct b43_phy *phy = &dev->phy;
3280 B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
3281 if (b43_status(dev) != B43_STAT_INITIALIZED)
3283 b43_set_status(dev, B43_STAT_UNINIT);
3286 b43_rng_exit(dev->wl);
3289 b43_radio_turn_off(dev, 1);
3290 b43_switch_analog(dev, 0);
3291 if (phy->dyn_tssi_tbl)
3292 kfree(phy->tssi2dbm);
3293 kfree(phy->lo_control);
3294 phy->lo_control = NULL;
3295 ssb_device_disable(dev->dev, 0);
3296 ssb_bus_may_powerdown(dev->dev->bus);
3299 /* Initialize a wireless core */
3300 static int b43_wireless_core_init(struct b43_wldev *dev)
3302 struct b43_wl *wl = dev->wl;
3303 struct ssb_bus *bus = dev->dev->bus;
3304 struct ssb_sprom *sprom = &bus->sprom;
3305 struct b43_phy *phy = &dev->phy;
3309 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3311 err = ssb_bus_powerup(bus, 0);
3314 if (!ssb_device_is_enabled(dev->dev)) {
3315 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
3316 b43_wireless_core_reset(dev, tmp);
3319 if ((phy->type == B43_PHYTYPE_B) || (phy->type == B43_PHYTYPE_G)) {
3321 kzalloc(sizeof(*(phy->lo_control)), GFP_KERNEL);
3322 if (!phy->lo_control) {
3327 setup_struct_wldev_for_init(dev);
3329 err = b43_phy_init_tssi2dbm_table(dev);
3331 goto err_kfree_lo_control;
3333 /* Enable IRQ routing to this device. */
3334 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3336 b43_imcfglo_timeouts_workaround(dev);
3337 b43_bluetooth_coext_disable(dev);
3338 b43_phy_early_init(dev);
3339 err = b43_chip_init(dev);
3341 goto err_kfree_tssitbl;
3342 b43_shm_write16(dev, B43_SHM_SHARED,
3343 B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
3344 hf = b43_hf_read(dev);
3345 if (phy->type == B43_PHYTYPE_G) {
3349 if (sprom->boardflags_lo & B43_BFL_PACTRL)
3350 hf |= B43_HF_OFDMPABOOST;
3351 } else if (phy->type == B43_PHYTYPE_B) {
3353 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
3356 b43_hf_write(dev, hf);
3358 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
3359 B43_DEFAULT_LONG_RETRY_LIMIT);
3360 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
3361 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
3363 /* Disable sending probe responses from firmware.
3364 * Setting the MaxTime to one usec will always trigger
3365 * a timeout, so we never send any probe resp.
3366 * A timeout of zero is infinite. */
3367 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
3369 b43_rate_memory_init(dev);
3371 /* Minimum Contention Window */
3372 if (phy->type == B43_PHYTYPE_B) {
3373 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
3375 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
3377 /* Maximum Contention Window */
3378 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
3380 err = b43_dma_init(dev);
3387 b43_write16(dev, 0x0612, 0x0050);
3388 b43_shm_write16(dev, B43_SHM_SHARED, 0x0416, 0x0050);
3389 b43_shm_write16(dev, B43_SHM_SHARED, 0x0414, 0x01F4);
3392 b43_bluetooth_coext_enable(dev);
3394 ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
3395 memset(wl->bssid, 0, ETH_ALEN);
3396 memset(wl->mac_addr, 0, ETH_ALEN);
3397 b43_upload_card_macaddress(dev);
3398 b43_security_init(dev);
3401 b43_set_status(dev, B43_STAT_INITIALIZED);
3410 if (phy->dyn_tssi_tbl)
3411 kfree(phy->tssi2dbm);
3412 err_kfree_lo_control:
3413 kfree(phy->lo_control);
3414 phy->lo_control = NULL;
3416 ssb_bus_may_powerdown(bus);
3417 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3421 static int b43_op_add_interface(struct ieee80211_hw *hw,
3422 struct ieee80211_if_init_conf *conf)
3424 struct b43_wl *wl = hw_to_b43_wl(hw);
3425 struct b43_wldev *dev;
3426 unsigned long flags;
3427 int err = -EOPNOTSUPP;
3429 /* TODO: allow WDS/AP devices to coexist */
3431 if (conf->type != IEEE80211_IF_TYPE_AP &&
3432 conf->type != IEEE80211_IF_TYPE_STA &&
3433 conf->type != IEEE80211_IF_TYPE_WDS &&
3434 conf->type != IEEE80211_IF_TYPE_IBSS)
3437 mutex_lock(&wl->mutex);
3439 goto out_mutex_unlock;
3441 b43dbg(wl, "Adding Interface type %d\n", conf->type);
3443 dev = wl->current_dev;
3445 wl->if_id = conf->if_id;
3446 wl->if_type = conf->type;
3447 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
3449 spin_lock_irqsave(&wl->irq_lock, flags);
3450 b43_adjust_opmode(dev);
3451 b43_upload_card_macaddress(dev);
3452 spin_unlock_irqrestore(&wl->irq_lock, flags);
3456 mutex_unlock(&wl->mutex);
3461 static void b43_op_remove_interface(struct ieee80211_hw *hw,
3462 struct ieee80211_if_init_conf *conf)
3464 struct b43_wl *wl = hw_to_b43_wl(hw);
3465 struct b43_wldev *dev = wl->current_dev;
3466 unsigned long flags;
3468 b43dbg(wl, "Removing Interface type %d\n", conf->type);
3470 mutex_lock(&wl->mutex);
3472 B43_WARN_ON(!wl->operating);
3473 B43_WARN_ON(wl->if_id != conf->if_id);
3477 spin_lock_irqsave(&wl->irq_lock, flags);
3478 b43_adjust_opmode(dev);
3479 memset(wl->mac_addr, 0, ETH_ALEN);
3480 b43_upload_card_macaddress(dev);
3481 spin_unlock_irqrestore(&wl->irq_lock, flags);
3483 mutex_unlock(&wl->mutex);
3486 static int b43_op_start(struct ieee80211_hw *hw)
3488 struct b43_wl *wl = hw_to_b43_wl(hw);
3489 struct b43_wldev *dev = wl->current_dev;
3493 /* First register RFkill.
3494 * LEDs that are registered later depend on it. */
3495 b43_rfkill_init(dev);
3497 mutex_lock(&wl->mutex);
3499 if (b43_status(dev) < B43_STAT_INITIALIZED) {
3500 err = b43_wireless_core_init(dev);
3502 goto out_mutex_unlock;
3506 if (b43_status(dev) < B43_STAT_STARTED) {
3507 err = b43_wireless_core_start(dev);
3510 b43_wireless_core_exit(dev);
3511 goto out_mutex_unlock;
3516 mutex_unlock(&wl->mutex);
3521 static void b43_op_stop(struct ieee80211_hw *hw)
3523 struct b43_wl *wl = hw_to_b43_wl(hw);
3524 struct b43_wldev *dev = wl->current_dev;
3526 b43_rfkill_exit(dev);
3528 mutex_lock(&wl->mutex);
3529 if (b43_status(dev) >= B43_STAT_STARTED)
3530 b43_wireless_core_stop(dev);
3531 b43_wireless_core_exit(dev);
3532 mutex_unlock(&wl->mutex);
3535 static int b43_op_set_retry_limit(struct ieee80211_hw *hw,
3536 u32 short_retry_limit, u32 long_retry_limit)
3538 struct b43_wl *wl = hw_to_b43_wl(hw);
3539 struct b43_wldev *dev;
3542 mutex_lock(&wl->mutex);
3543 dev = wl->current_dev;
3544 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED))) {
3548 b43_set_retry_limits(dev, short_retry_limit, long_retry_limit);
3550 mutex_unlock(&wl->mutex);
3555 static const struct ieee80211_ops b43_hw_ops = {
3557 .conf_tx = b43_op_conf_tx,
3558 .add_interface = b43_op_add_interface,
3559 .remove_interface = b43_op_remove_interface,
3560 .config = b43_op_config,
3561 .config_interface = b43_op_config_interface,
3562 .configure_filter = b43_op_configure_filter,
3563 .set_key = b43_op_set_key,
3564 .get_stats = b43_op_get_stats,
3565 .get_tx_stats = b43_op_get_tx_stats,
3566 .start = b43_op_start,
3567 .stop = b43_op_stop,
3568 .set_retry_limit = b43_op_set_retry_limit,
3571 /* Hard-reset the chip. Do not call this directly.
3572 * Use b43_controller_restart()
3574 static void b43_chip_reset(struct work_struct *work)
3576 struct b43_wldev *dev =
3577 container_of(work, struct b43_wldev, restart_work);
3578 struct b43_wl *wl = dev->wl;
3582 mutex_lock(&wl->mutex);
3584 prev_status = b43_status(dev);
3585 /* Bring the device down... */
3586 if (prev_status >= B43_STAT_STARTED)
3587 b43_wireless_core_stop(dev);
3588 if (prev_status >= B43_STAT_INITIALIZED)
3589 b43_wireless_core_exit(dev);
3591 /* ...and up again. */
3592 if (prev_status >= B43_STAT_INITIALIZED) {
3593 err = b43_wireless_core_init(dev);
3597 if (prev_status >= B43_STAT_STARTED) {
3598 err = b43_wireless_core_start(dev);
3600 b43_wireless_core_exit(dev);
3605 mutex_unlock(&wl->mutex);
3607 b43err(wl, "Controller restart FAILED\n");
3609 b43info(wl, "Controller restarted\n");
3612 static int b43_setup_modes(struct b43_wldev *dev,
3613 int have_aphy, int have_bphy, int have_gphy)
3615 struct ieee80211_hw *hw = dev->wl->hw;
3616 struct ieee80211_hw_mode *mode;
3617 struct b43_phy *phy = &dev->phy;
3621 /*FIXME: Don't tell ieee80211 about an A-PHY, because we currently don't support A-PHY. */
3624 phy->possible_phymodes = 0;
3627 B43_WARN_ON(cnt >= B43_MAX_PHYHWMODES);
3628 mode = &phy->hwmodes[cnt];
3630 mode->mode = MODE_IEEE80211A;
3631 mode->num_channels = b43_a_chantable_size;
3632 mode->channels = b43_a_chantable;
3633 mode->num_rates = b43_a_ratetable_size;
3634 mode->rates = b43_a_ratetable;
3635 err = ieee80211_register_hwmode(hw, mode);
3639 phy->possible_phymodes |= B43_PHYMODE_A;
3644 B43_WARN_ON(cnt >= B43_MAX_PHYHWMODES);
3645 mode = &phy->hwmodes[cnt];
3647 mode->mode = MODE_IEEE80211B;
3648 mode->num_channels = b43_bg_chantable_size;
3649 mode->channels = b43_bg_chantable;
3650 mode->num_rates = b43_b_ratetable_size;
3651 mode->rates = b43_b_ratetable;
3652 err = ieee80211_register_hwmode(hw, mode);
3656 phy->possible_phymodes |= B43_PHYMODE_B;
3661 B43_WARN_ON(cnt >= B43_MAX_PHYHWMODES);
3662 mode = &phy->hwmodes[cnt];
3664 mode->mode = MODE_IEEE80211G;
3665 mode->num_channels = b43_bg_chantable_size;
3666 mode->channels = b43_bg_chantable;
3667 mode->num_rates = b43_g_ratetable_size;
3668 mode->rates = b43_g_ratetable;
3669 err = ieee80211_register_hwmode(hw, mode);
3673 phy->possible_phymodes |= B43_PHYMODE_G;
3683 static void b43_wireless_core_detach(struct b43_wldev *dev)
3685 /* We release firmware that late to not be required to re-request
3686 * is all the time when we reinit the core. */
3687 b43_release_firmware(dev);
3690 static int b43_wireless_core_attach(struct b43_wldev *dev)
3692 struct b43_wl *wl = dev->wl;
3693 struct ssb_bus *bus = dev->dev->bus;
3694 struct pci_dev *pdev = bus->host_pci;
3696 int have_aphy = 0, have_bphy = 0, have_gphy = 0;
3699 /* Do NOT do any device initialization here.
3700 * Do it in wireless_core_init() instead.
3701 * This function is for gathering basic information about the HW, only.
3702 * Also some structs may be set up here. But most likely you want to have
3703 * that in core_init(), too.
3706 err = ssb_bus_powerup(bus, 0);
3708 b43err(wl, "Bus powerup failed\n");
3711 /* Get the PHY type. */
3712 if (dev->dev->id.revision >= 5) {
3715 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
3716 have_aphy = !!(tmshigh & B43_TMSHIGH_APHY);
3717 have_gphy = !!(tmshigh & B43_TMSHIGH_GPHY);
3718 if (!have_aphy && !have_gphy)
3720 } else if (dev->dev->id.revision == 4) {
3726 dev->phy.gmode = (have_gphy || have_bphy);
3727 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3728 b43_wireless_core_reset(dev, tmp);
3730 err = b43_phy_versioning(dev);
3733 /* Check if this device supports multiband. */
3735 (pdev->device != 0x4312 &&
3736 pdev->device != 0x4319 && pdev->device != 0x4324)) {
3737 /* No multiband support. */
3741 switch (dev->phy.type) {
3755 dev->phy.gmode = (have_gphy || have_bphy);
3756 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3757 b43_wireless_core_reset(dev, tmp);
3759 err = b43_validate_chipaccess(dev);
3762 err = b43_setup_modes(dev, have_aphy, have_bphy, have_gphy);
3766 /* Now set some default "current_dev" */
3767 if (!wl->current_dev)
3768 wl->current_dev = dev;
3769 INIT_WORK(&dev->restart_work, b43_chip_reset);
3771 b43_radio_turn_off(dev, 1);
3772 b43_switch_analog(dev, 0);
3773 ssb_device_disable(dev->dev, 0);
3774 ssb_bus_may_powerdown(bus);
3780 ssb_bus_may_powerdown(bus);
3784 static void b43_one_core_detach(struct ssb_device *dev)
3786 struct b43_wldev *wldev;
3789 wldev = ssb_get_drvdata(dev);
3791 cancel_work_sync(&wldev->restart_work);
3792 b43_debugfs_remove_device(wldev);
3793 b43_wireless_core_detach(wldev);
3794 list_del(&wldev->list);
3796 ssb_set_drvdata(dev, NULL);
3800 static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
3802 struct b43_wldev *wldev;
3803 struct pci_dev *pdev;
3806 if (!list_empty(&wl->devlist)) {
3807 /* We are not the first core on this chip. */
3808 pdev = dev->bus->host_pci;
3809 /* Only special chips support more than one wireless
3810 * core, although some of the other chips have more than
3811 * one wireless core as well. Check for this and
3815 ((pdev->device != 0x4321) &&
3816 (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
3817 b43dbg(wl, "Ignoring unconnected 802.11 core\n");
3822 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
3828 b43_set_status(wldev, B43_STAT_UNINIT);
3829 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
3830 tasklet_init(&wldev->isr_tasklet,
3831 (void (*)(unsigned long))b43_interrupt_tasklet,
3832 (unsigned long)wldev);
3833 INIT_LIST_HEAD(&wldev->list);
3835 err = b43_wireless_core_attach(wldev);
3837 goto err_kfree_wldev;
3839 list_add(&wldev->list, &wl->devlist);
3841 ssb_set_drvdata(dev, wldev);
3842 b43_debugfs_add_device(wldev);
3852 static void b43_sprom_fixup(struct ssb_bus *bus)
3854 /* boardflags workarounds */
3855 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
3856 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
3857 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
3858 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3859 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
3860 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
3863 static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
3865 struct ieee80211_hw *hw = wl->hw;
3867 ssb_set_devtypedata(dev, NULL);
3868 ieee80211_free_hw(hw);
3871 static int b43_wireless_init(struct ssb_device *dev)
3873 struct ssb_sprom *sprom = &dev->bus->sprom;
3874 struct ieee80211_hw *hw;
3878 b43_sprom_fixup(dev->bus);
3880 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
3882 b43err(NULL, "Could not allocate ieee80211 device\n");
3887 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
3888 IEEE80211_HW_RX_INCLUDES_FCS;
3889 hw->max_signal = 100;
3890 hw->max_rssi = -110;
3891 hw->max_noise = -110;
3892 hw->queues = 1; /* FIXME: hardware has more queues */
3893 SET_IEEE80211_DEV(hw, dev->dev);
3894 if (is_valid_ether_addr(sprom->et1mac))
3895 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
3897 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
3899 /* Get and initialize struct b43_wl */
3900 wl = hw_to_b43_wl(hw);
3901 memset(wl, 0, sizeof(*wl));
3903 spin_lock_init(&wl->irq_lock);
3904 spin_lock_init(&wl->leds_lock);
3905 mutex_init(&wl->mutex);
3906 INIT_LIST_HEAD(&wl->devlist);
3908 ssb_set_devtypedata(dev, wl);
3909 b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
3915 static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
3921 wl = ssb_get_devtypedata(dev);
3923 /* Probing the first core. Must setup common struct b43_wl */
3925 err = b43_wireless_init(dev);
3928 wl = ssb_get_devtypedata(dev);
3931 err = b43_one_core_attach(dev, wl);
3933 goto err_wireless_exit;
3936 err = ieee80211_register_hw(wl->hw);
3938 goto err_one_core_detach;
3944 err_one_core_detach:
3945 b43_one_core_detach(dev);
3948 b43_wireless_exit(dev, wl);
3952 static void b43_remove(struct ssb_device *dev)
3954 struct b43_wl *wl = ssb_get_devtypedata(dev);
3955 struct b43_wldev *wldev = ssb_get_drvdata(dev);
3958 if (wl->current_dev == wldev)
3959 ieee80211_unregister_hw(wl->hw);
3961 b43_one_core_detach(dev);
3963 if (list_empty(&wl->devlist)) {
3964 /* Last core on the chip unregistered.
3965 * We can destroy common struct b43_wl.
3967 b43_wireless_exit(dev, wl);
3971 /* Perform a hardware reset. This can be called from any context. */
3972 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
3974 /* Must avoid requeueing, if we are in shutdown. */
3975 if (b43_status(dev) < B43_STAT_INITIALIZED)
3977 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
3978 queue_work(dev->wl->hw->workqueue, &dev->restart_work);
3983 static int b43_suspend(struct ssb_device *dev, pm_message_t state)
3985 struct b43_wldev *wldev = ssb_get_drvdata(dev);
3986 struct b43_wl *wl = wldev->wl;
3988 b43dbg(wl, "Suspending...\n");
3990 mutex_lock(&wl->mutex);
3991 wldev->suspend_init_status = b43_status(wldev);
3992 if (wldev->suspend_init_status >= B43_STAT_STARTED)
3993 b43_wireless_core_stop(wldev);
3994 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED)
3995 b43_wireless_core_exit(wldev);
3996 mutex_unlock(&wl->mutex);
3998 b43dbg(wl, "Device suspended.\n");
4003 static int b43_resume(struct ssb_device *dev)
4005 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4006 struct b43_wl *wl = wldev->wl;
4009 b43dbg(wl, "Resuming...\n");
4011 mutex_lock(&wl->mutex);
4012 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
4013 err = b43_wireless_core_init(wldev);
4015 b43err(wl, "Resume failed at core init\n");
4019 if (wldev->suspend_init_status >= B43_STAT_STARTED) {
4020 err = b43_wireless_core_start(wldev);
4022 b43_wireless_core_exit(wldev);
4023 b43err(wl, "Resume failed at core start\n");
4027 mutex_unlock(&wl->mutex);
4029 b43dbg(wl, "Device resumed.\n");
4034 #else /* CONFIG_PM */
4035 # define b43_suspend NULL
4036 # define b43_resume NULL
4037 #endif /* CONFIG_PM */
4039 static struct ssb_driver b43_ssb_driver = {
4040 .name = KBUILD_MODNAME,
4041 .id_table = b43_ssb_tbl,
4043 .remove = b43_remove,
4044 .suspend = b43_suspend,
4045 .resume = b43_resume,
4048 static int __init b43_init(void)
4053 err = b43_pcmcia_init();
4056 err = ssb_driver_register(&b43_ssb_driver);
4058 goto err_pcmcia_exit;
4069 static void __exit b43_exit(void)
4071 ssb_driver_unregister(&b43_ssb_driver);
4076 module_init(b43_init)
4077 module_exit(b43_exit)