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   1 /*
   2
   3   Broadcom B43 wireless driver
   4
   5   Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
   6   Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
   7   Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
   8   Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
   9   Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
  10
  11   Some parts of the code in this file are derived from the ipw2200
  12   driver  Copyright(c) 2003 - 2004 Intel Corporation.
  13
  14   This program is free software; you can redistribute it and/or modify
  15   it under the terms of the GNU General Public License as published by
  16   the Free Software Foundation; either version 2 of the License, or
  17   (at your option) any later version.
  18
  19   This program is distributed in the hope that it will be useful,
  20   but WITHOUT ANY WARRANTY; without even the implied warranty of
  21   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22   GNU General Public License for more details.
  23
  24   You should have received a copy of the GNU General Public License
  25   along with this program; see the file COPYING.  If not, write to
  26   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  27   Boston, MA 02110-1301, USA.
  28
  29 */
  30
  31 #include <linux/delay.h>
  32 #include <linux/init.h>
  33 #include <linux/moduleparam.h>
  34 #include <linux/if_arp.h>
  35 #include <linux/etherdevice.h>
  36 #include <linux/version.h>
  37 #include <linux/firmware.h>
  38 #include <linux/wireless.h>
  39 #include <linux/workqueue.h>
  40 #include <linux/skbuff.h>
  41 #include <linux/dma-mapping.h>
  42 #include <asm/unaligned.h>
  43
  44 #include "b43.h"
  45 #include "main.h"
  46 #include "debugfs.h"
  47 #include "phy.h"
  48 #include "dma.h"
  49 #include "sysfs.h"
  50 #include "xmit.h"
  51 #include "lo.h"
  52 #include "pcmcia.h"
  53
  54 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
  55 MODULE_AUTHOR("Martin Langer");
  56 MODULE_AUTHOR("Stefano Brivio");
  57 MODULE_AUTHOR("Michael Buesch");
  58 MODULE_LICENSE("GPL");
  59
  60
  61 static int modparam_bad_frames_preempt;
  62 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
  63 MODULE_PARM_DESC(bad_frames_preempt,
  64                  "enable(1) / disable(0) Bad Frames Preemption");
  65
  66 static char modparam_fwpostfix[16];
  67 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
  68 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
  69
  70 static int modparam_hwpctl;
  71 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
  72 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
  73
  74 static int modparam_nohwcrypt;
  75 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
  76 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  77
  78 static const struct ssb_device_id b43_ssb_tbl[] = {
  79         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
  80         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
  81         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
  82         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
  83         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
  84         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
  85         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
  86         SSB_DEVTABLE_END
  87 };
  88
  89 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
  90
  91 /* Channel and ratetables are shared for all devices.
  92  * They can't be const, because ieee80211 puts some precalculated
  93  * data in there. This data is the same for all devices, so we don't
  94  * get concurrency issues */
  95 #define RATETAB_ENT(_rateid, _flags) \
  96         {                                                       \
  97                 .rate   = B43_RATE_TO_BASE100KBPS(_rateid),     \
  98                 .val    = (_rateid),                            \
  99                 .val2   = (_rateid),                            \
 100                 .flags  = (_flags),                             \
 101         }
 102 static struct ieee80211_rate __b43_ratetable[] = {
 103         RATETAB_ENT(B43_CCK_RATE_1MB, IEEE80211_RATE_CCK),
 104         RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_CCK_2),
 105         RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_CCK_2),
 106         RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_CCK_2),
 107         RATETAB_ENT(B43_OFDM_RATE_6MB, IEEE80211_RATE_OFDM),
 108         RATETAB_ENT(B43_OFDM_RATE_9MB, IEEE80211_RATE_OFDM),
 109         RATETAB_ENT(B43_OFDM_RATE_12MB, IEEE80211_RATE_OFDM),
 110         RATETAB_ENT(B43_OFDM_RATE_18MB, IEEE80211_RATE_OFDM),
 111         RATETAB_ENT(B43_OFDM_RATE_24MB, IEEE80211_RATE_OFDM),
 112         RATETAB_ENT(B43_OFDM_RATE_36MB, IEEE80211_RATE_OFDM),
 113         RATETAB_ENT(B43_OFDM_RATE_48MB, IEEE80211_RATE_OFDM),
 114         RATETAB_ENT(B43_OFDM_RATE_54MB, IEEE80211_RATE_OFDM),
 115 };
 116
 117 #define b43_a_ratetable         (__b43_ratetable + 4)
 118 #define b43_a_ratetable_size    8
 119 #define b43_b_ratetable         (__b43_ratetable + 0)
 120 #define b43_b_ratetable_size    4
 121 #define b43_g_ratetable         (__b43_ratetable + 0)
 122 #define b43_g_ratetable_size    12
 123
 124 #define CHANTAB_ENT(_chanid, _freq) \
 125         {                                                       \
 126                 .chan   = (_chanid),                            \
 127                 .freq   = (_freq),                              \
 128                 .val    = (_chanid),                            \
 129                 .flag   = IEEE80211_CHAN_W_SCAN |               \
 130                           IEEE80211_CHAN_W_ACTIVE_SCAN |        \
 131                           IEEE80211_CHAN_W_IBSS,                \
 132                 .power_level    = 0xFF,                         \
 133                 .antenna_max    = 0xFF,                         \
 134         }
 135 static struct ieee80211_channel b43_2ghz_chantable[] = {
 136         CHANTAB_ENT(1, 2412),
 137         CHANTAB_ENT(2, 2417),
 138         CHANTAB_ENT(3, 2422),
 139         CHANTAB_ENT(4, 2427),
 140         CHANTAB_ENT(5, 2432),
 141         CHANTAB_ENT(6, 2437),
 142         CHANTAB_ENT(7, 2442),
 143         CHANTAB_ENT(8, 2447),
 144         CHANTAB_ENT(9, 2452),
 145         CHANTAB_ENT(10, 2457),
 146         CHANTAB_ENT(11, 2462),
 147         CHANTAB_ENT(12, 2467),
 148         CHANTAB_ENT(13, 2472),
 149         CHANTAB_ENT(14, 2484),
 150 };
 151 #define b43_2ghz_chantable_size ARRAY_SIZE(b43_2ghz_chantable)
 152
 153 #if 0
 154 static struct ieee80211_channel b43_5ghz_chantable[] = {
 155         CHANTAB_ENT(36, 5180),
 156         CHANTAB_ENT(40, 5200),
 157         CHANTAB_ENT(44, 5220),
 158         CHANTAB_ENT(48, 5240),
 159         CHANTAB_ENT(52, 5260),
 160         CHANTAB_ENT(56, 5280),
 161         CHANTAB_ENT(60, 5300),
 162         CHANTAB_ENT(64, 5320),
 163         CHANTAB_ENT(149, 5745),
 164         CHANTAB_ENT(153, 5765),
 165         CHANTAB_ENT(157, 5785),
 166         CHANTAB_ENT(161, 5805),
 167         CHANTAB_ENT(165, 5825),
 168 };
 169 #define b43_5ghz_chantable_size ARRAY_SIZE(b43_5ghz_chantable)
 170 #endif
 171
 172 static void b43_wireless_core_exit(struct b43_wldev *dev);
 173 static int b43_wireless_core_init(struct b43_wldev *dev);
 174 static void b43_wireless_core_stop(struct b43_wldev *dev);
 175 static int b43_wireless_core_start(struct b43_wldev *dev);
 176
 177 static int b43_ratelimit(struct b43_wl *wl)
 178 {
 179         if (!wl || !wl->current_dev)
 180                 return 1;
 181         if (b43_status(wl->current_dev) < B43_STAT_STARTED)
 182                 return 1;
 183         /* We are up and running.
 184          * Ratelimit the messages to avoid DoS over the net. */
 185         return net_ratelimit();
 186 }
 187
 188 void b43info(struct b43_wl *wl, const char *fmt, ...)
 189 {
 190         va_list args;
 191
 192         if (!b43_ratelimit(wl))
 193                 return;
 194         va_start(args, fmt);
 195         printk(KERN_INFO "b43-%s: ",
 196                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
 197         vprintk(fmt, args);
 198         va_end(args);
 199 }
 200
 201 void b43err(struct b43_wl *wl, const char *fmt, ...)
 202 {
 203         va_list args;
 204
 205         if (!b43_ratelimit(wl))
 206                 return;
 207         va_start(args, fmt);
 208         printk(KERN_ERR "b43-%s ERROR: ",
 209                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
 210         vprintk(fmt, args);
 211         va_end(args);
 212 }
 213
 214 void b43warn(struct b43_wl *wl, const char *fmt, ...)
 215 {
 216         va_list args;
 217
 218         if (!b43_ratelimit(wl))
 219                 return;
 220         va_start(args, fmt);
 221         printk(KERN_WARNING "b43-%s warning: ",
 222                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
 223         vprintk(fmt, args);
 224         va_end(args);
 225 }
 226
 227 #if B43_DEBUG
 228 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
 229 {
 230         va_list args;
 231
 232         va_start(args, fmt);
 233         printk(KERN_DEBUG "b43-%s debug: ",
 234                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
 235         vprintk(fmt, args);
 236         va_end(args);
 237 }
 238 #endif /* DEBUG */
 239
 240 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
 241 {
 242         u32 macctl;
 243
 244         B43_WARN_ON(offset % 4 != 0);
 245
 246         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 247         if (macctl & B43_MACCTL_BE)
 248                 val = swab32(val);
 249
 250         b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
 251         mmiowb();
 252         b43_write32(dev, B43_MMIO_RAM_DATA, val);
 253 }
 254
 255 static inline
 256     void b43_shm_control_word(struct b43_wldev *dev, u16 routing, u16 offset)
 257 {
 258         u32 control;
 259
 260         /* "offset" is the WORD offset. */
 261
 262         control = routing;
 263         control <<= 16;
 264         control |= offset;
 265         b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
 266 }
 267
 268 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
 269 {
 270         u32 ret;
 271
 272         if (routing == B43_SHM_SHARED) {
 273                 B43_WARN_ON(offset & 0x0001);
 274                 if (offset & 0x0003) {
 275                         /* Unaligned access */
 276                         b43_shm_control_word(dev, routing, offset >> 2);
 277                         ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
 278                         ret <<= 16;
 279                         b43_shm_control_word(dev, routing, (offset >> 2) + 1);
 280                         ret |= b43_read16(dev, B43_MMIO_SHM_DATA);
 281
 282                         return ret;
 283                 }
 284                 offset >>= 2;
 285         }
 286         b43_shm_control_word(dev, routing, offset);
 287         ret = b43_read32(dev, B43_MMIO_SHM_DATA);
 288
 289         return ret;
 290 }
 291
 292 u16 b43_shm_read16(struct b43_wldev * dev, u16 routing, u16 offset)
 293 {
 294         u16 ret;
 295
 296         if (routing == B43_SHM_SHARED) {
 297                 B43_WARN_ON(offset & 0x0001);
 298                 if (offset & 0x0003) {
 299                         /* Unaligned access */
 300                         b43_shm_control_word(dev, routing, offset >> 2);
 301                         ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
 302
 303                         return ret;
 304                 }
 305                 offset >>= 2;
 306         }
 307         b43_shm_control_word(dev, routing, offset);
 308         ret = b43_read16(dev, B43_MMIO_SHM_DATA);
 309
 310         return ret;
 311 }
 312
 313 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
 314 {
 315         if (routing == B43_SHM_SHARED) {
 316                 B43_WARN_ON(offset & 0x0001);
 317                 if (offset & 0x0003) {
 318                         /* Unaligned access */
 319                         b43_shm_control_word(dev, routing, offset >> 2);
 320                         mmiowb();
 321                         b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
 322                                     (value >> 16) & 0xffff);
 323                         mmiowb();
 324                         b43_shm_control_word(dev, routing, (offset >> 2) + 1);
 325                         mmiowb();
 326                         b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
 327                         return;
 328                 }
 329                 offset >>= 2;
 330         }
 331         b43_shm_control_word(dev, routing, offset);
 332         mmiowb();
 333         b43_write32(dev, B43_MMIO_SHM_DATA, value);
 334 }
 335
 336 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
 337 {
 338         if (routing == B43_SHM_SHARED) {
 339                 B43_WARN_ON(offset & 0x0001);
 340                 if (offset & 0x0003) {
 341                         /* Unaligned access */
 342                         b43_shm_control_word(dev, routing, offset >> 2);
 343                         mmiowb();
 344                         b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
 345                         return;
 346                 }
 347                 offset >>= 2;
 348         }
 349         b43_shm_control_word(dev, routing, offset);
 350         mmiowb();
 351         b43_write16(dev, B43_MMIO_SHM_DATA, value);
 352 }
 353
 354 /* Read HostFlags */
 355 u32 b43_hf_read(struct b43_wldev * dev)
 356 {
 357         u32 ret;
 358
 359         ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
 360         ret <<= 16;
 361         ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
 362
 363         return ret;
 364 }
 365
 366 /* Write HostFlags */
 367 void b43_hf_write(struct b43_wldev *dev, u32 value)
 368 {
 369         b43_shm_write16(dev, B43_SHM_SHARED,
 370                         B43_SHM_SH_HOSTFLO, (value & 0x0000FFFF));
 371         b43_shm_write16(dev, B43_SHM_SHARED,
 372                         B43_SHM_SH_HOSTFHI, ((value & 0xFFFF0000) >> 16));
 373 }
 374
 375 void b43_tsf_read(struct b43_wldev *dev, u64 * tsf)
 376 {
 377         /* We need to be careful. As we read the TSF from multiple
 378          * registers, we should take care of register overflows.
 379          * In theory, the whole tsf read process should be atomic.
 380          * We try to be atomic here, by restaring the read process,
 381          * if any of the high registers changed (overflew).
 382          */
 383         if (dev->dev->id.revision >= 3) {
 384                 u32 low, high, high2;
 385
 386                 do {
 387                         high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
 388                         low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
 389                         high2 = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
 390                 } while (unlikely(high != high2));
 391
 392                 *tsf = high;
 393                 *tsf <<= 32;
 394                 *tsf |= low;
 395         } else {
 396                 u64 tmp;
 397                 u16 v0, v1, v2, v3;
 398                 u16 test1, test2, test3;
 399
 400                 do {
 401                         v3 = b43_read16(dev, B43_MMIO_TSF_3);
 402                         v2 = b43_read16(dev, B43_MMIO_TSF_2);
 403                         v1 = b43_read16(dev, B43_MMIO_TSF_1);
 404                         v0 = b43_read16(dev, B43_MMIO_TSF_0);
 405
 406                         test3 = b43_read16(dev, B43_MMIO_TSF_3);
 407                         test2 = b43_read16(dev, B43_MMIO_TSF_2);
 408                         test1 = b43_read16(dev, B43_MMIO_TSF_1);
 409                 } while (v3 != test3 || v2 != test2 || v1 != test1);
 410
 411                 *tsf = v3;
 412                 *tsf <<= 48;
 413                 tmp = v2;
 414                 tmp <<= 32;
 415                 *tsf |= tmp;
 416                 tmp = v1;
 417                 tmp <<= 16;
 418                 *tsf |= tmp;
 419                 *tsf |= v0;
 420         }
 421 }
 422
 423 static void b43_time_lock(struct b43_wldev *dev)
 424 {
 425         u32 macctl;
 426
 427         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 428         macctl |= B43_MACCTL_TBTTHOLD;
 429         b43_write32(dev, B43_MMIO_MACCTL, macctl);
 430         /* Commit the write */
 431         b43_read32(dev, B43_MMIO_MACCTL);
 432 }
 433
 434 static void b43_time_unlock(struct b43_wldev *dev)
 435 {
 436         u32 macctl;
 437
 438         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 439         macctl &= ~B43_MACCTL_TBTTHOLD;
 440         b43_write32(dev, B43_MMIO_MACCTL, macctl);
 441         /* Commit the write */
 442         b43_read32(dev, B43_MMIO_MACCTL);
 443 }
 444
 445 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
 446 {
 447         /* Be careful with the in-progress timer.
 448          * First zero out the low register, so we have a full
 449          * register-overflow duration to complete the operation.
 450          */
 451         if (dev->dev->id.revision >= 3) {
 452                 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
 453                 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
 454
 455                 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, 0);
 456                 mmiowb();
 457                 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, hi);
 458                 mmiowb();
 459                 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, lo);
 460         } else {
 461                 u16 v0 = (tsf & 0x000000000000FFFFULL);
 462                 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
 463                 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
 464                 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
 465
 466                 b43_write16(dev, B43_MMIO_TSF_0, 0);
 467                 mmiowb();
 468                 b43_write16(dev, B43_MMIO_TSF_3, v3);
 469                 mmiowb();
 470                 b43_write16(dev, B43_MMIO_TSF_2, v2);
 471                 mmiowb();
 472                 b43_write16(dev, B43_MMIO_TSF_1, v1);
 473                 mmiowb();
 474                 b43_write16(dev, B43_MMIO_TSF_0, v0);
 475         }
 476 }
 477
 478 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
 479 {
 480         b43_time_lock(dev);
 481         b43_tsf_write_locked(dev, tsf);
 482         b43_time_unlock(dev);
 483 }
 484
 485 static
 486 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac)
 487 {
 488         static const u8 zero_addr[ETH_ALEN] = { 0 };
 489         u16 data;
 490
 491         if (!mac)
 492                 mac = zero_addr;
 493
 494         offset |= 0x0020;
 495         b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
 496
 497         data = mac[0];
 498         data |= mac[1] << 8;
 499         b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
 500         data = mac[2];
 501         data |= mac[3] << 8;
 502         b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
 503         data = mac[4];
 504         data |= mac[5] << 8;
 505         b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
 506 }
 507
 508 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
 509 {
 510         const u8 *mac;
 511         const u8 *bssid;
 512         u8 mac_bssid[ETH_ALEN * 2];
 513         int i;
 514         u32 tmp;
 515
 516         bssid = dev->wl->bssid;
 517         mac = dev->wl->mac_addr;
 518
 519         b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
 520
 521         memcpy(mac_bssid, mac, ETH_ALEN);
 522         memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
 523
 524         /* Write our MAC address and BSSID to template ram */
 525         for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
 526                 tmp = (u32) (mac_bssid[i + 0]);
 527                 tmp |= (u32) (mac_bssid[i + 1]) << 8;
 528                 tmp |= (u32) (mac_bssid[i + 2]) << 16;
 529                 tmp |= (u32) (mac_bssid[i + 3]) << 24;
 530                 b43_ram_write(dev, 0x20 + i, tmp);
 531         }
 532 }
 533
 534 static void b43_upload_card_macaddress(struct b43_wldev *dev)
 535 {
 536         b43_write_mac_bssid_templates(dev);
 537         b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
 538 }
 539
 540 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
 541 {
 542         /* slot_time is in usec. */
 543         if (dev->phy.type != B43_PHYTYPE_G)
 544                 return;
 545         b43_write16(dev, 0x684, 510 + slot_time);
 546         b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
 547 }
 548
 549 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
 550 {
 551         b43_set_slot_time(dev, 9);
 552         dev->short_slot = 1;
 553 }
 554
 555 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
 556 {
 557         b43_set_slot_time(dev, 20);
 558         dev->short_slot = 0;
 559 }
 560
 561 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
 562  * Returns the _previously_ enabled IRQ mask.
 563  */
 564 static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask)
 565 {
 566         u32 old_mask;
 567
 568         old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
 569         b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask);
 570
 571         return old_mask;
 572 }
 573
 574 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
 575  * Returns the _previously_ enabled IRQ mask.
 576  */
 577 static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask)
 578 {
 579         u32 old_mask;
 580
 581         old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
 582         b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
 583
 584         return old_mask;
 585 }
 586
 587 /* Synchronize IRQ top- and bottom-half.
 588  * IRQs must be masked before calling this.
 589  * This must not be called with the irq_lock held.
 590  */
 591 static void b43_synchronize_irq(struct b43_wldev *dev)
 592 {
 593         synchronize_irq(dev->dev->irq);
 594         tasklet_kill(&dev->isr_tasklet);
 595 }
 596
 597 /* DummyTransmission function, as documented on
 598  * http://bcm-specs.sipsolutions.net/DummyTransmission
 599  */
 600 void b43_dummy_transmission(struct b43_wldev *dev)
 601 {
 602         struct b43_phy *phy = &dev->phy;
 603         unsigned int i, max_loop;
 604         u16 value;
 605         u32 buffer[5] = {
 606                 0x00000000,
 607                 0x00D40000,
 608                 0x00000000,
 609                 0x01000000,
 610                 0x00000000,
 611         };
 612
 613         switch (phy->type) {
 614         case B43_PHYTYPE_A:
 615                 max_loop = 0x1E;
 616                 buffer[0] = 0x000201CC;
 617                 break;
 618         case B43_PHYTYPE_B:
 619         case B43_PHYTYPE_G:
 620                 max_loop = 0xFA;
 621                 buffer[0] = 0x000B846E;
 622                 break;
 623         default:
 624                 B43_WARN_ON(1);
 625                 return;
 626         }
 627
 628         for (i = 0; i < 5; i++)
 629                 b43_ram_write(dev, i * 4, buffer[i]);
 630
 631         /* Commit writes */
 632         b43_read32(dev, B43_MMIO_MACCTL);
 633
 634         b43_write16(dev, 0x0568, 0x0000);
 635         b43_write16(dev, 0x07C0, 0x0000);
 636         value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0);
 637         b43_write16(dev, 0x050C, value);
 638         b43_write16(dev, 0x0508, 0x0000);
 639         b43_write16(dev, 0x050A, 0x0000);
 640         b43_write16(dev, 0x054C, 0x0000);
 641         b43_write16(dev, 0x056A, 0x0014);
 642         b43_write16(dev, 0x0568, 0x0826);
 643         b43_write16(dev, 0x0500, 0x0000);
 644         b43_write16(dev, 0x0502, 0x0030);
 645
 646         if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
 647                 b43_radio_write16(dev, 0x0051, 0x0017);
 648         for (i = 0x00; i < max_loop; i++) {
 649                 value = b43_read16(dev, 0x050E);
 650                 if (value & 0x0080)
 651                         break;
 652                 udelay(10);
 653         }
 654         for (i = 0x00; i < 0x0A; i++) {
 655                 value = b43_read16(dev, 0x050E);
 656                 if (value & 0x0400)
 657                         break;
 658                 udelay(10);
 659         }
 660         for (i = 0x00; i < 0x0A; i++) {
 661                 value = b43_read16(dev, 0x0690);
 662                 if (!(value & 0x0100))
 663                         break;
 664                 udelay(10);
 665         }
 666         if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
 667                 b43_radio_write16(dev, 0x0051, 0x0037);
 668 }
 669
 670 static void key_write(struct b43_wldev *dev,
 671                       u8 index, u8 algorithm, const u8 * key)
 672 {
 673         unsigned int i;
 674         u32 offset;
 675         u16 value;
 676         u16 kidx;
 677
 678         /* Key index/algo block */
 679         kidx = b43_kidx_to_fw(dev, index);
 680         value = ((kidx << 4) | algorithm);
 681         b43_shm_write16(dev, B43_SHM_SHARED,
 682                         B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
 683
 684         /* Write the key to the Key Table Pointer offset */
 685         offset = dev->ktp + (index * B43_SEC_KEYSIZE);
 686         for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
 687                 value = key[i];
 688                 value |= (u16) (key[i + 1]) << 8;
 689                 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
 690         }
 691 }
 692
 693 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr)
 694 {
 695         u32 addrtmp[2] = { 0, 0, };
 696         u8 per_sta_keys_start = 8;
 697
 698         if (b43_new_kidx_api(dev))
 699                 per_sta_keys_start = 4;
 700
 701         B43_WARN_ON(index < per_sta_keys_start);
 702         /* We have two default TX keys and possibly two default RX keys.
 703          * Physical mac 0 is mapped to physical key 4 or 8, depending
 704          * on the firmware version.
 705          * So we must adjust the index here.
 706          */
 707         index -= per_sta_keys_start;
 708
 709         if (addr) {
 710                 addrtmp[0] = addr[0];
 711                 addrtmp[0] |= ((u32) (addr[1]) << 8);
 712                 addrtmp[0] |= ((u32) (addr[2]) << 16);
 713                 addrtmp[0] |= ((u32) (addr[3]) << 24);
 714                 addrtmp[1] = addr[4];
 715                 addrtmp[1] |= ((u32) (addr[5]) << 8);
 716         }
 717
 718         if (dev->dev->id.revision >= 5) {
 719                 /* Receive match transmitter address mechanism */
 720                 b43_shm_write32(dev, B43_SHM_RCMTA,
 721                                 (index * 2) + 0, addrtmp[0]);
 722                 b43_shm_write16(dev, B43_SHM_RCMTA,
 723                                 (index * 2) + 1, addrtmp[1]);
 724         } else {
 725                 /* RXE (Receive Engine) and
 726                  * PSM (Programmable State Machine) mechanism
 727                  */
 728                 if (index < 8) {
 729                         /* TODO write to RCM 16, 19, 22 and 25 */
 730                 } else {
 731                         b43_shm_write32(dev, B43_SHM_SHARED,
 732                                         B43_SHM_SH_PSM + (index * 6) + 0,
 733                                         addrtmp[0]);
 734                         b43_shm_write16(dev, B43_SHM_SHARED,
 735                                         B43_SHM_SH_PSM + (index * 6) + 4,
 736                                         addrtmp[1]);
 737                 }
 738         }
 739 }
 740
 741 static void do_key_write(struct b43_wldev *dev,
 742                          u8 index, u8 algorithm,
 743                          const u8 * key, size_t key_len, const u8 * mac_addr)
 744 {
 745         u8 buf[B43_SEC_KEYSIZE] = { 0, };
 746         u8 per_sta_keys_start = 8;
 747
 748         if (b43_new_kidx_api(dev))
 749                 per_sta_keys_start = 4;
 750
 751         B43_WARN_ON(index >= dev->max_nr_keys);
 752         B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
 753
 754         if (index >= per_sta_keys_start)
 755                 keymac_write(dev, index, NULL); /* First zero out mac. */
 756         if (key)
 757                 memcpy(buf, key, key_len);
 758         key_write(dev, index, algorithm, buf);
 759         if (index >= per_sta_keys_start)
 760                 keymac_write(dev, index, mac_addr);
 761
 762         dev->key[index].algorithm = algorithm;
 763 }
 764
 765 static int b43_key_write(struct b43_wldev *dev,
 766                          int index, u8 algorithm,
 767                          const u8 * key, size_t key_len,
 768                          const u8 * mac_addr,
 769                          struct ieee80211_key_conf *keyconf)
 770 {
 771         int i;
 772         int sta_keys_start;
 773
 774         if (key_len > B43_SEC_KEYSIZE)
 775                 return -EINVAL;
 776         for (i = 0; i < dev->max_nr_keys; i++) {
 777                 /* Check that we don't already have this key. */
 778                 B43_WARN_ON(dev->key[i].keyconf == keyconf);
 779         }
 780         if (index < 0) {
 781                 /* Either pairwise key or address is 00:00:00:00:00:00
 782                  * for transmit-only keys. Search the index. */
 783                 if (b43_new_kidx_api(dev))
 784                         sta_keys_start = 4;
 785                 else
 786                         sta_keys_start = 8;
 787                 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
 788                         if (!dev->key[i].keyconf) {
 789                                 /* found empty */
 790                                 index = i;
 791                                 break;
 792                         }
 793                 }
 794                 if (index < 0) {
 795                         b43err(dev->wl, "Out of hardware key memory\n");
 796                         return -ENOSPC;
 797                 }
 798         } else
 799                 B43_WARN_ON(index > 3);
 800
 801         do_key_write(dev, index, algorithm, key, key_len, mac_addr);
 802         if ((index <= 3) && !b43_new_kidx_api(dev)) {
 803                 /* Default RX key */
 804                 B43_WARN_ON(mac_addr);
 805                 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
 806         }
 807         keyconf->hw_key_idx = index;
 808         dev->key[index].keyconf = keyconf;
 809
 810         return 0;
 811 }
 812
 813 static int b43_key_clear(struct b43_wldev *dev, int index)
 814 {
 815         if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys)))
 816                 return -EINVAL;
 817         do_key_write(dev, index, B43_SEC_ALGO_NONE,
 818                      NULL, B43_SEC_KEYSIZE, NULL);
 819         if ((index <= 3) && !b43_new_kidx_api(dev)) {
 820                 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
 821                              NULL, B43_SEC_KEYSIZE, NULL);
 822         }
 823         dev->key[index].keyconf = NULL;
 824
 825         return 0;
 826 }
 827
 828 static void b43_clear_keys(struct b43_wldev *dev)
 829 {
 830         int i;
 831
 832         for (i = 0; i < dev->max_nr_keys; i++)
 833                 b43_key_clear(dev, i);
 834 }
 835
 836 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
 837 {
 838         u32 macctl;
 839         u16 ucstat;
 840         bool hwps;
 841         bool awake;
 842         int i;
 843
 844         B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
 845                     (ps_flags & B43_PS_DISABLED));
 846         B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
 847
 848         if (ps_flags & B43_PS_ENABLED) {
 849                 hwps = 1;
 850         } else if (ps_flags & B43_PS_DISABLED) {
 851                 hwps = 0;
 852         } else {
 853                 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
 854                 //      and thus is not an AP and we are associated, set bit 25
 855         }
 856         if (ps_flags & B43_PS_AWAKE) {
 857                 awake = 1;
 858         } else if (ps_flags & B43_PS_ASLEEP) {
 859                 awake = 0;
 860         } else {
 861                 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
 862                 //      or we are associated, or FIXME, or the latest PS-Poll packet sent was
 863                 //      successful, set bit26
 864         }
 865
 866 /* FIXME: For now we force awake-on and hwps-off */
 867         hwps = 0;
 868         awake = 1;
 869
 870         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 871         if (hwps)
 872                 macctl |= B43_MACCTL_HWPS;
 873         else
 874                 macctl &= ~B43_MACCTL_HWPS;
 875         if (awake)
 876                 macctl |= B43_MACCTL_AWAKE;
 877         else
 878                 macctl &= ~B43_MACCTL_AWAKE;
 879         b43_write32(dev, B43_MMIO_MACCTL, macctl);
 880         /* Commit write */
 881         b43_read32(dev, B43_MMIO_MACCTL);
 882         if (awake && dev->dev->id.revision >= 5) {
 883                 /* Wait for the microcode to wake up. */
 884                 for (i = 0; i < 100; i++) {
 885                         ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
 886                                                 B43_SHM_SH_UCODESTAT);
 887                         if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
 888                                 break;
 889                         udelay(10);
 890                 }
 891         }
 892 }
 893
 894 /* Turn the Analog ON/OFF */
 895 static void b43_switch_analog(struct b43_wldev *dev, int on)
 896 {
 897         b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
 898 }
 899
 900 void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
 901 {
 902         u32 tmslow;
 903         u32 macctl;
 904
 905         flags |= B43_TMSLOW_PHYCLKEN;
 906         flags |= B43_TMSLOW_PHYRESET;
 907         ssb_device_enable(dev->dev, flags);
 908         msleep(2);              /* Wait for the PLL to turn on. */
 909
 910         /* Now take the PHY out of Reset again */
 911         tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
 912         tmslow |= SSB_TMSLOW_FGC;
 913         tmslow &= ~B43_TMSLOW_PHYRESET;
 914         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
 915         ssb_read32(dev->dev, SSB_TMSLOW);       /* flush */
 916         msleep(1);
 917         tmslow &= ~SSB_TMSLOW_FGC;
 918         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
 919         ssb_read32(dev->dev, SSB_TMSLOW);       /* flush */
 920         msleep(1);
 921
 922         /* Turn Analog ON */
 923         b43_switch_analog(dev, 1);
 924
 925         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 926         macctl &= ~B43_MACCTL_GMODE;
 927         if (flags & B43_TMSLOW_GMODE)
 928                 macctl |= B43_MACCTL_GMODE;
 929         macctl |= B43_MACCTL_IHR_ENABLED;
 930         b43_write32(dev, B43_MMIO_MACCTL, macctl);
 931 }
 932
 933 static void handle_irq_transmit_status(struct b43_wldev *dev)
 934 {
 935         u32 v0, v1;
 936         u16 tmp;
 937         struct b43_txstatus stat;
 938
 939         while (1) {
 940                 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
 941                 if (!(v0 & 0x00000001))
 942                         break;
 943                 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
 944
 945                 stat.cookie = (v0 >> 16);
 946                 stat.seq = (v1 & 0x0000FFFF);
 947                 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
 948                 tmp = (v0 & 0x0000FFFF);
 949                 stat.frame_count = ((tmp & 0xF000) >> 12);
 950                 stat.rts_count = ((tmp & 0x0F00) >> 8);
 951                 stat.supp_reason = ((tmp & 0x001C) >> 2);
 952                 stat.pm_indicated = !!(tmp & 0x0080);
 953                 stat.intermediate = !!(tmp & 0x0040);
 954                 stat.for_ampdu = !!(tmp & 0x0020);
 955                 stat.acked = !!(tmp & 0x0002);
 956
 957                 b43_handle_txstatus(dev, &stat);
 958         }
 959 }
 960
 961 static void drain_txstatus_queue(struct b43_wldev *dev)
 962 {
 963         u32 dummy;
 964
 965         if (dev->dev->id.revision < 5)
 966                 return;
 967         /* Read all entries from the microcode TXstatus FIFO
 968          * and throw them away.
 969          */
 970         while (1) {
 971                 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
 972                 if (!(dummy & 0x00000001))
 973                         break;
 974                 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
 975         }
 976 }
 977
 978 static u32 b43_jssi_read(struct b43_wldev *dev)
 979 {
 980         u32 val = 0;
 981
 982         val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
 983         val <<= 16;
 984         val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
 985
 986         return val;
 987 }
 988
 989 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
 990 {
 991         b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
 992         b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
 993 }
 994
 995 static void b43_generate_noise_sample(struct b43_wldev *dev)
 996 {
 997         b43_jssi_write(dev, 0x7F7F7F7F);
 998         b43_write32(dev, B43_MMIO_MACCMD,
 999                     b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
1000         B43_WARN_ON(dev->noisecalc.channel_at_start != dev->phy.channel);
1001 }
1002
1003 static void b43_calculate_link_quality(struct b43_wldev *dev)
1004 {
1005         /* Top half of Link Quality calculation. */
1006
1007         if (dev->noisecalc.calculation_running)
1008                 return;
1009         dev->noisecalc.channel_at_start = dev->phy.channel;
1010         dev->noisecalc.calculation_running = 1;
1011         dev->noisecalc.nr_samples = 0;
1012
1013         b43_generate_noise_sample(dev);
1014 }
1015
1016 static void handle_irq_noise(struct b43_wldev *dev)
1017 {
1018         struct b43_phy *phy = &dev->phy;
1019         u16 tmp;
1020         u8 noise[4];
1021         u8 i, j;
1022         s32 average;
1023
1024         /* Bottom half of Link Quality calculation. */
1025
1026         B43_WARN_ON(!dev->noisecalc.calculation_running);
1027         if (dev->noisecalc.channel_at_start != phy->channel)
1028                 goto drop_calculation;
1029         *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1030         if (noise[0] == 0x7F || noise[1] == 0x7F ||
1031             noise[2] == 0x7F || noise[3] == 0x7F)
1032                 goto generate_new;
1033
1034         /* Get the noise samples. */
1035         B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1036         i = dev->noisecalc.nr_samples;
1037         noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1038         noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1039         noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1040         noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1041         dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1042         dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1043         dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1044         dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1045         dev->noisecalc.nr_samples++;
1046         if (dev->noisecalc.nr_samples == 8) {
1047                 /* Calculate the Link Quality by the noise samples. */
1048                 average = 0;
1049                 for (i = 0; i < 8; i++) {
1050                         for (j = 0; j < 4; j++)
1051                                 average += dev->noisecalc.samples[i][j];
1052                 }
1053                 average /= (8 * 4);
1054                 average *= 125;
1055                 average += 64;
1056                 average /= 128;
1057                 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1058                 tmp = (tmp / 128) & 0x1F;
1059                 if (tmp >= 8)
1060                         average += 2;
1061                 else
1062                         average -= 25;
1063                 if (tmp == 8)
1064                         average -= 72;
1065                 else
1066                         average -= 48;
1067
1068                 dev->stats.link_noise = average;
1069               drop_calculation:
1070                 dev->noisecalc.calculation_running = 0;
1071                 return;
1072         }
1073       generate_new:
1074         b43_generate_noise_sample(dev);
1075 }
1076
1077 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1078 {
1079         if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
1080                 ///TODO: PS TBTT
1081         } else {
1082                 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1083                         b43_power_saving_ctl_bits(dev, 0);
1084         }
1085         if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
1086                 dev->dfq_valid = 1;
1087 }
1088
1089 static void handle_irq_atim_end(struct b43_wldev *dev)
1090 {
1091         if (dev->dfq_valid) {
1092                 b43_write32(dev, B43_MMIO_MACCMD,
1093                             b43_read32(dev, B43_MMIO_MACCMD)
1094                             | B43_MACCMD_DFQ_VALID);
1095                 dev->dfq_valid = 0;
1096         }
1097 }
1098
1099 static void handle_irq_pmq(struct b43_wldev *dev)
1100 {
1101         u32 tmp;
1102
1103         //TODO: AP mode.
1104
1105         while (1) {
1106                 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1107                 if (!(tmp & 0x00000008))
1108                         break;
1109         }
1110         /* 16bit write is odd, but correct. */
1111         b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1112 }
1113
1114 static void b43_write_template_common(struct b43_wldev *dev,
1115                                       const u8 * data, u16 size,
1116                                       u16 ram_offset,
1117                                       u16 shm_size_offset, u8 rate)
1118 {
1119         u32 i, tmp;
1120         struct b43_plcp_hdr4 plcp;
1121
1122         plcp.data = 0;
1123         b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1124         b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1125         ram_offset += sizeof(u32);
1126         /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1127          * So leave the first two bytes of the next write blank.
1128          */
1129         tmp = (u32) (data[0]) << 16;
1130         tmp |= (u32) (data[1]) << 24;
1131         b43_ram_write(dev, ram_offset, tmp);
1132         ram_offset += sizeof(u32);
1133         for (i = 2; i < size; i += sizeof(u32)) {
1134                 tmp = (u32) (data[i + 0]);
1135                 if (i + 1 < size)
1136                         tmp |= (u32) (data[i + 1]) << 8;
1137                 if (i + 2 < size)
1138                         tmp |= (u32) (data[i + 2]) << 16;
1139                 if (i + 3 < size)
1140                         tmp |= (u32) (data[i + 3]) << 24;
1141                 b43_ram_write(dev, ram_offset + i - 2, tmp);
1142         }
1143         b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1144                         size + sizeof(struct b43_plcp_hdr6));
1145 }
1146
1147 static void b43_write_beacon_template(struct b43_wldev *dev,
1148                                       u16 ram_offset,
1149                                       u16 shm_size_offset, u8 rate)
1150 {
1151         int i, len;
1152         const struct ieee80211_mgmt *bcn;
1153         const u8 *ie;
1154         bool tim_found = 0;
1155
1156         bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1157         len = min((size_t) dev->wl->current_beacon->len,
1158                   0x200 - sizeof(struct b43_plcp_hdr6));
1159
1160         b43_write_template_common(dev, (const u8 *)bcn,
1161                                   len, ram_offset, shm_size_offset, rate);
1162
1163         /* Find the position of the TIM and the DTIM_period value
1164          * and write them to SHM. */
1165         ie = bcn->u.beacon.variable;
1166         for (i = 0; i < len - 2; ) {
1167                 uint8_t ie_id, ie_len;
1168
1169                 ie_id = ie[i];
1170                 ie_len = ie[i + 1];
1171                 if (ie_id == 5) {
1172                         u16 tim_position;
1173                         u16 dtim_period;
1174                         /* This is the TIM Information Element */
1175
1176                         /* Check whether the ie_len is in the beacon data range. */
1177                         if (len < ie_len + 2 + i)
1178                                 break;
1179                         /* A valid TIM is at least 4 bytes long. */
1180                         if (ie_len < 4)
1181                                 break;
1182                         tim_found = 1;
1183
1184                         tim_position = sizeof(struct b43_plcp_hdr6);
1185                         tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1186                         tim_position += i;
1187
1188                         dtim_period = ie[i + 3];
1189
1190                         b43_shm_write16(dev, B43_SHM_SHARED,
1191                                         B43_SHM_SH_TIMBPOS, tim_position);
1192                         b43_shm_write16(dev, B43_SHM_SHARED,
1193                                         B43_SHM_SH_DTIMPER, dtim_period);
1194                         break;
1195                 }
1196                 i += ie_len + 2;
1197         }
1198         if (!tim_found) {
1199                 b43warn(dev->wl, "Did not find a valid TIM IE in "
1200                         "the beacon template packet. AP or IBSS operation "
1201                         "may be broken.\n");
1202         }
1203 }
1204
1205 static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
1206                                       u16 shm_offset, u16 size, u8 rate)
1207 {
1208         struct b43_plcp_hdr4 plcp;
1209         u32 tmp;
1210         __le16 dur;
1211
1212         plcp.data = 0;
1213         b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1214         dur = ieee80211_generic_frame_duration(dev->wl->hw,
1215                                                dev->wl->vif, size,
1216                                                B43_RATE_TO_BASE100KBPS(rate));
1217         /* Write PLCP in two parts and timing for packet transfer */
1218         tmp = le32_to_cpu(plcp.data);
1219         b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF);
1220         b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16);
1221         b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur));
1222 }
1223
1224 /* Instead of using custom probe response template, this function
1225  * just patches custom beacon template by:
1226  * 1) Changing packet type
1227  * 2) Patching duration field
1228  * 3) Stripping TIM
1229  */
1230 static const u8 * b43_generate_probe_resp(struct b43_wldev *dev,
1231                                           u16 *dest_size, u8 rate)
1232 {
1233         const u8 *src_data;
1234         u8 *dest_data;
1235         u16 src_size, elem_size, src_pos, dest_pos;
1236         __le16 dur;
1237         struct ieee80211_hdr *hdr;
1238         size_t ie_start;
1239
1240         src_size = dev->wl->current_beacon->len;
1241         src_data = (const u8 *)dev->wl->current_beacon->data;
1242
1243         /* Get the start offset of the variable IEs in the packet. */
1244         ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
1245         B43_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt, u.beacon.variable));
1246
1247         if (B43_WARN_ON(src_size < ie_start))
1248                 return NULL;
1249
1250         dest_data = kmalloc(src_size, GFP_ATOMIC);
1251         if (unlikely(!dest_data))
1252                 return NULL;
1253
1254         /* Copy the static data and all Information Elements, except the TIM. */
1255         memcpy(dest_data, src_data, ie_start);
1256         src_pos = ie_start;
1257         dest_pos = ie_start;
1258         for ( ; src_pos < src_size - 2; src_pos += elem_size) {
1259                 elem_size = src_data[src_pos + 1] + 2;
1260                 if (src_data[src_pos] == 5) {
1261                         /* This is the TIM. */
1262                         continue;
1263                 }
1264                 memcpy(dest_data + dest_pos, src_data + src_pos,
1265                        elem_size);
1266                 dest_pos += elem_size;
1267         }
1268         *dest_size = dest_pos;
1269         hdr = (struct ieee80211_hdr *)dest_data;
1270
1271         /* Set the frame control. */
1272         hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1273                                          IEEE80211_STYPE_PROBE_RESP);
1274         dur = ieee80211_generic_frame_duration(dev->wl->hw,
1275                                                dev->wl->vif, *dest_size,
1276                                                B43_RATE_TO_BASE100KBPS(rate));
1277         hdr->duration_id = dur;
1278
1279         return dest_data;
1280 }
1281
1282 static void b43_write_probe_resp_template(struct b43_wldev *dev,
1283                                           u16 ram_offset,
1284                                           u16 shm_size_offset, u8 rate)
1285 {
1286         const u8 *probe_resp_data;
1287         u16 size;
1288
1289         size = dev->wl->current_beacon->len;
1290         probe_resp_data = b43_generate_probe_resp(dev, &size, rate);
1291         if (unlikely(!probe_resp_data))
1292                 return;
1293
1294         /* Looks like PLCP headers plus packet timings are stored for
1295          * all possible basic rates
1296          */
1297         b43_write_probe_resp_plcp(dev, 0x31A, size, B43_CCK_RATE_1MB);
1298         b43_write_probe_resp_plcp(dev, 0x32C, size, B43_CCK_RATE_2MB);
1299         b43_write_probe_resp_plcp(dev, 0x33E, size, B43_CCK_RATE_5MB);
1300         b43_write_probe_resp_plcp(dev, 0x350, size, B43_CCK_RATE_11MB);
1301
1302         size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6));
1303         b43_write_template_common(dev, probe_resp_data,
1304                                   size, ram_offset, shm_size_offset, rate);
1305         kfree(probe_resp_data);
1306 }
1307
1308 /* Asynchronously update the packet templates in template RAM.
1309  * Locking: Requires wl->irq_lock to be locked. */
1310 static void b43_update_templates(struct b43_wl *wl, struct sk_buff *beacon)
1311 {
1312         /* This is the top half of the ansynchronous beacon update.
1313          * The bottom half is the beacon IRQ.
1314          * Beacon update must be asynchronous to avoid sending an
1315          * invalid beacon. This can happen for example, if the firmware
1316          * transmits a beacon while we are updating it. */
1317
1318         if (wl->current_beacon)
1319                 dev_kfree_skb_any(wl->current_beacon);
1320         wl->current_beacon = beacon;
1321         wl->beacon0_uploaded = 0;
1322         wl->beacon1_uploaded = 0;
1323 }
1324
1325 static void b43_set_ssid(struct b43_wldev *dev, const u8 * ssid, u8 ssid_len)
1326 {
1327         u32 tmp;
1328         u16 i, len;
1329
1330         len = min((u16) ssid_len, (u16) 0x100);
1331         for (i = 0; i < len; i += sizeof(u32)) {
1332                 tmp = (u32) (ssid[i + 0]);
1333                 if (i + 1 < len)
1334                         tmp |= (u32) (ssid[i + 1]) << 8;
1335                 if (i + 2 < len)
1336                         tmp |= (u32) (ssid[i + 2]) << 16;
1337                 if (i + 3 < len)
1338                         tmp |= (u32) (ssid[i + 3]) << 24;
1339                 b43_shm_write32(dev, B43_SHM_SHARED, 0x380 + i, tmp);
1340         }
1341         b43_shm_write16(dev, B43_SHM_SHARED, 0x48, len);
1342 }
1343
1344 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1345 {
1346         b43_time_lock(dev);
1347         if (dev->dev->id.revision >= 3) {
1348                 b43_write32(dev, 0x188, (beacon_int << 16));
1349         } else {
1350                 b43_write16(dev, 0x606, (beacon_int >> 6));
1351                 b43_write16(dev, 0x610, beacon_int);
1352         }
1353         b43_time_unlock(dev);
1354 }
1355
1356 static void handle_irq_beacon(struct b43_wldev *dev)
1357 {
1358         struct b43_wl *wl = dev->wl;
1359         u32 cmd;
1360
1361         if (!b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
1362                 return;
1363
1364         /* This is the bottom half of the asynchronous beacon update. */
1365
1366         cmd = b43_read32(dev, B43_MMIO_MACCMD);
1367         if (!(cmd & B43_MACCMD_BEACON0_VALID)) {
1368                 if (!wl->beacon0_uploaded) {
1369                         b43_write_beacon_template(dev, 0x68, 0x18,
1370                                                   B43_CCK_RATE_1MB);
1371                         b43_write_probe_resp_template(dev, 0x268, 0x4A,
1372                                                       B43_CCK_RATE_11MB);
1373                         wl->beacon0_uploaded = 1;
1374                 }
1375                 cmd |= B43_MACCMD_BEACON0_VALID;
1376         }
1377         if (!(cmd & B43_MACCMD_BEACON1_VALID)) {
1378                 if (!wl->beacon1_uploaded) {
1379                         b43_write_beacon_template(dev, 0x468, 0x1A,
1380                                                   B43_CCK_RATE_1MB);
1381                         wl->beacon1_uploaded = 1;
1382                 }
1383                 cmd |= B43_MACCMD_BEACON1_VALID;
1384         }
1385         b43_write32(dev, B43_MMIO_MACCMD, cmd);
1386 }
1387
1388 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1389 {
1390         //TODO
1391 }
1392
1393 /* Interrupt handler bottom-half */
1394 static void b43_interrupt_tasklet(struct b43_wldev *dev)
1395 {
1396         u32 reason;
1397         u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1398         u32 merged_dma_reason = 0;
1399         int i;
1400         unsigned long flags;
1401
1402         spin_lock_irqsave(&dev->wl->irq_lock, flags);
1403
1404         B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
1405
1406         reason = dev->irq_reason;
1407         for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1408                 dma_reason[i] = dev->dma_reason[i];
1409                 merged_dma_reason |= dma_reason[i];
1410         }
1411
1412         if (unlikely(reason & B43_IRQ_MAC_TXERR))
1413                 b43err(dev->wl, "MAC transmission error\n");
1414
1415         if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1416                 b43err(dev->wl, "PHY transmission error\n");
1417                 rmb();
1418                 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1419                         atomic_set(&dev->phy.txerr_cnt,
1420                                    B43_PHY_TX_BADNESS_LIMIT);
1421                         b43err(dev->wl, "Too many PHY TX errors, "
1422                                         "restarting the controller\n");
1423                         b43_controller_restart(dev, "PHY TX errors");
1424                 }
1425         }
1426
1427         if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1428                                           B43_DMAIRQ_NONFATALMASK))) {
1429                 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1430                         b43err(dev->wl, "Fatal DMA error: "
1431                                "0x%08X, 0x%08X, 0x%08X, "
1432                                "0x%08X, 0x%08X, 0x%08X\n",
1433                                dma_reason[0], dma_reason[1],
1434                                dma_reason[2], dma_reason[3],
1435                                dma_reason[4], dma_reason[5]);
1436                         b43_controller_restart(dev, "DMA error");
1437                         mmiowb();
1438                         spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1439                         return;
1440                 }
1441                 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1442                         b43err(dev->wl, "DMA error: "
1443                                "0x%08X, 0x%08X, 0x%08X, "
1444                                "0x%08X, 0x%08X, 0x%08X\n",
1445                                dma_reason[0], dma_reason[1],
1446                                dma_reason[2], dma_reason[3],
1447                                dma_reason[4], dma_reason[5]);
1448                 }
1449         }
1450
1451         if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1452                 handle_irq_ucode_debug(dev);
1453         if (reason & B43_IRQ_TBTT_INDI)
1454                 handle_irq_tbtt_indication(dev);
1455         if (reason & B43_IRQ_ATIM_END)
1456                 handle_irq_atim_end(dev);
1457         if (reason & B43_IRQ_BEACON)
1458                 handle_irq_beacon(dev);
1459         if (reason & B43_IRQ_PMQ)
1460                 handle_irq_pmq(dev);
1461         if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1462                 ;/* TODO */
1463         if (reason & B43_IRQ_NOISESAMPLE_OK)
1464                 handle_irq_noise(dev);
1465
1466         /* Check the DMA reason registers for received data. */
1467         if (dma_reason[0] & B43_DMAIRQ_RX_DONE)
1468                 b43_dma_rx(dev->dma.rx_ring0);
1469         if (dma_reason[3] & B43_DMAIRQ_RX_DONE)
1470                 b43_dma_rx(dev->dma.rx_ring3);
1471         B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1472         B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1473         B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1474         B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1475
1476         if (reason & B43_IRQ_TX_OK)
1477                 handle_irq_transmit_status(dev);
1478
1479         b43_interrupt_enable(dev, dev->irq_savedstate);
1480         mmiowb();
1481         spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1482 }
1483
1484 static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
1485 {
1486         b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1487
1488         b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1489         b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1490         b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1491         b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1492         b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1493         b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1494 }
1495
1496 /* Interrupt handler top-half */
1497 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1498 {
1499         irqreturn_t ret = IRQ_NONE;
1500         struct b43_wldev *dev = dev_id;
1501         u32 reason;
1502
1503         if (!dev)
1504                 return IRQ_NONE;
1505
1506         spin_lock(&dev->wl->irq_lock);
1507
1508         if (b43_status(dev) < B43_STAT_STARTED)
1509                 goto out;
1510         reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1511         if (reason == 0xffffffff)       /* shared IRQ */
1512                 goto out;
1513         ret = IRQ_HANDLED;
1514         reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1515         if (!reason)
1516                 goto out;
1517
1518         dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1519             & 0x0001DC00;
1520         dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1521             & 0x0000DC00;
1522         dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1523             & 0x0000DC00;
1524         dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1525             & 0x0001DC00;
1526         dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1527             & 0x0000DC00;
1528         dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1529             & 0x0000DC00;
1530
1531         b43_interrupt_ack(dev, reason);
1532         /* disable all IRQs. They are enabled again in the bottom half. */
1533         dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
1534         /* save the reason code and call our bottom half. */
1535         dev->irq_reason = reason;
1536         tasklet_schedule(&dev->isr_tasklet);
1537       out:
1538         mmiowb();
1539         spin_unlock(&dev->wl->irq_lock);
1540
1541         return ret;
1542 }
1543
1544 static void b43_release_firmware(struct b43_wldev *dev)
1545 {
1546         release_firmware(dev->fw.ucode);
1547         dev->fw.ucode = NULL;
1548         release_firmware(dev->fw.pcm);
1549         dev->fw.pcm = NULL;
1550         release_firmware(dev->fw.initvals);
1551         dev->fw.initvals = NULL;
1552         release_firmware(dev->fw.initvals_band);
1553         dev->fw.initvals_band = NULL;
1554 }
1555
1556 static void b43_print_fw_helptext(struct b43_wl *wl)
1557 {
1558         b43err(wl, "You must go to "
1559                "http://linuxwireless.org/en/users/Drivers/b43#devicefirmware "
1560                "and download the correct firmware (version 4).\n");
1561 }
1562
1563 static int do_request_fw(struct b43_wldev *dev,
1564                          const char *name,
1565                          const struct firmware **fw)
1566 {
1567         char path[sizeof(modparam_fwpostfix) + 32];
1568         struct b43_fw_header *hdr;
1569         u32 size;
1570         int err;
1571
1572         if (!name)
1573                 return 0;
1574
1575         snprintf(path, ARRAY_SIZE(path),
1576                  "b43%s/%s.fw",
1577                  modparam_fwpostfix, name);
1578         err = request_firmware(fw, path, dev->dev->dev);
1579         if (err) {
1580                 b43err(dev->wl, "Firmware file \"%s\" not found "
1581                        "or load failed.\n", path);
1582                 return err;
1583         }
1584         if ((*fw)->size < sizeof(struct b43_fw_header))
1585                 goto err_format;
1586         hdr = (struct b43_fw_header *)((*fw)->data);
1587         switch (hdr->type) {
1588         case B43_FW_TYPE_UCODE:
1589         case B43_FW_TYPE_PCM:
1590                 size = be32_to_cpu(hdr->size);
1591                 if (size != (*fw)->size - sizeof(struct b43_fw_header))
1592                         goto err_format;
1593                 /* fallthrough */
1594         case B43_FW_TYPE_IV:
1595                 if (hdr->ver != 1)
1596                         goto err_format;
1597                 break;
1598         default:
1599                 goto err_format;
1600         }
1601
1602         return err;
1603
1604 err_format:
1605         b43err(dev->wl, "Firmware file \"%s\" format error.\n", path);
1606         return -EPROTO;
1607 }
1608
1609 static int b43_request_firmware(struct b43_wldev *dev)
1610 {
1611         struct b43_firmware *fw = &dev->fw;
1612         const u8 rev = dev->dev->id.revision;
1613         const char *filename;
1614         u32 tmshigh;
1615         int err;
1616
1617         tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
1618         if (!fw->ucode) {
1619                 if ((rev >= 5) && (rev <= 10))
1620                         filename = "ucode5";
1621                 else if ((rev >= 11) && (rev <= 12))
1622                         filename = "ucode11";
1623                 else if (rev >= 13)
1624                         filename = "ucode13";
1625                 else
1626                         goto err_no_ucode;
1627                 err = do_request_fw(dev, filename, &fw->ucode);
1628                 if (err)
1629                         goto err_load;
1630         }
1631         if (!fw->pcm) {
1632                 if ((rev >= 5) && (rev <= 10))
1633                         filename = "pcm5";
1634                 else if (rev >= 11)
1635                         filename = NULL;
1636                 else
1637                         goto err_no_pcm;
1638                 err = do_request_fw(dev, filename, &fw->pcm);
1639                 if (err)
1640                         goto err_load;
1641         }
1642         if (!fw->initvals) {
1643                 switch (dev->phy.type) {
1644                 case B43_PHYTYPE_A:
1645                         if ((rev >= 5) && (rev <= 10)) {
1646                                 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
1647                                         filename = "a0g1initvals5";
1648                                 else
1649                                         filename = "a0g0initvals5";
1650                         } else
1651                                 goto err_no_initvals;
1652                         break;
1653                 case B43_PHYTYPE_G:
1654                         if ((rev >= 5) && (rev <= 10))
1655                                 filename = "b0g0initvals5";
1656                         else if (rev >= 13)
1657                                 filename = "lp0initvals13";
1658                         else
1659                                 goto err_no_initvals;
1660                         break;
1661                 default:
1662                         goto err_no_initvals;
1663                 }
1664                 err = do_request_fw(dev, filename, &fw->initvals);
1665                 if (err)
1666                         goto err_load;
1667         }
1668         if (!fw->initvals_band) {
1669                 switch (dev->phy.type) {
1670                 case B43_PHYTYPE_A:
1671                         if ((rev >= 5) && (rev <= 10)) {
1672                                 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
1673                                         filename = "a0g1bsinitvals5";
1674                                 else
1675                                         filename = "a0g0bsinitvals5";
1676                         } else if (rev >= 11)
1677                                 filename = NULL;
1678                         else
1679                                 goto err_no_initvals;
1680                         break;
1681                 case B43_PHYTYPE_G:
1682                         if ((rev >= 5) && (rev <= 10))
1683                                 filename = "b0g0bsinitvals5";
1684                         else if (rev >= 11)
1685                                 filename = NULL;
1686                         else
1687                                 goto err_no_initvals;
1688                         break;
1689                 default:
1690                         goto err_no_initvals;
1691                 }
1692                 err = do_request_fw(dev, filename, &fw->initvals_band);
1693                 if (err)
1694                         goto err_load;
1695         }
1696
1697         return 0;
1698
1699 err_load:
1700         b43_print_fw_helptext(dev->wl);
1701         goto error;
1702
1703 err_no_ucode:
1704         err = -ENODEV;
1705         b43err(dev->wl, "No microcode available for core rev %u\n", rev);
1706         goto error;
1707
1708 err_no_pcm:
1709         err = -ENODEV;
1710         b43err(dev->wl, "No PCM available for core rev %u\n", rev);
1711         goto error;
1712
1713 err_no_initvals:
1714         err = -ENODEV;
1715         b43err(dev->wl, "No Initial Values firmware file for PHY %u, "
1716                "core rev %u\n", dev->phy.type, rev);
1717         goto error;
1718
1719 error:
1720         b43_release_firmware(dev);
1721         return err;
1722 }
1723
1724 static int b43_upload_microcode(struct b43_wldev *dev)
1725 {
1726         const size_t hdr_len = sizeof(struct b43_fw_header);
1727         const __be32 *data;
1728         unsigned int i, len;
1729         u16 fwrev, fwpatch, fwdate, fwtime;
1730         u32 tmp;
1731         int err = 0;
1732
1733         /* Upload Microcode. */
1734         data = (__be32 *) (dev->fw.ucode->data + hdr_len);
1735         len = (dev->fw.ucode->size - hdr_len) / sizeof(__be32);
1736         b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
1737         for (i = 0; i < len; i++) {
1738                 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1739                 udelay(10);
1740         }
1741
1742         if (dev->fw.pcm) {
1743                 /* Upload PCM data. */
1744                 data = (__be32 *) (dev->fw.pcm->data + hdr_len);
1745                 len = (dev->fw.pcm->size - hdr_len) / sizeof(__be32);
1746                 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
1747                 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
1748                 /* No need for autoinc bit in SHM_HW */
1749                 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
1750                 for (i = 0; i < len; i++) {
1751                         b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1752                         udelay(10);
1753                 }
1754         }
1755
1756         b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1757         b43_write32(dev, B43_MMIO_MACCTL,
1758                     B43_MACCTL_PSM_RUN |
1759                     B43_MACCTL_IHR_ENABLED | B43_MACCTL_INFRA);
1760
1761         /* Wait for the microcode to load and respond */
1762         i = 0;
1763         while (1) {
1764                 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1765                 if (tmp == B43_IRQ_MAC_SUSPENDED)
1766                         break;
1767                 i++;
1768                 if (i >= 50) {
1769                         b43err(dev->wl, "Microcode not responding\n");
1770                         b43_print_fw_helptext(dev->wl);
1771                         err = -ENODEV;
1772                         goto out;
1773                 }
1774                 udelay(10);
1775         }
1776         b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);       /* dummy read */
1777
1778         /* Get and check the revisions. */
1779         fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
1780         fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
1781         fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
1782         fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
1783
1784         if (fwrev <= 0x128) {
1785                 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
1786                        "binary drivers older than version 4.x is unsupported. "
1787                        "You must upgrade your firmware files.\n");
1788                 b43_print_fw_helptext(dev->wl);
1789                 b43_write32(dev, B43_MMIO_MACCTL, 0);
1790                 err = -EOPNOTSUPP;
1791                 goto out;
1792         }
1793         b43dbg(dev->wl, "Loading firmware version %u.%u "
1794                "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
1795                fwrev, fwpatch,
1796                (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
1797                (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
1798
1799         dev->fw.rev = fwrev;
1800         dev->fw.patch = fwpatch;
1801
1802       out:
1803         return err;
1804 }
1805
1806 static int b43_write_initvals(struct b43_wldev *dev,
1807                               const struct b43_iv *ivals,
1808                               size_t count,
1809                               size_t array_size)
1810 {
1811         const struct b43_iv *iv;
1812         u16 offset;
1813         size_t i;
1814         bool bit32;
1815
1816         BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
1817         iv = ivals;
1818         for (i = 0; i < count; i++) {
1819                 if (array_size < sizeof(iv->offset_size))
1820                         goto err_format;
1821                 array_size -= sizeof(iv->offset_size);
1822                 offset = be16_to_cpu(iv->offset_size);
1823                 bit32 = !!(offset & B43_IV_32BIT);
1824                 offset &= B43_IV_OFFSET_MASK;
1825                 if (offset >= 0x1000)
1826                         goto err_format;
1827                 if (bit32) {
1828                         u32 value;
1829
1830                         if (array_size < sizeof(iv->data.d32))
1831                                 goto err_format;
1832                         array_size -= sizeof(iv->data.d32);
1833
1834                         value = be32_to_cpu(get_unaligned(&iv->data.d32));
1835                         b43_write32(dev, offset, value);
1836
1837                         iv = (const struct b43_iv *)((const uint8_t *)iv +
1838                                                         sizeof(__be16) +
1839                                                         sizeof(__be32));
1840                 } else {
1841                         u16 value;
1842
1843                         if (array_size < sizeof(iv->data.d16))
1844                                 goto err_format;
1845                         array_size -= sizeof(iv->data.d16);
1846
1847                         value = be16_to_cpu(iv->data.d16);
1848                         b43_write16(dev, offset, value);
1849
1850                         iv = (const struct b43_iv *)((const uint8_t *)iv +
1851                                                         sizeof(__be16) +
1852                                                         sizeof(__be16));
1853                 }
1854         }
1855         if (array_size)
1856                 goto err_format;
1857
1858         return 0;
1859
1860 err_format:
1861         b43err(dev->wl, "Initial Values Firmware file-format error.\n");
1862         b43_print_fw_helptext(dev->wl);
1863
1864         return -EPROTO;
1865 }
1866
1867 static int b43_upload_initvals(struct b43_wldev *dev)
1868 {
1869         const size_t hdr_len = sizeof(struct b43_fw_header);
1870         const struct b43_fw_header *hdr;
1871         struct b43_firmware *fw = &dev->fw;
1872         const struct b43_iv *ivals;
1873         size_t count;
1874         int err;
1875
1876         hdr = (const struct b43_fw_header *)(fw->initvals->data);
1877         ivals = (const struct b43_iv *)(fw->initvals->data + hdr_len);
1878         count = be32_to_cpu(hdr->size);
1879         err = b43_write_initvals(dev, ivals, count,
1880                                  fw->initvals->size - hdr_len);
1881         if (err)
1882                 goto out;
1883         if (fw->initvals_band) {
1884                 hdr = (const struct b43_fw_header *)(fw->initvals_band->data);
1885                 ivals = (const struct b43_iv *)(fw->initvals_band->data + hdr_len);
1886                 count = be32_to_cpu(hdr->size);
1887                 err = b43_write_initvals(dev, ivals, count,
1888                                          fw->initvals_band->size - hdr_len);
1889                 if (err)
1890                         goto out;
1891         }
1892 out:
1893
1894         return err;
1895 }
1896
1897 /* Initialize the GPIOs
1898  * http://bcm-specs.sipsolutions.net/GPIO
1899  */
1900 static int b43_gpio_init(struct b43_wldev *dev)
1901 {
1902         struct ssb_bus *bus = dev->dev->bus;
1903         struct ssb_device *gpiodev, *pcidev = NULL;
1904         u32 mask, set;
1905
1906         b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
1907                     & ~B43_MACCTL_GPOUTSMSK);
1908
1909         b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
1910                     | 0x000F);
1911
1912         mask = 0x0000001F;
1913         set = 0x0000000F;
1914         if (dev->dev->bus->chip_id == 0x4301) {
1915                 mask |= 0x0060;
1916                 set |= 0x0060;
1917         }
1918         if (0 /* FIXME: conditional unknown */ ) {
1919                 b43_write16(dev, B43_MMIO_GPIO_MASK,
1920                             b43_read16(dev, B43_MMIO_GPIO_MASK)
1921                             | 0x0100);
1922                 mask |= 0x0180;
1923                 set |= 0x0180;
1924         }
1925         if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
1926                 b43_write16(dev, B43_MMIO_GPIO_MASK,
1927                             b43_read16(dev, B43_MMIO_GPIO_MASK)
1928                             | 0x0200);
1929                 mask |= 0x0200;
1930                 set |= 0x0200;
1931         }
1932         if (dev->dev->id.revision >= 2)
1933                 mask |= 0x0010; /* FIXME: This is redundant. */
1934
1935 #ifdef CONFIG_SSB_DRIVER_PCICORE
1936         pcidev = bus->pcicore.dev;
1937 #endif
1938         gpiodev = bus->chipco.dev ? : pcidev;
1939         if (!gpiodev)
1940                 return 0;
1941         ssb_write32(gpiodev, B43_GPIO_CONTROL,
1942                     (ssb_read32(gpiodev, B43_GPIO_CONTROL)
1943                      & mask) | set);
1944
1945         return 0;
1946 }
1947
1948 /* Turn off all GPIO stuff. Call this on module unload, for example. */
1949 static void b43_gpio_cleanup(struct b43_wldev *dev)
1950 {
1951         struct ssb_bus *bus = dev->dev->bus;
1952         struct ssb_device *gpiodev, *pcidev = NULL;
1953
1954 #ifdef CONFIG_SSB_DRIVER_PCICORE
1955         pcidev = bus->pcicore.dev;
1956 #endif
1957         gpiodev = bus->chipco.dev ? : pcidev;
1958         if (!gpiodev)
1959                 return;
1960         ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
1961 }
1962
1963 /* http://bcm-specs.sipsolutions.net/EnableMac */
1964 void b43_mac_enable(struct b43_wldev *dev)
1965 {
1966         dev->mac_suspended--;
1967         B43_WARN_ON(dev->mac_suspended < 0);
1968         B43_WARN_ON(irqs_disabled());
1969         if (dev->mac_suspended == 0) {
1970                 b43_write32(dev, B43_MMIO_MACCTL,
1971                             b43_read32(dev, B43_MMIO_MACCTL)
1972                             | B43_MACCTL_ENABLED);
1973                 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
1974                             B43_IRQ_MAC_SUSPENDED);
1975                 /* Commit writes */
1976                 b43_read32(dev, B43_MMIO_MACCTL);
1977                 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1978                 b43_power_saving_ctl_bits(dev, 0);
1979
1980                 /* Re-enable IRQs. */
1981                 spin_lock_irq(&dev->wl->irq_lock);
1982                 b43_interrupt_enable(dev, dev->irq_savedstate);
1983                 spin_unlock_irq(&dev->wl->irq_lock);
1984         }
1985 }
1986
1987 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
1988 void b43_mac_suspend(struct b43_wldev *dev)
1989 {
1990         int i;
1991         u32 tmp;
1992
1993         might_sleep();
1994         B43_WARN_ON(irqs_disabled());
1995         B43_WARN_ON(dev->mac_suspended < 0);
1996
1997         if (dev->mac_suspended == 0) {
1998                 /* Mask IRQs before suspending MAC. Otherwise
1999                  * the MAC stays busy and won't suspend. */
2000                 spin_lock_irq(&dev->wl->irq_lock);
2001                 tmp = b43_interrupt_disable(dev, B43_IRQ_ALL);
2002                 spin_unlock_irq(&dev->wl->irq_lock);
2003                 b43_synchronize_irq(dev);
2004                 dev->irq_savedstate = tmp;
2005
2006                 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2007                 b43_write32(dev, B43_MMIO_MACCTL,
2008                             b43_read32(dev, B43_MMIO_MACCTL)
2009                             & ~B43_MACCTL_ENABLED);
2010                 /* force pci to flush the write */
2011                 b43_read32(dev, B43_MMIO_MACCTL);
2012                 for (i = 40; i; i--) {
2013                         tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2014                         if (tmp & B43_IRQ_MAC_SUSPENDED)
2015                                 goto out;
2016                         msleep(1);
2017                 }
2018                 b43err(dev->wl, "MAC suspend failed\n");
2019         }
2020 out:
2021         dev->mac_suspended++;
2022 }
2023
2024 static void b43_adjust_opmode(struct b43_wldev *dev)
2025 {
2026         struct b43_wl *wl = dev->wl;
2027         u32 ctl;
2028         u16 cfp_pretbtt;
2029
2030         ctl = b43_read32(dev, B43_MMIO_MACCTL);
2031         /* Reset status to STA infrastructure mode. */
2032         ctl &= ~B43_MACCTL_AP;
2033         ctl &= ~B43_MACCTL_KEEP_CTL;
2034         ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2035         ctl &= ~B43_MACCTL_KEEP_BAD;
2036         ctl &= ~B43_MACCTL_PROMISC;
2037         ctl &= ~B43_MACCTL_BEACPROMISC;
2038         ctl |= B43_MACCTL_INFRA;
2039
2040         if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2041                 ctl |= B43_MACCTL_AP;
2042         else if (b43_is_mode(wl, IEEE80211_IF_TYPE_IBSS))
2043                 ctl &= ~B43_MACCTL_INFRA;
2044
2045         if (wl->filter_flags & FIF_CONTROL)
2046                 ctl |= B43_MACCTL_KEEP_CTL;
2047         if (wl->filter_flags & FIF_FCSFAIL)
2048                 ctl |= B43_MACCTL_KEEP_BAD;
2049         if (wl->filter_flags & FIF_PLCPFAIL)
2050                 ctl |= B43_MACCTL_KEEP_BADPLCP;
2051         if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2052                 ctl |= B43_MACCTL_PROMISC;
2053         if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2054                 ctl |= B43_MACCTL_BEACPROMISC;
2055
2056         /* Workaround: On old hardware the HW-MAC-address-filter
2057          * doesn't work properly, so always run promisc in filter
2058          * it in software. */
2059         if (dev->dev->id.revision <= 4)
2060                 ctl |= B43_MACCTL_PROMISC;
2061
2062         b43_write32(dev, B43_MMIO_MACCTL, ctl);
2063
2064         cfp_pretbtt = 2;
2065         if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2066                 if (dev->dev->bus->chip_id == 0x4306 &&
2067                     dev->dev->bus->chip_rev == 3)
2068                         cfp_pretbtt = 100;
2069                 else
2070                         cfp_pretbtt = 50;
2071         }
2072         b43_write16(dev, 0x612, cfp_pretbtt);
2073 }
2074
2075 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2076 {
2077         u16 offset;
2078
2079         if (is_ofdm) {
2080                 offset = 0x480;
2081                 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2082         } else {
2083                 offset = 0x4C0;
2084                 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2085         }
2086         b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2087                         b43_shm_read16(dev, B43_SHM_SHARED, offset));
2088 }
2089
2090 static void b43_rate_memory_init(struct b43_wldev *dev)
2091 {
2092         switch (dev->phy.type) {
2093         case B43_PHYTYPE_A:
2094         case B43_PHYTYPE_G:
2095                 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2096                 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2097                 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2098                 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2099                 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2100                 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2101                 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2102                 if (dev->phy.type == B43_PHYTYPE_A)
2103                         break;
2104                 /* fallthrough */
2105         case B43_PHYTYPE_B:
2106                 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2107                 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2108                 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2109                 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2110                 break;
2111         default:
2112                 B43_WARN_ON(1);
2113         }
2114 }
2115
2116 /* Set the TX-Antenna for management frames sent by firmware. */
2117 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2118 {
2119         u16 ant = 0;
2120         u16 tmp;
2121
2122         switch (antenna) {
2123         case B43_ANTENNA0:
2124                 ant |= B43_TX4_PHY_ANT0;
2125                 break;
2126         case B43_ANTENNA1:
2127                 ant |= B43_TX4_PHY_ANT1;
2128                 break;
2129         case B43_ANTENNA_AUTO:
2130                 ant |= B43_TX4_PHY_ANTLAST;
2131                 break;
2132         default:
2133                 B43_WARN_ON(1);
2134         }
2135
2136         /* FIXME We also need to set the other flags of the PHY control field somewhere. */
2137
2138         /* For Beacons */
2139         tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
2140         tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2141         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, tmp);
2142         /* For ACK/CTS */
2143         tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
2144         tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2145         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2146         /* For Probe Resposes */
2147         tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
2148         tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2149         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2150 }
2151
2152 /* This is the opposite of b43_chip_init() */
2153 static void b43_chip_exit(struct b43_wldev *dev)
2154 {
2155         b43_radio_turn_off(dev, 1);
2156         b43_gpio_cleanup(dev);
2157         /* firmware is released later */
2158 }
2159
2160 /* Initialize the chip
2161  * http://bcm-specs.sipsolutions.net/ChipInit
2162  */
2163 static int b43_chip_init(struct b43_wldev *dev)
2164 {
2165         struct b43_phy *phy = &dev->phy;
2166         int err, tmp;
2167         u32 value32;
2168         u16 value16;
2169
2170         b43_write32(dev, B43_MMIO_MACCTL,
2171                     B43_MACCTL_PSM_JMP0 | B43_MACCTL_IHR_ENABLED);
2172
2173         err = b43_request_firmware(dev);
2174         if (err)
2175                 goto out;
2176         err = b43_upload_microcode(dev);
2177         if (err)
2178                 goto out;       /* firmware is released later */
2179
2180         err = b43_gpio_init(dev);
2181         if (err)
2182                 goto out;       /* firmware is released later */
2183
2184         err = b43_upload_initvals(dev);
2185         if (err)
2186                 goto err_gpio_clean;
2187         b43_radio_turn_on(dev);
2188
2189         b43_write16(dev, 0x03E6, 0x0000);
2190         err = b43_phy_init(dev);
2191         if (err)
2192                 goto err_radio_off;
2193
2194         /* Select initial Interference Mitigation. */
2195         tmp = phy->interfmode;
2196         phy->interfmode = B43_INTERFMODE_NONE;
2197         b43_radio_set_interference_mitigation(dev, tmp);
2198
2199         b43_set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2200         b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2201
2202         if (phy->type == B43_PHYTYPE_B) {
2203                 value16 = b43_read16(dev, 0x005E);
2204                 value16 |= 0x0004;
2205                 b43_write16(dev, 0x005E, value16);
2206         }
2207         b43_write32(dev, 0x0100, 0x01000000);
2208         if (dev->dev->id.revision < 5)
2209                 b43_write32(dev, 0x010C, 0x01000000);
2210
2211         b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2212                     & ~B43_MACCTL_INFRA);
2213         b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2214                     | B43_MACCTL_INFRA);
2215
2216         /* Probe Response Timeout value */
2217         /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2218         b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2219
2220         /* Initially set the wireless operation mode. */
2221         b43_adjust_opmode(dev);
2222
2223         if (dev->dev->id.revision < 3) {
2224                 b43_write16(dev, 0x060E, 0x0000);
2225                 b43_write16(dev, 0x0610, 0x8000);
2226                 b43_write16(dev, 0x0604, 0x0000);
2227                 b43_write16(dev, 0x0606, 0x0200);
2228         } else {
2229                 b43_write32(dev, 0x0188, 0x80000000);
2230                 b43_write32(dev, 0x018C, 0x02000000);
2231         }
2232         b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2233         b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2234         b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2235         b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2236         b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2237         b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2238         b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2239
2240         value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2241         value32 |= 0x00100000;
2242         ssb_write32(dev->dev, SSB_TMSLOW, value32);
2243
2244         b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2245                     dev->dev->bus->chipco.fast_pwrup_delay);
2246
2247         err = 0;
2248         b43dbg(dev->wl, "Chip initialized\n");
2249 out:
2250         return err;
2251
2252 err_radio_off:
2253         b43_radio_turn_off(dev, 1);
2254 err_gpio_clean:
2255         b43_gpio_cleanup(dev);
2256         return err;
2257 }
2258
2259 static void b43_periodic_every120sec(struct b43_wldev *dev)
2260 {
2261         struct b43_phy *phy = &dev->phy;
2262
2263         if (phy->type != B43_PHYTYPE_G || phy->rev < 2)
2264                 return;
2265
2266         b43_mac_suspend(dev);
2267         b43_lo_g_measure(dev);
2268         b43_mac_enable(dev);
2269         if (b43_has_hardware_pctl(phy))
2270                 b43_lo_g_ctl_mark_all_unused(dev);
2271 }
2272
2273 static void b43_periodic_every60sec(struct b43_wldev *dev)
2274 {
2275         struct b43_phy *phy = &dev->phy;
2276
2277         if (!b43_has_hardware_pctl(phy))
2278                 b43_lo_g_ctl_mark_all_unused(dev);
2279         if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI) {
2280                 b43_mac_suspend(dev);
2281                 b43_calc_nrssi_slope(dev);
2282                 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) {
2283                         u8 old_chan = phy->channel;
2284
2285                         /* VCO Calibration */
2286                         if (old_chan >= 8)
2287                                 b43_radio_selectchannel(dev, 1, 0);
2288                         else
2289                                 b43_radio_selectchannel(dev, 13, 0);
2290                         b43_radio_selectchannel(dev, old_chan, 0);
2291                 }
2292                 b43_mac_enable(dev);
2293         }
2294 }
2295
2296 static void b43_periodic_every30sec(struct b43_wldev *dev)
2297 {
2298         /* Update device statistics. */
2299         b43_calculate_link_quality(dev);
2300 }
2301
2302 static void b43_periodic_every15sec(struct b43_wldev *dev)
2303 {
2304         struct b43_phy *phy = &dev->phy;
2305
2306         if (phy->type == B43_PHYTYPE_G) {
2307                 //TODO: update_aci_moving_average
2308                 if (phy->aci_enable && phy->aci_wlan_automatic) {
2309                         b43_mac_suspend(dev);
2310                         if (!phy->aci_enable && 1 /*TODO: not scanning? */ ) {
2311                                 if (0 /*TODO: bunch of conditions */ ) {
2312                                         b43_radio_set_interference_mitigation
2313                                             (dev, B43_INTERFMODE_MANUALWLAN);
2314                                 }
2315                         } else if (1 /*TODO*/) {
2316                                 /*
2317                                    if ((aci_average > 1000) && !(b43_radio_aci_scan(dev))) {
2318                                    b43_radio_set_interference_mitigation(dev,
2319                                    B43_INTERFMODE_NONE);
2320                                    }
2321                                  */
2322                         }
2323                         b43_mac_enable(dev);
2324                 } else if (phy->interfmode == B43_INTERFMODE_NONWLAN &&
2325                            phy->rev == 1) {
2326                         //TODO: implement rev1 workaround
2327                 }
2328         }
2329         b43_phy_xmitpower(dev); //FIXME: unless scanning?
2330         //TODO for APHY (temperature?)
2331
2332         atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2333         wmb();
2334 }
2335
2336 static void do_periodic_work(struct b43_wldev *dev)
2337 {
2338         unsigned int state;
2339
2340         state = dev->periodic_state;
2341         if (state % 8 == 0)
2342                 b43_periodic_every120sec(dev);
2343         if (state % 4 == 0)
2344                 b43_periodic_every60sec(dev);
2345         if (state % 2 == 0)
2346                 b43_periodic_every30sec(dev);
2347         b43_periodic_every15sec(dev);
2348 }
2349
2350 /* Periodic work locking policy:
2351  *      The whole periodic work handler is protected by
2352  *      wl->mutex. If another lock is needed somewhere in the
2353  *      pwork callchain, it's aquired in-place, where it's needed.
2354  */
2355 static void b43_periodic_work_handler(struct work_struct *work)
2356 {
2357         struct b43_wldev *dev = container_of(work, struct b43_wldev,
2358                                              periodic_work.work);
2359         struct b43_wl *wl = dev->wl;
2360         unsigned long delay;
2361
2362         mutex_lock(&wl->mutex);
2363
2364         if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2365                 goto out;
2366         if (b43_debug(dev, B43_DBG_PWORK_STOP))
2367                 goto out_requeue;
2368
2369         do_periodic_work(dev);
2370
2371         dev->periodic_state++;
2372 out_requeue:
2373         if (b43_debug(dev, B43_DBG_PWORK_FAST))
2374                 delay = msecs_to_jiffies(50);
2375         else
2376                 delay = round_jiffies_relative(HZ * 15);
2377         queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
2378 out:
2379         mutex_unlock(&wl->mutex);
2380 }
2381
2382 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2383 {
2384         struct delayed_work *work = &dev->periodic_work;
2385
2386         dev->periodic_state = 0;
2387         INIT_DELAYED_WORK(work, b43_periodic_work_handler);
2388         queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2389 }
2390
2391 /* Check if communication with the device works correctly. */
2392 static int b43_validate_chipaccess(struct b43_wldev *dev)
2393 {
2394         u32 v, backup;
2395
2396         backup = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2397
2398         /* Check for read/write and endianness problems. */
2399         b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2400         if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2401                 goto error;
2402         b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2403         if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
2404                 goto error;
2405
2406         b43_shm_write32(dev, B43_SHM_SHARED, 0, backup);
2407
2408         if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
2409                 /* The 32bit register shadows the two 16bit registers
2410                  * with update sideeffects. Validate this. */
2411                 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
2412                 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
2413                 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
2414                         goto error;
2415                 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
2416                         goto error;
2417         }
2418         b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
2419
2420         v = b43_read32(dev, B43_MMIO_MACCTL);
2421         v |= B43_MACCTL_GMODE;
2422         if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
2423                 goto error;
2424
2425         return 0;
2426 error:
2427         b43err(dev->wl, "Failed to validate the chipaccess\n");
2428         return -ENODEV;
2429 }
2430
2431 static void b43_security_init(struct b43_wldev *dev)
2432 {
2433         dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2434         B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2435         dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
2436         /* KTP is a word address, but we address SHM bytewise.
2437          * So multiply by two.
2438          */
2439         dev->ktp *= 2;
2440         if (dev->dev->id.revision >= 5) {
2441                 /* Number of RCMTA address slots */
2442                 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8);
2443         }
2444         b43_clear_keys(dev);
2445 }
2446
2447 static int b43_rng_read(struct hwrng *rng, u32 * data)
2448 {
2449         struct b43_wl *wl = (struct b43_wl *)rng->priv;
2450         unsigned long flags;
2451
2452         /* Don't take wl->mutex here, as it could deadlock with
2453          * hwrng internal locking. It's not needed to take
2454          * wl->mutex here, anyway. */
2455
2456         spin_lock_irqsave(&wl->irq_lock, flags);
2457         *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
2458         spin_unlock_irqrestore(&wl->irq_lock, flags);
2459
2460         return (sizeof(u16));
2461 }
2462
2463 static void b43_rng_exit(struct b43_wl *wl)
2464 {
2465         if (wl->rng_initialized)
2466                 hwrng_unregister(&wl->rng);
2467 }
2468
2469 static int b43_rng_init(struct b43_wl *wl)
2470 {
2471         int err;
2472
2473         snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2474                  "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2475         wl->rng.name = wl->rng_name;
2476         wl->rng.data_read = b43_rng_read;
2477         wl->rng.priv = (unsigned long)wl;
2478         wl->rng_initialized = 1;
2479         err = hwrng_register(&wl->rng);
2480         if (err) {
2481                 wl->rng_initialized = 0;
2482                 b43err(wl, "Failed to register the random "
2483                        "number generator (%d)\n", err);
2484         }
2485
2486         return err;
2487 }
2488
2489 static int b43_op_tx(struct ieee80211_hw *hw,
2490                      struct sk_buff *skb,
2491                      struct ieee80211_tx_control *ctl)
2492 {
2493         struct b43_wl *wl = hw_to_b43_wl(hw);
2494         struct b43_wldev *dev = wl->current_dev;
2495         int err = -ENODEV;
2496
2497         if (unlikely(!dev))
2498                 goto out;
2499         if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2500                 goto out;
2501         /* DMA-TX is done without a global lock. */
2502         err = b43_dma_tx(dev, skb, ctl);
2503 out:
2504         if (unlikely(err))
2505                 return NETDEV_TX_BUSY;
2506         return NETDEV_TX_OK;
2507 }
2508
2509 static int b43_op_conf_tx(struct ieee80211_hw *hw,
2510                           int queue,
2511                           const struct ieee80211_tx_queue_params *params)
2512 {
2513         return 0;
2514 }
2515
2516 static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
2517                                struct ieee80211_tx_queue_stats *stats)
2518 {
2519         struct b43_wl *wl = hw_to_b43_wl(hw);
2520         struct b43_wldev *dev = wl->current_dev;
2521         unsigned long flags;
2522         int err = -ENODEV;
2523
2524         if (!dev)
2525                 goto out;
2526         spin_lock_irqsave(&wl->irq_lock, flags);
2527         if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
2528                 b43_dma_get_tx_stats(dev, stats);
2529                 err = 0;
2530         }
2531         spin_unlock_irqrestore(&wl->irq_lock, flags);
2532 out:
2533         return err;
2534 }
2535
2536 static int b43_op_get_stats(struct ieee80211_hw *hw,
2537                             struct ieee80211_low_level_stats *stats)
2538 {
2539         struct b43_wl *wl = hw_to_b43_wl(hw);
2540         unsigned long flags;
2541
2542         spin_lock_irqsave(&wl->irq_lock, flags);
2543         memcpy(stats, &wl->ieee_stats, sizeof(*stats));
2544         spin_unlock_irqrestore(&wl->irq_lock, flags);
2545
2546         return 0;
2547 }
2548
2549 static const char *phymode_to_string(unsigned int phymode)
2550 {
2551         switch (phymode) {
2552         case B43_PHYMODE_A:
2553                 return "A";
2554         case B43_PHYMODE_B:
2555                 return "B";
2556         case B43_PHYMODE_G:
2557                 return "G";
2558         default:
2559                 B43_WARN_ON(1);
2560         }
2561         return "";
2562 }
2563
2564 static int find_wldev_for_phymode(struct b43_wl *wl,
2565                                   unsigned int phymode,
2566                                   struct b43_wldev **dev, bool * gmode)
2567 {
2568         struct b43_wldev *d;
2569
2570         list_for_each_entry(d, &wl->devlist, list) {
2571                 if (d->phy.possible_phymodes & phymode) {
2572                         /* Ok, this device supports the PHY-mode.
2573                          * Now figure out how the gmode bit has to be
2574                          * set to support it. */
2575                         if (phymode == B43_PHYMODE_A)
2576                                 *gmode = 0;
2577                         else
2578                                 *gmode = 1;
2579                         *dev = d;
2580
2581                         return 0;
2582                 }
2583         }
2584
2585         return -ESRCH;
2586 }
2587
2588 static void b43_put_phy_into_reset(struct b43_wldev *dev)
2589 {
2590         struct ssb_device *sdev = dev->dev;
2591         u32 tmslow;
2592
2593         tmslow = ssb_read32(sdev, SSB_TMSLOW);
2594         tmslow &= ~B43_TMSLOW_GMODE;
2595         tmslow |= B43_TMSLOW_PHYRESET;
2596         tmslow |= SSB_TMSLOW_FGC;
2597         ssb_write32(sdev, SSB_TMSLOW, tmslow);
2598         msleep(1);
2599
2600         tmslow = ssb_read32(sdev, SSB_TMSLOW);
2601         tmslow &= ~SSB_TMSLOW_FGC;
2602         tmslow |= B43_TMSLOW_PHYRESET;
2603         ssb_write32(sdev, SSB_TMSLOW, tmslow);
2604         msleep(1);
2605 }
2606
2607 /* Expects wl->mutex locked */
2608 static int b43_switch_phymode(struct b43_wl *wl, unsigned int new_mode)
2609 {
2610         struct b43_wldev *up_dev;
2611         struct b43_wldev *down_dev;
2612         int err;
2613         bool gmode = 0;
2614         int prev_status;
2615
2616         err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
2617         if (err) {
2618                 b43err(wl, "Could not find a device for %s-PHY mode\n",
2619                        phymode_to_string(new_mode));
2620                 return err;
2621         }
2622         if ((up_dev == wl->current_dev) &&
2623             (!!wl->current_dev->phy.gmode == !!gmode)) {
2624                 /* This device is already running. */
2625                 return 0;
2626         }
2627         b43dbg(wl, "Reconfiguring PHYmode to %s-PHY\n",
2628                phymode_to_string(new_mode));
2629         down_dev = wl->current_dev;
2630
2631         prev_status = b43_status(down_dev);
2632         /* Shutdown the currently running core. */
2633         if (prev_status >= B43_STAT_STARTED)
2634                 b43_wireless_core_stop(down_dev);
2635         if (prev_status >= B43_STAT_INITIALIZED)
2636                 b43_wireless_core_exit(down_dev);
2637
2638         if (down_dev != up_dev) {
2639                 /* We switch to a different core, so we put PHY into
2640                  * RESET on the old core. */
2641                 b43_put_phy_into_reset(down_dev);
2642         }
2643
2644         /* Now start the new core. */
2645         up_dev->phy.gmode = gmode;
2646         if (prev_status >= B43_STAT_INITIALIZED) {
2647                 err = b43_wireless_core_init(up_dev);
2648                 if (err) {
2649                         b43err(wl, "Fatal: Could not initialize device for "
2650                                "newly selected %s-PHY mode\n",
2651                                phymode_to_string(new_mode));
2652                         goto init_failure;
2653                 }
2654         }
2655         if (prev_status >= B43_STAT_STARTED) {
2656                 err = b43_wireless_core_start(up_dev);
2657                 if (err) {
2658                         b43err(wl, "Fatal: Coult not start device for "
2659                                "newly selected %s-PHY mode\n",
2660                                phymode_to_string(new_mode));
2661                         b43_wireless_core_exit(up_dev);
2662                         goto init_failure;
2663                 }
2664         }
2665         B43_WARN_ON(b43_status(up_dev) != prev_status);
2666
2667         wl->current_dev = up_dev;
2668
2669         return 0;
2670       init_failure:
2671         /* Whoops, failed to init the new core. No core is operating now. */
2672         wl->current_dev = NULL;
2673         return err;
2674 }
2675
2676 /* Check if the use of the antenna that ieee80211 told us to
2677  * use is possible. This will fall back to DEFAULT.
2678  * "antenna_nr" is the antenna identifier we got from ieee80211. */
2679 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
2680                                   u8 antenna_nr)
2681 {
2682         u8 antenna_mask;
2683
2684         if (antenna_nr == 0) {
2685                 /* Zero means "use default antenna". That's always OK. */
2686                 return 0;
2687         }
2688
2689         /* Get the mask of available antennas. */
2690         if (dev->phy.gmode)
2691                 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
2692         else
2693                 antenna_mask = dev->dev->bus->sprom.ant_available_a;
2694
2695         if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
2696                 /* This antenna is not available. Fall back to default. */
2697                 return 0;
2698         }
2699
2700         return antenna_nr;
2701 }
2702
2703 static int b43_antenna_from_ieee80211(struct b43_wldev *dev, u8 antenna)
2704 {
2705         antenna = b43_ieee80211_antenna_sanitize(dev, antenna);
2706         switch (antenna) {
2707         case 0:         /* default/diversity */
2708                 return B43_ANTENNA_DEFAULT;
2709         case 1:         /* Antenna 0 */
2710                 return B43_ANTENNA0;
2711         case 2:         /* Antenna 1 */
2712                 return B43_ANTENNA1;
2713         default:
2714                 return B43_ANTENNA_DEFAULT;
2715         }
2716 }
2717
2718 static int b43_op_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
2719 {
2720         struct b43_wl *wl = hw_to_b43_wl(hw);
2721         struct b43_wldev *dev;
2722         struct b43_phy *phy;
2723         unsigned long flags;
2724         unsigned int new_phymode = 0xFFFF;
2725         int antenna;
2726         int err = 0;
2727         u32 savedirqs;
2728
2729         mutex_lock(&wl->mutex);
2730
2731         /* Switch the PHY mode (if necessary). */
2732         switch (conf->phymode) {
2733         case MODE_IEEE80211A:
2734                 new_phymode = B43_PHYMODE_A;
2735                 break;
2736         case MODE_IEEE80211B:
2737                 new_phymode = B43_PHYMODE_B;
2738                 break;
2739         case MODE_IEEE80211G:
2740                 new_phymode = B43_PHYMODE_G;
2741                 break;
2742         default:
2743                 B43_WARN_ON(1);
2744         }
2745         err = b43_switch_phymode(wl, new_phymode);
2746         if (err)
2747                 goto out_unlock_mutex;
2748         dev = wl->current_dev;
2749         phy = &dev->phy;
2750
2751         /* Disable IRQs while reconfiguring the device.
2752          * This makes it possible to drop the spinlock throughout
2753          * the reconfiguration process. */
2754         spin_lock_irqsave(&wl->irq_lock, flags);
2755         if (b43_status(dev) < B43_STAT_STARTED) {
2756                 spin_unlock_irqrestore(&wl->irq_lock, flags);
2757                 goto out_unlock_mutex;
2758         }
2759         savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL);
2760         spin_unlock_irqrestore(&wl->irq_lock, flags);
2761         b43_synchronize_irq(dev);
2762
2763         /* Switch to the requested channel.
2764          * The firmware takes care of races with the TX handler. */
2765         if (conf->channel_val != phy->channel)
2766                 b43_radio_selectchannel(dev, conf->channel_val, 0);
2767
2768         /* Enable/Disable ShortSlot timing. */
2769         if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) !=
2770             dev->short_slot) {
2771                 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
2772                 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
2773                         b43_short_slot_timing_enable(dev);
2774                 else
2775                         b43_short_slot_timing_disable(dev);
2776         }
2777
2778         dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
2779
2780         /* Adjust the desired TX power level. */
2781         if (conf->power_level != 0) {
2782                 if (conf->power_level != phy->power_level) {
2783                         phy->power_level = conf->power_level;
2784                         b43_phy_xmitpower(dev);
2785                 }
2786         }
2787
2788         /* Antennas for RX and management frame TX. */
2789         antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_tx);
2790         b43_mgmtframe_txantenna(dev, antenna);
2791         antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_rx);
2792         b43_set_rx_antenna(dev, antenna);
2793
2794         /* Update templates for AP mode. */
2795         if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2796                 b43_set_beacon_int(dev, conf->beacon_int);
2797
2798         if (!!conf->radio_enabled != phy->radio_on) {
2799                 if (conf->radio_enabled) {
2800                         b43_radio_turn_on(dev);
2801                         b43info(dev->wl, "Radio turned on by software\n");
2802                         if (!dev->radio_hw_enable) {
2803                                 b43info(dev->wl, "The hardware RF-kill button "
2804                                         "still turns the radio physically off. "
2805                                         "Press the button to turn it on.\n");
2806                         }
2807                 } else {
2808                         b43_radio_turn_off(dev, 0);
2809                         b43info(dev->wl, "Radio turned off by software\n");
2810                 }
2811         }
2812
2813         spin_lock_irqsave(&wl->irq_lock, flags);
2814         b43_interrupt_enable(dev, savedirqs);
2815         mmiowb();
2816         spin_unlock_irqrestore(&wl->irq_lock, flags);
2817       out_unlock_mutex:
2818         mutex_unlock(&wl->mutex);
2819
2820         return err;
2821 }
2822
2823 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2824                            const u8 *local_addr, const u8 *addr,
2825                            struct ieee80211_key_conf *key)
2826 {
2827         struct b43_wl *wl = hw_to_b43_wl(hw);
2828         struct b43_wldev *dev;
2829         unsigned long flags;
2830         u8 algorithm;
2831         u8 index;
2832         int err;
2833         DECLARE_MAC_BUF(mac);
2834
2835         if (modparam_nohwcrypt)
2836                 return -ENOSPC; /* User disabled HW-crypto */
2837
2838         mutex_lock(&wl->mutex);
2839         spin_lock_irqsave(&wl->irq_lock, flags);
2840
2841         dev = wl->current_dev;
2842         err = -ENODEV;
2843         if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
2844                 goto out_unlock;
2845
2846         err = -EINVAL;
2847         switch (key->alg) {
2848         case ALG_WEP:
2849                 if (key->keylen == 5)
2850                         algorithm = B43_SEC_ALGO_WEP40;
2851                 else
2852                         algorithm = B43_SEC_ALGO_WEP104;
2853                 break;
2854         case ALG_TKIP:
2855                 algorithm = B43_SEC_ALGO_TKIP;
2856                 break;
2857         case ALG_CCMP:
2858                 algorithm = B43_SEC_ALGO_AES;
2859                 break;
2860         default:
2861                 B43_WARN_ON(1);
2862                 goto out_unlock;
2863         }
2864         index = (u8) (key->keyidx);
2865         if (index > 3)
2866                 goto out_unlock;
2867
2868         switch (cmd) {
2869         case SET_KEY:
2870                 if (algorithm == B43_SEC_ALGO_TKIP) {
2871                         /* FIXME: No TKIP hardware encryption for now. */
2872                         err = -EOPNOTSUPP;
2873                         goto out_unlock;
2874                 }
2875
2876                 if (is_broadcast_ether_addr(addr)) {
2877                         /* addr is FF:FF:FF:FF:FF:FF for default keys */
2878                         err = b43_key_write(dev, index, algorithm,
2879                                             key->key, key->keylen, NULL, key);
2880                 } else {
2881                         /*
2882                          * either pairwise key or address is 00:00:00:00:00:00
2883                          * for transmit-only keys
2884                          */
2885                         err = b43_key_write(dev, -1, algorithm,
2886                                             key->key, key->keylen, addr, key);
2887                 }
2888                 if (err)
2889                         goto out_unlock;
2890
2891                 if (algorithm == B43_SEC_ALGO_WEP40 ||
2892                     algorithm == B43_SEC_ALGO_WEP104) {
2893                         b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
2894                 } else {
2895                         b43_hf_write(dev,
2896                                      b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
2897                 }
2898                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2899                 break;
2900         case DISABLE_KEY: {
2901                 err = b43_key_clear(dev, key->hw_key_idx);
2902                 if (err)
2903                         goto out_unlock;
2904                 break;
2905         }
2906         default:
2907                 B43_WARN_ON(1);
2908         }
2909 out_unlock:
2910         spin_unlock_irqrestore(&wl->irq_lock, flags);
2911         mutex_unlock(&wl->mutex);
2912         if (!err) {
2913                 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
2914                        "mac: %s\n",
2915                        cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
2916                        print_mac(mac, addr));
2917         }
2918         return err;
2919 }
2920
2921 static void b43_op_configure_filter(struct ieee80211_hw *hw,
2922                                     unsigned int changed, unsigned int *fflags,
2923                                     int mc_count, struct dev_addr_list *mc_list)
2924 {
2925         struct b43_wl *wl = hw_to_b43_wl(hw);
2926         struct b43_wldev *dev = wl->current_dev;
2927         unsigned long flags;
2928
2929         if (!dev) {
2930                 *fflags = 0;
2931                 return;
2932         }
2933
2934         spin_lock_irqsave(&wl->irq_lock, flags);
2935         *fflags &= FIF_PROMISC_IN_BSS |
2936                   FIF_ALLMULTI |
2937                   FIF_FCSFAIL |
2938                   FIF_PLCPFAIL |
2939                   FIF_CONTROL |
2940                   FIF_OTHER_BSS |
2941                   FIF_BCN_PRBRESP_PROMISC;
2942
2943         changed &= FIF_PROMISC_IN_BSS |
2944                    FIF_ALLMULTI |
2945                    FIF_FCSFAIL |
2946                    FIF_PLCPFAIL |
2947                    FIF_CONTROL |
2948                    FIF_OTHER_BSS |
2949                    FIF_BCN_PRBRESP_PROMISC;
2950
2951         wl->filter_flags = *fflags;
2952
2953         if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
2954                 b43_adjust_opmode(dev);
2955         spin_unlock_irqrestore(&wl->irq_lock, flags);
2956 }
2957
2958 static int b43_op_config_interface(struct ieee80211_hw *hw,
2959                                    struct ieee80211_vif *vif,
2960                                    struct ieee80211_if_conf *conf)
2961 {
2962         struct b43_wl *wl = hw_to_b43_wl(hw);
2963         struct b43_wldev *dev = wl->current_dev;
2964         unsigned long flags;
2965
2966         if (!dev)
2967                 return -ENODEV;
2968         mutex_lock(&wl->mutex);
2969         spin_lock_irqsave(&wl->irq_lock, flags);
2970         B43_WARN_ON(wl->vif != vif);
2971         if (conf->bssid)
2972                 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
2973         else
2974                 memset(wl->bssid, 0, ETH_ALEN);
2975         if (b43_status(dev) >= B43_STAT_INITIALIZED) {
2976                 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) {
2977                         B43_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP);
2978                         b43_set_ssid(dev, conf->ssid, conf->ssid_len);
2979                         if (conf->beacon)
2980                                 b43_update_templates(wl, conf->beacon);
2981                 }
2982                 b43_write_mac_bssid_templates(dev);
2983         }
2984         spin_unlock_irqrestore(&wl->irq_lock, flags);
2985         mutex_unlock(&wl->mutex);
2986
2987         return 0;
2988 }
2989
2990 /* Locking: wl->mutex */
2991 static void b43_wireless_core_stop(struct b43_wldev *dev)
2992 {
2993         struct b43_wl *wl = dev->wl;
2994         unsigned long flags;
2995
2996         if (b43_status(dev) < B43_STAT_STARTED)
2997                 return;
2998
2999         /* Disable and sync interrupts. We must do this before than
3000          * setting the status to INITIALIZED, as the interrupt handler
3001          * won't care about IRQs then. */
3002         spin_lock_irqsave(&wl->irq_lock, flags);
3003         dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
3004         b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
3005         spin_unlock_irqrestore(&wl->irq_lock, flags);
3006         b43_synchronize_irq(dev);
3007
3008         b43_set_status(dev, B43_STAT_INITIALIZED);
3009
3010         mutex_unlock(&wl->mutex);
3011         /* Must unlock as it would otherwise deadlock. No races here.
3012          * Cancel the possibly running self-rearming periodic work. */
3013         cancel_delayed_work_sync(&dev->periodic_work);
3014         mutex_lock(&wl->mutex);
3015
3016         ieee80211_stop_queues(wl->hw);  //FIXME this could cause a deadlock, as mac80211 seems buggy.
3017
3018         b43_mac_suspend(dev);
3019         free_irq(dev->dev->irq, dev);
3020         b43dbg(wl, "Wireless interface stopped\n");
3021 }
3022
3023 /* Locking: wl->mutex */
3024 static int b43_wireless_core_start(struct b43_wldev *dev)
3025 {
3026         int err;
3027
3028         B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3029
3030         drain_txstatus_queue(dev);
3031         err = request_irq(dev->dev->irq, b43_interrupt_handler,
3032                           IRQF_SHARED, KBUILD_MODNAME, dev);
3033         if (err) {
3034                 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3035                 goto out;
3036         }
3037
3038         /* We are ready to run. */
3039         b43_set_status(dev, B43_STAT_STARTED);
3040
3041         /* Start data flow (TX/RX). */
3042         b43_mac_enable(dev);
3043         b43_interrupt_enable(dev, dev->irq_savedstate);
3044         ieee80211_start_queues(dev->wl->hw);
3045
3046         /* Start maintainance work */
3047         b43_periodic_tasks_setup(dev);
3048
3049         b43dbg(dev->wl, "Wireless interface started\n");
3050       out:
3051         return err;
3052 }
3053
3054 /* Get PHY and RADIO versioning numbers */
3055 static int b43_phy_versioning(struct b43_wldev *dev)
3056 {
3057         struct b43_phy *phy = &dev->phy;
3058         u32 tmp;
3059         u8 analog_type;
3060         u8 phy_type;
3061         u8 phy_rev;
3062         u16 radio_manuf;
3063         u16 radio_ver;
3064         u16 radio_rev;
3065         int unsupported = 0;
3066
3067         /* Get PHY versioning */
3068         tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3069         analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3070         phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3071         phy_rev = (tmp & B43_PHYVER_VERSION);
3072         switch (phy_type) {
3073         case B43_PHYTYPE_A:
3074                 if (phy_rev >= 4)
3075                         unsupported = 1;
3076                 break;
3077         case B43_PHYTYPE_B:
3078                 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3079                     && phy_rev != 7)
3080                         unsupported = 1;
3081                 break;
3082         case B43_PHYTYPE_G:
3083                 if (phy_rev > 9)
3084                         unsupported = 1;
3085                 break;
3086 #ifdef CONFIG_B43_NPHY
3087         case B43_PHYTYPE_N:
3088                 if (phy_rev > 1)
3089                         unsupported = 1;
3090                 break;
3091 #endif
3092         default:
3093                 unsupported = 1;
3094         };
3095         if (unsupported) {
3096                 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3097                        "(Analog %u, Type %u, Revision %u)\n",
3098                        analog_type, phy_type, phy_rev);
3099                 return -EOPNOTSUPP;
3100         }
3101         b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3102                analog_type, phy_type, phy_rev);
3103
3104         /* Get RADIO versioning */
3105         if (dev->dev->bus->chip_id == 0x4317) {
3106                 if (dev->dev->bus->chip_rev == 0)
3107                         tmp = 0x3205017F;
3108                 else if (dev->dev->bus->chip_rev == 1)
3109                         tmp = 0x4205017F;
3110                 else
3111                         tmp = 0x5205017F;
3112         } else {
3113                 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3114                 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH);
3115                 tmp <<= 16;
3116                 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3117                 tmp |= b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3118         }
3119         radio_manuf = (tmp & 0x00000FFF);
3120         radio_ver = (tmp & 0x0FFFF000) >> 12;
3121         radio_rev = (tmp & 0xF0000000) >> 28;
3122         if (radio_manuf != 0x17F /* Broadcom */)
3123                 unsupported = 1;
3124         switch (phy_type) {
3125         case B43_PHYTYPE_A:
3126                 if (radio_ver != 0x2060)
3127                         unsupported = 1;
3128                 if (radio_rev != 1)
3129                         unsupported = 1;
3130                 if (radio_manuf != 0x17F)
3131                         unsupported = 1;
3132                 break;
3133         case B43_PHYTYPE_B:
3134                 if ((radio_ver & 0xFFF0) != 0x2050)
3135                         unsupported = 1;
3136                 break;
3137         case B43_PHYTYPE_G:
3138                 if (radio_ver != 0x2050)
3139                         unsupported = 1;
3140                 break;
3141         case B43_PHYTYPE_N:
3142                 if (radio_ver != 5)
3143                         unsupported = 1;
3144                 break;
3145         default:
3146                 B43_WARN_ON(1);
3147         }
3148         if (unsupported) {
3149                 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
3150                        "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3151                        radio_manuf, radio_ver, radio_rev);
3152                 return -EOPNOTSUPP;
3153         }
3154         b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3155                radio_manuf, radio_ver, radio_rev);
3156
3157         phy->radio_manuf = radio_manuf;
3158         phy->radio_ver = radio_ver;
3159         phy->radio_rev = radio_rev;
3160
3161         phy->analog = analog_type;
3162         phy->type = phy_type;
3163         phy->rev = phy_rev;
3164
3165         return 0;
3166 }
3167
3168 static void setup_struct_phy_for_init(struct b43_wldev *dev,
3169                                       struct b43_phy *phy)
3170 {
3171         struct b43_txpower_lo_control *lo;
3172         int i;
3173
3174         memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3175         memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3176
3177         phy->aci_enable = 0;
3178         phy->aci_wlan_automatic = 0;
3179         phy->aci_hw_rssi = 0;
3180
3181         phy->radio_off_context.valid = 0;
3182
3183         lo = phy->lo_control;
3184         if (lo) {
3185                 memset(lo, 0, sizeof(*(phy->lo_control)));
3186                 lo->rebuild = 1;
3187                 lo->tx_bias = 0xFF;
3188         }
3189         phy->max_lb_gain = 0;
3190         phy->trsw_rx_gain = 0;
3191         phy->txpwr_offset = 0;
3192
3193         /* NRSSI */
3194         phy->nrssislope = 0;
3195         for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3196                 phy->nrssi[i] = -1000;
3197         for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3198                 phy->nrssi_lt[i] = i;
3199
3200         phy->lofcal = 0xFFFF;
3201         phy->initval = 0xFFFF;
3202
3203         phy->interfmode = B43_INTERFMODE_NONE;
3204         phy->channel = 0xFF;
3205
3206         phy->hardware_power_control = !!modparam_hwpctl;
3207
3208         /* PHY TX errors counter. */
3209         atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3210
3211         /* OFDM-table address caching. */
3212         phy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_UNKNOWN;
3213 }
3214
3215 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
3216 {
3217         dev->dfq_valid = 0;
3218
3219         /* Assume the radio is enabled. If it's not enabled, the state will
3220          * immediately get fixed on the first periodic work run. */
3221         dev->radio_hw_enable = 1;
3222
3223         /* Stats */
3224         memset(&dev->stats, 0, sizeof(dev->stats));
3225
3226         setup_struct_phy_for_init(dev, &dev->phy);
3227
3228         /* IRQ related flags */
3229         dev->irq_reason = 0;
3230         memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3231         dev->irq_savedstate = B43_IRQ_MASKTEMPLATE;
3232
3233         dev->mac_suspended = 1;
3234
3235         /* Noise calculation context */
3236         memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3237 }
3238
3239 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
3240 {
3241         struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3242         u32 hf;
3243
3244         if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
3245                 return;
3246         if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
3247                 return;
3248
3249         hf = b43_hf_read(dev);
3250         if (sprom->boardflags_lo & B43_BFL_BTCMOD)
3251                 hf |= B43_HF_BTCOEXALT;
3252         else
3253                 hf |= B43_HF_BTCOEX;
3254         b43_hf_write(dev, hf);
3255         //TODO
3256 }
3257
3258 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
3259 {                               //TODO
3260 }
3261
3262 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
3263 {
3264 #ifdef CONFIG_SSB_DRIVER_PCICORE
3265         struct ssb_bus *bus = dev->dev->bus;
3266         u32 tmp;
3267
3268         if (bus->pcicore.dev &&
3269             bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
3270             bus->pcicore.dev->id.revision <= 5) {
3271                 /* IMCFGLO timeouts workaround. */
3272                 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
3273                 tmp &= ~SSB_IMCFGLO_REQTO;
3274                 tmp &= ~SSB_IMCFGLO_SERTO;
3275                 switch (bus->bustype) {
3276                 case SSB_BUSTYPE_PCI:
3277                 case SSB_BUSTYPE_PCMCIA:
3278                         tmp |= 0x32;
3279                         break;
3280                 case SSB_BUSTYPE_SSB:
3281                         tmp |= 0x53;
3282                         break;
3283                 }
3284                 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
3285         }
3286 #endif /* CONFIG_SSB_DRIVER_PCICORE */
3287 }
3288
3289 /* Write the short and long frame retry limit values. */
3290 static void b43_set_retry_limits(struct b43_wldev *dev,
3291                                  unsigned int short_retry,
3292                                  unsigned int long_retry)
3293 {
3294         /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3295          * the chip-internal counter. */
3296         short_retry = min(short_retry, (unsigned int)0xF);
3297         long_retry = min(long_retry, (unsigned int)0xF);
3298
3299         b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3300                         short_retry);
3301         b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3302                         long_retry);
3303 }
3304
3305 /* Shutdown a wireless core */
3306 /* Locking: wl->mutex */
3307 static void b43_wireless_core_exit(struct b43_wldev *dev)
3308 {
3309         struct b43_phy *phy = &dev->phy;
3310
3311         B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
3312         if (b43_status(dev) != B43_STAT_INITIALIZED)
3313                 return;
3314         b43_set_status(dev, B43_STAT_UNINIT);
3315
3316         b43_leds_exit(dev);
3317         b43_rng_exit(dev->wl);
3318         b43_dma_free(dev);
3319         b43_chip_exit(dev);
3320         b43_radio_turn_off(dev, 1);
3321         b43_switch_analog(dev, 0);
3322         if (phy->dyn_tssi_tbl)
3323                 kfree(phy->tssi2dbm);
3324         kfree(phy->lo_control);
3325         phy->lo_control = NULL;
3326         if (dev->wl->current_beacon) {
3327                 dev_kfree_skb_any(dev->wl->current_beacon);
3328                 dev->wl->current_beacon = NULL;
3329         }
3330
3331         ssb_device_disable(dev->dev, 0);
3332         ssb_bus_may_powerdown(dev->dev->bus);
3333 }
3334
3335 /* Initialize a wireless core */
3336 static int b43_wireless_core_init(struct b43_wldev *dev)
3337 {
3338         struct b43_wl *wl = dev->wl;
3339         struct ssb_bus *bus = dev->dev->bus;
3340         struct ssb_sprom *sprom = &bus->sprom;
3341         struct b43_phy *phy = &dev->phy;
3342         int err;
3343         u32 hf, tmp;
3344
3345         B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3346
3347         err = ssb_bus_powerup(bus, 0);
3348         if (err)
3349                 goto out;
3350         if (!ssb_device_is_enabled(dev->dev)) {
3351                 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
3352                 b43_wireless_core_reset(dev, tmp);
3353         }
3354
3355         if ((phy->type == B43_PHYTYPE_B) || (phy->type == B43_PHYTYPE_G)) {
3356                 phy->lo_control =
3357                     kzalloc(sizeof(*(phy->lo_control)), GFP_KERNEL);
3358                 if (!phy->lo_control) {
3359                         err = -ENOMEM;
3360                         goto err_busdown;
3361                 }
3362         }
3363         setup_struct_wldev_for_init(dev);
3364
3365         err = b43_phy_init_tssi2dbm_table(dev);
3366         if (err)
3367                 goto err_kfree_lo_control;
3368
3369         /* Enable IRQ routing to this device. */
3370         ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3371
3372         b43_imcfglo_timeouts_workaround(dev);
3373         b43_bluetooth_coext_disable(dev);
3374         b43_phy_early_init(dev);
3375         err = b43_chip_init(dev);
3376         if (err)
3377                 goto err_kfree_tssitbl;
3378         b43_shm_write16(dev, B43_SHM_SHARED,
3379                         B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
3380         hf = b43_hf_read(dev);
3381         if (phy->type == B43_PHYTYPE_G) {
3382                 hf |= B43_HF_SYMW;
3383                 if (phy->rev == 1)
3384                         hf |= B43_HF_GDCW;
3385                 if (sprom->boardflags_lo & B43_BFL_PACTRL)
3386                         hf |= B43_HF_OFDMPABOOST;
3387         } else if (phy->type == B43_PHYTYPE_B) {
3388                 hf |= B43_HF_SYMW;
3389                 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
3390                         hf &= ~B43_HF_GDCW;
3391         }
3392         b43_hf_write(dev, hf);
3393
3394         b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
3395                              B43_DEFAULT_LONG_RETRY_LIMIT);
3396         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
3397         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
3398
3399         /* Disable sending probe responses from firmware.
3400          * Setting the MaxTime to one usec will always trigger
3401          * a timeout, so we never send any probe resp.
3402          * A timeout of zero is infinite. */
3403         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
3404
3405         b43_rate_memory_init(dev);
3406
3407         /* Minimum Contention Window */
3408         if (phy->type == B43_PHYTYPE_B) {
3409                 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
3410         } else {
3411                 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
3412         }
3413         /* Maximum Contention Window */
3414         b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
3415
3416         err = b43_dma_init(dev);
3417         if (err)
3418                 goto err_chip_exit;
3419         b43_qos_init(dev);
3420
3421 //FIXME
3422 #if 1
3423         b43_write16(dev, 0x0612, 0x0050);
3424         b43_shm_write16(dev, B43_SHM_SHARED, 0x0416, 0x0050);
3425         b43_shm_write16(dev, B43_SHM_SHARED, 0x0414, 0x01F4);
3426 #endif
3427
3428         b43_bluetooth_coext_enable(dev);
3429
3430         ssb_bus_powerup(bus, 1);        /* Enable dynamic PCTL */
3431         memset(wl->bssid, 0, ETH_ALEN);
3432         memset(wl->mac_addr, 0, ETH_ALEN);
3433         b43_upload_card_macaddress(dev);
3434         b43_security_init(dev);
3435         b43_rng_init(wl);
3436
3437         b43_set_status(dev, B43_STAT_INITIALIZED);
3438
3439         b43_leds_init(dev);
3440 out:
3441         return err;
3442
3443       err_chip_exit:
3444         b43_chip_exit(dev);
3445       err_kfree_tssitbl:
3446         if (phy->dyn_tssi_tbl)
3447                 kfree(phy->tssi2dbm);
3448       err_kfree_lo_control:
3449         kfree(phy->lo_control);
3450         phy->lo_control = NULL;
3451       err_busdown:
3452         ssb_bus_may_powerdown(bus);
3453         B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3454         return err;
3455 }
3456
3457 static int b43_op_add_interface(struct ieee80211_hw *hw,
3458                                 struct ieee80211_if_init_conf *conf)
3459 {
3460         struct b43_wl *wl = hw_to_b43_wl(hw);
3461         struct b43_wldev *dev;
3462         unsigned long flags;
3463         int err = -EOPNOTSUPP;
3464
3465         /* TODO: allow WDS/AP devices to coexist */
3466
3467         if (conf->type != IEEE80211_IF_TYPE_AP &&
3468             conf->type != IEEE80211_IF_TYPE_STA &&
3469             conf->type != IEEE80211_IF_TYPE_WDS &&
3470             conf->type != IEEE80211_IF_TYPE_IBSS)
3471                 return -EOPNOTSUPP;
3472
3473         mutex_lock(&wl->mutex);
3474         if (wl->operating)
3475                 goto out_mutex_unlock;
3476
3477         b43dbg(wl, "Adding Interface type %d\n", conf->type);
3478
3479         dev = wl->current_dev;
3480         wl->operating = 1;
3481         wl->vif = conf->vif;
3482         wl->if_type = conf->type;
3483         memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
3484
3485         spin_lock_irqsave(&wl->irq_lock, flags);
3486         b43_adjust_opmode(dev);
3487         b43_upload_card_macaddress(dev);
3488         spin_unlock_irqrestore(&wl->irq_lock, flags);
3489
3490         err = 0;
3491  out_mutex_unlock:
3492         mutex_unlock(&wl->mutex);
3493
3494         return err;
3495 }
3496
3497 static void b43_op_remove_interface(struct ieee80211_hw *hw,
3498                                     struct ieee80211_if_init_conf *conf)
3499 {
3500         struct b43_wl *wl = hw_to_b43_wl(hw);
3501         struct b43_wldev *dev = wl->current_dev;
3502         unsigned long flags;
3503
3504         b43dbg(wl, "Removing Interface type %d\n", conf->type);
3505
3506         mutex_lock(&wl->mutex);
3507
3508         B43_WARN_ON(!wl->operating);
3509         B43_WARN_ON(wl->vif != conf->vif);
3510         wl->vif = NULL;
3511
3512         wl->operating = 0;
3513
3514         spin_lock_irqsave(&wl->irq_lock, flags);
3515         b43_adjust_opmode(dev);
3516         memset(wl->mac_addr, 0, ETH_ALEN);
3517         b43_upload_card_macaddress(dev);
3518         spin_unlock_irqrestore(&wl->irq_lock, flags);
3519
3520         mutex_unlock(&wl->mutex);
3521 }
3522
3523 static int b43_op_start(struct ieee80211_hw *hw)
3524 {
3525         struct b43_wl *wl = hw_to_b43_wl(hw);
3526         struct b43_wldev *dev = wl->current_dev;
3527         int did_init = 0;
3528         int err = 0;
3529
3530         /* First register RFkill.
3531          * LEDs that are registered later depend on it. */
3532         b43_rfkill_init(dev);
3533
3534         mutex_lock(&wl->mutex);
3535
3536         if (b43_status(dev) < B43_STAT_INITIALIZED) {
3537                 err = b43_wireless_core_init(dev);
3538                 if (err)
3539                         goto out_mutex_unlock;
3540                 did_init = 1;
3541         }
3542
3543         if (b43_status(dev) < B43_STAT_STARTED) {
3544                 err = b43_wireless_core_start(dev);
3545                 if (err) {
3546                         if (did_init)
3547                                 b43_wireless_core_exit(dev);
3548                         goto out_mutex_unlock;
3549                 }
3550         }
3551
3552  out_mutex_unlock:
3553         mutex_unlock(&wl->mutex);
3554
3555         return err;
3556 }
3557
3558 static void b43_op_stop(struct ieee80211_hw *hw)
3559 {
3560         struct b43_wl *wl = hw_to_b43_wl(hw);
3561         struct b43_wldev *dev = wl->current_dev;
3562
3563         b43_rfkill_exit(dev);
3564
3565         mutex_lock(&wl->mutex);
3566         if (b43_status(dev) >= B43_STAT_STARTED)
3567                 b43_wireless_core_stop(dev);
3568         b43_wireless_core_exit(dev);
3569         mutex_unlock(&wl->mutex);
3570 }
3571
3572 static int b43_op_set_retry_limit(struct ieee80211_hw *hw,
3573                                   u32 short_retry_limit, u32 long_retry_limit)
3574 {
3575         struct b43_wl *wl = hw_to_b43_wl(hw);
3576         struct b43_wldev *dev;
3577         int err = 0;
3578
3579         mutex_lock(&wl->mutex);
3580         dev = wl->current_dev;
3581         if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED))) {
3582                 err = -ENODEV;
3583                 goto out_unlock;
3584         }
3585         b43_set_retry_limits(dev, short_retry_limit, long_retry_limit);
3586 out_unlock:
3587         mutex_unlock(&wl->mutex);
3588
3589         return err;
3590 }
3591
3592 static int b43_op_beacon_set_tim(struct ieee80211_hw *hw, int aid, int set)
3593 {
3594         struct b43_wl *wl = hw_to_b43_wl(hw);
3595         struct sk_buff *beacon;
3596         unsigned long flags;
3597
3598         /* We could modify the existing beacon and set the aid bit in
3599          * the TIM field, but that would probably require resizing and
3600          * moving of data within the beacon template.
3601          * Simply request a new beacon and let mac80211 do the hard work. */
3602         beacon = ieee80211_beacon_get(hw, wl->vif, NULL);
3603         if (unlikely(!beacon))
3604                 return -ENOMEM;
3605         spin_lock_irqsave(&wl->irq_lock, flags);
3606         b43_update_templates(wl, beacon);
3607         spin_unlock_irqrestore(&wl->irq_lock, flags);
3608
3609         return 0;
3610 }
3611
3612 static int b43_op_ibss_beacon_update(struct ieee80211_hw *hw,
3613                                      struct sk_buff *beacon,
3614                                      struct ieee80211_tx_control *ctl)
3615 {
3616         struct b43_wl *wl = hw_to_b43_wl(hw);
3617         unsigned long flags;
3618
3619         spin_lock_irqsave(&wl->irq_lock, flags);
3620         b43_update_templates(wl, beacon);
3621         spin_unlock_irqrestore(&wl->irq_lock, flags);
3622
3623         return 0;
3624 }
3625
3626 static const struct ieee80211_ops b43_hw_ops = {
3627         .tx                     = b43_op_tx,
3628         .conf_tx                = b43_op_conf_tx,
3629         .add_interface          = b43_op_add_interface,
3630         .remove_interface       = b43_op_remove_interface,
3631         .config                 = b43_op_config,
3632         .config_interface       = b43_op_config_interface,
3633         .configure_filter       = b43_op_configure_filter,
3634         .set_key                = b43_op_set_key,
3635         .get_stats              = b43_op_get_stats,
3636         .get_tx_stats           = b43_op_get_tx_stats,
3637         .start                  = b43_op_start,
3638         .stop                   = b43_op_stop,
3639         .set_retry_limit        = b43_op_set_retry_limit,
3640         .set_tim                = b43_op_beacon_set_tim,
3641         .beacon_update          = b43_op_ibss_beacon_update,
3642 };
3643
3644 /* Hard-reset the chip. Do not call this directly.
3645  * Use b43_controller_restart()
3646  */
3647 static void b43_chip_reset(struct work_struct *work)
3648 {
3649         struct b43_wldev *dev =
3650             container_of(work, struct b43_wldev, restart_work);
3651         struct b43_wl *wl = dev->wl;
3652         int err = 0;
3653         int prev_status;
3654
3655         mutex_lock(&wl->mutex);
3656
3657         prev_status = b43_status(dev);
3658         /* Bring the device down... */
3659         if (prev_status >= B43_STAT_STARTED)
3660                 b43_wireless_core_stop(dev);
3661         if (prev_status >= B43_STAT_INITIALIZED)
3662                 b43_wireless_core_exit(dev);
3663
3664         /* ...and up again. */
3665         if (prev_status >= B43_STAT_INITIALIZED) {
3666                 err = b43_wireless_core_init(dev);
3667                 if (err)
3668                         goto out;
3669         }
3670         if (prev_status >= B43_STAT_STARTED) {
3671                 err = b43_wireless_core_start(dev);
3672                 if (err) {
3673                         b43_wireless_core_exit(dev);
3674                         goto out;
3675                 }
3676         }
3677       out:
3678         mutex_unlock(&wl->mutex);
3679         if (err)
3680                 b43err(wl, "Controller restart FAILED\n");
3681         else
3682                 b43info(wl, "Controller restarted\n");
3683 }
3684
3685 static int b43_setup_modes(struct b43_wldev *dev,
3686                            bool have_2ghz_phy, bool have_5ghz_phy)
3687 {
3688         struct ieee80211_hw *hw = dev->wl->hw;
3689         struct ieee80211_hw_mode *mode;
3690         struct b43_phy *phy = &dev->phy;
3691         int err;
3692
3693         /* XXX: This function will go away soon, when mac80211
3694          *      band stuff is rewritten. So this is just a hack.
3695          *      For now we always claim GPHY mode, as there is no
3696          *      support for NPHY and APHY in the device, yet.
3697          *      This assumption is OK, as any B, N or A PHY will already
3698          *      have died a horrible sanity check death earlier. */
3699
3700         mode = &phy->hwmodes[0];
3701         mode->mode = MODE_IEEE80211G;
3702         mode->num_channels = b43_2ghz_chantable_size;
3703         mode->channels = b43_2ghz_chantable;
3704         mode->num_rates = b43_g_ratetable_size;
3705         mode->rates = b43_g_ratetable;
3706         err = ieee80211_register_hwmode(hw, mode);
3707         if (err)
3708                 return err;
3709         phy->possible_phymodes |= B43_PHYMODE_G;
3710
3711         return 0;
3712 }
3713
3714 static void b43_wireless_core_detach(struct b43_wldev *dev)
3715 {
3716         /* We release firmware that late to not be required to re-request
3717          * is all the time when we reinit the core. */
3718         b43_release_firmware(dev);
3719 }
3720
3721 static int b43_wireless_core_attach(struct b43_wldev *dev)
3722 {
3723         struct b43_wl *wl = dev->wl;
3724         struct ssb_bus *bus = dev->dev->bus;
3725         struct pci_dev *pdev = bus->host_pci;
3726         int err;
3727         bool have_2ghz_phy = 0, have_5ghz_phy = 0;
3728         u32 tmp;
3729
3730         /* Do NOT do any device initialization here.
3731          * Do it in wireless_core_init() instead.
3732          * This function is for gathering basic information about the HW, only.
3733          * Also some structs may be set up here. But most likely you want to have
3734          * that in core_init(), too.
3735          */
3736
3737         err = ssb_bus_powerup(bus, 0);
3738         if (err) {
3739                 b43err(wl, "Bus powerup failed\n");
3740                 goto out;
3741         }
3742         /* Get the PHY type. */
3743         if (dev->dev->id.revision >= 5) {
3744                 u32 tmshigh;
3745
3746                 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
3747                 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
3748                 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
3749         } else
3750                 B43_WARN_ON(1);
3751
3752         dev->phy.gmode = have_2ghz_phy;
3753         tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3754         b43_wireless_core_reset(dev, tmp);
3755
3756         err = b43_phy_versioning(dev);
3757         if (err)
3758                 goto err_powerdown;
3759         /* Check if this device supports multiband. */
3760         if (!pdev ||
3761             (pdev->device != 0x4312 &&
3762              pdev->device != 0x4319 && pdev->device != 0x4324)) {
3763                 /* No multiband support. */
3764                 have_2ghz_phy = 0;
3765                 have_5ghz_phy = 0;
3766                 switch (dev->phy.type) {
3767                 case B43_PHYTYPE_A:
3768                         have_5ghz_phy = 1;
3769                         break;
3770                 case B43_PHYTYPE_G:
3771                 case B43_PHYTYPE_N:
3772                         have_2ghz_phy = 1;
3773                         break;
3774                 default:
3775                         B43_WARN_ON(1);
3776                 }
3777         }
3778         if (dev->phy.type == B43_PHYTYPE_A) {
3779                 /* FIXME */
3780                 b43err(wl, "IEEE 802.11a devices are unsupported\n");
3781                 err = -EOPNOTSUPP;
3782                 goto err_powerdown;
3783         }
3784         dev->phy.gmode = have_2ghz_phy;
3785         tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3786         b43_wireless_core_reset(dev, tmp);
3787
3788         err = b43_validate_chipaccess(dev);
3789         if (err)
3790                 goto err_powerdown;
3791         err = b43_setup_modes(dev, have_2ghz_phy, have_5ghz_phy);
3792         if (err)
3793                 goto err_powerdown;
3794
3795         /* Now set some default "current_dev" */
3796         if (!wl->current_dev)
3797                 wl->current_dev = dev;
3798         INIT_WORK(&dev->restart_work, b43_chip_reset);
3799
3800         b43_radio_turn_off(dev, 1);
3801         b43_switch_analog(dev, 0);
3802         ssb_device_disable(dev->dev, 0);
3803         ssb_bus_may_powerdown(bus);
3804
3805 out:
3806         return err;
3807
3808 err_powerdown:
3809         ssb_bus_may_powerdown(bus);
3810         return err;
3811 }
3812
3813 static void b43_one_core_detach(struct ssb_device *dev)
3814 {
3815         struct b43_wldev *wldev;
3816         struct b43_wl *wl;
3817
3818         wldev = ssb_get_drvdata(dev);
3819         wl = wldev->wl;
3820         cancel_work_sync(&wldev->restart_work);
3821         b43_debugfs_remove_device(wldev);
3822         b43_wireless_core_detach(wldev);
3823         list_del(&wldev->list);
3824         wl->nr_devs--;
3825         ssb_set_drvdata(dev, NULL);
3826         kfree(wldev);
3827 }
3828
3829 static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
3830 {
3831         struct b43_wldev *wldev;
3832         struct pci_dev *pdev;
3833         int err = -ENOMEM;
3834
3835         if (!list_empty(&wl->devlist)) {
3836                 /* We are not the first core on this chip. */
3837                 pdev = dev->bus->host_pci;
3838                 /* Only special chips support more than one wireless
3839                  * core, although some of the other chips have more than
3840                  * one wireless core as well. Check for this and
3841                  * bail out early.
3842                  */
3843                 if (!pdev ||
3844                     ((pdev->device != 0x4321) &&
3845                      (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
3846                         b43dbg(wl, "Ignoring unconnected 802.11 core\n");
3847                         return -ENODEV;
3848                 }
3849         }
3850
3851         wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
3852         if (!wldev)
3853                 goto out;
3854
3855         wldev->dev = dev;
3856         wldev->wl = wl;
3857         b43_set_status(wldev, B43_STAT_UNINIT);
3858         wldev->bad_frames_preempt = modparam_bad_frames_preempt;
3859         tasklet_init(&wldev->isr_tasklet,
3860                      (void (*)(unsigned long))b43_interrupt_tasklet,
3861                      (unsigned long)wldev);
3862         INIT_LIST_HEAD(&wldev->list);
3863
3864         err = b43_wireless_core_attach(wldev);
3865         if (err)
3866                 goto err_kfree_wldev;
3867
3868         list_add(&wldev->list, &wl->devlist);
3869         wl->nr_devs++;
3870         ssb_set_drvdata(dev, wldev);
3871         b43_debugfs_add_device(wldev);
3872
3873       out:
3874         return err;
3875
3876       err_kfree_wldev:
3877         kfree(wldev);
3878         return err;
3879 }
3880
3881 static void b43_sprom_fixup(struct ssb_bus *bus)
3882 {
3883         /* boardflags workarounds */
3884         if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
3885             bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
3886                 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
3887         if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3888             bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
3889                 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
3890 }
3891
3892 static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
3893 {
3894         struct ieee80211_hw *hw = wl->hw;
3895
3896         ssb_set_devtypedata(dev, NULL);
3897         ieee80211_free_hw(hw);
3898 }
3899
3900 static int b43_wireless_init(struct ssb_device *dev)
3901 {
3902         struct ssb_sprom *sprom = &dev->bus->sprom;
3903         struct ieee80211_hw *hw;
3904         struct b43_wl *wl;
3905         int err = -ENOMEM;
3906
3907         b43_sprom_fixup(dev->bus);
3908
3909         hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
3910         if (!hw) {
3911                 b43err(NULL, "Could not allocate ieee80211 device\n");
3912                 goto out;
3913         }
3914
3915         /* fill hw info */
3916         hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
3917                     IEEE80211_HW_RX_INCLUDES_FCS;
3918         hw->max_signal = 100;
3919         hw->max_rssi = -110;
3920         hw->max_noise = -110;
3921         hw->queues = 1;         /* FIXME: hardware has more queues */
3922         SET_IEEE80211_DEV(hw, dev->dev);
3923         if (is_valid_ether_addr(sprom->et1mac))
3924                 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
3925         else
3926                 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
3927
3928         /* Get and initialize struct b43_wl */
3929         wl = hw_to_b43_wl(hw);
3930         memset(wl, 0, sizeof(*wl));
3931         wl->hw = hw;
3932         spin_lock_init(&wl->irq_lock);
3933         spin_lock_init(&wl->leds_lock);
3934         mutex_init(&wl->mutex);
3935         INIT_LIST_HEAD(&wl->devlist);
3936
3937         ssb_set_devtypedata(dev, wl);
3938         b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
3939         err = 0;
3940       out:
3941         return err;
3942 }
3943
3944 static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
3945 {
3946         struct b43_wl *wl;
3947         int err;
3948         int first = 0;
3949
3950         wl = ssb_get_devtypedata(dev);
3951         if (!wl) {
3952                 /* Probing the first core. Must setup common struct b43_wl */
3953                 first = 1;
3954                 err = b43_wireless_init(dev);
3955                 if (err)
3956                         goto out;
3957                 wl = ssb_get_devtypedata(dev);
3958                 B43_WARN_ON(!wl);
3959         }
3960         err = b43_one_core_attach(dev, wl);
3961         if (err)
3962                 goto err_wireless_exit;
3963
3964         if (first) {
3965                 err = ieee80211_register_hw(wl->hw);
3966                 if (err)
3967                         goto err_one_core_detach;
3968         }
3969
3970       out:
3971         return err;
3972
3973       err_one_core_detach:
3974         b43_one_core_detach(dev);
3975       err_wireless_exit:
3976         if (first)
3977                 b43_wireless_exit(dev, wl);
3978         return err;
3979 }
3980
3981 static void b43_remove(struct ssb_device *dev)
3982 {
3983         struct b43_wl *wl = ssb_get_devtypedata(dev);
3984         struct b43_wldev *wldev = ssb_get_drvdata(dev);
3985
3986         B43_WARN_ON(!wl);
3987         if (wl->current_dev == wldev)
3988                 ieee80211_unregister_hw(wl->hw);
3989
3990         b43_one_core_detach(dev);
3991
3992         if (list_empty(&wl->devlist)) {
3993                 /* Last core on the chip unregistered.
3994                  * We can destroy common struct b43_wl.
3995                  */
3996                 b43_wireless_exit(dev, wl);
3997         }
3998 }
3999
4000 /* Perform a hardware reset. This can be called from any context. */
4001 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
4002 {
4003         /* Must avoid requeueing, if we are in shutdown. */
4004         if (b43_status(dev) < B43_STAT_INITIALIZED)
4005                 return;
4006         b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
4007         queue_work(dev->wl->hw->workqueue, &dev->restart_work);
4008 }
4009
4010 #ifdef CONFIG_PM
4011
4012 static int b43_suspend(struct ssb_device *dev, pm_message_t state)
4013 {
4014         struct b43_wldev *wldev = ssb_get_drvdata(dev);
4015         struct b43_wl *wl = wldev->wl;
4016
4017         b43dbg(wl, "Suspending...\n");
4018
4019         mutex_lock(&wl->mutex);
4020         wldev->suspend_init_status = b43_status(wldev);
4021         if (wldev->suspend_init_status >= B43_STAT_STARTED)
4022                 b43_wireless_core_stop(wldev);
4023         if (wldev->suspend_init_status >= B43_STAT_INITIALIZED)
4024                 b43_wireless_core_exit(wldev);
4025         mutex_unlock(&wl->mutex);
4026
4027         b43dbg(wl, "Device suspended.\n");
4028
4029         return 0;
4030 }
4031
4032 static int b43_resume(struct ssb_device *dev)
4033 {
4034         struct b43_wldev *wldev = ssb_get_drvdata(dev);
4035         struct b43_wl *wl = wldev->wl;
4036         int err = 0;
4037
4038         b43dbg(wl, "Resuming...\n");
4039
4040         mutex_lock(&wl->mutex);
4041         if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
4042                 err = b43_wireless_core_init(wldev);
4043                 if (err) {
4044                         b43err(wl, "Resume failed at core init\n");
4045                         goto out;
4046                 }
4047         }
4048         if (wldev->suspend_init_status >= B43_STAT_STARTED) {
4049                 err = b43_wireless_core_start(wldev);
4050                 if (err) {
4051                         b43_wireless_core_exit(wldev);
4052                         b43err(wl, "Resume failed at core start\n");
4053                         goto out;
4054                 }
4055         }
4056         mutex_unlock(&wl->mutex);
4057
4058         b43dbg(wl, "Device resumed.\n");
4059       out:
4060         return err;
4061 }
4062
4063 #else /* CONFIG_PM */
4064 # define b43_suspend    NULL
4065 # define b43_resume     NULL
4066 #endif /* CONFIG_PM */
4067
4068 static struct ssb_driver b43_ssb_driver = {
4069         .name           = KBUILD_MODNAME,
4070         .id_table       = b43_ssb_tbl,
4071         .probe          = b43_probe,
4072         .remove         = b43_remove,
4073         .suspend        = b43_suspend,
4074         .resume         = b43_resume,
4075 };
4076
4077 static int __init b43_init(void)
4078 {
4079         int err;
4080
4081         b43_debugfs_init();
4082         err = b43_pcmcia_init();
4083         if (err)
4084                 goto err_dfs_exit;
4085         err = ssb_driver_register(&b43_ssb_driver);
4086         if (err)
4087                 goto err_pcmcia_exit;
4088
4089         return err;
4090
4091 err_pcmcia_exit:
4092         b43_pcmcia_exit();
4093 err_dfs_exit:
4094         b43_debugfs_exit();
4095         return err;
4096 }
4097
4098 static void __exit b43_exit(void)
4099 {
4100         ssb_driver_unregister(&b43_ssb_driver);
4101         b43_pcmcia_exit();
4102         b43_debugfs_exit();
4103 }
4104
4105 module_init(b43_init)
4106 module_exit(b43_exit)