SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/b43/main.c

   1 /*
   2
   3   Broadcom B43 wireless driver
   4
   5   Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
   6   Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
   7   Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
   8   Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
   9   Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
  10
  11   Some parts of the code in this file are derived from the ipw2200
  12   driver  Copyright(c) 2003 - 2004 Intel Corporation.
  13
  14   This program is free software; you can redistribute it and/or modify
  15   it under the terms of the GNU General Public License as published by
  16   the Free Software Foundation; either version 2 of the License, or
  17   (at your option) any later version.
  18
  19   This program is distributed in the hope that it will be useful,
  20   but WITHOUT ANY WARRANTY; without even the implied warranty of
  21   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22   GNU General Public License for more details.
  23
  24   You should have received a copy of the GNU General Public License
  25   along with this program; see the file COPYING.  If not, write to
  26   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  27   Boston, MA 02110-1301, USA.
  28
  29 */
  30
  31 #include <linux/delay.h>
  32 #include <linux/init.h>
  33 #include <linux/moduleparam.h>
  34 #include <linux/if_arp.h>
  35 #include <linux/etherdevice.h>
  36 #include <linux/version.h>
  37 #include <linux/firmware.h>
  38 #include <linux/wireless.h>
  39 #include <linux/workqueue.h>
  40 #include <linux/skbuff.h>
  41 #include <linux/dma-mapping.h>
  42 #include <asm/unaligned.h>
  43
  44 #include "b43.h"
  45 #include "main.h"
  46 #include "debugfs.h"
  47 #include "phy.h"
  48 #include "dma.h"
  49 #include "sysfs.h"
  50 #include "xmit.h"
  51 #include "lo.h"
  52 #include "pcmcia.h"
  53
  54 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
  55 MODULE_AUTHOR("Martin Langer");
  56 MODULE_AUTHOR("Stefano Brivio");
  57 MODULE_AUTHOR("Michael Buesch");
  58 MODULE_LICENSE("GPL");
  59
  60
  61 static int modparam_bad_frames_preempt;
  62 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
  63 MODULE_PARM_DESC(bad_frames_preempt,
  64                  "enable(1) / disable(0) Bad Frames Preemption");
  65
  66 static char modparam_fwpostfix[16];
  67 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
  68 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
  69
  70 static int modparam_hwpctl;
  71 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
  72 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
  73
  74 static int modparam_nohwcrypt;
  75 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
  76 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  77
  78 static const struct ssb_device_id b43_ssb_tbl[] = {
  79         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
  80         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
  81         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
  82         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
  83         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
  84         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
  85         SSB_DEVTABLE_END
  86 };
  87
  88 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
  89
  90 /* Channel and ratetables are shared for all devices.
  91  * They can't be const, because ieee80211 puts some precalculated
  92  * data in there. This data is the same for all devices, so we don't
  93  * get concurrency issues */
  94 #define RATETAB_ENT(_rateid, _flags) \
  95         {                                                       \
  96                 .rate   = B43_RATE_TO_BASE100KBPS(_rateid),     \
  97                 .val    = (_rateid),                            \
  98                 .val2   = (_rateid),                            \
  99                 .flags  = (_flags),                             \
 100         }
 101 static struct ieee80211_rate __b43_ratetable[] = {
 102         RATETAB_ENT(B43_CCK_RATE_1MB, IEEE80211_RATE_CCK),
 103         RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_CCK_2),
 104         RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_CCK_2),
 105         RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_CCK_2),
 106         RATETAB_ENT(B43_OFDM_RATE_6MB, IEEE80211_RATE_OFDM),
 107         RATETAB_ENT(B43_OFDM_RATE_9MB, IEEE80211_RATE_OFDM),
 108         RATETAB_ENT(B43_OFDM_RATE_12MB, IEEE80211_RATE_OFDM),
 109         RATETAB_ENT(B43_OFDM_RATE_18MB, IEEE80211_RATE_OFDM),
 110         RATETAB_ENT(B43_OFDM_RATE_24MB, IEEE80211_RATE_OFDM),
 111         RATETAB_ENT(B43_OFDM_RATE_36MB, IEEE80211_RATE_OFDM),
 112         RATETAB_ENT(B43_OFDM_RATE_48MB, IEEE80211_RATE_OFDM),
 113         RATETAB_ENT(B43_OFDM_RATE_54MB, IEEE80211_RATE_OFDM),
 114 };
 115
 116 #define b43_a_ratetable         (__b43_ratetable + 4)
 117 #define b43_a_ratetable_size    8
 118 #define b43_b_ratetable         (__b43_ratetable + 0)
 119 #define b43_b_ratetable_size    4
 120 #define b43_g_ratetable         (__b43_ratetable + 0)
 121 #define b43_g_ratetable_size    12
 122
 123 #define CHANTAB_ENT(_chanid, _freq) \
 124         {                                                       \
 125                 .chan   = (_chanid),                            \
 126                 .freq   = (_freq),                              \
 127                 .val    = (_chanid),                            \
 128                 .flag   = IEEE80211_CHAN_W_SCAN |               \
 129                           IEEE80211_CHAN_W_ACTIVE_SCAN |        \
 130                           IEEE80211_CHAN_W_IBSS,                \
 131                 .power_level    = 0xFF,                         \
 132                 .antenna_max    = 0xFF,                         \
 133         }
 134 static struct ieee80211_channel b43_bg_chantable[] = {
 135         CHANTAB_ENT(1, 2412),
 136         CHANTAB_ENT(2, 2417),
 137         CHANTAB_ENT(3, 2422),
 138         CHANTAB_ENT(4, 2427),
 139         CHANTAB_ENT(5, 2432),
 140         CHANTAB_ENT(6, 2437),
 141         CHANTAB_ENT(7, 2442),
 142         CHANTAB_ENT(8, 2447),
 143         CHANTAB_ENT(9, 2452),
 144         CHANTAB_ENT(10, 2457),
 145         CHANTAB_ENT(11, 2462),
 146         CHANTAB_ENT(12, 2467),
 147         CHANTAB_ENT(13, 2472),
 148         CHANTAB_ENT(14, 2484),
 149 };
 150
 151 #define b43_bg_chantable_size   ARRAY_SIZE(b43_bg_chantable)
 152 static struct ieee80211_channel b43_a_chantable[] = {
 153         CHANTAB_ENT(36, 5180),
 154         CHANTAB_ENT(40, 5200),
 155         CHANTAB_ENT(44, 5220),
 156         CHANTAB_ENT(48, 5240),
 157         CHANTAB_ENT(52, 5260),
 158         CHANTAB_ENT(56, 5280),
 159         CHANTAB_ENT(60, 5300),
 160         CHANTAB_ENT(64, 5320),
 161         CHANTAB_ENT(149, 5745),
 162         CHANTAB_ENT(153, 5765),
 163         CHANTAB_ENT(157, 5785),
 164         CHANTAB_ENT(161, 5805),
 165         CHANTAB_ENT(165, 5825),
 166 };
 167
 168 #define b43_a_chantable_size    ARRAY_SIZE(b43_a_chantable)
 169
 170 static void b43_wireless_core_exit(struct b43_wldev *dev);
 171 static int b43_wireless_core_init(struct b43_wldev *dev);
 172 static void b43_wireless_core_stop(struct b43_wldev *dev);
 173 static int b43_wireless_core_start(struct b43_wldev *dev);
 174
 175 static int b43_ratelimit(struct b43_wl *wl)
 176 {
 177         if (!wl || !wl->current_dev)
 178                 return 1;
 179         if (b43_status(wl->current_dev) < B43_STAT_STARTED)
 180                 return 1;
 181         /* We are up and running.
 182          * Ratelimit the messages to avoid DoS over the net. */
 183         return net_ratelimit();
 184 }
 185
 186 void b43info(struct b43_wl *wl, const char *fmt, ...)
 187 {
 188         va_list args;
 189
 190         if (!b43_ratelimit(wl))
 191                 return;
 192         va_start(args, fmt);
 193         printk(KERN_INFO "b43-%s: ",
 194                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
 195         vprintk(fmt, args);
 196         va_end(args);
 197 }
 198
 199 void b43err(struct b43_wl *wl, const char *fmt, ...)
 200 {
 201         va_list args;
 202
 203         if (!b43_ratelimit(wl))
 204                 return;
 205         va_start(args, fmt);
 206         printk(KERN_ERR "b43-%s ERROR: ",
 207                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
 208         vprintk(fmt, args);
 209         va_end(args);
 210 }
 211
 212 void b43warn(struct b43_wl *wl, const char *fmt, ...)
 213 {
 214         va_list args;
 215
 216         if (!b43_ratelimit(wl))
 217                 return;
 218         va_start(args, fmt);
 219         printk(KERN_WARNING "b43-%s warning: ",
 220                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
 221         vprintk(fmt, args);
 222         va_end(args);
 223 }
 224
 225 #if B43_DEBUG
 226 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
 227 {
 228         va_list args;
 229
 230         va_start(args, fmt);
 231         printk(KERN_DEBUG "b43-%s debug: ",
 232                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
 233         vprintk(fmt, args);
 234         va_end(args);
 235 }
 236 #endif /* DEBUG */
 237
 238 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
 239 {
 240         u32 macctl;
 241
 242         B43_WARN_ON(offset % 4 != 0);
 243
 244         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 245         if (macctl & B43_MACCTL_BE)
 246                 val = swab32(val);
 247
 248         b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
 249         mmiowb();
 250         b43_write32(dev, B43_MMIO_RAM_DATA, val);
 251 }
 252
 253 static inline
 254     void b43_shm_control_word(struct b43_wldev *dev, u16 routing, u16 offset)
 255 {
 256         u32 control;
 257
 258         /* "offset" is the WORD offset. */
 259
 260         control = routing;
 261         control <<= 16;
 262         control |= offset;
 263         b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
 264 }
 265
 266 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
 267 {
 268         u32 ret;
 269
 270         if (routing == B43_SHM_SHARED) {
 271                 B43_WARN_ON(offset & 0x0001);
 272                 if (offset & 0x0003) {
 273                         /* Unaligned access */
 274                         b43_shm_control_word(dev, routing, offset >> 2);
 275                         ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
 276                         ret <<= 16;
 277                         b43_shm_control_word(dev, routing, (offset >> 2) + 1);
 278                         ret |= b43_read16(dev, B43_MMIO_SHM_DATA);
 279
 280                         return ret;
 281                 }
 282                 offset >>= 2;
 283         }
 284         b43_shm_control_word(dev, routing, offset);
 285         ret = b43_read32(dev, B43_MMIO_SHM_DATA);
 286
 287         return ret;
 288 }
 289
 290 u16 b43_shm_read16(struct b43_wldev * dev, u16 routing, u16 offset)
 291 {
 292         u16 ret;
 293
 294         if (routing == B43_SHM_SHARED) {
 295                 B43_WARN_ON(offset & 0x0001);
 296                 if (offset & 0x0003) {
 297                         /* Unaligned access */
 298                         b43_shm_control_word(dev, routing, offset >> 2);
 299                         ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
 300
 301                         return ret;
 302                 }
 303                 offset >>= 2;
 304         }
 305         b43_shm_control_word(dev, routing, offset);
 306         ret = b43_read16(dev, B43_MMIO_SHM_DATA);
 307
 308         return ret;
 309 }
 310
 311 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
 312 {
 313         if (routing == B43_SHM_SHARED) {
 314                 B43_WARN_ON(offset & 0x0001);
 315                 if (offset & 0x0003) {
 316                         /* Unaligned access */
 317                         b43_shm_control_word(dev, routing, offset >> 2);
 318                         mmiowb();
 319                         b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
 320                                     (value >> 16) & 0xffff);
 321                         mmiowb();
 322                         b43_shm_control_word(dev, routing, (offset >> 2) + 1);
 323                         mmiowb();
 324                         b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
 325                         return;
 326                 }
 327                 offset >>= 2;
 328         }
 329         b43_shm_control_word(dev, routing, offset);
 330         mmiowb();
 331         b43_write32(dev, B43_MMIO_SHM_DATA, value);
 332 }
 333
 334 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
 335 {
 336         if (routing == B43_SHM_SHARED) {
 337                 B43_WARN_ON(offset & 0x0001);
 338                 if (offset & 0x0003) {
 339                         /* Unaligned access */
 340                         b43_shm_control_word(dev, routing, offset >> 2);
 341                         mmiowb();
 342                         b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
 343                         return;
 344                 }
 345                 offset >>= 2;
 346         }
 347         b43_shm_control_word(dev, routing, offset);
 348         mmiowb();
 349         b43_write16(dev, B43_MMIO_SHM_DATA, value);
 350 }
 351
 352 /* Read HostFlags */
 353 u32 b43_hf_read(struct b43_wldev * dev)
 354 {
 355         u32 ret;
 356
 357         ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
 358         ret <<= 16;
 359         ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
 360
 361         return ret;
 362 }
 363
 364 /* Write HostFlags */
 365 void b43_hf_write(struct b43_wldev *dev, u32 value)
 366 {
 367         b43_shm_write16(dev, B43_SHM_SHARED,
 368                         B43_SHM_SH_HOSTFLO, (value & 0x0000FFFF));
 369         b43_shm_write16(dev, B43_SHM_SHARED,
 370                         B43_SHM_SH_HOSTFHI, ((value & 0xFFFF0000) >> 16));
 371 }
 372
 373 void b43_tsf_read(struct b43_wldev *dev, u64 * tsf)
 374 {
 375         /* We need to be careful. As we read the TSF from multiple
 376          * registers, we should take care of register overflows.
 377          * In theory, the whole tsf read process should be atomic.
 378          * We try to be atomic here, by restaring the read process,
 379          * if any of the high registers changed (overflew).
 380          */
 381         if (dev->dev->id.revision >= 3) {
 382                 u32 low, high, high2;
 383
 384                 do {
 385                         high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
 386                         low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
 387                         high2 = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
 388                 } while (unlikely(high != high2));
 389
 390                 *tsf = high;
 391                 *tsf <<= 32;
 392                 *tsf |= low;
 393         } else {
 394                 u64 tmp;
 395                 u16 v0, v1, v2, v3;
 396                 u16 test1, test2, test3;
 397
 398                 do {
 399                         v3 = b43_read16(dev, B43_MMIO_TSF_3);
 400                         v2 = b43_read16(dev, B43_MMIO_TSF_2);
 401                         v1 = b43_read16(dev, B43_MMIO_TSF_1);
 402                         v0 = b43_read16(dev, B43_MMIO_TSF_0);
 403
 404                         test3 = b43_read16(dev, B43_MMIO_TSF_3);
 405                         test2 = b43_read16(dev, B43_MMIO_TSF_2);
 406                         test1 = b43_read16(dev, B43_MMIO_TSF_1);
 407                 } while (v3 != test3 || v2 != test2 || v1 != test1);
 408
 409                 *tsf = v3;
 410                 *tsf <<= 48;
 411                 tmp = v2;
 412                 tmp <<= 32;
 413                 *tsf |= tmp;
 414                 tmp = v1;
 415                 tmp <<= 16;
 416                 *tsf |= tmp;
 417                 *tsf |= v0;
 418         }
 419 }
 420
 421 static void b43_time_lock(struct b43_wldev *dev)
 422 {
 423         u32 macctl;
 424
 425         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 426         macctl |= B43_MACCTL_TBTTHOLD;
 427         b43_write32(dev, B43_MMIO_MACCTL, macctl);
 428         /* Commit the write */
 429         b43_read32(dev, B43_MMIO_MACCTL);
 430 }
 431
 432 static void b43_time_unlock(struct b43_wldev *dev)
 433 {
 434         u32 macctl;
 435
 436         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 437         macctl &= ~B43_MACCTL_TBTTHOLD;
 438         b43_write32(dev, B43_MMIO_MACCTL, macctl);
 439         /* Commit the write */
 440         b43_read32(dev, B43_MMIO_MACCTL);
 441 }
 442
 443 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
 444 {
 445         /* Be careful with the in-progress timer.
 446          * First zero out the low register, so we have a full
 447          * register-overflow duration to complete the operation.
 448          */
 449         if (dev->dev->id.revision >= 3) {
 450                 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
 451                 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
 452
 453                 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, 0);
 454                 mmiowb();
 455                 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, hi);
 456                 mmiowb();
 457                 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, lo);
 458         } else {
 459                 u16 v0 = (tsf & 0x000000000000FFFFULL);
 460                 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
 461                 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
 462                 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
 463
 464                 b43_write16(dev, B43_MMIO_TSF_0, 0);
 465                 mmiowb();
 466                 b43_write16(dev, B43_MMIO_TSF_3, v3);
 467                 mmiowb();
 468                 b43_write16(dev, B43_MMIO_TSF_2, v2);
 469                 mmiowb();
 470                 b43_write16(dev, B43_MMIO_TSF_1, v1);
 471                 mmiowb();
 472                 b43_write16(dev, B43_MMIO_TSF_0, v0);
 473         }
 474 }
 475
 476 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
 477 {
 478         b43_time_lock(dev);
 479         b43_tsf_write_locked(dev, tsf);
 480         b43_time_unlock(dev);
 481 }
 482
 483 static
 484 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac)
 485 {
 486         static const u8 zero_addr[ETH_ALEN] = { 0 };
 487         u16 data;
 488
 489         if (!mac)
 490                 mac = zero_addr;
 491
 492         offset |= 0x0020;
 493         b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
 494
 495         data = mac[0];
 496         data |= mac[1] << 8;
 497         b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
 498         data = mac[2];
 499         data |= mac[3] << 8;
 500         b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
 501         data = mac[4];
 502         data |= mac[5] << 8;
 503         b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
 504 }
 505
 506 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
 507 {
 508         const u8 *mac;
 509         const u8 *bssid;
 510         u8 mac_bssid[ETH_ALEN * 2];
 511         int i;
 512         u32 tmp;
 513
 514         bssid = dev->wl->bssid;
 515         mac = dev->wl->mac_addr;
 516
 517         b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
 518
 519         memcpy(mac_bssid, mac, ETH_ALEN);
 520         memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
 521
 522         /* Write our MAC address and BSSID to template ram */
 523         for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
 524                 tmp = (u32) (mac_bssid[i + 0]);
 525                 tmp |= (u32) (mac_bssid[i + 1]) << 8;
 526                 tmp |= (u32) (mac_bssid[i + 2]) << 16;
 527                 tmp |= (u32) (mac_bssid[i + 3]) << 24;
 528                 b43_ram_write(dev, 0x20 + i, tmp);
 529         }
 530 }
 531
 532 static void b43_upload_card_macaddress(struct b43_wldev *dev)
 533 {
 534         b43_write_mac_bssid_templates(dev);
 535         b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
 536 }
 537
 538 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
 539 {
 540         /* slot_time is in usec. */
 541         if (dev->phy.type != B43_PHYTYPE_G)
 542                 return;
 543         b43_write16(dev, 0x684, 510 + slot_time);
 544         b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
 545 }
 546
 547 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
 548 {
 549         b43_set_slot_time(dev, 9);
 550         dev->short_slot = 1;
 551 }
 552
 553 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
 554 {
 555         b43_set_slot_time(dev, 20);
 556         dev->short_slot = 0;
 557 }
 558
 559 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
 560  * Returns the _previously_ enabled IRQ mask.
 561  */
 562 static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask)
 563 {
 564         u32 old_mask;
 565
 566         old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
 567         b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask);
 568
 569         return old_mask;
 570 }
 571
 572 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
 573  * Returns the _previously_ enabled IRQ mask.
 574  */
 575 static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask)
 576 {
 577         u32 old_mask;
 578
 579         old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
 580         b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
 581
 582         return old_mask;
 583 }
 584
 585 /* Synchronize IRQ top- and bottom-half.
 586  * IRQs must be masked before calling this.
 587  * This must not be called with the irq_lock held.
 588  */
 589 static void b43_synchronize_irq(struct b43_wldev *dev)
 590 {
 591         synchronize_irq(dev->dev->irq);
 592         tasklet_kill(&dev->isr_tasklet);
 593 }
 594
 595 /* DummyTransmission function, as documented on
 596  * http://bcm-specs.sipsolutions.net/DummyTransmission
 597  */
 598 void b43_dummy_transmission(struct b43_wldev *dev)
 599 {
 600         struct b43_phy *phy = &dev->phy;
 601         unsigned int i, max_loop;
 602         u16 value;
 603         u32 buffer[5] = {
 604                 0x00000000,
 605                 0x00D40000,
 606                 0x00000000,
 607                 0x01000000,
 608                 0x00000000,
 609         };
 610
 611         switch (phy->type) {
 612         case B43_PHYTYPE_A:
 613                 max_loop = 0x1E;
 614                 buffer[0] = 0x000201CC;
 615                 break;
 616         case B43_PHYTYPE_B:
 617         case B43_PHYTYPE_G:
 618                 max_loop = 0xFA;
 619                 buffer[0] = 0x000B846E;
 620                 break;
 621         default:
 622                 B43_WARN_ON(1);
 623                 return;
 624         }
 625
 626         for (i = 0; i < 5; i++)
 627                 b43_ram_write(dev, i * 4, buffer[i]);
 628
 629         /* Commit writes */
 630         b43_read32(dev, B43_MMIO_MACCTL);
 631
 632         b43_write16(dev, 0x0568, 0x0000);
 633         b43_write16(dev, 0x07C0, 0x0000);
 634         value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0);
 635         b43_write16(dev, 0x050C, value);
 636         b43_write16(dev, 0x0508, 0x0000);
 637         b43_write16(dev, 0x050A, 0x0000);
 638         b43_write16(dev, 0x054C, 0x0000);
 639         b43_write16(dev, 0x056A, 0x0014);
 640         b43_write16(dev, 0x0568, 0x0826);
 641         b43_write16(dev, 0x0500, 0x0000);
 642         b43_write16(dev, 0x0502, 0x0030);
 643
 644         if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
 645                 b43_radio_write16(dev, 0x0051, 0x0017);
 646         for (i = 0x00; i < max_loop; i++) {
 647                 value = b43_read16(dev, 0x050E);
 648                 if (value & 0x0080)
 649                         break;
 650                 udelay(10);
 651         }
 652         for (i = 0x00; i < 0x0A; i++) {
 653                 value = b43_read16(dev, 0x050E);
 654                 if (value & 0x0400)
 655                         break;
 656                 udelay(10);
 657         }
 658         for (i = 0x00; i < 0x0A; i++) {
 659                 value = b43_read16(dev, 0x0690);
 660                 if (!(value & 0x0100))
 661                         break;
 662                 udelay(10);
 663         }
 664         if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
 665                 b43_radio_write16(dev, 0x0051, 0x0037);
 666 }
 667
 668 static void key_write(struct b43_wldev *dev,
 669                       u8 index, u8 algorithm, const u8 * key)
 670 {
 671         unsigned int i;
 672         u32 offset;
 673         u16 value;
 674         u16 kidx;
 675
 676         /* Key index/algo block */
 677         kidx = b43_kidx_to_fw(dev, index);
 678         value = ((kidx << 4) | algorithm);
 679         b43_shm_write16(dev, B43_SHM_SHARED,
 680                         B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
 681
 682         /* Write the key to the Key Table Pointer offset */
 683         offset = dev->ktp + (index * B43_SEC_KEYSIZE);
 684         for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
 685                 value = key[i];
 686                 value |= (u16) (key[i + 1]) << 8;
 687                 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
 688         }
 689 }
 690
 691 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr)
 692 {
 693         u32 addrtmp[2] = { 0, 0, };
 694         u8 per_sta_keys_start = 8;
 695
 696         if (b43_new_kidx_api(dev))
 697                 per_sta_keys_start = 4;
 698
 699         B43_WARN_ON(index < per_sta_keys_start);
 700         /* We have two default TX keys and possibly two default RX keys.
 701          * Physical mac 0 is mapped to physical key 4 or 8, depending
 702          * on the firmware version.
 703          * So we must adjust the index here.
 704          */
 705         index -= per_sta_keys_start;
 706
 707         if (addr) {
 708                 addrtmp[0] = addr[0];
 709                 addrtmp[0] |= ((u32) (addr[1]) << 8);
 710                 addrtmp[0] |= ((u32) (addr[2]) << 16);
 711                 addrtmp[0] |= ((u32) (addr[3]) << 24);
 712                 addrtmp[1] = addr[4];
 713                 addrtmp[1] |= ((u32) (addr[5]) << 8);
 714         }
 715
 716         if (dev->dev->id.revision >= 5) {
 717                 /* Receive match transmitter address mechanism */
 718                 b43_shm_write32(dev, B43_SHM_RCMTA,
 719                                 (index * 2) + 0, addrtmp[0]);
 720                 b43_shm_write16(dev, B43_SHM_RCMTA,
 721                                 (index * 2) + 1, addrtmp[1]);
 722         } else {
 723                 /* RXE (Receive Engine) and
 724                  * PSM (Programmable State Machine) mechanism
 725                  */
 726                 if (index < 8) {
 727                         /* TODO write to RCM 16, 19, 22 and 25 */
 728                 } else {
 729                         b43_shm_write32(dev, B43_SHM_SHARED,
 730                                         B43_SHM_SH_PSM + (index * 6) + 0,
 731                                         addrtmp[0]);
 732                         b43_shm_write16(dev, B43_SHM_SHARED,
 733                                         B43_SHM_SH_PSM + (index * 6) + 4,
 734                                         addrtmp[1]);
 735                 }
 736         }
 737 }
 738
 739 static void do_key_write(struct b43_wldev *dev,
 740                          u8 index, u8 algorithm,
 741                          const u8 * key, size_t key_len, const u8 * mac_addr)
 742 {
 743         u8 buf[B43_SEC_KEYSIZE] = { 0, };
 744         u8 per_sta_keys_start = 8;
 745
 746         if (b43_new_kidx_api(dev))
 747                 per_sta_keys_start = 4;
 748
 749         B43_WARN_ON(index >= dev->max_nr_keys);
 750         B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
 751
 752         if (index >= per_sta_keys_start)
 753                 keymac_write(dev, index, NULL); /* First zero out mac. */
 754         if (key)
 755                 memcpy(buf, key, key_len);
 756         key_write(dev, index, algorithm, buf);
 757         if (index >= per_sta_keys_start)
 758                 keymac_write(dev, index, mac_addr);
 759
 760         dev->key[index].algorithm = algorithm;
 761 }
 762
 763 static int b43_key_write(struct b43_wldev *dev,
 764                          int index, u8 algorithm,
 765                          const u8 * key, size_t key_len,
 766                          const u8 * mac_addr,
 767                          struct ieee80211_key_conf *keyconf)
 768 {
 769         int i;
 770         int sta_keys_start;
 771
 772         if (key_len > B43_SEC_KEYSIZE)
 773                 return -EINVAL;
 774         for (i = 0; i < dev->max_nr_keys; i++) {
 775                 /* Check that we don't already have this key. */
 776                 B43_WARN_ON(dev->key[i].keyconf == keyconf);
 777         }
 778         if (index < 0) {
 779                 /* Either pairwise key or address is 00:00:00:00:00:00
 780                  * for transmit-only keys. Search the index. */
 781                 if (b43_new_kidx_api(dev))
 782                         sta_keys_start = 4;
 783                 else
 784                         sta_keys_start = 8;
 785                 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
 786                         if (!dev->key[i].keyconf) {
 787                                 /* found empty */
 788                                 index = i;
 789                                 break;
 790                         }
 791                 }
 792                 if (index < 0) {
 793                         b43err(dev->wl, "Out of hardware key memory\n");
 794                         return -ENOSPC;
 795                 }
 796         } else
 797                 B43_WARN_ON(index > 3);
 798
 799         do_key_write(dev, index, algorithm, key, key_len, mac_addr);
 800         if ((index <= 3) && !b43_new_kidx_api(dev)) {
 801                 /* Default RX key */
 802                 B43_WARN_ON(mac_addr);
 803                 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
 804         }
 805         keyconf->hw_key_idx = index;
 806         dev->key[index].keyconf = keyconf;
 807
 808         return 0;
 809 }
 810
 811 static int b43_key_clear(struct b43_wldev *dev, int index)
 812 {
 813         if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys)))
 814                 return -EINVAL;
 815         do_key_write(dev, index, B43_SEC_ALGO_NONE,
 816                      NULL, B43_SEC_KEYSIZE, NULL);
 817         if ((index <= 3) && !b43_new_kidx_api(dev)) {
 818                 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
 819                              NULL, B43_SEC_KEYSIZE, NULL);
 820         }
 821         dev->key[index].keyconf = NULL;
 822
 823         return 0;
 824 }
 825
 826 static void b43_clear_keys(struct b43_wldev *dev)
 827 {
 828         int i;
 829
 830         for (i = 0; i < dev->max_nr_keys; i++)
 831                 b43_key_clear(dev, i);
 832 }
 833
 834 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
 835 {
 836         u32 macctl;
 837         u16 ucstat;
 838         bool hwps;
 839         bool awake;
 840         int i;
 841
 842         B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
 843                     (ps_flags & B43_PS_DISABLED));
 844         B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
 845
 846         if (ps_flags & B43_PS_ENABLED) {
 847                 hwps = 1;
 848         } else if (ps_flags & B43_PS_DISABLED) {
 849                 hwps = 0;
 850         } else {
 851                 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
 852                 //      and thus is not an AP and we are associated, set bit 25
 853         }
 854         if (ps_flags & B43_PS_AWAKE) {
 855                 awake = 1;
 856         } else if (ps_flags & B43_PS_ASLEEP) {
 857                 awake = 0;
 858         } else {
 859                 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
 860                 //      or we are associated, or FIXME, or the latest PS-Poll packet sent was
 861                 //      successful, set bit26
 862         }
 863
 864 /* FIXME: For now we force awake-on and hwps-off */
 865         hwps = 0;
 866         awake = 1;
 867
 868         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 869         if (hwps)
 870                 macctl |= B43_MACCTL_HWPS;
 871         else
 872                 macctl &= ~B43_MACCTL_HWPS;
 873         if (awake)
 874                 macctl |= B43_MACCTL_AWAKE;
 875         else
 876                 macctl &= ~B43_MACCTL_AWAKE;
 877         b43_write32(dev, B43_MMIO_MACCTL, macctl);
 878         /* Commit write */
 879         b43_read32(dev, B43_MMIO_MACCTL);
 880         if (awake && dev->dev->id.revision >= 5) {
 881                 /* Wait for the microcode to wake up. */
 882                 for (i = 0; i < 100; i++) {
 883                         ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
 884                                                 B43_SHM_SH_UCODESTAT);
 885                         if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
 886                                 break;
 887                         udelay(10);
 888                 }
 889         }
 890 }
 891
 892 /* Turn the Analog ON/OFF */
 893 static void b43_switch_analog(struct b43_wldev *dev, int on)
 894 {
 895         b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
 896 }
 897
 898 void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
 899 {
 900         u32 tmslow;
 901         u32 macctl;
 902
 903         flags |= B43_TMSLOW_PHYCLKEN;
 904         flags |= B43_TMSLOW_PHYRESET;
 905         ssb_device_enable(dev->dev, flags);
 906         msleep(2);              /* Wait for the PLL to turn on. */
 907
 908         /* Now take the PHY out of Reset again */
 909         tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
 910         tmslow |= SSB_TMSLOW_FGC;
 911         tmslow &= ~B43_TMSLOW_PHYRESET;
 912         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
 913         ssb_read32(dev->dev, SSB_TMSLOW);       /* flush */
 914         msleep(1);
 915         tmslow &= ~SSB_TMSLOW_FGC;
 916         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
 917         ssb_read32(dev->dev, SSB_TMSLOW);       /* flush */
 918         msleep(1);
 919
 920         /* Turn Analog ON */
 921         b43_switch_analog(dev, 1);
 922
 923         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 924         macctl &= ~B43_MACCTL_GMODE;
 925         if (flags & B43_TMSLOW_GMODE)
 926                 macctl |= B43_MACCTL_GMODE;
 927         macctl |= B43_MACCTL_IHR_ENABLED;
 928         b43_write32(dev, B43_MMIO_MACCTL, macctl);
 929 }
 930
 931 static void handle_irq_transmit_status(struct b43_wldev *dev)
 932 {
 933         u32 v0, v1;
 934         u16 tmp;
 935         struct b43_txstatus stat;
 936
 937         while (1) {
 938                 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
 939                 if (!(v0 & 0x00000001))
 940                         break;
 941                 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
 942
 943                 stat.cookie = (v0 >> 16);
 944                 stat.seq = (v1 & 0x0000FFFF);
 945                 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
 946                 tmp = (v0 & 0x0000FFFF);
 947                 stat.frame_count = ((tmp & 0xF000) >> 12);
 948                 stat.rts_count = ((tmp & 0x0F00) >> 8);
 949                 stat.supp_reason = ((tmp & 0x001C) >> 2);
 950                 stat.pm_indicated = !!(tmp & 0x0080);
 951                 stat.intermediate = !!(tmp & 0x0040);
 952                 stat.for_ampdu = !!(tmp & 0x0020);
 953                 stat.acked = !!(tmp & 0x0002);
 954
 955                 b43_handle_txstatus(dev, &stat);
 956         }
 957 }
 958
 959 static void drain_txstatus_queue(struct b43_wldev *dev)
 960 {
 961         u32 dummy;
 962
 963         if (dev->dev->id.revision < 5)
 964                 return;
 965         /* Read all entries from the microcode TXstatus FIFO
 966          * and throw them away.
 967          */
 968         while (1) {
 969                 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
 970                 if (!(dummy & 0x00000001))
 971                         break;
 972                 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
 973         }
 974 }
 975
 976 static u32 b43_jssi_read(struct b43_wldev *dev)
 977 {
 978         u32 val = 0;
 979
 980         val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
 981         val <<= 16;
 982         val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
 983
 984         return val;
 985 }
 986
 987 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
 988 {
 989         b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
 990         b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
 991 }
 992
 993 static void b43_generate_noise_sample(struct b43_wldev *dev)
 994 {
 995         b43_jssi_write(dev, 0x7F7F7F7F);
 996         b43_write32(dev, B43_MMIO_MACCMD,
 997                     b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
 998         B43_WARN_ON(dev->noisecalc.channel_at_start != dev->phy.channel);
 999 }
1000
1001 static void b43_calculate_link_quality(struct b43_wldev *dev)
1002 {
1003         /* Top half of Link Quality calculation. */
1004
1005         if (dev->noisecalc.calculation_running)
1006                 return;
1007         dev->noisecalc.channel_at_start = dev->phy.channel;
1008         dev->noisecalc.calculation_running = 1;
1009         dev->noisecalc.nr_samples = 0;
1010
1011         b43_generate_noise_sample(dev);
1012 }
1013
1014 static void handle_irq_noise(struct b43_wldev *dev)
1015 {
1016         struct b43_phy *phy = &dev->phy;
1017         u16 tmp;
1018         u8 noise[4];
1019         u8 i, j;
1020         s32 average;
1021
1022         /* Bottom half of Link Quality calculation. */
1023
1024         B43_WARN_ON(!dev->noisecalc.calculation_running);
1025         if (dev->noisecalc.channel_at_start != phy->channel)
1026                 goto drop_calculation;
1027         *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1028         if (noise[0] == 0x7F || noise[1] == 0x7F ||
1029             noise[2] == 0x7F || noise[3] == 0x7F)
1030                 goto generate_new;
1031
1032         /* Get the noise samples. */
1033         B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1034         i = dev->noisecalc.nr_samples;
1035         noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1036         noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1037         noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1038         noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1039         dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1040         dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1041         dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1042         dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1043         dev->noisecalc.nr_samples++;
1044         if (dev->noisecalc.nr_samples == 8) {
1045                 /* Calculate the Link Quality by the noise samples. */
1046                 average = 0;
1047                 for (i = 0; i < 8; i++) {
1048                         for (j = 0; j < 4; j++)
1049                                 average += dev->noisecalc.samples[i][j];
1050                 }
1051                 average /= (8 * 4);
1052                 average *= 125;
1053                 average += 64;
1054                 average /= 128;
1055                 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1056                 tmp = (tmp / 128) & 0x1F;
1057                 if (tmp >= 8)
1058                         average += 2;
1059                 else
1060                         average -= 25;
1061                 if (tmp == 8)
1062                         average -= 72;
1063                 else
1064                         average -= 48;
1065
1066                 dev->stats.link_noise = average;
1067               drop_calculation:
1068                 dev->noisecalc.calculation_running = 0;
1069                 return;
1070         }
1071       generate_new:
1072         b43_generate_noise_sample(dev);
1073 }
1074
1075 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1076 {
1077         if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
1078                 ///TODO: PS TBTT
1079         } else {
1080                 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1081                         b43_power_saving_ctl_bits(dev, 0);
1082         }
1083         if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
1084                 dev->dfq_valid = 1;
1085 }
1086
1087 static void handle_irq_atim_end(struct b43_wldev *dev)
1088 {
1089         if (dev->dfq_valid) {
1090                 b43_write32(dev, B43_MMIO_MACCMD,
1091                             b43_read32(dev, B43_MMIO_MACCMD)
1092                             | B43_MACCMD_DFQ_VALID);
1093                 dev->dfq_valid = 0;
1094         }
1095 }
1096
1097 static void handle_irq_pmq(struct b43_wldev *dev)
1098 {
1099         u32 tmp;
1100
1101         //TODO: AP mode.
1102
1103         while (1) {
1104                 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1105                 if (!(tmp & 0x00000008))
1106                         break;
1107         }
1108         /* 16bit write is odd, but correct. */
1109         b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1110 }
1111
1112 static void b43_write_template_common(struct b43_wldev *dev,
1113                                       const u8 * data, u16 size,
1114                                       u16 ram_offset,
1115                                       u16 shm_size_offset, u8 rate)
1116 {
1117         u32 i, tmp;
1118         struct b43_plcp_hdr4 plcp;
1119
1120         plcp.data = 0;
1121         b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1122         b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1123         ram_offset += sizeof(u32);
1124         /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1125          * So leave the first two bytes of the next write blank.
1126          */
1127         tmp = (u32) (data[0]) << 16;
1128         tmp |= (u32) (data[1]) << 24;
1129         b43_ram_write(dev, ram_offset, tmp);
1130         ram_offset += sizeof(u32);
1131         for (i = 2; i < size; i += sizeof(u32)) {
1132                 tmp = (u32) (data[i + 0]);
1133                 if (i + 1 < size)
1134                         tmp |= (u32) (data[i + 1]) << 8;
1135                 if (i + 2 < size)
1136                         tmp |= (u32) (data[i + 2]) << 16;
1137                 if (i + 3 < size)
1138                         tmp |= (u32) (data[i + 3]) << 24;
1139                 b43_ram_write(dev, ram_offset + i - 2, tmp);
1140         }
1141         b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1142                         size + sizeof(struct b43_plcp_hdr6));
1143 }
1144
1145 static void b43_write_beacon_template(struct b43_wldev *dev,
1146                                       u16 ram_offset,
1147                                       u16 shm_size_offset, u8 rate)
1148 {
1149         int len;
1150         const u8 *data;
1151
1152         B43_WARN_ON(!dev->cached_beacon);
1153         len = min((size_t) dev->cached_beacon->len,
1154                   0x200 - sizeof(struct b43_plcp_hdr6));
1155         data = (const u8 *)(dev->cached_beacon->data);
1156         b43_write_template_common(dev, data,
1157                                   len, ram_offset, shm_size_offset, rate);
1158 }
1159
1160 static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
1161                                       u16 shm_offset, u16 size, u8 rate)
1162 {
1163         struct b43_plcp_hdr4 plcp;
1164         u32 tmp;
1165         __le16 dur;
1166
1167         plcp.data = 0;
1168         b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1169         dur = ieee80211_generic_frame_duration(dev->wl->hw,
1170                                                dev->wl->if_id, size,
1171                                                B43_RATE_TO_BASE100KBPS(rate));
1172         /* Write PLCP in two parts and timing for packet transfer */
1173         tmp = le32_to_cpu(plcp.data);
1174         b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF);
1175         b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16);
1176         b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur));
1177 }
1178
1179 /* Instead of using custom probe response template, this function
1180  * just patches custom beacon template by:
1181  * 1) Changing packet type
1182  * 2) Patching duration field
1183  * 3) Stripping TIM
1184  */
1185 static u8 *b43_generate_probe_resp(struct b43_wldev *dev,
1186                                    u16 * dest_size, u8 rate)
1187 {
1188         const u8 *src_data;
1189         u8 *dest_data;
1190         u16 src_size, elem_size, src_pos, dest_pos;
1191         __le16 dur;
1192         struct ieee80211_hdr *hdr;
1193
1194         B43_WARN_ON(!dev->cached_beacon);
1195         src_size = dev->cached_beacon->len;
1196         src_data = (const u8 *)dev->cached_beacon->data;
1197
1198         if (unlikely(src_size < 0x24)) {
1199                 b43dbg(dev->wl, "b43_generate_probe_resp: " "invalid beacon\n");
1200                 return NULL;
1201         }
1202
1203         dest_data = kmalloc(src_size, GFP_ATOMIC);
1204         if (unlikely(!dest_data))
1205                 return NULL;
1206
1207         /* 0x24 is offset of first variable-len Information-Element
1208          * in beacon frame.
1209          */
1210         memcpy(dest_data, src_data, 0x24);
1211         src_pos = dest_pos = 0x24;
1212         for (; src_pos < src_size - 2; src_pos += elem_size) {
1213                 elem_size = src_data[src_pos + 1] + 2;
1214                 if (src_data[src_pos] != 0x05) {        /* TIM */
1215                         memcpy(dest_data + dest_pos, src_data + src_pos,
1216                                elem_size);
1217                         dest_pos += elem_size;
1218                 }
1219         }
1220         *dest_size = dest_pos;
1221         hdr = (struct ieee80211_hdr *)dest_data;
1222
1223         /* Set the frame control. */
1224         hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1225                                          IEEE80211_STYPE_PROBE_RESP);
1226         dur = ieee80211_generic_frame_duration(dev->wl->hw,
1227                                                dev->wl->if_id, *dest_size,
1228                                                B43_RATE_TO_BASE100KBPS(rate));
1229         hdr->duration_id = dur;
1230
1231         return dest_data;
1232 }
1233
1234 static void b43_write_probe_resp_template(struct b43_wldev *dev,
1235                                           u16 ram_offset,
1236                                           u16 shm_size_offset, u8 rate)
1237 {
1238         u8 *probe_resp_data;
1239         u16 size;
1240
1241         B43_WARN_ON(!dev->cached_beacon);
1242         size = dev->cached_beacon->len;
1243         probe_resp_data = b43_generate_probe_resp(dev, &size, rate);
1244         if (unlikely(!probe_resp_data))
1245                 return;
1246
1247         /* Looks like PLCP headers plus packet timings are stored for
1248          * all possible basic rates
1249          */
1250         b43_write_probe_resp_plcp(dev, 0x31A, size, B43_CCK_RATE_1MB);
1251         b43_write_probe_resp_plcp(dev, 0x32C, size, B43_CCK_RATE_2MB);
1252         b43_write_probe_resp_plcp(dev, 0x33E, size, B43_CCK_RATE_5MB);
1253         b43_write_probe_resp_plcp(dev, 0x350, size, B43_CCK_RATE_11MB);
1254
1255         size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6));
1256         b43_write_template_common(dev, probe_resp_data,
1257                                   size, ram_offset, shm_size_offset, rate);
1258         kfree(probe_resp_data);
1259 }
1260
1261 static int b43_refresh_cached_beacon(struct b43_wldev *dev,
1262                                      struct sk_buff *beacon)
1263 {
1264         if (dev->cached_beacon)
1265                 kfree_skb(dev->cached_beacon);
1266         dev->cached_beacon = beacon;
1267
1268         return 0;
1269 }
1270
1271 static void b43_update_templates(struct b43_wldev *dev)
1272 {
1273         u32 cmd;
1274
1275         B43_WARN_ON(!dev->cached_beacon);
1276
1277         b43_write_beacon_template(dev, 0x68, 0x18, B43_CCK_RATE_1MB);
1278         b43_write_beacon_template(dev, 0x468, 0x1A, B43_CCK_RATE_1MB);
1279         b43_write_probe_resp_template(dev, 0x268, 0x4A, B43_CCK_RATE_11MB);
1280
1281         cmd = b43_read32(dev, B43_MMIO_MACCMD);
1282         cmd |= B43_MACCMD_BEACON0_VALID | B43_MACCMD_BEACON1_VALID;
1283         b43_write32(dev, B43_MMIO_MACCMD, cmd);
1284 }
1285
1286 static void b43_refresh_templates(struct b43_wldev *dev, struct sk_buff *beacon)
1287 {
1288         int err;
1289
1290         err = b43_refresh_cached_beacon(dev, beacon);
1291         if (unlikely(err))
1292                 return;
1293         b43_update_templates(dev);
1294 }
1295
1296 static void b43_set_ssid(struct b43_wldev *dev, const u8 * ssid, u8 ssid_len)
1297 {
1298         u32 tmp;
1299         u16 i, len;
1300
1301         len = min((u16) ssid_len, (u16) 0x100);
1302         for (i = 0; i < len; i += sizeof(u32)) {
1303                 tmp = (u32) (ssid[i + 0]);
1304                 if (i + 1 < len)
1305                         tmp |= (u32) (ssid[i + 1]) << 8;
1306                 if (i + 2 < len)
1307                         tmp |= (u32) (ssid[i + 2]) << 16;
1308                 if (i + 3 < len)
1309                         tmp |= (u32) (ssid[i + 3]) << 24;
1310                 b43_shm_write32(dev, B43_SHM_SHARED, 0x380 + i, tmp);
1311         }
1312         b43_shm_write16(dev, B43_SHM_SHARED, 0x48, len);
1313 }
1314
1315 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1316 {
1317         b43_time_lock(dev);
1318         if (dev->dev->id.revision >= 3) {
1319                 b43_write32(dev, 0x188, (beacon_int << 16));
1320         } else {
1321                 b43_write16(dev, 0x606, (beacon_int >> 6));
1322                 b43_write16(dev, 0x610, beacon_int);
1323         }
1324         b43_time_unlock(dev);
1325 }
1326
1327 static void handle_irq_beacon(struct b43_wldev *dev)
1328 {
1329         u32 status;
1330
1331         if (!b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
1332                 return;
1333
1334         dev->irq_savedstate &= ~B43_IRQ_BEACON;
1335         status = b43_read32(dev, B43_MMIO_MACCMD);
1336
1337         if (!dev->cached_beacon || ((status & 0x1) && (status & 0x2))) {
1338                 /* ACK beacon IRQ. */
1339                 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1340                 dev->irq_savedstate |= B43_IRQ_BEACON;
1341                 if (dev->cached_beacon)
1342                         kfree_skb(dev->cached_beacon);
1343                 dev->cached_beacon = NULL;
1344                 return;
1345         }
1346         if (!(status & 0x1)) {
1347                 b43_write_beacon_template(dev, 0x68, 0x18, B43_CCK_RATE_1MB);
1348                 status |= 0x1;
1349                 b43_write32(dev, B43_MMIO_MACCMD, status);
1350         }
1351         if (!(status & 0x2)) {
1352                 b43_write_beacon_template(dev, 0x468, 0x1A, B43_CCK_RATE_1MB);
1353                 status |= 0x2;
1354                 b43_write32(dev, B43_MMIO_MACCMD, status);
1355         }
1356 }
1357
1358 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1359 {
1360         //TODO
1361 }
1362
1363 /* Interrupt handler bottom-half */
1364 static void b43_interrupt_tasklet(struct b43_wldev *dev)
1365 {
1366         u32 reason;
1367         u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1368         u32 merged_dma_reason = 0;
1369         int i;
1370         unsigned long flags;
1371
1372         spin_lock_irqsave(&dev->wl->irq_lock, flags);
1373
1374         B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
1375
1376         reason = dev->irq_reason;
1377         for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1378                 dma_reason[i] = dev->dma_reason[i];
1379                 merged_dma_reason |= dma_reason[i];
1380         }
1381
1382         if (unlikely(reason & B43_IRQ_MAC_TXERR))
1383                 b43err(dev->wl, "MAC transmission error\n");
1384
1385         if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1386                 b43err(dev->wl, "PHY transmission error\n");
1387                 rmb();
1388                 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1389                         atomic_set(&dev->phy.txerr_cnt,
1390                                    B43_PHY_TX_BADNESS_LIMIT);
1391                         b43err(dev->wl, "Too many PHY TX errors, "
1392                                         "restarting the controller\n");
1393                         b43_controller_restart(dev, "PHY TX errors");
1394                 }
1395         }
1396
1397         if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1398                                           B43_DMAIRQ_NONFATALMASK))) {
1399                 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1400                         b43err(dev->wl, "Fatal DMA error: "
1401                                "0x%08X, 0x%08X, 0x%08X, "
1402                                "0x%08X, 0x%08X, 0x%08X\n",
1403                                dma_reason[0], dma_reason[1],
1404                                dma_reason[2], dma_reason[3],
1405                                dma_reason[4], dma_reason[5]);
1406                         b43_controller_restart(dev, "DMA error");
1407                         mmiowb();
1408                         spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1409                         return;
1410                 }
1411                 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1412                         b43err(dev->wl, "DMA error: "
1413                                "0x%08X, 0x%08X, 0x%08X, "
1414                                "0x%08X, 0x%08X, 0x%08X\n",
1415                                dma_reason[0], dma_reason[1],
1416                                dma_reason[2], dma_reason[3],
1417                                dma_reason[4], dma_reason[5]);
1418                 }
1419         }
1420
1421         if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1422                 handle_irq_ucode_debug(dev);
1423         if (reason & B43_IRQ_TBTT_INDI)
1424                 handle_irq_tbtt_indication(dev);
1425         if (reason & B43_IRQ_ATIM_END)
1426                 handle_irq_atim_end(dev);
1427         if (reason & B43_IRQ_BEACON)
1428                 handle_irq_beacon(dev);
1429         if (reason & B43_IRQ_PMQ)
1430                 handle_irq_pmq(dev);
1431         if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1432                 ;/* TODO */
1433         if (reason & B43_IRQ_NOISESAMPLE_OK)
1434                 handle_irq_noise(dev);
1435
1436         /* Check the DMA reason registers for received data. */
1437         if (dma_reason[0] & B43_DMAIRQ_RX_DONE)
1438                 b43_dma_rx(dev->dma.rx_ring0);
1439         if (dma_reason[3] & B43_DMAIRQ_RX_DONE)
1440                 b43_dma_rx(dev->dma.rx_ring3);
1441         B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1442         B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1443         B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1444         B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1445
1446         if (reason & B43_IRQ_TX_OK)
1447                 handle_irq_transmit_status(dev);
1448
1449         b43_interrupt_enable(dev, dev->irq_savedstate);
1450         mmiowb();
1451         spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1452 }
1453
1454 static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
1455 {
1456         b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1457
1458         b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1459         b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1460         b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1461         b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1462         b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1463         b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1464 }
1465
1466 /* Interrupt handler top-half */
1467 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1468 {
1469         irqreturn_t ret = IRQ_NONE;
1470         struct b43_wldev *dev = dev_id;
1471         u32 reason;
1472
1473         if (!dev)
1474                 return IRQ_NONE;
1475
1476         spin_lock(&dev->wl->irq_lock);
1477
1478         if (b43_status(dev) < B43_STAT_STARTED)
1479                 goto out;
1480         reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1481         if (reason == 0xffffffff)       /* shared IRQ */
1482                 goto out;
1483         ret = IRQ_HANDLED;
1484         reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1485         if (!reason)
1486                 goto out;
1487
1488         dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1489             & 0x0001DC00;
1490         dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1491             & 0x0000DC00;
1492         dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1493             & 0x0000DC00;
1494         dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1495             & 0x0001DC00;
1496         dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1497             & 0x0000DC00;
1498         dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1499             & 0x0000DC00;
1500
1501         b43_interrupt_ack(dev, reason);
1502         /* disable all IRQs. They are enabled again in the bottom half. */
1503         dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
1504         /* save the reason code and call our bottom half. */
1505         dev->irq_reason = reason;
1506         tasklet_schedule(&dev->isr_tasklet);
1507       out:
1508         mmiowb();
1509         spin_unlock(&dev->wl->irq_lock);
1510
1511         return ret;
1512 }
1513
1514 static void b43_release_firmware(struct b43_wldev *dev)
1515 {
1516         release_firmware(dev->fw.ucode);
1517         dev->fw.ucode = NULL;
1518         release_firmware(dev->fw.pcm);
1519         dev->fw.pcm = NULL;
1520         release_firmware(dev->fw.initvals);
1521         dev->fw.initvals = NULL;
1522         release_firmware(dev->fw.initvals_band);
1523         dev->fw.initvals_band = NULL;
1524 }
1525
1526 static void b43_print_fw_helptext(struct b43_wl *wl)
1527 {
1528         b43err(wl, "You must go to "
1529                "http://linuxwireless.org/en/users/Drivers/b43#devicefirmware "
1530                "and download the correct firmware (version 4).\n");
1531 }
1532
1533 static int do_request_fw(struct b43_wldev *dev,
1534                          const char *name,
1535                          const struct firmware **fw)
1536 {
1537         char path[sizeof(modparam_fwpostfix) + 32];
1538         struct b43_fw_header *hdr;
1539         u32 size;
1540         int err;
1541
1542         if (!name)
1543                 return 0;
1544
1545         snprintf(path, ARRAY_SIZE(path),
1546                  "b43%s/%s.fw",
1547                  modparam_fwpostfix, name);
1548         err = request_firmware(fw, path, dev->dev->dev);
1549         if (err) {
1550                 b43err(dev->wl, "Firmware file \"%s\" not found "
1551                        "or load failed.\n", path);
1552                 return err;
1553         }
1554         if ((*fw)->size < sizeof(struct b43_fw_header))
1555                 goto err_format;
1556         hdr = (struct b43_fw_header *)((*fw)->data);
1557         switch (hdr->type) {
1558         case B43_FW_TYPE_UCODE:
1559         case B43_FW_TYPE_PCM:
1560                 size = be32_to_cpu(hdr->size);
1561                 if (size != (*fw)->size - sizeof(struct b43_fw_header))
1562                         goto err_format;
1563                 /* fallthrough */
1564         case B43_FW_TYPE_IV:
1565                 if (hdr->ver != 1)
1566                         goto err_format;
1567                 break;
1568         default:
1569                 goto err_format;
1570         }
1571
1572         return err;
1573
1574 err_format:
1575         b43err(dev->wl, "Firmware file \"%s\" format error.\n", path);
1576         return -EPROTO;
1577 }
1578
1579 static int b43_request_firmware(struct b43_wldev *dev)
1580 {
1581         struct b43_firmware *fw = &dev->fw;
1582         const u8 rev = dev->dev->id.revision;
1583         const char *filename;
1584         u32 tmshigh;
1585         int err;
1586
1587         tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
1588         if (!fw->ucode) {
1589                 if ((rev >= 5) && (rev <= 10))
1590                         filename = "ucode5";
1591                 else if ((rev >= 11) && (rev <= 12))
1592                         filename = "ucode11";
1593                 else if (rev >= 13)
1594                         filename = "ucode13";
1595                 else
1596                         goto err_no_ucode;
1597                 err = do_request_fw(dev, filename, &fw->ucode);
1598                 if (err)
1599                         goto err_load;
1600         }
1601         if (!fw->pcm) {
1602                 if ((rev >= 5) && (rev <= 10))
1603                         filename = "pcm5";
1604                 else if (rev >= 11)
1605                         filename = NULL;
1606                 else
1607                         goto err_no_pcm;
1608                 err = do_request_fw(dev, filename, &fw->pcm);
1609                 if (err)
1610                         goto err_load;
1611         }
1612         if (!fw->initvals) {
1613                 switch (dev->phy.type) {
1614                 case B43_PHYTYPE_A:
1615                         if ((rev >= 5) && (rev <= 10)) {
1616                                 if (tmshigh & B43_TMSHIGH_GPHY)
1617                                         filename = "a0g1initvals5";
1618                                 else
1619                                         filename = "a0g0initvals5";
1620                         } else
1621                                 goto err_no_initvals;
1622                         break;
1623                 case B43_PHYTYPE_G:
1624                         if ((rev >= 5) && (rev <= 10))
1625                                 filename = "b0g0initvals5";
1626                         else if (rev >= 13)
1627                                 filename = "lp0initvals13";
1628                         else
1629                                 goto err_no_initvals;
1630                         break;
1631                 default:
1632                         goto err_no_initvals;
1633                 }
1634                 err = do_request_fw(dev, filename, &fw->initvals);
1635                 if (err)
1636                         goto err_load;
1637         }
1638         if (!fw->initvals_band) {
1639                 switch (dev->phy.type) {
1640                 case B43_PHYTYPE_A:
1641                         if ((rev >= 5) && (rev <= 10)) {
1642                                 if (tmshigh & B43_TMSHIGH_GPHY)
1643                                         filename = "a0g1bsinitvals5";
1644                                 else
1645                                         filename = "a0g0bsinitvals5";
1646                         } else if (rev >= 11)
1647                                 filename = NULL;
1648                         else
1649                                 goto err_no_initvals;
1650                         break;
1651                 case B43_PHYTYPE_G:
1652                         if ((rev >= 5) && (rev <= 10))
1653                                 filename = "b0g0bsinitvals5";
1654                         else if (rev >= 11)
1655                                 filename = NULL;
1656                         else
1657                                 goto err_no_initvals;
1658                         break;
1659                 default:
1660                         goto err_no_initvals;
1661                 }
1662                 err = do_request_fw(dev, filename, &fw->initvals_band);
1663                 if (err)
1664                         goto err_load;
1665         }
1666
1667         return 0;
1668
1669 err_load:
1670         b43_print_fw_helptext(dev->wl);
1671         goto error;
1672
1673 err_no_ucode:
1674         err = -ENODEV;
1675         b43err(dev->wl, "No microcode available for core rev %u\n", rev);
1676         goto error;
1677
1678 err_no_pcm:
1679         err = -ENODEV;
1680         b43err(dev->wl, "No PCM available for core rev %u\n", rev);
1681         goto error;
1682
1683 err_no_initvals:
1684         err = -ENODEV;
1685         b43err(dev->wl, "No Initial Values firmware file for PHY %u, "
1686                "core rev %u\n", dev->phy.type, rev);
1687         goto error;
1688
1689 error:
1690         b43_release_firmware(dev);
1691         return err;
1692 }
1693
1694 static int b43_upload_microcode(struct b43_wldev *dev)
1695 {
1696         const size_t hdr_len = sizeof(struct b43_fw_header);
1697         const __be32 *data;
1698         unsigned int i, len;
1699         u16 fwrev, fwpatch, fwdate, fwtime;
1700         u32 tmp;
1701         int err = 0;
1702
1703         /* Upload Microcode. */
1704         data = (__be32 *) (dev->fw.ucode->data + hdr_len);
1705         len = (dev->fw.ucode->size - hdr_len) / sizeof(__be32);
1706         b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
1707         for (i = 0; i < len; i++) {
1708                 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1709                 udelay(10);
1710         }
1711
1712         if (dev->fw.pcm) {
1713                 /* Upload PCM data. */
1714                 data = (__be32 *) (dev->fw.pcm->data + hdr_len);
1715                 len = (dev->fw.pcm->size - hdr_len) / sizeof(__be32);
1716                 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
1717                 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
1718                 /* No need for autoinc bit in SHM_HW */
1719                 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
1720                 for (i = 0; i < len; i++) {
1721                         b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1722                         udelay(10);
1723                 }
1724         }
1725
1726         b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1727         b43_write32(dev, B43_MMIO_MACCTL,
1728                     B43_MACCTL_PSM_RUN |
1729                     B43_MACCTL_IHR_ENABLED | B43_MACCTL_INFRA);
1730
1731         /* Wait for the microcode to load and respond */
1732         i = 0;
1733         while (1) {
1734                 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1735                 if (tmp == B43_IRQ_MAC_SUSPENDED)
1736                         break;
1737                 i++;
1738                 if (i >= 50) {
1739                         b43err(dev->wl, "Microcode not responding\n");
1740                         b43_print_fw_helptext(dev->wl);
1741                         err = -ENODEV;
1742                         goto out;
1743                 }
1744                 udelay(10);
1745         }
1746         b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);       /* dummy read */
1747
1748         /* Get and check the revisions. */
1749         fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
1750         fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
1751         fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
1752         fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
1753
1754         if (fwrev <= 0x128) {
1755                 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
1756                        "binary drivers older than version 4.x is unsupported. "
1757                        "You must upgrade your firmware files.\n");
1758                 b43_print_fw_helptext(dev->wl);
1759                 b43_write32(dev, B43_MMIO_MACCTL, 0);
1760                 err = -EOPNOTSUPP;
1761                 goto out;
1762         }
1763         b43dbg(dev->wl, "Loading firmware version %u.%u "
1764                "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
1765                fwrev, fwpatch,
1766                (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
1767                (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
1768
1769         dev->fw.rev = fwrev;
1770         dev->fw.patch = fwpatch;
1771
1772       out:
1773         return err;
1774 }
1775
1776 static int b43_write_initvals(struct b43_wldev *dev,
1777                               const struct b43_iv *ivals,
1778                               size_t count,
1779                               size_t array_size)
1780 {
1781         const struct b43_iv *iv;
1782         u16 offset;
1783         size_t i;
1784         bool bit32;
1785
1786         BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
1787         iv = ivals;
1788         for (i = 0; i < count; i++) {
1789                 if (array_size < sizeof(iv->offset_size))
1790                         goto err_format;
1791                 array_size -= sizeof(iv->offset_size);
1792                 offset = be16_to_cpu(iv->offset_size);
1793                 bit32 = !!(offset & B43_IV_32BIT);
1794                 offset &= B43_IV_OFFSET_MASK;
1795                 if (offset >= 0x1000)
1796                         goto err_format;
1797                 if (bit32) {
1798                         u32 value;
1799
1800                         if (array_size < sizeof(iv->data.d32))
1801                                 goto err_format;
1802                         array_size -= sizeof(iv->data.d32);
1803
1804                         value = be32_to_cpu(get_unaligned(&iv->data.d32));
1805                         b43_write32(dev, offset, value);
1806
1807                         iv = (const struct b43_iv *)((const uint8_t *)iv +
1808                                                         sizeof(__be16) +
1809                                                         sizeof(__be32));
1810                 } else {
1811                         u16 value;
1812
1813                         if (array_size < sizeof(iv->data.d16))
1814                                 goto err_format;
1815                         array_size -= sizeof(iv->data.d16);
1816
1817                         value = be16_to_cpu(iv->data.d16);
1818                         b43_write16(dev, offset, value);
1819
1820                         iv = (const struct b43_iv *)((const uint8_t *)iv +
1821                                                         sizeof(__be16) +
1822                                                         sizeof(__be16));
1823                 }
1824         }
1825         if (array_size)
1826                 goto err_format;
1827
1828         return 0;
1829
1830 err_format:
1831         b43err(dev->wl, "Initial Values Firmware file-format error.\n");
1832         b43_print_fw_helptext(dev->wl);
1833
1834         return -EPROTO;
1835 }
1836
1837 static int b43_upload_initvals(struct b43_wldev *dev)
1838 {
1839         const size_t hdr_len = sizeof(struct b43_fw_header);
1840         const struct b43_fw_header *hdr;
1841         struct b43_firmware *fw = &dev->fw;
1842         const struct b43_iv *ivals;
1843         size_t count;
1844         int err;
1845
1846         hdr = (const struct b43_fw_header *)(fw->initvals->data);
1847         ivals = (const struct b43_iv *)(fw->initvals->data + hdr_len);
1848         count = be32_to_cpu(hdr->size);
1849         err = b43_write_initvals(dev, ivals, count,
1850                                  fw->initvals->size - hdr_len);
1851         if (err)
1852                 goto out;
1853         if (fw->initvals_band) {
1854                 hdr = (const struct b43_fw_header *)(fw->initvals_band->data);
1855                 ivals = (const struct b43_iv *)(fw->initvals_band->data + hdr_len);
1856                 count = be32_to_cpu(hdr->size);
1857                 err = b43_write_initvals(dev, ivals, count,
1858                                          fw->initvals_band->size - hdr_len);
1859                 if (err)
1860                         goto out;
1861         }
1862 out:
1863
1864         return err;
1865 }
1866
1867 /* Initialize the GPIOs
1868  * http://bcm-specs.sipsolutions.net/GPIO
1869  */
1870 static int b43_gpio_init(struct b43_wldev *dev)
1871 {
1872         struct ssb_bus *bus = dev->dev->bus;
1873         struct ssb_device *gpiodev, *pcidev = NULL;
1874         u32 mask, set;
1875
1876         b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
1877                     & ~B43_MACCTL_GPOUTSMSK);
1878
1879         b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
1880                     | 0x000F);
1881
1882         mask = 0x0000001F;
1883         set = 0x0000000F;
1884         if (dev->dev->bus->chip_id == 0x4301) {
1885                 mask |= 0x0060;
1886                 set |= 0x0060;
1887         }
1888         if (0 /* FIXME: conditional unknown */ ) {
1889                 b43_write16(dev, B43_MMIO_GPIO_MASK,
1890                             b43_read16(dev, B43_MMIO_GPIO_MASK)
1891                             | 0x0100);
1892                 mask |= 0x0180;
1893                 set |= 0x0180;
1894         }
1895         if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
1896                 b43_write16(dev, B43_MMIO_GPIO_MASK,
1897                             b43_read16(dev, B43_MMIO_GPIO_MASK)
1898                             | 0x0200);
1899                 mask |= 0x0200;
1900                 set |= 0x0200;
1901         }
1902         if (dev->dev->id.revision >= 2)
1903                 mask |= 0x0010; /* FIXME: This is redundant. */
1904
1905 #ifdef CONFIG_SSB_DRIVER_PCICORE
1906         pcidev = bus->pcicore.dev;
1907 #endif
1908         gpiodev = bus->chipco.dev ? : pcidev;
1909         if (!gpiodev)
1910                 return 0;
1911         ssb_write32(gpiodev, B43_GPIO_CONTROL,
1912                     (ssb_read32(gpiodev, B43_GPIO_CONTROL)
1913                      & mask) | set);
1914
1915         return 0;
1916 }
1917
1918 /* Turn off all GPIO stuff. Call this on module unload, for example. */
1919 static void b43_gpio_cleanup(struct b43_wldev *dev)
1920 {
1921         struct ssb_bus *bus = dev->dev->bus;
1922         struct ssb_device *gpiodev, *pcidev = NULL;
1923
1924 #ifdef CONFIG_SSB_DRIVER_PCICORE
1925         pcidev = bus->pcicore.dev;
1926 #endif
1927         gpiodev = bus->chipco.dev ? : pcidev;
1928         if (!gpiodev)
1929                 return;
1930         ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
1931 }
1932
1933 /* http://bcm-specs.sipsolutions.net/EnableMac */
1934 void b43_mac_enable(struct b43_wldev *dev)
1935 {
1936         dev->mac_suspended--;
1937         B43_WARN_ON(dev->mac_suspended < 0);
1938         B43_WARN_ON(irqs_disabled());
1939         if (dev->mac_suspended == 0) {
1940                 b43_write32(dev, B43_MMIO_MACCTL,
1941                             b43_read32(dev, B43_MMIO_MACCTL)
1942                             | B43_MACCTL_ENABLED);
1943                 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
1944                             B43_IRQ_MAC_SUSPENDED);
1945                 /* Commit writes */
1946                 b43_read32(dev, B43_MMIO_MACCTL);
1947                 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1948                 b43_power_saving_ctl_bits(dev, 0);
1949
1950                 /* Re-enable IRQs. */
1951                 spin_lock_irq(&dev->wl->irq_lock);
1952                 b43_interrupt_enable(dev, dev->irq_savedstate);
1953                 spin_unlock_irq(&dev->wl->irq_lock);
1954         }
1955 }
1956
1957 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
1958 void b43_mac_suspend(struct b43_wldev *dev)
1959 {
1960         int i;
1961         u32 tmp;
1962
1963         might_sleep();
1964         B43_WARN_ON(irqs_disabled());
1965         B43_WARN_ON(dev->mac_suspended < 0);
1966
1967         if (dev->mac_suspended == 0) {
1968                 /* Mask IRQs before suspending MAC. Otherwise
1969                  * the MAC stays busy and won't suspend. */
1970                 spin_lock_irq(&dev->wl->irq_lock);
1971                 tmp = b43_interrupt_disable(dev, B43_IRQ_ALL);
1972                 spin_unlock_irq(&dev->wl->irq_lock);
1973                 b43_synchronize_irq(dev);
1974                 dev->irq_savedstate = tmp;
1975
1976                 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
1977                 b43_write32(dev, B43_MMIO_MACCTL,
1978                             b43_read32(dev, B43_MMIO_MACCTL)
1979                             & ~B43_MACCTL_ENABLED);
1980                 /* force pci to flush the write */
1981                 b43_read32(dev, B43_MMIO_MACCTL);
1982                 for (i = 40; i; i--) {
1983                         tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1984                         if (tmp & B43_IRQ_MAC_SUSPENDED)
1985                                 goto out;
1986                         msleep(1);
1987                 }
1988                 b43err(dev->wl, "MAC suspend failed\n");
1989         }
1990 out:
1991         dev->mac_suspended++;
1992 }
1993
1994 static void b43_adjust_opmode(struct b43_wldev *dev)
1995 {
1996         struct b43_wl *wl = dev->wl;
1997         u32 ctl;
1998         u16 cfp_pretbtt;
1999
2000         ctl = b43_read32(dev, B43_MMIO_MACCTL);
2001         /* Reset status to STA infrastructure mode. */
2002         ctl &= ~B43_MACCTL_AP;
2003         ctl &= ~B43_MACCTL_KEEP_CTL;
2004         ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2005         ctl &= ~B43_MACCTL_KEEP_BAD;
2006         ctl &= ~B43_MACCTL_PROMISC;
2007         ctl &= ~B43_MACCTL_BEACPROMISC;
2008         ctl |= B43_MACCTL_INFRA;
2009
2010         if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2011                 ctl |= B43_MACCTL_AP;
2012         else if (b43_is_mode(wl, IEEE80211_IF_TYPE_IBSS))
2013                 ctl &= ~B43_MACCTL_INFRA;
2014
2015         if (wl->filter_flags & FIF_CONTROL)
2016                 ctl |= B43_MACCTL_KEEP_CTL;
2017         if (wl->filter_flags & FIF_FCSFAIL)
2018                 ctl |= B43_MACCTL_KEEP_BAD;
2019         if (wl->filter_flags & FIF_PLCPFAIL)
2020                 ctl |= B43_MACCTL_KEEP_BADPLCP;
2021         if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2022                 ctl |= B43_MACCTL_PROMISC;
2023         if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2024                 ctl |= B43_MACCTL_BEACPROMISC;
2025
2026         /* Workaround: On old hardware the HW-MAC-address-filter
2027          * doesn't work properly, so always run promisc in filter
2028          * it in software. */
2029         if (dev->dev->id.revision <= 4)
2030                 ctl |= B43_MACCTL_PROMISC;
2031
2032         b43_write32(dev, B43_MMIO_MACCTL, ctl);
2033
2034         cfp_pretbtt = 2;
2035         if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2036                 if (dev->dev->bus->chip_id == 0x4306 &&
2037                     dev->dev->bus->chip_rev == 3)
2038                         cfp_pretbtt = 100;
2039                 else
2040                         cfp_pretbtt = 50;
2041         }
2042         b43_write16(dev, 0x612, cfp_pretbtt);
2043 }
2044
2045 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2046 {
2047         u16 offset;
2048
2049         if (is_ofdm) {
2050                 offset = 0x480;
2051                 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2052         } else {
2053                 offset = 0x4C0;
2054                 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2055         }
2056         b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2057                         b43_shm_read16(dev, B43_SHM_SHARED, offset));
2058 }
2059
2060 static void b43_rate_memory_init(struct b43_wldev *dev)
2061 {
2062         switch (dev->phy.type) {
2063         case B43_PHYTYPE_A:
2064         case B43_PHYTYPE_G:
2065                 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2066                 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2067                 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2068                 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2069                 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2070                 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2071                 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2072                 if (dev->phy.type == B43_PHYTYPE_A)
2073                         break;
2074                 /* fallthrough */
2075         case B43_PHYTYPE_B:
2076                 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2077                 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2078                 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2079                 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2080                 break;
2081         default:
2082                 B43_WARN_ON(1);
2083         }
2084 }
2085
2086 /* Set the TX-Antenna for management frames sent by firmware. */
2087 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2088 {
2089         u16 ant = 0;
2090         u16 tmp;
2091
2092         switch (antenna) {
2093         case B43_ANTENNA0:
2094                 ant |= B43_TX4_PHY_ANT0;
2095                 break;
2096         case B43_ANTENNA1:
2097                 ant |= B43_TX4_PHY_ANT1;
2098                 break;
2099         case B43_ANTENNA_AUTO:
2100                 ant |= B43_TX4_PHY_ANTLAST;
2101                 break;
2102         default:
2103                 B43_WARN_ON(1);
2104         }
2105
2106         /* FIXME We also need to set the other flags of the PHY control field somewhere. */
2107
2108         /* For Beacons */
2109         tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
2110         tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2111         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, tmp);
2112         /* For ACK/CTS */
2113         tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
2114         tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2115         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2116         /* For Probe Resposes */
2117         tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
2118         tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2119         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2120 }
2121
2122 /* This is the opposite of b43_chip_init() */
2123 static void b43_chip_exit(struct b43_wldev *dev)
2124 {
2125         b43_radio_turn_off(dev, 1);
2126         b43_gpio_cleanup(dev);
2127         /* firmware is released later */
2128 }
2129
2130 /* Initialize the chip
2131  * http://bcm-specs.sipsolutions.net/ChipInit
2132  */
2133 static int b43_chip_init(struct b43_wldev *dev)
2134 {
2135         struct b43_phy *phy = &dev->phy;
2136         int err, tmp;
2137         u32 value32;
2138         u16 value16;
2139
2140         b43_write32(dev, B43_MMIO_MACCTL,
2141                     B43_MACCTL_PSM_JMP0 | B43_MACCTL_IHR_ENABLED);
2142
2143         err = b43_request_firmware(dev);
2144         if (err)
2145                 goto out;
2146         err = b43_upload_microcode(dev);
2147         if (err)
2148                 goto out;       /* firmware is released later */
2149
2150         err = b43_gpio_init(dev);
2151         if (err)
2152                 goto out;       /* firmware is released later */
2153
2154         err = b43_upload_initvals(dev);
2155         if (err)
2156                 goto err_gpio_clean;
2157         b43_radio_turn_on(dev);
2158
2159         b43_write16(dev, 0x03E6, 0x0000);
2160         err = b43_phy_init(dev);
2161         if (err)
2162                 goto err_radio_off;
2163
2164         /* Select initial Interference Mitigation. */
2165         tmp = phy->interfmode;
2166         phy->interfmode = B43_INTERFMODE_NONE;
2167         b43_radio_set_interference_mitigation(dev, tmp);
2168
2169         b43_set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2170         b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2171
2172         if (phy->type == B43_PHYTYPE_B) {
2173                 value16 = b43_read16(dev, 0x005E);
2174                 value16 |= 0x0004;
2175                 b43_write16(dev, 0x005E, value16);
2176         }
2177         b43_write32(dev, 0x0100, 0x01000000);
2178         if (dev->dev->id.revision < 5)
2179                 b43_write32(dev, 0x010C, 0x01000000);
2180
2181         b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2182                     & ~B43_MACCTL_INFRA);
2183         b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2184                     | B43_MACCTL_INFRA);
2185
2186         /* Probe Response Timeout value */
2187         /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2188         b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2189
2190         /* Initially set the wireless operation mode. */
2191         b43_adjust_opmode(dev);
2192
2193         if (dev->dev->id.revision < 3) {
2194                 b43_write16(dev, 0x060E, 0x0000);
2195                 b43_write16(dev, 0x0610, 0x8000);
2196                 b43_write16(dev, 0x0604, 0x0000);
2197                 b43_write16(dev, 0x0606, 0x0200);
2198         } else {
2199                 b43_write32(dev, 0x0188, 0x80000000);
2200                 b43_write32(dev, 0x018C, 0x02000000);
2201         }
2202         b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2203         b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2204         b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2205         b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2206         b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2207         b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2208         b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2209
2210         value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2211         value32 |= 0x00100000;
2212         ssb_write32(dev->dev, SSB_TMSLOW, value32);
2213
2214         b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2215                     dev->dev->bus->chipco.fast_pwrup_delay);
2216
2217         err = 0;
2218         b43dbg(dev->wl, "Chip initialized\n");
2219 out:
2220         return err;
2221
2222 err_radio_off:
2223         b43_radio_turn_off(dev, 1);
2224 err_gpio_clean:
2225         b43_gpio_cleanup(dev);
2226         return err;
2227 }
2228
2229 static void b43_periodic_every120sec(struct b43_wldev *dev)
2230 {
2231         struct b43_phy *phy = &dev->phy;
2232
2233         if (phy->type != B43_PHYTYPE_G || phy->rev < 2)
2234                 return;
2235
2236         b43_mac_suspend(dev);
2237         b43_lo_g_measure(dev);
2238         b43_mac_enable(dev);
2239         if (b43_has_hardware_pctl(phy))
2240                 b43_lo_g_ctl_mark_all_unused(dev);
2241 }
2242
2243 static void b43_periodic_every60sec(struct b43_wldev *dev)
2244 {
2245         struct b43_phy *phy = &dev->phy;
2246
2247         if (!b43_has_hardware_pctl(phy))
2248                 b43_lo_g_ctl_mark_all_unused(dev);
2249         if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI) {
2250                 b43_mac_suspend(dev);
2251                 b43_calc_nrssi_slope(dev);
2252                 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) {
2253                         u8 old_chan = phy->channel;
2254
2255                         /* VCO Calibration */
2256                         if (old_chan >= 8)
2257                                 b43_radio_selectchannel(dev, 1, 0);
2258                         else
2259                                 b43_radio_selectchannel(dev, 13, 0);
2260                         b43_radio_selectchannel(dev, old_chan, 0);
2261                 }
2262                 b43_mac_enable(dev);
2263         }
2264 }
2265
2266 static void b43_periodic_every30sec(struct b43_wldev *dev)
2267 {
2268         /* Update device statistics. */
2269         b43_calculate_link_quality(dev);
2270 }
2271
2272 static void b43_periodic_every15sec(struct b43_wldev *dev)
2273 {
2274         struct b43_phy *phy = &dev->phy;
2275
2276         if (phy->type == B43_PHYTYPE_G) {
2277                 //TODO: update_aci_moving_average
2278                 if (phy->aci_enable && phy->aci_wlan_automatic) {
2279                         b43_mac_suspend(dev);
2280                         if (!phy->aci_enable && 1 /*TODO: not scanning? */ ) {
2281                                 if (0 /*TODO: bunch of conditions */ ) {
2282                                         b43_radio_set_interference_mitigation
2283                                             (dev, B43_INTERFMODE_MANUALWLAN);
2284                                 }
2285                         } else if (1 /*TODO*/) {
2286                                 /*
2287                                    if ((aci_average > 1000) && !(b43_radio_aci_scan(dev))) {
2288                                    b43_radio_set_interference_mitigation(dev,
2289                                    B43_INTERFMODE_NONE);
2290                                    }
2291                                  */
2292                         }
2293                         b43_mac_enable(dev);
2294                 } else if (phy->interfmode == B43_INTERFMODE_NONWLAN &&
2295                            phy->rev == 1) {
2296                         //TODO: implement rev1 workaround
2297                 }
2298         }
2299         b43_phy_xmitpower(dev); //FIXME: unless scanning?
2300         //TODO for APHY (temperature?)
2301
2302         atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2303         wmb();
2304 }
2305
2306 static void do_periodic_work(struct b43_wldev *dev)
2307 {
2308         unsigned int state;
2309
2310         state = dev->periodic_state;
2311         if (state % 8 == 0)
2312                 b43_periodic_every120sec(dev);
2313         if (state % 4 == 0)
2314                 b43_periodic_every60sec(dev);
2315         if (state % 2 == 0)
2316                 b43_periodic_every30sec(dev);
2317         b43_periodic_every15sec(dev);
2318 }
2319
2320 /* Periodic work locking policy:
2321  *      The whole periodic work handler is protected by
2322  *      wl->mutex. If another lock is needed somewhere in the
2323  *      pwork callchain, it's aquired in-place, where it's needed.
2324  */
2325 static void b43_periodic_work_handler(struct work_struct *work)
2326 {
2327         struct b43_wldev *dev = container_of(work, struct b43_wldev,
2328                                              periodic_work.work);
2329         struct b43_wl *wl = dev->wl;
2330         unsigned long delay;
2331
2332         mutex_lock(&wl->mutex);
2333
2334         if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2335                 goto out;
2336         if (b43_debug(dev, B43_DBG_PWORK_STOP))
2337                 goto out_requeue;
2338
2339         do_periodic_work(dev);
2340
2341         dev->periodic_state++;
2342 out_requeue:
2343         if (b43_debug(dev, B43_DBG_PWORK_FAST))
2344                 delay = msecs_to_jiffies(50);
2345         else
2346                 delay = round_jiffies_relative(HZ * 15);
2347         queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
2348 out:
2349         mutex_unlock(&wl->mutex);
2350 }
2351
2352 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2353 {
2354         struct delayed_work *work = &dev->periodic_work;
2355
2356         dev->periodic_state = 0;
2357         INIT_DELAYED_WORK(work, b43_periodic_work_handler);
2358         queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2359 }
2360
2361 /* Check if communication with the device works correctly. */
2362 static int b43_validate_chipaccess(struct b43_wldev *dev)
2363 {
2364         u32 v, backup;
2365
2366         backup = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2367
2368         /* Check for read/write and endianness problems. */
2369         b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2370         if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2371                 goto error;
2372         b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2373         if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
2374                 goto error;
2375
2376         b43_shm_write32(dev, B43_SHM_SHARED, 0, backup);
2377
2378         if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
2379                 /* The 32bit register shadows the two 16bit registers
2380                  * with update sideeffects. Validate this. */
2381                 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
2382                 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
2383                 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
2384                         goto error;
2385                 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
2386                         goto error;
2387         }
2388         b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
2389
2390         v = b43_read32(dev, B43_MMIO_MACCTL);
2391         v |= B43_MACCTL_GMODE;
2392         if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
2393                 goto error;
2394
2395         return 0;
2396 error:
2397         b43err(dev->wl, "Failed to validate the chipaccess\n");
2398         return -ENODEV;
2399 }
2400
2401 static void b43_security_init(struct b43_wldev *dev)
2402 {
2403         dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2404         B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2405         dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
2406         /* KTP is a word address, but we address SHM bytewise.
2407          * So multiply by two.
2408          */
2409         dev->ktp *= 2;
2410         if (dev->dev->id.revision >= 5) {
2411                 /* Number of RCMTA address slots */
2412                 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8);
2413         }
2414         b43_clear_keys(dev);
2415 }
2416
2417 static int b43_rng_read(struct hwrng *rng, u32 * data)
2418 {
2419         struct b43_wl *wl = (struct b43_wl *)rng->priv;
2420         unsigned long flags;
2421
2422         /* Don't take wl->mutex here, as it could deadlock with
2423          * hwrng internal locking. It's not needed to take
2424          * wl->mutex here, anyway. */
2425
2426         spin_lock_irqsave(&wl->irq_lock, flags);
2427         *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
2428         spin_unlock_irqrestore(&wl->irq_lock, flags);
2429
2430         return (sizeof(u16));
2431 }
2432
2433 static void b43_rng_exit(struct b43_wl *wl)
2434 {
2435         if (wl->rng_initialized)
2436                 hwrng_unregister(&wl->rng);
2437 }
2438
2439 static int b43_rng_init(struct b43_wl *wl)
2440 {
2441         int err;
2442
2443         snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2444                  "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2445         wl->rng.name = wl->rng_name;
2446         wl->rng.data_read = b43_rng_read;
2447         wl->rng.priv = (unsigned long)wl;
2448         wl->rng_initialized = 1;
2449         err = hwrng_register(&wl->rng);
2450         if (err) {
2451                 wl->rng_initialized = 0;
2452                 b43err(wl, "Failed to register the random "
2453                        "number generator (%d)\n", err);
2454         }
2455
2456         return err;
2457 }
2458
2459 static int b43_op_tx(struct ieee80211_hw *hw,
2460                      struct sk_buff *skb,
2461                      struct ieee80211_tx_control *ctl)
2462 {
2463         struct b43_wl *wl = hw_to_b43_wl(hw);
2464         struct b43_wldev *dev = wl->current_dev;
2465         int err = -ENODEV;
2466
2467         if (unlikely(!dev))
2468                 goto out;
2469         if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2470                 goto out;
2471         /* DMA-TX is done without a global lock. */
2472         err = b43_dma_tx(dev, skb, ctl);
2473 out:
2474         if (unlikely(err))
2475                 return NETDEV_TX_BUSY;
2476         return NETDEV_TX_OK;
2477 }
2478
2479 static int b43_op_conf_tx(struct ieee80211_hw *hw,
2480                           int queue,
2481                           const struct ieee80211_tx_queue_params *params)
2482 {
2483         return 0;
2484 }
2485
2486 static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
2487                                struct ieee80211_tx_queue_stats *stats)
2488 {
2489         struct b43_wl *wl = hw_to_b43_wl(hw);
2490         struct b43_wldev *dev = wl->current_dev;
2491         unsigned long flags;
2492         int err = -ENODEV;
2493
2494         if (!dev)
2495                 goto out;
2496         spin_lock_irqsave(&wl->irq_lock, flags);
2497         if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
2498                 b43_dma_get_tx_stats(dev, stats);
2499                 err = 0;
2500         }
2501         spin_unlock_irqrestore(&wl->irq_lock, flags);
2502 out:
2503         return err;
2504 }
2505
2506 static int b43_op_get_stats(struct ieee80211_hw *hw,
2507                             struct ieee80211_low_level_stats *stats)
2508 {
2509         struct b43_wl *wl = hw_to_b43_wl(hw);
2510         unsigned long flags;
2511
2512         spin_lock_irqsave(&wl->irq_lock, flags);
2513         memcpy(stats, &wl->ieee_stats, sizeof(*stats));
2514         spin_unlock_irqrestore(&wl->irq_lock, flags);
2515
2516         return 0;
2517 }
2518
2519 static const char *phymode_to_string(unsigned int phymode)
2520 {
2521         switch (phymode) {
2522         case B43_PHYMODE_A:
2523                 return "A";
2524         case B43_PHYMODE_B:
2525                 return "B";
2526         case B43_PHYMODE_G:
2527                 return "G";
2528         default:
2529                 B43_WARN_ON(1);
2530         }
2531         return "";
2532 }
2533
2534 static int find_wldev_for_phymode(struct b43_wl *wl,
2535                                   unsigned int phymode,
2536                                   struct b43_wldev **dev, bool * gmode)
2537 {
2538         struct b43_wldev *d;
2539
2540         list_for_each_entry(d, &wl->devlist, list) {
2541                 if (d->phy.possible_phymodes & phymode) {
2542                         /* Ok, this device supports the PHY-mode.
2543                          * Now figure out how the gmode bit has to be
2544                          * set to support it. */
2545                         if (phymode == B43_PHYMODE_A)
2546                                 *gmode = 0;
2547                         else
2548                                 *gmode = 1;
2549                         *dev = d;
2550
2551                         return 0;
2552                 }
2553         }
2554
2555         return -ESRCH;
2556 }
2557
2558 static void b43_put_phy_into_reset(struct b43_wldev *dev)
2559 {
2560         struct ssb_device *sdev = dev->dev;
2561         u32 tmslow;
2562
2563         tmslow = ssb_read32(sdev, SSB_TMSLOW);
2564         tmslow &= ~B43_TMSLOW_GMODE;
2565         tmslow |= B43_TMSLOW_PHYRESET;
2566         tmslow |= SSB_TMSLOW_FGC;
2567         ssb_write32(sdev, SSB_TMSLOW, tmslow);
2568         msleep(1);
2569
2570         tmslow = ssb_read32(sdev, SSB_TMSLOW);
2571         tmslow &= ~SSB_TMSLOW_FGC;
2572         tmslow |= B43_TMSLOW_PHYRESET;
2573         ssb_write32(sdev, SSB_TMSLOW, tmslow);
2574         msleep(1);
2575 }
2576
2577 /* Expects wl->mutex locked */
2578 static int b43_switch_phymode(struct b43_wl *wl, unsigned int new_mode)
2579 {
2580         struct b43_wldev *up_dev;
2581         struct b43_wldev *down_dev;
2582         int err;
2583         bool gmode = 0;
2584         int prev_status;
2585
2586         err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
2587         if (err) {
2588                 b43err(wl, "Could not find a device for %s-PHY mode\n",
2589                        phymode_to_string(new_mode));
2590                 return err;
2591         }
2592         if ((up_dev == wl->current_dev) &&
2593             (!!wl->current_dev->phy.gmode == !!gmode)) {
2594                 /* This device is already running. */
2595                 return 0;
2596         }
2597         b43dbg(wl, "Reconfiguring PHYmode to %s-PHY\n",
2598                phymode_to_string(new_mode));
2599         down_dev = wl->current_dev;
2600
2601         prev_status = b43_status(down_dev);
2602         /* Shutdown the currently running core. */
2603         if (prev_status >= B43_STAT_STARTED)
2604                 b43_wireless_core_stop(down_dev);
2605         if (prev_status >= B43_STAT_INITIALIZED)
2606                 b43_wireless_core_exit(down_dev);
2607
2608         if (down_dev != up_dev) {
2609                 /* We switch to a different core, so we put PHY into
2610                  * RESET on the old core. */
2611                 b43_put_phy_into_reset(down_dev);
2612         }
2613
2614         /* Now start the new core. */
2615         up_dev->phy.gmode = gmode;
2616         if (prev_status >= B43_STAT_INITIALIZED) {
2617                 err = b43_wireless_core_init(up_dev);
2618                 if (err) {
2619                         b43err(wl, "Fatal: Could not initialize device for "
2620                                "newly selected %s-PHY mode\n",
2621                                phymode_to_string(new_mode));
2622                         goto init_failure;
2623                 }
2624         }
2625         if (prev_status >= B43_STAT_STARTED) {
2626                 err = b43_wireless_core_start(up_dev);
2627                 if (err) {
2628                         b43err(wl, "Fatal: Coult not start device for "
2629                                "newly selected %s-PHY mode\n",
2630                                phymode_to_string(new_mode));
2631                         b43_wireless_core_exit(up_dev);
2632                         goto init_failure;
2633                 }
2634         }
2635         B43_WARN_ON(b43_status(up_dev) != prev_status);
2636
2637         wl->current_dev = up_dev;
2638
2639         return 0;
2640       init_failure:
2641         /* Whoops, failed to init the new core. No core is operating now. */
2642         wl->current_dev = NULL;
2643         return err;
2644 }
2645
2646 /* Check if the use of the antenna that ieee80211 told us to
2647  * use is possible. This will fall back to DEFAULT.
2648  * "antenna_nr" is the antenna identifier we got from ieee80211. */
2649 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
2650                                   u8 antenna_nr)
2651 {
2652         u8 antenna_mask;
2653
2654         if (antenna_nr == 0) {
2655                 /* Zero means "use default antenna". That's always OK. */
2656                 return 0;
2657         }
2658
2659         /* Get the mask of available antennas. */
2660         if (dev->phy.gmode)
2661                 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
2662         else
2663                 antenna_mask = dev->dev->bus->sprom.ant_available_a;
2664
2665         if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
2666                 /* This antenna is not available. Fall back to default. */
2667                 return 0;
2668         }
2669
2670         return antenna_nr;
2671 }
2672
2673 static int b43_antenna_from_ieee80211(struct b43_wldev *dev, u8 antenna)
2674 {
2675         antenna = b43_ieee80211_antenna_sanitize(dev, antenna);
2676         switch (antenna) {
2677         case 0:         /* default/diversity */
2678                 return B43_ANTENNA_DEFAULT;
2679         case 1:         /* Antenna 0 */
2680                 return B43_ANTENNA0;
2681         case 2:         /* Antenna 1 */
2682                 return B43_ANTENNA1;
2683         default:
2684                 return B43_ANTENNA_DEFAULT;
2685         }
2686 }
2687
2688 static int b43_op_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
2689 {
2690         struct b43_wl *wl = hw_to_b43_wl(hw);
2691         struct b43_wldev *dev;
2692         struct b43_phy *phy;
2693         unsigned long flags;
2694         unsigned int new_phymode = 0xFFFF;
2695         int antenna;
2696         int err = 0;
2697         u32 savedirqs;
2698
2699         mutex_lock(&wl->mutex);
2700
2701         /* Switch the PHY mode (if necessary). */
2702         switch (conf->phymode) {
2703         case MODE_IEEE80211A:
2704                 new_phymode = B43_PHYMODE_A;
2705                 break;
2706         case MODE_IEEE80211B:
2707                 new_phymode = B43_PHYMODE_B;
2708                 break;
2709         case MODE_IEEE80211G:
2710                 new_phymode = B43_PHYMODE_G;
2711                 break;
2712         default:
2713                 B43_WARN_ON(1);
2714         }
2715         err = b43_switch_phymode(wl, new_phymode);
2716         if (err)
2717                 goto out_unlock_mutex;
2718         dev = wl->current_dev;
2719         phy = &dev->phy;
2720
2721         /* Disable IRQs while reconfiguring the device.
2722          * This makes it possible to drop the spinlock throughout
2723          * the reconfiguration process. */
2724         spin_lock_irqsave(&wl->irq_lock, flags);
2725         if (b43_status(dev) < B43_STAT_STARTED) {
2726                 spin_unlock_irqrestore(&wl->irq_lock, flags);
2727                 goto out_unlock_mutex;
2728         }
2729         savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL);
2730         spin_unlock_irqrestore(&wl->irq_lock, flags);
2731         b43_synchronize_irq(dev);
2732
2733         /* Switch to the requested channel.
2734          * The firmware takes care of races with the TX handler. */
2735         if (conf->channel_val != phy->channel)
2736                 b43_radio_selectchannel(dev, conf->channel_val, 0);
2737
2738         /* Enable/Disable ShortSlot timing. */
2739         if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) !=
2740             dev->short_slot) {
2741                 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
2742                 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
2743                         b43_short_slot_timing_enable(dev);
2744                 else
2745                         b43_short_slot_timing_disable(dev);
2746         }
2747
2748         dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
2749
2750         /* Adjust the desired TX power level. */
2751         if (conf->power_level != 0) {
2752                 if (conf->power_level != phy->power_level) {
2753                         phy->power_level = conf->power_level;
2754                         b43_phy_xmitpower(dev);
2755                 }
2756         }
2757
2758         /* Antennas for RX and management frame TX. */
2759         antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_tx);
2760         b43_mgmtframe_txantenna(dev, antenna);
2761         antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_rx);
2762         b43_set_rx_antenna(dev, antenna);
2763
2764         /* Update templates for AP mode. */
2765         if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2766                 b43_set_beacon_int(dev, conf->beacon_int);
2767
2768         if (!!conf->radio_enabled != phy->radio_on) {
2769                 if (conf->radio_enabled) {
2770                         b43_radio_turn_on(dev);
2771                         b43info(dev->wl, "Radio turned on by software\n");
2772                         if (!dev->radio_hw_enable) {
2773                                 b43info(dev->wl, "The hardware RF-kill button "
2774                                         "still turns the radio physically off. "
2775                                         "Press the button to turn it on.\n");
2776                         }
2777                 } else {
2778                         b43_radio_turn_off(dev, 0);
2779                         b43info(dev->wl, "Radio turned off by software\n");
2780                 }
2781         }
2782
2783         spin_lock_irqsave(&wl->irq_lock, flags);
2784         b43_interrupt_enable(dev, savedirqs);
2785         mmiowb();
2786         spin_unlock_irqrestore(&wl->irq_lock, flags);
2787       out_unlock_mutex:
2788         mutex_unlock(&wl->mutex);
2789
2790         return err;
2791 }
2792
2793 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2794                            const u8 *local_addr, const u8 *addr,
2795                            struct ieee80211_key_conf *key)
2796 {
2797         struct b43_wl *wl = hw_to_b43_wl(hw);
2798         struct b43_wldev *dev;
2799         unsigned long flags;
2800         u8 algorithm;
2801         u8 index;
2802         int err;
2803         DECLARE_MAC_BUF(mac);
2804
2805         if (modparam_nohwcrypt)
2806                 return -ENOSPC; /* User disabled HW-crypto */
2807
2808         mutex_lock(&wl->mutex);
2809         spin_lock_irqsave(&wl->irq_lock, flags);
2810
2811         dev = wl->current_dev;
2812         err = -ENODEV;
2813         if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
2814                 goto out_unlock;
2815
2816         err = -EINVAL;
2817         switch (key->alg) {
2818         case ALG_WEP:
2819                 if (key->keylen == 5)
2820                         algorithm = B43_SEC_ALGO_WEP40;
2821                 else
2822                         algorithm = B43_SEC_ALGO_WEP104;
2823                 break;
2824         case ALG_TKIP:
2825                 algorithm = B43_SEC_ALGO_TKIP;
2826                 break;
2827         case ALG_CCMP:
2828                 algorithm = B43_SEC_ALGO_AES;
2829                 break;
2830         default:
2831                 B43_WARN_ON(1);
2832                 goto out_unlock;
2833         }
2834         index = (u8) (key->keyidx);
2835         if (index > 3)
2836                 goto out_unlock;
2837
2838         switch (cmd) {
2839         case SET_KEY:
2840                 if (algorithm == B43_SEC_ALGO_TKIP) {
2841                         /* FIXME: No TKIP hardware encryption for now. */
2842                         err = -EOPNOTSUPP;
2843                         goto out_unlock;
2844                 }
2845
2846                 if (is_broadcast_ether_addr(addr)) {
2847                         /* addr is FF:FF:FF:FF:FF:FF for default keys */
2848                         err = b43_key_write(dev, index, algorithm,
2849                                             key->key, key->keylen, NULL, key);
2850                 } else {
2851                         /*
2852                          * either pairwise key or address is 00:00:00:00:00:00
2853                          * for transmit-only keys
2854                          */
2855                         err = b43_key_write(dev, -1, algorithm,
2856                                             key->key, key->keylen, addr, key);
2857                 }
2858                 if (err)
2859                         goto out_unlock;
2860
2861                 if (algorithm == B43_SEC_ALGO_WEP40 ||
2862                     algorithm == B43_SEC_ALGO_WEP104) {
2863                         b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
2864                 } else {
2865                         b43_hf_write(dev,
2866                                      b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
2867                 }
2868                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2869                 break;
2870         case DISABLE_KEY: {
2871                 err = b43_key_clear(dev, key->hw_key_idx);
2872                 if (err)
2873                         goto out_unlock;
2874                 break;
2875         }
2876         default:
2877                 B43_WARN_ON(1);
2878         }
2879 out_unlock:
2880         spin_unlock_irqrestore(&wl->irq_lock, flags);
2881         mutex_unlock(&wl->mutex);
2882         if (!err) {
2883                 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
2884                        "mac: %s\n",
2885                        cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
2886                        print_mac(mac, addr));
2887         }
2888         return err;
2889 }
2890
2891 static void b43_op_configure_filter(struct ieee80211_hw *hw,
2892                                     unsigned int changed, unsigned int *fflags,
2893                                     int mc_count, struct dev_addr_list *mc_list)
2894 {
2895         struct b43_wl *wl = hw_to_b43_wl(hw);
2896         struct b43_wldev *dev = wl->current_dev;
2897         unsigned long flags;
2898
2899         if (!dev) {
2900                 *fflags = 0;
2901                 return;
2902         }
2903
2904         spin_lock_irqsave(&wl->irq_lock, flags);
2905         *fflags &= FIF_PROMISC_IN_BSS |
2906                   FIF_ALLMULTI |
2907                   FIF_FCSFAIL |
2908                   FIF_PLCPFAIL |
2909                   FIF_CONTROL |
2910                   FIF_OTHER_BSS |
2911                   FIF_BCN_PRBRESP_PROMISC;
2912
2913         changed &= FIF_PROMISC_IN_BSS |
2914                    FIF_ALLMULTI |
2915                    FIF_FCSFAIL |
2916                    FIF_PLCPFAIL |
2917                    FIF_CONTROL |
2918                    FIF_OTHER_BSS |
2919                    FIF_BCN_PRBRESP_PROMISC;
2920
2921         wl->filter_flags = *fflags;
2922
2923         if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
2924                 b43_adjust_opmode(dev);
2925         spin_unlock_irqrestore(&wl->irq_lock, flags);
2926 }
2927
2928 static int b43_op_config_interface(struct ieee80211_hw *hw,
2929                                    int if_id,
2930                                    struct ieee80211_if_conf *conf)
2931 {
2932         struct b43_wl *wl = hw_to_b43_wl(hw);
2933         struct b43_wldev *dev = wl->current_dev;
2934         unsigned long flags;
2935
2936         if (!dev)
2937                 return -ENODEV;
2938         mutex_lock(&wl->mutex);
2939         spin_lock_irqsave(&wl->irq_lock, flags);
2940         B43_WARN_ON(wl->if_id != if_id);
2941         if (conf->bssid)
2942                 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
2943         else
2944                 memset(wl->bssid, 0, ETH_ALEN);
2945         if (b43_status(dev) >= B43_STAT_INITIALIZED) {
2946                 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) {
2947                         B43_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP);
2948                         b43_set_ssid(dev, conf->ssid, conf->ssid_len);
2949                         if (conf->beacon)
2950                                 b43_refresh_templates(dev, conf->beacon);
2951                 }
2952                 b43_write_mac_bssid_templates(dev);
2953         }
2954         spin_unlock_irqrestore(&wl->irq_lock, flags);
2955         mutex_unlock(&wl->mutex);
2956
2957         return 0;
2958 }
2959
2960 /* Locking: wl->mutex */
2961 static void b43_wireless_core_stop(struct b43_wldev *dev)
2962 {
2963         struct b43_wl *wl = dev->wl;
2964         unsigned long flags;
2965
2966         if (b43_status(dev) < B43_STAT_STARTED)
2967                 return;
2968
2969         /* Disable and sync interrupts. We must do this before than
2970          * setting the status to INITIALIZED, as the interrupt handler
2971          * won't care about IRQs then. */
2972         spin_lock_irqsave(&wl->irq_lock, flags);
2973         dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
2974         b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
2975         spin_unlock_irqrestore(&wl->irq_lock, flags);
2976         b43_synchronize_irq(dev);
2977
2978         b43_set_status(dev, B43_STAT_INITIALIZED);
2979
2980         mutex_unlock(&wl->mutex);
2981         /* Must unlock as it would otherwise deadlock. No races here.
2982          * Cancel the possibly running self-rearming periodic work. */
2983         cancel_delayed_work_sync(&dev->periodic_work);
2984         mutex_lock(&wl->mutex);
2985
2986         ieee80211_stop_queues(wl->hw);  //FIXME this could cause a deadlock, as mac80211 seems buggy.
2987
2988         b43_mac_suspend(dev);
2989         free_irq(dev->dev->irq, dev);
2990         b43dbg(wl, "Wireless interface stopped\n");
2991 }
2992
2993 /* Locking: wl->mutex */
2994 static int b43_wireless_core_start(struct b43_wldev *dev)
2995 {
2996         int err;
2997
2998         B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
2999
3000         drain_txstatus_queue(dev);
3001         err = request_irq(dev->dev->irq, b43_interrupt_handler,
3002                           IRQF_SHARED, KBUILD_MODNAME, dev);
3003         if (err) {
3004                 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3005                 goto out;
3006         }
3007
3008         /* We are ready to run. */
3009         b43_set_status(dev, B43_STAT_STARTED);
3010
3011         /* Start data flow (TX/RX). */
3012         b43_mac_enable(dev);
3013         b43_interrupt_enable(dev, dev->irq_savedstate);
3014         ieee80211_start_queues(dev->wl->hw);
3015
3016         /* Start maintainance work */
3017         b43_periodic_tasks_setup(dev);
3018
3019         b43dbg(dev->wl, "Wireless interface started\n");
3020       out:
3021         return err;
3022 }
3023
3024 /* Get PHY and RADIO versioning numbers */
3025 static int b43_phy_versioning(struct b43_wldev *dev)
3026 {
3027         struct b43_phy *phy = &dev->phy;
3028         u32 tmp;
3029         u8 analog_type;
3030         u8 phy_type;
3031         u8 phy_rev;
3032         u16 radio_manuf;
3033         u16 radio_ver;
3034         u16 radio_rev;
3035         int unsupported = 0;
3036
3037         /* Get PHY versioning */
3038         tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3039         analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3040         phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3041         phy_rev = (tmp & B43_PHYVER_VERSION);
3042         switch (phy_type) {
3043         case B43_PHYTYPE_A:
3044                 if (phy_rev >= 4)
3045                         unsupported = 1;
3046                 break;
3047         case B43_PHYTYPE_B:
3048                 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3049                     && phy_rev != 7)
3050                         unsupported = 1;
3051                 break;
3052         case B43_PHYTYPE_G:
3053                 if (phy_rev > 9)
3054                         unsupported = 1;
3055                 break;
3056         default:
3057                 unsupported = 1;
3058         };
3059         if (unsupported) {
3060                 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3061                        "(Analog %u, Type %u, Revision %u)\n",
3062                        analog_type, phy_type, phy_rev);
3063                 return -EOPNOTSUPP;
3064         }
3065         b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3066                analog_type, phy_type, phy_rev);
3067
3068         /* Get RADIO versioning */
3069         if (dev->dev->bus->chip_id == 0x4317) {
3070                 if (dev->dev->bus->chip_rev == 0)
3071                         tmp = 0x3205017F;
3072                 else if (dev->dev->bus->chip_rev == 1)
3073                         tmp = 0x4205017F;
3074                 else
3075                         tmp = 0x5205017F;
3076         } else {
3077                 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3078                 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH);
3079                 tmp <<= 16;
3080                 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3081                 tmp |= b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3082         }
3083         radio_manuf = (tmp & 0x00000FFF);
3084         radio_ver = (tmp & 0x0FFFF000) >> 12;
3085         radio_rev = (tmp & 0xF0000000) >> 28;
3086         switch (phy_type) {
3087         case B43_PHYTYPE_A:
3088                 if (radio_ver != 0x2060)
3089                         unsupported = 1;
3090                 if (radio_rev != 1)
3091                         unsupported = 1;
3092                 if (radio_manuf != 0x17F)
3093                         unsupported = 1;
3094                 break;
3095         case B43_PHYTYPE_B:
3096                 if ((radio_ver & 0xFFF0) != 0x2050)
3097                         unsupported = 1;
3098                 break;
3099         case B43_PHYTYPE_G:
3100                 if (radio_ver != 0x2050)
3101                         unsupported = 1;
3102                 break;
3103         default:
3104                 B43_WARN_ON(1);
3105         }
3106         if (unsupported) {
3107                 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
3108                        "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3109                        radio_manuf, radio_ver, radio_rev);
3110                 return -EOPNOTSUPP;
3111         }
3112         b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3113                radio_manuf, radio_ver, radio_rev);
3114
3115         phy->radio_manuf = radio_manuf;
3116         phy->radio_ver = radio_ver;
3117         phy->radio_rev = radio_rev;
3118
3119         phy->analog = analog_type;
3120         phy->type = phy_type;
3121         phy->rev = phy_rev;
3122
3123         return 0;
3124 }
3125
3126 static void setup_struct_phy_for_init(struct b43_wldev *dev,
3127                                       struct b43_phy *phy)
3128 {
3129         struct b43_txpower_lo_control *lo;
3130         int i;
3131
3132         memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3133         memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3134
3135         /* Flags */
3136         phy->locked = 0;
3137
3138         phy->aci_enable = 0;
3139         phy->aci_wlan_automatic = 0;
3140         phy->aci_hw_rssi = 0;
3141
3142         phy->radio_off_context.valid = 0;
3143
3144         lo = phy->lo_control;
3145         if (lo) {
3146                 memset(lo, 0, sizeof(*(phy->lo_control)));
3147                 lo->rebuild = 1;
3148                 lo->tx_bias = 0xFF;
3149         }
3150         phy->max_lb_gain = 0;
3151         phy->trsw_rx_gain = 0;
3152         phy->txpwr_offset = 0;
3153
3154         /* NRSSI */
3155         phy->nrssislope = 0;
3156         for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3157                 phy->nrssi[i] = -1000;
3158         for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3159                 phy->nrssi_lt[i] = i;
3160
3161         phy->lofcal = 0xFFFF;
3162         phy->initval = 0xFFFF;
3163
3164         spin_lock_init(&phy->lock);
3165         phy->interfmode = B43_INTERFMODE_NONE;
3166         phy->channel = 0xFF;
3167
3168         phy->hardware_power_control = !!modparam_hwpctl;
3169
3170         /* PHY TX errors counter. */
3171         atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3172
3173         /* OFDM-table address caching. */
3174         phy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_UNKNOWN;
3175 }
3176
3177 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
3178 {
3179         dev->dfq_valid = 0;
3180
3181         /* Assume the radio is enabled. If it's not enabled, the state will
3182          * immediately get fixed on the first periodic work run. */
3183         dev->radio_hw_enable = 1;
3184
3185         /* Stats */
3186         memset(&dev->stats, 0, sizeof(dev->stats));
3187
3188         setup_struct_phy_for_init(dev, &dev->phy);
3189
3190         /* IRQ related flags */
3191         dev->irq_reason = 0;
3192         memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3193         dev->irq_savedstate = B43_IRQ_MASKTEMPLATE;
3194
3195         dev->mac_suspended = 1;
3196
3197         /* Noise calculation context */
3198         memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3199 }
3200
3201 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
3202 {
3203         struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3204         u32 hf;
3205
3206         if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
3207                 return;
3208         if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
3209                 return;
3210
3211         hf = b43_hf_read(dev);
3212         if (sprom->boardflags_lo & B43_BFL_BTCMOD)
3213                 hf |= B43_HF_BTCOEXALT;
3214         else
3215                 hf |= B43_HF_BTCOEX;
3216         b43_hf_write(dev, hf);
3217         //TODO
3218 }
3219
3220 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
3221 {                               //TODO
3222 }
3223
3224 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
3225 {
3226 #ifdef CONFIG_SSB_DRIVER_PCICORE
3227         struct ssb_bus *bus = dev->dev->bus;
3228         u32 tmp;
3229
3230         if (bus->pcicore.dev &&
3231             bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
3232             bus->pcicore.dev->id.revision <= 5) {
3233                 /* IMCFGLO timeouts workaround. */
3234                 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
3235                 tmp &= ~SSB_IMCFGLO_REQTO;
3236                 tmp &= ~SSB_IMCFGLO_SERTO;
3237                 switch (bus->bustype) {
3238                 case SSB_BUSTYPE_PCI:
3239                 case SSB_BUSTYPE_PCMCIA:
3240                         tmp |= 0x32;
3241                         break;
3242                 case SSB_BUSTYPE_SSB:
3243                         tmp |= 0x53;
3244                         break;
3245                 }
3246                 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
3247         }
3248 #endif /* CONFIG_SSB_DRIVER_PCICORE */
3249 }
3250
3251 /* Write the short and long frame retry limit values. */
3252 static void b43_set_retry_limits(struct b43_wldev *dev,
3253                                  unsigned int short_retry,
3254                                  unsigned int long_retry)
3255 {
3256         /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3257          * the chip-internal counter. */
3258         short_retry = min(short_retry, (unsigned int)0xF);
3259         long_retry = min(long_retry, (unsigned int)0xF);
3260
3261         b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3262                         short_retry);
3263         b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3264                         long_retry);
3265 }
3266
3267 /* Shutdown a wireless core */
3268 /* Locking: wl->mutex */
3269 static void b43_wireless_core_exit(struct b43_wldev *dev)
3270 {
3271         struct b43_phy *phy = &dev->phy;
3272
3273         B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
3274         if (b43_status(dev) != B43_STAT_INITIALIZED)
3275                 return;
3276         b43_set_status(dev, B43_STAT_UNINIT);
3277
3278         b43_leds_exit(dev);
3279         b43_rng_exit(dev->wl);
3280         b43_dma_free(dev);
3281         b43_chip_exit(dev);
3282         b43_radio_turn_off(dev, 1);
3283         b43_switch_analog(dev, 0);
3284         if (phy->dyn_tssi_tbl)
3285                 kfree(phy->tssi2dbm);
3286         kfree(phy->lo_control);
3287         phy->lo_control = NULL;
3288         ssb_device_disable(dev->dev, 0);
3289         ssb_bus_may_powerdown(dev->dev->bus);
3290 }
3291
3292 /* Initialize a wireless core */
3293 static int b43_wireless_core_init(struct b43_wldev *dev)
3294 {
3295         struct b43_wl *wl = dev->wl;
3296         struct ssb_bus *bus = dev->dev->bus;
3297         struct ssb_sprom *sprom = &bus->sprom;
3298         struct b43_phy *phy = &dev->phy;
3299         int err;
3300         u32 hf, tmp;
3301
3302         B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3303
3304         err = ssb_bus_powerup(bus, 0);
3305         if (err)
3306                 goto out;
3307         if (!ssb_device_is_enabled(dev->dev)) {
3308                 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
3309                 b43_wireless_core_reset(dev, tmp);
3310         }
3311
3312         if ((phy->type == B43_PHYTYPE_B) || (phy->type == B43_PHYTYPE_G)) {
3313                 phy->lo_control =
3314                     kzalloc(sizeof(*(phy->lo_control)), GFP_KERNEL);
3315                 if (!phy->lo_control) {
3316                         err = -ENOMEM;
3317                         goto err_busdown;
3318                 }
3319         }
3320         setup_struct_wldev_for_init(dev);
3321
3322         err = b43_phy_init_tssi2dbm_table(dev);
3323         if (err)
3324                 goto err_kfree_lo_control;
3325
3326         /* Enable IRQ routing to this device. */
3327         ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3328
3329         b43_imcfglo_timeouts_workaround(dev);
3330         b43_bluetooth_coext_disable(dev);
3331         b43_phy_early_init(dev);
3332         err = b43_chip_init(dev);
3333         if (err)
3334                 goto err_kfree_tssitbl;
3335         b43_shm_write16(dev, B43_SHM_SHARED,
3336                         B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
3337         hf = b43_hf_read(dev);
3338         if (phy->type == B43_PHYTYPE_G) {
3339                 hf |= B43_HF_SYMW;
3340                 if (phy->rev == 1)
3341                         hf |= B43_HF_GDCW;
3342                 if (sprom->boardflags_lo & B43_BFL_PACTRL)
3343                         hf |= B43_HF_OFDMPABOOST;
3344         } else if (phy->type == B43_PHYTYPE_B) {
3345                 hf |= B43_HF_SYMW;
3346                 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
3347                         hf &= ~B43_HF_GDCW;
3348         }
3349         b43_hf_write(dev, hf);
3350
3351         b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
3352                              B43_DEFAULT_LONG_RETRY_LIMIT);
3353         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
3354         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
3355
3356         /* Disable sending probe responses from firmware.
3357          * Setting the MaxTime to one usec will always trigger
3358          * a timeout, so we never send any probe resp.
3359          * A timeout of zero is infinite. */
3360         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
3361
3362         b43_rate_memory_init(dev);
3363
3364         /* Minimum Contention Window */
3365         if (phy->type == B43_PHYTYPE_B) {
3366                 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
3367         } else {
3368                 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
3369         }
3370         /* Maximum Contention Window */
3371         b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
3372
3373         err = b43_dma_init(dev);
3374         if (err)
3375                 goto err_chip_exit;
3376         b43_qos_init(dev);
3377
3378 //FIXME
3379 #if 1
3380         b43_write16(dev, 0x0612, 0x0050);
3381         b43_shm_write16(dev, B43_SHM_SHARED, 0x0416, 0x0050);
3382         b43_shm_write16(dev, B43_SHM_SHARED, 0x0414, 0x01F4);
3383 #endif
3384
3385         b43_bluetooth_coext_enable(dev);
3386
3387         ssb_bus_powerup(bus, 1);        /* Enable dynamic PCTL */
3388         memset(wl->bssid, 0, ETH_ALEN);
3389         memset(wl->mac_addr, 0, ETH_ALEN);
3390         b43_upload_card_macaddress(dev);
3391         b43_security_init(dev);
3392         b43_rng_init(wl);
3393
3394         b43_set_status(dev, B43_STAT_INITIALIZED);
3395
3396         b43_leds_init(dev);
3397 out:
3398         return err;
3399
3400       err_chip_exit:
3401         b43_chip_exit(dev);
3402       err_kfree_tssitbl:
3403         if (phy->dyn_tssi_tbl)
3404                 kfree(phy->tssi2dbm);
3405       err_kfree_lo_control:
3406         kfree(phy->lo_control);
3407         phy->lo_control = NULL;
3408       err_busdown:
3409         ssb_bus_may_powerdown(bus);
3410         B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3411         return err;
3412 }
3413
3414 static int b43_op_add_interface(struct ieee80211_hw *hw,
3415                                 struct ieee80211_if_init_conf *conf)
3416 {
3417         struct b43_wl *wl = hw_to_b43_wl(hw);
3418         struct b43_wldev *dev;
3419         unsigned long flags;
3420         int err = -EOPNOTSUPP;
3421
3422         /* TODO: allow WDS/AP devices to coexist */
3423
3424         if (conf->type != IEEE80211_IF_TYPE_AP &&
3425             conf->type != IEEE80211_IF_TYPE_STA &&
3426             conf->type != IEEE80211_IF_TYPE_WDS &&
3427             conf->type != IEEE80211_IF_TYPE_IBSS)
3428                 return -EOPNOTSUPP;
3429
3430         mutex_lock(&wl->mutex);
3431         if (wl->operating)
3432                 goto out_mutex_unlock;
3433
3434         b43dbg(wl, "Adding Interface type %d\n", conf->type);
3435
3436         dev = wl->current_dev;
3437         wl->operating = 1;
3438         wl->if_id = conf->if_id;
3439         wl->if_type = conf->type;
3440         memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
3441
3442         spin_lock_irqsave(&wl->irq_lock, flags);
3443         b43_adjust_opmode(dev);
3444         b43_upload_card_macaddress(dev);
3445         spin_unlock_irqrestore(&wl->irq_lock, flags);
3446
3447         err = 0;
3448  out_mutex_unlock:
3449         mutex_unlock(&wl->mutex);
3450
3451         return err;
3452 }
3453
3454 static void b43_op_remove_interface(struct ieee80211_hw *hw,
3455                                     struct ieee80211_if_init_conf *conf)
3456 {
3457         struct b43_wl *wl = hw_to_b43_wl(hw);
3458         struct b43_wldev *dev = wl->current_dev;
3459         unsigned long flags;
3460
3461         b43dbg(wl, "Removing Interface type %d\n", conf->type);
3462
3463         mutex_lock(&wl->mutex);
3464
3465         B43_WARN_ON(!wl->operating);
3466         B43_WARN_ON(wl->if_id != conf->if_id);
3467
3468         wl->operating = 0;
3469
3470         spin_lock_irqsave(&wl->irq_lock, flags);
3471         b43_adjust_opmode(dev);
3472         memset(wl->mac_addr, 0, ETH_ALEN);
3473         b43_upload_card_macaddress(dev);
3474         spin_unlock_irqrestore(&wl->irq_lock, flags);
3475
3476         mutex_unlock(&wl->mutex);
3477 }
3478
3479 static int b43_op_start(struct ieee80211_hw *hw)
3480 {
3481         struct b43_wl *wl = hw_to_b43_wl(hw);
3482         struct b43_wldev *dev = wl->current_dev;
3483         int did_init = 0;
3484         int err = 0;
3485
3486         /* First register RFkill.
3487          * LEDs that are registered later depend on it. */
3488         b43_rfkill_init(dev);
3489
3490         mutex_lock(&wl->mutex);
3491
3492         if (b43_status(dev) < B43_STAT_INITIALIZED) {
3493                 err = b43_wireless_core_init(dev);
3494                 if (err)
3495                         goto out_mutex_unlock;
3496                 did_init = 1;
3497         }
3498
3499         if (b43_status(dev) < B43_STAT_STARTED) {
3500                 err = b43_wireless_core_start(dev);
3501                 if (err) {
3502                         if (did_init)
3503                                 b43_wireless_core_exit(dev);
3504                         goto out_mutex_unlock;
3505                 }
3506         }
3507
3508  out_mutex_unlock:
3509         mutex_unlock(&wl->mutex);
3510
3511         return err;
3512 }
3513
3514 static void b43_op_stop(struct ieee80211_hw *hw)
3515 {
3516         struct b43_wl *wl = hw_to_b43_wl(hw);
3517         struct b43_wldev *dev = wl->current_dev;
3518
3519         b43_rfkill_exit(dev);
3520
3521         mutex_lock(&wl->mutex);
3522         if (b43_status(dev) >= B43_STAT_STARTED)
3523                 b43_wireless_core_stop(dev);
3524         b43_wireless_core_exit(dev);
3525         mutex_unlock(&wl->mutex);
3526 }
3527
3528 static int b43_op_set_retry_limit(struct ieee80211_hw *hw,
3529                                   u32 short_retry_limit, u32 long_retry_limit)
3530 {
3531         struct b43_wl *wl = hw_to_b43_wl(hw);
3532         struct b43_wldev *dev;
3533         int err = 0;
3534
3535         mutex_lock(&wl->mutex);
3536         dev = wl->current_dev;
3537         if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED))) {
3538                 err = -ENODEV;
3539                 goto out_unlock;
3540         }
3541         b43_set_retry_limits(dev, short_retry_limit, long_retry_limit);
3542 out_unlock:
3543         mutex_unlock(&wl->mutex);
3544
3545         return err;
3546 }
3547
3548 static const struct ieee80211_ops b43_hw_ops = {
3549         .tx                     = b43_op_tx,
3550         .conf_tx                = b43_op_conf_tx,
3551         .add_interface          = b43_op_add_interface,
3552         .remove_interface       = b43_op_remove_interface,
3553         .config                 = b43_op_config,
3554         .config_interface       = b43_op_config_interface,
3555         .configure_filter       = b43_op_configure_filter,
3556         .set_key                = b43_op_set_key,
3557         .get_stats              = b43_op_get_stats,
3558         .get_tx_stats           = b43_op_get_tx_stats,
3559         .start                  = b43_op_start,
3560         .stop                   = b43_op_stop,
3561         .set_retry_limit        = b43_op_set_retry_limit,
3562 };
3563
3564 /* Hard-reset the chip. Do not call this directly.
3565  * Use b43_controller_restart()
3566  */
3567 static void b43_chip_reset(struct work_struct *work)
3568 {
3569         struct b43_wldev *dev =
3570             container_of(work, struct b43_wldev, restart_work);
3571         struct b43_wl *wl = dev->wl;
3572         int err = 0;
3573         int prev_status;
3574
3575         mutex_lock(&wl->mutex);
3576
3577         prev_status = b43_status(dev);
3578         /* Bring the device down... */
3579         if (prev_status >= B43_STAT_STARTED)
3580                 b43_wireless_core_stop(dev);
3581         if (prev_status >= B43_STAT_INITIALIZED)
3582                 b43_wireless_core_exit(dev);
3583
3584         /* ...and up again. */
3585         if (prev_status >= B43_STAT_INITIALIZED) {
3586                 err = b43_wireless_core_init(dev);
3587                 if (err)
3588                         goto out;
3589         }
3590         if (prev_status >= B43_STAT_STARTED) {
3591                 err = b43_wireless_core_start(dev);
3592                 if (err) {
3593                         b43_wireless_core_exit(dev);
3594                         goto out;
3595                 }
3596         }
3597       out:
3598         mutex_unlock(&wl->mutex);
3599         if (err)
3600                 b43err(wl, "Controller restart FAILED\n");
3601         else
3602                 b43info(wl, "Controller restarted\n");
3603 }
3604
3605 static int b43_setup_modes(struct b43_wldev *dev,
3606                            int have_aphy, int have_bphy, int have_gphy)
3607 {
3608         struct ieee80211_hw *hw = dev->wl->hw;
3609         struct ieee80211_hw_mode *mode;
3610         struct b43_phy *phy = &dev->phy;
3611         int cnt = 0;
3612         int err;
3613
3614 /*FIXME: Don't tell ieee80211 about an A-PHY, because we currently don't support A-PHY. */
3615         have_aphy = 0;
3616
3617         phy->possible_phymodes = 0;
3618         for (; 1; cnt++) {
3619                 if (have_aphy) {
3620                         B43_WARN_ON(cnt >= B43_MAX_PHYHWMODES);
3621                         mode = &phy->hwmodes[cnt];
3622
3623                         mode->mode = MODE_IEEE80211A;
3624                         mode->num_channels = b43_a_chantable_size;
3625                         mode->channels = b43_a_chantable;
3626                         mode->num_rates = b43_a_ratetable_size;
3627                         mode->rates = b43_a_ratetable;
3628                         err = ieee80211_register_hwmode(hw, mode);
3629                         if (err)
3630                                 return err;
3631
3632                         phy->possible_phymodes |= B43_PHYMODE_A;
3633                         have_aphy = 0;
3634                         continue;
3635                 }
3636                 if (have_bphy) {
3637                         B43_WARN_ON(cnt >= B43_MAX_PHYHWMODES);
3638                         mode = &phy->hwmodes[cnt];
3639
3640                         mode->mode = MODE_IEEE80211B;
3641                         mode->num_channels = b43_bg_chantable_size;
3642                         mode->channels = b43_bg_chantable;
3643                         mode->num_rates = b43_b_ratetable_size;
3644                         mode->rates = b43_b_ratetable;
3645                         err = ieee80211_register_hwmode(hw, mode);
3646                         if (err)
3647                                 return err;
3648
3649                         phy->possible_phymodes |= B43_PHYMODE_B;
3650                         have_bphy = 0;
3651                         continue;
3652                 }
3653                 if (have_gphy) {
3654                         B43_WARN_ON(cnt >= B43_MAX_PHYHWMODES);
3655                         mode = &phy->hwmodes[cnt];
3656
3657                         mode->mode = MODE_IEEE80211G;
3658                         mode->num_channels = b43_bg_chantable_size;
3659                         mode->channels = b43_bg_chantable;
3660                         mode->num_rates = b43_g_ratetable_size;
3661                         mode->rates = b43_g_ratetable;
3662                         err = ieee80211_register_hwmode(hw, mode);
3663                         if (err)
3664                                 return err;
3665
3666                         phy->possible_phymodes |= B43_PHYMODE_G;
3667                         have_gphy = 0;
3668                         continue;
3669                 }
3670                 break;
3671         }
3672
3673         return 0;
3674 }
3675
3676 static void b43_wireless_core_detach(struct b43_wldev *dev)
3677 {
3678         /* We release firmware that late to not be required to re-request
3679          * is all the time when we reinit the core. */
3680         b43_release_firmware(dev);
3681 }
3682
3683 static int b43_wireless_core_attach(struct b43_wldev *dev)
3684 {
3685         struct b43_wl *wl = dev->wl;
3686         struct ssb_bus *bus = dev->dev->bus;
3687         struct pci_dev *pdev = bus->host_pci;
3688         int err;
3689         int have_aphy = 0, have_bphy = 0, have_gphy = 0;
3690         u32 tmp;
3691
3692         /* Do NOT do any device initialization here.
3693          * Do it in wireless_core_init() instead.
3694          * This function is for gathering basic information about the HW, only.
3695          * Also some structs may be set up here. But most likely you want to have
3696          * that in core_init(), too.
3697          */
3698
3699         err = ssb_bus_powerup(bus, 0);
3700         if (err) {
3701                 b43err(wl, "Bus powerup failed\n");
3702                 goto out;
3703         }
3704         /* Get the PHY type. */
3705         if (dev->dev->id.revision >= 5) {
3706                 u32 tmshigh;
3707
3708                 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
3709                 have_aphy = !!(tmshigh & B43_TMSHIGH_APHY);
3710                 have_gphy = !!(tmshigh & B43_TMSHIGH_GPHY);
3711                 if (!have_aphy && !have_gphy)
3712                         have_bphy = 1;
3713         } else if (dev->dev->id.revision == 4) {
3714                 have_gphy = 1;
3715                 have_aphy = 1;
3716         } else
3717                 have_bphy = 1;
3718
3719         dev->phy.gmode = (have_gphy || have_bphy);
3720         tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3721         b43_wireless_core_reset(dev, tmp);
3722
3723         err = b43_phy_versioning(dev);
3724         if (err)
3725                 goto err_powerdown;
3726         /* Check if this device supports multiband. */
3727         if (!pdev ||
3728             (pdev->device != 0x4312 &&
3729              pdev->device != 0x4319 && pdev->device != 0x4324)) {
3730                 /* No multiband support. */
3731                 have_aphy = 0;
3732                 have_bphy = 0;
3733                 have_gphy = 0;
3734                 switch (dev->phy.type) {
3735                 case B43_PHYTYPE_A:
3736                         have_aphy = 1;
3737                         break;
3738                 case B43_PHYTYPE_B:
3739                         have_bphy = 1;
3740                         break;
3741                 case B43_PHYTYPE_G:
3742                         have_gphy = 1;
3743                         break;
3744                 default:
3745                         B43_WARN_ON(1);
3746                 }
3747         }
3748         dev->phy.gmode = (have_gphy || have_bphy);
3749         tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3750         b43_wireless_core_reset(dev, tmp);
3751
3752         err = b43_validate_chipaccess(dev);
3753         if (err)
3754                 goto err_powerdown;
3755         err = b43_setup_modes(dev, have_aphy, have_bphy, have_gphy);
3756         if (err)
3757                 goto err_powerdown;
3758
3759         /* Now set some default "current_dev" */
3760         if (!wl->current_dev)
3761                 wl->current_dev = dev;
3762         INIT_WORK(&dev->restart_work, b43_chip_reset);
3763
3764         b43_radio_turn_off(dev, 1);
3765         b43_switch_analog(dev, 0);
3766         ssb_device_disable(dev->dev, 0);
3767         ssb_bus_may_powerdown(bus);
3768
3769 out:
3770         return err;
3771
3772 err_powerdown:
3773         ssb_bus_may_powerdown(bus);
3774         return err;
3775 }
3776
3777 static void b43_one_core_detach(struct ssb_device *dev)
3778 {
3779         struct b43_wldev *wldev;
3780         struct b43_wl *wl;
3781
3782         wldev = ssb_get_drvdata(dev);
3783         wl = wldev->wl;
3784         cancel_work_sync(&wldev->restart_work);
3785         b43_debugfs_remove_device(wldev);
3786         b43_wireless_core_detach(wldev);
3787         list_del(&wldev->list);
3788         wl->nr_devs--;
3789         ssb_set_drvdata(dev, NULL);
3790         kfree(wldev);
3791 }
3792
3793 static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
3794 {
3795         struct b43_wldev *wldev;
3796         struct pci_dev *pdev;
3797         int err = -ENOMEM;
3798
3799         if (!list_empty(&wl->devlist)) {
3800                 /* We are not the first core on this chip. */
3801                 pdev = dev->bus->host_pci;
3802                 /* Only special chips support more than one wireless
3803                  * core, although some of the other chips have more than
3804                  * one wireless core as well. Check for this and
3805                  * bail out early.
3806                  */
3807                 if (!pdev ||
3808                     ((pdev->device != 0x4321) &&
3809                      (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
3810                         b43dbg(wl, "Ignoring unconnected 802.11 core\n");
3811                         return -ENODEV;
3812                 }
3813         }
3814
3815         wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
3816         if (!wldev)
3817                 goto out;
3818
3819         wldev->dev = dev;
3820         wldev->wl = wl;
3821         b43_set_status(wldev, B43_STAT_UNINIT);
3822         wldev->bad_frames_preempt = modparam_bad_frames_preempt;
3823         tasklet_init(&wldev->isr_tasklet,
3824                      (void (*)(unsigned long))b43_interrupt_tasklet,
3825                      (unsigned long)wldev);
3826         INIT_LIST_HEAD(&wldev->list);
3827
3828         err = b43_wireless_core_attach(wldev);
3829         if (err)
3830                 goto err_kfree_wldev;
3831
3832         list_add(&wldev->list, &wl->devlist);
3833         wl->nr_devs++;
3834         ssb_set_drvdata(dev, wldev);
3835         b43_debugfs_add_device(wldev);
3836
3837       out:
3838         return err;
3839
3840       err_kfree_wldev:
3841         kfree(wldev);
3842         return err;
3843 }
3844
3845 static void b43_sprom_fixup(struct ssb_bus *bus)
3846 {
3847         /* boardflags workarounds */
3848         if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
3849             bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
3850                 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
3851         if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3852             bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
3853                 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
3854 }
3855
3856 static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
3857 {
3858         struct ieee80211_hw *hw = wl->hw;
3859
3860         ssb_set_devtypedata(dev, NULL);
3861         ieee80211_free_hw(hw);
3862 }
3863
3864 static int b43_wireless_init(struct ssb_device *dev)
3865 {
3866         struct ssb_sprom *sprom = &dev->bus->sprom;
3867         struct ieee80211_hw *hw;
3868         struct b43_wl *wl;
3869         int err = -ENOMEM;
3870
3871         b43_sprom_fixup(dev->bus);
3872
3873         hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
3874         if (!hw) {
3875                 b43err(NULL, "Could not allocate ieee80211 device\n");
3876                 goto out;
3877         }
3878
3879         /* fill hw info */
3880         hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
3881                     IEEE80211_HW_RX_INCLUDES_FCS;
3882         hw->max_signal = 100;
3883         hw->max_rssi = -110;
3884         hw->max_noise = -110;
3885         hw->queues = 1;         /* FIXME: hardware has more queues */
3886         SET_IEEE80211_DEV(hw, dev->dev);
3887         if (is_valid_ether_addr(sprom->et1mac))
3888                 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
3889         else
3890                 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
3891
3892         /* Get and initialize struct b43_wl */
3893         wl = hw_to_b43_wl(hw);
3894         memset(wl, 0, sizeof(*wl));
3895         wl->hw = hw;
3896         spin_lock_init(&wl->irq_lock);
3897         spin_lock_init(&wl->leds_lock);
3898         mutex_init(&wl->mutex);
3899         INIT_LIST_HEAD(&wl->devlist);
3900
3901         ssb_set_devtypedata(dev, wl);
3902         b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
3903         err = 0;
3904       out:
3905         return err;
3906 }
3907
3908 static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
3909 {
3910         struct b43_wl *wl;
3911         int err;
3912         int first = 0;
3913
3914         wl = ssb_get_devtypedata(dev);
3915         if (!wl) {
3916                 /* Probing the first core. Must setup common struct b43_wl */
3917                 first = 1;
3918                 err = b43_wireless_init(dev);
3919                 if (err)
3920                         goto out;
3921                 wl = ssb_get_devtypedata(dev);
3922                 B43_WARN_ON(!wl);
3923         }
3924         err = b43_one_core_attach(dev, wl);
3925         if (err)
3926                 goto err_wireless_exit;
3927
3928         if (first) {
3929                 err = ieee80211_register_hw(wl->hw);
3930                 if (err)
3931                         goto err_one_core_detach;
3932         }
3933
3934       out:
3935         return err;
3936
3937       err_one_core_detach:
3938         b43_one_core_detach(dev);
3939       err_wireless_exit:
3940         if (first)
3941                 b43_wireless_exit(dev, wl);
3942         return err;
3943 }
3944
3945 static void b43_remove(struct ssb_device *dev)
3946 {
3947         struct b43_wl *wl = ssb_get_devtypedata(dev);
3948         struct b43_wldev *wldev = ssb_get_drvdata(dev);
3949
3950         B43_WARN_ON(!wl);
3951         if (wl->current_dev == wldev)
3952                 ieee80211_unregister_hw(wl->hw);
3953
3954         b43_one_core_detach(dev);
3955
3956         if (list_empty(&wl->devlist)) {
3957                 /* Last core on the chip unregistered.
3958                  * We can destroy common struct b43_wl.
3959                  */
3960                 b43_wireless_exit(dev, wl);
3961         }
3962 }
3963
3964 /* Perform a hardware reset. This can be called from any context. */
3965 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
3966 {
3967         /* Must avoid requeueing, if we are in shutdown. */
3968         if (b43_status(dev) < B43_STAT_INITIALIZED)
3969                 return;
3970         b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
3971         queue_work(dev->wl->hw->workqueue, &dev->restart_work);
3972 }
3973
3974 #ifdef CONFIG_PM
3975
3976 static int b43_suspend(struct ssb_device *dev, pm_message_t state)
3977 {
3978         struct b43_wldev *wldev = ssb_get_drvdata(dev);
3979         struct b43_wl *wl = wldev->wl;
3980
3981         b43dbg(wl, "Suspending...\n");
3982
3983         mutex_lock(&wl->mutex);
3984         wldev->suspend_init_status = b43_status(wldev);
3985         if (wldev->suspend_init_status >= B43_STAT_STARTED)
3986                 b43_wireless_core_stop(wldev);
3987         if (wldev->suspend_init_status >= B43_STAT_INITIALIZED)
3988                 b43_wireless_core_exit(wldev);
3989         mutex_unlock(&wl->mutex);
3990
3991         b43dbg(wl, "Device suspended.\n");
3992
3993         return 0;
3994 }
3995
3996 static int b43_resume(struct ssb_device *dev)
3997 {
3998         struct b43_wldev *wldev = ssb_get_drvdata(dev);
3999         struct b43_wl *wl = wldev->wl;
4000         int err = 0;
4001
4002         b43dbg(wl, "Resuming...\n");
4003
4004         mutex_lock(&wl->mutex);
4005         if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
4006                 err = b43_wireless_core_init(wldev);
4007                 if (err) {
4008                         b43err(wl, "Resume failed at core init\n");
4009                         goto out;
4010                 }
4011         }
4012         if (wldev->suspend_init_status >= B43_STAT_STARTED) {
4013                 err = b43_wireless_core_start(wldev);
4014                 if (err) {
4015                         b43_wireless_core_exit(wldev);
4016                         b43err(wl, "Resume failed at core start\n");
4017                         goto out;
4018                 }
4019         }
4020         mutex_unlock(&wl->mutex);
4021
4022         b43dbg(wl, "Device resumed.\n");
4023       out:
4024         return err;
4025 }
4026
4027 #else /* CONFIG_PM */
4028 # define b43_suspend    NULL
4029 # define b43_resume     NULL
4030 #endif /* CONFIG_PM */
4031
4032 static struct ssb_driver b43_ssb_driver = {
4033         .name           = KBUILD_MODNAME,
4034         .id_table       = b43_ssb_tbl,
4035         .probe          = b43_probe,
4036         .remove         = b43_remove,
4037         .suspend        = b43_suspend,
4038         .resume         = b43_resume,
4039 };
4040
4041 static int __init b43_init(void)
4042 {
4043         int err;
4044
4045         b43_debugfs_init();
4046         err = b43_pcmcia_init();
4047         if (err)
4048                 goto err_dfs_exit;
4049         err = ssb_driver_register(&b43_ssb_driver);
4050         if (err)
4051                 goto err_pcmcia_exit;
4052
4053         return err;
4054
4055 err_pcmcia_exit:
4056         b43_pcmcia_exit();
4057 err_dfs_exit:
4058         b43_debugfs_exit();
4059         return err;
4060 }
4061
4062 static void __exit b43_exit(void)
4063 {
4064         ssb_driver_unregister(&b43_ssb_driver);
4065         b43_pcmcia_exit();
4066         b43_debugfs_exit();
4067 }
4068
4069 module_init(b43_init)
4070 module_exit(b43_exit)