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   1 /*
   2
   3   Broadcom B43 wireless driver
   4
   5   Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
   6   Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
   7   Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
   8   Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
   9   Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
  10
  11   Some parts of the code in this file are derived from the ipw2200
  12   driver  Copyright(c) 2003 - 2004 Intel Corporation.
  13
  14   This program is free software; you can redistribute it and/or modify
  15   it under the terms of the GNU General Public License as published by
  16   the Free Software Foundation; either version 2 of the License, or
  17   (at your option) any later version.
  18
  19   This program is distributed in the hope that it will be useful,
  20   but WITHOUT ANY WARRANTY; without even the implied warranty of
  21   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22   GNU General Public License for more details.
  23
  24   You should have received a copy of the GNU General Public License
  25   along with this program; see the file COPYING.  If not, write to
  26   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  27   Boston, MA 02110-1301, USA.
  28
  29 */
  30
  31 #include <linux/delay.h>
  32 #include <linux/init.h>
  33 #include <linux/moduleparam.h>
  34 #include <linux/if_arp.h>
  35 #include <linux/etherdevice.h>
  36 #include <linux/version.h>
  37 #include <linux/firmware.h>
  38 #include <linux/wireless.h>
  39 #include <linux/workqueue.h>
  40 #include <linux/skbuff.h>
  41 #include <linux/dma-mapping.h>
  42 #include <asm/unaligned.h>
  43
  44 #include "b43.h"
  45 #include "main.h"
  46 #include "debugfs.h"
  47 #include "phy.h"
  48 #include "dma.h"
  49 #include "pio.h"
  50 #include "sysfs.h"
  51 #include "xmit.h"
  52 #include "lo.h"
  53 #include "pcmcia.h"
  54
  55 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
  56 MODULE_AUTHOR("Martin Langer");
  57 MODULE_AUTHOR("Stefano Brivio");
  58 MODULE_AUTHOR("Michael Buesch");
  59 MODULE_LICENSE("GPL");
  60
  61 extern char *nvram_get(char *name);
  62
  63 #if defined(CONFIG_B43_DMA) && defined(CONFIG_B43_PIO)
  64 static int modparam_pio;
  65 module_param_named(pio, modparam_pio, int, 0444);
  66 MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
  67 #elif defined(CONFIG_B43_DMA)
  68 # define modparam_pio   0
  69 #elif defined(CONFIG_B43_PIO)
  70 # define modparam_pio   1
  71 #endif
  72
  73 static int modparam_bad_frames_preempt;
  74 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
  75 MODULE_PARM_DESC(bad_frames_preempt,
  76                  "enable(1) / disable(0) Bad Frames Preemption");
  77
  78 static char modparam_fwpostfix[16];
  79 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
  80 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
  81
  82 static int modparam_hwpctl;
  83 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
  84 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
  85
  86 static int modparam_nohwcrypt;
  87 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
  88 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  89
  90 static const struct ssb_device_id b43_ssb_tbl[] = {
  91         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
  92         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
  93         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
  94         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
  95         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
  96         SSB_DEVTABLE_END
  97 };
  98
  99 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
 100
 101 /* Channel and ratetables are shared for all devices.
 102  * They can't be const, because ieee80211 puts some precalculated
 103  * data in there. This data is the same for all devices, so we don't
 104  * get concurrency issues */
 105 #define RATETAB_ENT(_rateid, _flags) \
 106         {                                                       \
 107                 .rate   = B43_RATE_TO_BASE100KBPS(_rateid),     \
 108                 .val    = (_rateid),                            \
 109                 .val2   = (_rateid),                            \
 110                 .flags  = (_flags),                             \
 111         }
 112 static struct ieee80211_rate __b43_ratetable[] = {
 113         RATETAB_ENT(B43_CCK_RATE_1MB, IEEE80211_RATE_CCK),
 114         RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_CCK_2),
 115         RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_CCK_2),
 116         RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_CCK_2),
 117         RATETAB_ENT(B43_OFDM_RATE_6MB, IEEE80211_RATE_OFDM),
 118         RATETAB_ENT(B43_OFDM_RATE_9MB, IEEE80211_RATE_OFDM),
 119         RATETAB_ENT(B43_OFDM_RATE_12MB, IEEE80211_RATE_OFDM),
 120         RATETAB_ENT(B43_OFDM_RATE_18MB, IEEE80211_RATE_OFDM),
 121         RATETAB_ENT(B43_OFDM_RATE_24MB, IEEE80211_RATE_OFDM),
 122         RATETAB_ENT(B43_OFDM_RATE_36MB, IEEE80211_RATE_OFDM),
 123         RATETAB_ENT(B43_OFDM_RATE_48MB, IEEE80211_RATE_OFDM),
 124         RATETAB_ENT(B43_OFDM_RATE_54MB, IEEE80211_RATE_OFDM),
 125 };
 126
 127 #define b43_a_ratetable         (__b43_ratetable + 4)
 128 #define b43_a_ratetable_size    8
 129 #define b43_b_ratetable         (__b43_ratetable + 0)
 130 #define b43_b_ratetable_size    4
 131 #define b43_g_ratetable         (__b43_ratetable + 0)
 132 #define b43_g_ratetable_size    12
 133
 134 #define CHANTAB_ENT(_chanid, _freq) \
 135         {                                                       \
 136                 .chan   = (_chanid),                            \
 137                 .freq   = (_freq),                              \
 138                 .val    = (_chanid),                            \
 139                 .flag   = IEEE80211_CHAN_W_SCAN |               \
 140                           IEEE80211_CHAN_W_ACTIVE_SCAN |        \
 141                           IEEE80211_CHAN_W_IBSS,                \
 142                 .power_level    = 0xFF,                         \
 143                 .antenna_max    = 0xFF,                         \
 144         }
 145 static struct ieee80211_channel b43_bg_chantable[] = {
 146         CHANTAB_ENT(1, 2412),
 147         CHANTAB_ENT(2, 2417),
 148         CHANTAB_ENT(3, 2422),
 149         CHANTAB_ENT(4, 2427),
 150         CHANTAB_ENT(5, 2432),
 151         CHANTAB_ENT(6, 2437),
 152         CHANTAB_ENT(7, 2442),
 153         CHANTAB_ENT(8, 2447),
 154         CHANTAB_ENT(9, 2452),
 155         CHANTAB_ENT(10, 2457),
 156         CHANTAB_ENT(11, 2462),
 157         CHANTAB_ENT(12, 2467),
 158         CHANTAB_ENT(13, 2472),
 159         CHANTAB_ENT(14, 2484),
 160 };
 161
 162 #define b43_bg_chantable_size   ARRAY_SIZE(b43_bg_chantable)
 163 static struct ieee80211_channel b43_a_chantable[] = {
 164         CHANTAB_ENT(36, 5180),
 165         CHANTAB_ENT(40, 5200),
 166         CHANTAB_ENT(44, 5220),
 167         CHANTAB_ENT(48, 5240),
 168         CHANTAB_ENT(52, 5260),
 169         CHANTAB_ENT(56, 5280),
 170         CHANTAB_ENT(60, 5300),
 171         CHANTAB_ENT(64, 5320),
 172         CHANTAB_ENT(149, 5745),
 173         CHANTAB_ENT(153, 5765),
 174         CHANTAB_ENT(157, 5785),
 175         CHANTAB_ENT(161, 5805),
 176         CHANTAB_ENT(165, 5825),
 177 };
 178
 179 #define b43_a_chantable_size    ARRAY_SIZE(b43_a_chantable)
 180
 181 static void b43_wireless_core_exit(struct b43_wldev *dev);
 182 static int b43_wireless_core_init(struct b43_wldev *dev);
 183 static void b43_wireless_core_stop(struct b43_wldev *dev);
 184 static int b43_wireless_core_start(struct b43_wldev *dev);
 185
 186 static int b43_ratelimit(struct b43_wl *wl)
 187 {
 188         if (!wl || !wl->current_dev)
 189                 return 1;
 190         if (b43_status(wl->current_dev) < B43_STAT_STARTED)
 191                 return 1;
 192         /* We are up and running.
 193          * Ratelimit the messages to avoid DoS over the net. */
 194         return net_ratelimit();
 195 }
 196
 197 void b43info(struct b43_wl *wl, const char *fmt, ...)
 198 {
 199         va_list args;
 200
 201         if (!b43_ratelimit(wl))
 202                 return;
 203         va_start(args, fmt);
 204         printk(KERN_INFO "b43-%s: ",
 205                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
 206         vprintk(fmt, args);
 207         va_end(args);
 208 }
 209
 210 void b43err(struct b43_wl *wl, const char *fmt, ...)
 211 {
 212         va_list args;
 213
 214         if (!b43_ratelimit(wl))
 215                 return;
 216         va_start(args, fmt);
 217         printk(KERN_ERR "b43-%s ERROR: ",
 218                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
 219         vprintk(fmt, args);
 220         va_end(args);
 221 }
 222
 223 void b43warn(struct b43_wl *wl, const char *fmt, ...)
 224 {
 225         va_list args;
 226
 227         if (!b43_ratelimit(wl))
 228                 return;
 229         va_start(args, fmt);
 230         printk(KERN_WARNING "b43-%s warning: ",
 231                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
 232         vprintk(fmt, args);
 233         va_end(args);
 234 }
 235
 236 #if B43_DEBUG
 237 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
 238 {
 239         va_list args;
 240
 241         va_start(args, fmt);
 242         printk(KERN_DEBUG "b43-%s debug: ",
 243                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
 244         vprintk(fmt, args);
 245         va_end(args);
 246 }
 247 #endif /* DEBUG */
 248
 249 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
 250 {
 251         u32 macctl;
 252
 253         B43_WARN_ON(offset % 4 != 0);
 254
 255         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 256         if (macctl & B43_MACCTL_BE)
 257                 val = swab32(val);
 258
 259         b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
 260         mmiowb();
 261         b43_write32(dev, B43_MMIO_RAM_DATA, val);
 262 }
 263
 264 static inline
 265     void b43_shm_control_word(struct b43_wldev *dev, u16 routing, u16 offset)
 266 {
 267         u32 control;
 268
 269         /* "offset" is the WORD offset. */
 270
 271         control = routing;
 272         control <<= 16;
 273         control |= offset;
 274         b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
 275 }
 276
 277 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
 278 {
 279         u32 ret;
 280
 281         if (routing == B43_SHM_SHARED) {
 282                 B43_WARN_ON(offset & 0x0001);
 283                 if (offset & 0x0003) {
 284                         /* Unaligned access */
 285                         b43_shm_control_word(dev, routing, offset >> 2);
 286                         ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
 287                         ret <<= 16;
 288                         b43_shm_control_word(dev, routing, (offset >> 2) + 1);
 289                         ret |= b43_read16(dev, B43_MMIO_SHM_DATA);
 290
 291                         return ret;
 292                 }
 293                 offset >>= 2;
 294         }
 295         b43_shm_control_word(dev, routing, offset);
 296         ret = b43_read32(dev, B43_MMIO_SHM_DATA);
 297
 298         return ret;
 299 }
 300
 301 u16 b43_shm_read16(struct b43_wldev * dev, u16 routing, u16 offset)
 302 {
 303         u16 ret;
 304
 305         if (routing == B43_SHM_SHARED) {
 306                 B43_WARN_ON(offset & 0x0001);
 307                 if (offset & 0x0003) {
 308                         /* Unaligned access */
 309                         b43_shm_control_word(dev, routing, offset >> 2);
 310                         ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
 311
 312                         return ret;
 313                 }
 314                 offset >>= 2;
 315         }
 316         b43_shm_control_word(dev, routing, offset);
 317         ret = b43_read16(dev, B43_MMIO_SHM_DATA);
 318
 319         return ret;
 320 }
 321
 322 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
 323 {
 324         if (routing == B43_SHM_SHARED) {
 325                 B43_WARN_ON(offset & 0x0001);
 326                 if (offset & 0x0003) {
 327                         /* Unaligned access */
 328                         b43_shm_control_word(dev, routing, offset >> 2);
 329                         mmiowb();
 330                         b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
 331                                     (value >> 16) & 0xffff);
 332                         mmiowb();
 333                         b43_shm_control_word(dev, routing, (offset >> 2) + 1);
 334                         mmiowb();
 335                         b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
 336                         return;
 337                 }
 338                 offset >>= 2;
 339         }
 340         b43_shm_control_word(dev, routing, offset);
 341         mmiowb();
 342         b43_write32(dev, B43_MMIO_SHM_DATA, value);
 343 }
 344
 345 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
 346 {
 347         if (routing == B43_SHM_SHARED) {
 348                 B43_WARN_ON(offset & 0x0001);
 349                 if (offset & 0x0003) {
 350                         /* Unaligned access */
 351                         b43_shm_control_word(dev, routing, offset >> 2);
 352                         mmiowb();
 353                         b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
 354                         return;
 355                 }
 356                 offset >>= 2;
 357         }
 358         b43_shm_control_word(dev, routing, offset);
 359         mmiowb();
 360         b43_write16(dev, B43_MMIO_SHM_DATA, value);
 361 }
 362
 363 /* Read HostFlags */
 364 u32 b43_hf_read(struct b43_wldev * dev)
 365 {
 366         u32 ret;
 367
 368         ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
 369         ret <<= 16;
 370         ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
 371
 372         return ret;
 373 }
 374
 375 /* Write HostFlags */
 376 void b43_hf_write(struct b43_wldev *dev, u32 value)
 377 {
 378         b43_shm_write16(dev, B43_SHM_SHARED,
 379                         B43_SHM_SH_HOSTFLO, (value & 0x0000FFFF));
 380         b43_shm_write16(dev, B43_SHM_SHARED,
 381                         B43_SHM_SH_HOSTFHI, ((value & 0xFFFF0000) >> 16));
 382 }
 383
 384 void b43_tsf_read(struct b43_wldev *dev, u64 * tsf)
 385 {
 386         /* We need to be careful. As we read the TSF from multiple
 387          * registers, we should take care of register overflows.
 388          * In theory, the whole tsf read process should be atomic.
 389          * We try to be atomic here, by restaring the read process,
 390          * if any of the high registers changed (overflew).
 391          */
 392         if (dev->dev->id.revision >= 3) {
 393                 u32 low, high, high2;
 394
 395                 do {
 396                         high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
 397                         low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
 398                         high2 = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
 399                 } while (unlikely(high != high2));
 400
 401                 *tsf = high;
 402                 *tsf <<= 32;
 403                 *tsf |= low;
 404         } else {
 405                 u64 tmp;
 406                 u16 v0, v1, v2, v3;
 407                 u16 test1, test2, test3;
 408
 409                 do {
 410                         v3 = b43_read16(dev, B43_MMIO_TSF_3);
 411                         v2 = b43_read16(dev, B43_MMIO_TSF_2);
 412                         v1 = b43_read16(dev, B43_MMIO_TSF_1);
 413                         v0 = b43_read16(dev, B43_MMIO_TSF_0);
 414
 415                         test3 = b43_read16(dev, B43_MMIO_TSF_3);
 416                         test2 = b43_read16(dev, B43_MMIO_TSF_2);
 417                         test1 = b43_read16(dev, B43_MMIO_TSF_1);
 418                 } while (v3 != test3 || v2 != test2 || v1 != test1);
 419
 420                 *tsf = v3;
 421                 *tsf <<= 48;
 422                 tmp = v2;
 423                 tmp <<= 32;
 424                 *tsf |= tmp;
 425                 tmp = v1;
 426                 tmp <<= 16;
 427                 *tsf |= tmp;
 428                 *tsf |= v0;
 429         }
 430 }
 431
 432 static void b43_time_lock(struct b43_wldev *dev)
 433 {
 434         u32 macctl;
 435
 436         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 437         macctl |= B43_MACCTL_TBTTHOLD;
 438         b43_write32(dev, B43_MMIO_MACCTL, macctl);
 439         /* Commit the write */
 440         b43_read32(dev, B43_MMIO_MACCTL);
 441 }
 442
 443 static void b43_time_unlock(struct b43_wldev *dev)
 444 {
 445         u32 macctl;
 446
 447         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 448         macctl &= ~B43_MACCTL_TBTTHOLD;
 449         b43_write32(dev, B43_MMIO_MACCTL, macctl);
 450         /* Commit the write */
 451         b43_read32(dev, B43_MMIO_MACCTL);
 452 }
 453
 454 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
 455 {
 456         /* Be careful with the in-progress timer.
 457          * First zero out the low register, so we have a full
 458          * register-overflow duration to complete the operation.
 459          */
 460         if (dev->dev->id.revision >= 3) {
 461                 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
 462                 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
 463
 464                 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, 0);
 465                 mmiowb();
 466                 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, hi);
 467                 mmiowb();
 468                 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, lo);
 469         } else {
 470                 u16 v0 = (tsf & 0x000000000000FFFFULL);
 471                 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
 472                 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
 473                 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
 474
 475                 b43_write16(dev, B43_MMIO_TSF_0, 0);
 476                 mmiowb();
 477                 b43_write16(dev, B43_MMIO_TSF_3, v3);
 478                 mmiowb();
 479                 b43_write16(dev, B43_MMIO_TSF_2, v2);
 480                 mmiowb();
 481                 b43_write16(dev, B43_MMIO_TSF_1, v1);
 482                 mmiowb();
 483                 b43_write16(dev, B43_MMIO_TSF_0, v0);
 484         }
 485 }
 486
 487 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
 488 {
 489         b43_time_lock(dev);
 490         b43_tsf_write_locked(dev, tsf);
 491         b43_time_unlock(dev);
 492 }
 493
 494 static
 495 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac)
 496 {
 497         static const u8 zero_addr[ETH_ALEN] = { 0 };
 498         u16 data;
 499
 500         if (!mac)
 501                 mac = zero_addr;
 502
 503         offset |= 0x0020;
 504         b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
 505
 506         data = mac[0];
 507         data |= mac[1] << 8;
 508         b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
 509         data = mac[2];
 510         data |= mac[3] << 8;
 511         b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
 512         data = mac[4];
 513         data |= mac[5] << 8;
 514         b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
 515 }
 516
 517 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
 518 {
 519         const u8 *mac;
 520         const u8 *bssid;
 521         u8 mac_bssid[ETH_ALEN * 2];
 522         int i;
 523         u32 tmp;
 524
 525         bssid = dev->wl->bssid;
 526         mac = dev->wl->mac_addr;
 527
 528         b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
 529
 530         memcpy(mac_bssid, mac, ETH_ALEN);
 531         memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
 532
 533         /* Write our MAC address and BSSID to template ram */
 534         for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
 535                 tmp = (u32) (mac_bssid[i + 0]);
 536                 tmp |= (u32) (mac_bssid[i + 1]) << 8;
 537                 tmp |= (u32) (mac_bssid[i + 2]) << 16;
 538                 tmp |= (u32) (mac_bssid[i + 3]) << 24;
 539                 b43_ram_write(dev, 0x20 + i, tmp);
 540         }
 541 }
 542
 543 static void b43_upload_card_macaddress(struct b43_wldev *dev)
 544 {
 545         b43_write_mac_bssid_templates(dev);
 546         b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
 547 }
 548
 549 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
 550 {
 551         /* slot_time is in usec. */
 552         if (dev->phy.type != B43_PHYTYPE_G)
 553                 return;
 554         b43_write16(dev, 0x684, 510 + slot_time);
 555         b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
 556 }
 557
 558 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
 559 {
 560         b43_set_slot_time(dev, 9);
 561         dev->short_slot = 1;
 562 }
 563
 564 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
 565 {
 566         b43_set_slot_time(dev, 20);
 567         dev->short_slot = 0;
 568 }
 569
 570 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
 571  * Returns the _previously_ enabled IRQ mask.
 572  */
 573 static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask)
 574 {
 575         u32 old_mask;
 576
 577         old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
 578         b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask);
 579
 580         return old_mask;
 581 }
 582
 583 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
 584  * Returns the _previously_ enabled IRQ mask.
 585  */
 586 static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask)
 587 {
 588         u32 old_mask;
 589
 590         old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
 591         b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
 592
 593         return old_mask;
 594 }
 595
 596 /* Synchronize IRQ top- and bottom-half.
 597  * IRQs must be masked before calling this.
 598  * This must not be called with the irq_lock held.
 599  */
 600 static void b43_synchronize_irq(struct b43_wldev *dev)
 601 {
 602         synchronize_irq(dev->dev->irq);
 603         tasklet_kill(&dev->isr_tasklet);
 604 }
 605
 606 /* DummyTransmission function, as documented on
 607  * http://bcm-specs.sipsolutions.net/DummyTransmission
 608  */
 609 void b43_dummy_transmission(struct b43_wldev *dev)
 610 {
 611         struct b43_phy *phy = &dev->phy;
 612         unsigned int i, max_loop;
 613         u16 value;
 614         u32 buffer[5] = {
 615                 0x00000000,
 616                 0x00D40000,
 617                 0x00000000,
 618                 0x01000000,
 619                 0x00000000,
 620         };
 621
 622         switch (phy->type) {
 623         case B43_PHYTYPE_A:
 624                 max_loop = 0x1E;
 625                 buffer[0] = 0x000201CC;
 626                 break;
 627         case B43_PHYTYPE_B:
 628         case B43_PHYTYPE_G:
 629                 max_loop = 0xFA;
 630                 buffer[0] = 0x000B846E;
 631                 break;
 632         default:
 633                 B43_WARN_ON(1);
 634                 return;
 635         }
 636
 637         for (i = 0; i < 5; i++)
 638                 b43_ram_write(dev, i * 4, buffer[i]);
 639
 640         /* Commit writes */
 641         b43_read32(dev, B43_MMIO_MACCTL);
 642
 643         b43_write16(dev, 0x0568, 0x0000);
 644         b43_write16(dev, 0x07C0, 0x0000);
 645         value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0);
 646         b43_write16(dev, 0x050C, value);
 647         b43_write16(dev, 0x0508, 0x0000);
 648         b43_write16(dev, 0x050A, 0x0000);
 649         b43_write16(dev, 0x054C, 0x0000);
 650         b43_write16(dev, 0x056A, 0x0014);
 651         b43_write16(dev, 0x0568, 0x0826);
 652         b43_write16(dev, 0x0500, 0x0000);
 653         b43_write16(dev, 0x0502, 0x0030);
 654
 655         if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
 656                 b43_radio_write16(dev, 0x0051, 0x0017);
 657         for (i = 0x00; i < max_loop; i++) {
 658                 value = b43_read16(dev, 0x050E);
 659                 if (value & 0x0080)
 660                         break;
 661                 udelay(10);
 662         }
 663         for (i = 0x00; i < 0x0A; i++) {
 664                 value = b43_read16(dev, 0x050E);
 665                 if (value & 0x0400)
 666                         break;
 667                 udelay(10);
 668         }
 669         for (i = 0x00; i < 0x0A; i++) {
 670                 value = b43_read16(dev, 0x0690);
 671                 if (!(value & 0x0100))
 672                         break;
 673                 udelay(10);
 674         }
 675         if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
 676                 b43_radio_write16(dev, 0x0051, 0x0037);
 677 }
 678
 679 static void key_write(struct b43_wldev *dev,
 680                       u8 index, u8 algorithm, const u8 * key)
 681 {
 682         unsigned int i;
 683         u32 offset;
 684         u16 value;
 685         u16 kidx;
 686
 687         /* Key index/algo block */
 688         kidx = b43_kidx_to_fw(dev, index);
 689         value = ((kidx << 4) | algorithm);
 690         b43_shm_write16(dev, B43_SHM_SHARED,
 691                         B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
 692
 693         /* Write the key to the Key Table Pointer offset */
 694         offset = dev->ktp + (index * B43_SEC_KEYSIZE);
 695         for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
 696                 value = key[i];
 697                 value |= (u16) (key[i + 1]) << 8;
 698                 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
 699         }
 700 }
 701
 702 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr)
 703 {
 704         u32 addrtmp[2] = { 0, 0, };
 705         u8 per_sta_keys_start = 8;
 706
 707         if (b43_new_kidx_api(dev))
 708                 per_sta_keys_start = 4;
 709
 710         B43_WARN_ON(index < per_sta_keys_start);
 711         /* We have two default TX keys and possibly two default RX keys.
 712          * Physical mac 0 is mapped to physical key 4 or 8, depending
 713          * on the firmware version.
 714          * So we must adjust the index here.
 715          */
 716         index -= per_sta_keys_start;
 717
 718         if (addr) {
 719                 addrtmp[0] = addr[0];
 720                 addrtmp[0] |= ((u32) (addr[1]) << 8);
 721                 addrtmp[0] |= ((u32) (addr[2]) << 16);
 722                 addrtmp[0] |= ((u32) (addr[3]) << 24);
 723                 addrtmp[1] = addr[4];
 724                 addrtmp[1] |= ((u32) (addr[5]) << 8);
 725         }
 726
 727         if (dev->dev->id.revision >= 5) {
 728                 /* Receive match transmitter address mechanism */
 729                 b43_shm_write32(dev, B43_SHM_RCMTA,
 730                                 (index * 2) + 0, addrtmp[0]);
 731                 b43_shm_write16(dev, B43_SHM_RCMTA,
 732                                 (index * 2) + 1, addrtmp[1]);
 733         } else {
 734                 /* RXE (Receive Engine) and
 735                  * PSM (Programmable State Machine) mechanism
 736                  */
 737                 if (index < 8) {
 738                         /* TODO write to RCM 16, 19, 22 and 25 */
 739                 } else {
 740                         b43_shm_write32(dev, B43_SHM_SHARED,
 741                                         B43_SHM_SH_PSM + (index * 6) + 0,
 742                                         addrtmp[0]);
 743                         b43_shm_write16(dev, B43_SHM_SHARED,
 744                                         B43_SHM_SH_PSM + (index * 6) + 4,
 745                                         addrtmp[1]);
 746                 }
 747         }
 748 }
 749
 750 static void do_key_write(struct b43_wldev *dev,
 751                          u8 index, u8 algorithm,
 752                          const u8 * key, size_t key_len, const u8 * mac_addr)
 753 {
 754         u8 buf[B43_SEC_KEYSIZE] = { 0, };
 755         u8 per_sta_keys_start = 8;
 756
 757         if (b43_new_kidx_api(dev))
 758                 per_sta_keys_start = 4;
 759
 760         B43_WARN_ON(index >= dev->max_nr_keys);
 761         B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
 762
 763         if (index >= per_sta_keys_start)
 764                 keymac_write(dev, index, NULL); /* First zero out mac. */
 765         if (key)
 766                 memcpy(buf, key, key_len);
 767         key_write(dev, index, algorithm, buf);
 768         if (index >= per_sta_keys_start)
 769                 keymac_write(dev, index, mac_addr);
 770
 771         dev->key[index].algorithm = algorithm;
 772 }
 773
 774 static int b43_key_write(struct b43_wldev *dev,
 775                          int index, u8 algorithm,
 776                          const u8 * key, size_t key_len,
 777                          const u8 * mac_addr,
 778                          struct ieee80211_key_conf *keyconf)
 779 {
 780         int i;
 781         int sta_keys_start;
 782
 783         if (key_len > B43_SEC_KEYSIZE)
 784                 return -EINVAL;
 785         for (i = 0; i < dev->max_nr_keys; i++) {
 786                 /* Check that we don't already have this key. */
 787                 B43_WARN_ON(dev->key[i].keyconf == keyconf);
 788         }
 789         if (index < 0) {
 790                 /* Either pairwise key or address is 00:00:00:00:00:00
 791                  * for transmit-only keys. Search the index. */
 792                 if (b43_new_kidx_api(dev))
 793                         sta_keys_start = 4;
 794                 else
 795                         sta_keys_start = 8;
 796                 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
 797                         if (!dev->key[i].keyconf) {
 798                                 /* found empty */
 799                                 index = i;
 800                                 break;
 801                         }
 802                 }
 803                 if (index < 0) {
 804                         b43err(dev->wl, "Out of hardware key memory\n");
 805                         return -ENOSPC;
 806                 }
 807         } else
 808                 B43_WARN_ON(index > 3);
 809
 810         do_key_write(dev, index, algorithm, key, key_len, mac_addr);
 811         if ((index <= 3) && !b43_new_kidx_api(dev)) {
 812                 /* Default RX key */
 813                 B43_WARN_ON(mac_addr);
 814                 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
 815         }
 816         keyconf->hw_key_idx = index;
 817         dev->key[index].keyconf = keyconf;
 818
 819         return 0;
 820 }
 821
 822 static int b43_key_clear(struct b43_wldev *dev, int index)
 823 {
 824         if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys)))
 825                 return -EINVAL;
 826         do_key_write(dev, index, B43_SEC_ALGO_NONE,
 827                      NULL, B43_SEC_KEYSIZE, NULL);
 828         if ((index <= 3) && !b43_new_kidx_api(dev)) {
 829                 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
 830                              NULL, B43_SEC_KEYSIZE, NULL);
 831         }
 832         dev->key[index].keyconf = NULL;
 833
 834         return 0;
 835 }
 836
 837 static void b43_clear_keys(struct b43_wldev *dev)
 838 {
 839         int i;
 840
 841         for (i = 0; i < dev->max_nr_keys; i++)
 842                 b43_key_clear(dev, i);
 843 }
 844
 845 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
 846 {
 847         u32 macctl;
 848         u16 ucstat;
 849         bool hwps;
 850         bool awake;
 851         int i;
 852
 853         B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
 854                     (ps_flags & B43_PS_DISABLED));
 855         B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
 856
 857         if (ps_flags & B43_PS_ENABLED) {
 858                 hwps = 1;
 859         } else if (ps_flags & B43_PS_DISABLED) {
 860                 hwps = 0;
 861         } else {
 862                 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
 863                 //      and thus is not an AP and we are associated, set bit 25
 864         }
 865         if (ps_flags & B43_PS_AWAKE) {
 866                 awake = 1;
 867         } else if (ps_flags & B43_PS_ASLEEP) {
 868                 awake = 0;
 869         } else {
 870                 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
 871                 //      or we are associated, or FIXME, or the latest PS-Poll packet sent was
 872                 //      successful, set bit26
 873         }
 874
 875 /* FIXME: For now we force awake-on and hwps-off */
 876         hwps = 0;
 877         awake = 1;
 878
 879         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 880         if (hwps)
 881                 macctl |= B43_MACCTL_HWPS;
 882         else
 883                 macctl &= ~B43_MACCTL_HWPS;
 884         if (awake)
 885                 macctl |= B43_MACCTL_AWAKE;
 886         else
 887                 macctl &= ~B43_MACCTL_AWAKE;
 888         b43_write32(dev, B43_MMIO_MACCTL, macctl);
 889         /* Commit write */
 890         b43_read32(dev, B43_MMIO_MACCTL);
 891         if (awake && dev->dev->id.revision >= 5) {
 892                 /* Wait for the microcode to wake up. */
 893                 for (i = 0; i < 100; i++) {
 894                         ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
 895                                                 B43_SHM_SH_UCODESTAT);
 896                         if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
 897                                 break;
 898                         udelay(10);
 899                 }
 900         }
 901 }
 902
 903 /* Turn the Analog ON/OFF */
 904 static void b43_switch_analog(struct b43_wldev *dev, int on)
 905 {
 906         b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
 907 }
 908
 909 void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
 910 {
 911         u32 tmslow;
 912         u32 macctl;
 913
 914         flags |= B43_TMSLOW_PHYCLKEN;
 915         flags |= B43_TMSLOW_PHYRESET;
 916         ssb_device_enable(dev->dev, flags);
 917         msleep(2);              /* Wait for the PLL to turn on. */
 918
 919         /* Now take the PHY out of Reset again */
 920         tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
 921         tmslow |= SSB_TMSLOW_FGC;
 922         tmslow &= ~B43_TMSLOW_PHYRESET;
 923         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
 924         ssb_read32(dev->dev, SSB_TMSLOW);       /* flush */
 925         msleep(1);
 926         tmslow &= ~SSB_TMSLOW_FGC;
 927         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
 928         ssb_read32(dev->dev, SSB_TMSLOW);       /* flush */
 929         msleep(1);
 930
 931         /* Turn Analog ON */
 932         b43_switch_analog(dev, 1);
 933
 934         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 935         macctl &= ~B43_MACCTL_GMODE;
 936         if (flags & B43_TMSLOW_GMODE)
 937                 macctl |= B43_MACCTL_GMODE;
 938         macctl |= B43_MACCTL_IHR_ENABLED;
 939         b43_write32(dev, B43_MMIO_MACCTL, macctl);
 940 }
 941
 942 static void handle_irq_transmit_status(struct b43_wldev *dev)
 943 {
 944         u32 v0, v1;
 945         u16 tmp;
 946         struct b43_txstatus stat;
 947
 948         while (1) {
 949                 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
 950                 if (!(v0 & 0x00000001))
 951                         break;
 952                 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
 953
 954                 stat.cookie = (v0 >> 16);
 955                 stat.seq = (v1 & 0x0000FFFF);
 956                 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
 957                 tmp = (v0 & 0x0000FFFF);
 958                 stat.frame_count = ((tmp & 0xF000) >> 12);
 959                 stat.rts_count = ((tmp & 0x0F00) >> 8);
 960                 stat.supp_reason = ((tmp & 0x001C) >> 2);
 961                 stat.pm_indicated = !!(tmp & 0x0080);
 962                 stat.intermediate = !!(tmp & 0x0040);
 963                 stat.for_ampdu = !!(tmp & 0x0020);
 964                 stat.acked = !!(tmp & 0x0002);
 965
 966                 b43_handle_txstatus(dev, &stat);
 967         }
 968 }
 969
 970 static void drain_txstatus_queue(struct b43_wldev *dev)
 971 {
 972         u32 dummy;
 973
 974         if (dev->dev->id.revision < 5)
 975                 return;
 976         /* Read all entries from the microcode TXstatus FIFO
 977          * and throw them away.
 978          */
 979         while (1) {
 980                 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
 981                 if (!(dummy & 0x00000001))
 982                         break;
 983                 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
 984         }
 985 }
 986
 987 static u32 b43_jssi_read(struct b43_wldev *dev)
 988 {
 989         u32 val = 0;
 990
 991         val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
 992         val <<= 16;
 993         val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
 994
 995         return val;
 996 }
 997
 998 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
 999 {
1000         b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1001         b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1002 }
1003
1004 static void b43_generate_noise_sample(struct b43_wldev *dev)
1005 {
1006         b43_jssi_write(dev, 0x7F7F7F7F);
1007         b43_write32(dev, B43_MMIO_STATUS2_BITFIELD,
1008                     b43_read32(dev, B43_MMIO_STATUS2_BITFIELD)
1009                     | (1 << 4));
1010         B43_WARN_ON(dev->noisecalc.channel_at_start != dev->phy.channel);
1011 }
1012
1013 static void b43_calculate_link_quality(struct b43_wldev *dev)
1014 {
1015         /* Top half of Link Quality calculation. */
1016
1017         if (dev->noisecalc.calculation_running)
1018                 return;
1019         dev->noisecalc.channel_at_start = dev->phy.channel;
1020         dev->noisecalc.calculation_running = 1;
1021         dev->noisecalc.nr_samples = 0;
1022
1023         b43_generate_noise_sample(dev);
1024 }
1025
1026 static void handle_irq_noise(struct b43_wldev *dev)
1027 {
1028         struct b43_phy *phy = &dev->phy;
1029         u16 tmp;
1030         u8 noise[4];
1031         u8 i, j;
1032         s32 average;
1033
1034         /* Bottom half of Link Quality calculation. */
1035
1036         B43_WARN_ON(!dev->noisecalc.calculation_running);
1037         if (dev->noisecalc.channel_at_start != phy->channel)
1038                 goto drop_calculation;
1039         *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1040         if (noise[0] == 0x7F || noise[1] == 0x7F ||
1041             noise[2] == 0x7F || noise[3] == 0x7F)
1042                 goto generate_new;
1043
1044         /* Get the noise samples. */
1045         B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1046         i = dev->noisecalc.nr_samples;
1047         noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1048         noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1049         noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1050         noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1051         dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1052         dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1053         dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1054         dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1055         dev->noisecalc.nr_samples++;
1056         if (dev->noisecalc.nr_samples == 8) {
1057                 /* Calculate the Link Quality by the noise samples. */
1058                 average = 0;
1059                 for (i = 0; i < 8; i++) {
1060                         for (j = 0; j < 4; j++)
1061                                 average += dev->noisecalc.samples[i][j];
1062                 }
1063                 average /= (8 * 4);
1064                 average *= 125;
1065                 average += 64;
1066                 average /= 128;
1067                 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1068                 tmp = (tmp / 128) & 0x1F;
1069                 if (tmp >= 8)
1070                         average += 2;
1071                 else
1072                         average -= 25;
1073                 if (tmp == 8)
1074                         average -= 72;
1075                 else
1076                         average -= 48;
1077
1078                 dev->stats.link_noise = average;
1079               drop_calculation:
1080                 dev->noisecalc.calculation_running = 0;
1081                 return;
1082         }
1083       generate_new:
1084         b43_generate_noise_sample(dev);
1085 }
1086
1087 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1088 {
1089         if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
1090                 ///TODO: PS TBTT
1091         } else {
1092                 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1093                         b43_power_saving_ctl_bits(dev, 0);
1094         }
1095         dev->reg124_set_0x4 = 0;
1096         if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
1097                 dev->reg124_set_0x4 = 1;
1098 }
1099
1100 static void handle_irq_atim_end(struct b43_wldev *dev)
1101 {
1102         if (!dev->reg124_set_0x4 /*FIXME rename this variable */ )
1103                 return;
1104         b43_write32(dev, B43_MMIO_STATUS2_BITFIELD,
1105                     b43_read32(dev, B43_MMIO_STATUS2_BITFIELD)
1106                     | 0x4);
1107 }
1108
1109 static void handle_irq_pmq(struct b43_wldev *dev)
1110 {
1111         u32 tmp;
1112
1113         //TODO: AP mode.
1114
1115         while (1) {
1116                 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1117                 if (!(tmp & 0x00000008))
1118                         break;
1119         }
1120         /* 16bit write is odd, but correct. */
1121         b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1122 }
1123
1124 static void b43_write_template_common(struct b43_wldev *dev,
1125                                       const u8 * data, u16 size,
1126                                       u16 ram_offset,
1127                                       u16 shm_size_offset, u8 rate)
1128 {
1129         u32 i, tmp;
1130         struct b43_plcp_hdr4 plcp;
1131
1132         plcp.data = 0;
1133         b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1134         b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1135         ram_offset += sizeof(u32);
1136         /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1137          * So leave the first two bytes of the next write blank.
1138          */
1139         tmp = (u32) (data[0]) << 16;
1140         tmp |= (u32) (data[1]) << 24;
1141         b43_ram_write(dev, ram_offset, tmp);
1142         ram_offset += sizeof(u32);
1143         for (i = 2; i < size; i += sizeof(u32)) {
1144                 tmp = (u32) (data[i + 0]);
1145                 if (i + 1 < size)
1146                         tmp |= (u32) (data[i + 1]) << 8;
1147                 if (i + 2 < size)
1148                         tmp |= (u32) (data[i + 2]) << 16;
1149                 if (i + 3 < size)
1150                         tmp |= (u32) (data[i + 3]) << 24;
1151                 b43_ram_write(dev, ram_offset + i - 2, tmp);
1152         }
1153         b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1154                         size + sizeof(struct b43_plcp_hdr6));
1155 }
1156
1157 static void b43_write_beacon_template(struct b43_wldev *dev,
1158                                       u16 ram_offset,
1159                                       u16 shm_size_offset, u8 rate)
1160 {
1161         int len;
1162         const u8 *data;
1163
1164         B43_WARN_ON(!dev->cached_beacon);
1165         len = min((size_t) dev->cached_beacon->len,
1166                   0x200 - sizeof(struct b43_plcp_hdr6));
1167         data = (const u8 *)(dev->cached_beacon->data);
1168         b43_write_template_common(dev, data,
1169                                   len, ram_offset, shm_size_offset, rate);
1170 }
1171
1172 static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
1173                                       u16 shm_offset, u16 size, u8 rate)
1174 {
1175         struct b43_plcp_hdr4 plcp;
1176         u32 tmp;
1177         __le16 dur;
1178
1179         plcp.data = 0;
1180         b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1181         dur = ieee80211_generic_frame_duration(dev->wl->hw,
1182                                                dev->wl->if_id, size,
1183                                                B43_RATE_TO_BASE100KBPS(rate));
1184         /* Write PLCP in two parts and timing for packet transfer */
1185         tmp = le32_to_cpu(plcp.data);
1186         b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF);
1187         b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16);
1188         b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur));
1189 }
1190
1191 /* Instead of using custom probe response template, this function
1192  * just patches custom beacon template by:
1193  * 1) Changing packet type
1194  * 2) Patching duration field
1195  * 3) Stripping TIM
1196  */
1197 static u8 *b43_generate_probe_resp(struct b43_wldev *dev,
1198                                    u16 * dest_size, u8 rate)
1199 {
1200         const u8 *src_data;
1201         u8 *dest_data;
1202         u16 src_size, elem_size, src_pos, dest_pos;
1203         __le16 dur;
1204         struct ieee80211_hdr *hdr;
1205
1206         B43_WARN_ON(!dev->cached_beacon);
1207         src_size = dev->cached_beacon->len;
1208         src_data = (const u8 *)dev->cached_beacon->data;
1209
1210         if (unlikely(src_size < 0x24)) {
1211                 b43dbg(dev->wl, "b43_generate_probe_resp: " "invalid beacon\n");
1212                 return NULL;
1213         }
1214
1215         dest_data = kmalloc(src_size, GFP_ATOMIC);
1216         if (unlikely(!dest_data))
1217                 return NULL;
1218
1219         /* 0x24 is offset of first variable-len Information-Element
1220          * in beacon frame.
1221          */
1222         memcpy(dest_data, src_data, 0x24);
1223         src_pos = dest_pos = 0x24;
1224         for (; src_pos < src_size - 2; src_pos += elem_size) {
1225                 elem_size = src_data[src_pos + 1] + 2;
1226                 if (src_data[src_pos] != 0x05) {        /* TIM */
1227                         memcpy(dest_data + dest_pos, src_data + src_pos,
1228                                elem_size);
1229                         dest_pos += elem_size;
1230                 }
1231         }
1232         *dest_size = dest_pos;
1233         hdr = (struct ieee80211_hdr *)dest_data;
1234
1235         /* Set the frame control. */
1236         hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1237                                          IEEE80211_STYPE_PROBE_RESP);
1238         dur = ieee80211_generic_frame_duration(dev->wl->hw,
1239                                                dev->wl->if_id, *dest_size,
1240                                                B43_RATE_TO_BASE100KBPS(rate));
1241         hdr->duration_id = dur;
1242
1243         return dest_data;
1244 }
1245
1246 static void b43_write_probe_resp_template(struct b43_wldev *dev,
1247                                           u16 ram_offset,
1248                                           u16 shm_size_offset, u8 rate)
1249 {
1250         u8 *probe_resp_data;
1251         u16 size;
1252
1253         B43_WARN_ON(!dev->cached_beacon);
1254         size = dev->cached_beacon->len;
1255         probe_resp_data = b43_generate_probe_resp(dev, &size, rate);
1256         if (unlikely(!probe_resp_data))
1257                 return;
1258
1259         /* Looks like PLCP headers plus packet timings are stored for
1260          * all possible basic rates
1261          */
1262         b43_write_probe_resp_plcp(dev, 0x31A, size, B43_CCK_RATE_1MB);
1263         b43_write_probe_resp_plcp(dev, 0x32C, size, B43_CCK_RATE_2MB);
1264         b43_write_probe_resp_plcp(dev, 0x33E, size, B43_CCK_RATE_5MB);
1265         b43_write_probe_resp_plcp(dev, 0x350, size, B43_CCK_RATE_11MB);
1266
1267         size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6));
1268         b43_write_template_common(dev, probe_resp_data,
1269                                   size, ram_offset, shm_size_offset, rate);
1270         kfree(probe_resp_data);
1271 }
1272
1273 static int b43_refresh_cached_beacon(struct b43_wldev *dev,
1274                                      struct sk_buff *beacon)
1275 {
1276         if (dev->cached_beacon)
1277                 kfree_skb(dev->cached_beacon);
1278         dev->cached_beacon = beacon;
1279
1280         return 0;
1281 }
1282
1283 static void b43_update_templates(struct b43_wldev *dev)
1284 {
1285         u32 status;
1286
1287         B43_WARN_ON(!dev->cached_beacon);
1288
1289         b43_write_beacon_template(dev, 0x68, 0x18, B43_CCK_RATE_1MB);
1290         b43_write_beacon_template(dev, 0x468, 0x1A, B43_CCK_RATE_1MB);
1291         b43_write_probe_resp_template(dev, 0x268, 0x4A, B43_CCK_RATE_11MB);
1292
1293         status = b43_read32(dev, B43_MMIO_STATUS2_BITFIELD);
1294         status |= 0x03;
1295         b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, status);
1296 }
1297
1298 static void b43_refresh_templates(struct b43_wldev *dev, struct sk_buff *beacon)
1299 {
1300         int err;
1301
1302         err = b43_refresh_cached_beacon(dev, beacon);
1303         if (unlikely(err))
1304                 return;
1305         b43_update_templates(dev);
1306 }
1307
1308 static void b43_set_ssid(struct b43_wldev *dev, const u8 * ssid, u8 ssid_len)
1309 {
1310         u32 tmp;
1311         u16 i, len;
1312
1313         len = min((u16) ssid_len, (u16) 0x100);
1314         for (i = 0; i < len; i += sizeof(u32)) {
1315                 tmp = (u32) (ssid[i + 0]);
1316                 if (i + 1 < len)
1317                         tmp |= (u32) (ssid[i + 1]) << 8;
1318                 if (i + 2 < len)
1319                         tmp |= (u32) (ssid[i + 2]) << 16;
1320                 if (i + 3 < len)
1321                         tmp |= (u32) (ssid[i + 3]) << 24;
1322                 b43_shm_write32(dev, B43_SHM_SHARED, 0x380 + i, tmp);
1323         }
1324         b43_shm_write16(dev, B43_SHM_SHARED, 0x48, len);
1325 }
1326
1327 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1328 {
1329         b43_time_lock(dev);
1330         if (dev->dev->id.revision >= 3) {
1331                 b43_write32(dev, 0x188, (beacon_int << 16));
1332         } else {
1333                 b43_write16(dev, 0x606, (beacon_int >> 6));
1334                 b43_write16(dev, 0x610, beacon_int);
1335         }
1336         b43_time_unlock(dev);
1337 }
1338
1339 static void handle_irq_beacon(struct b43_wldev *dev)
1340 {
1341         u32 status;
1342
1343         if (!b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
1344                 return;
1345
1346         dev->irq_savedstate &= ~B43_IRQ_BEACON;
1347         status = b43_read32(dev, B43_MMIO_STATUS2_BITFIELD);
1348
1349         if (!dev->cached_beacon || ((status & 0x1) && (status & 0x2))) {
1350                 /* ACK beacon IRQ. */
1351                 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1352                 dev->irq_savedstate |= B43_IRQ_BEACON;
1353                 if (dev->cached_beacon)
1354                         kfree_skb(dev->cached_beacon);
1355                 dev->cached_beacon = NULL;
1356                 return;
1357         }
1358         if (!(status & 0x1)) {
1359                 b43_write_beacon_template(dev, 0x68, 0x18, B43_CCK_RATE_1MB);
1360                 status |= 0x1;
1361                 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, status);
1362         }
1363         if (!(status & 0x2)) {
1364                 b43_write_beacon_template(dev, 0x468, 0x1A, B43_CCK_RATE_1MB);
1365                 status |= 0x2;
1366                 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, status);
1367         }
1368 }
1369
1370 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1371 {
1372         //TODO
1373 }
1374
1375 /* Interrupt handler bottom-half */
1376 static void b43_interrupt_tasklet(struct b43_wldev *dev)
1377 {
1378         u32 reason;
1379         u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1380         u32 merged_dma_reason = 0;
1381         int i;
1382         unsigned long flags;
1383
1384         spin_lock_irqsave(&dev->wl->irq_lock, flags);
1385
1386         B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
1387
1388         reason = dev->irq_reason;
1389         for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1390                 dma_reason[i] = dev->dma_reason[i];
1391                 merged_dma_reason |= dma_reason[i];
1392         }
1393
1394         if (unlikely(reason & B43_IRQ_MAC_TXERR))
1395                 b43err(dev->wl, "MAC transmission error\n");
1396
1397         if (unlikely(reason & B43_IRQ_PHY_TXERR))
1398                 b43err(dev->wl, "PHY transmission error\n");
1399
1400         if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1401                                           B43_DMAIRQ_NONFATALMASK))) {
1402                 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1403                         b43err(dev->wl, "Fatal DMA error: "
1404                                "0x%08X, 0x%08X, 0x%08X, "
1405                                "0x%08X, 0x%08X, 0x%08X\n",
1406                                dma_reason[0], dma_reason[1],
1407                                dma_reason[2], dma_reason[3],
1408                                dma_reason[4], dma_reason[5]);
1409                         b43_controller_restart(dev, "DMA error");
1410                         mmiowb();
1411                         spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1412                         return;
1413                 }
1414                 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1415                         b43err(dev->wl, "DMA error: "
1416                                "0x%08X, 0x%08X, 0x%08X, "
1417                                "0x%08X, 0x%08X, 0x%08X\n",
1418                                dma_reason[0], dma_reason[1],
1419                                dma_reason[2], dma_reason[3],
1420                                dma_reason[4], dma_reason[5]);
1421                 }
1422         }
1423
1424         if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1425                 handle_irq_ucode_debug(dev);
1426         if (reason & B43_IRQ_TBTT_INDI)
1427                 handle_irq_tbtt_indication(dev);
1428         if (reason & B43_IRQ_ATIM_END)
1429                 handle_irq_atim_end(dev);
1430         if (reason & B43_IRQ_BEACON)
1431                 handle_irq_beacon(dev);
1432         if (reason & B43_IRQ_PMQ)
1433                 handle_irq_pmq(dev);
1434         if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1435                 ;/* TODO */
1436         if (reason & B43_IRQ_NOISESAMPLE_OK)
1437                 handle_irq_noise(dev);
1438
1439         /* Check the DMA reason registers for received data. */
1440         if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1441                 if (b43_using_pio(dev))
1442                         b43_pio_rx(dev->pio.queue0);
1443                 else
1444                         b43_dma_rx(dev->dma.rx_ring0);
1445         }
1446         B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1447         B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1448         if (dma_reason[3] & B43_DMAIRQ_RX_DONE) {
1449                 if (b43_using_pio(dev))
1450                         b43_pio_rx(dev->pio.queue3);
1451                 else
1452                         b43_dma_rx(dev->dma.rx_ring3);
1453         }
1454         B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1455         B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1456
1457         if (reason & B43_IRQ_TX_OK)
1458                 handle_irq_transmit_status(dev);
1459
1460         b43_interrupt_enable(dev, dev->irq_savedstate);
1461         mmiowb();
1462         spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1463 }
1464
1465 static void pio_irq_workaround(struct b43_wldev *dev, u16 base, int queueidx)
1466 {
1467         u16 rxctl;
1468
1469         rxctl = b43_read16(dev, base + B43_PIO_RXCTL);
1470         if (rxctl & B43_PIO_RXCTL_DATAAVAILABLE)
1471                 dev->dma_reason[queueidx] |= B43_DMAIRQ_RX_DONE;
1472         else
1473                 dev->dma_reason[queueidx] &= ~B43_DMAIRQ_RX_DONE;
1474 }
1475
1476 static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
1477 {
1478         if (b43_using_pio(dev) &&
1479             (dev->dev->id.revision < 3) &&
1480             (!(reason & B43_IRQ_PIO_WORKAROUND))) {
1481                 /* Apply a PIO specific workaround to the dma_reasons */
1482                 pio_irq_workaround(dev, B43_MMIO_PIO1_BASE, 0);
1483                 pio_irq_workaround(dev, B43_MMIO_PIO2_BASE, 1);
1484                 pio_irq_workaround(dev, B43_MMIO_PIO3_BASE, 2);
1485                 pio_irq_workaround(dev, B43_MMIO_PIO4_BASE, 3);
1486         }
1487
1488         b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1489
1490         b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1491         b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1492         b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1493         b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1494         b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1495         b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1496 }
1497
1498 /* Interrupt handler top-half */
1499 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1500 {
1501         irqreturn_t ret = IRQ_NONE;
1502         struct b43_wldev *dev = dev_id;
1503         u32 reason;
1504
1505         if (!dev)
1506                 return IRQ_NONE;
1507
1508         spin_lock(&dev->wl->irq_lock);
1509
1510         if (b43_status(dev) < B43_STAT_STARTED)
1511                 goto out;
1512         reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1513         if (reason == 0xffffffff)       /* shared IRQ */
1514                 goto out;
1515         ret = IRQ_HANDLED;
1516         reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1517         if (!reason)
1518                 goto out;
1519
1520         dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1521             & 0x0001DC00;
1522         dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1523             & 0x0000DC00;
1524         dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1525             & 0x0000DC00;
1526         dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1527             & 0x0001DC00;
1528         dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1529             & 0x0000DC00;
1530         dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1531             & 0x0000DC00;
1532
1533         b43_interrupt_ack(dev, reason);
1534         /* disable all IRQs. They are enabled again in the bottom half. */
1535         dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
1536         /* save the reason code and call our bottom half. */
1537         dev->irq_reason = reason;
1538         tasklet_schedule(&dev->isr_tasklet);
1539       out:
1540         mmiowb();
1541         spin_unlock(&dev->wl->irq_lock);
1542
1543         return ret;
1544 }
1545
1546 static void b43_release_firmware(struct b43_wldev *dev)
1547 {
1548         release_firmware(dev->fw.ucode);
1549         dev->fw.ucode = NULL;
1550         release_firmware(dev->fw.pcm);
1551         dev->fw.pcm = NULL;
1552         release_firmware(dev->fw.initvals);
1553         dev->fw.initvals = NULL;
1554         release_firmware(dev->fw.initvals_band);
1555         dev->fw.initvals_band = NULL;
1556 }
1557
1558 static void b43_print_fw_helptext(struct b43_wl *wl)
1559 {
1560         b43err(wl, "You must go to "
1561                "http://linuxwireless.org/en/users/Drivers/b43#devicefirmware "
1562                "and download the correct firmware (version 4).\n");
1563 }
1564
1565 static int do_request_fw(struct b43_wldev *dev,
1566                          const char *name,
1567                          const struct firmware **fw)
1568 {
1569         char path[sizeof(modparam_fwpostfix) + 32];
1570         struct b43_fw_header *hdr;
1571         u32 size;
1572         int err;
1573
1574         if (!name)
1575                 return 0;
1576
1577         snprintf(path, ARRAY_SIZE(path),
1578                  "b43%s/%s.fw",
1579                  modparam_fwpostfix, name);
1580         err = request_firmware(fw, path, dev->dev->dev);
1581         if (err) {
1582                 b43err(dev->wl, "Firmware file \"%s\" not found "
1583                        "or load failed.\n", path);
1584                 return err;
1585         }
1586         if ((*fw)->size < sizeof(struct b43_fw_header))
1587                 goto err_format;
1588         hdr = (struct b43_fw_header *)((*fw)->data);
1589         switch (hdr->type) {
1590         case B43_FW_TYPE_UCODE:
1591         case B43_FW_TYPE_PCM:
1592                 size = be32_to_cpu(hdr->size);
1593                 if (size != (*fw)->size - sizeof(struct b43_fw_header))
1594                         goto err_format;
1595                 /* fallthrough */
1596         case B43_FW_TYPE_IV:
1597                 if (hdr->ver != 1)
1598                         goto err_format;
1599                 break;
1600         default:
1601                 goto err_format;
1602         }
1603
1604         return err;
1605
1606 err_format:
1607         b43err(dev->wl, "Firmware file \"%s\" format error.\n", path);
1608         return -EPROTO;
1609 }
1610
1611 static int b43_request_firmware(struct b43_wldev *dev)
1612 {
1613         struct b43_firmware *fw = &dev->fw;
1614         const u8 rev = dev->dev->id.revision;
1615         const char *filename;
1616         u32 tmshigh;
1617         int err;
1618
1619         tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
1620         if (!fw->ucode) {
1621                 if ((rev >= 5) && (rev <= 10))
1622                         filename = "ucode5";
1623                 else if ((rev >= 11) && (rev <= 12))
1624                         filename = "ucode11";
1625                 else if (rev >= 13)
1626                         filename = "ucode13";
1627                 else
1628                         goto err_no_ucode;
1629                 err = do_request_fw(dev, filename, &fw->ucode);
1630                 if (err)
1631                         goto err_load;
1632         }
1633         if (!fw->pcm) {
1634                 if ((rev >= 5) && (rev <= 10))
1635                         filename = "pcm5";
1636                 else if (rev >= 11)
1637                         filename = NULL;
1638                 else
1639                         goto err_no_pcm;
1640                 err = do_request_fw(dev, filename, &fw->pcm);
1641                 if (err)
1642                         goto err_load;
1643         }
1644         if (!fw->initvals) {
1645                 switch (dev->phy.type) {
1646                 case B43_PHYTYPE_A:
1647                         if ((rev >= 5) && (rev <= 10)) {
1648                                 if (tmshigh & B43_TMSHIGH_GPHY)
1649                                         filename = "a0g1initvals5";
1650                                 else
1651                                         filename = "a0g0initvals5";
1652                         } else
1653                                 goto err_no_initvals;
1654                         break;
1655                 case B43_PHYTYPE_G:
1656                         if ((rev >= 5) && (rev <= 10))
1657                                 filename = "b0g0initvals5";
1658                         else if (rev >= 13)
1659                                 filename = "lp0initvals13";
1660                         else
1661                                 goto err_no_initvals;
1662                         break;
1663                 default:
1664                         goto err_no_initvals;
1665                 }
1666                 err = do_request_fw(dev, filename, &fw->initvals);
1667                 if (err)
1668                         goto err_load;
1669         }
1670         if (!fw->initvals_band) {
1671                 switch (dev->phy.type) {
1672                 case B43_PHYTYPE_A:
1673                         if ((rev >= 5) && (rev <= 10)) {
1674                                 if (tmshigh & B43_TMSHIGH_GPHY)
1675                                         filename = "a0g1bsinitvals5";
1676                                 else
1677                                         filename = "a0g0bsinitvals5";
1678                         } else if (rev >= 11)
1679                                 filename = NULL;
1680                         else
1681                                 goto err_no_initvals;
1682                         break;
1683                 case B43_PHYTYPE_G:
1684                         if ((rev >= 5) && (rev <= 10))
1685                                 filename = "b0g0bsinitvals5";
1686                         else if (rev >= 11)
1687                                 filename = NULL;
1688                         else
1689                                 goto err_no_initvals;
1690                         break;
1691                 default:
1692                         goto err_no_initvals;
1693                 }
1694                 err = do_request_fw(dev, filename, &fw->initvals_band);
1695                 if (err)
1696                         goto err_load;
1697         }
1698
1699         return 0;
1700
1701 err_load:
1702         b43_print_fw_helptext(dev->wl);
1703         goto error;
1704
1705 err_no_ucode:
1706         err = -ENODEV;
1707         b43err(dev->wl, "No microcode available for core rev %u\n", rev);
1708         goto error;
1709
1710 err_no_pcm:
1711         err = -ENODEV;
1712         b43err(dev->wl, "No PCM available for core rev %u\n", rev);
1713         goto error;
1714
1715 err_no_initvals:
1716         err = -ENODEV;
1717         b43err(dev->wl, "No Initial Values firmware file for PHY %u, "
1718                "core rev %u\n", dev->phy.type, rev);
1719         goto error;
1720
1721 error:
1722         b43_release_firmware(dev);
1723         return err;
1724 }
1725
1726 static int b43_upload_microcode(struct b43_wldev *dev)
1727 {
1728         const size_t hdr_len = sizeof(struct b43_fw_header);
1729         const __be32 *data;
1730         unsigned int i, len;
1731         u16 fwrev, fwpatch, fwdate, fwtime;
1732         u32 tmp;
1733         int err = 0;
1734
1735         /* Upload Microcode. */
1736         data = (__be32 *) (dev->fw.ucode->data + hdr_len);
1737         len = (dev->fw.ucode->size - hdr_len) / sizeof(__be32);
1738         b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
1739         for (i = 0; i < len; i++) {
1740                 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1741                 udelay(10);
1742         }
1743
1744         if (dev->fw.pcm) {
1745                 /* Upload PCM data. */
1746                 data = (__be32 *) (dev->fw.pcm->data + hdr_len);
1747                 len = (dev->fw.pcm->size - hdr_len) / sizeof(__be32);
1748                 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
1749                 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
1750                 /* No need for autoinc bit in SHM_HW */
1751                 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
1752                 for (i = 0; i < len; i++) {
1753                         b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1754                         udelay(10);
1755                 }
1756         }
1757
1758         b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1759         b43_write32(dev, B43_MMIO_MACCTL,
1760                     B43_MACCTL_PSM_RUN |
1761                     B43_MACCTL_IHR_ENABLED | B43_MACCTL_INFRA);
1762
1763         /* Wait for the microcode to load and respond */
1764         i = 0;
1765         while (1) {
1766                 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1767                 if (tmp == B43_IRQ_MAC_SUSPENDED)
1768                         break;
1769                 i++;
1770                 if (i >= 50) {
1771                         b43err(dev->wl, "Microcode not responding\n");
1772                         b43_print_fw_helptext(dev->wl);
1773                         err = -ENODEV;
1774                         goto out;
1775                 }
1776                 udelay(10);
1777         }
1778         b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);       /* dummy read */
1779
1780         /* Get and check the revisions. */
1781         fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
1782         fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
1783         fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
1784         fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
1785
1786         if (fwrev <= 0x128) {
1787                 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
1788                        "binary drivers older than version 4.x is unsupported. "
1789                        "You must upgrade your firmware files.\n");
1790                 b43_print_fw_helptext(dev->wl);
1791                 b43_write32(dev, B43_MMIO_MACCTL, 0);
1792                 err = -EOPNOTSUPP;
1793                 goto out;
1794         }
1795         b43dbg(dev->wl, "Loading firmware version %u.%u "
1796                "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
1797                fwrev, fwpatch,
1798                (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
1799                (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
1800
1801         dev->fw.rev = fwrev;
1802         dev->fw.patch = fwpatch;
1803
1804       out:
1805         return err;
1806 }
1807
1808 static int b43_write_initvals(struct b43_wldev *dev,
1809                               const struct b43_iv *ivals,
1810                               size_t count,
1811                               size_t array_size)
1812 {
1813         const struct b43_iv *iv;
1814         u16 offset;
1815         size_t i;
1816         bool bit32;
1817
1818         BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
1819         iv = ivals;
1820         for (i = 0; i < count; i++) {
1821                 if (array_size < sizeof(iv->offset_size))
1822                         goto err_format;
1823                 array_size -= sizeof(iv->offset_size);
1824                 offset = be16_to_cpu(iv->offset_size);
1825                 bit32 = !!(offset & B43_IV_32BIT);
1826                 offset &= B43_IV_OFFSET_MASK;
1827                 if (offset >= 0x1000)
1828                         goto err_format;
1829                 if (bit32) {
1830                         u32 value;
1831
1832                         if (array_size < sizeof(iv->data.d32))
1833                                 goto err_format;
1834                         array_size -= sizeof(iv->data.d32);
1835
1836                         value = be32_to_cpu(get_unaligned(&iv->data.d32));
1837                         b43_write32(dev, offset, value);
1838
1839                         iv = (const struct b43_iv *)((const uint8_t *)iv +
1840                                                         sizeof(__be16) +
1841                                                         sizeof(__be32));
1842                 } else {
1843                         u16 value;
1844
1845                         if (array_size < sizeof(iv->data.d16))
1846                                 goto err_format;
1847                         array_size -= sizeof(iv->data.d16);
1848
1849                         value = be16_to_cpu(iv->data.d16);
1850                         b43_write16(dev, offset, value);
1851
1852                         iv = (const struct b43_iv *)((const uint8_t *)iv +
1853                                                         sizeof(__be16) +
1854                                                         sizeof(__be16));
1855                 }
1856         }
1857         if (array_size)
1858                 goto err_format;
1859
1860         return 0;
1861
1862 err_format:
1863         b43err(dev->wl, "Initial Values Firmware file-format error.\n");
1864         b43_print_fw_helptext(dev->wl);
1865
1866         return -EPROTO;
1867 }
1868
1869 static int b43_upload_initvals(struct b43_wldev *dev)
1870 {
1871         const size_t hdr_len = sizeof(struct b43_fw_header);
1872         const struct b43_fw_header *hdr;
1873         struct b43_firmware *fw = &dev->fw;
1874         const struct b43_iv *ivals;
1875         size_t count;
1876         int err;
1877
1878         hdr = (const struct b43_fw_header *)(fw->initvals->data);
1879         ivals = (const struct b43_iv *)(fw->initvals->data + hdr_len);
1880         count = be32_to_cpu(hdr->size);
1881         err = b43_write_initvals(dev, ivals, count,
1882                                  fw->initvals->size - hdr_len);
1883         if (err)
1884                 goto out;
1885         if (fw->initvals_band) {
1886                 hdr = (const struct b43_fw_header *)(fw->initvals_band->data);
1887                 ivals = (const struct b43_iv *)(fw->initvals_band->data + hdr_len);
1888                 count = be32_to_cpu(hdr->size);
1889                 err = b43_write_initvals(dev, ivals, count,
1890                                          fw->initvals_band->size - hdr_len);
1891                 if (err)
1892                         goto out;
1893         }
1894 out:
1895
1896         return err;
1897 }
1898
1899 /* Initialize the GPIOs
1900  * http://bcm-specs.sipsolutions.net/GPIO
1901  */
1902 static int b43_gpio_init(struct b43_wldev *dev)
1903 {
1904         struct ssb_bus *bus = dev->dev->bus;
1905         struct ssb_device *gpiodev, *pcidev = NULL;
1906         u32 mask, set;
1907
1908         b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
1909                     & ~B43_MACCTL_GPOUTSMSK);
1910
1911         b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
1912                     | 0x000F);
1913
1914         mask = 0x0000001F;
1915         set = 0x0000000F;
1916         if (dev->dev->bus->chip_id == 0x4301) {
1917                 mask |= 0x0060;
1918                 set |= 0x0060;
1919         }
1920         if (0 /* FIXME: conditional unknown */ ) {
1921                 b43_write16(dev, B43_MMIO_GPIO_MASK,
1922                             b43_read16(dev, B43_MMIO_GPIO_MASK)
1923                             | 0x0100);
1924                 mask |= 0x0180;
1925                 set |= 0x0180;
1926         }
1927         if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
1928                 b43_write16(dev, B43_MMIO_GPIO_MASK,
1929                             b43_read16(dev, B43_MMIO_GPIO_MASK)
1930                             | 0x0200);
1931                 mask |= 0x0200;
1932                 set |= 0x0200;
1933         }
1934         if (dev->dev->id.revision >= 2)
1935                 mask |= 0x0010; /* FIXME: This is redundant. */
1936
1937 #ifdef CONFIG_SSB_DRIVER_PCICORE
1938         pcidev = bus->pcicore.dev;
1939 #endif
1940         gpiodev = bus->chipco.dev ? : pcidev;
1941         if (!gpiodev)
1942                 return 0;
1943         ssb_write32(gpiodev, B43_GPIO_CONTROL,
1944                     (ssb_read32(gpiodev, B43_GPIO_CONTROL)
1945                      & mask) | set);
1946
1947         return 0;
1948 }
1949
1950 /* Turn off all GPIO stuff. Call this on module unload, for example. */
1951 static void b43_gpio_cleanup(struct b43_wldev *dev)
1952 {
1953         struct ssb_bus *bus = dev->dev->bus;
1954         struct ssb_device *gpiodev, *pcidev = NULL;
1955
1956 #ifdef CONFIG_SSB_DRIVER_PCICORE
1957         pcidev = bus->pcicore.dev;
1958 #endif
1959         gpiodev = bus->chipco.dev ? : pcidev;
1960         if (!gpiodev)
1961                 return;
1962         ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
1963 }
1964
1965 /* http://bcm-specs.sipsolutions.net/EnableMac */
1966 void b43_mac_enable(struct b43_wldev *dev)
1967 {
1968         dev->mac_suspended--;
1969         B43_WARN_ON(dev->mac_suspended < 0);
1970         B43_WARN_ON(irqs_disabled());
1971         if (dev->mac_suspended == 0) {
1972                 b43_write32(dev, B43_MMIO_MACCTL,
1973                             b43_read32(dev, B43_MMIO_MACCTL)
1974                             | B43_MACCTL_ENABLED);
1975                 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
1976                             B43_IRQ_MAC_SUSPENDED);
1977                 /* Commit writes */
1978                 b43_read32(dev, B43_MMIO_MACCTL);
1979                 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1980                 b43_power_saving_ctl_bits(dev, 0);
1981
1982                 /* Re-enable IRQs. */
1983                 spin_lock_irq(&dev->wl->irq_lock);
1984                 b43_interrupt_enable(dev, dev->irq_savedstate);
1985                 spin_unlock_irq(&dev->wl->irq_lock);
1986         }
1987 }
1988
1989 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
1990 void b43_mac_suspend(struct b43_wldev *dev)
1991 {
1992         int i;
1993         u32 tmp;
1994
1995         might_sleep();
1996         B43_WARN_ON(irqs_disabled());
1997         B43_WARN_ON(dev->mac_suspended < 0);
1998
1999         if (dev->mac_suspended == 0) {
2000                 /* Mask IRQs before suspending MAC. Otherwise
2001                  * the MAC stays busy and won't suspend. */
2002                 spin_lock_irq(&dev->wl->irq_lock);
2003                 tmp = b43_interrupt_disable(dev, B43_IRQ_ALL);
2004                 spin_unlock_irq(&dev->wl->irq_lock);
2005                 b43_synchronize_irq(dev);
2006                 dev->irq_savedstate = tmp;
2007
2008                 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2009                 b43_write32(dev, B43_MMIO_MACCTL,
2010                             b43_read32(dev, B43_MMIO_MACCTL)
2011                             & ~B43_MACCTL_ENABLED);
2012                 /* force pci to flush the write */
2013                 b43_read32(dev, B43_MMIO_MACCTL);
2014                 for (i = 40; i; i--) {
2015                         tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2016                         if (tmp & B43_IRQ_MAC_SUSPENDED)
2017                                 goto out;
2018                         msleep(1);
2019                 }
2020                 b43err(dev->wl, "MAC suspend failed\n");
2021         }
2022 out:
2023         dev->mac_suspended++;
2024 }
2025
2026 static void b43_adjust_opmode(struct b43_wldev *dev)
2027 {
2028         struct b43_wl *wl = dev->wl;
2029         u32 ctl;
2030         u16 cfp_pretbtt;
2031
2032         ctl = b43_read32(dev, B43_MMIO_MACCTL);
2033         /* Reset status to STA infrastructure mode. */
2034         ctl &= ~B43_MACCTL_AP;
2035         ctl &= ~B43_MACCTL_KEEP_CTL;
2036         ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2037         ctl &= ~B43_MACCTL_KEEP_BAD;
2038         ctl &= ~B43_MACCTL_PROMISC;
2039         ctl &= ~B43_MACCTL_BEACPROMISC;
2040         ctl |= B43_MACCTL_INFRA;
2041
2042         if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2043                 ctl |= B43_MACCTL_AP;
2044         else if (b43_is_mode(wl, IEEE80211_IF_TYPE_IBSS))
2045                 ctl &= ~B43_MACCTL_INFRA;
2046
2047         if (wl->filter_flags & FIF_CONTROL)
2048                 ctl |= B43_MACCTL_KEEP_CTL;
2049         if (wl->filter_flags & FIF_FCSFAIL)
2050                 ctl |= B43_MACCTL_KEEP_BAD;
2051         if (wl->filter_flags & FIF_PLCPFAIL)
2052                 ctl |= B43_MACCTL_KEEP_BADPLCP;
2053         if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2054                 ctl |= B43_MACCTL_PROMISC;
2055         if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2056                 ctl |= B43_MACCTL_BEACPROMISC;
2057
2058         /* Workaround: On old hardware the HW-MAC-address-filter
2059          * doesn't work properly, so always run promisc in filter
2060          * it in software. */
2061         if (dev->dev->id.revision <= 4)
2062                 ctl |= B43_MACCTL_PROMISC;
2063
2064         b43_write32(dev, B43_MMIO_MACCTL, ctl);
2065
2066         cfp_pretbtt = 2;
2067         if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2068                 if (dev->dev->bus->chip_id == 0x4306 &&
2069                     dev->dev->bus->chip_rev == 3)
2070                         cfp_pretbtt = 100;
2071                 else
2072                         cfp_pretbtt = 50;
2073         }
2074         b43_write16(dev, 0x612, cfp_pretbtt);
2075 }
2076
2077 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2078 {
2079         u16 offset;
2080
2081         if (is_ofdm) {
2082                 offset = 0x480;
2083                 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2084         } else {
2085                 offset = 0x4C0;
2086                 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2087         }
2088         b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2089                         b43_shm_read16(dev, B43_SHM_SHARED, offset));
2090 }
2091
2092 static void b43_rate_memory_init(struct b43_wldev *dev)
2093 {
2094         switch (dev->phy.type) {
2095         case B43_PHYTYPE_A:
2096         case B43_PHYTYPE_G:
2097                 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2098                 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2099                 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2100                 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2101                 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2102                 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2103                 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2104                 if (dev->phy.type == B43_PHYTYPE_A)
2105                         break;
2106                 /* fallthrough */
2107         case B43_PHYTYPE_B:
2108                 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2109                 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2110                 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2111                 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2112                 break;
2113         default:
2114                 B43_WARN_ON(1);
2115         }
2116 }
2117
2118 /* Set the TX-Antenna for management frames sent by firmware. */
2119 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2120 {
2121         u16 ant = 0;
2122         u16 tmp;
2123
2124         switch (antenna) {
2125         case B43_ANTENNA0:
2126                 ant |= B43_TX4_PHY_ANT0;
2127                 break;
2128         case B43_ANTENNA1:
2129                 ant |= B43_TX4_PHY_ANT1;
2130                 break;
2131         case B43_ANTENNA_AUTO:
2132                 ant |= B43_TX4_PHY_ANTLAST;
2133                 break;
2134         default:
2135                 B43_WARN_ON(1);
2136         }
2137
2138         /* FIXME We also need to set the other flags of the PHY control field somewhere. */
2139
2140         /* For Beacons */
2141         tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
2142         tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2143         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, tmp);
2144         /* For ACK/CTS */
2145         tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
2146         tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2147         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2148         /* For Probe Resposes */
2149         tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
2150         tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2151         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2152 }
2153
2154 /* This is the opposite of b43_chip_init() */
2155 static void b43_chip_exit(struct b43_wldev *dev)
2156 {
2157         b43_radio_turn_off(dev, 1);
2158         b43_gpio_cleanup(dev);
2159         /* firmware is released later */
2160 }
2161
2162 /* Initialize the chip
2163  * http://bcm-specs.sipsolutions.net/ChipInit
2164  */
2165 static int b43_chip_init(struct b43_wldev *dev)
2166 {
2167         struct b43_phy *phy = &dev->phy;
2168         int err, tmp;
2169         u32 value32;
2170         u16 value16;
2171
2172         b43_write32(dev, B43_MMIO_MACCTL,
2173                     B43_MACCTL_PSM_JMP0 | B43_MACCTL_IHR_ENABLED);
2174
2175         err = b43_request_firmware(dev);
2176         if (err)
2177                 goto out;
2178         err = b43_upload_microcode(dev);
2179         if (err)
2180                 goto out;       /* firmware is released later */
2181
2182         err = b43_gpio_init(dev);
2183         if (err)
2184                 goto out;       /* firmware is released later */
2185
2186         err = b43_upload_initvals(dev);
2187         if (err)
2188                 goto err_gpio_clean;
2189         b43_radio_turn_on(dev);
2190
2191         b43_write16(dev, 0x03E6, 0x0000);
2192         err = b43_phy_init(dev);
2193         if (err)
2194                 goto err_radio_off;
2195
2196         /* Select initial Interference Mitigation. */
2197         tmp = phy->interfmode;
2198         phy->interfmode = B43_INTERFMODE_NONE;
2199         b43_radio_set_interference_mitigation(dev, tmp);
2200
2201         b43_set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2202         b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2203
2204         if (phy->type == B43_PHYTYPE_B) {
2205                 value16 = b43_read16(dev, 0x005E);
2206                 value16 |= 0x0004;
2207                 b43_write16(dev, 0x005E, value16);
2208         }
2209         b43_write32(dev, 0x0100, 0x01000000);
2210         if (dev->dev->id.revision < 5)
2211                 b43_write32(dev, 0x010C, 0x01000000);
2212
2213         b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2214                     & ~B43_MACCTL_INFRA);
2215         b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2216                     | B43_MACCTL_INFRA);
2217
2218         if (b43_using_pio(dev)) {
2219                 b43_write32(dev, 0x0210, 0x00000100);
2220                 b43_write32(dev, 0x0230, 0x00000100);
2221                 b43_write32(dev, 0x0250, 0x00000100);
2222                 b43_write32(dev, 0x0270, 0x00000100);
2223                 b43_shm_write16(dev, B43_SHM_SHARED, 0x0034, 0x0000);
2224         }
2225
2226         /* Probe Response Timeout value */
2227         /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2228         b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2229
2230         /* Initially set the wireless operation mode. */
2231         b43_adjust_opmode(dev);
2232
2233         if (dev->dev->id.revision < 3) {
2234                 b43_write16(dev, 0x060E, 0x0000);
2235                 b43_write16(dev, 0x0610, 0x8000);
2236                 b43_write16(dev, 0x0604, 0x0000);
2237                 b43_write16(dev, 0x0606, 0x0200);
2238         } else {
2239                 b43_write32(dev, 0x0188, 0x80000000);
2240                 b43_write32(dev, 0x018C, 0x02000000);
2241         }
2242         b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2243         b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2244         b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2245         b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2246         b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2247         b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2248         b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2249
2250         value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2251         value32 |= 0x00100000;
2252         ssb_write32(dev->dev, SSB_TMSLOW, value32);
2253
2254         b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2255                     dev->dev->bus->chipco.fast_pwrup_delay);
2256
2257         /* OFDM address caching. */
2258         phy->ofdm_valid = 0;
2259
2260         err = 0;
2261         b43dbg(dev->wl, "Chip initialized\n");
2262 out:
2263         return err;
2264
2265 err_radio_off:
2266         b43_radio_turn_off(dev, 1);
2267 err_gpio_clean:
2268         b43_gpio_cleanup(dev);
2269         return err;
2270 }
2271
2272 static void b43_periodic_every120sec(struct b43_wldev *dev)
2273 {
2274         struct b43_phy *phy = &dev->phy;
2275
2276         if (phy->type != B43_PHYTYPE_G || phy->rev < 2)
2277                 return;
2278
2279         b43_mac_suspend(dev);
2280         b43_lo_g_measure(dev);
2281         b43_mac_enable(dev);
2282         if (b43_has_hardware_pctl(phy))
2283                 b43_lo_g_ctl_mark_all_unused(dev);
2284 }
2285
2286 static void b43_periodic_every60sec(struct b43_wldev *dev)
2287 {
2288         struct b43_phy *phy = &dev->phy;
2289
2290         if (!b43_has_hardware_pctl(phy))
2291                 b43_lo_g_ctl_mark_all_unused(dev);
2292         if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI) {
2293                 b43_mac_suspend(dev);
2294                 b43_calc_nrssi_slope(dev);
2295                 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) {
2296                         u8 old_chan = phy->channel;
2297
2298                         /* VCO Calibration */
2299                         if (old_chan >= 8)
2300                                 b43_radio_selectchannel(dev, 1, 0);
2301                         else
2302                                 b43_radio_selectchannel(dev, 13, 0);
2303                         b43_radio_selectchannel(dev, old_chan, 0);
2304                 }
2305                 b43_mac_enable(dev);
2306         }
2307 }
2308
2309 static void b43_periodic_every30sec(struct b43_wldev *dev)
2310 {
2311         /* Update device statistics. */
2312         b43_calculate_link_quality(dev);
2313 }
2314
2315 static void b43_periodic_every15sec(struct b43_wldev *dev)
2316 {
2317         struct b43_phy *phy = &dev->phy;
2318
2319         if (phy->type == B43_PHYTYPE_G) {
2320                 //TODO: update_aci_moving_average
2321                 if (phy->aci_enable && phy->aci_wlan_automatic) {
2322                         b43_mac_suspend(dev);
2323                         if (!phy->aci_enable && 1 /*TODO: not scanning? */ ) {
2324                                 if (0 /*TODO: bunch of conditions */ ) {
2325                                         b43_radio_set_interference_mitigation
2326                                             (dev, B43_INTERFMODE_MANUALWLAN);
2327                                 }
2328                         } else if (1 /*TODO*/) {
2329                                 /*
2330                                    if ((aci_average > 1000) && !(b43_radio_aci_scan(dev))) {
2331                                    b43_radio_set_interference_mitigation(dev,
2332                                    B43_INTERFMODE_NONE);
2333                                    }
2334                                  */
2335                         }
2336                         b43_mac_enable(dev);
2337                 } else if (phy->interfmode == B43_INTERFMODE_NONWLAN &&
2338                            phy->rev == 1) {
2339                         //TODO: implement rev1 workaround
2340                 }
2341         }
2342         b43_phy_xmitpower(dev); //FIXME: unless scanning?
2343         //TODO for APHY (temperature?)
2344 }
2345
2346 static void do_periodic_work(struct b43_wldev *dev)
2347 {
2348         unsigned int state;
2349
2350         state = dev->periodic_state;
2351         if (state % 8 == 0)
2352                 b43_periodic_every120sec(dev);
2353         if (state % 4 == 0)
2354                 b43_periodic_every60sec(dev);
2355         if (state % 2 == 0)
2356                 b43_periodic_every30sec(dev);
2357         b43_periodic_every15sec(dev);
2358 }
2359
2360 /* Periodic work locking policy:
2361  *      The whole periodic work handler is protected by
2362  *      wl->mutex. If another lock is needed somewhere in the
2363  *      pwork callchain, it's aquired in-place, where it's needed.
2364  */
2365 static void b43_periodic_work_handler(struct work_struct *work)
2366 {
2367         struct b43_wldev *dev = container_of(work, struct b43_wldev,
2368                                              periodic_work.work);
2369         struct b43_wl *wl = dev->wl;
2370         unsigned long delay;
2371
2372         mutex_lock(&wl->mutex);
2373
2374         if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2375                 goto out;
2376         if (b43_debug(dev, B43_DBG_PWORK_STOP))
2377                 goto out_requeue;
2378
2379         do_periodic_work(dev);
2380
2381         dev->periodic_state++;
2382 out_requeue:
2383         if (b43_debug(dev, B43_DBG_PWORK_FAST))
2384                 delay = msecs_to_jiffies(50);
2385         else
2386                 delay = round_jiffies_relative(HZ * 15);
2387         queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
2388 out:
2389         mutex_unlock(&wl->mutex);
2390 }
2391
2392 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2393 {
2394         struct delayed_work *work = &dev->periodic_work;
2395
2396         dev->periodic_state = 0;
2397         INIT_DELAYED_WORK(work, b43_periodic_work_handler);
2398         queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2399 }
2400
2401 /* Validate access to the chip (SHM) */
2402 static int b43_validate_chipaccess(struct b43_wldev *dev)
2403 {
2404         u32 value;
2405         u32 shm_backup;
2406
2407         shm_backup = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2408         b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2409         if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
2410                 goto error;
2411         b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2412         if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2413                 goto error;
2414         b43_shm_write32(dev, B43_SHM_SHARED, 0, shm_backup);
2415
2416         value = b43_read32(dev, B43_MMIO_MACCTL);
2417         if ((value | B43_MACCTL_GMODE) !=
2418             (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
2419                 goto error;
2420
2421         value = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2422         if (value)
2423                 goto error;
2424
2425         return 0;
2426       error:
2427         b43err(dev->wl, "Failed to validate the chipaccess\n");
2428         return -ENODEV;
2429 }
2430
2431 static void b43_security_init(struct b43_wldev *dev)
2432 {
2433         dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2434         B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2435         dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
2436         /* KTP is a word address, but we address SHM bytewise.
2437          * So multiply by two.
2438          */
2439         dev->ktp *= 2;
2440         if (dev->dev->id.revision >= 5) {
2441                 /* Number of RCMTA address slots */
2442                 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8);
2443         }
2444         b43_clear_keys(dev);
2445 }
2446
2447 static int b43_rng_read(struct hwrng *rng, u32 * data)
2448 {
2449         struct b43_wl *wl = (struct b43_wl *)rng->priv;
2450         unsigned long flags;
2451
2452         /* Don't take wl->mutex here, as it could deadlock with
2453          * hwrng internal locking. It's not needed to take
2454          * wl->mutex here, anyway. */
2455
2456         spin_lock_irqsave(&wl->irq_lock, flags);
2457         *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
2458         spin_unlock_irqrestore(&wl->irq_lock, flags);
2459
2460         return (sizeof(u16));
2461 }
2462
2463 static void b43_rng_exit(struct b43_wl *wl)
2464 {
2465         if (wl->rng_initialized)
2466                 hwrng_unregister(&wl->rng);
2467 }
2468
2469 static int b43_rng_init(struct b43_wl *wl)
2470 {
2471         int err;
2472
2473         snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2474                  "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2475         wl->rng.name = wl->rng_name;
2476         wl->rng.data_read = b43_rng_read;
2477         wl->rng.priv = (unsigned long)wl;
2478         wl->rng_initialized = 1;
2479         err = hwrng_register(&wl->rng);
2480         if (err) {
2481                 wl->rng_initialized = 0;
2482                 b43err(wl, "Failed to register the random "
2483                        "number generator (%d)\n", err);
2484         }
2485
2486         return err;
2487 }
2488
2489 static int b43_op_tx(struct ieee80211_hw *hw,
2490                      struct sk_buff *skb,
2491                      struct ieee80211_tx_control *ctl)
2492 {
2493         struct b43_wl *wl = hw_to_b43_wl(hw);
2494         struct b43_wldev *dev = wl->current_dev;
2495         int err = -ENODEV;
2496         unsigned long flags;
2497
2498         if (unlikely(!dev))
2499                 goto out;
2500         if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2501                 goto out;
2502         /* DMA-TX is done without a global lock. */
2503         if (b43_using_pio(dev)) {
2504                 spin_lock_irqsave(&wl->irq_lock, flags);
2505                 err = b43_pio_tx(dev, skb, ctl);
2506                 spin_unlock_irqrestore(&wl->irq_lock, flags);
2507         } else
2508                 err = b43_dma_tx(dev, skb, ctl);
2509 out:
2510         if (unlikely(err))
2511                 return NETDEV_TX_BUSY;
2512         return NETDEV_TX_OK;
2513 }
2514
2515 static int b43_op_conf_tx(struct ieee80211_hw *hw,
2516                           int queue,
2517                           const struct ieee80211_tx_queue_params *params)
2518 {
2519         return 0;
2520 }
2521
2522 static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
2523                                struct ieee80211_tx_queue_stats *stats)
2524 {
2525         struct b43_wl *wl = hw_to_b43_wl(hw);
2526         struct b43_wldev *dev = wl->current_dev;
2527         unsigned long flags;
2528         int err = -ENODEV;
2529
2530         if (!dev)
2531                 goto out;
2532         spin_lock_irqsave(&wl->irq_lock, flags);
2533         if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
2534                 if (b43_using_pio(dev))
2535                         b43_pio_get_tx_stats(dev, stats);
2536                 else
2537                         b43_dma_get_tx_stats(dev, stats);
2538                 err = 0;
2539         }
2540         spin_unlock_irqrestore(&wl->irq_lock, flags);
2541 out:
2542         return err;
2543 }
2544
2545 static int b43_op_get_stats(struct ieee80211_hw *hw,
2546                             struct ieee80211_low_level_stats *stats)
2547 {
2548         struct b43_wl *wl = hw_to_b43_wl(hw);
2549         unsigned long flags;
2550
2551         spin_lock_irqsave(&wl->irq_lock, flags);
2552         memcpy(stats, &wl->ieee_stats, sizeof(*stats));
2553         spin_unlock_irqrestore(&wl->irq_lock, flags);
2554
2555         return 0;
2556 }
2557
2558 static const char *phymode_to_string(unsigned int phymode)
2559 {
2560         switch (phymode) {
2561         case B43_PHYMODE_A:
2562                 return "A";
2563         case B43_PHYMODE_B:
2564                 return "B";
2565         case B43_PHYMODE_G:
2566                 return "G";
2567         default:
2568                 B43_WARN_ON(1);
2569         }
2570         return "";
2571 }
2572
2573 static int find_wldev_for_phymode(struct b43_wl *wl,
2574                                   unsigned int phymode,
2575                                   struct b43_wldev **dev, bool * gmode)
2576 {
2577         struct b43_wldev *d;
2578
2579         list_for_each_entry(d, &wl->devlist, list) {
2580                 if (d->phy.possible_phymodes & phymode) {
2581                         /* Ok, this device supports the PHY-mode.
2582                          * Now figure out how the gmode bit has to be
2583                          * set to support it. */
2584                         if (phymode == B43_PHYMODE_A)
2585                                 *gmode = 0;
2586                         else
2587                                 *gmode = 1;
2588                         *dev = d;
2589
2590                         return 0;
2591                 }
2592         }
2593
2594         return -ESRCH;
2595 }
2596
2597 static void b43_put_phy_into_reset(struct b43_wldev *dev)
2598 {
2599         struct ssb_device *sdev = dev->dev;
2600         u32 tmslow;
2601
2602         tmslow = ssb_read32(sdev, SSB_TMSLOW);
2603         tmslow &= ~B43_TMSLOW_GMODE;
2604         tmslow |= B43_TMSLOW_PHYRESET;
2605         tmslow |= SSB_TMSLOW_FGC;
2606         ssb_write32(sdev, SSB_TMSLOW, tmslow);
2607         msleep(1);
2608
2609         tmslow = ssb_read32(sdev, SSB_TMSLOW);
2610         tmslow &= ~SSB_TMSLOW_FGC;
2611         tmslow |= B43_TMSLOW_PHYRESET;
2612         ssb_write32(sdev, SSB_TMSLOW, tmslow);
2613         msleep(1);
2614 }
2615
2616 /* Expects wl->mutex locked */
2617 static int b43_switch_phymode(struct b43_wl *wl, unsigned int new_mode)
2618 {
2619         struct b43_wldev *up_dev;
2620         struct b43_wldev *down_dev;
2621         int err;
2622         bool gmode = 0;
2623         int prev_status;
2624
2625         err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
2626         if (err) {
2627                 b43err(wl, "Could not find a device for %s-PHY mode\n",
2628                        phymode_to_string(new_mode));
2629                 return err;
2630         }
2631         if ((up_dev == wl->current_dev) &&
2632             (!!wl->current_dev->phy.gmode == !!gmode)) {
2633                 /* This device is already running. */
2634                 return 0;
2635         }
2636         b43dbg(wl, "Reconfiguring PHYmode to %s-PHY\n",
2637                phymode_to_string(new_mode));
2638         down_dev = wl->current_dev;
2639
2640         prev_status = b43_status(down_dev);
2641         /* Shutdown the currently running core. */
2642         if (prev_status >= B43_STAT_STARTED)
2643                 b43_wireless_core_stop(down_dev);
2644         if (prev_status >= B43_STAT_INITIALIZED)
2645                 b43_wireless_core_exit(down_dev);
2646
2647         if (down_dev != up_dev) {
2648                 /* We switch to a different core, so we put PHY into
2649                  * RESET on the old core. */
2650                 b43_put_phy_into_reset(down_dev);
2651         }
2652
2653         /* Now start the new core. */
2654         up_dev->phy.gmode = gmode;
2655         if (prev_status >= B43_STAT_INITIALIZED) {
2656                 err = b43_wireless_core_init(up_dev);
2657                 if (err) {
2658                         b43err(wl, "Fatal: Could not initialize device for "
2659                                "newly selected %s-PHY mode\n",
2660                                phymode_to_string(new_mode));
2661                         goto init_failure;
2662                 }
2663         }
2664         if (prev_status >= B43_STAT_STARTED) {
2665                 err = b43_wireless_core_start(up_dev);
2666                 if (err) {
2667                         b43err(wl, "Fatal: Coult not start device for "
2668                                "newly selected %s-PHY mode\n",
2669                                phymode_to_string(new_mode));
2670                         b43_wireless_core_exit(up_dev);
2671                         goto init_failure;
2672                 }
2673         }
2674         B43_WARN_ON(b43_status(up_dev) != prev_status);
2675
2676         wl->current_dev = up_dev;
2677
2678         return 0;
2679       init_failure:
2680         /* Whoops, failed to init the new core. No core is operating now. */
2681         wl->current_dev = NULL;
2682         return err;
2683 }
2684
2685 static int b43_antenna_from_ieee80211(u8 antenna)
2686 {
2687         switch (antenna) {
2688         case 0:         /* default/diversity */
2689                 return B43_ANTENNA_DEFAULT;
2690         case 1:         /* Antenna 0 */
2691                 return B43_ANTENNA0;
2692         case 2:         /* Antenna 1 */
2693                 return B43_ANTENNA1;
2694         default:
2695                 return B43_ANTENNA_DEFAULT;
2696         }
2697 }
2698
2699 static int b43_op_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
2700 {
2701         struct b43_wl *wl = hw_to_b43_wl(hw);
2702         struct b43_wldev *dev;
2703         struct b43_phy *phy;
2704         unsigned long flags;
2705         unsigned int new_phymode = 0xFFFF;
2706         int antenna_tx;
2707         int antenna_rx;
2708         int err = 0;
2709         u32 savedirqs;
2710
2711         antenna_tx = b43_antenna_from_ieee80211(conf->antenna_sel_tx);
2712         antenna_rx = b43_antenna_from_ieee80211(conf->antenna_sel_rx);
2713
2714         mutex_lock(&wl->mutex);
2715
2716         /* Switch the PHY mode (if necessary). */
2717         switch (conf->phymode) {
2718         case MODE_IEEE80211A:
2719                 new_phymode = B43_PHYMODE_A;
2720                 break;
2721         case MODE_IEEE80211B:
2722                 new_phymode = B43_PHYMODE_B;
2723                 break;
2724         case MODE_IEEE80211G:
2725                 new_phymode = B43_PHYMODE_G;
2726                 break;
2727         default:
2728                 B43_WARN_ON(1);
2729         }
2730         err = b43_switch_phymode(wl, new_phymode);
2731         if (err)
2732                 goto out_unlock_mutex;
2733         dev = wl->current_dev;
2734         phy = &dev->phy;
2735
2736         /* Disable IRQs while reconfiguring the device.
2737          * This makes it possible to drop the spinlock throughout
2738          * the reconfiguration process. */
2739         spin_lock_irqsave(&wl->irq_lock, flags);
2740         if (b43_status(dev) < B43_STAT_STARTED) {
2741                 spin_unlock_irqrestore(&wl->irq_lock, flags);
2742                 goto out_unlock_mutex;
2743         }
2744         savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL);
2745         spin_unlock_irqrestore(&wl->irq_lock, flags);
2746         b43_synchronize_irq(dev);
2747
2748         /* Switch to the requested channel.
2749          * The firmware takes care of races with the TX handler. */
2750         if (conf->channel_val != phy->channel)
2751                 b43_radio_selectchannel(dev, conf->channel_val, 0);
2752
2753         /* Enable/Disable ShortSlot timing. */
2754         if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) !=
2755             dev->short_slot) {
2756                 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
2757                 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
2758                         b43_short_slot_timing_enable(dev);
2759                 else
2760                         b43_short_slot_timing_disable(dev);
2761         }
2762
2763         /* Adjust the desired TX power level. */
2764         if (conf->power_level != 0) {
2765                 if (conf->power_level != phy->power_level) {
2766                         phy->power_level = conf->power_level;
2767                         b43_phy_xmitpower(dev);
2768                 }
2769         }
2770
2771         /* Antennas for RX and management frame TX. */
2772         b43_mgmtframe_txantenna(dev, antenna_tx);
2773         b43_set_rx_antenna(dev, antenna_rx);
2774
2775         /* Update templates for AP mode. */
2776         if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2777                 b43_set_beacon_int(dev, conf->beacon_int);
2778
2779         if (!!conf->radio_enabled != phy->radio_on) {
2780                 if (conf->radio_enabled) {
2781                         b43_radio_turn_on(dev);
2782                         b43info(dev->wl, "Radio turned on by software\n");
2783                         if (!dev->radio_hw_enable) {
2784                                 b43info(dev->wl, "The hardware RF-kill button "
2785                                         "still turns the radio physically off. "
2786                                         "Press the button to turn it on.\n");
2787                         }
2788                 } else {
2789                         b43_radio_turn_off(dev, 0);
2790                         b43info(dev->wl, "Radio turned off by software\n");
2791                 }
2792         }
2793
2794         spin_lock_irqsave(&wl->irq_lock, flags);
2795         b43_interrupt_enable(dev, savedirqs);
2796         mmiowb();
2797         spin_unlock_irqrestore(&wl->irq_lock, flags);
2798       out_unlock_mutex:
2799         mutex_unlock(&wl->mutex);
2800
2801         return err;
2802 }
2803
2804 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2805                            const u8 *local_addr, const u8 *addr,
2806                            struct ieee80211_key_conf *key)
2807 {
2808         struct b43_wl *wl = hw_to_b43_wl(hw);
2809         struct b43_wldev *dev;
2810         unsigned long flags;
2811         u8 algorithm;
2812         u8 index;
2813         int err;
2814         DECLARE_MAC_BUF(mac);
2815
2816         if (modparam_nohwcrypt)
2817                 return -ENOSPC; /* User disabled HW-crypto */
2818
2819         mutex_lock(&wl->mutex);
2820         spin_lock_irqsave(&wl->irq_lock, flags);
2821
2822         dev = wl->current_dev;
2823         err = -ENODEV;
2824         if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
2825                 goto out_unlock;
2826
2827         err = -EINVAL;
2828         switch (key->alg) {
2829         case ALG_WEP:
2830                 if (key->keylen == 5)
2831                         algorithm = B43_SEC_ALGO_WEP40;
2832                 else
2833                         algorithm = B43_SEC_ALGO_WEP104;
2834                 break;
2835         case ALG_TKIP:
2836                 algorithm = B43_SEC_ALGO_TKIP;
2837                 break;
2838         case ALG_CCMP:
2839                 algorithm = B43_SEC_ALGO_AES;
2840                 break;
2841         default:
2842                 B43_WARN_ON(1);
2843                 goto out_unlock;
2844         }
2845         index = (u8) (key->keyidx);
2846         if (index > 3)
2847                 goto out_unlock;
2848
2849         switch (cmd) {
2850         case SET_KEY:
2851                 if (algorithm == B43_SEC_ALGO_TKIP) {
2852                         /* FIXME: No TKIP hardware encryption for now. */
2853                         err = -EOPNOTSUPP;
2854                         goto out_unlock;
2855                 }
2856
2857                 if (is_broadcast_ether_addr(addr)) {
2858                         /* addr is FF:FF:FF:FF:FF:FF for default keys */
2859                         err = b43_key_write(dev, index, algorithm,
2860                                             key->key, key->keylen, NULL, key);
2861                 } else {
2862                         /*
2863                          * either pairwise key or address is 00:00:00:00:00:00
2864                          * for transmit-only keys
2865                          */
2866                         err = b43_key_write(dev, -1, algorithm,
2867                                             key->key, key->keylen, addr, key);
2868                 }
2869                 if (err)
2870                         goto out_unlock;
2871
2872                 if (algorithm == B43_SEC_ALGO_WEP40 ||
2873                     algorithm == B43_SEC_ALGO_WEP104) {
2874                         b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
2875                 } else {
2876                         b43_hf_write(dev,
2877                                      b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
2878                 }
2879                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2880                 break;
2881         case DISABLE_KEY: {
2882                 err = b43_key_clear(dev, key->hw_key_idx);
2883                 if (err)
2884                         goto out_unlock;
2885                 break;
2886         }
2887         default:
2888                 B43_WARN_ON(1);
2889         }
2890 out_unlock:
2891         spin_unlock_irqrestore(&wl->irq_lock, flags);
2892         mutex_unlock(&wl->mutex);
2893         if (!err) {
2894                 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
2895                        "mac: %s\n",
2896                        cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
2897                        print_mac(mac, addr));
2898         }
2899         return err;
2900 }
2901
2902 static void b43_op_configure_filter(struct ieee80211_hw *hw,
2903                                     unsigned int changed, unsigned int *fflags,
2904                                     int mc_count, struct dev_addr_list *mc_list)
2905 {
2906         struct b43_wl *wl = hw_to_b43_wl(hw);
2907         struct b43_wldev *dev = wl->current_dev;
2908         unsigned long flags;
2909
2910         if (!dev) {
2911                 *fflags = 0;
2912                 return;
2913         }
2914
2915         spin_lock_irqsave(&wl->irq_lock, flags);
2916         *fflags &= FIF_PROMISC_IN_BSS |
2917                   FIF_ALLMULTI |
2918                   FIF_FCSFAIL |
2919                   FIF_PLCPFAIL |
2920                   FIF_CONTROL |
2921                   FIF_OTHER_BSS |
2922                   FIF_BCN_PRBRESP_PROMISC;
2923
2924         changed &= FIF_PROMISC_IN_BSS |
2925                    FIF_ALLMULTI |
2926                    FIF_FCSFAIL |
2927                    FIF_PLCPFAIL |
2928                    FIF_CONTROL |
2929                    FIF_OTHER_BSS |
2930                    FIF_BCN_PRBRESP_PROMISC;
2931
2932         wl->filter_flags = *fflags;
2933
2934         if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
2935                 b43_adjust_opmode(dev);
2936         spin_unlock_irqrestore(&wl->irq_lock, flags);
2937 }
2938
2939 static int b43_op_config_interface(struct ieee80211_hw *hw,
2940                                    int if_id,
2941                                    struct ieee80211_if_conf *conf)
2942 {
2943         struct b43_wl *wl = hw_to_b43_wl(hw);
2944         struct b43_wldev *dev = wl->current_dev;
2945         unsigned long flags;
2946
2947         if (!dev)
2948                 return -ENODEV;
2949         mutex_lock(&wl->mutex);
2950         spin_lock_irqsave(&wl->irq_lock, flags);
2951         B43_WARN_ON(wl->if_id != if_id);
2952         if (conf->bssid)
2953                 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
2954         else
2955                 memset(wl->bssid, 0, ETH_ALEN);
2956         if (b43_status(dev) >= B43_STAT_INITIALIZED) {
2957                 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) {
2958                         B43_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP);
2959                         b43_set_ssid(dev, conf->ssid, conf->ssid_len);
2960                         if (conf->beacon)
2961                                 b43_refresh_templates(dev, conf->beacon);
2962                 }
2963                 b43_write_mac_bssid_templates(dev);
2964         }
2965         spin_unlock_irqrestore(&wl->irq_lock, flags);
2966         mutex_unlock(&wl->mutex);
2967
2968         return 0;
2969 }
2970
2971 /* Locking: wl->mutex */
2972 static void b43_wireless_core_stop(struct b43_wldev *dev)
2973 {
2974         struct b43_wl *wl = dev->wl;
2975         unsigned long flags;
2976
2977         if (b43_status(dev) < B43_STAT_STARTED)
2978                 return;
2979
2980         /* Disable and sync interrupts. We must do this before than
2981          * setting the status to INITIALIZED, as the interrupt handler
2982          * won't care about IRQs then. */
2983         spin_lock_irqsave(&wl->irq_lock, flags);
2984         dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
2985         b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
2986         spin_unlock_irqrestore(&wl->irq_lock, flags);
2987         b43_synchronize_irq(dev);
2988
2989         b43_set_status(dev, B43_STAT_INITIALIZED);
2990
2991         mutex_unlock(&wl->mutex);
2992         /* Must unlock as it would otherwise deadlock. No races here.
2993          * Cancel the possibly running self-rearming periodic work. */
2994         cancel_delayed_work_sync(&dev->periodic_work);
2995         mutex_lock(&wl->mutex);
2996
2997         ieee80211_stop_queues(wl->hw);  //FIXME this could cause a deadlock, as mac80211 seems buggy.
2998
2999         b43_mac_suspend(dev);
3000         free_irq(dev->dev->irq, dev);
3001         b43dbg(wl, "Wireless interface stopped\n");
3002 }
3003
3004 /* Locking: wl->mutex */
3005 static int b43_wireless_core_start(struct b43_wldev *dev)
3006 {
3007         int err;
3008
3009         B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3010
3011         drain_txstatus_queue(dev);
3012         err = request_irq(dev->dev->irq, b43_interrupt_handler,
3013                           IRQF_SHARED, KBUILD_MODNAME, dev);
3014         if (err) {
3015                 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3016                 goto out;
3017         }
3018
3019         /* We are ready to run. */
3020         b43_set_status(dev, B43_STAT_STARTED);
3021
3022         /* Start data flow (TX/RX). */
3023         b43_mac_enable(dev);
3024         b43_interrupt_enable(dev, dev->irq_savedstate);
3025         ieee80211_start_queues(dev->wl->hw);
3026
3027         /* Start maintainance work */
3028         b43_periodic_tasks_setup(dev);
3029
3030         b43dbg(dev->wl, "Wireless interface started\n");
3031       out:
3032         return err;
3033 }
3034
3035 /* Get PHY and RADIO versioning numbers */
3036 static int b43_phy_versioning(struct b43_wldev *dev)
3037 {
3038         struct b43_phy *phy = &dev->phy;
3039         u32 tmp;
3040         u8 analog_type;
3041         u8 phy_type;
3042         u8 phy_rev;
3043         u16 radio_manuf;
3044         u16 radio_ver;
3045         u16 radio_rev;
3046         int unsupported = 0;
3047
3048         /* Get PHY versioning */
3049         tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3050         analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3051         phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3052         phy_rev = (tmp & B43_PHYVER_VERSION);
3053         switch (phy_type) {
3054         case B43_PHYTYPE_A:
3055                 if (phy_rev >= 4)
3056                         unsupported = 1;
3057                 break;
3058         case B43_PHYTYPE_B:
3059                 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3060                     && phy_rev != 7)
3061                         unsupported = 1;
3062                 break;
3063         case B43_PHYTYPE_G:
3064                 if (phy_rev > 8)
3065                         unsupported = 1;
3066                 break;
3067         default:
3068                 unsupported = 1;
3069         };
3070         if (unsupported) {
3071                 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3072                        "(Analog %u, Type %u, Revision %u)\n",
3073                        analog_type, phy_type, phy_rev);
3074                 return -EOPNOTSUPP;
3075         }
3076         b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3077                analog_type, phy_type, phy_rev);
3078
3079         /* Get RADIO versioning */
3080         if (dev->dev->bus->chip_id == 0x4317) {
3081                 if (dev->dev->bus->chip_rev == 0)
3082                         tmp = 0x3205017F;
3083                 else if (dev->dev->bus->chip_rev == 1)
3084                         tmp = 0x4205017F;
3085                 else
3086                         tmp = 0x5205017F;
3087         } else {
3088                 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3089                 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH);
3090                 tmp <<= 16;
3091                 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3092                 tmp |= b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3093         }
3094         radio_manuf = (tmp & 0x00000FFF);
3095         radio_ver = (tmp & 0x0FFFF000) >> 12;
3096         radio_rev = (tmp & 0xF0000000) >> 28;
3097         switch (phy_type) {
3098         case B43_PHYTYPE_A:
3099                 if (radio_ver != 0x2060)
3100                         unsupported = 1;
3101                 if (radio_rev != 1)
3102                         unsupported = 1;
3103                 if (radio_manuf != 0x17F)
3104                         unsupported = 1;
3105                 break;
3106         case B43_PHYTYPE_B:
3107                 if ((radio_ver & 0xFFF0) != 0x2050)
3108                         unsupported = 1;
3109                 break;
3110         case B43_PHYTYPE_G:
3111                 if (radio_ver != 0x2050)
3112                         unsupported = 1;
3113                 break;
3114         default:
3115                 B43_WARN_ON(1);
3116         }
3117         if (unsupported) {
3118                 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
3119                        "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3120                        radio_manuf, radio_ver, radio_rev);
3121                 return -EOPNOTSUPP;
3122         }
3123         b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3124                radio_manuf, radio_ver, radio_rev);
3125
3126         phy->radio_manuf = radio_manuf;
3127         phy->radio_ver = radio_ver;
3128         phy->radio_rev = radio_rev;
3129
3130         phy->analog = analog_type;
3131         phy->type = phy_type;
3132         phy->rev = phy_rev;
3133
3134         return 0;
3135 }
3136
3137 static void setup_struct_phy_for_init(struct b43_wldev *dev,
3138                                       struct b43_phy *phy)
3139 {
3140         struct b43_txpower_lo_control *lo;
3141         int i;
3142
3143         memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3144         memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3145
3146         /* Flags */
3147         phy->locked = 0;
3148
3149         phy->aci_enable = 0;
3150         phy->aci_wlan_automatic = 0;
3151         phy->aci_hw_rssi = 0;
3152
3153         phy->radio_off_context.valid = 0;
3154
3155         lo = phy->lo_control;
3156         if (lo) {
3157                 memset(lo, 0, sizeof(*(phy->lo_control)));
3158                 lo->rebuild = 1;
3159                 lo->tx_bias = 0xFF;
3160         }
3161         phy->max_lb_gain = 0;
3162         phy->trsw_rx_gain = 0;
3163         phy->txpwr_offset = 0;
3164
3165         /* NRSSI */
3166         phy->nrssislope = 0;
3167         for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3168                 phy->nrssi[i] = -1000;
3169         for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3170                 phy->nrssi_lt[i] = i;
3171
3172         phy->lofcal = 0xFFFF;
3173         phy->initval = 0xFFFF;
3174
3175         spin_lock_init(&phy->lock);
3176         phy->interfmode = B43_INTERFMODE_NONE;
3177         phy->channel = 0xFF;
3178
3179         phy->hardware_power_control = !!modparam_hwpctl;
3180 }
3181
3182 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
3183 {
3184         /* Flags */
3185         dev->reg124_set_0x4 = 0;
3186         /* Assume the radio is enabled. If it's not enabled, the state will
3187          * immediately get fixed on the first periodic work run. */
3188         dev->radio_hw_enable = 1;
3189
3190         /* Stats */
3191         memset(&dev->stats, 0, sizeof(dev->stats));
3192
3193         setup_struct_phy_for_init(dev, &dev->phy);
3194
3195         /* IRQ related flags */
3196         dev->irq_reason = 0;
3197         memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3198         dev->irq_savedstate = B43_IRQ_MASKTEMPLATE;
3199
3200         dev->mac_suspended = 1;
3201
3202         /* Noise calculation context */
3203         memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3204 }
3205
3206 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
3207 {
3208         struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3209         u32 hf;
3210
3211         if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
3212                 return;
3213         if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
3214                 return;
3215
3216         hf = b43_hf_read(dev);
3217         if (sprom->boardflags_lo & B43_BFL_BTCMOD)
3218                 hf |= B43_HF_BTCOEXALT;
3219         else
3220                 hf |= B43_HF_BTCOEX;
3221         b43_hf_write(dev, hf);
3222         //TODO
3223 }
3224
3225 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
3226 {                               //TODO
3227 }
3228
3229 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
3230 {
3231 #ifdef CONFIG_SSB_DRIVER_PCICORE
3232         struct ssb_bus *bus = dev->dev->bus;
3233         u32 tmp;
3234
3235         if (bus->pcicore.dev &&
3236             bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
3237             bus->pcicore.dev->id.revision <= 5) {
3238                 /* IMCFGLO timeouts workaround. */
3239                 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
3240                 tmp &= ~SSB_IMCFGLO_REQTO;
3241                 tmp &= ~SSB_IMCFGLO_SERTO;
3242                 switch (bus->bustype) {
3243                 case SSB_BUSTYPE_PCI:
3244                 case SSB_BUSTYPE_PCMCIA:
3245                         tmp |= 0x32;
3246                         break;
3247                 case SSB_BUSTYPE_SSB:
3248                         tmp |= 0x53;
3249                         break;
3250                 }
3251                 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
3252         }
3253 #endif /* CONFIG_SSB_DRIVER_PCICORE */
3254 }
3255
3256 /* Write the short and long frame retry limit values. */
3257 static void b43_set_retry_limits(struct b43_wldev *dev,
3258                                  unsigned int short_retry,
3259                                  unsigned int long_retry)
3260 {
3261         /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3262          * the chip-internal counter. */
3263         short_retry = min(short_retry, (unsigned int)0xF);
3264         long_retry = min(long_retry, (unsigned int)0xF);
3265
3266         b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3267                         short_retry);
3268         b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3269                         long_retry);
3270 }
3271
3272 /* Shutdown a wireless core */
3273 /* Locking: wl->mutex */
3274 static void b43_wireless_core_exit(struct b43_wldev *dev)
3275 {
3276         struct b43_phy *phy = &dev->phy;
3277
3278         B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
3279         if (b43_status(dev) != B43_STAT_INITIALIZED)
3280                 return;
3281         b43_set_status(dev, B43_STAT_UNINIT);
3282
3283         b43_leds_exit(dev);
3284         b43_rng_exit(dev->wl);
3285         b43_pio_free(dev);
3286         b43_dma_free(dev);
3287         b43_chip_exit(dev);
3288         b43_radio_turn_off(dev, 1);
3289         b43_switch_analog(dev, 0);
3290         if (phy->dyn_tssi_tbl)
3291                 kfree(phy->tssi2dbm);
3292         kfree(phy->lo_control);
3293         phy->lo_control = NULL;
3294         ssb_device_disable(dev->dev, 0);
3295         ssb_bus_may_powerdown(dev->dev->bus);
3296 }
3297
3298 /* Initialize a wireless core */
3299 static int b43_wireless_core_init(struct b43_wldev *dev)
3300 {
3301         struct b43_wl *wl = dev->wl;
3302         struct ssb_bus *bus = dev->dev->bus;
3303         struct ssb_sprom *sprom = &bus->sprom;
3304         struct b43_phy *phy = &dev->phy;
3305         int err;
3306         u32 hf, tmp;
3307
3308         B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3309
3310         err = ssb_bus_powerup(bus, 0);
3311         if (err)
3312                 goto out;
3313         if (!ssb_device_is_enabled(dev->dev)) {
3314                 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
3315                 b43_wireless_core_reset(dev, tmp);
3316         }
3317
3318         if ((phy->type == B43_PHYTYPE_B) || (phy->type == B43_PHYTYPE_G)) {
3319                 phy->lo_control =
3320                     kzalloc(sizeof(*(phy->lo_control)), GFP_KERNEL);
3321                 if (!phy->lo_control) {
3322                         err = -ENOMEM;
3323                         goto err_busdown;
3324                 }
3325         }
3326         setup_struct_wldev_for_init(dev);
3327
3328         err = b43_phy_init_tssi2dbm_table(dev);
3329         if (err)
3330                 goto err_kfree_lo_control;
3331
3332         /* Enable IRQ routing to this device. */
3333         ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3334
3335         b43_imcfglo_timeouts_workaround(dev);
3336         b43_bluetooth_coext_disable(dev);
3337         b43_phy_early_init(dev);
3338         err = b43_chip_init(dev);
3339         if (err)
3340                 goto err_kfree_tssitbl;
3341         b43_shm_write16(dev, B43_SHM_SHARED,
3342                         B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
3343         hf = b43_hf_read(dev);
3344         if (phy->type == B43_PHYTYPE_G) {
3345                 hf |= B43_HF_SYMW;
3346                 if (phy->rev == 1)
3347                         hf |= B43_HF_GDCW;
3348                 if (sprom->boardflags_lo & B43_BFL_PACTRL)
3349                         hf |= B43_HF_OFDMPABOOST;
3350         } else if (phy->type == B43_PHYTYPE_B) {
3351                 hf |= B43_HF_SYMW;
3352                 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
3353                         hf &= ~B43_HF_GDCW;
3354         }
3355         b43_hf_write(dev, hf);
3356
3357         b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
3358                              B43_DEFAULT_LONG_RETRY_LIMIT);
3359         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
3360         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
3361
3362         /* Disable sending probe responses from firmware.
3363          * Setting the MaxTime to one usec will always trigger
3364          * a timeout, so we never send any probe resp.
3365          * A timeout of zero is infinite. */
3366         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
3367
3368         b43_rate_memory_init(dev);
3369
3370         /* Minimum Contention Window */
3371         if (phy->type == B43_PHYTYPE_B) {
3372                 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
3373         } else {
3374                 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
3375         }
3376         /* Maximum Contention Window */
3377         b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
3378
3379         do {
3380                 if (b43_using_pio(dev)) {
3381                         err = b43_pio_init(dev);
3382                 } else {
3383                         err = b43_dma_init(dev);
3384                         if (!err)
3385                                 b43_qos_init(dev);
3386                 }
3387         } while (err == -EAGAIN);
3388         if (err)
3389                 goto err_chip_exit;
3390
3391 //FIXME
3392 #if 1
3393         b43_write16(dev, 0x0612, 0x0050);
3394         b43_shm_write16(dev, B43_SHM_SHARED, 0x0416, 0x0050);
3395         b43_shm_write16(dev, B43_SHM_SHARED, 0x0414, 0x01F4);
3396 #endif
3397
3398         b43_bluetooth_coext_enable(dev);
3399
3400         ssb_bus_powerup(bus, 1);        /* Enable dynamic PCTL */
3401         memset(wl->bssid, 0, ETH_ALEN);
3402         memset(wl->mac_addr, 0, ETH_ALEN);
3403         b43_upload_card_macaddress(dev);
3404         b43_security_init(dev);
3405         b43_rng_init(wl);
3406
3407         b43_set_status(dev, B43_STAT_INITIALIZED);
3408
3409         b43_leds_init(dev);
3410 out:
3411         return err;
3412
3413       err_chip_exit:
3414         b43_chip_exit(dev);
3415       err_kfree_tssitbl:
3416         if (phy->dyn_tssi_tbl)
3417                 kfree(phy->tssi2dbm);
3418       err_kfree_lo_control:
3419         kfree(phy->lo_control);
3420         phy->lo_control = NULL;
3421       err_busdown:
3422         ssb_bus_may_powerdown(bus);
3423         B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3424         return err;
3425 }
3426
3427 static int b43_op_add_interface(struct ieee80211_hw *hw,
3428                                 struct ieee80211_if_init_conf *conf)
3429 {
3430         struct b43_wl *wl = hw_to_b43_wl(hw);
3431         struct b43_wldev *dev;
3432         unsigned long flags;
3433         int err = -EOPNOTSUPP;
3434
3435         /* TODO: allow WDS/AP devices to coexist */
3436
3437         if (conf->type != IEEE80211_IF_TYPE_AP &&
3438             conf->type != IEEE80211_IF_TYPE_STA &&
3439             conf->type != IEEE80211_IF_TYPE_WDS &&
3440             conf->type != IEEE80211_IF_TYPE_IBSS)
3441                 return -EOPNOTSUPP;
3442
3443         mutex_lock(&wl->mutex);
3444         if (wl->operating)
3445                 goto out_mutex_unlock;
3446
3447         b43dbg(wl, "Adding Interface type %d\n", conf->type);
3448
3449         dev = wl->current_dev;
3450         wl->operating = 1;
3451         wl->if_id = conf->if_id;
3452         wl->if_type = conf->type;
3453         memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
3454
3455         spin_lock_irqsave(&wl->irq_lock, flags);
3456         b43_adjust_opmode(dev);
3457         b43_upload_card_macaddress(dev);
3458         spin_unlock_irqrestore(&wl->irq_lock, flags);
3459
3460         err = 0;
3461  out_mutex_unlock:
3462         mutex_unlock(&wl->mutex);
3463
3464         return err;
3465 }
3466
3467 static void b43_op_remove_interface(struct ieee80211_hw *hw,
3468                                     struct ieee80211_if_init_conf *conf)
3469 {
3470         struct b43_wl *wl = hw_to_b43_wl(hw);
3471         struct b43_wldev *dev = wl->current_dev;
3472         unsigned long flags;
3473
3474         b43dbg(wl, "Removing Interface type %d\n", conf->type);
3475
3476         mutex_lock(&wl->mutex);
3477
3478         B43_WARN_ON(!wl->operating);
3479         B43_WARN_ON(wl->if_id != conf->if_id);
3480
3481         wl->operating = 0;
3482
3483         spin_lock_irqsave(&wl->irq_lock, flags);
3484         b43_adjust_opmode(dev);
3485         memset(wl->mac_addr, 0, ETH_ALEN);
3486         b43_upload_card_macaddress(dev);
3487         spin_unlock_irqrestore(&wl->irq_lock, flags);
3488
3489         mutex_unlock(&wl->mutex);
3490 }
3491
3492 static int b43_op_start(struct ieee80211_hw *hw)
3493 {
3494         struct b43_wl *wl = hw_to_b43_wl(hw);
3495         struct b43_wldev *dev = wl->current_dev;
3496         int did_init = 0;
3497         int err = 0;
3498
3499         /* First register RFkill.
3500          * LEDs that are registered later depend on it. */
3501         b43_rfkill_init(dev);
3502
3503         mutex_lock(&wl->mutex);
3504
3505         if (b43_status(dev) < B43_STAT_INITIALIZED) {
3506                 err = b43_wireless_core_init(dev);
3507                 if (err)
3508                         goto out_mutex_unlock;
3509                 did_init = 1;
3510         }
3511
3512         if (b43_status(dev) < B43_STAT_STARTED) {
3513                 err = b43_wireless_core_start(dev);
3514                 if (err) {
3515                         if (did_init)
3516                                 b43_wireless_core_exit(dev);
3517                         goto out_mutex_unlock;
3518                 }
3519         }
3520
3521  out_mutex_unlock:
3522         mutex_unlock(&wl->mutex);
3523
3524         return err;
3525 }
3526
3527 static void b43_op_stop(struct ieee80211_hw *hw)
3528 {
3529         struct b43_wl *wl = hw_to_b43_wl(hw);
3530         struct b43_wldev *dev = wl->current_dev;
3531
3532         b43_rfkill_exit(dev);
3533
3534         mutex_lock(&wl->mutex);
3535         if (b43_status(dev) >= B43_STAT_STARTED)
3536                 b43_wireless_core_stop(dev);
3537         b43_wireless_core_exit(dev);
3538         mutex_unlock(&wl->mutex);
3539 }
3540
3541 static int b43_op_set_retry_limit(struct ieee80211_hw *hw,
3542                                   u32 short_retry_limit, u32 long_retry_limit)
3543 {
3544         struct b43_wl *wl = hw_to_b43_wl(hw);
3545         struct b43_wldev *dev;
3546         int err = 0;
3547
3548         mutex_lock(&wl->mutex);
3549         dev = wl->current_dev;
3550         if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED))) {
3551                 err = -ENODEV;
3552                 goto out_unlock;
3553         }
3554         b43_set_retry_limits(dev, short_retry_limit, long_retry_limit);
3555 out_unlock:
3556         mutex_unlock(&wl->mutex);
3557
3558         return err;
3559 }
3560
3561 static const struct ieee80211_ops b43_hw_ops = {
3562         .tx                     = b43_op_tx,
3563         .conf_tx                = b43_op_conf_tx,
3564         .add_interface          = b43_op_add_interface,
3565         .remove_interface       = b43_op_remove_interface,
3566         .config                 = b43_op_config,
3567         .config_interface       = b43_op_config_interface,
3568         .configure_filter       = b43_op_configure_filter,
3569         .set_key                = b43_op_set_key,
3570         .get_stats              = b43_op_get_stats,
3571         .get_tx_stats           = b43_op_get_tx_stats,
3572         .start                  = b43_op_start,
3573         .stop                   = b43_op_stop,
3574         .set_retry_limit        = b43_op_set_retry_limit,
3575 };
3576
3577 /* Hard-reset the chip. Do not call this directly.
3578  * Use b43_controller_restart()
3579  */
3580 static void b43_chip_reset(struct work_struct *work)
3581 {
3582         struct b43_wldev *dev =
3583             container_of(work, struct b43_wldev, restart_work);
3584         struct b43_wl *wl = dev->wl;
3585         int err = 0;
3586         int prev_status;
3587
3588         mutex_lock(&wl->mutex);
3589
3590         prev_status = b43_status(dev);
3591         /* Bring the device down... */
3592         if (prev_status >= B43_STAT_STARTED)
3593                 b43_wireless_core_stop(dev);
3594         if (prev_status >= B43_STAT_INITIALIZED)
3595                 b43_wireless_core_exit(dev);
3596
3597         /* ...and up again. */
3598         if (prev_status >= B43_STAT_INITIALIZED) {
3599                 err = b43_wireless_core_init(dev);
3600                 if (err)
3601                         goto out;
3602         }
3603         if (prev_status >= B43_STAT_STARTED) {
3604                 err = b43_wireless_core_start(dev);
3605                 if (err) {
3606                         b43_wireless_core_exit(dev);
3607                         goto out;
3608                 }
3609         }
3610       out:
3611         mutex_unlock(&wl->mutex);
3612         if (err)
3613                 b43err(wl, "Controller restart FAILED\n");
3614         else
3615                 b43info(wl, "Controller restarted\n");
3616 }
3617
3618 static int b43_setup_modes(struct b43_wldev *dev,
3619                            int have_aphy, int have_bphy, int have_gphy)
3620 {
3621         struct ieee80211_hw *hw = dev->wl->hw;
3622         struct ieee80211_hw_mode *mode;
3623         struct b43_phy *phy = &dev->phy;
3624         int cnt = 0;
3625         int err;
3626
3627 /*FIXME: Don't tell ieee80211 about an A-PHY, because we currently don't support A-PHY. */
3628         have_aphy = 0;
3629
3630         phy->possible_phymodes = 0;
3631         for (; 1; cnt++) {
3632                 if (have_aphy) {
3633                         B43_WARN_ON(cnt >= B43_MAX_PHYHWMODES);
3634                         mode = &phy->hwmodes[cnt];
3635
3636                         mode->mode = MODE_IEEE80211A;
3637                         mode->num_channels = b43_a_chantable_size;
3638                         mode->channels = b43_a_chantable;
3639                         mode->num_rates = b43_a_ratetable_size;
3640                         mode->rates = b43_a_ratetable;
3641                         err = ieee80211_register_hwmode(hw, mode);
3642                         if (err)
3643                                 return err;
3644
3645                         phy->possible_phymodes |= B43_PHYMODE_A;
3646                         have_aphy = 0;
3647                         continue;
3648                 }
3649                 if (have_bphy) {
3650                         B43_WARN_ON(cnt >= B43_MAX_PHYHWMODES);
3651                         mode = &phy->hwmodes[cnt];
3652
3653                         mode->mode = MODE_IEEE80211B;
3654                         mode->num_channels = b43_bg_chantable_size;
3655                         mode->channels = b43_bg_chantable;
3656                         mode->num_rates = b43_b_ratetable_size;
3657                         mode->rates = b43_b_ratetable;
3658                         err = ieee80211_register_hwmode(hw, mode);
3659                         if (err)
3660                                 return err;
3661
3662                         phy->possible_phymodes |= B43_PHYMODE_B;
3663                         have_bphy = 0;
3664                         continue;
3665                 }
3666                 if (have_gphy) {
3667                         B43_WARN_ON(cnt >= B43_MAX_PHYHWMODES);
3668                         mode = &phy->hwmodes[cnt];
3669
3670                         mode->mode = MODE_IEEE80211G;
3671                         mode->num_channels = b43_bg_chantable_size;
3672                         mode->channels = b43_bg_chantable;
3673                         mode->num_rates = b43_g_ratetable_size;
3674                         mode->rates = b43_g_ratetable;
3675                         err = ieee80211_register_hwmode(hw, mode);
3676                         if (err)
3677                                 return err;
3678
3679                         phy->possible_phymodes |= B43_PHYMODE_G;
3680                         have_gphy = 0;
3681                         continue;
3682                 }
3683                 break;
3684         }
3685
3686         return 0;
3687 }
3688
3689 static void b43_wireless_core_detach(struct b43_wldev *dev)
3690 {
3691         /* We release firmware that late to not be required to re-request
3692          * is all the time when we reinit the core. */
3693         b43_release_firmware(dev);
3694 }
3695
3696 static int b43_wireless_core_attach(struct b43_wldev *dev)
3697 {
3698         struct b43_wl *wl = dev->wl;
3699         struct ssb_bus *bus = dev->dev->bus;
3700         struct pci_dev *pdev = bus->host_pci;
3701         int err;
3702         int have_aphy = 0, have_bphy = 0, have_gphy = 0;
3703         u32 tmp;
3704
3705         /* Do NOT do any device initialization here.
3706          * Do it in wireless_core_init() instead.
3707          * This function is for gathering basic information about the HW, only.
3708          * Also some structs may be set up here. But most likely you want to have
3709          * that in core_init(), too.
3710          */
3711
3712         err = ssb_bus_powerup(bus, 0);
3713         if (err) {
3714                 b43err(wl, "Bus powerup failed\n");
3715                 goto out;
3716         }
3717         /* Get the PHY type. */
3718         if (dev->dev->id.revision >= 5) {
3719                 u32 tmshigh;
3720
3721                 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
3722                 have_aphy = !!(tmshigh & B43_TMSHIGH_APHY);
3723                 have_gphy = !!(tmshigh & B43_TMSHIGH_GPHY);
3724                 if (!have_aphy && !have_gphy)
3725                         have_bphy = 1;
3726         } else if (dev->dev->id.revision == 4) {
3727                 have_gphy = 1;
3728                 have_aphy = 1;
3729         } else
3730                 have_bphy = 1;
3731
3732         dev->phy.gmode = (have_gphy || have_bphy);
3733         tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3734         b43_wireless_core_reset(dev, tmp);
3735
3736         err = b43_phy_versioning(dev);
3737         if (err)
3738                 goto err_powerdown;
3739         /* Check if this device supports multiband. */
3740         if (!pdev ||
3741             (pdev->device != 0x4312 &&
3742              pdev->device != 0x4319 && pdev->device != 0x4324)) {
3743                 /* No multiband support. */
3744                 have_aphy = 0;
3745                 have_bphy = 0;
3746                 have_gphy = 0;
3747                 switch (dev->phy.type) {
3748                 case B43_PHYTYPE_A:
3749                         have_aphy = 1;
3750                         break;
3751                 case B43_PHYTYPE_B:
3752                         have_bphy = 1;
3753                         break;
3754                 case B43_PHYTYPE_G:
3755                         have_gphy = 1;
3756                         break;
3757                 default:
3758                         B43_WARN_ON(1);
3759                 }
3760         }
3761         dev->phy.gmode = (have_gphy || have_bphy);
3762         tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3763         b43_wireless_core_reset(dev, tmp);
3764
3765         err = b43_validate_chipaccess(dev);
3766         if (err)
3767                 goto err_powerdown;
3768         err = b43_setup_modes(dev, have_aphy, have_bphy, have_gphy);
3769         if (err)
3770                 goto err_powerdown;
3771
3772         /* Now set some default "current_dev" */
3773         if (!wl->current_dev)
3774                 wl->current_dev = dev;
3775         INIT_WORK(&dev->restart_work, b43_chip_reset);
3776
3777         b43_radio_turn_off(dev, 1);
3778         b43_switch_analog(dev, 0);
3779         ssb_device_disable(dev->dev, 0);
3780         ssb_bus_may_powerdown(bus);
3781
3782 out:
3783         return err;
3784
3785 err_powerdown:
3786         ssb_bus_may_powerdown(bus);
3787         return err;
3788 }
3789
3790 static void b43_one_core_detach(struct ssb_device *dev)
3791 {
3792         struct b43_wldev *wldev;
3793         struct b43_wl *wl;
3794
3795         wldev = ssb_get_drvdata(dev);
3796         wl = wldev->wl;
3797         cancel_work_sync(&wldev->restart_work);
3798         b43_debugfs_remove_device(wldev);
3799         b43_wireless_core_detach(wldev);
3800         list_del(&wldev->list);
3801         wl->nr_devs--;
3802         ssb_set_drvdata(dev, NULL);
3803         kfree(wldev);
3804 }
3805
3806 static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
3807 {
3808         struct b43_wldev *wldev;
3809         struct pci_dev *pdev;
3810         int err = -ENOMEM;
3811
3812         if (!list_empty(&wl->devlist)) {
3813                 /* We are not the first core on this chip. */
3814                 pdev = dev->bus->host_pci;
3815                 /* Only special chips support more than one wireless
3816                  * core, although some of the other chips have more than
3817                  * one wireless core as well. Check for this and
3818                  * bail out early.
3819                  */
3820                 if (!pdev ||
3821                     ((pdev->device != 0x4321) &&
3822                      (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
3823                         b43dbg(wl, "Ignoring unconnected 802.11 core\n");
3824                         return -ENODEV;
3825                 }
3826         }
3827
3828         wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
3829         if (!wldev)
3830                 goto out;
3831
3832         wldev->dev = dev;
3833         wldev->wl = wl;
3834         b43_set_status(wldev, B43_STAT_UNINIT);
3835         wldev->bad_frames_preempt = modparam_bad_frames_preempt;
3836         tasklet_init(&wldev->isr_tasklet,
3837                      (void (*)(unsigned long))b43_interrupt_tasklet,
3838                      (unsigned long)wldev);
3839         if (modparam_pio)
3840                 wldev->__using_pio = 1;
3841         INIT_LIST_HEAD(&wldev->list);
3842
3843         err = b43_wireless_core_attach(wldev);
3844         if (err)
3845                 goto err_kfree_wldev;
3846
3847         list_add(&wldev->list, &wl->devlist);
3848         wl->nr_devs++;
3849         ssb_set_drvdata(dev, wldev);
3850         b43_debugfs_add_device(wldev);
3851
3852       out:
3853         return err;
3854
3855       err_kfree_wldev:
3856         kfree(wldev);
3857         return err;
3858 }
3859
3860 static void b43_sprom_fixup(struct ssb_bus *bus)
3861 {
3862         /* boardflags workarounds */
3863         if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
3864             bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
3865                 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
3866         if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3867             bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
3868                 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
3869
3870         /* Handle case when gain is not set in sprom */
3871         if (bus->sprom.antenna_gain_a == 0xFF)
3872                 bus->sprom.antenna_gain_a = 2;
3873         if (bus->sprom.antenna_gain_bg == 0xFF)
3874                 bus->sprom.antenna_gain_bg = 2;
3875
3876         /* Convert Antennagain values to Q5.2 */
3877         bus->sprom.antenna_gain_a <<= 2;
3878         bus->sprom.antenna_gain_bg <<= 2;
3879 }
3880
3881 static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
3882 {
3883         struct ieee80211_hw *hw = wl->hw;
3884
3885         ssb_set_devtypedata(dev, NULL);
3886         ieee80211_free_hw(hw);
3887 }
3888
3889 static int b43_wireless_init(struct ssb_device *dev)
3890 {
3891         struct ssb_sprom *sprom = &dev->bus->sprom;
3892         struct ieee80211_hw *hw;
3893         struct b43_wl *wl;
3894         int err = -ENOMEM;
3895
3896         b43_sprom_fixup(dev->bus);
3897
3898         hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
3899         if (!hw) {
3900                 b43err(NULL, "Could not allocate ieee80211 device\n");
3901                 goto out;
3902         }
3903
3904         /* fill hw info */
3905         hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE;
3906         hw->max_signal = 100;
3907         hw->max_rssi = -110;
3908         hw->max_noise = -110;
3909         hw->queues = 1;         /* FIXME: hardware has more queues */
3910         SET_IEEE80211_DEV(hw, dev->dev);
3911         if (is_valid_ether_addr(sprom->et1mac))
3912                 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
3913         else
3914                 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
3915
3916         /* Get and initialize struct b43_wl */
3917         wl = hw_to_b43_wl(hw);
3918         memset(wl, 0, sizeof(*wl));
3919         wl->hw = hw;
3920         spin_lock_init(&wl->irq_lock);
3921         spin_lock_init(&wl->leds_lock);
3922         mutex_init(&wl->mutex);
3923         INIT_LIST_HEAD(&wl->devlist);
3924
3925         ssb_set_devtypedata(dev, wl);
3926         b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
3927         err = 0;
3928       out:
3929         return err;
3930 }
3931
3932 static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
3933 {
3934         struct b43_wl *wl;
3935         int err;
3936         int first = 0;
3937
3938         wl = ssb_get_devtypedata(dev);
3939         if (!wl) {
3940                 /* Probing the first core. Must setup common struct b43_wl */
3941                 first = 1;
3942                 err = b43_wireless_init(dev);
3943                 if (err)
3944                         goto out;
3945                 wl = ssb_get_devtypedata(dev);
3946                 B43_WARN_ON(!wl);
3947         }
3948         err = b43_one_core_attach(dev, wl);
3949         if (err)
3950                 goto err_wireless_exit;
3951
3952         if (first) {
3953                 err = ieee80211_register_hw(wl->hw);
3954                 if (err)
3955                         goto err_one_core_detach;
3956         }
3957
3958       out:
3959         return err;
3960
3961       err_one_core_detach:
3962         b43_one_core_detach(dev);
3963       err_wireless_exit:
3964         if (first)
3965                 b43_wireless_exit(dev, wl);
3966         return err;
3967 }
3968
3969 static void b43_remove(struct ssb_device *dev)
3970 {
3971         struct b43_wl *wl = ssb_get_devtypedata(dev);
3972         struct b43_wldev *wldev = ssb_get_drvdata(dev);
3973
3974         B43_WARN_ON(!wl);
3975         if (wl->current_dev == wldev)
3976                 ieee80211_unregister_hw(wl->hw);
3977
3978         b43_one_core_detach(dev);
3979
3980         if (list_empty(&wl->devlist)) {
3981                 /* Last core on the chip unregistered.
3982                  * We can destroy common struct b43_wl.
3983                  */
3984                 b43_wireless_exit(dev, wl);
3985         }
3986 }
3987
3988 /* Perform a hardware reset. This can be called from any context. */
3989 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
3990 {
3991         /* Must avoid requeueing, if we are in shutdown. */
3992         if (b43_status(dev) < B43_STAT_INITIALIZED)
3993                 return;
3994         b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
3995         queue_work(dev->wl->hw->workqueue, &dev->restart_work);
3996 }
3997
3998 #ifdef CONFIG_PM
3999
4000 static int b43_suspend(struct ssb_device *dev, pm_message_t state)
4001 {
4002         struct b43_wldev *wldev = ssb_get_drvdata(dev);
4003         struct b43_wl *wl = wldev->wl;
4004
4005         b43dbg(wl, "Suspending...\n");
4006
4007         mutex_lock(&wl->mutex);
4008         wldev->suspend_init_status = b43_status(wldev);
4009         if (wldev->suspend_init_status >= B43_STAT_STARTED)
4010                 b43_wireless_core_stop(wldev);
4011         if (wldev->suspend_init_status >= B43_STAT_INITIALIZED)
4012                 b43_wireless_core_exit(wldev);
4013         mutex_unlock(&wl->mutex);
4014
4015         b43dbg(wl, "Device suspended.\n");
4016
4017         return 0;
4018 }
4019
4020 static int b43_resume(struct ssb_device *dev)
4021 {
4022         struct b43_wldev *wldev = ssb_get_drvdata(dev);
4023         struct b43_wl *wl = wldev->wl;
4024         int err = 0;
4025
4026         b43dbg(wl, "Resuming...\n");
4027
4028         mutex_lock(&wl->mutex);
4029         if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
4030                 err = b43_wireless_core_init(wldev);
4031                 if (err) {
4032                         b43err(wl, "Resume failed at core init\n");
4033                         goto out;
4034                 }
4035         }
4036         if (wldev->suspend_init_status >= B43_STAT_STARTED) {
4037                 err = b43_wireless_core_start(wldev);
4038                 if (err) {
4039                         b43_wireless_core_exit(wldev);
4040                         b43err(wl, "Resume failed at core start\n");
4041                         goto out;
4042                 }
4043         }
4044         mutex_unlock(&wl->mutex);
4045
4046         b43dbg(wl, "Device resumed.\n");
4047       out:
4048         return err;
4049 }
4050
4051 #else /* CONFIG_PM */
4052 # define b43_suspend    NULL
4053 # define b43_resume     NULL
4054 #endif /* CONFIG_PM */
4055
4056 static struct ssb_driver b43_ssb_driver = {
4057         .name           = KBUILD_MODNAME,
4058         .id_table       = b43_ssb_tbl,
4059         .probe          = b43_probe,
4060         .remove         = b43_remove,
4061         .suspend        = b43_suspend,
4062         .resume         = b43_resume,
4063 };
4064
4065 static int __init b43_init(void)
4066 {
4067         int err;
4068
4069         b43_debugfs_init();
4070         err = b43_pcmcia_init();
4071         if (err)
4072                 goto err_dfs_exit;
4073         err = ssb_driver_register(&b43_ssb_driver);
4074         if (err)
4075                 goto err_pcmcia_exit;
4076
4077         return err;
4078
4079 err_pcmcia_exit:
4080         b43_pcmcia_exit();
4081 err_dfs_exit:
4082         b43_debugfs_exit();
4083         return err;
4084 }
4085
4086 static void __exit b43_exit(void)
4087 {
4088         ssb_driver_unregister(&b43_ssb_driver);
4089         b43_pcmcia_exit();
4090         b43_debugfs_exit();
4091 }
4092
4093 module_init(b43_init)
4094 module_exit(b43_exit)