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   1 /*
   2
   3   Broadcom B43 wireless driver
   4
   5   Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
   6   Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
   7   Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
   8   Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
   9   Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
  10
  11   Some parts of the code in this file are derived from the ipw2200
  12   driver  Copyright(c) 2003 - 2004 Intel Corporation.
  13
  14   This program is free software; you can redistribute it and/or modify
  15   it under the terms of the GNU General Public License as published by
  16   the Free Software Foundation; either version 2 of the License, or
  17   (at your option) any later version.
  18
  19   This program is distributed in the hope that it will be useful,
  20   but WITHOUT ANY WARRANTY; without even the implied warranty of
  21   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22   GNU General Public License for more details.
  23
  24   You should have received a copy of the GNU General Public License
  25   along with this program; see the file COPYING.  If not, write to
  26   the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
  27   Boston, MA 02110-1301, USA.
  28
  29 */
  30
  31 #include <linux/delay.h>
  32 #include <linux/init.h>
  33 #include <linux/moduleparam.h>
  34 #include <linux/if_arp.h>
  35 #include <linux/etherdevice.h>
  36 #include <linux/version.h>
  37 #include <linux/firmware.h>
  38 #include <linux/wireless.h>
  39 #include <linux/workqueue.h>
  40 #include <linux/skbuff.h>
  41 #include <linux/dma-mapping.h>
  42 #include <asm/unaligned.h>
  43
  44 #include "b43.h"
  45 #include "main.h"
  46 #include "debugfs.h"
  47 #include "phy.h"
  48 #include "dma.h"
  49 #include "pio.h"
  50 #include "sysfs.h"
  51 #include "xmit.h"
  52 #include "lo.h"
  53 #include "pcmcia.h"
  54
  55 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
  56 MODULE_AUTHOR("Martin Langer");
  57 MODULE_AUTHOR("Stefano Brivio");
  58 MODULE_AUTHOR("Michael Buesch");
  59 MODULE_LICENSE("GPL");
  60
  61 extern char *nvram_get(char *name);
  62
  63 #if defined(CONFIG_B43_DMA) && defined(CONFIG_B43_PIO)
  64 static int modparam_pio;
  65 module_param_named(pio, modparam_pio, int, 0444);
  66 MODULE_PARM_DESC(pio, "enable(1) / disable(0) PIO mode");
  67 #elif defined(CONFIG_B43_DMA)
  68 # define modparam_pio   0
  69 #elif defined(CONFIG_B43_PIO)
  70 # define modparam_pio   1
  71 #endif
  72
  73 static int modparam_bad_frames_preempt;
  74 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
  75 MODULE_PARM_DESC(bad_frames_preempt,
  76                  "enable(1) / disable(0) Bad Frames Preemption");
  77
  78 static char modparam_fwpostfix[16];
  79 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
  80 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
  81
  82 static int modparam_hwpctl;
  83 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
  84 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
  85
  86 static int modparam_nohwcrypt;
  87 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
  88 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
  89
  90 static const struct ssb_device_id b43_ssb_tbl[] = {
  91         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
  92         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
  93         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
  94         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
  95         SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
  96         SSB_DEVTABLE_END
  97 };
  98
  99 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
 100
 101 /* Channel and ratetables are shared for all devices.
 102  * They can't be const, because ieee80211 puts some precalculated
 103  * data in there. This data is the same for all devices, so we don't
 104  * get concurrency issues */
 105 #define RATETAB_ENT(_rateid, _flags) \
 106         {                                                       \
 107                 .rate   = B43_RATE_TO_BASE100KBPS(_rateid),     \
 108                 .val    = (_rateid),                            \
 109                 .val2   = (_rateid),                            \
 110                 .flags  = (_flags),                             \
 111         }
 112 static struct ieee80211_rate __b43_ratetable[] = {
 113         RATETAB_ENT(B43_CCK_RATE_1MB, IEEE80211_RATE_CCK),
 114         RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_CCK_2),
 115         RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_CCK_2),
 116         RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_CCK_2),
 117         RATETAB_ENT(B43_OFDM_RATE_6MB, IEEE80211_RATE_OFDM),
 118         RATETAB_ENT(B43_OFDM_RATE_9MB, IEEE80211_RATE_OFDM),
 119         RATETAB_ENT(B43_OFDM_RATE_12MB, IEEE80211_RATE_OFDM),
 120         RATETAB_ENT(B43_OFDM_RATE_18MB, IEEE80211_RATE_OFDM),
 121         RATETAB_ENT(B43_OFDM_RATE_24MB, IEEE80211_RATE_OFDM),
 122         RATETAB_ENT(B43_OFDM_RATE_36MB, IEEE80211_RATE_OFDM),
 123         RATETAB_ENT(B43_OFDM_RATE_48MB, IEEE80211_RATE_OFDM),
 124         RATETAB_ENT(B43_OFDM_RATE_54MB, IEEE80211_RATE_OFDM),
 125 };
 126
 127 #define b43_a_ratetable         (__b43_ratetable + 4)
 128 #define b43_a_ratetable_size    8
 129 #define b43_b_ratetable         (__b43_ratetable + 0)
 130 #define b43_b_ratetable_size    4
 131 #define b43_g_ratetable         (__b43_ratetable + 0)
 132 #define b43_g_ratetable_size    12
 133
 134 #define CHANTAB_ENT(_chanid, _freq) \
 135         {                                                       \
 136                 .chan   = (_chanid),                            \
 137                 .freq   = (_freq),                              \
 138                 .val    = (_chanid),                            \
 139                 .flag   = IEEE80211_CHAN_W_SCAN |               \
 140                           IEEE80211_CHAN_W_ACTIVE_SCAN |        \
 141                           IEEE80211_CHAN_W_IBSS,                \
 142                 .power_level    = 0xFF,                         \
 143                 .antenna_max    = 0xFF,                         \
 144         }
 145 static struct ieee80211_channel b43_bg_chantable[] = {
 146         CHANTAB_ENT(1, 2412),
 147         CHANTAB_ENT(2, 2417),
 148         CHANTAB_ENT(3, 2422),
 149         CHANTAB_ENT(4, 2427),
 150         CHANTAB_ENT(5, 2432),
 151         CHANTAB_ENT(6, 2437),
 152         CHANTAB_ENT(7, 2442),
 153         CHANTAB_ENT(8, 2447),
 154         CHANTAB_ENT(9, 2452),
 155         CHANTAB_ENT(10, 2457),
 156         CHANTAB_ENT(11, 2462),
 157         CHANTAB_ENT(12, 2467),
 158         CHANTAB_ENT(13, 2472),
 159         CHANTAB_ENT(14, 2484),
 160 };
 161
 162 #define b43_bg_chantable_size   ARRAY_SIZE(b43_bg_chantable)
 163 static struct ieee80211_channel b43_a_chantable[] = {
 164         CHANTAB_ENT(36, 5180),
 165         CHANTAB_ENT(40, 5200),
 166         CHANTAB_ENT(44, 5220),
 167         CHANTAB_ENT(48, 5240),
 168         CHANTAB_ENT(52, 5260),
 169         CHANTAB_ENT(56, 5280),
 170         CHANTAB_ENT(60, 5300),
 171         CHANTAB_ENT(64, 5320),
 172         CHANTAB_ENT(149, 5745),
 173         CHANTAB_ENT(153, 5765),
 174         CHANTAB_ENT(157, 5785),
 175         CHANTAB_ENT(161, 5805),
 176         CHANTAB_ENT(165, 5825),
 177 };
 178
 179 #define b43_a_chantable_size    ARRAY_SIZE(b43_a_chantable)
 180
 181 static void b43_wireless_core_exit(struct b43_wldev *dev);
 182 static int b43_wireless_core_init(struct b43_wldev *dev);
 183 static void b43_wireless_core_stop(struct b43_wldev *dev);
 184 static int b43_wireless_core_start(struct b43_wldev *dev);
 185
 186 static int b43_ratelimit(struct b43_wl *wl)
 187 {
 188         if (!wl || !wl->current_dev)
 189                 return 1;
 190         if (b43_status(wl->current_dev) < B43_STAT_STARTED)
 191                 return 1;
 192         /* We are up and running.
 193          * Ratelimit the messages to avoid DoS over the net. */
 194         return net_ratelimit();
 195 }
 196
 197 void b43info(struct b43_wl *wl, const char *fmt, ...)
 198 {
 199         va_list args;
 200
 201         if (!b43_ratelimit(wl))
 202                 return;
 203         va_start(args, fmt);
 204         printk(KERN_INFO "b43-%s: ",
 205                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
 206         vprintk(fmt, args);
 207         va_end(args);
 208 }
 209
 210 void b43err(struct b43_wl *wl, const char *fmt, ...)
 211 {
 212         va_list args;
 213
 214         if (!b43_ratelimit(wl))
 215                 return;
 216         va_start(args, fmt);
 217         printk(KERN_ERR "b43-%s ERROR: ",
 218                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
 219         vprintk(fmt, args);
 220         va_end(args);
 221 }
 222
 223 void b43warn(struct b43_wl *wl, const char *fmt, ...)
 224 {
 225         va_list args;
 226
 227         if (!b43_ratelimit(wl))
 228                 return;
 229         va_start(args, fmt);
 230         printk(KERN_WARNING "b43-%s warning: ",
 231                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
 232         vprintk(fmt, args);
 233         va_end(args);
 234 }
 235
 236 #if B43_DEBUG
 237 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
 238 {
 239         va_list args;
 240
 241         va_start(args, fmt);
 242         printk(KERN_DEBUG "b43-%s debug: ",
 243                (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
 244         vprintk(fmt, args);
 245         va_end(args);
 246 }
 247 #endif /* DEBUG */
 248
 249 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
 250 {
 251         u32 macctl;
 252
 253         B43_WARN_ON(offset % 4 != 0);
 254
 255         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 256         if (macctl & B43_MACCTL_BE)
 257                 val = swab32(val);
 258
 259         b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
 260         mmiowb();
 261         b43_write32(dev, B43_MMIO_RAM_DATA, val);
 262 }
 263
 264 static inline
 265     void b43_shm_control_word(struct b43_wldev *dev, u16 routing, u16 offset)
 266 {
 267         u32 control;
 268
 269         /* "offset" is the WORD offset. */
 270
 271         control = routing;
 272         control <<= 16;
 273         control |= offset;
 274         b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
 275 }
 276
 277 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
 278 {
 279         u32 ret;
 280
 281         if (routing == B43_SHM_SHARED) {
 282                 B43_WARN_ON(offset & 0x0001);
 283                 if (offset & 0x0003) {
 284                         /* Unaligned access */
 285                         b43_shm_control_word(dev, routing, offset >> 2);
 286                         ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
 287                         ret <<= 16;
 288                         b43_shm_control_word(dev, routing, (offset >> 2) + 1);
 289                         ret |= b43_read16(dev, B43_MMIO_SHM_DATA);
 290
 291                         return ret;
 292                 }
 293                 offset >>= 2;
 294         }
 295         b43_shm_control_word(dev, routing, offset);
 296         ret = b43_read32(dev, B43_MMIO_SHM_DATA);
 297
 298         return ret;
 299 }
 300
 301 u16 b43_shm_read16(struct b43_wldev * dev, u16 routing, u16 offset)
 302 {
 303         u16 ret;
 304
 305         if (routing == B43_SHM_SHARED) {
 306                 B43_WARN_ON(offset & 0x0001);
 307                 if (offset & 0x0003) {
 308                         /* Unaligned access */
 309                         b43_shm_control_word(dev, routing, offset >> 2);
 310                         ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
 311
 312                         return ret;
 313                 }
 314                 offset >>= 2;
 315         }
 316         b43_shm_control_word(dev, routing, offset);
 317         ret = b43_read16(dev, B43_MMIO_SHM_DATA);
 318
 319         return ret;
 320 }
 321
 322 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
 323 {
 324         if (routing == B43_SHM_SHARED) {
 325                 B43_WARN_ON(offset & 0x0001);
 326                 if (offset & 0x0003) {
 327                         /* Unaligned access */
 328                         b43_shm_control_word(dev, routing, offset >> 2);
 329                         mmiowb();
 330                         b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
 331                                     (value >> 16) & 0xffff);
 332                         mmiowb();
 333                         b43_shm_control_word(dev, routing, (offset >> 2) + 1);
 334                         mmiowb();
 335                         b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
 336                         return;
 337                 }
 338                 offset >>= 2;
 339         }
 340         b43_shm_control_word(dev, routing, offset);
 341         mmiowb();
 342         b43_write32(dev, B43_MMIO_SHM_DATA, value);
 343 }
 344
 345 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
 346 {
 347         if (routing == B43_SHM_SHARED) {
 348                 B43_WARN_ON(offset & 0x0001);
 349                 if (offset & 0x0003) {
 350                         /* Unaligned access */
 351                         b43_shm_control_word(dev, routing, offset >> 2);
 352                         mmiowb();
 353                         b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
 354                         return;
 355                 }
 356                 offset >>= 2;
 357         }
 358         b43_shm_control_word(dev, routing, offset);
 359         mmiowb();
 360         b43_write16(dev, B43_MMIO_SHM_DATA, value);
 361 }
 362
 363 /* Read HostFlags */
 364 u32 b43_hf_read(struct b43_wldev * dev)
 365 {
 366         u32 ret;
 367
 368         ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
 369         ret <<= 16;
 370         ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
 371
 372         return ret;
 373 }
 374
 375 /* Write HostFlags */
 376 void b43_hf_write(struct b43_wldev *dev, u32 value)
 377 {
 378         b43_shm_write16(dev, B43_SHM_SHARED,
 379                         B43_SHM_SH_HOSTFLO, (value & 0x0000FFFF));
 380         b43_shm_write16(dev, B43_SHM_SHARED,
 381                         B43_SHM_SH_HOSTFHI, ((value & 0xFFFF0000) >> 16));
 382 }
 383
 384 void b43_tsf_read(struct b43_wldev *dev, u64 * tsf)
 385 {
 386         /* We need to be careful. As we read the TSF from multiple
 387          * registers, we should take care of register overflows.
 388          * In theory, the whole tsf read process should be atomic.
 389          * We try to be atomic here, by restaring the read process,
 390          * if any of the high registers changed (overflew).
 391          */
 392         if (dev->dev->id.revision >= 3) {
 393                 u32 low, high, high2;
 394
 395                 do {
 396                         high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
 397                         low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
 398                         high2 = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
 399                 } while (unlikely(high != high2));
 400
 401                 *tsf = high;
 402                 *tsf <<= 32;
 403                 *tsf |= low;
 404         } else {
 405                 u64 tmp;
 406                 u16 v0, v1, v2, v3;
 407                 u16 test1, test2, test3;
 408
 409                 do {
 410                         v3 = b43_read16(dev, B43_MMIO_TSF_3);
 411                         v2 = b43_read16(dev, B43_MMIO_TSF_2);
 412                         v1 = b43_read16(dev, B43_MMIO_TSF_1);
 413                         v0 = b43_read16(dev, B43_MMIO_TSF_0);
 414
 415                         test3 = b43_read16(dev, B43_MMIO_TSF_3);
 416                         test2 = b43_read16(dev, B43_MMIO_TSF_2);
 417                         test1 = b43_read16(dev, B43_MMIO_TSF_1);
 418                 } while (v3 != test3 || v2 != test2 || v1 != test1);
 419
 420                 *tsf = v3;
 421                 *tsf <<= 48;
 422                 tmp = v2;
 423                 tmp <<= 32;
 424                 *tsf |= tmp;
 425                 tmp = v1;
 426                 tmp <<= 16;
 427                 *tsf |= tmp;
 428                 *tsf |= v0;
 429         }
 430 }
 431
 432 static void b43_time_lock(struct b43_wldev *dev)
 433 {
 434         u32 macctl;
 435
 436         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 437         macctl |= B43_MACCTL_TBTTHOLD;
 438         b43_write32(dev, B43_MMIO_MACCTL, macctl);
 439         /* Commit the write */
 440         b43_read32(dev, B43_MMIO_MACCTL);
 441 }
 442
 443 static void b43_time_unlock(struct b43_wldev *dev)
 444 {
 445         u32 macctl;
 446
 447         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 448         macctl &= ~B43_MACCTL_TBTTHOLD;
 449         b43_write32(dev, B43_MMIO_MACCTL, macctl);
 450         /* Commit the write */
 451         b43_read32(dev, B43_MMIO_MACCTL);
 452 }
 453
 454 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
 455 {
 456         /* Be careful with the in-progress timer.
 457          * First zero out the low register, so we have a full
 458          * register-overflow duration to complete the operation.
 459          */
 460         if (dev->dev->id.revision >= 3) {
 461                 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
 462                 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
 463
 464                 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, 0);
 465                 mmiowb();
 466                 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, hi);
 467                 mmiowb();
 468                 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, lo);
 469         } else {
 470                 u16 v0 = (tsf & 0x000000000000FFFFULL);
 471                 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
 472                 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
 473                 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
 474
 475                 b43_write16(dev, B43_MMIO_TSF_0, 0);
 476                 mmiowb();
 477                 b43_write16(dev, B43_MMIO_TSF_3, v3);
 478                 mmiowb();
 479                 b43_write16(dev, B43_MMIO_TSF_2, v2);
 480                 mmiowb();
 481                 b43_write16(dev, B43_MMIO_TSF_1, v1);
 482                 mmiowb();
 483                 b43_write16(dev, B43_MMIO_TSF_0, v0);
 484         }
 485 }
 486
 487 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
 488 {
 489         b43_time_lock(dev);
 490         b43_tsf_write_locked(dev, tsf);
 491         b43_time_unlock(dev);
 492 }
 493
 494 static
 495 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac)
 496 {
 497         static const u8 zero_addr[ETH_ALEN] = { 0 };
 498         u16 data;
 499
 500         if (!mac)
 501                 mac = zero_addr;
 502
 503         offset |= 0x0020;
 504         b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
 505
 506         data = mac[0];
 507         data |= mac[1] << 8;
 508         b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
 509         data = mac[2];
 510         data |= mac[3] << 8;
 511         b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
 512         data = mac[4];
 513         data |= mac[5] << 8;
 514         b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
 515 }
 516
 517 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
 518 {
 519         const u8 *mac;
 520         const u8 *bssid;
 521         u8 mac_bssid[ETH_ALEN * 2];
 522         int i;
 523         u32 tmp;
 524
 525         bssid = dev->wl->bssid;
 526         mac = dev->wl->mac_addr;
 527
 528         b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
 529
 530         memcpy(mac_bssid, mac, ETH_ALEN);
 531         memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
 532
 533         /* Write our MAC address and BSSID to template ram */
 534         for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
 535                 tmp = (u32) (mac_bssid[i + 0]);
 536                 tmp |= (u32) (mac_bssid[i + 1]) << 8;
 537                 tmp |= (u32) (mac_bssid[i + 2]) << 16;
 538                 tmp |= (u32) (mac_bssid[i + 3]) << 24;
 539                 b43_ram_write(dev, 0x20 + i, tmp);
 540         }
 541 }
 542
 543 static void b43_upload_card_macaddress(struct b43_wldev *dev)
 544 {
 545         b43_write_mac_bssid_templates(dev);
 546         b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
 547 }
 548
 549 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
 550 {
 551         /* slot_time is in usec. */
 552         if (dev->phy.type != B43_PHYTYPE_G)
 553                 return;
 554         b43_write16(dev, 0x684, 510 + slot_time);
 555         b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
 556 }
 557
 558 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
 559 {
 560         b43_set_slot_time(dev, 9);
 561         dev->short_slot = 1;
 562 }
 563
 564 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
 565 {
 566         b43_set_slot_time(dev, 20);
 567         dev->short_slot = 0;
 568 }
 569
 570 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
 571  * Returns the _previously_ enabled IRQ mask.
 572  */
 573 static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask)
 574 {
 575         u32 old_mask;
 576
 577         old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
 578         b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask);
 579
 580         return old_mask;
 581 }
 582
 583 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
 584  * Returns the _previously_ enabled IRQ mask.
 585  */
 586 static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask)
 587 {
 588         u32 old_mask;
 589
 590         old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
 591         b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
 592
 593         return old_mask;
 594 }
 595
 596 /* Synchronize IRQ top- and bottom-half.
 597  * IRQs must be masked before calling this.
 598  * This must not be called with the irq_lock held.
 599  */
 600 static void b43_synchronize_irq(struct b43_wldev *dev)
 601 {
 602         synchronize_irq(dev->dev->irq);
 603         tasklet_kill(&dev->isr_tasklet);
 604 }
 605
 606 /* DummyTransmission function, as documented on
 607  * http://bcm-specs.sipsolutions.net/DummyTransmission
 608  */
 609 void b43_dummy_transmission(struct b43_wldev *dev)
 610 {
 611         struct b43_phy *phy = &dev->phy;
 612         unsigned int i, max_loop;
 613         u16 value;
 614         u32 buffer[5] = {
 615                 0x00000000,
 616                 0x00D40000,
 617                 0x00000000,
 618                 0x01000000,
 619                 0x00000000,
 620         };
 621
 622         switch (phy->type) {
 623         case B43_PHYTYPE_A:
 624                 max_loop = 0x1E;
 625                 buffer[0] = 0x000201CC;
 626                 break;
 627         case B43_PHYTYPE_B:
 628         case B43_PHYTYPE_G:
 629                 max_loop = 0xFA;
 630                 buffer[0] = 0x000B846E;
 631                 break;
 632         default:
 633                 B43_WARN_ON(1);
 634                 return;
 635         }
 636
 637         for (i = 0; i < 5; i++)
 638                 b43_ram_write(dev, i * 4, buffer[i]);
 639
 640         /* Commit writes */
 641         b43_read32(dev, B43_MMIO_MACCTL);
 642
 643         b43_write16(dev, 0x0568, 0x0000);
 644         b43_write16(dev, 0x07C0, 0x0000);
 645         value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0);
 646         b43_write16(dev, 0x050C, value);
 647         b43_write16(dev, 0x0508, 0x0000);
 648         b43_write16(dev, 0x050A, 0x0000);
 649         b43_write16(dev, 0x054C, 0x0000);
 650         b43_write16(dev, 0x056A, 0x0014);
 651         b43_write16(dev, 0x0568, 0x0826);
 652         b43_write16(dev, 0x0500, 0x0000);
 653         b43_write16(dev, 0x0502, 0x0030);
 654
 655         if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
 656                 b43_radio_write16(dev, 0x0051, 0x0017);
 657         for (i = 0x00; i < max_loop; i++) {
 658                 value = b43_read16(dev, 0x050E);
 659                 if (value & 0x0080)
 660                         break;
 661                 udelay(10);
 662         }
 663         for (i = 0x00; i < 0x0A; i++) {
 664                 value = b43_read16(dev, 0x050E);
 665                 if (value & 0x0400)
 666                         break;
 667                 udelay(10);
 668         }
 669         for (i = 0x00; i < 0x0A; i++) {
 670                 value = b43_read16(dev, 0x0690);
 671                 if (!(value & 0x0100))
 672                         break;
 673                 udelay(10);
 674         }
 675         if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
 676                 b43_radio_write16(dev, 0x0051, 0x0037);
 677 }
 678
 679 static void key_write(struct b43_wldev *dev,
 680                       u8 index, u8 algorithm, const u8 * key)
 681 {
 682         unsigned int i;
 683         u32 offset;
 684         u16 value;
 685         u16 kidx;
 686
 687         /* Key index/algo block */
 688         kidx = b43_kidx_to_fw(dev, index);
 689         value = ((kidx << 4) | algorithm);
 690         b43_shm_write16(dev, B43_SHM_SHARED,
 691                         B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
 692
 693         /* Write the key to the Key Table Pointer offset */
 694         offset = dev->ktp + (index * B43_SEC_KEYSIZE);
 695         for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
 696                 value = key[i];
 697                 value |= (u16) (key[i + 1]) << 8;
 698                 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
 699         }
 700 }
 701
 702 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr)
 703 {
 704         u32 addrtmp[2] = { 0, 0, };
 705         u8 per_sta_keys_start = 8;
 706
 707         if (b43_new_kidx_api(dev))
 708                 per_sta_keys_start = 4;
 709
 710         B43_WARN_ON(index < per_sta_keys_start);
 711         /* We have two default TX keys and possibly two default RX keys.
 712          * Physical mac 0 is mapped to physical key 4 or 8, depending
 713          * on the firmware version.
 714          * So we must adjust the index here.
 715          */
 716         index -= per_sta_keys_start;
 717
 718         if (addr) {
 719                 addrtmp[0] = addr[0];
 720                 addrtmp[0] |= ((u32) (addr[1]) << 8);
 721                 addrtmp[0] |= ((u32) (addr[2]) << 16);
 722                 addrtmp[0] |= ((u32) (addr[3]) << 24);
 723                 addrtmp[1] = addr[4];
 724                 addrtmp[1] |= ((u32) (addr[5]) << 8);
 725         }
 726
 727         if (dev->dev->id.revision >= 5) {
 728                 /* Receive match transmitter address mechanism */
 729                 b43_shm_write32(dev, B43_SHM_RCMTA,
 730                                 (index * 2) + 0, addrtmp[0]);
 731                 b43_shm_write16(dev, B43_SHM_RCMTA,
 732                                 (index * 2) + 1, addrtmp[1]);
 733         } else {
 734                 /* RXE (Receive Engine) and
 735                  * PSM (Programmable State Machine) mechanism
 736                  */
 737                 if (index < 8) {
 738                         /* TODO write to RCM 16, 19, 22 and 25 */
 739                 } else {
 740                         b43_shm_write32(dev, B43_SHM_SHARED,
 741                                         B43_SHM_SH_PSM + (index * 6) + 0,
 742                                         addrtmp[0]);
 743                         b43_shm_write16(dev, B43_SHM_SHARED,
 744                                         B43_SHM_SH_PSM + (index * 6) + 4,
 745                                         addrtmp[1]);
 746                 }
 747         }
 748 }
 749
 750 static void do_key_write(struct b43_wldev *dev,
 751                          u8 index, u8 algorithm,
 752                          const u8 * key, size_t key_len, const u8 * mac_addr)
 753 {
 754         u8 buf[B43_SEC_KEYSIZE] = { 0, };
 755         u8 per_sta_keys_start = 8;
 756
 757         if (b43_new_kidx_api(dev))
 758                 per_sta_keys_start = 4;
 759
 760         B43_WARN_ON(index >= dev->max_nr_keys);
 761         B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
 762
 763         if (index >= per_sta_keys_start)
 764                 keymac_write(dev, index, NULL); /* First zero out mac. */
 765         if (key)
 766                 memcpy(buf, key, key_len);
 767         key_write(dev, index, algorithm, buf);
 768         if (index >= per_sta_keys_start)
 769                 keymac_write(dev, index, mac_addr);
 770
 771         dev->key[index].algorithm = algorithm;
 772 }
 773
 774 static int b43_key_write(struct b43_wldev *dev,
 775                          int index, u8 algorithm,
 776                          const u8 * key, size_t key_len,
 777                          const u8 * mac_addr,
 778                          struct ieee80211_key_conf *keyconf)
 779 {
 780         int i;
 781         int sta_keys_start;
 782
 783         if (key_len > B43_SEC_KEYSIZE)
 784                 return -EINVAL;
 785         for (i = 0; i < dev->max_nr_keys; i++) {
 786                 /* Check that we don't already have this key. */
 787                 B43_WARN_ON(dev->key[i].keyconf == keyconf);
 788         }
 789         if (index < 0) {
 790                 /* Either pairwise key or address is 00:00:00:00:00:00
 791                  * for transmit-only keys. Search the index. */
 792                 if (b43_new_kidx_api(dev))
 793                         sta_keys_start = 4;
 794                 else
 795                         sta_keys_start = 8;
 796                 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
 797                         if (!dev->key[i].keyconf) {
 798                                 /* found empty */
 799                                 index = i;
 800                                 break;
 801                         }
 802                 }
 803                 if (index < 0) {
 804                         b43err(dev->wl, "Out of hardware key memory\n");
 805                         return -ENOSPC;
 806                 }
 807         } else
 808                 B43_WARN_ON(index > 3);
 809
 810         do_key_write(dev, index, algorithm, key, key_len, mac_addr);
 811         if ((index <= 3) && !b43_new_kidx_api(dev)) {
 812                 /* Default RX key */
 813                 B43_WARN_ON(mac_addr);
 814                 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
 815         }
 816         keyconf->hw_key_idx = index;
 817         dev->key[index].keyconf = keyconf;
 818
 819         return 0;
 820 }
 821
 822 static int b43_key_clear(struct b43_wldev *dev, int index)
 823 {
 824         if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys)))
 825                 return -EINVAL;
 826         do_key_write(dev, index, B43_SEC_ALGO_NONE,
 827                      NULL, B43_SEC_KEYSIZE, NULL);
 828         if ((index <= 3) && !b43_new_kidx_api(dev)) {
 829                 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
 830                              NULL, B43_SEC_KEYSIZE, NULL);
 831         }
 832         dev->key[index].keyconf = NULL;
 833
 834         return 0;
 835 }
 836
 837 static void b43_clear_keys(struct b43_wldev *dev)
 838 {
 839         int i;
 840
 841         for (i = 0; i < dev->max_nr_keys; i++)
 842                 b43_key_clear(dev, i);
 843 }
 844
 845 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
 846 {
 847         u32 macctl;
 848         u16 ucstat;
 849         bool hwps;
 850         bool awake;
 851         int i;
 852
 853         B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
 854                     (ps_flags & B43_PS_DISABLED));
 855         B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
 856
 857         if (ps_flags & B43_PS_ENABLED) {
 858                 hwps = 1;
 859         } else if (ps_flags & B43_PS_DISABLED) {
 860                 hwps = 0;
 861         } else {
 862                 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
 863                 //      and thus is not an AP and we are associated, set bit 25
 864         }
 865         if (ps_flags & B43_PS_AWAKE) {
 866                 awake = 1;
 867         } else if (ps_flags & B43_PS_ASLEEP) {
 868                 awake = 0;
 869         } else {
 870                 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
 871                 //      or we are associated, or FIXME, or the latest PS-Poll packet sent was
 872                 //      successful, set bit26
 873         }
 874
 875 /* FIXME: For now we force awake-on and hwps-off */
 876         hwps = 0;
 877         awake = 1;
 878
 879         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 880         if (hwps)
 881                 macctl |= B43_MACCTL_HWPS;
 882         else
 883                 macctl &= ~B43_MACCTL_HWPS;
 884         if (awake)
 885                 macctl |= B43_MACCTL_AWAKE;
 886         else
 887                 macctl &= ~B43_MACCTL_AWAKE;
 888         b43_write32(dev, B43_MMIO_MACCTL, macctl);
 889         /* Commit write */
 890         b43_read32(dev, B43_MMIO_MACCTL);
 891         if (awake && dev->dev->id.revision >= 5) {
 892                 /* Wait for the microcode to wake up. */
 893                 for (i = 0; i < 100; i++) {
 894                         ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
 895                                                 B43_SHM_SH_UCODESTAT);
 896                         if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
 897                                 break;
 898                         udelay(10);
 899                 }
 900         }
 901 }
 902
 903 /* Turn the Analog ON/OFF */
 904 static void b43_switch_analog(struct b43_wldev *dev, int on)
 905 {
 906         b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
 907 }
 908
 909 void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
 910 {
 911         u32 tmslow;
 912         u32 macctl;
 913
 914         flags |= B43_TMSLOW_PHYCLKEN;
 915         flags |= B43_TMSLOW_PHYRESET;
 916         ssb_device_enable(dev->dev, flags);
 917         msleep(2);              /* Wait for the PLL to turn on. */
 918
 919         /* Now take the PHY out of Reset again */
 920         tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
 921         tmslow |= SSB_TMSLOW_FGC;
 922         tmslow &= ~B43_TMSLOW_PHYRESET;
 923         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
 924         ssb_read32(dev->dev, SSB_TMSLOW);       /* flush */
 925         msleep(1);
 926         tmslow &= ~SSB_TMSLOW_FGC;
 927         ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
 928         ssb_read32(dev->dev, SSB_TMSLOW);       /* flush */
 929         msleep(1);
 930
 931         /* Turn Analog ON */
 932         b43_switch_analog(dev, 1);
 933
 934         macctl = b43_read32(dev, B43_MMIO_MACCTL);
 935         macctl &= ~B43_MACCTL_GMODE;
 936         if (flags & B43_TMSLOW_GMODE)
 937                 macctl |= B43_MACCTL_GMODE;
 938         macctl |= B43_MACCTL_IHR_ENABLED;
 939         b43_write32(dev, B43_MMIO_MACCTL, macctl);
 940 }
 941
 942 static void handle_irq_transmit_status(struct b43_wldev *dev)
 943 {
 944         u32 v0, v1;
 945         u16 tmp;
 946         struct b43_txstatus stat;
 947
 948         while (1) {
 949                 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
 950                 if (!(v0 & 0x00000001))
 951                         break;
 952                 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
 953
 954                 stat.cookie = (v0 >> 16);
 955                 stat.seq = (v1 & 0x0000FFFF);
 956                 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
 957                 tmp = (v0 & 0x0000FFFF);
 958                 stat.frame_count = ((tmp & 0xF000) >> 12);
 959                 stat.rts_count = ((tmp & 0x0F00) >> 8);
 960                 stat.supp_reason = ((tmp & 0x001C) >> 2);
 961                 stat.pm_indicated = !!(tmp & 0x0080);
 962                 stat.intermediate = !!(tmp & 0x0040);
 963                 stat.for_ampdu = !!(tmp & 0x0020);
 964                 stat.acked = !!(tmp & 0x0002);
 965
 966                 b43_handle_txstatus(dev, &stat);
 967         }
 968 }
 969
 970 static void drain_txstatus_queue(struct b43_wldev *dev)
 971 {
 972         u32 dummy;
 973
 974         if (dev->dev->id.revision < 5)
 975                 return;
 976         /* Read all entries from the microcode TXstatus FIFO
 977          * and throw them away.
 978          */
 979         while (1) {
 980                 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
 981                 if (!(dummy & 0x00000001))
 982                         break;
 983                 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
 984         }
 985 }
 986
 987 static u32 b43_jssi_read(struct b43_wldev *dev)
 988 {
 989         u32 val = 0;
 990
 991         val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
 992         val <<= 16;
 993         val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
 994
 995         return val;
 996 }
 997
 998 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
 999 {
1000         b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1001         b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1002 }
1003
1004 static void b43_generate_noise_sample(struct b43_wldev *dev)
1005 {
1006         b43_jssi_write(dev, 0x7F7F7F7F);
1007         b43_write32(dev, B43_MMIO_STATUS2_BITFIELD,
1008                     b43_read32(dev, B43_MMIO_STATUS2_BITFIELD)
1009                     | (1 << 4));
1010         B43_WARN_ON(dev->noisecalc.channel_at_start != dev->phy.channel);
1011 }
1012
1013 static void b43_calculate_link_quality(struct b43_wldev *dev)
1014 {
1015         /* Top half of Link Quality calculation. */
1016
1017         if (dev->noisecalc.calculation_running)
1018                 return;
1019         dev->noisecalc.channel_at_start = dev->phy.channel;
1020         dev->noisecalc.calculation_running = 1;
1021         dev->noisecalc.nr_samples = 0;
1022
1023         b43_generate_noise_sample(dev);
1024 }
1025
1026 static void handle_irq_noise(struct b43_wldev *dev)
1027 {
1028         struct b43_phy *phy = &dev->phy;
1029         u16 tmp;
1030         u8 noise[4];
1031         u8 i, j;
1032         s32 average;
1033
1034         /* Bottom half of Link Quality calculation. */
1035
1036         B43_WARN_ON(!dev->noisecalc.calculation_running);
1037         if (dev->noisecalc.channel_at_start != phy->channel)
1038                 goto drop_calculation;
1039         *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1040         if (noise[0] == 0x7F || noise[1] == 0x7F ||
1041             noise[2] == 0x7F || noise[3] == 0x7F)
1042                 goto generate_new;
1043
1044         /* Get the noise samples. */
1045         B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1046         i = dev->noisecalc.nr_samples;
1047         noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1048         noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1049         noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1050         noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1051         dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1052         dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1053         dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1054         dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1055         dev->noisecalc.nr_samples++;
1056         if (dev->noisecalc.nr_samples == 8) {
1057                 /* Calculate the Link Quality by the noise samples. */
1058                 average = 0;
1059                 for (i = 0; i < 8; i++) {
1060                         for (j = 0; j < 4; j++)
1061                                 average += dev->noisecalc.samples[i][j];
1062                 }
1063                 average /= (8 * 4);
1064                 average *= 125;
1065                 average += 64;
1066                 average /= 128;
1067                 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1068                 tmp = (tmp / 128) & 0x1F;
1069                 if (tmp >= 8)
1070                         average += 2;
1071                 else
1072                         average -= 25;
1073                 if (tmp == 8)
1074                         average -= 72;
1075                 else
1076                         average -= 48;
1077
1078                 dev->stats.link_noise = average;
1079               drop_calculation:
1080                 dev->noisecalc.calculation_running = 0;
1081                 return;
1082         }
1083       generate_new:
1084         b43_generate_noise_sample(dev);
1085 }
1086
1087 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1088 {
1089         if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
1090                 ///TODO: PS TBTT
1091         } else {
1092                 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1093                         b43_power_saving_ctl_bits(dev, 0);
1094         }
1095         dev->reg124_set_0x4 = 0;
1096         if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
1097                 dev->reg124_set_0x4 = 1;
1098 }
1099
1100 static void handle_irq_atim_end(struct b43_wldev *dev)
1101 {
1102         if (!dev->reg124_set_0x4 /*FIXME rename this variable */ )
1103                 return;
1104         b43_write32(dev, B43_MMIO_STATUS2_BITFIELD,
1105                     b43_read32(dev, B43_MMIO_STATUS2_BITFIELD)
1106                     | 0x4);
1107 }
1108
1109 static void handle_irq_pmq(struct b43_wldev *dev)
1110 {
1111         u32 tmp;
1112
1113         //TODO: AP mode.
1114
1115         while (1) {
1116                 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1117                 if (!(tmp & 0x00000008))
1118                         break;
1119         }
1120         /* 16bit write is odd, but correct. */
1121         b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1122 }
1123
1124 static void b43_write_template_common(struct b43_wldev *dev,
1125                                       const u8 * data, u16 size,
1126                                       u16 ram_offset,
1127                                       u16 shm_size_offset, u8 rate)
1128 {
1129         u32 i, tmp;
1130         struct b43_plcp_hdr4 plcp;
1131
1132         plcp.data = 0;
1133         b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1134         b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1135         ram_offset += sizeof(u32);
1136         /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1137          * So leave the first two bytes of the next write blank.
1138          */
1139         tmp = (u32) (data[0]) << 16;
1140         tmp |= (u32) (data[1]) << 24;
1141         b43_ram_write(dev, ram_offset, tmp);
1142         ram_offset += sizeof(u32);
1143         for (i = 2; i < size; i += sizeof(u32)) {
1144                 tmp = (u32) (data[i + 0]);
1145                 if (i + 1 < size)
1146                         tmp |= (u32) (data[i + 1]) << 8;
1147                 if (i + 2 < size)
1148                         tmp |= (u32) (data[i + 2]) << 16;
1149                 if (i + 3 < size)
1150                         tmp |= (u32) (data[i + 3]) << 24;
1151                 b43_ram_write(dev, ram_offset + i - 2, tmp);
1152         }
1153         b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1154                         size + sizeof(struct b43_plcp_hdr6));
1155 }
1156
1157 static void b43_write_beacon_template(struct b43_wldev *dev,
1158                                       u16 ram_offset,
1159                                       u16 shm_size_offset, u8 rate)
1160 {
1161         int len;
1162         const u8 *data;
1163
1164         B43_WARN_ON(!dev->cached_beacon);
1165         len = min((size_t) dev->cached_beacon->len,
1166                   0x200 - sizeof(struct b43_plcp_hdr6));
1167         data = (const u8 *)(dev->cached_beacon->data);
1168         b43_write_template_common(dev, data,
1169                                   len, ram_offset, shm_size_offset, rate);
1170 }
1171
1172 static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
1173                                       u16 shm_offset, u16 size, u8 rate)
1174 {
1175         struct b43_plcp_hdr4 plcp;
1176         u32 tmp;
1177         __le16 dur;
1178
1179         plcp.data = 0;
1180         b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1181         dur = ieee80211_generic_frame_duration(dev->wl->hw,
1182                                                dev->wl->if_id, size,
1183                                                B43_RATE_TO_BASE100KBPS(rate));
1184         /* Write PLCP in two parts and timing for packet transfer */
1185         tmp = le32_to_cpu(plcp.data);
1186         b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF);
1187         b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16);
1188         b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur));
1189 }
1190
1191 /* Instead of using custom probe response template, this function
1192  * just patches custom beacon template by:
1193  * 1) Changing packet type
1194  * 2) Patching duration field
1195  * 3) Stripping TIM
1196  */
1197 static u8 *b43_generate_probe_resp(struct b43_wldev *dev,
1198                                    u16 * dest_size, u8 rate)
1199 {
1200         const u8 *src_data;
1201         u8 *dest_data;
1202         u16 src_size, elem_size, src_pos, dest_pos;
1203         __le16 dur;
1204         struct ieee80211_hdr *hdr;
1205
1206         B43_WARN_ON(!dev->cached_beacon);
1207         src_size = dev->cached_beacon->len;
1208         src_data = (const u8 *)dev->cached_beacon->data;
1209
1210         if (unlikely(src_size < 0x24)) {
1211                 b43dbg(dev->wl, "b43_generate_probe_resp: " "invalid beacon\n");
1212                 return NULL;
1213         }
1214
1215         dest_data = kmalloc(src_size, GFP_ATOMIC);
1216         if (unlikely(!dest_data))
1217                 return NULL;
1218
1219         /* 0x24 is offset of first variable-len Information-Element
1220          * in beacon frame.
1221          */
1222         memcpy(dest_data, src_data, 0x24);
1223         src_pos = dest_pos = 0x24;
1224         for (; src_pos < src_size - 2; src_pos += elem_size) {
1225                 elem_size = src_data[src_pos + 1] + 2;
1226                 if (src_data[src_pos] != 0x05) {        /* TIM */
1227                         memcpy(dest_data + dest_pos, src_data + src_pos,
1228                                elem_size);
1229                         dest_pos += elem_size;
1230                 }
1231         }
1232         *dest_size = dest_pos;
1233         hdr = (struct ieee80211_hdr *)dest_data;
1234
1235         /* Set the frame control. */
1236         hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1237                                          IEEE80211_STYPE_PROBE_RESP);
1238         dur = ieee80211_generic_frame_duration(dev->wl->hw,
1239                                                dev->wl->if_id, *dest_size,
1240                                                B43_RATE_TO_BASE100KBPS(rate));
1241         hdr->duration_id = dur;
1242
1243         return dest_data;
1244 }
1245
1246 static void b43_write_probe_resp_template(struct b43_wldev *dev,
1247                                           u16 ram_offset,
1248                                           u16 shm_size_offset, u8 rate)
1249 {
1250         u8 *probe_resp_data;
1251         u16 size;
1252
1253         B43_WARN_ON(!dev->cached_beacon);
1254         size = dev->cached_beacon->len;
1255         probe_resp_data = b43_generate_probe_resp(dev, &size, rate);
1256         if (unlikely(!probe_resp_data))
1257                 return;
1258
1259         /* Looks like PLCP headers plus packet timings are stored for
1260          * all possible basic rates
1261          */
1262         b43_write_probe_resp_plcp(dev, 0x31A, size, B43_CCK_RATE_1MB);
1263         b43_write_probe_resp_plcp(dev, 0x32C, size, B43_CCK_RATE_2MB);
1264         b43_write_probe_resp_plcp(dev, 0x33E, size, B43_CCK_RATE_5MB);
1265         b43_write_probe_resp_plcp(dev, 0x350, size, B43_CCK_RATE_11MB);
1266
1267         size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6));
1268         b43_write_template_common(dev, probe_resp_data,
1269                                   size, ram_offset, shm_size_offset, rate);
1270         kfree(probe_resp_data);
1271 }
1272
1273 static int b43_refresh_cached_beacon(struct b43_wldev *dev,
1274                                      struct sk_buff *beacon)
1275 {
1276         if (dev->cached_beacon)
1277                 kfree_skb(dev->cached_beacon);
1278         dev->cached_beacon = beacon;
1279
1280         return 0;
1281 }
1282
1283 static void b43_update_templates(struct b43_wldev *dev)
1284 {
1285         u32 status;
1286
1287         B43_WARN_ON(!dev->cached_beacon);
1288
1289         b43_write_beacon_template(dev, 0x68, 0x18, B43_CCK_RATE_1MB);
1290         b43_write_beacon_template(dev, 0x468, 0x1A, B43_CCK_RATE_1MB);
1291         b43_write_probe_resp_template(dev, 0x268, 0x4A, B43_CCK_RATE_11MB);
1292
1293         status = b43_read32(dev, B43_MMIO_STATUS2_BITFIELD);
1294         status |= 0x03;
1295         b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, status);
1296 }
1297
1298 static void b43_refresh_templates(struct b43_wldev *dev, struct sk_buff *beacon)
1299 {
1300         int err;
1301
1302         err = b43_refresh_cached_beacon(dev, beacon);
1303         if (unlikely(err))
1304                 return;
1305         b43_update_templates(dev);
1306 }
1307
1308 static void b43_set_ssid(struct b43_wldev *dev, const u8 * ssid, u8 ssid_len)
1309 {
1310         u32 tmp;
1311         u16 i, len;
1312
1313         len = min((u16) ssid_len, (u16) 0x100);
1314         for (i = 0; i < len; i += sizeof(u32)) {
1315                 tmp = (u32) (ssid[i + 0]);
1316                 if (i + 1 < len)
1317                         tmp |= (u32) (ssid[i + 1]) << 8;
1318                 if (i + 2 < len)
1319                         tmp |= (u32) (ssid[i + 2]) << 16;
1320                 if (i + 3 < len)
1321                         tmp |= (u32) (ssid[i + 3]) << 24;
1322                 b43_shm_write32(dev, B43_SHM_SHARED, 0x380 + i, tmp);
1323         }
1324         b43_shm_write16(dev, B43_SHM_SHARED, 0x48, len);
1325 }
1326
1327 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1328 {
1329         b43_time_lock(dev);
1330         if (dev->dev->id.revision >= 3) {
1331                 b43_write32(dev, 0x188, (beacon_int << 16));
1332         } else {
1333                 b43_write16(dev, 0x606, (beacon_int >> 6));
1334                 b43_write16(dev, 0x610, beacon_int);
1335         }
1336         b43_time_unlock(dev);
1337 }
1338
1339 static void handle_irq_beacon(struct b43_wldev *dev)
1340 {
1341         u32 status;
1342
1343         if (!b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP))
1344                 return;
1345
1346         dev->irq_savedstate &= ~B43_IRQ_BEACON;
1347         status = b43_read32(dev, B43_MMIO_STATUS2_BITFIELD);
1348
1349         if (!dev->cached_beacon || ((status & 0x1) && (status & 0x2))) {
1350                 /* ACK beacon IRQ. */
1351                 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1352                 dev->irq_savedstate |= B43_IRQ_BEACON;
1353                 if (dev->cached_beacon)
1354                         kfree_skb(dev->cached_beacon);
1355                 dev->cached_beacon = NULL;
1356                 return;
1357         }
1358         if (!(status & 0x1)) {
1359                 b43_write_beacon_template(dev, 0x68, 0x18, B43_CCK_RATE_1MB);
1360                 status |= 0x1;
1361                 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, status);
1362         }
1363         if (!(status & 0x2)) {
1364                 b43_write_beacon_template(dev, 0x468, 0x1A, B43_CCK_RATE_1MB);
1365                 status |= 0x2;
1366                 b43_write32(dev, B43_MMIO_STATUS2_BITFIELD, status);
1367         }
1368 }
1369
1370 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1371 {
1372         //TODO
1373 }
1374
1375 /* Interrupt handler bottom-half */
1376 static void b43_interrupt_tasklet(struct b43_wldev *dev)
1377 {
1378         u32 reason;
1379         u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1380         u32 merged_dma_reason = 0;
1381         int i;
1382         unsigned long flags;
1383
1384         spin_lock_irqsave(&dev->wl->irq_lock, flags);
1385
1386         B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
1387
1388         reason = dev->irq_reason;
1389         for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1390                 dma_reason[i] = dev->dma_reason[i];
1391                 merged_dma_reason |= dma_reason[i];
1392         }
1393
1394         if (unlikely(reason & B43_IRQ_MAC_TXERR))
1395                 b43err(dev->wl, "MAC transmission error\n");
1396
1397         if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1398                 b43err(dev->wl, "PHY transmission error\n");
1399                 rmb();
1400                 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1401                         atomic_set(&dev->phy.txerr_cnt,
1402                                    B43_PHY_TX_BADNESS_LIMIT);
1403                         b43err(dev->wl, "Too many PHY TX errors, "
1404                                         "restarting the controller\n");
1405                         b43_controller_restart(dev, "PHY TX errors");
1406                 }
1407         }
1408
1409         if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1410                                           B43_DMAIRQ_NONFATALMASK))) {
1411                 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1412                         b43err(dev->wl, "Fatal DMA error: "
1413                                "0x%08X, 0x%08X, 0x%08X, "
1414                                "0x%08X, 0x%08X, 0x%08X\n",
1415                                dma_reason[0], dma_reason[1],
1416                                dma_reason[2], dma_reason[3],
1417                                dma_reason[4], dma_reason[5]);
1418                         b43_controller_restart(dev, "DMA error");
1419                         mmiowb();
1420                         spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1421                         return;
1422                 }
1423                 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1424                         b43err(dev->wl, "DMA error: "
1425                                "0x%08X, 0x%08X, 0x%08X, "
1426                                "0x%08X, 0x%08X, 0x%08X\n",
1427                                dma_reason[0], dma_reason[1],
1428                                dma_reason[2], dma_reason[3],
1429                                dma_reason[4], dma_reason[5]);
1430                 }
1431         }
1432
1433         if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1434                 handle_irq_ucode_debug(dev);
1435         if (reason & B43_IRQ_TBTT_INDI)
1436                 handle_irq_tbtt_indication(dev);
1437         if (reason & B43_IRQ_ATIM_END)
1438                 handle_irq_atim_end(dev);
1439         if (reason & B43_IRQ_BEACON)
1440                 handle_irq_beacon(dev);
1441         if (reason & B43_IRQ_PMQ)
1442                 handle_irq_pmq(dev);
1443         if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1444                 ;/* TODO */
1445         if (reason & B43_IRQ_NOISESAMPLE_OK)
1446                 handle_irq_noise(dev);
1447
1448         /* Check the DMA reason registers for received data. */
1449         if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1450                 if (b43_using_pio(dev))
1451                         b43_pio_rx(dev->pio.queue0);
1452                 else
1453                         b43_dma_rx(dev->dma.rx_ring0);
1454         }
1455         B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1456         B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1457         if (dma_reason[3] & B43_DMAIRQ_RX_DONE) {
1458                 if (b43_using_pio(dev))
1459                         b43_pio_rx(dev->pio.queue3);
1460                 else
1461                         b43_dma_rx(dev->dma.rx_ring3);
1462         }
1463         B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1464         B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1465
1466         if (reason & B43_IRQ_TX_OK)
1467                 handle_irq_transmit_status(dev);
1468
1469         b43_interrupt_enable(dev, dev->irq_savedstate);
1470         mmiowb();
1471         spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1472 }
1473
1474 static void pio_irq_workaround(struct b43_wldev *dev, u16 base, int queueidx)
1475 {
1476         u16 rxctl;
1477
1478         rxctl = b43_read16(dev, base + B43_PIO_RXCTL);
1479         if (rxctl & B43_PIO_RXCTL_DATAAVAILABLE)
1480                 dev->dma_reason[queueidx] |= B43_DMAIRQ_RX_DONE;
1481         else
1482                 dev->dma_reason[queueidx] &= ~B43_DMAIRQ_RX_DONE;
1483 }
1484
1485 static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
1486 {
1487         if (b43_using_pio(dev) &&
1488             (dev->dev->id.revision < 3) &&
1489             (!(reason & B43_IRQ_PIO_WORKAROUND))) {
1490                 /* Apply a PIO specific workaround to the dma_reasons */
1491                 pio_irq_workaround(dev, B43_MMIO_PIO1_BASE, 0);
1492                 pio_irq_workaround(dev, B43_MMIO_PIO2_BASE, 1);
1493                 pio_irq_workaround(dev, B43_MMIO_PIO3_BASE, 2);
1494                 pio_irq_workaround(dev, B43_MMIO_PIO4_BASE, 3);
1495         }
1496
1497         b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1498
1499         b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1500         b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1501         b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1502         b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1503         b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1504         b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1505 }
1506
1507 /* Interrupt handler top-half */
1508 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1509 {
1510         irqreturn_t ret = IRQ_NONE;
1511         struct b43_wldev *dev = dev_id;
1512         u32 reason;
1513
1514         if (!dev)
1515                 return IRQ_NONE;
1516
1517         spin_lock(&dev->wl->irq_lock);
1518
1519         if (b43_status(dev) < B43_STAT_STARTED)
1520                 goto out;
1521         reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1522         if (reason == 0xffffffff)       /* shared IRQ */
1523                 goto out;
1524         ret = IRQ_HANDLED;
1525         reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1526         if (!reason)
1527                 goto out;
1528
1529         dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1530             & 0x0001DC00;
1531         dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1532             & 0x0000DC00;
1533         dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1534             & 0x0000DC00;
1535         dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1536             & 0x0001DC00;
1537         dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1538             & 0x0000DC00;
1539         dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1540             & 0x0000DC00;
1541
1542         b43_interrupt_ack(dev, reason);
1543         /* disable all IRQs. They are enabled again in the bottom half. */
1544         dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
1545         /* save the reason code and call our bottom half. */
1546         dev->irq_reason = reason;
1547         tasklet_schedule(&dev->isr_tasklet);
1548       out:
1549         mmiowb();
1550         spin_unlock(&dev->wl->irq_lock);
1551
1552         return ret;
1553 }
1554
1555 static void b43_release_firmware(struct b43_wldev *dev)
1556 {
1557         release_firmware(dev->fw.ucode);
1558         dev->fw.ucode = NULL;
1559         release_firmware(dev->fw.pcm);
1560         dev->fw.pcm = NULL;
1561         release_firmware(dev->fw.initvals);
1562         dev->fw.initvals = NULL;
1563         release_firmware(dev->fw.initvals_band);
1564         dev->fw.initvals_band = NULL;
1565 }
1566
1567 static void b43_print_fw_helptext(struct b43_wl *wl)
1568 {
1569         b43err(wl, "You must go to "
1570                "http://linuxwireless.org/en/users/Drivers/b43#devicefirmware "
1571                "and download the correct firmware (version 4).\n");
1572 }
1573
1574 static int do_request_fw(struct b43_wldev *dev,
1575                          const char *name,
1576                          const struct firmware **fw)
1577 {
1578         char path[sizeof(modparam_fwpostfix) + 32];
1579         struct b43_fw_header *hdr;
1580         u32 size;
1581         int err;
1582
1583         if (!name)
1584                 return 0;
1585
1586         snprintf(path, ARRAY_SIZE(path),
1587                  "b43%s/%s.fw",
1588                  modparam_fwpostfix, name);
1589         err = request_firmware(fw, path, dev->dev->dev);
1590         if (err) {
1591                 b43err(dev->wl, "Firmware file \"%s\" not found "
1592                        "or load failed.\n", path);
1593                 return err;
1594         }
1595         if ((*fw)->size < sizeof(struct b43_fw_header))
1596                 goto err_format;
1597         hdr = (struct b43_fw_header *)((*fw)->data);
1598         switch (hdr->type) {
1599         case B43_FW_TYPE_UCODE:
1600         case B43_FW_TYPE_PCM:
1601                 size = be32_to_cpu(hdr->size);
1602                 if (size != (*fw)->size - sizeof(struct b43_fw_header))
1603                         goto err_format;
1604                 /* fallthrough */
1605         case B43_FW_TYPE_IV:
1606                 if (hdr->ver != 1)
1607                         goto err_format;
1608                 break;
1609         default:
1610                 goto err_format;
1611         }
1612
1613         return err;
1614
1615 err_format:
1616         b43err(dev->wl, "Firmware file \"%s\" format error.\n", path);
1617         return -EPROTO;
1618 }
1619
1620 static int b43_request_firmware(struct b43_wldev *dev)
1621 {
1622         struct b43_firmware *fw = &dev->fw;
1623         const u8 rev = dev->dev->id.revision;
1624         const char *filename;
1625         u32 tmshigh;
1626         int err;
1627
1628         tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
1629         if (!fw->ucode) {
1630                 if ((rev >= 5) && (rev <= 10))
1631                         filename = "ucode5";
1632                 else if ((rev >= 11) && (rev <= 12))
1633                         filename = "ucode11";
1634                 else if (rev >= 13)
1635                         filename = "ucode13";
1636                 else
1637                         goto err_no_ucode;
1638                 err = do_request_fw(dev, filename, &fw->ucode);
1639                 if (err)
1640                         goto err_load;
1641         }
1642         if (!fw->pcm) {
1643                 if ((rev >= 5) && (rev <= 10))
1644                         filename = "pcm5";
1645                 else if (rev >= 11)
1646                         filename = NULL;
1647                 else
1648                         goto err_no_pcm;
1649                 err = do_request_fw(dev, filename, &fw->pcm);
1650                 if (err)
1651                         goto err_load;
1652         }
1653         if (!fw->initvals) {
1654                 switch (dev->phy.type) {
1655                 case B43_PHYTYPE_A:
1656                         if ((rev >= 5) && (rev <= 10)) {
1657                                 if (tmshigh & B43_TMSHIGH_GPHY)
1658                                         filename = "a0g1initvals5";
1659                                 else
1660                                         filename = "a0g0initvals5";
1661                         } else
1662                                 goto err_no_initvals;
1663                         break;
1664                 case B43_PHYTYPE_G:
1665                         if ((rev >= 5) && (rev <= 10))
1666                                 filename = "b0g0initvals5";
1667                         else if (rev >= 13)
1668                                 filename = "lp0initvals13";
1669                         else
1670                                 goto err_no_initvals;
1671                         break;
1672                 default:
1673                         goto err_no_initvals;
1674                 }
1675                 err = do_request_fw(dev, filename, &fw->initvals);
1676                 if (err)
1677                         goto err_load;
1678         }
1679         if (!fw->initvals_band) {
1680                 switch (dev->phy.type) {
1681                 case B43_PHYTYPE_A:
1682                         if ((rev >= 5) && (rev <= 10)) {
1683                                 if (tmshigh & B43_TMSHIGH_GPHY)
1684                                         filename = "a0g1bsinitvals5";
1685                                 else
1686                                         filename = "a0g0bsinitvals5";
1687                         } else if (rev >= 11)
1688                                 filename = NULL;
1689                         else
1690                                 goto err_no_initvals;
1691                         break;
1692                 case B43_PHYTYPE_G:
1693                         if ((rev >= 5) && (rev <= 10))
1694                                 filename = "b0g0bsinitvals5";
1695                         else if (rev >= 11)
1696                                 filename = NULL;
1697                         else
1698                                 goto err_no_initvals;
1699                         break;
1700                 default:
1701                         goto err_no_initvals;
1702                 }
1703                 err = do_request_fw(dev, filename, &fw->initvals_band);
1704                 if (err)
1705                         goto err_load;
1706         }
1707
1708         return 0;
1709
1710 err_load:
1711         b43_print_fw_helptext(dev->wl);
1712         goto error;
1713
1714 err_no_ucode:
1715         err = -ENODEV;
1716         b43err(dev->wl, "No microcode available for core rev %u\n", rev);
1717         goto error;
1718
1719 err_no_pcm:
1720         err = -ENODEV;
1721         b43err(dev->wl, "No PCM available for core rev %u\n", rev);
1722         goto error;
1723
1724 err_no_initvals:
1725         err = -ENODEV;
1726         b43err(dev->wl, "No Initial Values firmware file for PHY %u, "
1727                "core rev %u\n", dev->phy.type, rev);
1728         goto error;
1729
1730 error:
1731         b43_release_firmware(dev);
1732         return err;
1733 }
1734
1735 static int b43_upload_microcode(struct b43_wldev *dev)
1736 {
1737         const size_t hdr_len = sizeof(struct b43_fw_header);
1738         const __be32 *data;
1739         unsigned int i, len;
1740         u16 fwrev, fwpatch, fwdate, fwtime;
1741         u32 tmp;
1742         int err = 0;
1743
1744         /* Upload Microcode. */
1745         data = (__be32 *) (dev->fw.ucode->data + hdr_len);
1746         len = (dev->fw.ucode->size - hdr_len) / sizeof(__be32);
1747         b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
1748         for (i = 0; i < len; i++) {
1749                 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1750                 udelay(10);
1751         }
1752
1753         if (dev->fw.pcm) {
1754                 /* Upload PCM data. */
1755                 data = (__be32 *) (dev->fw.pcm->data + hdr_len);
1756                 len = (dev->fw.pcm->size - hdr_len) / sizeof(__be32);
1757                 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
1758                 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
1759                 /* No need for autoinc bit in SHM_HW */
1760                 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
1761                 for (i = 0; i < len; i++) {
1762                         b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1763                         udelay(10);
1764                 }
1765         }
1766
1767         b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1768         b43_write32(dev, B43_MMIO_MACCTL,
1769                     B43_MACCTL_PSM_RUN |
1770                     B43_MACCTL_IHR_ENABLED | B43_MACCTL_INFRA);
1771
1772         /* Wait for the microcode to load and respond */
1773         i = 0;
1774         while (1) {
1775                 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1776                 if (tmp == B43_IRQ_MAC_SUSPENDED)
1777                         break;
1778                 i++;
1779                 if (i >= 50) {
1780                         b43err(dev->wl, "Microcode not responding\n");
1781                         b43_print_fw_helptext(dev->wl);
1782                         err = -ENODEV;
1783                         goto out;
1784                 }
1785                 udelay(10);
1786         }
1787         b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);       /* dummy read */
1788
1789         /* Get and check the revisions. */
1790         fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
1791         fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
1792         fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
1793         fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
1794
1795         if (fwrev <= 0x128) {
1796                 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
1797                        "binary drivers older than version 4.x is unsupported. "
1798                        "You must upgrade your firmware files.\n");
1799                 b43_print_fw_helptext(dev->wl);
1800                 b43_write32(dev, B43_MMIO_MACCTL, 0);
1801                 err = -EOPNOTSUPP;
1802                 goto out;
1803         }
1804         b43dbg(dev->wl, "Loading firmware version %u.%u "
1805                "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
1806                fwrev, fwpatch,
1807                (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
1808                (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
1809
1810         dev->fw.rev = fwrev;
1811         dev->fw.patch = fwpatch;
1812
1813       out:
1814         return err;
1815 }
1816
1817 static int b43_write_initvals(struct b43_wldev *dev,
1818                               const struct b43_iv *ivals,
1819                               size_t count,
1820                               size_t array_size)
1821 {
1822         const struct b43_iv *iv;
1823         u16 offset;
1824         size_t i;
1825         bool bit32;
1826
1827         BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
1828         iv = ivals;
1829         for (i = 0; i < count; i++) {
1830                 if (array_size < sizeof(iv->offset_size))
1831                         goto err_format;
1832                 array_size -= sizeof(iv->offset_size);
1833                 offset = be16_to_cpu(iv->offset_size);
1834                 bit32 = !!(offset & B43_IV_32BIT);
1835                 offset &= B43_IV_OFFSET_MASK;
1836                 if (offset >= 0x1000)
1837                         goto err_format;
1838                 if (bit32) {
1839                         u32 value;
1840
1841                         if (array_size < sizeof(iv->data.d32))
1842                                 goto err_format;
1843                         array_size -= sizeof(iv->data.d32);
1844
1845                         value = be32_to_cpu(get_unaligned(&iv->data.d32));
1846                         b43_write32(dev, offset, value);
1847
1848                         iv = (const struct b43_iv *)((const uint8_t *)iv +
1849                                                         sizeof(__be16) +
1850                                                         sizeof(__be32));
1851                 } else {
1852                         u16 value;
1853
1854                         if (array_size < sizeof(iv->data.d16))
1855                                 goto err_format;
1856                         array_size -= sizeof(iv->data.d16);
1857
1858                         value = be16_to_cpu(iv->data.d16);
1859                         b43_write16(dev, offset, value);
1860
1861                         iv = (const struct b43_iv *)((const uint8_t *)iv +
1862                                                         sizeof(__be16) +
1863                                                         sizeof(__be16));
1864                 }
1865         }
1866         if (array_size)
1867                 goto err_format;
1868
1869         return 0;
1870
1871 err_format:
1872         b43err(dev->wl, "Initial Values Firmware file-format error.\n");
1873         b43_print_fw_helptext(dev->wl);
1874
1875         return -EPROTO;
1876 }
1877
1878 static int b43_upload_initvals(struct b43_wldev *dev)
1879 {
1880         const size_t hdr_len = sizeof(struct b43_fw_header);
1881         const struct b43_fw_header *hdr;
1882         struct b43_firmware *fw = &dev->fw;
1883         const struct b43_iv *ivals;
1884         size_t count;
1885         int err;
1886
1887         hdr = (const struct b43_fw_header *)(fw->initvals->data);
1888         ivals = (const struct b43_iv *)(fw->initvals->data + hdr_len);
1889         count = be32_to_cpu(hdr->size);
1890         err = b43_write_initvals(dev, ivals, count,
1891                                  fw->initvals->size - hdr_len);
1892         if (err)
1893                 goto out;
1894         if (fw->initvals_band) {
1895                 hdr = (const struct b43_fw_header *)(fw->initvals_band->data);
1896                 ivals = (const struct b43_iv *)(fw->initvals_band->data + hdr_len);
1897                 count = be32_to_cpu(hdr->size);
1898                 err = b43_write_initvals(dev, ivals, count,
1899                                          fw->initvals_band->size - hdr_len);
1900                 if (err)
1901                         goto out;
1902         }
1903 out:
1904
1905         return err;
1906 }
1907
1908 /* Initialize the GPIOs
1909  * http://bcm-specs.sipsolutions.net/GPIO
1910  */
1911 static int b43_gpio_init(struct b43_wldev *dev)
1912 {
1913         struct ssb_bus *bus = dev->dev->bus;
1914         struct ssb_device *gpiodev, *pcidev = NULL;
1915         u32 mask, set;
1916
1917         b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
1918                     & ~B43_MACCTL_GPOUTSMSK);
1919
1920         b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
1921                     | 0x000F);
1922
1923         mask = 0x0000001F;
1924         set = 0x0000000F;
1925         if (dev->dev->bus->chip_id == 0x4301) {
1926                 mask |= 0x0060;
1927                 set |= 0x0060;
1928         }
1929         if (0 /* FIXME: conditional unknown */ ) {
1930                 b43_write16(dev, B43_MMIO_GPIO_MASK,
1931                             b43_read16(dev, B43_MMIO_GPIO_MASK)
1932                             | 0x0100);
1933                 mask |= 0x0180;
1934                 set |= 0x0180;
1935         }
1936         if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
1937                 b43_write16(dev, B43_MMIO_GPIO_MASK,
1938                             b43_read16(dev, B43_MMIO_GPIO_MASK)
1939                             | 0x0200);
1940                 mask |= 0x0200;
1941                 set |= 0x0200;
1942         }
1943         if (dev->dev->id.revision >= 2)
1944                 mask |= 0x0010; /* FIXME: This is redundant. */
1945
1946 #ifdef CONFIG_SSB_DRIVER_PCICORE
1947         pcidev = bus->pcicore.dev;
1948 #endif
1949         gpiodev = bus->chipco.dev ? : pcidev;
1950         if (!gpiodev)
1951                 return 0;
1952         ssb_write32(gpiodev, B43_GPIO_CONTROL,
1953                     (ssb_read32(gpiodev, B43_GPIO_CONTROL)
1954                      & mask) | set);
1955
1956         return 0;
1957 }
1958
1959 /* Turn off all GPIO stuff. Call this on module unload, for example. */
1960 static void b43_gpio_cleanup(struct b43_wldev *dev)
1961 {
1962         struct ssb_bus *bus = dev->dev->bus;
1963         struct ssb_device *gpiodev, *pcidev = NULL;
1964
1965 #ifdef CONFIG_SSB_DRIVER_PCICORE
1966         pcidev = bus->pcicore.dev;
1967 #endif
1968         gpiodev = bus->chipco.dev ? : pcidev;
1969         if (!gpiodev)
1970                 return;
1971         ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
1972 }
1973
1974 /* http://bcm-specs.sipsolutions.net/EnableMac */
1975 void b43_mac_enable(struct b43_wldev *dev)
1976 {
1977         dev->mac_suspended--;
1978         B43_WARN_ON(dev->mac_suspended < 0);
1979         B43_WARN_ON(irqs_disabled());
1980         if (dev->mac_suspended == 0) {
1981                 b43_write32(dev, B43_MMIO_MACCTL,
1982                             b43_read32(dev, B43_MMIO_MACCTL)
1983                             | B43_MACCTL_ENABLED);
1984                 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
1985                             B43_IRQ_MAC_SUSPENDED);
1986                 /* Commit writes */
1987                 b43_read32(dev, B43_MMIO_MACCTL);
1988                 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1989                 b43_power_saving_ctl_bits(dev, 0);
1990
1991                 /* Re-enable IRQs. */
1992                 spin_lock_irq(&dev->wl->irq_lock);
1993                 b43_interrupt_enable(dev, dev->irq_savedstate);
1994                 spin_unlock_irq(&dev->wl->irq_lock);
1995         }
1996 }
1997
1998 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
1999 void b43_mac_suspend(struct b43_wldev *dev)
2000 {
2001         int i;
2002         u32 tmp;
2003
2004         might_sleep();
2005         B43_WARN_ON(irqs_disabled());
2006         B43_WARN_ON(dev->mac_suspended < 0);
2007
2008         if (dev->mac_suspended == 0) {
2009                 /* Mask IRQs before suspending MAC. Otherwise
2010                  * the MAC stays busy and won't suspend. */
2011                 spin_lock_irq(&dev->wl->irq_lock);
2012                 tmp = b43_interrupt_disable(dev, B43_IRQ_ALL);
2013                 spin_unlock_irq(&dev->wl->irq_lock);
2014                 b43_synchronize_irq(dev);
2015                 dev->irq_savedstate = tmp;
2016
2017                 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2018                 b43_write32(dev, B43_MMIO_MACCTL,
2019                             b43_read32(dev, B43_MMIO_MACCTL)
2020                             & ~B43_MACCTL_ENABLED);
2021                 /* force pci to flush the write */
2022                 b43_read32(dev, B43_MMIO_MACCTL);
2023                 for (i = 40; i; i--) {
2024                         tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2025                         if (tmp & B43_IRQ_MAC_SUSPENDED)
2026                                 goto out;
2027                         msleep(1);
2028                 }
2029                 b43err(dev->wl, "MAC suspend failed\n");
2030         }
2031 out:
2032         dev->mac_suspended++;
2033 }
2034
2035 static void b43_adjust_opmode(struct b43_wldev *dev)
2036 {
2037         struct b43_wl *wl = dev->wl;
2038         u32 ctl;
2039         u16 cfp_pretbtt;
2040
2041         ctl = b43_read32(dev, B43_MMIO_MACCTL);
2042         /* Reset status to STA infrastructure mode. */
2043         ctl &= ~B43_MACCTL_AP;
2044         ctl &= ~B43_MACCTL_KEEP_CTL;
2045         ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2046         ctl &= ~B43_MACCTL_KEEP_BAD;
2047         ctl &= ~B43_MACCTL_PROMISC;
2048         ctl &= ~B43_MACCTL_BEACPROMISC;
2049         ctl |= B43_MACCTL_INFRA;
2050
2051         if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2052                 ctl |= B43_MACCTL_AP;
2053         else if (b43_is_mode(wl, IEEE80211_IF_TYPE_IBSS))
2054                 ctl &= ~B43_MACCTL_INFRA;
2055
2056         if (wl->filter_flags & FIF_CONTROL)
2057                 ctl |= B43_MACCTL_KEEP_CTL;
2058         if (wl->filter_flags & FIF_FCSFAIL)
2059                 ctl |= B43_MACCTL_KEEP_BAD;
2060         if (wl->filter_flags & FIF_PLCPFAIL)
2061                 ctl |= B43_MACCTL_KEEP_BADPLCP;
2062         if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2063                 ctl |= B43_MACCTL_PROMISC;
2064         if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2065                 ctl |= B43_MACCTL_BEACPROMISC;
2066
2067         /* Workaround: On old hardware the HW-MAC-address-filter
2068          * doesn't work properly, so always run promisc in filter
2069          * it in software. */
2070         if (dev->dev->id.revision <= 4)
2071                 ctl |= B43_MACCTL_PROMISC;
2072
2073         b43_write32(dev, B43_MMIO_MACCTL, ctl);
2074
2075         cfp_pretbtt = 2;
2076         if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2077                 if (dev->dev->bus->chip_id == 0x4306 &&
2078                     dev->dev->bus->chip_rev == 3)
2079                         cfp_pretbtt = 100;
2080                 else
2081                         cfp_pretbtt = 50;
2082         }
2083         b43_write16(dev, 0x612, cfp_pretbtt);
2084 }
2085
2086 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2087 {
2088         u16 offset;
2089
2090         if (is_ofdm) {
2091                 offset = 0x480;
2092                 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2093         } else {
2094                 offset = 0x4C0;
2095                 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2096         }
2097         b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2098                         b43_shm_read16(dev, B43_SHM_SHARED, offset));
2099 }
2100
2101 static void b43_rate_memory_init(struct b43_wldev *dev)
2102 {
2103         switch (dev->phy.type) {
2104         case B43_PHYTYPE_A:
2105         case B43_PHYTYPE_G:
2106                 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2107                 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2108                 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2109                 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2110                 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2111                 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2112                 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2113                 if (dev->phy.type == B43_PHYTYPE_A)
2114                         break;
2115                 /* fallthrough */
2116         case B43_PHYTYPE_B:
2117                 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2118                 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2119                 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2120                 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2121                 break;
2122         default:
2123                 B43_WARN_ON(1);
2124         }
2125 }
2126
2127 /* Set the TX-Antenna for management frames sent by firmware. */
2128 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2129 {
2130         u16 ant = 0;
2131         u16 tmp;
2132
2133         switch (antenna) {
2134         case B43_ANTENNA0:
2135                 ant |= B43_TX4_PHY_ANT0;
2136                 break;
2137         case B43_ANTENNA1:
2138                 ant |= B43_TX4_PHY_ANT1;
2139                 break;
2140         case B43_ANTENNA_AUTO:
2141                 ant |= B43_TX4_PHY_ANTLAST;
2142                 break;
2143         default:
2144                 B43_WARN_ON(1);
2145         }
2146
2147         /* FIXME We also need to set the other flags of the PHY control field somewhere. */
2148
2149         /* For Beacons */
2150         tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
2151         tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2152         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, tmp);
2153         /* For ACK/CTS */
2154         tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
2155         tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2156         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2157         /* For Probe Resposes */
2158         tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
2159         tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2160         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2161 }
2162
2163 /* This is the opposite of b43_chip_init() */
2164 static void b43_chip_exit(struct b43_wldev *dev)
2165 {
2166         b43_radio_turn_off(dev, 1);
2167         b43_gpio_cleanup(dev);
2168         /* firmware is released later */
2169 }
2170
2171 /* Initialize the chip
2172  * http://bcm-specs.sipsolutions.net/ChipInit
2173  */
2174 static int b43_chip_init(struct b43_wldev *dev)
2175 {
2176         struct b43_phy *phy = &dev->phy;
2177         int err, tmp;
2178         u32 value32;
2179         u16 value16;
2180
2181         b43_write32(dev, B43_MMIO_MACCTL,
2182                     B43_MACCTL_PSM_JMP0 | B43_MACCTL_IHR_ENABLED);
2183
2184         err = b43_request_firmware(dev);
2185         if (err)
2186                 goto out;
2187         err = b43_upload_microcode(dev);
2188         if (err)
2189                 goto out;       /* firmware is released later */
2190
2191         err = b43_gpio_init(dev);
2192         if (err)
2193                 goto out;       /* firmware is released later */
2194
2195         err = b43_upload_initvals(dev);
2196         if (err)
2197                 goto err_gpio_clean;
2198         b43_radio_turn_on(dev);
2199
2200         b43_write16(dev, 0x03E6, 0x0000);
2201         err = b43_phy_init(dev);
2202         if (err)
2203                 goto err_radio_off;
2204
2205         /* Select initial Interference Mitigation. */
2206         tmp = phy->interfmode;
2207         phy->interfmode = B43_INTERFMODE_NONE;
2208         b43_radio_set_interference_mitigation(dev, tmp);
2209
2210         b43_set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2211         b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2212
2213         if (phy->type == B43_PHYTYPE_B) {
2214                 value16 = b43_read16(dev, 0x005E);
2215                 value16 |= 0x0004;
2216                 b43_write16(dev, 0x005E, value16);
2217         }
2218         b43_write32(dev, 0x0100, 0x01000000);
2219         if (dev->dev->id.revision < 5)
2220                 b43_write32(dev, 0x010C, 0x01000000);
2221
2222         b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2223                     & ~B43_MACCTL_INFRA);
2224         b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2225                     | B43_MACCTL_INFRA);
2226
2227         if (b43_using_pio(dev)) {
2228                 b43_write32(dev, 0x0210, 0x00000100);
2229                 b43_write32(dev, 0x0230, 0x00000100);
2230                 b43_write32(dev, 0x0250, 0x00000100);
2231                 b43_write32(dev, 0x0270, 0x00000100);
2232                 b43_shm_write16(dev, B43_SHM_SHARED, 0x0034, 0x0000);
2233         }
2234
2235         /* Probe Response Timeout value */
2236         /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2237         b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2238
2239         /* Initially set the wireless operation mode. */
2240         b43_adjust_opmode(dev);
2241
2242         if (dev->dev->id.revision < 3) {
2243                 b43_write16(dev, 0x060E, 0x0000);
2244                 b43_write16(dev, 0x0610, 0x8000);
2245                 b43_write16(dev, 0x0604, 0x0000);
2246                 b43_write16(dev, 0x0606, 0x0200);
2247         } else {
2248                 b43_write32(dev, 0x0188, 0x80000000);
2249                 b43_write32(dev, 0x018C, 0x02000000);
2250         }
2251         b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2252         b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2253         b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2254         b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2255         b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2256         b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2257         b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2258
2259         value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2260         value32 |= 0x00100000;
2261         ssb_write32(dev->dev, SSB_TMSLOW, value32);
2262
2263         b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2264                     dev->dev->bus->chipco.fast_pwrup_delay);
2265
2266         /* OFDM address caching. */
2267         phy->ofdm_valid = 0;
2268
2269         /* PHY TX errors counter. */
2270         atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2271
2272         err = 0;
2273         b43dbg(dev->wl, "Chip initialized\n");
2274 out:
2275         return err;
2276
2277 err_radio_off:
2278         b43_radio_turn_off(dev, 1);
2279 err_gpio_clean:
2280         b43_gpio_cleanup(dev);
2281         return err;
2282 }
2283
2284 static void b43_periodic_every120sec(struct b43_wldev *dev)
2285 {
2286         struct b43_phy *phy = &dev->phy;
2287
2288         if (phy->type != B43_PHYTYPE_G || phy->rev < 2)
2289                 return;
2290
2291         b43_mac_suspend(dev);
2292         b43_lo_g_measure(dev);
2293         b43_mac_enable(dev);
2294         if (b43_has_hardware_pctl(phy))
2295                 b43_lo_g_ctl_mark_all_unused(dev);
2296 }
2297
2298 static void b43_periodic_every60sec(struct b43_wldev *dev)
2299 {
2300         struct b43_phy *phy = &dev->phy;
2301
2302         if (!b43_has_hardware_pctl(phy))
2303                 b43_lo_g_ctl_mark_all_unused(dev);
2304         if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI) {
2305                 b43_mac_suspend(dev);
2306                 b43_calc_nrssi_slope(dev);
2307                 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) {
2308                         u8 old_chan = phy->channel;
2309
2310                         /* VCO Calibration */
2311                         if (old_chan >= 8)
2312                                 b43_radio_selectchannel(dev, 1, 0);
2313                         else
2314                                 b43_radio_selectchannel(dev, 13, 0);
2315                         b43_radio_selectchannel(dev, old_chan, 0);
2316                 }
2317                 b43_mac_enable(dev);
2318         }
2319 }
2320
2321 static void b43_periodic_every30sec(struct b43_wldev *dev)
2322 {
2323         /* Update device statistics. */
2324         b43_calculate_link_quality(dev);
2325 }
2326
2327 static void b43_periodic_every15sec(struct b43_wldev *dev)
2328 {
2329         struct b43_phy *phy = &dev->phy;
2330
2331         if (phy->type == B43_PHYTYPE_G) {
2332                 //TODO: update_aci_moving_average
2333                 if (phy->aci_enable && phy->aci_wlan_automatic) {
2334                         b43_mac_suspend(dev);
2335                         if (!phy->aci_enable && 1 /*TODO: not scanning? */ ) {
2336                                 if (0 /*TODO: bunch of conditions */ ) {
2337                                         b43_radio_set_interference_mitigation
2338                                             (dev, B43_INTERFMODE_MANUALWLAN);
2339                                 }
2340                         } else if (1 /*TODO*/) {
2341                                 /*
2342                                    if ((aci_average > 1000) && !(b43_radio_aci_scan(dev))) {
2343                                    b43_radio_set_interference_mitigation(dev,
2344                                    B43_INTERFMODE_NONE);
2345                                    }
2346                                  */
2347                         }
2348                         b43_mac_enable(dev);
2349                 } else if (phy->interfmode == B43_INTERFMODE_NONWLAN &&
2350                            phy->rev == 1) {
2351                         //TODO: implement rev1 workaround
2352                 }
2353         }
2354         b43_phy_xmitpower(dev); //FIXME: unless scanning?
2355         //TODO for APHY (temperature?)
2356
2357         atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2358         wmb();
2359 }
2360
2361 static void do_periodic_work(struct b43_wldev *dev)
2362 {
2363         unsigned int state;
2364
2365         state = dev->periodic_state;
2366         if (state % 8 == 0)
2367                 b43_periodic_every120sec(dev);
2368         if (state % 4 == 0)
2369                 b43_periodic_every60sec(dev);
2370         if (state % 2 == 0)
2371                 b43_periodic_every30sec(dev);
2372         b43_periodic_every15sec(dev);
2373 }
2374
2375 /* Periodic work locking policy:
2376  *      The whole periodic work handler is protected by
2377  *      wl->mutex. If another lock is needed somewhere in the
2378  *      pwork callchain, it's aquired in-place, where it's needed.
2379  */
2380 static void b43_periodic_work_handler(struct work_struct *work)
2381 {
2382         struct b43_wldev *dev = container_of(work, struct b43_wldev,
2383                                              periodic_work.work);
2384         struct b43_wl *wl = dev->wl;
2385         unsigned long delay;
2386
2387         mutex_lock(&wl->mutex);
2388
2389         if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2390                 goto out;
2391         if (b43_debug(dev, B43_DBG_PWORK_STOP))
2392                 goto out_requeue;
2393
2394         do_periodic_work(dev);
2395
2396         dev->periodic_state++;
2397 out_requeue:
2398         if (b43_debug(dev, B43_DBG_PWORK_FAST))
2399                 delay = msecs_to_jiffies(50);
2400         else
2401                 delay = round_jiffies_relative(HZ * 15);
2402         queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
2403 out:
2404         mutex_unlock(&wl->mutex);
2405 }
2406
2407 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2408 {
2409         struct delayed_work *work = &dev->periodic_work;
2410
2411         dev->periodic_state = 0;
2412         INIT_DELAYED_WORK(work, b43_periodic_work_handler);
2413         queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2414 }
2415
2416 /* Validate access to the chip (SHM) */
2417 static int b43_validate_chipaccess(struct b43_wldev *dev)
2418 {
2419         u32 value;
2420         u32 shm_backup;
2421
2422         shm_backup = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2423         b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2424         if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
2425                 goto error;
2426         b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2427         if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2428                 goto error;
2429         b43_shm_write32(dev, B43_SHM_SHARED, 0, shm_backup);
2430
2431         value = b43_read32(dev, B43_MMIO_MACCTL);
2432         if ((value | B43_MACCTL_GMODE) !=
2433             (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
2434                 goto error;
2435
2436         value = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2437         if (value)
2438                 goto error;
2439
2440         return 0;
2441       error:
2442         b43err(dev->wl, "Failed to validate the chipaccess\n");
2443         return -ENODEV;
2444 }
2445
2446 static void b43_security_init(struct b43_wldev *dev)
2447 {
2448         dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2449         B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2450         dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
2451         /* KTP is a word address, but we address SHM bytewise.
2452          * So multiply by two.
2453          */
2454         dev->ktp *= 2;
2455         if (dev->dev->id.revision >= 5) {
2456                 /* Number of RCMTA address slots */
2457                 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8);
2458         }
2459         b43_clear_keys(dev);
2460 }
2461
2462 static int b43_rng_read(struct hwrng *rng, u32 * data)
2463 {
2464         struct b43_wl *wl = (struct b43_wl *)rng->priv;
2465         unsigned long flags;
2466
2467         /* Don't take wl->mutex here, as it could deadlock with
2468          * hwrng internal locking. It's not needed to take
2469          * wl->mutex here, anyway. */
2470
2471         spin_lock_irqsave(&wl->irq_lock, flags);
2472         *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
2473         spin_unlock_irqrestore(&wl->irq_lock, flags);
2474
2475         return (sizeof(u16));
2476 }
2477
2478 static void b43_rng_exit(struct b43_wl *wl)
2479 {
2480         if (wl->rng_initialized)
2481                 hwrng_unregister(&wl->rng);
2482 }
2483
2484 static int b43_rng_init(struct b43_wl *wl)
2485 {
2486         int err;
2487
2488         snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2489                  "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2490         wl->rng.name = wl->rng_name;
2491         wl->rng.data_read = b43_rng_read;
2492         wl->rng.priv = (unsigned long)wl;
2493         wl->rng_initialized = 1;
2494         err = hwrng_register(&wl->rng);
2495         if (err) {
2496                 wl->rng_initialized = 0;
2497                 b43err(wl, "Failed to register the random "
2498                        "number generator (%d)\n", err);
2499         }
2500
2501         return err;
2502 }
2503
2504 static int b43_op_tx(struct ieee80211_hw *hw,
2505                      struct sk_buff *skb,
2506                      struct ieee80211_tx_control *ctl)
2507 {
2508         struct b43_wl *wl = hw_to_b43_wl(hw);
2509         struct b43_wldev *dev = wl->current_dev;
2510         int err = -ENODEV;
2511         unsigned long flags;
2512
2513         if (unlikely(!dev))
2514                 goto out;
2515         if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2516                 goto out;
2517         /* DMA-TX is done without a global lock. */
2518         if (b43_using_pio(dev)) {
2519                 spin_lock_irqsave(&wl->irq_lock, flags);
2520                 err = b43_pio_tx(dev, skb, ctl);
2521                 spin_unlock_irqrestore(&wl->irq_lock, flags);
2522         } else
2523                 err = b43_dma_tx(dev, skb, ctl);
2524 out:
2525         if (unlikely(err))
2526                 return NETDEV_TX_BUSY;
2527         return NETDEV_TX_OK;
2528 }
2529
2530 static int b43_op_conf_tx(struct ieee80211_hw *hw,
2531                           int queue,
2532                           const struct ieee80211_tx_queue_params *params)
2533 {
2534         return 0;
2535 }
2536
2537 static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
2538                                struct ieee80211_tx_queue_stats *stats)
2539 {
2540         struct b43_wl *wl = hw_to_b43_wl(hw);
2541         struct b43_wldev *dev = wl->current_dev;
2542         unsigned long flags;
2543         int err = -ENODEV;
2544
2545         if (!dev)
2546                 goto out;
2547         spin_lock_irqsave(&wl->irq_lock, flags);
2548         if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
2549                 if (b43_using_pio(dev))
2550                         b43_pio_get_tx_stats(dev, stats);
2551                 else
2552                         b43_dma_get_tx_stats(dev, stats);
2553                 err = 0;
2554         }
2555         spin_unlock_irqrestore(&wl->irq_lock, flags);
2556 out:
2557         return err;
2558 }
2559
2560 static int b43_op_get_stats(struct ieee80211_hw *hw,
2561                             struct ieee80211_low_level_stats *stats)
2562 {
2563         struct b43_wl *wl = hw_to_b43_wl(hw);
2564         unsigned long flags;
2565
2566         spin_lock_irqsave(&wl->irq_lock, flags);
2567         memcpy(stats, &wl->ieee_stats, sizeof(*stats));
2568         spin_unlock_irqrestore(&wl->irq_lock, flags);
2569
2570         return 0;
2571 }
2572
2573 static const char *phymode_to_string(unsigned int phymode)
2574 {
2575         switch (phymode) {
2576         case B43_PHYMODE_A:
2577                 return "A";
2578         case B43_PHYMODE_B:
2579                 return "B";
2580         case B43_PHYMODE_G:
2581                 return "G";
2582         default:
2583                 B43_WARN_ON(1);
2584         }
2585         return "";
2586 }
2587
2588 static int find_wldev_for_phymode(struct b43_wl *wl,
2589                                   unsigned int phymode,
2590                                   struct b43_wldev **dev, bool * gmode)
2591 {
2592         struct b43_wldev *d;
2593
2594         list_for_each_entry(d, &wl->devlist, list) {
2595                 if (d->phy.possible_phymodes & phymode) {
2596                         /* Ok, this device supports the PHY-mode.
2597                          * Now figure out how the gmode bit has to be
2598                          * set to support it. */
2599                         if (phymode == B43_PHYMODE_A)
2600                                 *gmode = 0;
2601                         else
2602                                 *gmode = 1;
2603                         *dev = d;
2604
2605                         return 0;
2606                 }
2607         }
2608
2609         return -ESRCH;
2610 }
2611
2612 static void b43_put_phy_into_reset(struct b43_wldev *dev)
2613 {
2614         struct ssb_device *sdev = dev->dev;
2615         u32 tmslow;
2616
2617         tmslow = ssb_read32(sdev, SSB_TMSLOW);
2618         tmslow &= ~B43_TMSLOW_GMODE;
2619         tmslow |= B43_TMSLOW_PHYRESET;
2620         tmslow |= SSB_TMSLOW_FGC;
2621         ssb_write32(sdev, SSB_TMSLOW, tmslow);
2622         msleep(1);
2623
2624         tmslow = ssb_read32(sdev, SSB_TMSLOW);
2625         tmslow &= ~SSB_TMSLOW_FGC;
2626         tmslow |= B43_TMSLOW_PHYRESET;
2627         ssb_write32(sdev, SSB_TMSLOW, tmslow);
2628         msleep(1);
2629 }
2630
2631 /* Expects wl->mutex locked */
2632 static int b43_switch_phymode(struct b43_wl *wl, unsigned int new_mode)
2633 {
2634         struct b43_wldev *up_dev;
2635         struct b43_wldev *down_dev;
2636         int err;
2637         bool gmode = 0;
2638         int prev_status;
2639
2640         err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
2641         if (err) {
2642                 b43err(wl, "Could not find a device for %s-PHY mode\n",
2643                        phymode_to_string(new_mode));
2644                 return err;
2645         }
2646         if ((up_dev == wl->current_dev) &&
2647             (!!wl->current_dev->phy.gmode == !!gmode)) {
2648                 /* This device is already running. */
2649                 return 0;
2650         }
2651         b43dbg(wl, "Reconfiguring PHYmode to %s-PHY\n",
2652                phymode_to_string(new_mode));
2653         down_dev = wl->current_dev;
2654
2655         prev_status = b43_status(down_dev);
2656         /* Shutdown the currently running core. */
2657         if (prev_status >= B43_STAT_STARTED)
2658                 b43_wireless_core_stop(down_dev);
2659         if (prev_status >= B43_STAT_INITIALIZED)
2660                 b43_wireless_core_exit(down_dev);
2661
2662         if (down_dev != up_dev) {
2663                 /* We switch to a different core, so we put PHY into
2664                  * RESET on the old core. */
2665                 b43_put_phy_into_reset(down_dev);
2666         }
2667
2668         /* Now start the new core. */
2669         up_dev->phy.gmode = gmode;
2670         if (prev_status >= B43_STAT_INITIALIZED) {
2671                 err = b43_wireless_core_init(up_dev);
2672                 if (err) {
2673                         b43err(wl, "Fatal: Could not initialize device for "
2674                                "newly selected %s-PHY mode\n",
2675                                phymode_to_string(new_mode));
2676                         goto init_failure;
2677                 }
2678         }
2679         if (prev_status >= B43_STAT_STARTED) {
2680                 err = b43_wireless_core_start(up_dev);
2681                 if (err) {
2682                         b43err(wl, "Fatal: Coult not start device for "
2683                                "newly selected %s-PHY mode\n",
2684                                phymode_to_string(new_mode));
2685                         b43_wireless_core_exit(up_dev);
2686                         goto init_failure;
2687                 }
2688         }
2689         B43_WARN_ON(b43_status(up_dev) != prev_status);
2690
2691         wl->current_dev = up_dev;
2692
2693         return 0;
2694       init_failure:
2695         /* Whoops, failed to init the new core. No core is operating now. */
2696         wl->current_dev = NULL;
2697         return err;
2698 }
2699
2700 static int b43_antenna_from_ieee80211(u8 antenna)
2701 {
2702         switch (antenna) {
2703         case 0:         /* default/diversity */
2704                 return B43_ANTENNA_DEFAULT;
2705         case 1:         /* Antenna 0 */
2706                 return B43_ANTENNA0;
2707         case 2:         /* Antenna 1 */
2708                 return B43_ANTENNA1;
2709         default:
2710                 return B43_ANTENNA_DEFAULT;
2711         }
2712 }
2713
2714 static int b43_op_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
2715 {
2716         struct b43_wl *wl = hw_to_b43_wl(hw);
2717         struct b43_wldev *dev;
2718         struct b43_phy *phy;
2719         unsigned long flags;
2720         unsigned int new_phymode = 0xFFFF;
2721         int antenna_tx;
2722         int antenna_rx;
2723         int err = 0;
2724         u32 savedirqs;
2725
2726         antenna_tx = b43_antenna_from_ieee80211(conf->antenna_sel_tx);
2727         antenna_rx = b43_antenna_from_ieee80211(conf->antenna_sel_rx);
2728
2729         mutex_lock(&wl->mutex);
2730
2731         /* Switch the PHY mode (if necessary). */
2732         switch (conf->phymode) {
2733         case MODE_IEEE80211A:
2734                 new_phymode = B43_PHYMODE_A;
2735                 break;
2736         case MODE_IEEE80211B:
2737                 new_phymode = B43_PHYMODE_B;
2738                 break;
2739         case MODE_IEEE80211G:
2740                 new_phymode = B43_PHYMODE_G;
2741                 break;
2742         default:
2743                 B43_WARN_ON(1);
2744         }
2745         err = b43_switch_phymode(wl, new_phymode);
2746         if (err)
2747                 goto out_unlock_mutex;
2748         dev = wl->current_dev;
2749         phy = &dev->phy;
2750
2751         /* Disable IRQs while reconfiguring the device.
2752          * This makes it possible to drop the spinlock throughout
2753          * the reconfiguration process. */
2754         spin_lock_irqsave(&wl->irq_lock, flags);
2755         if (b43_status(dev) < B43_STAT_STARTED) {
2756                 spin_unlock_irqrestore(&wl->irq_lock, flags);
2757                 goto out_unlock_mutex;
2758         }
2759         savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL);
2760         spin_unlock_irqrestore(&wl->irq_lock, flags);
2761         b43_synchronize_irq(dev);
2762
2763         /* Switch to the requested channel.
2764          * The firmware takes care of races with the TX handler. */
2765         if (conf->channel_val != phy->channel)
2766                 b43_radio_selectchannel(dev, conf->channel_val, 0);
2767
2768         /* Enable/Disable ShortSlot timing. */
2769         if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) !=
2770             dev->short_slot) {
2771                 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
2772                 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
2773                         b43_short_slot_timing_enable(dev);
2774                 else
2775                         b43_short_slot_timing_disable(dev);
2776         }
2777
2778         dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
2779
2780         /* Adjust the desired TX power level. */
2781         if (conf->power_level != 0) {
2782                 if (conf->power_level != phy->power_level) {
2783                         phy->power_level = conf->power_level;
2784                         b43_phy_xmitpower(dev);
2785                 }
2786         }
2787
2788         /* Antennas for RX and management frame TX. */
2789         b43_mgmtframe_txantenna(dev, antenna_tx);
2790         b43_set_rx_antenna(dev, antenna_rx);
2791
2792         /* Update templates for AP mode. */
2793         if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2794                 b43_set_beacon_int(dev, conf->beacon_int);
2795
2796         if (!!conf->radio_enabled != phy->radio_on) {
2797                 if (conf->radio_enabled) {
2798                         b43_radio_turn_on(dev);
2799                         b43info(dev->wl, "Radio turned on by software\n");
2800                         if (!dev->radio_hw_enable) {
2801                                 b43info(dev->wl, "The hardware RF-kill button "
2802                                         "still turns the radio physically off. "
2803                                         "Press the button to turn it on.\n");
2804                         }
2805                 } else {
2806                         b43_radio_turn_off(dev, 0);
2807                         b43info(dev->wl, "Radio turned off by software\n");
2808                 }
2809         }
2810
2811         spin_lock_irqsave(&wl->irq_lock, flags);
2812         b43_interrupt_enable(dev, savedirqs);
2813         mmiowb();
2814         spin_unlock_irqrestore(&wl->irq_lock, flags);
2815       out_unlock_mutex:
2816         mutex_unlock(&wl->mutex);
2817
2818         return err;
2819 }
2820
2821 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2822                            const u8 *local_addr, const u8 *addr,
2823                            struct ieee80211_key_conf *key)
2824 {
2825         struct b43_wl *wl = hw_to_b43_wl(hw);
2826         struct b43_wldev *dev;
2827         unsigned long flags;
2828         u8 algorithm;
2829         u8 index;
2830         int err;
2831         DECLARE_MAC_BUF(mac);
2832
2833         if (modparam_nohwcrypt)
2834                 return -ENOSPC; /* User disabled HW-crypto */
2835
2836         mutex_lock(&wl->mutex);
2837         spin_lock_irqsave(&wl->irq_lock, flags);
2838
2839         dev = wl->current_dev;
2840         err = -ENODEV;
2841         if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
2842                 goto out_unlock;
2843
2844         err = -EINVAL;
2845         switch (key->alg) {
2846         case ALG_WEP:
2847                 if (key->keylen == 5)
2848                         algorithm = B43_SEC_ALGO_WEP40;
2849                 else
2850                         algorithm = B43_SEC_ALGO_WEP104;
2851                 break;
2852         case ALG_TKIP:
2853                 algorithm = B43_SEC_ALGO_TKIP;
2854                 break;
2855         case ALG_CCMP:
2856                 algorithm = B43_SEC_ALGO_AES;
2857                 break;
2858         default:
2859                 B43_WARN_ON(1);
2860                 goto out_unlock;
2861         }
2862         index = (u8) (key->keyidx);
2863         if (index > 3)
2864                 goto out_unlock;
2865
2866         switch (cmd) {
2867         case SET_KEY:
2868                 if (algorithm == B43_SEC_ALGO_TKIP) {
2869                         /* FIXME: No TKIP hardware encryption for now. */
2870                         err = -EOPNOTSUPP;
2871                         goto out_unlock;
2872                 }
2873
2874                 if (is_broadcast_ether_addr(addr)) {
2875                         /* addr is FF:FF:FF:FF:FF:FF for default keys */
2876                         err = b43_key_write(dev, index, algorithm,
2877                                             key->key, key->keylen, NULL, key);
2878                 } else {
2879                         /*
2880                          * either pairwise key or address is 00:00:00:00:00:00
2881                          * for transmit-only keys
2882                          */
2883                         err = b43_key_write(dev, -1, algorithm,
2884                                             key->key, key->keylen, addr, key);
2885                 }
2886                 if (err)
2887                         goto out_unlock;
2888
2889                 if (algorithm == B43_SEC_ALGO_WEP40 ||
2890                     algorithm == B43_SEC_ALGO_WEP104) {
2891                         b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
2892                 } else {
2893                         b43_hf_write(dev,
2894                                      b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
2895                 }
2896                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2897                 break;
2898         case DISABLE_KEY: {
2899                 err = b43_key_clear(dev, key->hw_key_idx);
2900                 if (err)
2901                         goto out_unlock;
2902                 break;
2903         }
2904         default:
2905                 B43_WARN_ON(1);
2906         }
2907 out_unlock:
2908         spin_unlock_irqrestore(&wl->irq_lock, flags);
2909         mutex_unlock(&wl->mutex);
2910         if (!err) {
2911                 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
2912                        "mac: %s\n",
2913                        cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
2914                        print_mac(mac, addr));
2915         }
2916         return err;
2917 }
2918
2919 static void b43_op_configure_filter(struct ieee80211_hw *hw,
2920                                     unsigned int changed, unsigned int *fflags,
2921                                     int mc_count, struct dev_addr_list *mc_list)
2922 {
2923         struct b43_wl *wl = hw_to_b43_wl(hw);
2924         struct b43_wldev *dev = wl->current_dev;
2925         unsigned long flags;
2926
2927         if (!dev) {
2928                 *fflags = 0;
2929                 return;
2930         }
2931
2932         spin_lock_irqsave(&wl->irq_lock, flags);
2933         *fflags &= FIF_PROMISC_IN_BSS |
2934                   FIF_ALLMULTI |
2935                   FIF_FCSFAIL |
2936                   FIF_PLCPFAIL |
2937                   FIF_CONTROL |
2938                   FIF_OTHER_BSS |
2939                   FIF_BCN_PRBRESP_PROMISC;
2940
2941         changed &= FIF_PROMISC_IN_BSS |
2942                    FIF_ALLMULTI |
2943                    FIF_FCSFAIL |
2944                    FIF_PLCPFAIL |
2945                    FIF_CONTROL |
2946                    FIF_OTHER_BSS |
2947                    FIF_BCN_PRBRESP_PROMISC;
2948
2949         wl->filter_flags = *fflags;
2950
2951         if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
2952                 b43_adjust_opmode(dev);
2953         spin_unlock_irqrestore(&wl->irq_lock, flags);
2954 }
2955
2956 static int b43_op_config_interface(struct ieee80211_hw *hw,
2957                                    int if_id,
2958                                    struct ieee80211_if_conf *conf)
2959 {
2960         struct b43_wl *wl = hw_to_b43_wl(hw);
2961         struct b43_wldev *dev = wl->current_dev;
2962         unsigned long flags;
2963
2964         if (!dev)
2965                 return -ENODEV;
2966         mutex_lock(&wl->mutex);
2967         spin_lock_irqsave(&wl->irq_lock, flags);
2968         B43_WARN_ON(wl->if_id != if_id);
2969         if (conf->bssid)
2970                 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
2971         else
2972                 memset(wl->bssid, 0, ETH_ALEN);
2973         if (b43_status(dev) >= B43_STAT_INITIALIZED) {
2974                 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) {
2975                         B43_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP);
2976                         b43_set_ssid(dev, conf->ssid, conf->ssid_len);
2977                         if (conf->beacon)
2978                                 b43_refresh_templates(dev, conf->beacon);
2979                 }
2980                 b43_write_mac_bssid_templates(dev);
2981         }
2982         spin_unlock_irqrestore(&wl->irq_lock, flags);
2983         mutex_unlock(&wl->mutex);
2984
2985         return 0;
2986 }
2987
2988 /* Locking: wl->mutex */
2989 static void b43_wireless_core_stop(struct b43_wldev *dev)
2990 {
2991         struct b43_wl *wl = dev->wl;
2992         unsigned long flags;
2993
2994         if (b43_status(dev) < B43_STAT_STARTED)
2995                 return;
2996
2997         /* Disable and sync interrupts. We must do this before than
2998          * setting the status to INITIALIZED, as the interrupt handler
2999          * won't care about IRQs then. */
3000         spin_lock_irqsave(&wl->irq_lock, flags);
3001         dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
3002         b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
3003         spin_unlock_irqrestore(&wl->irq_lock, flags);
3004         b43_synchronize_irq(dev);
3005
3006         b43_set_status(dev, B43_STAT_INITIALIZED);
3007
3008         mutex_unlock(&wl->mutex);
3009         /* Must unlock as it would otherwise deadlock. No races here.
3010          * Cancel the possibly running self-rearming periodic work. */
3011         cancel_delayed_work_sync(&dev->periodic_work);
3012         mutex_lock(&wl->mutex);
3013
3014         ieee80211_stop_queues(wl->hw);  //FIXME this could cause a deadlock, as mac80211 seems buggy.
3015
3016         b43_mac_suspend(dev);
3017         free_irq(dev->dev->irq, dev);
3018         b43dbg(wl, "Wireless interface stopped\n");
3019 }
3020
3021 /* Locking: wl->mutex */
3022 static int b43_wireless_core_start(struct b43_wldev *dev)
3023 {
3024         int err;
3025
3026         B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3027
3028         drain_txstatus_queue(dev);
3029         err = request_irq(dev->dev->irq, b43_interrupt_handler,
3030                           IRQF_SHARED, KBUILD_MODNAME, dev);
3031         if (err) {
3032                 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3033                 goto out;
3034         }
3035
3036         /* We are ready to run. */
3037         b43_set_status(dev, B43_STAT_STARTED);
3038
3039         /* Start data flow (TX/RX). */
3040         b43_mac_enable(dev);
3041         b43_interrupt_enable(dev, dev->irq_savedstate);
3042         ieee80211_start_queues(dev->wl->hw);
3043
3044         /* Start maintainance work */
3045         b43_periodic_tasks_setup(dev);
3046
3047         b43dbg(dev->wl, "Wireless interface started\n");
3048       out:
3049         return err;
3050 }
3051
3052 /* Get PHY and RADIO versioning numbers */
3053 static int b43_phy_versioning(struct b43_wldev *dev)
3054 {
3055         struct b43_phy *phy = &dev->phy;
3056         u32 tmp;
3057         u8 analog_type;
3058         u8 phy_type;
3059         u8 phy_rev;
3060         u16 radio_manuf;
3061         u16 radio_ver;
3062         u16 radio_rev;
3063         int unsupported = 0;
3064
3065         /* Get PHY versioning */
3066         tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3067         analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3068         phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3069         phy_rev = (tmp & B43_PHYVER_VERSION);
3070         switch (phy_type) {
3071         case B43_PHYTYPE_A:
3072                 if (phy_rev >= 4)
3073                         unsupported = 1;
3074                 break;
3075         case B43_PHYTYPE_B:
3076                 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3077                     && phy_rev != 7)
3078                         unsupported = 1;
3079                 break;
3080         case B43_PHYTYPE_G:
3081                 if (phy_rev > 8)
3082                         unsupported = 1;
3083                 break;
3084         default:
3085                 unsupported = 1;
3086         };
3087         if (unsupported) {
3088                 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3089                        "(Analog %u, Type %u, Revision %u)\n",
3090                        analog_type, phy_type, phy_rev);
3091                 return -EOPNOTSUPP;
3092         }
3093         b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3094                analog_type, phy_type, phy_rev);
3095
3096         /* Get RADIO versioning */
3097         if (dev->dev->bus->chip_id == 0x4317) {
3098                 if (dev->dev->bus->chip_rev == 0)
3099                         tmp = 0x3205017F;
3100                 else if (dev->dev->bus->chip_rev == 1)
3101                         tmp = 0x4205017F;
3102                 else
3103                         tmp = 0x5205017F;
3104         } else {
3105                 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3106                 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH);
3107                 tmp <<= 16;
3108                 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3109                 tmp |= b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3110         }
3111         radio_manuf = (tmp & 0x00000FFF);
3112         radio_ver = (tmp & 0x0FFFF000) >> 12;
3113         radio_rev = (tmp & 0xF0000000) >> 28;
3114         switch (phy_type) {
3115         case B43_PHYTYPE_A:
3116                 if (radio_ver != 0x2060)
3117                         unsupported = 1;
3118                 if (radio_rev != 1)
3119                         unsupported = 1;
3120                 if (radio_manuf != 0x17F)
3121                         unsupported = 1;
3122                 break;
3123         case B43_PHYTYPE_B:
3124                 if ((radio_ver & 0xFFF0) != 0x2050)
3125                         unsupported = 1;
3126                 break;
3127         case B43_PHYTYPE_G:
3128                 if (radio_ver != 0x2050)
3129                         unsupported = 1;
3130                 break;
3131         default:
3132                 B43_WARN_ON(1);
3133         }
3134         if (unsupported) {
3135                 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
3136                        "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3137                        radio_manuf, radio_ver, radio_rev);
3138                 return -EOPNOTSUPP;
3139         }
3140         b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3141                radio_manuf, radio_ver, radio_rev);
3142
3143         phy->radio_manuf = radio_manuf;
3144         phy->radio_ver = radio_ver;
3145         phy->radio_rev = radio_rev;
3146
3147         phy->analog = analog_type;
3148         phy->type = phy_type;
3149         phy->rev = phy_rev;
3150
3151         return 0;
3152 }
3153
3154 static void setup_struct_phy_for_init(struct b43_wldev *dev,
3155                                       struct b43_phy *phy)
3156 {
3157         struct b43_txpower_lo_control *lo;
3158         int i;
3159
3160         memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3161         memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3162
3163         /* Flags */
3164         phy->locked = 0;
3165
3166         phy->aci_enable = 0;
3167         phy->aci_wlan_automatic = 0;
3168         phy->aci_hw_rssi = 0;
3169
3170         phy->radio_off_context.valid = 0;
3171
3172         lo = phy->lo_control;
3173         if (lo) {
3174                 memset(lo, 0, sizeof(*(phy->lo_control)));
3175                 lo->rebuild = 1;
3176                 lo->tx_bias = 0xFF;
3177         }
3178         phy->max_lb_gain = 0;
3179         phy->trsw_rx_gain = 0;
3180         phy->txpwr_offset = 0;
3181
3182         /* NRSSI */
3183         phy->nrssislope = 0;
3184         for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3185                 phy->nrssi[i] = -1000;
3186         for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3187                 phy->nrssi_lt[i] = i;
3188
3189         phy->lofcal = 0xFFFF;
3190         phy->initval = 0xFFFF;
3191
3192         spin_lock_init(&phy->lock);
3193         phy->interfmode = B43_INTERFMODE_NONE;
3194         phy->channel = 0xFF;
3195
3196         phy->hardware_power_control = !!modparam_hwpctl;
3197 }
3198
3199 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
3200 {
3201         /* Flags */
3202         dev->reg124_set_0x4 = 0;
3203         /* Assume the radio is enabled. If it's not enabled, the state will
3204          * immediately get fixed on the first periodic work run. */
3205         dev->radio_hw_enable = 1;
3206
3207         /* Stats */
3208         memset(&dev->stats, 0, sizeof(dev->stats));
3209
3210         setup_struct_phy_for_init(dev, &dev->phy);
3211
3212         /* IRQ related flags */
3213         dev->irq_reason = 0;
3214         memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3215         dev->irq_savedstate = B43_IRQ_MASKTEMPLATE;
3216
3217         dev->mac_suspended = 1;
3218
3219         /* Noise calculation context */
3220         memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3221 }
3222
3223 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
3224 {
3225         struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3226         u32 hf;
3227
3228         if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
3229                 return;
3230         if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
3231                 return;
3232
3233         hf = b43_hf_read(dev);
3234         if (sprom->boardflags_lo & B43_BFL_BTCMOD)
3235                 hf |= B43_HF_BTCOEXALT;
3236         else
3237                 hf |= B43_HF_BTCOEX;
3238         b43_hf_write(dev, hf);
3239         //TODO
3240 }
3241
3242 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
3243 {                               //TODO
3244 }
3245
3246 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
3247 {
3248 #ifdef CONFIG_SSB_DRIVER_PCICORE
3249         struct ssb_bus *bus = dev->dev->bus;
3250         u32 tmp;
3251
3252         if (bus->pcicore.dev &&
3253             bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
3254             bus->pcicore.dev->id.revision <= 5) {
3255                 /* IMCFGLO timeouts workaround. */
3256                 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
3257                 tmp &= ~SSB_IMCFGLO_REQTO;
3258                 tmp &= ~SSB_IMCFGLO_SERTO;
3259                 switch (bus->bustype) {
3260                 case SSB_BUSTYPE_PCI:
3261                 case SSB_BUSTYPE_PCMCIA:
3262                         tmp |= 0x32;
3263                         break;
3264                 case SSB_BUSTYPE_SSB:
3265                         tmp |= 0x53;
3266                         break;
3267                 }
3268                 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
3269         }
3270 #endif /* CONFIG_SSB_DRIVER_PCICORE */
3271 }
3272
3273 /* Write the short and long frame retry limit values. */
3274 static void b43_set_retry_limits(struct b43_wldev *dev,
3275                                  unsigned int short_retry,
3276                                  unsigned int long_retry)
3277 {
3278         /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3279          * the chip-internal counter. */
3280         short_retry = min(short_retry, (unsigned int)0xF);
3281         long_retry = min(long_retry, (unsigned int)0xF);
3282
3283         b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3284                         short_retry);
3285         b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3286                         long_retry);
3287 }
3288
3289 /* Shutdown a wireless core */
3290 /* Locking: wl->mutex */
3291 static void b43_wireless_core_exit(struct b43_wldev *dev)
3292 {
3293         struct b43_phy *phy = &dev->phy;
3294
3295         B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
3296         if (b43_status(dev) != B43_STAT_INITIALIZED)
3297                 return;
3298         b43_set_status(dev, B43_STAT_UNINIT);
3299
3300         b43_leds_exit(dev);
3301         b43_rng_exit(dev->wl);
3302         b43_pio_free(dev);
3303         b43_dma_free(dev);
3304         b43_chip_exit(dev);
3305         b43_radio_turn_off(dev, 1);
3306         b43_switch_analog(dev, 0);
3307         if (phy->dyn_tssi_tbl)
3308                 kfree(phy->tssi2dbm);
3309         kfree(phy->lo_control);
3310         phy->lo_control = NULL;
3311         ssb_device_disable(dev->dev, 0);
3312         ssb_bus_may_powerdown(dev->dev->bus);
3313 }
3314
3315 /* Initialize a wireless core */
3316 static int b43_wireless_core_init(struct b43_wldev *dev)
3317 {
3318         struct b43_wl *wl = dev->wl;
3319         struct ssb_bus *bus = dev->dev->bus;
3320         struct ssb_sprom *sprom = &bus->sprom;
3321         struct b43_phy *phy = &dev->phy;
3322         int err;
3323         u32 hf, tmp;
3324
3325         B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3326
3327         err = ssb_bus_powerup(bus, 0);
3328         if (err)
3329                 goto out;
3330         if (!ssb_device_is_enabled(dev->dev)) {
3331                 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
3332                 b43_wireless_core_reset(dev, tmp);
3333         }
3334
3335         if ((phy->type == B43_PHYTYPE_B) || (phy->type == B43_PHYTYPE_G)) {
3336                 phy->lo_control =
3337                     kzalloc(sizeof(*(phy->lo_control)), GFP_KERNEL);
3338                 if (!phy->lo_control) {
3339                         err = -ENOMEM;
3340                         goto err_busdown;
3341                 }
3342         }
3343         setup_struct_wldev_for_init(dev);
3344
3345         err = b43_phy_init_tssi2dbm_table(dev);
3346         if (err)
3347                 goto err_kfree_lo_control;
3348
3349         /* Enable IRQ routing to this device. */
3350         ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3351
3352         b43_imcfglo_timeouts_workaround(dev);
3353         b43_bluetooth_coext_disable(dev);
3354         b43_phy_early_init(dev);
3355         err = b43_chip_init(dev);
3356         if (err)
3357                 goto err_kfree_tssitbl;
3358         b43_shm_write16(dev, B43_SHM_SHARED,
3359                         B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
3360         hf = b43_hf_read(dev);
3361         if (phy->type == B43_PHYTYPE_G) {
3362                 hf |= B43_HF_SYMW;
3363                 if (phy->rev == 1)
3364                         hf |= B43_HF_GDCW;
3365                 if (sprom->boardflags_lo & B43_BFL_PACTRL)
3366                         hf |= B43_HF_OFDMPABOOST;
3367         } else if (phy->type == B43_PHYTYPE_B) {
3368                 hf |= B43_HF_SYMW;
3369                 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
3370                         hf &= ~B43_HF_GDCW;
3371         }
3372         b43_hf_write(dev, hf);
3373
3374         b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
3375                              B43_DEFAULT_LONG_RETRY_LIMIT);
3376         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
3377         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
3378
3379         /* Disable sending probe responses from firmware.
3380          * Setting the MaxTime to one usec will always trigger
3381          * a timeout, so we never send any probe resp.
3382          * A timeout of zero is infinite. */
3383         b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
3384
3385         b43_rate_memory_init(dev);
3386
3387         /* Minimum Contention Window */
3388         if (phy->type == B43_PHYTYPE_B) {
3389                 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
3390         } else {
3391                 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
3392         }
3393         /* Maximum Contention Window */
3394         b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
3395
3396         do {
3397                 if (b43_using_pio(dev)) {
3398                         err = b43_pio_init(dev);
3399                 } else {
3400                         err = b43_dma_init(dev);
3401                         if (!err)
3402                                 b43_qos_init(dev);
3403                 }
3404         } while (err == -EAGAIN);
3405         if (err)
3406                 goto err_chip_exit;
3407
3408 //FIXME
3409 #if 1
3410         b43_write16(dev, 0x0612, 0x0050);
3411         b43_shm_write16(dev, B43_SHM_SHARED, 0x0416, 0x0050);
3412         b43_shm_write16(dev, B43_SHM_SHARED, 0x0414, 0x01F4);
3413 #endif
3414
3415         b43_bluetooth_coext_enable(dev);
3416
3417         ssb_bus_powerup(bus, 1);        /* Enable dynamic PCTL */
3418         memset(wl->bssid, 0, ETH_ALEN);
3419         memset(wl->mac_addr, 0, ETH_ALEN);
3420         b43_upload_card_macaddress(dev);
3421         b43_security_init(dev);
3422         b43_rng_init(wl);
3423
3424         b43_set_status(dev, B43_STAT_INITIALIZED);
3425
3426         b43_leds_init(dev);
3427 out:
3428         return err;
3429
3430       err_chip_exit:
3431         b43_chip_exit(dev);
3432       err_kfree_tssitbl:
3433         if (phy->dyn_tssi_tbl)
3434                 kfree(phy->tssi2dbm);
3435       err_kfree_lo_control:
3436         kfree(phy->lo_control);
3437         phy->lo_control = NULL;
3438       err_busdown:
3439         ssb_bus_may_powerdown(bus);
3440         B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3441         return err;
3442 }
3443
3444 static int b43_op_add_interface(struct ieee80211_hw *hw,
3445                                 struct ieee80211_if_init_conf *conf)
3446 {
3447         struct b43_wl *wl = hw_to_b43_wl(hw);
3448         struct b43_wldev *dev;
3449         unsigned long flags;
3450         int err = -EOPNOTSUPP;
3451
3452         /* TODO: allow WDS/AP devices to coexist */
3453
3454         if (conf->type != IEEE80211_IF_TYPE_AP &&
3455             conf->type != IEEE80211_IF_TYPE_STA &&
3456             conf->type != IEEE80211_IF_TYPE_WDS &&
3457             conf->type != IEEE80211_IF_TYPE_IBSS)
3458                 return -EOPNOTSUPP;
3459
3460         mutex_lock(&wl->mutex);
3461         if (wl->operating)
3462                 goto out_mutex_unlock;
3463
3464         b43dbg(wl, "Adding Interface type %d\n", conf->type);
3465
3466         dev = wl->current_dev;
3467         wl->operating = 1;
3468         wl->if_id = conf->if_id;
3469         wl->if_type = conf->type;
3470         memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
3471
3472         spin_lock_irqsave(&wl->irq_lock, flags);
3473         b43_adjust_opmode(dev);
3474         b43_upload_card_macaddress(dev);
3475         spin_unlock_irqrestore(&wl->irq_lock, flags);
3476
3477         err = 0;
3478  out_mutex_unlock:
3479         mutex_unlock(&wl->mutex);
3480
3481         return err;
3482 }
3483
3484 static void b43_op_remove_interface(struct ieee80211_hw *hw,
3485                                     struct ieee80211_if_init_conf *conf)
3486 {
3487         struct b43_wl *wl = hw_to_b43_wl(hw);
3488         struct b43_wldev *dev = wl->current_dev;
3489         unsigned long flags;
3490
3491         b43dbg(wl, "Removing Interface type %d\n", conf->type);
3492
3493         mutex_lock(&wl->mutex);
3494
3495         B43_WARN_ON(!wl->operating);
3496         B43_WARN_ON(wl->if_id != conf->if_id);
3497
3498         wl->operating = 0;
3499
3500         spin_lock_irqsave(&wl->irq_lock, flags);
3501         b43_adjust_opmode(dev);
3502         memset(wl->mac_addr, 0, ETH_ALEN);
3503         b43_upload_card_macaddress(dev);
3504         spin_unlock_irqrestore(&wl->irq_lock, flags);
3505
3506         mutex_unlock(&wl->mutex);
3507 }
3508
3509 static int b43_op_start(struct ieee80211_hw *hw)
3510 {
3511         struct b43_wl *wl = hw_to_b43_wl(hw);
3512         struct b43_wldev *dev = wl->current_dev;
3513         int did_init = 0;
3514         int err = 0;
3515
3516         /* First register RFkill.
3517          * LEDs that are registered later depend on it. */
3518         b43_rfkill_init(dev);
3519
3520         mutex_lock(&wl->mutex);
3521
3522         if (b43_status(dev) < B43_STAT_INITIALIZED) {
3523                 err = b43_wireless_core_init(dev);
3524                 if (err)
3525                         goto out_mutex_unlock;
3526                 did_init = 1;
3527         }
3528
3529         if (b43_status(dev) < B43_STAT_STARTED) {
3530                 err = b43_wireless_core_start(dev);
3531                 if (err) {
3532                         if (did_init)
3533                                 b43_wireless_core_exit(dev);
3534                         goto out_mutex_unlock;
3535                 }
3536         }
3537
3538  out_mutex_unlock:
3539         mutex_unlock(&wl->mutex);
3540
3541         return err;
3542 }
3543
3544 static void b43_op_stop(struct ieee80211_hw *hw)
3545 {
3546         struct b43_wl *wl = hw_to_b43_wl(hw);
3547         struct b43_wldev *dev = wl->current_dev;
3548
3549         b43_rfkill_exit(dev);
3550
3551         mutex_lock(&wl->mutex);
3552         if (b43_status(dev) >= B43_STAT_STARTED)
3553                 b43_wireless_core_stop(dev);
3554         b43_wireless_core_exit(dev);
3555         mutex_unlock(&wl->mutex);
3556 }
3557
3558 static int b43_op_set_retry_limit(struct ieee80211_hw *hw,
3559                                   u32 short_retry_limit, u32 long_retry_limit)
3560 {
3561         struct b43_wl *wl = hw_to_b43_wl(hw);
3562         struct b43_wldev *dev;
3563         int err = 0;
3564
3565         mutex_lock(&wl->mutex);
3566         dev = wl->current_dev;
3567         if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED))) {
3568                 err = -ENODEV;
3569                 goto out_unlock;
3570         }
3571         b43_set_retry_limits(dev, short_retry_limit, long_retry_limit);
3572 out_unlock:
3573         mutex_unlock(&wl->mutex);
3574
3575         return err;
3576 }
3577
3578 static const struct ieee80211_ops b43_hw_ops = {
3579         .tx                     = b43_op_tx,
3580         .conf_tx                = b43_op_conf_tx,
3581         .add_interface          = b43_op_add_interface,
3582         .remove_interface       = b43_op_remove_interface,
3583         .config                 = b43_op_config,
3584         .config_interface       = b43_op_config_interface,
3585         .configure_filter       = b43_op_configure_filter,
3586         .set_key                = b43_op_set_key,
3587         .get_stats              = b43_op_get_stats,
3588         .get_tx_stats           = b43_op_get_tx_stats,
3589         .start                  = b43_op_start,
3590         .stop                   = b43_op_stop,
3591         .set_retry_limit        = b43_op_set_retry_limit,
3592 };
3593
3594 /* Hard-reset the chip. Do not call this directly.
3595  * Use b43_controller_restart()
3596  */
3597 static void b43_chip_reset(struct work_struct *work)
3598 {
3599         struct b43_wldev *dev =
3600             container_of(work, struct b43_wldev, restart_work);
3601         struct b43_wl *wl = dev->wl;
3602         int err = 0;
3603         int prev_status;
3604
3605         mutex_lock(&wl->mutex);
3606
3607         prev_status = b43_status(dev);
3608         /* Bring the device down... */
3609         if (prev_status >= B43_STAT_STARTED)
3610                 b43_wireless_core_stop(dev);
3611         if (prev_status >= B43_STAT_INITIALIZED)
3612                 b43_wireless_core_exit(dev);
3613
3614         /* ...and up again. */
3615         if (prev_status >= B43_STAT_INITIALIZED) {
3616                 err = b43_wireless_core_init(dev);
3617                 if (err)
3618                         goto out;
3619         }
3620         if (prev_status >= B43_STAT_STARTED) {
3621                 err = b43_wireless_core_start(dev);
3622                 if (err) {
3623                         b43_wireless_core_exit(dev);
3624                         goto out;
3625                 }
3626         }
3627       out:
3628         mutex_unlock(&wl->mutex);
3629         if (err)
3630                 b43err(wl, "Controller restart FAILED\n");
3631         else
3632                 b43info(wl, "Controller restarted\n");
3633 }
3634
3635 static int b43_setup_modes(struct b43_wldev *dev,
3636                            int have_aphy, int have_bphy, int have_gphy)
3637 {
3638         struct ieee80211_hw *hw = dev->wl->hw;
3639         struct ieee80211_hw_mode *mode;
3640         struct b43_phy *phy = &dev->phy;
3641         int cnt = 0;
3642         int err;
3643
3644 /*FIXME: Don't tell ieee80211 about an A-PHY, because we currently don't support A-PHY. */
3645         have_aphy = 0;
3646
3647         phy->possible_phymodes = 0;
3648         for (; 1; cnt++) {
3649                 if (have_aphy) {
3650                         B43_WARN_ON(cnt >= B43_MAX_PHYHWMODES);
3651                         mode = &phy->hwmodes[cnt];
3652
3653                         mode->mode = MODE_IEEE80211A;
3654                         mode->num_channels = b43_a_chantable_size;
3655                         mode->channels = b43_a_chantable;
3656                         mode->num_rates = b43_a_ratetable_size;
3657                         mode->rates = b43_a_ratetable;
3658                         err = ieee80211_register_hwmode(hw, mode);
3659                         if (err)
3660                                 return err;
3661
3662                         phy->possible_phymodes |= B43_PHYMODE_A;
3663                         have_aphy = 0;
3664                         continue;
3665                 }
3666                 if (have_bphy) {
3667                         B43_WARN_ON(cnt >= B43_MAX_PHYHWMODES);
3668                         mode = &phy->hwmodes[cnt];
3669
3670                         mode->mode = MODE_IEEE80211B;
3671                         mode->num_channels = b43_bg_chantable_size;
3672                         mode->channels = b43_bg_chantable;
3673                         mode->num_rates = b43_b_ratetable_size;
3674                         mode->rates = b43_b_ratetable;
3675                         err = ieee80211_register_hwmode(hw, mode);
3676                         if (err)
3677                                 return err;
3678
3679                         phy->possible_phymodes |= B43_PHYMODE_B;
3680                         have_bphy = 0;
3681                         continue;
3682                 }
3683                 if (have_gphy) {
3684                         B43_WARN_ON(cnt >= B43_MAX_PHYHWMODES);
3685                         mode = &phy->hwmodes[cnt];
3686
3687                         mode->mode = MODE_IEEE80211G;
3688                         mode->num_channels = b43_bg_chantable_size;
3689                         mode->channels = b43_bg_chantable;
3690                         mode->num_rates = b43_g_ratetable_size;
3691                         mode->rates = b43_g_ratetable;
3692                         err = ieee80211_register_hwmode(hw, mode);
3693                         if (err)
3694                                 return err;
3695
3696                         phy->possible_phymodes |= B43_PHYMODE_G;
3697                         have_gphy = 0;
3698                         continue;
3699                 }
3700                 break;
3701         }
3702
3703         return 0;
3704 }
3705
3706 static void b43_wireless_core_detach(struct b43_wldev *dev)
3707 {
3708         /* We release firmware that late to not be required to re-request
3709          * is all the time when we reinit the core. */
3710         b43_release_firmware(dev);
3711 }
3712
3713 static int b43_wireless_core_attach(struct b43_wldev *dev)
3714 {
3715         struct b43_wl *wl = dev->wl;
3716         struct ssb_bus *bus = dev->dev->bus;
3717         struct pci_dev *pdev = bus->host_pci;
3718         int err;
3719         int have_aphy = 0, have_bphy = 0, have_gphy = 0;
3720         u32 tmp;
3721
3722         /* Do NOT do any device initialization here.
3723          * Do it in wireless_core_init() instead.
3724          * This function is for gathering basic information about the HW, only.
3725          * Also some structs may be set up here. But most likely you want to have
3726          * that in core_init(), too.
3727          */
3728
3729         err = ssb_bus_powerup(bus, 0);
3730         if (err) {
3731                 b43err(wl, "Bus powerup failed\n");
3732                 goto out;
3733         }
3734         /* Get the PHY type. */
3735         if (dev->dev->id.revision >= 5) {
3736                 u32 tmshigh;
3737
3738                 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
3739                 have_aphy = !!(tmshigh & B43_TMSHIGH_APHY);
3740                 have_gphy = !!(tmshigh & B43_TMSHIGH_GPHY);
3741                 if (!have_aphy && !have_gphy)
3742                         have_bphy = 1;
3743         } else if (dev->dev->id.revision == 4) {
3744                 have_gphy = 1;
3745                 have_aphy = 1;
3746         } else
3747                 have_bphy = 1;
3748
3749         dev->phy.gmode = (have_gphy || have_bphy);
3750         tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3751         b43_wireless_core_reset(dev, tmp);
3752
3753         err = b43_phy_versioning(dev);
3754         if (err)
3755                 goto err_powerdown;
3756         /* Check if this device supports multiband. */
3757         if (!pdev ||
3758             (pdev->device != 0x4312 &&
3759              pdev->device != 0x4319 && pdev->device != 0x4324)) {
3760                 /* No multiband support. */
3761                 have_aphy = 0;
3762                 have_bphy = 0;
3763                 have_gphy = 0;
3764                 switch (dev->phy.type) {
3765                 case B43_PHYTYPE_A:
3766                         have_aphy = 1;
3767                         break;
3768                 case B43_PHYTYPE_B:
3769                         have_bphy = 1;
3770                         break;
3771                 case B43_PHYTYPE_G:
3772                         have_gphy = 1;
3773                         break;
3774                 default:
3775                         B43_WARN_ON(1);
3776                 }
3777         }
3778         dev->phy.gmode = (have_gphy || have_bphy);
3779         tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3780         b43_wireless_core_reset(dev, tmp);
3781
3782         err = b43_validate_chipaccess(dev);
3783         if (err)
3784                 goto err_powerdown;
3785         err = b43_setup_modes(dev, have_aphy, have_bphy, have_gphy);
3786         if (err)
3787                 goto err_powerdown;
3788
3789         /* Now set some default "current_dev" */
3790         if (!wl->current_dev)
3791                 wl->current_dev = dev;
3792         INIT_WORK(&dev->restart_work, b43_chip_reset);
3793
3794         b43_radio_turn_off(dev, 1);
3795         b43_switch_analog(dev, 0);
3796         ssb_device_disable(dev->dev, 0);
3797         ssb_bus_may_powerdown(bus);
3798
3799 out:
3800         return err;
3801
3802 err_powerdown:
3803         ssb_bus_may_powerdown(bus);
3804         return err;
3805 }
3806
3807 static void b43_one_core_detach(struct ssb_device *dev)
3808 {
3809         struct b43_wldev *wldev;
3810         struct b43_wl *wl;
3811
3812         wldev = ssb_get_drvdata(dev);
3813         wl = wldev->wl;
3814         cancel_work_sync(&wldev->restart_work);
3815         b43_debugfs_remove_device(wldev);
3816         b43_wireless_core_detach(wldev);
3817         list_del(&wldev->list);
3818         wl->nr_devs--;
3819         ssb_set_drvdata(dev, NULL);
3820         kfree(wldev);
3821 }
3822
3823 static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
3824 {
3825         struct b43_wldev *wldev;
3826         struct pci_dev *pdev;
3827         int err = -ENOMEM;
3828
3829         if (!list_empty(&wl->devlist)) {
3830                 /* We are not the first core on this chip. */
3831                 pdev = dev->bus->host_pci;
3832                 /* Only special chips support more than one wireless
3833                  * core, although some of the other chips have more than
3834                  * one wireless core as well. Check for this and
3835                  * bail out early.
3836                  */
3837                 if (!pdev ||
3838                     ((pdev->device != 0x4321) &&
3839                      (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
3840                         b43dbg(wl, "Ignoring unconnected 802.11 core\n");
3841                         return -ENODEV;
3842                 }
3843         }
3844
3845         wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
3846         if (!wldev)
3847                 goto out;
3848
3849         wldev->dev = dev;
3850         wldev->wl = wl;
3851         b43_set_status(wldev, B43_STAT_UNINIT);
3852         wldev->bad_frames_preempt = modparam_bad_frames_preempt;
3853         tasklet_init(&wldev->isr_tasklet,
3854                      (void (*)(unsigned long))b43_interrupt_tasklet,
3855                      (unsigned long)wldev);
3856         if (modparam_pio)
3857                 wldev->__using_pio = 1;
3858         INIT_LIST_HEAD(&wldev->list);
3859
3860         err = b43_wireless_core_attach(wldev);
3861         if (err)
3862                 goto err_kfree_wldev;
3863
3864         list_add(&wldev->list, &wl->devlist);
3865         wl->nr_devs++;
3866         ssb_set_drvdata(dev, wldev);
3867         b43_debugfs_add_device(wldev);
3868
3869       out:
3870         return err;
3871
3872       err_kfree_wldev:
3873         kfree(wldev);
3874         return err;
3875 }
3876
3877 static void b43_sprom_fixup(struct ssb_bus *bus)
3878 {
3879         /* boardflags workarounds */
3880         if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
3881             bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
3882                 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
3883         if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3884             bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
3885                 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
3886
3887         /* Handle case when gain is not set in sprom */
3888         if (bus->sprom.antenna_gain_a == 0xFF)
3889                 bus->sprom.antenna_gain_a = 2;
3890         if (bus->sprom.antenna_gain_bg == 0xFF)
3891                 bus->sprom.antenna_gain_bg = 2;
3892
3893         /* Convert Antennagain values to Q5.2 */
3894         bus->sprom.antenna_gain_a <<= 2;
3895         bus->sprom.antenna_gain_bg <<= 2;
3896 }
3897
3898 static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
3899 {
3900         struct ieee80211_hw *hw = wl->hw;
3901
3902         ssb_set_devtypedata(dev, NULL);
3903         ieee80211_free_hw(hw);
3904 }
3905
3906 static int b43_wireless_init(struct ssb_device *dev)
3907 {
3908         struct ssb_sprom *sprom = &dev->bus->sprom;
3909         struct ieee80211_hw *hw;
3910         struct b43_wl *wl;
3911         int err = -ENOMEM;
3912
3913         b43_sprom_fixup(dev->bus);
3914
3915         hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
3916         if (!hw) {
3917                 b43err(NULL, "Could not allocate ieee80211 device\n");
3918                 goto out;
3919         }
3920
3921         /* fill hw info */
3922         hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
3923                     IEEE80211_HW_RX_INCLUDES_FCS;
3924         hw->max_signal = 100;
3925         hw->max_rssi = -110;
3926         hw->max_noise = -110;
3927         hw->queues = 1;         /* FIXME: hardware has more queues */
3928         SET_IEEE80211_DEV(hw, dev->dev);
3929         if (is_valid_ether_addr(sprom->et1mac))
3930                 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
3931         else
3932                 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
3933
3934         /* Get and initialize struct b43_wl */
3935         wl = hw_to_b43_wl(hw);
3936         memset(wl, 0, sizeof(*wl));
3937         wl->hw = hw;
3938         spin_lock_init(&wl->irq_lock);
3939         spin_lock_init(&wl->leds_lock);
3940         mutex_init(&wl->mutex);
3941         INIT_LIST_HEAD(&wl->devlist);
3942
3943         ssb_set_devtypedata(dev, wl);
3944         b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
3945         err = 0;
3946       out:
3947         return err;
3948 }
3949
3950 static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
3951 {
3952         struct b43_wl *wl;
3953         int err;
3954         int first = 0;
3955
3956         wl = ssb_get_devtypedata(dev);
3957         if (!wl) {
3958                 /* Probing the first core. Must setup common struct b43_wl */
3959                 first = 1;
3960                 err = b43_wireless_init(dev);
3961                 if (err)
3962                         goto out;
3963                 wl = ssb_get_devtypedata(dev);
3964                 B43_WARN_ON(!wl);
3965         }
3966         err = b43_one_core_attach(dev, wl);
3967         if (err)
3968                 goto err_wireless_exit;
3969
3970         if (first) {
3971                 err = ieee80211_register_hw(wl->hw);
3972                 if (err)
3973                         goto err_one_core_detach;
3974         }
3975
3976       out:
3977         return err;
3978
3979       err_one_core_detach:
3980         b43_one_core_detach(dev);
3981       err_wireless_exit:
3982         if (first)
3983                 b43_wireless_exit(dev, wl);
3984         return err;
3985 }
3986
3987 static void b43_remove(struct ssb_device *dev)
3988 {
3989         struct b43_wl *wl = ssb_get_devtypedata(dev);
3990         struct b43_wldev *wldev = ssb_get_drvdata(dev);
3991
3992         B43_WARN_ON(!wl);
3993         if (wl->current_dev == wldev)
3994                 ieee80211_unregister_hw(wl->hw);
3995
3996         b43_one_core_detach(dev);
3997
3998         if (list_empty(&wl->devlist)) {
3999                 /* Last core on the chip unregistered.
4000                  * We can destroy common struct b43_wl.
4001                  */
4002                 b43_wireless_exit(dev, wl);
4003         }
4004 }
4005
4006 /* Perform a hardware reset. This can be called from any context. */
4007 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
4008 {
4009         /* Must avoid requeueing, if we are in shutdown. */
4010         if (b43_status(dev) < B43_STAT_INITIALIZED)
4011                 return;
4012         b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
4013         queue_work(dev->wl->hw->workqueue, &dev->restart_work);
4014 }
4015
4016 #ifdef CONFIG_PM
4017
4018 static int b43_suspend(struct ssb_device *dev, pm_message_t state)
4019 {
4020         struct b43_wldev *wldev = ssb_get_drvdata(dev);
4021         struct b43_wl *wl = wldev->wl;
4022
4023         b43dbg(wl, "Suspending...\n");
4024
4025         mutex_lock(&wl->mutex);
4026         wldev->suspend_init_status = b43_status(wldev);
4027         if (wldev->suspend_init_status >= B43_STAT_STARTED)
4028                 b43_wireless_core_stop(wldev);
4029         if (wldev->suspend_init_status >= B43_STAT_INITIALIZED)
4030                 b43_wireless_core_exit(wldev);
4031         mutex_unlock(&wl->mutex);
4032
4033         b43dbg(wl, "Device suspended.\n");
4034
4035         return 0;
4036 }
4037
4038 static int b43_resume(struct ssb_device *dev)
4039 {
4040         struct b43_wldev *wldev = ssb_get_drvdata(dev);
4041         struct b43_wl *wl = wldev->wl;
4042         int err = 0;
4043
4044         b43dbg(wl, "Resuming...\n");
4045
4046         mutex_lock(&wl->mutex);
4047         if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
4048                 err = b43_wireless_core_init(wldev);
4049                 if (err) {
4050                         b43err(wl, "Resume failed at core init\n");
4051                         goto out;
4052                 }
4053         }
4054         if (wldev->suspend_init_status >= B43_STAT_STARTED) {
4055                 err = b43_wireless_core_start(wldev);
4056                 if (err) {
4057                         b43_wireless_core_exit(wldev);
4058                         b43err(wl, "Resume failed at core start\n");
4059                         goto out;
4060                 }
4061         }
4062         mutex_unlock(&wl->mutex);
4063
4064         b43dbg(wl, "Device resumed.\n");
4065       out:
4066         return err;
4067 }
4068
4069 #else /* CONFIG_PM */
4070 # define b43_suspend    NULL
4071 # define b43_resume     NULL
4072 #endif /* CONFIG_PM */
4073
4074 static struct ssb_driver b43_ssb_driver = {
4075         .name           = KBUILD_MODNAME,
4076         .id_table       = b43_ssb_tbl,
4077         .probe          = b43_probe,
4078         .remove         = b43_remove,
4079         .suspend        = b43_suspend,
4080         .resume         = b43_resume,
4081 };
4082
4083 static int __init b43_init(void)
4084 {
4085         int err;
4086
4087         b43_debugfs_init();
4088         err = b43_pcmcia_init();
4089         if (err)
4090                 goto err_dfs_exit;
4091         err = ssb_driver_register(&b43_ssb_driver);
4092         if (err)
4093                 goto err_pcmcia_exit;
4094
4095         return err;
4096
4097 err_pcmcia_exit:
4098         b43_pcmcia_exit();
4099 err_dfs_exit:
4100         b43_debugfs_exit();
4101         return err;
4102 }
4103
4104 static void __exit b43_exit(void)
4105 {
4106         ssb_driver_unregister(&b43_ssb_driver);
4107         b43_pcmcia_exit();
4108         b43_debugfs_exit();
4109 }
4110
4111 module_init(b43_init)
4112 module_exit(b43_exit)