3 Broadcom B43 wireless driver
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
7 Copyright (c) 2005-2009 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
31 #include <linux/delay.h>
32 #include <linux/init.h>
33 #include <linux/moduleparam.h>
34 #include <linux/if_arp.h>
35 #include <linux/etherdevice.h>
36 #include <linux/firmware.h>
37 #include <linux/wireless.h>
38 #include <linux/workqueue.h>
39 #include <linux/skbuff.h>
41 #include <linux/dma-mapping.h>
42 #include <asm/unaligned.h>
47 #include "phy_common.h"
57 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
58 MODULE_AUTHOR("Martin Langer");
59 MODULE_AUTHOR("Stefano Brivio");
60 MODULE_AUTHOR("Michael Buesch");
61 MODULE_AUTHOR("Gábor Stefanik");
62 MODULE_LICENSE("GPL");
64 MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID);
67 static int modparam_bad_frames_preempt;
68 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
69 MODULE_PARM_DESC(bad_frames_preempt,
70 "enable(1) / disable(0) Bad Frames Preemption");
72 static char modparam_fwpostfix[16];
73 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
74 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
76 static int modparam_hwpctl;
77 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
78 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
80 static int modparam_nohwcrypt;
81 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
82 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
84 static int modparam_hwtkip;
85 module_param_named(hwtkip, modparam_hwtkip, int, 0444);
86 MODULE_PARM_DESC(hwtkip, "Enable hardware tkip.");
88 static int modparam_qos = 1;
89 module_param_named(qos, modparam_qos, int, 0444);
90 MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
92 static int modparam_btcoex = 1;
93 module_param_named(btcoex, modparam_btcoex, int, 0444);
94 MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistence (default on)");
96 int b43_modparam_verbose = B43_VERBOSITY_DEFAULT;
97 module_param_named(verbose, b43_modparam_verbose, int, 0644);
98 MODULE_PARM_DESC(verbose, "Log message verbosity: 0=error, 1=warn, 2=info(default), 3=debug");
101 static const struct ssb_device_id b43_ssb_tbl[] = {
102 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
103 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
104 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
105 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
106 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
107 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
108 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
109 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 15),
110 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 16),
114 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
116 /* Channel and ratetables are shared for all devices.
117 * They can't be const, because ieee80211 puts some precalculated
118 * data in there. This data is the same for all devices, so we don't
119 * get concurrency issues */
120 #define RATETAB_ENT(_rateid, _flags) \
122 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
123 .hw_value = (_rateid), \
128 * NOTE: When changing this, sync with xmit.c's
129 * b43_plcp_get_bitrate_idx_* functions!
131 static struct ieee80211_rate __b43_ratetable[] = {
132 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
133 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
134 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
135 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
136 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
137 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
138 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
139 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
140 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
141 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
142 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
143 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
146 #define b43_a_ratetable (__b43_ratetable + 4)
147 #define b43_a_ratetable_size 8
148 #define b43_b_ratetable (__b43_ratetable + 0)
149 #define b43_b_ratetable_size 4
150 #define b43_g_ratetable (__b43_ratetable + 0)
151 #define b43_g_ratetable_size 12
153 #define CHAN4G(_channel, _freq, _flags) { \
154 .band = IEEE80211_BAND_2GHZ, \
155 .center_freq = (_freq), \
156 .hw_value = (_channel), \
158 .max_antenna_gain = 0, \
161 static struct ieee80211_channel b43_2ghz_chantable[] = {
179 #define CHAN5G(_channel, _flags) { \
180 .band = IEEE80211_BAND_5GHZ, \
181 .center_freq = 5000 + (5 * (_channel)), \
182 .hw_value = (_channel), \
184 .max_antenna_gain = 0, \
187 static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
188 CHAN5G(32, 0), CHAN5G(34, 0),
189 CHAN5G(36, 0), CHAN5G(38, 0),
190 CHAN5G(40, 0), CHAN5G(42, 0),
191 CHAN5G(44, 0), CHAN5G(46, 0),
192 CHAN5G(48, 0), CHAN5G(50, 0),
193 CHAN5G(52, 0), CHAN5G(54, 0),
194 CHAN5G(56, 0), CHAN5G(58, 0),
195 CHAN5G(60, 0), CHAN5G(62, 0),
196 CHAN5G(64, 0), CHAN5G(66, 0),
197 CHAN5G(68, 0), CHAN5G(70, 0),
198 CHAN5G(72, 0), CHAN5G(74, 0),
199 CHAN5G(76, 0), CHAN5G(78, 0),
200 CHAN5G(80, 0), CHAN5G(82, 0),
201 CHAN5G(84, 0), CHAN5G(86, 0),
202 CHAN5G(88, 0), CHAN5G(90, 0),
203 CHAN5G(92, 0), CHAN5G(94, 0),
204 CHAN5G(96, 0), CHAN5G(98, 0),
205 CHAN5G(100, 0), CHAN5G(102, 0),
206 CHAN5G(104, 0), CHAN5G(106, 0),
207 CHAN5G(108, 0), CHAN5G(110, 0),
208 CHAN5G(112, 0), CHAN5G(114, 0),
209 CHAN5G(116, 0), CHAN5G(118, 0),
210 CHAN5G(120, 0), CHAN5G(122, 0),
211 CHAN5G(124, 0), CHAN5G(126, 0),
212 CHAN5G(128, 0), CHAN5G(130, 0),
213 CHAN5G(132, 0), CHAN5G(134, 0),
214 CHAN5G(136, 0), CHAN5G(138, 0),
215 CHAN5G(140, 0), CHAN5G(142, 0),
216 CHAN5G(144, 0), CHAN5G(145, 0),
217 CHAN5G(146, 0), CHAN5G(147, 0),
218 CHAN5G(148, 0), CHAN5G(149, 0),
219 CHAN5G(150, 0), CHAN5G(151, 0),
220 CHAN5G(152, 0), CHAN5G(153, 0),
221 CHAN5G(154, 0), CHAN5G(155, 0),
222 CHAN5G(156, 0), CHAN5G(157, 0),
223 CHAN5G(158, 0), CHAN5G(159, 0),
224 CHAN5G(160, 0), CHAN5G(161, 0),
225 CHAN5G(162, 0), CHAN5G(163, 0),
226 CHAN5G(164, 0), CHAN5G(165, 0),
227 CHAN5G(166, 0), CHAN5G(168, 0),
228 CHAN5G(170, 0), CHAN5G(172, 0),
229 CHAN5G(174, 0), CHAN5G(176, 0),
230 CHAN5G(178, 0), CHAN5G(180, 0),
231 CHAN5G(182, 0), CHAN5G(184, 0),
232 CHAN5G(186, 0), CHAN5G(188, 0),
233 CHAN5G(190, 0), CHAN5G(192, 0),
234 CHAN5G(194, 0), CHAN5G(196, 0),
235 CHAN5G(198, 0), CHAN5G(200, 0),
236 CHAN5G(202, 0), CHAN5G(204, 0),
237 CHAN5G(206, 0), CHAN5G(208, 0),
238 CHAN5G(210, 0), CHAN5G(212, 0),
239 CHAN5G(214, 0), CHAN5G(216, 0),
240 CHAN5G(218, 0), CHAN5G(220, 0),
241 CHAN5G(222, 0), CHAN5G(224, 0),
242 CHAN5G(226, 0), CHAN5G(228, 0),
245 static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
246 CHAN5G(34, 0), CHAN5G(36, 0),
247 CHAN5G(38, 0), CHAN5G(40, 0),
248 CHAN5G(42, 0), CHAN5G(44, 0),
249 CHAN5G(46, 0), CHAN5G(48, 0),
250 CHAN5G(52, 0), CHAN5G(56, 0),
251 CHAN5G(60, 0), CHAN5G(64, 0),
252 CHAN5G(100, 0), CHAN5G(104, 0),
253 CHAN5G(108, 0), CHAN5G(112, 0),
254 CHAN5G(116, 0), CHAN5G(120, 0),
255 CHAN5G(124, 0), CHAN5G(128, 0),
256 CHAN5G(132, 0), CHAN5G(136, 0),
257 CHAN5G(140, 0), CHAN5G(149, 0),
258 CHAN5G(153, 0), CHAN5G(157, 0),
259 CHAN5G(161, 0), CHAN5G(165, 0),
260 CHAN5G(184, 0), CHAN5G(188, 0),
261 CHAN5G(192, 0), CHAN5G(196, 0),
262 CHAN5G(200, 0), CHAN5G(204, 0),
263 CHAN5G(208, 0), CHAN5G(212, 0),
268 static struct ieee80211_supported_band b43_band_5GHz_nphy = {
269 .band = IEEE80211_BAND_5GHZ,
270 .channels = b43_5ghz_nphy_chantable,
271 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
272 .bitrates = b43_a_ratetable,
273 .n_bitrates = b43_a_ratetable_size,
276 static struct ieee80211_supported_band b43_band_5GHz_aphy = {
277 .band = IEEE80211_BAND_5GHZ,
278 .channels = b43_5ghz_aphy_chantable,
279 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
280 .bitrates = b43_a_ratetable,
281 .n_bitrates = b43_a_ratetable_size,
284 static struct ieee80211_supported_band b43_band_2GHz = {
285 .band = IEEE80211_BAND_2GHZ,
286 .channels = b43_2ghz_chantable,
287 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
288 .bitrates = b43_g_ratetable,
289 .n_bitrates = b43_g_ratetable_size,
292 static void b43_wireless_core_exit(struct b43_wldev *dev);
293 static int b43_wireless_core_init(struct b43_wldev *dev);
294 static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev);
295 static int b43_wireless_core_start(struct b43_wldev *dev);
297 static int b43_ratelimit(struct b43_wl *wl)
299 if (!wl || !wl->current_dev)
301 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
303 /* We are up and running.
304 * Ratelimit the messages to avoid DoS over the net. */
305 return net_ratelimit();
308 void b43info(struct b43_wl *wl, const char *fmt, ...)
312 if (b43_modparam_verbose < B43_VERBOSITY_INFO)
314 if (!b43_ratelimit(wl))
317 printk(KERN_INFO "b43-%s: ",
318 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
323 void b43err(struct b43_wl *wl, const char *fmt, ...)
327 if (b43_modparam_verbose < B43_VERBOSITY_ERROR)
329 if (!b43_ratelimit(wl))
332 printk(KERN_ERR "b43-%s ERROR: ",
333 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
338 void b43warn(struct b43_wl *wl, const char *fmt, ...)
342 if (b43_modparam_verbose < B43_VERBOSITY_WARN)
344 if (!b43_ratelimit(wl))
347 printk(KERN_WARNING "b43-%s warning: ",
348 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
353 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
357 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
360 printk(KERN_DEBUG "b43-%s debug: ",
361 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
366 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
370 B43_WARN_ON(offset % 4 != 0);
372 macctl = b43_read32(dev, B43_MMIO_MACCTL);
373 if (macctl & B43_MACCTL_BE)
376 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
378 b43_write32(dev, B43_MMIO_RAM_DATA, val);
381 static inline void b43_shm_control_word(struct b43_wldev *dev,
382 u16 routing, u16 offset)
386 /* "offset" is the WORD offset. */
390 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
393 u32 __b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
397 if (routing == B43_SHM_SHARED) {
398 B43_WARN_ON(offset & 0x0001);
399 if (offset & 0x0003) {
400 /* Unaligned access */
401 b43_shm_control_word(dev, routing, offset >> 2);
402 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
403 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
404 ret |= ((u32)b43_read16(dev, B43_MMIO_SHM_DATA)) << 16;
410 b43_shm_control_word(dev, routing, offset);
411 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
416 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
418 struct b43_wl *wl = dev->wl;
422 spin_lock_irqsave(&wl->shm_lock, flags);
423 ret = __b43_shm_read32(dev, routing, offset);
424 spin_unlock_irqrestore(&wl->shm_lock, flags);
429 u16 __b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
433 if (routing == B43_SHM_SHARED) {
434 B43_WARN_ON(offset & 0x0001);
435 if (offset & 0x0003) {
436 /* Unaligned access */
437 b43_shm_control_word(dev, routing, offset >> 2);
438 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
444 b43_shm_control_word(dev, routing, offset);
445 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
450 u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
452 struct b43_wl *wl = dev->wl;
456 spin_lock_irqsave(&wl->shm_lock, flags);
457 ret = __b43_shm_read16(dev, routing, offset);
458 spin_unlock_irqrestore(&wl->shm_lock, flags);
463 void __b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
465 if (routing == B43_SHM_SHARED) {
466 B43_WARN_ON(offset & 0x0001);
467 if (offset & 0x0003) {
468 /* Unaligned access */
469 b43_shm_control_word(dev, routing, offset >> 2);
470 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
472 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
473 b43_write16(dev, B43_MMIO_SHM_DATA,
474 (value >> 16) & 0xFFFF);
479 b43_shm_control_word(dev, routing, offset);
480 b43_write32(dev, B43_MMIO_SHM_DATA, value);
483 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
485 struct b43_wl *wl = dev->wl;
488 spin_lock_irqsave(&wl->shm_lock, flags);
489 __b43_shm_write32(dev, routing, offset, value);
490 spin_unlock_irqrestore(&wl->shm_lock, flags);
493 void __b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
495 if (routing == B43_SHM_SHARED) {
496 B43_WARN_ON(offset & 0x0001);
497 if (offset & 0x0003) {
498 /* Unaligned access */
499 b43_shm_control_word(dev, routing, offset >> 2);
500 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
505 b43_shm_control_word(dev, routing, offset);
506 b43_write16(dev, B43_MMIO_SHM_DATA, value);
509 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
511 struct b43_wl *wl = dev->wl;
514 spin_lock_irqsave(&wl->shm_lock, flags);
515 __b43_shm_write16(dev, routing, offset, value);
516 spin_unlock_irqrestore(&wl->shm_lock, flags);
520 u64 b43_hf_read(struct b43_wldev *dev)
524 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
526 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
528 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
533 /* Write HostFlags */
534 void b43_hf_write(struct b43_wldev *dev, u64 value)
538 lo = (value & 0x00000000FFFFULL);
539 mi = (value & 0x0000FFFF0000ULL) >> 16;
540 hi = (value & 0xFFFF00000000ULL) >> 32;
541 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
542 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
543 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
546 /* Read the firmware capabilities bitmask (Opensource firmware only) */
547 static u16 b43_fwcapa_read(struct b43_wldev *dev)
549 B43_WARN_ON(!dev->fw.opensource);
550 return b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_FWCAPA);
553 void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
557 B43_WARN_ON(dev->dev->id.revision < 3);
559 /* The hardware guarantees us an atomic read, if we
560 * read the low register first. */
561 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
562 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
569 static void b43_time_lock(struct b43_wldev *dev)
573 macctl = b43_read32(dev, B43_MMIO_MACCTL);
574 macctl |= B43_MACCTL_TBTTHOLD;
575 b43_write32(dev, B43_MMIO_MACCTL, macctl);
576 /* Commit the write */
577 b43_read32(dev, B43_MMIO_MACCTL);
580 static void b43_time_unlock(struct b43_wldev *dev)
584 macctl = b43_read32(dev, B43_MMIO_MACCTL);
585 macctl &= ~B43_MACCTL_TBTTHOLD;
586 b43_write32(dev, B43_MMIO_MACCTL, macctl);
587 /* Commit the write */
588 b43_read32(dev, B43_MMIO_MACCTL);
591 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
595 B43_WARN_ON(dev->dev->id.revision < 3);
599 /* The hardware guarantees us an atomic write, if we
600 * write the low register first. */
601 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, low);
603 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, high);
607 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
610 b43_tsf_write_locked(dev, tsf);
611 b43_time_unlock(dev);
615 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 *mac)
617 static const u8 zero_addr[ETH_ALEN] = { 0 };
624 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
628 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
631 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
634 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
637 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
641 u8 mac_bssid[ETH_ALEN * 2];
645 bssid = dev->wl->bssid;
646 mac = dev->wl->mac_addr;
648 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
650 memcpy(mac_bssid, mac, ETH_ALEN);
651 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
653 /* Write our MAC address and BSSID to template ram */
654 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
655 tmp = (u32) (mac_bssid[i + 0]);
656 tmp |= (u32) (mac_bssid[i + 1]) << 8;
657 tmp |= (u32) (mac_bssid[i + 2]) << 16;
658 tmp |= (u32) (mac_bssid[i + 3]) << 24;
659 b43_ram_write(dev, 0x20 + i, tmp);
663 static void b43_upload_card_macaddress(struct b43_wldev *dev)
665 b43_write_mac_bssid_templates(dev);
666 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
669 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
671 /* slot_time is in usec. */
672 if (dev->phy.type != B43_PHYTYPE_G)
674 b43_write16(dev, 0x684, 510 + slot_time);
675 b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
678 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
680 b43_set_slot_time(dev, 9);
683 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
685 b43_set_slot_time(dev, 20);
688 /* DummyTransmission function, as documented on
689 * http://bcm-v4.sipsolutions.net/802.11/DummyTransmission
691 void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on)
693 struct b43_phy *phy = &dev->phy;
694 unsigned int i, max_loop;
706 buffer[0] = 0x000201CC;
709 buffer[0] = 0x000B846E;
712 for (i = 0; i < 5; i++)
713 b43_ram_write(dev, i * 4, buffer[i]);
715 b43_write16(dev, 0x0568, 0x0000);
716 if (dev->dev->id.revision < 11)
717 b43_write16(dev, 0x07C0, 0x0000);
719 b43_write16(dev, 0x07C0, 0x0100);
720 value = (ofdm ? 0x41 : 0x40);
721 b43_write16(dev, 0x050C, value);
722 if ((phy->type == B43_PHYTYPE_N) || (phy->type == B43_PHYTYPE_LP))
723 b43_write16(dev, 0x0514, 0x1A02);
724 b43_write16(dev, 0x0508, 0x0000);
725 b43_write16(dev, 0x050A, 0x0000);
726 b43_write16(dev, 0x054C, 0x0000);
727 b43_write16(dev, 0x056A, 0x0014);
728 b43_write16(dev, 0x0568, 0x0826);
729 b43_write16(dev, 0x0500, 0x0000);
730 if (!pa_on && (phy->type == B43_PHYTYPE_N)) {
736 b43_write16(dev, 0x0502, 0x00D0);
739 b43_write16(dev, 0x0502, 0x0050);
742 b43_write16(dev, 0x0502, 0x0030);
745 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
746 b43_radio_write16(dev, 0x0051, 0x0017);
747 for (i = 0x00; i < max_loop; i++) {
748 value = b43_read16(dev, 0x050E);
753 for (i = 0x00; i < 0x0A; i++) {
754 value = b43_read16(dev, 0x050E);
759 for (i = 0x00; i < 0x19; i++) {
760 value = b43_read16(dev, 0x0690);
761 if (!(value & 0x0100))
765 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
766 b43_radio_write16(dev, 0x0051, 0x0037);
769 static void key_write(struct b43_wldev *dev,
770 u8 index, u8 algorithm, const u8 *key)
777 /* Key index/algo block */
778 kidx = b43_kidx_to_fw(dev, index);
779 value = ((kidx << 4) | algorithm);
780 b43_shm_write16(dev, B43_SHM_SHARED,
781 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
783 /* Write the key to the Key Table Pointer offset */
784 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
785 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
787 value |= (u16) (key[i + 1]) << 8;
788 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
792 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 *addr)
794 u32 addrtmp[2] = { 0, 0, };
795 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
797 if (b43_new_kidx_api(dev))
798 pairwise_keys_start = B43_NR_GROUP_KEYS;
800 B43_WARN_ON(index < pairwise_keys_start);
801 /* We have four default TX keys and possibly four default RX keys.
802 * Physical mac 0 is mapped to physical key 4 or 8, depending
803 * on the firmware version.
804 * So we must adjust the index here.
806 index -= pairwise_keys_start;
807 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
810 addrtmp[0] = addr[0];
811 addrtmp[0] |= ((u32) (addr[1]) << 8);
812 addrtmp[0] |= ((u32) (addr[2]) << 16);
813 addrtmp[0] |= ((u32) (addr[3]) << 24);
814 addrtmp[1] = addr[4];
815 addrtmp[1] |= ((u32) (addr[5]) << 8);
818 /* Receive match transmitter address (RCMTA) mechanism */
819 b43_shm_write32(dev, B43_SHM_RCMTA,
820 (index * 2) + 0, addrtmp[0]);
821 b43_shm_write16(dev, B43_SHM_RCMTA,
822 (index * 2) + 1, addrtmp[1]);
825 /* The ucode will use phase1 key with TEK key to decrypt rx packets.
826 * When a packet is received, the iv32 is checked.
827 * - if it doesn't the packet is returned without modification (and software
828 * decryption can be done). That's what happen when iv16 wrap.
829 * - if it does, the rc4 key is computed, and decryption is tried.
830 * Either it will success and B43_RX_MAC_DEC is returned,
831 * either it fails and B43_RX_MAC_DEC|B43_RX_MAC_DECERR is returned
832 * and the packet is not usable (it got modified by the ucode).
833 * So in order to never have B43_RX_MAC_DECERR, we should provide
834 * a iv32 and phase1key that match. Because we drop packets in case of
835 * B43_RX_MAC_DECERR, if we have a correct iv32 but a wrong phase1key, all
836 * packets will be lost without higher layer knowing (ie no resync possible
839 * NOTE : this should support 50 key like RCMTA because
840 * (B43_SHM_SH_KEYIDXBLOCK - B43_SHM_SH_TKIPTSCTTAK)/14 = 50
842 static void rx_tkip_phase1_write(struct b43_wldev *dev, u8 index, u32 iv32,
847 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
849 if (!modparam_hwtkip)
852 if (b43_new_kidx_api(dev))
853 pairwise_keys_start = B43_NR_GROUP_KEYS;
855 B43_WARN_ON(index < pairwise_keys_start);
856 /* We have four default TX keys and possibly four default RX keys.
857 * Physical mac 0 is mapped to physical key 4 or 8, depending
858 * on the firmware version.
859 * So we must adjust the index here.
861 index -= pairwise_keys_start;
862 B43_WARN_ON(index >= B43_NR_PAIRWISE_KEYS);
864 if (b43_debug(dev, B43_DBG_KEYS)) {
865 b43dbg(dev->wl, "rx_tkip_phase1_write : idx 0x%x, iv32 0x%x\n",
868 /* Write the key to the RX tkip shared mem */
869 offset = B43_SHM_SH_TKIPTSCTTAK + index * (10 + 4);
870 for (i = 0; i < 10; i += 2) {
871 b43_shm_write16(dev, B43_SHM_SHARED, offset + i,
872 phase1key ? phase1key[i / 2] : 0);
874 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, iv32);
875 b43_shm_write16(dev, B43_SHM_SHARED, offset + i + 2, iv32 >> 16);
878 static void b43_op_update_tkip_key(struct ieee80211_hw *hw,
879 struct ieee80211_key_conf *keyconf, const u8 *addr,
880 u32 iv32, u16 *phase1key)
882 struct b43_wl *wl = hw_to_b43_wl(hw);
883 struct b43_wldev *dev;
884 int index = keyconf->hw_key_idx;
886 if (B43_WARN_ON(!modparam_hwtkip))
889 mutex_lock(&wl->mutex);
891 dev = wl->current_dev;
892 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
895 keymac_write(dev, index, NULL); /* First zero out mac to avoid race */
897 rx_tkip_phase1_write(dev, index, iv32, phase1key);
898 keymac_write(dev, index, addr);
901 mutex_unlock(&wl->mutex);
904 static void do_key_write(struct b43_wldev *dev,
905 u8 index, u8 algorithm,
906 const u8 *key, size_t key_len, const u8 *mac_addr)
908 u8 buf[B43_SEC_KEYSIZE] = { 0, };
909 u8 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
911 if (b43_new_kidx_api(dev))
912 pairwise_keys_start = B43_NR_GROUP_KEYS;
914 B43_WARN_ON(index >= ARRAY_SIZE(dev->key));
915 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
917 if (index >= pairwise_keys_start)
918 keymac_write(dev, index, NULL); /* First zero out mac. */
919 if (algorithm == B43_SEC_ALGO_TKIP) {
921 * We should provide an initial iv32, phase1key pair.
922 * We could start with iv32=0 and compute the corresponding
923 * phase1key, but this means calling ieee80211_get_tkip_key
924 * with a fake skb (or export other tkip function).
925 * Because we are lazy we hope iv32 won't start with
926 * 0xffffffff and let's b43_op_update_tkip_key provide a
929 rx_tkip_phase1_write(dev, index, 0xffffffff, (u16*)buf);
930 } else if (index >= pairwise_keys_start) /* clear it */
931 rx_tkip_phase1_write(dev, index, 0, NULL);
933 memcpy(buf, key, key_len);
934 key_write(dev, index, algorithm, buf);
935 if (index >= pairwise_keys_start)
936 keymac_write(dev, index, mac_addr);
938 dev->key[index].algorithm = algorithm;
941 static int b43_key_write(struct b43_wldev *dev,
942 int index, u8 algorithm,
943 const u8 *key, size_t key_len,
945 struct ieee80211_key_conf *keyconf)
948 int pairwise_keys_start;
950 /* For ALG_TKIP the key is encoded as a 256-bit (32 byte) data block:
951 * - Temporal Encryption Key (128 bits)
952 * - Temporal Authenticator Tx MIC Key (64 bits)
953 * - Temporal Authenticator Rx MIC Key (64 bits)
955 * Hardware only store TEK
957 if (algorithm == B43_SEC_ALGO_TKIP && key_len == 32)
959 if (key_len > B43_SEC_KEYSIZE)
961 for (i = 0; i < ARRAY_SIZE(dev->key); i++) {
962 /* Check that we don't already have this key. */
963 B43_WARN_ON(dev->key[i].keyconf == keyconf);
966 /* Pairwise key. Get an empty slot for the key. */
967 if (b43_new_kidx_api(dev))
968 pairwise_keys_start = B43_NR_GROUP_KEYS;
970 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
971 for (i = pairwise_keys_start;
972 i < pairwise_keys_start + B43_NR_PAIRWISE_KEYS;
974 B43_WARN_ON(i >= ARRAY_SIZE(dev->key));
975 if (!dev->key[i].keyconf) {
982 b43warn(dev->wl, "Out of hardware key memory\n");
986 B43_WARN_ON(index > 3);
988 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
989 if ((index <= 3) && !b43_new_kidx_api(dev)) {
991 B43_WARN_ON(mac_addr);
992 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
994 keyconf->hw_key_idx = index;
995 dev->key[index].keyconf = keyconf;
1000 static int b43_key_clear(struct b43_wldev *dev, int index)
1002 if (B43_WARN_ON((index < 0) || (index >= ARRAY_SIZE(dev->key))))
1004 do_key_write(dev, index, B43_SEC_ALGO_NONE,
1005 NULL, B43_SEC_KEYSIZE, NULL);
1006 if ((index <= 3) && !b43_new_kidx_api(dev)) {
1007 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
1008 NULL, B43_SEC_KEYSIZE, NULL);
1010 dev->key[index].keyconf = NULL;
1015 static void b43_clear_keys(struct b43_wldev *dev)
1019 if (b43_new_kidx_api(dev))
1020 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1022 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1023 for (i = 0; i < count; i++)
1024 b43_key_clear(dev, i);
1027 static void b43_dump_keymemory(struct b43_wldev *dev)
1029 unsigned int i, index, count, offset, pairwise_keys_start;
1035 struct b43_key *key;
1037 if (!b43_debug(dev, B43_DBG_KEYS))
1040 hf = b43_hf_read(dev);
1041 b43dbg(dev->wl, "Hardware key memory dump: USEDEFKEYS=%u\n",
1042 !!(hf & B43_HF_USEDEFKEYS));
1043 if (b43_new_kidx_api(dev)) {
1044 pairwise_keys_start = B43_NR_GROUP_KEYS;
1045 count = B43_NR_GROUP_KEYS + B43_NR_PAIRWISE_KEYS;
1047 pairwise_keys_start = B43_NR_GROUP_KEYS * 2;
1048 count = B43_NR_GROUP_KEYS * 2 + B43_NR_PAIRWISE_KEYS;
1050 for (index = 0; index < count; index++) {
1051 key = &(dev->key[index]);
1052 printk(KERN_DEBUG "Key slot %02u: %s",
1053 index, (key->keyconf == NULL) ? " " : "*");
1054 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
1055 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
1056 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1057 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1060 algo = b43_shm_read16(dev, B43_SHM_SHARED,
1061 B43_SHM_SH_KEYIDXBLOCK + (index * 2));
1062 printk(" Algo: %04X/%02X", algo, key->algorithm);
1064 if (index >= pairwise_keys_start) {
1065 if (key->algorithm == B43_SEC_ALGO_TKIP) {
1067 offset = B43_SHM_SH_TKIPTSCTTAK + (index - 4) * (10 + 4);
1068 for (i = 0; i < 14; i += 2) {
1069 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, offset + i);
1070 printk("%02X%02X", (tmp & 0xFF), ((tmp >> 8) & 0xFF));
1073 rcmta0 = b43_shm_read32(dev, B43_SHM_RCMTA,
1074 ((index - pairwise_keys_start) * 2) + 0);
1075 rcmta1 = b43_shm_read16(dev, B43_SHM_RCMTA,
1076 ((index - pairwise_keys_start) * 2) + 1);
1077 *((__le32 *)(&mac[0])) = cpu_to_le32(rcmta0);
1078 *((__le16 *)(&mac[4])) = cpu_to_le16(rcmta1);
1079 printk(" MAC: %pM", mac);
1081 printk(" DEFAULT KEY");
1086 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
1094 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
1095 (ps_flags & B43_PS_DISABLED));
1096 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
1098 if (ps_flags & B43_PS_ENABLED) {
1100 } else if (ps_flags & B43_PS_DISABLED) {
1103 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1104 // and thus is not an AP and we are associated, set bit 25
1106 if (ps_flags & B43_PS_AWAKE) {
1108 } else if (ps_flags & B43_PS_ASLEEP) {
1111 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1112 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1113 // successful, set bit26
1116 /* FIXME: For now we force awake-on and hwps-off */
1120 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1122 macctl |= B43_MACCTL_HWPS;
1124 macctl &= ~B43_MACCTL_HWPS;
1126 macctl |= B43_MACCTL_AWAKE;
1128 macctl &= ~B43_MACCTL_AWAKE;
1129 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1131 b43_read32(dev, B43_MMIO_MACCTL);
1132 if (awake && dev->dev->id.revision >= 5) {
1133 /* Wait for the microcode to wake up. */
1134 for (i = 0; i < 100; i++) {
1135 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1136 B43_SHM_SH_UCODESTAT);
1137 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1144 void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
1149 flags |= B43_TMSLOW_PHYCLKEN;
1150 flags |= B43_TMSLOW_PHYRESET;
1151 ssb_device_enable(dev->dev, flags);
1152 msleep(2); /* Wait for the PLL to turn on. */
1154 /* Now take the PHY out of Reset again */
1155 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
1156 tmslow |= SSB_TMSLOW_FGC;
1157 tmslow &= ~B43_TMSLOW_PHYRESET;
1158 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1159 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1161 tmslow &= ~SSB_TMSLOW_FGC;
1162 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1163 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1166 /* Turn Analog ON, but only if we already know the PHY-type.
1167 * This protects against very early setup where we don't know the
1168 * PHY-type, yet. wireless_core_reset will be called once again later,
1169 * when we know the PHY-type. */
1171 dev->phy.ops->switch_analog(dev, 1);
1173 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1174 macctl &= ~B43_MACCTL_GMODE;
1175 if (flags & B43_TMSLOW_GMODE)
1176 macctl |= B43_MACCTL_GMODE;
1177 macctl |= B43_MACCTL_IHR_ENABLED;
1178 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1181 static void handle_irq_transmit_status(struct b43_wldev *dev)
1185 struct b43_txstatus stat;
1188 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1189 if (!(v0 & 0x00000001))
1191 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1193 stat.cookie = (v0 >> 16);
1194 stat.seq = (v1 & 0x0000FFFF);
1195 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1196 tmp = (v0 & 0x0000FFFF);
1197 stat.frame_count = ((tmp & 0xF000) >> 12);
1198 stat.rts_count = ((tmp & 0x0F00) >> 8);
1199 stat.supp_reason = ((tmp & 0x001C) >> 2);
1200 stat.pm_indicated = !!(tmp & 0x0080);
1201 stat.intermediate = !!(tmp & 0x0040);
1202 stat.for_ampdu = !!(tmp & 0x0020);
1203 stat.acked = !!(tmp & 0x0002);
1205 b43_handle_txstatus(dev, &stat);
1209 static void drain_txstatus_queue(struct b43_wldev *dev)
1213 if (dev->dev->id.revision < 5)
1215 /* Read all entries from the microcode TXstatus FIFO
1216 * and throw them away.
1219 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1220 if (!(dummy & 0x00000001))
1222 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1226 static u32 b43_jssi_read(struct b43_wldev *dev)
1230 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1232 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1237 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1239 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1240 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1243 static void b43_generate_noise_sample(struct b43_wldev *dev)
1245 b43_jssi_write(dev, 0x7F7F7F7F);
1246 b43_write32(dev, B43_MMIO_MACCMD,
1247 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
1250 static void b43_calculate_link_quality(struct b43_wldev *dev)
1252 /* Top half of Link Quality calculation. */
1254 if (dev->phy.type != B43_PHYTYPE_G)
1256 if (dev->noisecalc.calculation_running)
1258 dev->noisecalc.calculation_running = 1;
1259 dev->noisecalc.nr_samples = 0;
1261 b43_generate_noise_sample(dev);
1264 static void handle_irq_noise(struct b43_wldev *dev)
1266 struct b43_phy_g *phy = dev->phy.g;
1272 /* Bottom half of Link Quality calculation. */
1274 if (dev->phy.type != B43_PHYTYPE_G)
1277 /* Possible race condition: It might be possible that the user
1278 * changed to a different channel in the meantime since we
1279 * started the calculation. We ignore that fact, since it's
1280 * not really that much of a problem. The background noise is
1281 * an estimation only anyway. Slightly wrong results will get damped
1282 * by the averaging of the 8 sample rounds. Additionally the
1283 * value is shortlived. So it will be replaced by the next noise
1284 * calculation round soon. */
1286 B43_WARN_ON(!dev->noisecalc.calculation_running);
1287 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1288 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1289 noise[2] == 0x7F || noise[3] == 0x7F)
1292 /* Get the noise samples. */
1293 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1294 i = dev->noisecalc.nr_samples;
1295 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1296 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1297 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1298 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1299 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1300 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1301 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1302 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1303 dev->noisecalc.nr_samples++;
1304 if (dev->noisecalc.nr_samples == 8) {
1305 /* Calculate the Link Quality by the noise samples. */
1307 for (i = 0; i < 8; i++) {
1308 for (j = 0; j < 4; j++)
1309 average += dev->noisecalc.samples[i][j];
1315 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1316 tmp = (tmp / 128) & 0x1F;
1326 dev->stats.link_noise = average;
1327 dev->noisecalc.calculation_running = 0;
1331 b43_generate_noise_sample(dev);
1334 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1336 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
1339 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1340 b43_power_saving_ctl_bits(dev, 0);
1342 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
1346 static void handle_irq_atim_end(struct b43_wldev *dev)
1348 if (dev->dfq_valid) {
1349 b43_write32(dev, B43_MMIO_MACCMD,
1350 b43_read32(dev, B43_MMIO_MACCMD)
1351 | B43_MACCMD_DFQ_VALID);
1356 static void handle_irq_pmq(struct b43_wldev *dev)
1363 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1364 if (!(tmp & 0x00000008))
1367 /* 16bit write is odd, but correct. */
1368 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1371 static void b43_write_template_common(struct b43_wldev *dev,
1372 const u8 *data, u16 size,
1374 u16 shm_size_offset, u8 rate)
1377 struct b43_plcp_hdr4 plcp;
1380 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1381 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1382 ram_offset += sizeof(u32);
1383 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1384 * So leave the first two bytes of the next write blank.
1386 tmp = (u32) (data[0]) << 16;
1387 tmp |= (u32) (data[1]) << 24;
1388 b43_ram_write(dev, ram_offset, tmp);
1389 ram_offset += sizeof(u32);
1390 for (i = 2; i < size; i += sizeof(u32)) {
1391 tmp = (u32) (data[i + 0]);
1393 tmp |= (u32) (data[i + 1]) << 8;
1395 tmp |= (u32) (data[i + 2]) << 16;
1397 tmp |= (u32) (data[i + 3]) << 24;
1398 b43_ram_write(dev, ram_offset + i - 2, tmp);
1400 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1401 size + sizeof(struct b43_plcp_hdr6));
1404 /* Check if the use of the antenna that ieee80211 told us to
1405 * use is possible. This will fall back to DEFAULT.
1406 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1407 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1412 if (antenna_nr == 0) {
1413 /* Zero means "use default antenna". That's always OK. */
1417 /* Get the mask of available antennas. */
1419 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
1421 antenna_mask = dev->dev->bus->sprom.ant_available_a;
1423 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1424 /* This antenna is not available. Fall back to default. */
1431 /* Convert a b43 antenna number value to the PHY TX control value. */
1432 static u16 b43_antenna_to_phyctl(int antenna)
1436 return B43_TXH_PHY_ANT0;
1438 return B43_TXH_PHY_ANT1;
1440 return B43_TXH_PHY_ANT2;
1442 return B43_TXH_PHY_ANT3;
1443 case B43_ANTENNA_AUTO0:
1444 case B43_ANTENNA_AUTO1:
1445 return B43_TXH_PHY_ANT01AUTO;
1451 static void b43_write_beacon_template(struct b43_wldev *dev,
1453 u16 shm_size_offset)
1455 unsigned int i, len, variable_len;
1456 const struct ieee80211_mgmt *bcn;
1462 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
1464 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1465 len = min((size_t) dev->wl->current_beacon->len,
1466 0x200 - sizeof(struct b43_plcp_hdr6));
1467 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
1469 b43_write_template_common(dev, (const u8 *)bcn,
1470 len, ram_offset, shm_size_offset, rate);
1472 /* Write the PHY TX control parameters. */
1473 antenna = B43_ANTENNA_DEFAULT;
1474 antenna = b43_antenna_to_phyctl(antenna);
1475 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1476 /* We can't send beacons with short preamble. Would get PHY errors. */
1477 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1478 ctl &= ~B43_TXH_PHY_ANT;
1479 ctl &= ~B43_TXH_PHY_ENC;
1481 if (b43_is_cck_rate(rate))
1482 ctl |= B43_TXH_PHY_ENC_CCK;
1484 ctl |= B43_TXH_PHY_ENC_OFDM;
1485 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1487 /* Find the position of the TIM and the DTIM_period value
1488 * and write them to SHM. */
1489 ie = bcn->u.beacon.variable;
1490 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1491 for (i = 0; i < variable_len - 2; ) {
1492 uint8_t ie_id, ie_len;
1499 /* This is the TIM Information Element */
1501 /* Check whether the ie_len is in the beacon data range. */
1502 if (variable_len < ie_len + 2 + i)
1504 /* A valid TIM is at least 4 bytes long. */
1509 tim_position = sizeof(struct b43_plcp_hdr6);
1510 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1513 dtim_period = ie[i + 3];
1515 b43_shm_write16(dev, B43_SHM_SHARED,
1516 B43_SHM_SH_TIMBPOS, tim_position);
1517 b43_shm_write16(dev, B43_SHM_SHARED,
1518 B43_SHM_SH_DTIMPER, dtim_period);
1525 * If ucode wants to modify TIM do it behind the beacon, this
1526 * will happen, for example, when doing mesh networking.
1528 b43_shm_write16(dev, B43_SHM_SHARED,
1530 len + sizeof(struct b43_plcp_hdr6));
1531 b43_shm_write16(dev, B43_SHM_SHARED,
1532 B43_SHM_SH_DTIMPER, 0);
1534 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
1537 static void b43_upload_beacon0(struct b43_wldev *dev)
1539 struct b43_wl *wl = dev->wl;
1541 if (wl->beacon0_uploaded)
1543 b43_write_beacon_template(dev, 0x68, 0x18);
1544 wl->beacon0_uploaded = 1;
1547 static void b43_upload_beacon1(struct b43_wldev *dev)
1549 struct b43_wl *wl = dev->wl;
1551 if (wl->beacon1_uploaded)
1553 b43_write_beacon_template(dev, 0x468, 0x1A);
1554 wl->beacon1_uploaded = 1;
1557 static void handle_irq_beacon(struct b43_wldev *dev)
1559 struct b43_wl *wl = dev->wl;
1560 u32 cmd, beacon0_valid, beacon1_valid;
1562 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
1563 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
1566 /* This is the bottom half of the asynchronous beacon update. */
1568 /* Ignore interrupt in the future. */
1569 dev->irq_mask &= ~B43_IRQ_BEACON;
1571 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1572 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1573 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1575 /* Schedule interrupt manually, if busy. */
1576 if (beacon0_valid && beacon1_valid) {
1577 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1578 dev->irq_mask |= B43_IRQ_BEACON;
1582 if (unlikely(wl->beacon_templates_virgin)) {
1583 /* We never uploaded a beacon before.
1584 * Upload both templates now, but only mark one valid. */
1585 wl->beacon_templates_virgin = 0;
1586 b43_upload_beacon0(dev);
1587 b43_upload_beacon1(dev);
1588 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1589 cmd |= B43_MACCMD_BEACON0_VALID;
1590 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1592 if (!beacon0_valid) {
1593 b43_upload_beacon0(dev);
1594 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1595 cmd |= B43_MACCMD_BEACON0_VALID;
1596 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1597 } else if (!beacon1_valid) {
1598 b43_upload_beacon1(dev);
1599 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1600 cmd |= B43_MACCMD_BEACON1_VALID;
1601 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1606 static void b43_do_beacon_update_trigger_work(struct b43_wldev *dev)
1608 u32 old_irq_mask = dev->irq_mask;
1610 /* update beacon right away or defer to irq */
1611 handle_irq_beacon(dev);
1612 if (old_irq_mask != dev->irq_mask) {
1613 /* The handler updated the IRQ mask. */
1614 B43_WARN_ON(!dev->irq_mask);
1615 if (b43_read32(dev, B43_MMIO_GEN_IRQ_MASK)) {
1616 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1618 /* Device interrupts are currently disabled. That means
1619 * we just ran the hardirq handler and scheduled the
1620 * IRQ thread. The thread will write the IRQ mask when
1621 * it finished, so there's nothing to do here. Writing
1622 * the mask _here_ would incorrectly re-enable IRQs. */
1627 static void b43_beacon_update_trigger_work(struct work_struct *work)
1629 struct b43_wl *wl = container_of(work, struct b43_wl,
1630 beacon_update_trigger);
1631 struct b43_wldev *dev;
1633 mutex_lock(&wl->mutex);
1634 dev = wl->current_dev;
1635 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
1636 if (0 /*FIXME dev->dev->bus->bustype == SSB_BUSTYPE_SDIO*/) {
1637 /* wl->mutex is enough. */
1638 b43_do_beacon_update_trigger_work(dev);
1641 spin_lock_irq(&wl->hardirq_lock);
1642 b43_do_beacon_update_trigger_work(dev);
1644 spin_unlock_irq(&wl->hardirq_lock);
1647 mutex_unlock(&wl->mutex);
1650 /* Asynchronously update the packet templates in template RAM.
1651 * Locking: Requires wl->mutex to be locked. */
1652 static void b43_update_templates(struct b43_wl *wl)
1654 struct sk_buff *beacon;
1656 /* This is the top half of the ansynchronous beacon update.
1657 * The bottom half is the beacon IRQ.
1658 * Beacon update must be asynchronous to avoid sending an
1659 * invalid beacon. This can happen for example, if the firmware
1660 * transmits a beacon while we are updating it. */
1662 /* We could modify the existing beacon and set the aid bit in
1663 * the TIM field, but that would probably require resizing and
1664 * moving of data within the beacon template.
1665 * Simply request a new beacon and let mac80211 do the hard work. */
1666 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1667 if (unlikely(!beacon))
1670 if (wl->current_beacon)
1671 dev_kfree_skb_any(wl->current_beacon);
1672 wl->current_beacon = beacon;
1673 wl->beacon0_uploaded = 0;
1674 wl->beacon1_uploaded = 0;
1675 ieee80211_queue_work(wl->hw, &wl->beacon_update_trigger);
1678 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1681 if (dev->dev->id.revision >= 3) {
1682 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1683 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
1685 b43_write16(dev, 0x606, (beacon_int >> 6));
1686 b43_write16(dev, 0x610, beacon_int);
1688 b43_time_unlock(dev);
1689 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
1692 static void b43_handle_firmware_panic(struct b43_wldev *dev)
1696 /* Read the register that contains the reason code for the panic. */
1697 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1698 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1702 b43dbg(dev->wl, "The panic reason is unknown.\n");
1704 case B43_FWPANIC_DIE:
1705 /* Do not restart the controller or firmware.
1706 * The device is nonfunctional from now on.
1707 * Restarting would result in this panic to trigger again,
1708 * so we avoid that recursion. */
1710 case B43_FWPANIC_RESTART:
1711 b43_controller_restart(dev, "Microcode panic");
1716 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1718 unsigned int i, cnt;
1719 u16 reason, marker_id, marker_line;
1722 /* The proprietary firmware doesn't have this IRQ. */
1723 if (!dev->fw.opensource)
1726 /* Read the register that contains the reason code for this IRQ. */
1727 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1730 case B43_DEBUGIRQ_PANIC:
1731 b43_handle_firmware_panic(dev);
1733 case B43_DEBUGIRQ_DUMP_SHM:
1735 break; /* Only with driver debugging enabled. */
1736 buf = kmalloc(4096, GFP_ATOMIC);
1738 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1741 for (i = 0; i < 4096; i += 2) {
1742 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1743 buf[i / 2] = cpu_to_le16(tmp);
1745 b43info(dev->wl, "Shared memory dump:\n");
1746 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1747 16, 2, buf, 4096, 1);
1750 case B43_DEBUGIRQ_DUMP_REGS:
1752 break; /* Only with driver debugging enabled. */
1753 b43info(dev->wl, "Microcode register dump:\n");
1754 for (i = 0, cnt = 0; i < 64; i++) {
1755 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1758 printk("r%02u: 0x%04X ", i, tmp);
1767 case B43_DEBUGIRQ_MARKER:
1769 break; /* Only with driver debugging enabled. */
1770 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1772 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1773 B43_MARKER_LINE_REG);
1774 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1775 "at line number %u\n",
1776 marker_id, marker_line);
1779 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1783 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1784 b43_shm_write16(dev, B43_SHM_SCRATCH,
1785 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
1788 static void b43_do_interrupt_thread(struct b43_wldev *dev)
1791 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1792 u32 merged_dma_reason = 0;
1795 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
1798 reason = dev->irq_reason;
1799 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1800 dma_reason[i] = dev->dma_reason[i];
1801 merged_dma_reason |= dma_reason[i];
1804 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1805 b43err(dev->wl, "MAC transmission error\n");
1807 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1808 b43err(dev->wl, "PHY transmission error\n");
1810 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1811 atomic_set(&dev->phy.txerr_cnt,
1812 B43_PHY_TX_BADNESS_LIMIT);
1813 b43err(dev->wl, "Too many PHY TX errors, "
1814 "restarting the controller\n");
1815 b43_controller_restart(dev, "PHY TX errors");
1819 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1820 B43_DMAIRQ_NONFATALMASK))) {
1821 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1822 b43err(dev->wl, "Fatal DMA error: "
1823 "0x%08X, 0x%08X, 0x%08X, "
1824 "0x%08X, 0x%08X, 0x%08X\n",
1825 dma_reason[0], dma_reason[1],
1826 dma_reason[2], dma_reason[3],
1827 dma_reason[4], dma_reason[5]);
1828 b43_controller_restart(dev, "DMA error");
1831 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1832 b43err(dev->wl, "DMA error: "
1833 "0x%08X, 0x%08X, 0x%08X, "
1834 "0x%08X, 0x%08X, 0x%08X\n",
1835 dma_reason[0], dma_reason[1],
1836 dma_reason[2], dma_reason[3],
1837 dma_reason[4], dma_reason[5]);
1841 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1842 handle_irq_ucode_debug(dev);
1843 if (reason & B43_IRQ_TBTT_INDI)
1844 handle_irq_tbtt_indication(dev);
1845 if (reason & B43_IRQ_ATIM_END)
1846 handle_irq_atim_end(dev);
1847 if (reason & B43_IRQ_BEACON)
1848 handle_irq_beacon(dev);
1849 if (reason & B43_IRQ_PMQ)
1850 handle_irq_pmq(dev);
1851 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1853 if (reason & B43_IRQ_NOISESAMPLE_OK)
1854 handle_irq_noise(dev);
1856 /* Check the DMA reason registers for received data. */
1857 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1858 if (b43_using_pio_transfers(dev))
1859 b43_pio_rx(dev->pio.rx_queue);
1861 b43_dma_rx(dev->dma.rx_ring);
1863 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1864 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1865 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
1866 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1867 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1869 if (reason & B43_IRQ_TX_OK)
1870 handle_irq_transmit_status(dev);
1872 /* Re-enable interrupts on the device by restoring the current interrupt mask. */
1873 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
1876 /* Interrupt thread handler. Handles device interrupts in thread context. */
1877 static irqreturn_t b43_interrupt_thread_handler(int irq, void *dev_id)
1879 struct b43_wldev *dev = dev_id;
1881 mutex_lock(&dev->wl->mutex);
1882 b43_do_interrupt_thread(dev);
1884 mutex_unlock(&dev->wl->mutex);
1889 static irqreturn_t b43_do_interrupt(struct b43_wldev *dev)
1893 /* This code runs under wl->hardirq_lock, but _only_ on non-SDIO busses.
1894 * On SDIO, this runs under wl->mutex. */
1896 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1897 if (reason == 0xffffffff) /* shared IRQ */
1899 reason &= dev->irq_mask;
1903 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1905 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1907 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1909 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1911 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1914 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1918 /* ACK the interrupt. */
1919 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1920 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1921 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1922 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1923 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1924 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1926 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1929 /* Disable IRQs on the device. The IRQ thread handler will re-enable them. */
1930 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
1931 /* Save the reason bitmasks for the IRQ thread handler. */
1932 dev->irq_reason = reason;
1934 return IRQ_WAKE_THREAD;
1937 /* Interrupt handler top-half. This runs with interrupts disabled. */
1938 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1940 struct b43_wldev *dev = dev_id;
1943 if (unlikely(b43_status(dev) < B43_STAT_STARTED))
1946 spin_lock(&dev->wl->hardirq_lock);
1947 ret = b43_do_interrupt(dev);
1949 spin_unlock(&dev->wl->hardirq_lock);
1954 void b43_do_release_fw(struct b43_firmware_file *fw)
1956 release_firmware(fw->data);
1958 fw->filename = NULL;
1961 static void b43_release_firmware(struct b43_wldev *dev)
1963 b43_do_release_fw(&dev->fw.ucode);
1964 b43_do_release_fw(&dev->fw.pcm);
1965 b43_do_release_fw(&dev->fw.initvals);
1966 b43_do_release_fw(&dev->fw.initvals_band);
1969 static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
1973 "http://wireless.kernel.org/en/users/Drivers/b43#devicefirmware " \
1974 "and download the correct firmware for this driver version. " \
1975 "Please carefully read all instructions on this website.\n";
1983 int b43_do_request_fw(struct b43_request_fw_context *ctx,
1985 struct b43_firmware_file *fw)
1987 const struct firmware *blob;
1988 struct b43_fw_header *hdr;
1993 /* Don't fetch anything. Free possibly cached firmware. */
1994 /* FIXME: We should probably keep it anyway, to save some headache
1995 * on suspend/resume with multiband devices. */
1996 b43_do_release_fw(fw);
2000 if ((fw->type == ctx->req_type) &&
2001 (strcmp(fw->filename, name) == 0))
2002 return 0; /* Already have this fw. */
2003 /* Free the cached firmware first. */
2004 /* FIXME: We should probably do this later after we successfully
2005 * got the new fw. This could reduce headache with multiband devices.
2006 * We could also redesign this to cache the firmware for all possible
2007 * bands all the time. */
2008 b43_do_release_fw(fw);
2011 switch (ctx->req_type) {
2012 case B43_FWTYPE_PROPRIETARY:
2013 snprintf(ctx->fwname, sizeof(ctx->fwname),
2015 modparam_fwpostfix, name);
2017 case B43_FWTYPE_OPENSOURCE:
2018 snprintf(ctx->fwname, sizeof(ctx->fwname),
2020 modparam_fwpostfix, name);
2026 err = request_firmware(&blob, ctx->fwname, ctx->dev->dev->dev);
2027 if (err == -ENOENT) {
2028 snprintf(ctx->errors[ctx->req_type],
2029 sizeof(ctx->errors[ctx->req_type]),
2030 "Firmware file \"%s\" not found\n", ctx->fwname);
2033 snprintf(ctx->errors[ctx->req_type],
2034 sizeof(ctx->errors[ctx->req_type]),
2035 "Firmware file \"%s\" request failed (err=%d)\n",
2039 if (blob->size < sizeof(struct b43_fw_header))
2041 hdr = (struct b43_fw_header *)(blob->data);
2042 switch (hdr->type) {
2043 case B43_FW_TYPE_UCODE:
2044 case B43_FW_TYPE_PCM:
2045 size = be32_to_cpu(hdr->size);
2046 if (size != blob->size - sizeof(struct b43_fw_header))
2049 case B43_FW_TYPE_IV:
2058 fw->filename = name;
2059 fw->type = ctx->req_type;
2064 snprintf(ctx->errors[ctx->req_type],
2065 sizeof(ctx->errors[ctx->req_type]),
2066 "Firmware file \"%s\" format error.\n", ctx->fwname);
2067 release_firmware(blob);
2072 static int b43_try_request_fw(struct b43_request_fw_context *ctx)
2074 struct b43_wldev *dev = ctx->dev;
2075 struct b43_firmware *fw = &ctx->dev->fw;
2076 const u8 rev = ctx->dev->dev->id.revision;
2077 const char *filename;
2082 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
2083 if ((rev >= 5) && (rev <= 10))
2084 filename = "ucode5";
2085 else if ((rev >= 11) && (rev <= 12))
2086 filename = "ucode11";
2088 filename = "ucode13";
2090 filename = "ucode14";
2092 filename = "ucode15";
2095 err = b43_do_request_fw(ctx, filename, &fw->ucode);
2100 if ((rev >= 5) && (rev <= 10))
2106 fw->pcm_request_failed = 0;
2107 err = b43_do_request_fw(ctx, filename, &fw->pcm);
2108 if (err == -ENOENT) {
2109 /* We did not find a PCM file? Not fatal, but
2110 * core rev <= 10 must do without hwcrypto then. */
2111 fw->pcm_request_failed = 1;
2116 switch (dev->phy.type) {
2118 if ((rev >= 5) && (rev <= 10)) {
2119 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2120 filename = "a0g1initvals5";
2122 filename = "a0g0initvals5";
2124 goto err_no_initvals;
2127 if ((rev >= 5) && (rev <= 10))
2128 filename = "b0g0initvals5";
2130 filename = "b0g0initvals13";
2132 goto err_no_initvals;
2135 if ((rev >= 11) && (rev <= 12))
2136 filename = "n0initvals11";
2138 goto err_no_initvals;
2140 case B43_PHYTYPE_LP:
2142 filename = "lp0initvals13";
2144 filename = "lp0initvals14";
2146 filename = "lp0initvals15";
2148 goto err_no_initvals;
2151 goto err_no_initvals;
2153 err = b43_do_request_fw(ctx, filename, &fw->initvals);
2157 /* Get bandswitch initvals */
2158 switch (dev->phy.type) {
2160 if ((rev >= 5) && (rev <= 10)) {
2161 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2162 filename = "a0g1bsinitvals5";
2164 filename = "a0g0bsinitvals5";
2165 } else if (rev >= 11)
2168 goto err_no_initvals;
2171 if ((rev >= 5) && (rev <= 10))
2172 filename = "b0g0bsinitvals5";
2176 goto err_no_initvals;
2179 if ((rev >= 11) && (rev <= 12))
2180 filename = "n0bsinitvals11";
2182 goto err_no_initvals;
2184 case B43_PHYTYPE_LP:
2186 filename = "lp0bsinitvals13";
2188 filename = "lp0bsinitvals14";
2190 filename = "lp0bsinitvals15";
2192 goto err_no_initvals;
2195 goto err_no_initvals;
2197 err = b43_do_request_fw(ctx, filename, &fw->initvals_band);
2204 err = ctx->fatal_failure = -EOPNOTSUPP;
2205 b43err(dev->wl, "The driver does not know which firmware (ucode) "
2206 "is required for your device (wl-core rev %u)\n", rev);
2210 err = ctx->fatal_failure = -EOPNOTSUPP;
2211 b43err(dev->wl, "The driver does not know which firmware (PCM) "
2212 "is required for your device (wl-core rev %u)\n", rev);
2216 err = ctx->fatal_failure = -EOPNOTSUPP;
2217 b43err(dev->wl, "The driver does not know which firmware (initvals) "
2218 "is required for your device (wl-core rev %u)\n", rev);
2222 /* We failed to load this firmware image. The error message
2223 * already is in ctx->errors. Return and let our caller decide
2228 b43_release_firmware(dev);
2232 static int b43_request_firmware(struct b43_wldev *dev)
2234 struct b43_request_fw_context *ctx;
2239 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
2244 ctx->req_type = B43_FWTYPE_PROPRIETARY;
2245 err = b43_try_request_fw(ctx);
2247 goto out; /* Successfully loaded it. */
2248 err = ctx->fatal_failure;
2252 ctx->req_type = B43_FWTYPE_OPENSOURCE;
2253 err = b43_try_request_fw(ctx);
2255 goto out; /* Successfully loaded it. */
2256 err = ctx->fatal_failure;
2260 /* Could not find a usable firmware. Print the errors. */
2261 for (i = 0; i < B43_NR_FWTYPES; i++) {
2262 errmsg = ctx->errors[i];
2264 b43err(dev->wl, errmsg);
2266 b43_print_fw_helptext(dev->wl, 1);
2274 static int b43_upload_microcode(struct b43_wldev *dev)
2276 const size_t hdr_len = sizeof(struct b43_fw_header);
2278 unsigned int i, len;
2279 u16 fwrev, fwpatch, fwdate, fwtime;
2283 /* Jump the microcode PSM to offset 0 */
2284 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2285 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2286 macctl |= B43_MACCTL_PSM_JMP0;
2287 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2288 /* Zero out all microcode PSM registers and shared memory. */
2289 for (i = 0; i < 64; i++)
2290 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2291 for (i = 0; i < 4096; i += 2)
2292 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2294 /* Upload Microcode. */
2295 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2296 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
2297 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2298 for (i = 0; i < len; i++) {
2299 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2303 if (dev->fw.pcm.data) {
2304 /* Upload PCM data. */
2305 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2306 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
2307 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2308 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2309 /* No need for autoinc bit in SHM_HW */
2310 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2311 for (i = 0; i < len; i++) {
2312 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2317 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
2319 /* Start the microcode PSM */
2320 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2321 macctl &= ~B43_MACCTL_PSM_JMP0;
2322 macctl |= B43_MACCTL_PSM_RUN;
2323 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2325 /* Wait for the microcode to load and respond */
2328 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2329 if (tmp == B43_IRQ_MAC_SUSPENDED)
2333 b43err(dev->wl, "Microcode not responding\n");
2334 b43_print_fw_helptext(dev->wl, 1);
2338 msleep_interruptible(50);
2339 if (signal_pending(current)) {
2344 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2346 /* Get and check the revisions. */
2347 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2348 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2349 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2350 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2352 if (fwrev <= 0x128) {
2353 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2354 "binary drivers older than version 4.x is unsupported. "
2355 "You must upgrade your firmware files.\n");
2356 b43_print_fw_helptext(dev->wl, 1);
2360 dev->fw.rev = fwrev;
2361 dev->fw.patch = fwpatch;
2362 dev->fw.opensource = (fwdate == 0xFFFF);
2364 /* Default to use-all-queues. */
2365 dev->wl->hw->queues = dev->wl->mac80211_initially_registered_queues;
2366 dev->qos_enabled = !!modparam_qos;
2367 /* Default to firmware/hardware crypto acceleration. */
2368 dev->hwcrypto_enabled = 1;
2370 if (dev->fw.opensource) {
2373 /* Patchlevel info is encoded in the "time" field. */
2374 dev->fw.patch = fwtime;
2375 b43info(dev->wl, "Loading OpenSource firmware version %u.%u\n",
2376 dev->fw.rev, dev->fw.patch);
2378 fwcapa = b43_fwcapa_read(dev);
2379 if (!(fwcapa & B43_FWCAPA_HWCRYPTO) || dev->fw.pcm_request_failed) {
2380 b43info(dev->wl, "Hardware crypto acceleration not supported by firmware\n");
2381 /* Disable hardware crypto and fall back to software crypto. */
2382 dev->hwcrypto_enabled = 0;
2384 if (!(fwcapa & B43_FWCAPA_QOS)) {
2385 b43info(dev->wl, "QoS not supported by firmware\n");
2386 /* Disable QoS. Tweak hw->queues to 1. It will be restored before
2387 * ieee80211_unregister to make sure the networking core can
2388 * properly free possible resources. */
2389 dev->wl->hw->queues = 1;
2390 dev->qos_enabled = 0;
2393 b43info(dev->wl, "Loading firmware version %u.%u "
2394 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2396 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2397 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
2398 if (dev->fw.pcm_request_failed) {
2399 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2400 "Hardware accelerated cryptography is disabled.\n");
2401 b43_print_fw_helptext(dev->wl, 0);
2405 if (b43_is_old_txhdr_format(dev)) {
2406 /* We're over the deadline, but we keep support for old fw
2407 * until it turns out to be in major conflict with something new. */
2408 b43warn(dev->wl, "You are using an old firmware image. "
2409 "Support for old firmware will be removed soon "
2410 "(official deadline was July 2008).\n");
2411 b43_print_fw_helptext(dev->wl, 0);
2417 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2418 macctl &= ~B43_MACCTL_PSM_RUN;
2419 macctl |= B43_MACCTL_PSM_JMP0;
2420 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2425 static int b43_write_initvals(struct b43_wldev *dev,
2426 const struct b43_iv *ivals,
2430 const struct b43_iv *iv;
2435 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2437 for (i = 0; i < count; i++) {
2438 if (array_size < sizeof(iv->offset_size))
2440 array_size -= sizeof(iv->offset_size);
2441 offset = be16_to_cpu(iv->offset_size);
2442 bit32 = !!(offset & B43_IV_32BIT);
2443 offset &= B43_IV_OFFSET_MASK;
2444 if (offset >= 0x1000)
2449 if (array_size < sizeof(iv->data.d32))
2451 array_size -= sizeof(iv->data.d32);
2453 value = get_unaligned_be32(&iv->data.d32);
2454 b43_write32(dev, offset, value);
2456 iv = (const struct b43_iv *)((const uint8_t *)iv +
2462 if (array_size < sizeof(iv->data.d16))
2464 array_size -= sizeof(iv->data.d16);
2466 value = be16_to_cpu(iv->data.d16);
2467 b43_write16(dev, offset, value);
2469 iv = (const struct b43_iv *)((const uint8_t *)iv +
2480 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
2481 b43_print_fw_helptext(dev->wl, 1);
2486 static int b43_upload_initvals(struct b43_wldev *dev)
2488 const size_t hdr_len = sizeof(struct b43_fw_header);
2489 const struct b43_fw_header *hdr;
2490 struct b43_firmware *fw = &dev->fw;
2491 const struct b43_iv *ivals;
2495 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2496 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
2497 count = be32_to_cpu(hdr->size);
2498 err = b43_write_initvals(dev, ivals, count,
2499 fw->initvals.data->size - hdr_len);
2502 if (fw->initvals_band.data) {
2503 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2504 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
2505 count = be32_to_cpu(hdr->size);
2506 err = b43_write_initvals(dev, ivals, count,
2507 fw->initvals_band.data->size - hdr_len);
2516 /* Initialize the GPIOs
2517 * http://bcm-specs.sipsolutions.net/GPIO
2519 static int b43_gpio_init(struct b43_wldev *dev)
2521 struct ssb_bus *bus = dev->dev->bus;
2522 struct ssb_device *gpiodev, *pcidev = NULL;
2525 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2526 & ~B43_MACCTL_GPOUTSMSK);
2528 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
2533 if (dev->dev->bus->chip_id == 0x4301) {
2537 if (0 /* FIXME: conditional unknown */ ) {
2538 b43_write16(dev, B43_MMIO_GPIO_MASK,
2539 b43_read16(dev, B43_MMIO_GPIO_MASK)
2544 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
2545 b43_write16(dev, B43_MMIO_GPIO_MASK,
2546 b43_read16(dev, B43_MMIO_GPIO_MASK)
2551 if (dev->dev->id.revision >= 2)
2552 mask |= 0x0010; /* FIXME: This is redundant. */
2554 #ifdef CONFIG_SSB_DRIVER_PCICORE
2555 pcidev = bus->pcicore.dev;
2557 gpiodev = bus->chipco.dev ? : pcidev;
2560 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2561 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2567 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2568 static void b43_gpio_cleanup(struct b43_wldev *dev)
2570 struct ssb_bus *bus = dev->dev->bus;
2571 struct ssb_device *gpiodev, *pcidev = NULL;
2573 #ifdef CONFIG_SSB_DRIVER_PCICORE
2574 pcidev = bus->pcicore.dev;
2576 gpiodev = bus->chipco.dev ? : pcidev;
2579 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2582 /* http://bcm-specs.sipsolutions.net/EnableMac */
2583 void b43_mac_enable(struct b43_wldev *dev)
2585 if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2588 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2589 B43_SHM_SH_UCODESTAT);
2590 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2591 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2592 b43err(dev->wl, "b43_mac_enable(): The firmware "
2593 "should be suspended, but current state is %u\n",
2598 dev->mac_suspended--;
2599 B43_WARN_ON(dev->mac_suspended < 0);
2600 if (dev->mac_suspended == 0) {
2601 b43_write32(dev, B43_MMIO_MACCTL,
2602 b43_read32(dev, B43_MMIO_MACCTL)
2603 | B43_MACCTL_ENABLED);
2604 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2605 B43_IRQ_MAC_SUSPENDED);
2607 b43_read32(dev, B43_MMIO_MACCTL);
2608 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2609 b43_power_saving_ctl_bits(dev, 0);
2613 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2614 void b43_mac_suspend(struct b43_wldev *dev)
2620 B43_WARN_ON(dev->mac_suspended < 0);
2622 if (dev->mac_suspended == 0) {
2623 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2624 b43_write32(dev, B43_MMIO_MACCTL,
2625 b43_read32(dev, B43_MMIO_MACCTL)
2626 & ~B43_MACCTL_ENABLED);
2627 /* force pci to flush the write */
2628 b43_read32(dev, B43_MMIO_MACCTL);
2629 for (i = 35; i; i--) {
2630 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2631 if (tmp & B43_IRQ_MAC_SUSPENDED)
2635 /* Hm, it seems this will take some time. Use msleep(). */
2636 for (i = 40; i; i--) {
2637 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2638 if (tmp & B43_IRQ_MAC_SUSPENDED)
2642 b43err(dev->wl, "MAC suspend failed\n");
2645 dev->mac_suspended++;
2648 static void b43_adjust_opmode(struct b43_wldev *dev)
2650 struct b43_wl *wl = dev->wl;
2654 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2655 /* Reset status to STA infrastructure mode. */
2656 ctl &= ~B43_MACCTL_AP;
2657 ctl &= ~B43_MACCTL_KEEP_CTL;
2658 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2659 ctl &= ~B43_MACCTL_KEEP_BAD;
2660 ctl &= ~B43_MACCTL_PROMISC;
2661 ctl &= ~B43_MACCTL_BEACPROMISC;
2662 ctl |= B43_MACCTL_INFRA;
2664 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
2665 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
2666 ctl |= B43_MACCTL_AP;
2667 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
2668 ctl &= ~B43_MACCTL_INFRA;
2670 if (wl->filter_flags & FIF_CONTROL)
2671 ctl |= B43_MACCTL_KEEP_CTL;
2672 if (wl->filter_flags & FIF_FCSFAIL)
2673 ctl |= B43_MACCTL_KEEP_BAD;
2674 if (wl->filter_flags & FIF_PLCPFAIL)
2675 ctl |= B43_MACCTL_KEEP_BADPLCP;
2676 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2677 ctl |= B43_MACCTL_PROMISC;
2678 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2679 ctl |= B43_MACCTL_BEACPROMISC;
2681 /* Workaround: On old hardware the HW-MAC-address-filter
2682 * doesn't work properly, so always run promisc in filter
2683 * it in software. */
2684 if (dev->dev->id.revision <= 4)
2685 ctl |= B43_MACCTL_PROMISC;
2687 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2690 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2691 if (dev->dev->bus->chip_id == 0x4306 &&
2692 dev->dev->bus->chip_rev == 3)
2697 b43_write16(dev, 0x612, cfp_pretbtt);
2700 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2706 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2709 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2711 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2712 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2715 static void b43_rate_memory_init(struct b43_wldev *dev)
2717 switch (dev->phy.type) {
2721 case B43_PHYTYPE_LP:
2722 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2723 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2724 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2725 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2726 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2727 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2728 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2729 if (dev->phy.type == B43_PHYTYPE_A)
2733 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2734 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2735 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2736 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2743 /* Set the default values for the PHY TX Control Words. */
2744 static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
2748 ctl |= B43_TXH_PHY_ENC_CCK;
2749 ctl |= B43_TXH_PHY_ANT01AUTO;
2750 ctl |= B43_TXH_PHY_TXPWR;
2752 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
2753 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
2754 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
2757 /* Set the TX-Antenna for management frames sent by firmware. */
2758 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2763 ant = b43_antenna_to_phyctl(antenna);
2766 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
2767 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2768 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2769 /* For Probe Resposes */
2770 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
2771 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2772 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2775 /* This is the opposite of b43_chip_init() */
2776 static void b43_chip_exit(struct b43_wldev *dev)
2779 b43_gpio_cleanup(dev);
2780 /* firmware is released later */
2783 /* Initialize the chip
2784 * http://bcm-specs.sipsolutions.net/ChipInit
2786 static int b43_chip_init(struct b43_wldev *dev)
2788 struct b43_phy *phy = &dev->phy;
2790 u32 value32, macctl;
2793 /* Initialize the MAC control */
2794 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
2796 macctl |= B43_MACCTL_GMODE;
2797 macctl |= B43_MACCTL_INFRA;
2798 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2800 err = b43_request_firmware(dev);
2803 err = b43_upload_microcode(dev);
2805 goto out; /* firmware is released later */
2807 err = b43_gpio_init(dev);
2809 goto out; /* firmware is released later */
2811 err = b43_upload_initvals(dev);
2813 goto err_gpio_clean;
2815 /* Turn the Analog on and initialize the PHY. */
2816 phy->ops->switch_analog(dev, 1);
2817 err = b43_phy_init(dev);
2819 goto err_gpio_clean;
2821 /* Disable Interference Mitigation. */
2822 if (phy->ops->interf_mitigation)
2823 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
2825 /* Select the antennae */
2826 if (phy->ops->set_rx_antenna)
2827 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2828 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2830 if (phy->type == B43_PHYTYPE_B) {
2831 value16 = b43_read16(dev, 0x005E);
2833 b43_write16(dev, 0x005E, value16);
2835 b43_write32(dev, 0x0100, 0x01000000);
2836 if (dev->dev->id.revision < 5)
2837 b43_write32(dev, 0x010C, 0x01000000);
2839 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2840 & ~B43_MACCTL_INFRA);
2841 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2842 | B43_MACCTL_INFRA);
2844 /* Probe Response Timeout value */
2845 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2846 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2848 /* Initially set the wireless operation mode. */
2849 b43_adjust_opmode(dev);
2851 if (dev->dev->id.revision < 3) {
2852 b43_write16(dev, 0x060E, 0x0000);
2853 b43_write16(dev, 0x0610, 0x8000);
2854 b43_write16(dev, 0x0604, 0x0000);
2855 b43_write16(dev, 0x0606, 0x0200);
2857 b43_write32(dev, 0x0188, 0x80000000);
2858 b43_write32(dev, 0x018C, 0x02000000);
2860 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2861 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2862 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2863 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2864 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2865 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2866 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2868 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2869 value32 |= 0x00100000;
2870 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2872 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2873 dev->dev->bus->chipco.fast_pwrup_delay);
2876 b43dbg(dev->wl, "Chip initialized\n");
2881 b43_gpio_cleanup(dev);
2885 static void b43_periodic_every60sec(struct b43_wldev *dev)
2887 const struct b43_phy_operations *ops = dev->phy.ops;
2889 if (ops->pwork_60sec)
2890 ops->pwork_60sec(dev);
2892 /* Force check the TX power emission now. */
2893 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
2896 static void b43_periodic_every30sec(struct b43_wldev *dev)
2898 /* Update device statistics. */
2899 b43_calculate_link_quality(dev);
2902 static void b43_periodic_every15sec(struct b43_wldev *dev)
2904 struct b43_phy *phy = &dev->phy;
2907 if (dev->fw.opensource) {
2908 /* Check if the firmware is still alive.
2909 * It will reset the watchdog counter to 0 in its idle loop. */
2910 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
2911 if (unlikely(wdr)) {
2912 b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
2913 b43_controller_restart(dev, "Firmware watchdog");
2916 b43_shm_write16(dev, B43_SHM_SCRATCH,
2917 B43_WATCHDOG_REG, 1);
2921 if (phy->ops->pwork_15sec)
2922 phy->ops->pwork_15sec(dev);
2924 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2928 static void do_periodic_work(struct b43_wldev *dev)
2932 state = dev->periodic_state;
2934 b43_periodic_every60sec(dev);
2936 b43_periodic_every30sec(dev);
2937 b43_periodic_every15sec(dev);
2940 /* Periodic work locking policy:
2941 * The whole periodic work handler is protected by
2942 * wl->mutex. If another lock is needed somewhere in the
2943 * pwork callchain, it's aquired in-place, where it's needed.
2945 static void b43_periodic_work_handler(struct work_struct *work)
2947 struct b43_wldev *dev = container_of(work, struct b43_wldev,
2948 periodic_work.work);
2949 struct b43_wl *wl = dev->wl;
2950 unsigned long delay;
2952 mutex_lock(&wl->mutex);
2954 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2956 if (b43_debug(dev, B43_DBG_PWORK_STOP))
2959 do_periodic_work(dev);
2961 dev->periodic_state++;
2963 if (b43_debug(dev, B43_DBG_PWORK_FAST))
2964 delay = msecs_to_jiffies(50);
2966 delay = round_jiffies_relative(HZ * 15);
2967 ieee80211_queue_delayed_work(wl->hw, &dev->periodic_work, delay);
2969 mutex_unlock(&wl->mutex);
2972 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2974 struct delayed_work *work = &dev->periodic_work;
2976 dev->periodic_state = 0;
2977 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
2978 ieee80211_queue_delayed_work(dev->wl->hw, work, 0);
2981 /* Check if communication with the device works correctly. */
2982 static int b43_validate_chipaccess(struct b43_wldev *dev)
2984 u32 v, backup0, backup4;
2986 backup0 = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2987 backup4 = b43_shm_read32(dev, B43_SHM_SHARED, 4);
2989 /* Check for read/write and endianness problems. */
2990 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2991 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2993 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2994 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
2997 /* Check if unaligned 32bit SHM_SHARED access works properly.
2998 * However, don't bail out on failure, because it's noncritical. */
2999 b43_shm_write16(dev, B43_SHM_SHARED, 0, 0x1122);
3000 b43_shm_write16(dev, B43_SHM_SHARED, 2, 0x3344);
3001 b43_shm_write16(dev, B43_SHM_SHARED, 4, 0x5566);
3002 b43_shm_write16(dev, B43_SHM_SHARED, 6, 0x7788);
3003 if (b43_shm_read32(dev, B43_SHM_SHARED, 2) != 0x55663344)
3004 b43warn(dev->wl, "Unaligned 32bit SHM read access is broken\n");
3005 b43_shm_write32(dev, B43_SHM_SHARED, 2, 0xAABBCCDD);
3006 if (b43_shm_read16(dev, B43_SHM_SHARED, 0) != 0x1122 ||
3007 b43_shm_read16(dev, B43_SHM_SHARED, 2) != 0xCCDD ||
3008 b43_shm_read16(dev, B43_SHM_SHARED, 4) != 0xAABB ||
3009 b43_shm_read16(dev, B43_SHM_SHARED, 6) != 0x7788)
3010 b43warn(dev->wl, "Unaligned 32bit SHM write access is broken\n");
3012 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0);
3013 b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4);
3015 if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
3016 /* The 32bit register shadows the two 16bit registers
3017 * with update sideeffects. Validate this. */
3018 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
3019 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
3020 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
3022 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
3025 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
3027 v = b43_read32(dev, B43_MMIO_MACCTL);
3028 v |= B43_MACCTL_GMODE;
3029 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
3034 b43err(dev->wl, "Failed to validate the chipaccess\n");
3038 static void b43_security_init(struct b43_wldev *dev)
3040 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
3041 /* KTP is a word address, but we address SHM bytewise.
3042 * So multiply by two.
3045 /* Number of RCMTA address slots */
3046 b43_write16(dev, B43_MMIO_RCMTA_COUNT, B43_NR_PAIRWISE_KEYS);
3047 /* Clear the key memory. */
3048 b43_clear_keys(dev);
3051 #ifdef CONFIG_B43_HWRNG
3052 static int b43_rng_read(struct hwrng *rng, u32 *data)
3054 struct b43_wl *wl = (struct b43_wl *)rng->priv;
3056 /* FIXME: We need to take wl->mutex here to make sure the device
3057 * is not going away from under our ass. However it could deadlock
3058 * with hwrng internal locking. */
3060 *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
3062 return (sizeof(u16));
3064 #endif /* CONFIG_B43_HWRNG */
3066 static void b43_rng_exit(struct b43_wl *wl)
3068 #ifdef CONFIG_B43_HWRNG
3069 if (wl->rng_initialized)
3070 hwrng_unregister(&wl->rng);
3071 #endif /* CONFIG_B43_HWRNG */
3074 static int b43_rng_init(struct b43_wl *wl)
3078 #ifdef CONFIG_B43_HWRNG
3079 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
3080 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
3081 wl->rng.name = wl->rng_name;
3082 wl->rng.data_read = b43_rng_read;
3083 wl->rng.priv = (unsigned long)wl;
3084 wl->rng_initialized = 1;
3085 err = hwrng_register(&wl->rng);
3087 wl->rng_initialized = 0;
3088 b43err(wl, "Failed to register the random "
3089 "number generator (%d)\n", err);
3091 #endif /* CONFIG_B43_HWRNG */
3096 static void b43_tx_work(struct work_struct *work)
3098 struct b43_wl *wl = container_of(work, struct b43_wl, tx_work);
3099 struct b43_wldev *dev;
3100 struct sk_buff *skb;
3103 mutex_lock(&wl->mutex);
3104 dev = wl->current_dev;
3105 if (unlikely(!dev || b43_status(dev) < B43_STAT_STARTED)) {
3106 mutex_unlock(&wl->mutex);
3110 while (skb_queue_len(&wl->tx_queue)) {
3111 skb = skb_dequeue(&wl->tx_queue);
3113 if (b43_using_pio_transfers(dev))
3114 err = b43_pio_tx(dev, skb);
3116 err = b43_dma_tx(dev, skb);
3118 dev_kfree_skb(skb); /* Drop it */
3121 mutex_unlock(&wl->mutex);
3124 static int b43_op_tx(struct ieee80211_hw *hw,
3125 struct sk_buff *skb)
3127 struct b43_wl *wl = hw_to_b43_wl(hw);
3129 if (unlikely(skb->len < 2 + 2 + 6)) {
3130 /* Too short, this can't be a valid frame. */
3131 dev_kfree_skb_any(skb);
3132 return NETDEV_TX_OK;
3134 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
3136 skb_queue_tail(&wl->tx_queue, skb);
3137 ieee80211_queue_work(wl->hw, &wl->tx_work);
3139 return NETDEV_TX_OK;
3142 /* Locking: wl->irq_lock */
3143 static void b43_qos_params_upload(struct b43_wldev *dev,
3144 const struct ieee80211_tx_queue_params *p,
3147 u16 params[B43_NR_QOSPARAMS];
3151 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
3153 memset(¶ms, 0, sizeof(params));
3155 params[B43_QOSPARAM_TXOP] = p->txop * 32;
3156 params[B43_QOSPARAM_CWMIN] = p->cw_min;
3157 params[B43_QOSPARAM_CWMAX] = p->cw_max;
3158 params[B43_QOSPARAM_CWCUR] = p->cw_min;
3159 params[B43_QOSPARAM_AIFS] = p->aifs;
3160 params[B43_QOSPARAM_BSLOTS] = bslots;
3161 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
3163 for (i = 0; i < ARRAY_SIZE(params); i++) {
3164 if (i == B43_QOSPARAM_STATUS) {
3165 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3166 shm_offset + (i * 2));
3167 /* Mark the parameters as updated. */
3169 b43_shm_write16(dev, B43_SHM_SHARED,
3170 shm_offset + (i * 2),
3173 b43_shm_write16(dev, B43_SHM_SHARED,
3174 shm_offset + (i * 2),
3180 /* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3181 static const u16 b43_qos_shm_offsets[] = {
3182 /* [mac80211-queue-nr] = SHM_OFFSET, */
3183 [0] = B43_QOS_VOICE,
3184 [1] = B43_QOS_VIDEO,
3185 [2] = B43_QOS_BESTEFFORT,
3186 [3] = B43_QOS_BACKGROUND,
3189 /* Update all QOS parameters in hardware. */
3190 static void b43_qos_upload_all(struct b43_wldev *dev)
3192 struct b43_wl *wl = dev->wl;
3193 struct b43_qos_params *params;
3196 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3197 ARRAY_SIZE(wl->qos_params));
3199 b43_mac_suspend(dev);
3200 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3201 params = &(wl->qos_params[i]);
3202 b43_qos_params_upload(dev, &(params->p),
3203 b43_qos_shm_offsets[i]);
3205 b43_mac_enable(dev);
3208 static void b43_qos_clear(struct b43_wl *wl)
3210 struct b43_qos_params *params;
3213 /* Initialize QoS parameters to sane defaults. */
3215 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3216 ARRAY_SIZE(wl->qos_params));
3218 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3219 params = &(wl->qos_params[i]);
3221 switch (b43_qos_shm_offsets[i]) {
3225 params->p.cw_min = 0x0001;
3226 params->p.cw_max = 0x0001;
3231 params->p.cw_min = 0x0001;
3232 params->p.cw_max = 0x0001;
3234 case B43_QOS_BESTEFFORT:
3237 params->p.cw_min = 0x0001;
3238 params->p.cw_max = 0x03FF;
3240 case B43_QOS_BACKGROUND:
3243 params->p.cw_min = 0x0001;
3244 params->p.cw_max = 0x03FF;
3252 /* Initialize the core's QOS capabilities */
3253 static void b43_qos_init(struct b43_wldev *dev)
3255 /* Upload the current QOS parameters. */
3256 b43_qos_upload_all(dev);
3258 /* Enable QOS support. */
3259 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3260 b43_write16(dev, B43_MMIO_IFSCTL,
3261 b43_read16(dev, B43_MMIO_IFSCTL)
3262 | B43_MMIO_IFSCTL_USE_EDCF);
3265 static int b43_op_conf_tx(struct ieee80211_hw *hw, u16 _queue,
3266 const struct ieee80211_tx_queue_params *params)
3268 struct b43_wl *wl = hw_to_b43_wl(hw);
3269 struct b43_wldev *dev;
3270 unsigned int queue = (unsigned int)_queue;
3273 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3274 /* Queue not available or don't support setting
3275 * params on this queue. Return success to not
3276 * confuse mac80211. */
3279 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3280 ARRAY_SIZE(wl->qos_params));
3282 mutex_lock(&wl->mutex);
3283 dev = wl->current_dev;
3284 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
3287 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
3288 b43_mac_suspend(dev);
3289 b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
3290 b43_qos_shm_offsets[queue]);
3291 b43_mac_enable(dev);
3295 mutex_unlock(&wl->mutex);
3300 static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
3301 struct ieee80211_tx_queue_stats *stats)
3303 struct b43_wl *wl = hw_to_b43_wl(hw);
3304 struct b43_wldev *dev;
3307 mutex_lock(&wl->mutex);
3308 dev = wl->current_dev;
3309 if (dev && b43_status(dev) >= B43_STAT_STARTED) {
3310 if (b43_using_pio_transfers(dev))
3311 b43_pio_get_tx_stats(dev, stats);
3313 b43_dma_get_tx_stats(dev, stats);
3316 mutex_unlock(&wl->mutex);
3321 static int b43_op_get_stats(struct ieee80211_hw *hw,
3322 struct ieee80211_low_level_stats *stats)
3324 struct b43_wl *wl = hw_to_b43_wl(hw);
3326 mutex_lock(&wl->mutex);
3327 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
3328 mutex_unlock(&wl->mutex);
3333 static u64 b43_op_get_tsf(struct ieee80211_hw *hw)
3335 struct b43_wl *wl = hw_to_b43_wl(hw);
3336 struct b43_wldev *dev;
3339 mutex_lock(&wl->mutex);
3340 dev = wl->current_dev;
3342 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3343 b43_tsf_read(dev, &tsf);
3347 mutex_unlock(&wl->mutex);
3352 static void b43_op_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3354 struct b43_wl *wl = hw_to_b43_wl(hw);
3355 struct b43_wldev *dev;
3357 mutex_lock(&wl->mutex);
3358 dev = wl->current_dev;
3360 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED))
3361 b43_tsf_write(dev, tsf);
3363 mutex_unlock(&wl->mutex);
3366 static void b43_put_phy_into_reset(struct b43_wldev *dev)
3368 struct ssb_device *sdev = dev->dev;
3371 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3372 tmslow &= ~B43_TMSLOW_GMODE;
3373 tmslow |= B43_TMSLOW_PHYRESET;
3374 tmslow |= SSB_TMSLOW_FGC;
3375 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3378 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3379 tmslow &= ~SSB_TMSLOW_FGC;
3380 tmslow |= B43_TMSLOW_PHYRESET;
3381 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3385 static const char *band_to_string(enum ieee80211_band band)
3388 case IEEE80211_BAND_5GHZ:
3390 case IEEE80211_BAND_2GHZ:
3399 /* Expects wl->mutex locked */
3400 static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan)
3402 struct b43_wldev *up_dev = NULL;
3403 struct b43_wldev *down_dev;
3404 struct b43_wldev *d;
3406 bool uninitialized_var(gmode);
3409 /* Find a device and PHY which supports the band. */
3410 list_for_each_entry(d, &wl->devlist, list) {
3411 switch (chan->band) {
3412 case IEEE80211_BAND_5GHZ:
3413 if (d->phy.supports_5ghz) {
3418 case IEEE80211_BAND_2GHZ:
3419 if (d->phy.supports_2ghz) {
3432 b43err(wl, "Could not find a device for %s-GHz band operation\n",
3433 band_to_string(chan->band));
3436 if ((up_dev == wl->current_dev) &&
3437 (!!wl->current_dev->phy.gmode == !!gmode)) {
3438 /* This device is already running. */
3441 b43dbg(wl, "Switching to %s-GHz band\n",
3442 band_to_string(chan->band));
3443 down_dev = wl->current_dev;
3445 prev_status = b43_status(down_dev);
3446 /* Shutdown the currently running core. */
3447 if (prev_status >= B43_STAT_STARTED)
3448 down_dev = b43_wireless_core_stop(down_dev);
3449 if (prev_status >= B43_STAT_INITIALIZED)
3450 b43_wireless_core_exit(down_dev);
3452 if (down_dev != up_dev) {
3453 /* We switch to a different core, so we put PHY into
3454 * RESET on the old core. */
3455 b43_put_phy_into_reset(down_dev);
3458 /* Now start the new core. */
3459 up_dev->phy.gmode = gmode;
3460 if (prev_status >= B43_STAT_INITIALIZED) {
3461 err = b43_wireless_core_init(up_dev);
3463 b43err(wl, "Fatal: Could not initialize device for "
3464 "selected %s-GHz band\n",
3465 band_to_string(chan->band));
3469 if (prev_status >= B43_STAT_STARTED) {
3470 err = b43_wireless_core_start(up_dev);
3472 b43err(wl, "Fatal: Coult not start device for "
3473 "selected %s-GHz band\n",
3474 band_to_string(chan->band));
3475 b43_wireless_core_exit(up_dev);
3479 B43_WARN_ON(b43_status(up_dev) != prev_status);
3481 wl->current_dev = up_dev;
3485 /* Whoops, failed to init the new core. No core is operating now. */
3486 wl->current_dev = NULL;
3490 /* Write the short and long frame retry limit values. */
3491 static void b43_set_retry_limits(struct b43_wldev *dev,
3492 unsigned int short_retry,
3493 unsigned int long_retry)
3495 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3496 * the chip-internal counter. */
3497 short_retry = min(short_retry, (unsigned int)0xF);
3498 long_retry = min(long_retry, (unsigned int)0xF);
3500 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3502 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3506 static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
3508 struct b43_wl *wl = hw_to_b43_wl(hw);
3509 struct b43_wldev *dev;
3510 struct b43_phy *phy;
3511 struct ieee80211_conf *conf = &hw->conf;
3515 mutex_lock(&wl->mutex);
3517 /* Switch the band (if necessary). This might change the active core. */
3518 err = b43_switch_band(wl, conf->channel);
3520 goto out_unlock_mutex;
3521 dev = wl->current_dev;
3524 b43_mac_suspend(dev);
3526 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3527 b43_set_retry_limits(dev, conf->short_frame_max_tx_count,
3528 conf->long_frame_max_tx_count);
3529 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
3531 goto out_mac_enable;
3533 /* Switch to the requested channel.
3534 * The firmware takes care of races with the TX handler. */
3535 if (conf->channel->hw_value != phy->channel)
3536 b43_switch_channel(dev, conf->channel->hw_value);
3538 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
3540 /* Adjust the desired TX power level. */
3541 if (conf->power_level != 0) {
3542 if (conf->power_level != phy->desired_txpower) {
3543 phy->desired_txpower = conf->power_level;
3544 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
3545 B43_TXPWR_IGNORE_TSSI);
3549 /* Antennas for RX and management frame TX. */
3550 antenna = B43_ANTENNA_DEFAULT;
3551 b43_mgmtframe_txantenna(dev, antenna);
3552 antenna = B43_ANTENNA_DEFAULT;
3553 if (phy->ops->set_rx_antenna)
3554 phy->ops->set_rx_antenna(dev, antenna);
3556 if (wl->radio_enabled != phy->radio_on) {
3557 if (wl->radio_enabled) {
3558 b43_software_rfkill(dev, false);
3559 b43info(dev->wl, "Radio turned on by software\n");
3560 if (!dev->radio_hw_enable) {
3561 b43info(dev->wl, "The hardware RF-kill button "
3562 "still turns the radio physically off. "
3563 "Press the button to turn it on.\n");
3566 b43_software_rfkill(dev, true);
3567 b43info(dev->wl, "Radio turned off by software\n");
3572 b43_mac_enable(dev);
3574 mutex_unlock(&wl->mutex);
3579 static void b43_update_basic_rates(struct b43_wldev *dev, u32 brates)
3581 struct ieee80211_supported_band *sband =
3582 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)];
3583 struct ieee80211_rate *rate;
3585 u16 basic, direct, offset, basic_offset, rateptr;
3587 for (i = 0; i < sband->n_bitrates; i++) {
3588 rate = &sband->bitrates[i];
3590 if (b43_is_cck_rate(rate->hw_value)) {
3591 direct = B43_SHM_SH_CCKDIRECT;
3592 basic = B43_SHM_SH_CCKBASIC;
3593 offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3596 direct = B43_SHM_SH_OFDMDIRECT;
3597 basic = B43_SHM_SH_OFDMBASIC;
3598 offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3602 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
3604 if (b43_is_cck_rate(rate->hw_value)) {
3605 basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3606 basic_offset &= 0xF;
3608 basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3609 basic_offset &= 0xF;
3613 * Get the pointer that we need to point to
3614 * from the direct map
3616 rateptr = b43_shm_read16(dev, B43_SHM_SHARED,
3617 direct + 2 * basic_offset);
3618 /* and write it to the basic map */
3619 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset,
3624 static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
3625 struct ieee80211_vif *vif,
3626 struct ieee80211_bss_conf *conf,
3629 struct b43_wl *wl = hw_to_b43_wl(hw);
3630 struct b43_wldev *dev;
3632 mutex_lock(&wl->mutex);
3634 dev = wl->current_dev;
3635 if (!dev || b43_status(dev) < B43_STAT_STARTED)
3636 goto out_unlock_mutex;
3638 B43_WARN_ON(wl->vif != vif);
3640 if (changed & BSS_CHANGED_BSSID) {
3642 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3644 memset(wl->bssid, 0, ETH_ALEN);
3647 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3648 if (changed & BSS_CHANGED_BEACON &&
3649 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3650 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3651 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
3652 b43_update_templates(wl);
3654 if (changed & BSS_CHANGED_BSSID)
3655 b43_write_mac_bssid_templates(dev);
3658 b43_mac_suspend(dev);
3660 /* Update templates for AP/mesh mode. */
3661 if (changed & BSS_CHANGED_BEACON_INT &&
3662 (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3663 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT) ||
3664 b43_is_mode(wl, NL80211_IFTYPE_ADHOC)))
3665 b43_set_beacon_int(dev, conf->beacon_int);
3667 if (changed & BSS_CHANGED_BASIC_RATES)
3668 b43_update_basic_rates(dev, conf->basic_rates);
3670 if (changed & BSS_CHANGED_ERP_SLOT) {
3671 if (conf->use_short_slot)
3672 b43_short_slot_timing_enable(dev);
3674 b43_short_slot_timing_disable(dev);
3677 b43_mac_enable(dev);
3679 mutex_unlock(&wl->mutex);
3682 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3683 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3684 struct ieee80211_key_conf *key)
3686 struct b43_wl *wl = hw_to_b43_wl(hw);
3687 struct b43_wldev *dev;
3691 static const u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
3693 if (modparam_nohwcrypt)
3694 return -ENOSPC; /* User disabled HW-crypto */
3696 mutex_lock(&wl->mutex);
3698 dev = wl->current_dev;
3700 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
3703 if (dev->fw.pcm_request_failed || !dev->hwcrypto_enabled) {
3704 /* We don't have firmware for the crypto engine.
3705 * Must use software-crypto. */
3713 if (key->keylen == WLAN_KEY_LEN_WEP40)
3714 algorithm = B43_SEC_ALGO_WEP40;
3716 algorithm = B43_SEC_ALGO_WEP104;
3719 algorithm = B43_SEC_ALGO_TKIP;
3722 algorithm = B43_SEC_ALGO_AES;
3728 index = (u8) (key->keyidx);
3734 if (algorithm == B43_SEC_ALGO_TKIP &&
3735 (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE) ||
3736 !modparam_hwtkip)) {
3737 /* We support only pairwise key */
3742 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
3743 if (WARN_ON(!sta)) {
3747 /* Pairwise key with an assigned MAC address. */
3748 err = b43_key_write(dev, -1, algorithm,
3749 key->key, key->keylen,
3753 err = b43_key_write(dev, index, algorithm,
3754 key->key, key->keylen, NULL, key);
3759 if (algorithm == B43_SEC_ALGO_WEP40 ||
3760 algorithm == B43_SEC_ALGO_WEP104) {
3761 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
3764 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
3766 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3767 if (algorithm == B43_SEC_ALGO_TKIP)
3768 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
3771 err = b43_key_clear(dev, key->hw_key_idx);
3782 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
3784 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
3785 sta ? sta->addr : bcast_addr);
3786 b43_dump_keymemory(dev);
3788 mutex_unlock(&wl->mutex);
3793 static void b43_op_configure_filter(struct ieee80211_hw *hw,
3794 unsigned int changed, unsigned int *fflags,
3797 struct b43_wl *wl = hw_to_b43_wl(hw);
3798 struct b43_wldev *dev;
3800 mutex_lock(&wl->mutex);
3801 dev = wl->current_dev;
3807 *fflags &= FIF_PROMISC_IN_BSS |
3813 FIF_BCN_PRBRESP_PROMISC;
3815 changed &= FIF_PROMISC_IN_BSS |
3821 FIF_BCN_PRBRESP_PROMISC;
3823 wl->filter_flags = *fflags;
3825 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
3826 b43_adjust_opmode(dev);
3829 mutex_unlock(&wl->mutex);
3832 /* Locking: wl->mutex
3833 * Returns the current dev. This might be different from the passed in dev,
3834 * because the core might be gone away while we unlocked the mutex. */
3835 static struct b43_wldev * b43_wireless_core_stop(struct b43_wldev *dev)
3837 struct b43_wl *wl = dev->wl;
3838 struct b43_wldev *orig_dev;
3841 if (!dev || b43_status(dev) < B43_STAT_STARTED)
3844 /* Cancel work. Unlock to avoid deadlocks. */
3845 mutex_unlock(&wl->mutex);
3846 cancel_delayed_work_sync(&dev->periodic_work);
3847 cancel_work_sync(&wl->tx_work);
3848 mutex_lock(&wl->mutex);
3849 dev = wl->current_dev;
3850 if (!dev || b43_status(dev) < B43_STAT_STARTED) {
3851 /* Whoops, aliens ate up the device while we were unlocked. */
3855 /* Disable interrupts on the device. */
3856 b43_set_status(dev, B43_STAT_INITIALIZED);
3857 if (0 /*FIXME dev->dev->bus->bustype == SSB_BUSTYPE_SDIO*/) {
3858 /* wl->mutex is locked. That is enough. */
3859 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
3860 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
3862 spin_lock_irq(&wl->hardirq_lock);
3863 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, 0);
3864 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* Flush */
3865 spin_unlock_irq(&wl->hardirq_lock);
3867 /* Synchronize the interrupt handlers. Unlock to avoid deadlocks. */
3869 mutex_unlock(&wl->mutex);
3870 synchronize_irq(dev->dev->irq);
3871 mutex_lock(&wl->mutex);
3872 dev = wl->current_dev;
3875 if (dev != orig_dev) {
3876 if (b43_status(dev) >= B43_STAT_STARTED)
3880 B43_WARN_ON(b43_read32(dev, B43_MMIO_GEN_IRQ_MASK));
3882 /* Drain the TX queue */
3883 while (skb_queue_len(&wl->tx_queue))
3884 dev_kfree_skb(skb_dequeue(&wl->tx_queue));
3887 b43_mac_suspend(dev);
3888 free_irq(dev->dev->irq, dev);
3889 b43dbg(wl, "Wireless interface stopped\n");
3894 /* Locking: wl->mutex */
3895 static int b43_wireless_core_start(struct b43_wldev *dev)
3899 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3901 drain_txstatus_queue(dev);
3902 err = request_threaded_irq(dev->dev->irq, b43_interrupt_handler,
3903 b43_interrupt_thread_handler,
3904 IRQF_SHARED, KBUILD_MODNAME, dev);
3906 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3910 /* We are ready to run. */
3911 b43_set_status(dev, B43_STAT_STARTED);
3913 /* Start data flow (TX/RX). */
3914 b43_mac_enable(dev);
3915 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, dev->irq_mask);
3917 /* Start maintainance work */
3918 b43_periodic_tasks_setup(dev);
3920 b43dbg(dev->wl, "Wireless interface started\n");
3925 /* Get PHY and RADIO versioning numbers */
3926 static int b43_phy_versioning(struct b43_wldev *dev)
3928 struct b43_phy *phy = &dev->phy;
3936 int unsupported = 0;
3938 /* Get PHY versioning */
3939 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3940 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3941 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3942 phy_rev = (tmp & B43_PHYVER_VERSION);
3949 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3957 #ifdef CONFIG_B43_NPHY
3963 #ifdef CONFIG_B43_PHY_LP
3964 case B43_PHYTYPE_LP:
3973 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3974 "(Analog %u, Type %u, Revision %u)\n",
3975 analog_type, phy_type, phy_rev);
3978 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3979 analog_type, phy_type, phy_rev);
3981 /* Get RADIO versioning */
3982 if (dev->dev->bus->chip_id == 0x4317) {
3983 if (dev->dev->bus->chip_rev == 0)
3985 else if (dev->dev->bus->chip_rev == 1)
3990 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3991 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3992 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3993 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
3995 radio_manuf = (tmp & 0x00000FFF);
3996 radio_ver = (tmp & 0x0FFFF000) >> 12;
3997 radio_rev = (tmp & 0xF0000000) >> 28;
3998 if (radio_manuf != 0x17F /* Broadcom */)
4002 if (radio_ver != 0x2060)
4006 if (radio_manuf != 0x17F)
4010 if ((radio_ver & 0xFFF0) != 0x2050)
4014 if (radio_ver != 0x2050)
4018 if (radio_ver != 0x2055 && radio_ver != 0x2056)
4021 case B43_PHYTYPE_LP:
4022 if (radio_ver != 0x2062 && radio_ver != 0x2063)
4029 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
4030 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
4031 radio_manuf, radio_ver, radio_rev);
4034 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
4035 radio_manuf, radio_ver, radio_rev);
4037 phy->radio_manuf = radio_manuf;
4038 phy->radio_ver = radio_ver;
4039 phy->radio_rev = radio_rev;
4041 phy->analog = analog_type;
4042 phy->type = phy_type;
4048 static void setup_struct_phy_for_init(struct b43_wldev *dev,
4049 struct b43_phy *phy)
4051 phy->hardware_power_control = !!modparam_hwpctl;
4052 phy->next_txpwr_check_time = jiffies;
4053 /* PHY TX errors counter. */
4054 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
4057 phy->phy_locked = 0;
4058 phy->radio_locked = 0;
4062 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
4066 /* Assume the radio is enabled. If it's not enabled, the state will
4067 * immediately get fixed on the first periodic work run. */
4068 dev->radio_hw_enable = 1;
4071 memset(&dev->stats, 0, sizeof(dev->stats));
4073 setup_struct_phy_for_init(dev, &dev->phy);
4075 /* IRQ related flags */
4076 dev->irq_reason = 0;
4077 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
4078 dev->irq_mask = B43_IRQ_MASKTEMPLATE;
4079 if (b43_modparam_verbose < B43_VERBOSITY_DEBUG)
4080 dev->irq_mask &= ~B43_IRQ_PHY_TXERR;
4082 dev->mac_suspended = 1;
4084 /* Noise calculation context */
4085 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
4088 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
4090 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
4093 if (!modparam_btcoex)
4095 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
4097 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
4100 hf = b43_hf_read(dev);
4101 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
4102 hf |= B43_HF_BTCOEXALT;
4104 hf |= B43_HF_BTCOEX;
4105 b43_hf_write(dev, hf);
4108 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
4110 if (!modparam_btcoex)
4115 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
4117 #ifdef CONFIG_SSB_DRIVER_PCICORE
4118 struct ssb_bus *bus = dev->dev->bus;
4121 if (bus->pcicore.dev &&
4122 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
4123 bus->pcicore.dev->id.revision <= 5) {
4124 /* IMCFGLO timeouts workaround. */
4125 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
4126 tmp &= ~SSB_IMCFGLO_REQTO;
4127 tmp &= ~SSB_IMCFGLO_SERTO;
4128 switch (bus->bustype) {
4129 case SSB_BUSTYPE_PCI:
4130 case SSB_BUSTYPE_PCMCIA:
4133 case SSB_BUSTYPE_SSB:
4137 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
4139 #endif /* CONFIG_SSB_DRIVER_PCICORE */
4142 static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
4146 /* The time value is in microseconds. */
4147 if (dev->phy.type == B43_PHYTYPE_A)
4151 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
4153 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
4154 pu_delay = max(pu_delay, (u16)2400);
4156 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
4159 /* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
4160 static void b43_set_pretbtt(struct b43_wldev *dev)
4164 /* The time value is in microseconds. */
4165 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) {
4168 if (dev->phy.type == B43_PHYTYPE_A)
4173 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
4174 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
4177 /* Shutdown a wireless core */
4178 /* Locking: wl->mutex */
4179 static void b43_wireless_core_exit(struct b43_wldev *dev)
4183 B43_WARN_ON(dev && b43_status(dev) > B43_STAT_INITIALIZED);
4184 if (!dev || b43_status(dev) != B43_STAT_INITIALIZED)
4186 b43_set_status(dev, B43_STAT_UNINIT);
4188 /* Stop the microcode PSM. */
4189 macctl = b43_read32(dev, B43_MMIO_MACCTL);
4190 macctl &= ~B43_MACCTL_PSM_RUN;
4191 macctl |= B43_MACCTL_PSM_JMP0;
4192 b43_write32(dev, B43_MMIO_MACCTL, macctl);
4194 if (!dev->suspend_in_progress) {
4196 b43_rng_exit(dev->wl);
4201 dev->phy.ops->switch_analog(dev, 0);
4202 if (dev->wl->current_beacon) {
4203 dev_kfree_skb_any(dev->wl->current_beacon);
4204 dev->wl->current_beacon = NULL;
4207 ssb_device_disable(dev->dev, 0);
4208 ssb_bus_may_powerdown(dev->dev->bus);
4211 /* Initialize a wireless core */
4212 static int b43_wireless_core_init(struct b43_wldev *dev)
4214 struct b43_wl *wl = dev->wl;
4215 struct ssb_bus *bus = dev->dev->bus;
4216 struct ssb_sprom *sprom = &bus->sprom;
4217 struct b43_phy *phy = &dev->phy;
4222 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4224 err = ssb_bus_powerup(bus, 0);
4227 if (!ssb_device_is_enabled(dev->dev)) {
4228 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
4229 b43_wireless_core_reset(dev, tmp);
4232 /* Reset all data structures. */
4233 setup_struct_wldev_for_init(dev);
4234 phy->ops->prepare_structs(dev);
4236 /* Enable IRQ routing to this device. */
4237 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
4239 b43_imcfglo_timeouts_workaround(dev);
4240 b43_bluetooth_coext_disable(dev);
4241 if (phy->ops->prepare_hardware) {
4242 err = phy->ops->prepare_hardware(dev);
4246 err = b43_chip_init(dev);
4249 b43_shm_write16(dev, B43_SHM_SHARED,
4250 B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
4251 hf = b43_hf_read(dev);
4252 if (phy->type == B43_PHYTYPE_G) {
4256 if (sprom->boardflags_lo & B43_BFL_PACTRL)
4257 hf |= B43_HF_OFDMPABOOST;
4259 if (phy->radio_ver == 0x2050) {
4260 if (phy->radio_rev == 6)
4261 hf |= B43_HF_4318TSSI;
4262 if (phy->radio_rev < 6)
4263 hf |= B43_HF_VCORECALC;
4265 if (sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW)
4266 hf |= B43_HF_DSCRQ; /* Disable slowclock requests from ucode. */
4267 #ifdef CONFIG_SSB_DRIVER_PCICORE
4268 if ((bus->bustype == SSB_BUSTYPE_PCI) &&
4269 (bus->pcicore.dev->id.revision <= 10))
4270 hf |= B43_HF_PCISCW; /* PCI slow clock workaround. */
4272 hf &= ~B43_HF_SKCFPUP;
4273 b43_hf_write(dev, hf);
4275 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4276 B43_DEFAULT_LONG_RETRY_LIMIT);
4277 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4278 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4280 /* Disable sending probe responses from firmware.
4281 * Setting the MaxTime to one usec will always trigger
4282 * a timeout, so we never send any probe resp.
4283 * A timeout of zero is infinite. */
4284 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4286 b43_rate_memory_init(dev);
4287 b43_set_phytxctl_defaults(dev);
4289 /* Minimum Contention Window */
4290 if (phy->type == B43_PHYTYPE_B) {
4291 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
4293 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
4295 /* Maximum Contention Window */
4296 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4298 if ((dev->dev->bus->bustype == SSB_BUSTYPE_PCMCIA) || B43_FORCE_PIO) {
4299 dev->__using_pio_transfers = 1;
4300 err = b43_pio_init(dev);
4302 dev->__using_pio_transfers = 0;
4303 err = b43_dma_init(dev);
4308 b43_set_synth_pu_delay(dev, 1);
4309 b43_bluetooth_coext_enable(dev);
4311 ssb_bus_powerup(bus, !(sprom->boardflags_lo & B43_BFL_XTAL_NOSLOW));
4312 b43_upload_card_macaddress(dev);
4313 b43_security_init(dev);
4314 if (!dev->suspend_in_progress)
4317 b43_set_status(dev, B43_STAT_INITIALIZED);
4319 if (!dev->suspend_in_progress)
4327 ssb_bus_may_powerdown(bus);
4328 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4332 static int b43_op_add_interface(struct ieee80211_hw *hw,
4333 struct ieee80211_if_init_conf *conf)
4335 struct b43_wl *wl = hw_to_b43_wl(hw);
4336 struct b43_wldev *dev;
4337 int err = -EOPNOTSUPP;
4339 /* TODO: allow WDS/AP devices to coexist */
4341 if (conf->type != NL80211_IFTYPE_AP &&
4342 conf->type != NL80211_IFTYPE_MESH_POINT &&
4343 conf->type != NL80211_IFTYPE_STATION &&
4344 conf->type != NL80211_IFTYPE_WDS &&
4345 conf->type != NL80211_IFTYPE_ADHOC)
4348 mutex_lock(&wl->mutex);
4350 goto out_mutex_unlock;
4352 b43dbg(wl, "Adding Interface type %d\n", conf->type);
4354 dev = wl->current_dev;
4356 wl->vif = conf->vif;
4357 wl->if_type = conf->type;
4358 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
4360 b43_adjust_opmode(dev);
4361 b43_set_pretbtt(dev);
4362 b43_set_synth_pu_delay(dev, 0);
4363 b43_upload_card_macaddress(dev);
4367 mutex_unlock(&wl->mutex);
4372 static void b43_op_remove_interface(struct ieee80211_hw *hw,
4373 struct ieee80211_if_init_conf *conf)
4375 struct b43_wl *wl = hw_to_b43_wl(hw);
4376 struct b43_wldev *dev = wl->current_dev;
4378 b43dbg(wl, "Removing Interface type %d\n", conf->type);
4380 mutex_lock(&wl->mutex);
4382 B43_WARN_ON(!wl->operating);
4383 B43_WARN_ON(wl->vif != conf->vif);
4388 b43_adjust_opmode(dev);
4389 memset(wl->mac_addr, 0, ETH_ALEN);
4390 b43_upload_card_macaddress(dev);
4392 mutex_unlock(&wl->mutex);
4395 static int b43_op_start(struct ieee80211_hw *hw)
4397 struct b43_wl *wl = hw_to_b43_wl(hw);
4398 struct b43_wldev *dev = wl->current_dev;
4402 /* Kill all old instance specific information to make sure
4403 * the card won't use it in the short timeframe between start
4404 * and mac80211 reconfiguring it. */
4405 memset(wl->bssid, 0, ETH_ALEN);
4406 memset(wl->mac_addr, 0, ETH_ALEN);
4407 wl->filter_flags = 0;
4408 wl->radiotap_enabled = 0;
4410 wl->beacon0_uploaded = 0;
4411 wl->beacon1_uploaded = 0;
4412 wl->beacon_templates_virgin = 1;
4413 wl->radio_enabled = 1;
4415 mutex_lock(&wl->mutex);
4417 if (b43_status(dev) < B43_STAT_INITIALIZED) {
4418 err = b43_wireless_core_init(dev);
4420 goto out_mutex_unlock;
4424 if (b43_status(dev) < B43_STAT_STARTED) {
4425 err = b43_wireless_core_start(dev);
4428 b43_wireless_core_exit(dev);
4429 goto out_mutex_unlock;
4433 /* XXX: only do if device doesn't support rfkill irq */
4434 wiphy_rfkill_start_polling(hw->wiphy);
4437 mutex_unlock(&wl->mutex);
4442 static void b43_op_stop(struct ieee80211_hw *hw)
4444 struct b43_wl *wl = hw_to_b43_wl(hw);
4445 struct b43_wldev *dev = wl->current_dev;
4447 cancel_work_sync(&(wl->beacon_update_trigger));
4449 mutex_lock(&wl->mutex);
4450 if (b43_status(dev) >= B43_STAT_STARTED) {
4451 dev = b43_wireless_core_stop(dev);
4455 b43_wireless_core_exit(dev);
4456 wl->radio_enabled = 0;
4459 mutex_unlock(&wl->mutex);
4461 cancel_work_sync(&(wl->txpower_adjust_work));
4464 static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
4465 struct ieee80211_sta *sta, bool set)
4467 struct b43_wl *wl = hw_to_b43_wl(hw);
4469 mutex_lock(&wl->mutex);
4470 b43_update_templates(wl);
4471 mutex_unlock(&wl->mutex);
4476 static void b43_op_sta_notify(struct ieee80211_hw *hw,
4477 struct ieee80211_vif *vif,
4478 enum sta_notify_cmd notify_cmd,
4479 struct ieee80211_sta *sta)
4481 struct b43_wl *wl = hw_to_b43_wl(hw);
4483 B43_WARN_ON(!vif || wl->vif != vif);
4486 static void b43_op_sw_scan_start_notifier(struct ieee80211_hw *hw)
4488 struct b43_wl *wl = hw_to_b43_wl(hw);
4489 struct b43_wldev *dev;
4491 mutex_lock(&wl->mutex);
4492 dev = wl->current_dev;
4493 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4494 /* Disable CFP update during scan on other channels. */
4495 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_SKCFPUP);
4497 mutex_unlock(&wl->mutex);
4500 static void b43_op_sw_scan_complete_notifier(struct ieee80211_hw *hw)
4502 struct b43_wl *wl = hw_to_b43_wl(hw);
4503 struct b43_wldev *dev;
4505 mutex_lock(&wl->mutex);
4506 dev = wl->current_dev;
4507 if (dev && (b43_status(dev) >= B43_STAT_INITIALIZED)) {
4508 /* Re-enable CFP update. */
4509 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_SKCFPUP);
4511 mutex_unlock(&wl->mutex);
4514 static const struct ieee80211_ops b43_hw_ops = {
4516 .conf_tx = b43_op_conf_tx,
4517 .add_interface = b43_op_add_interface,
4518 .remove_interface = b43_op_remove_interface,
4519 .config = b43_op_config,
4520 .bss_info_changed = b43_op_bss_info_changed,
4521 .configure_filter = b43_op_configure_filter,
4522 .set_key = b43_op_set_key,
4523 .update_tkip_key = b43_op_update_tkip_key,
4524 .get_stats = b43_op_get_stats,
4525 .get_tx_stats = b43_op_get_tx_stats,
4526 .get_tsf = b43_op_get_tsf,
4527 .set_tsf = b43_op_set_tsf,
4528 .start = b43_op_start,
4529 .stop = b43_op_stop,
4530 .set_tim = b43_op_beacon_set_tim,
4531 .sta_notify = b43_op_sta_notify,
4532 .sw_scan_start = b43_op_sw_scan_start_notifier,
4533 .sw_scan_complete = b43_op_sw_scan_complete_notifier,
4534 .rfkill_poll = b43_rfkill_poll,
4537 /* Hard-reset the chip. Do not call this directly.
4538 * Use b43_controller_restart()
4540 static void b43_chip_reset(struct work_struct *work)
4542 struct b43_wldev *dev =
4543 container_of(work, struct b43_wldev, restart_work);
4544 struct b43_wl *wl = dev->wl;
4548 mutex_lock(&wl->mutex);
4550 prev_status = b43_status(dev);
4551 /* Bring the device down... */
4552 if (prev_status >= B43_STAT_STARTED) {
4553 dev = b43_wireless_core_stop(dev);
4559 if (prev_status >= B43_STAT_INITIALIZED)
4560 b43_wireless_core_exit(dev);
4562 /* ...and up again. */
4563 if (prev_status >= B43_STAT_INITIALIZED) {
4564 err = b43_wireless_core_init(dev);
4568 if (prev_status >= B43_STAT_STARTED) {
4569 err = b43_wireless_core_start(dev);
4571 b43_wireless_core_exit(dev);
4577 wl->current_dev = NULL; /* Failed to init the dev. */
4578 mutex_unlock(&wl->mutex);
4580 b43err(wl, "Controller restart FAILED\n");
4582 b43info(wl, "Controller restarted\n");
4585 static int b43_setup_bands(struct b43_wldev *dev,
4586 bool have_2ghz_phy, bool have_5ghz_phy)
4588 struct ieee80211_hw *hw = dev->wl->hw;
4591 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
4592 if (dev->phy.type == B43_PHYTYPE_N) {
4594 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
4597 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
4600 dev->phy.supports_2ghz = have_2ghz_phy;
4601 dev->phy.supports_5ghz = have_5ghz_phy;
4606 static void b43_wireless_core_detach(struct b43_wldev *dev)
4608 /* We release firmware that late to not be required to re-request
4609 * is all the time when we reinit the core. */
4610 b43_release_firmware(dev);
4614 static int b43_wireless_core_attach(struct b43_wldev *dev)
4616 struct b43_wl *wl = dev->wl;
4617 struct ssb_bus *bus = dev->dev->bus;
4618 struct pci_dev *pdev = bus->host_pci;
4620 bool have_2ghz_phy = 0, have_5ghz_phy = 0;
4623 /* Do NOT do any device initialization here.
4624 * Do it in wireless_core_init() instead.
4625 * This function is for gathering basic information about the HW, only.
4626 * Also some structs may be set up here. But most likely you want to have
4627 * that in core_init(), too.
4630 err = ssb_bus_powerup(bus, 0);
4632 b43err(wl, "Bus powerup failed\n");
4635 /* Get the PHY type. */
4636 if (dev->dev->id.revision >= 5) {
4639 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
4640 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
4641 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
4645 dev->phy.gmode = have_2ghz_phy;
4646 dev->phy.radio_on = 1;
4647 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4648 b43_wireless_core_reset(dev, tmp);
4650 err = b43_phy_versioning(dev);
4653 /* Check if this device supports multiband. */
4655 (pdev->device != 0x4312 &&
4656 pdev->device != 0x4319 && pdev->device != 0x4324)) {
4657 /* No multiband support. */
4660 switch (dev->phy.type) {
4664 case B43_PHYTYPE_LP: //FIXME not always!
4665 #if 0 //FIXME enabling 5GHz causes a NULL pointer dereference
4676 if (dev->phy.type == B43_PHYTYPE_A) {
4678 b43err(wl, "IEEE 802.11a devices are unsupported\n");
4682 if (1 /* disable A-PHY */) {
4683 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */
4684 if (dev->phy.type != B43_PHYTYPE_N &&
4685 dev->phy.type != B43_PHYTYPE_LP) {
4691 err = b43_phy_allocate(dev);
4695 dev->phy.gmode = have_2ghz_phy;
4696 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4697 b43_wireless_core_reset(dev, tmp);
4699 err = b43_validate_chipaccess(dev);
4702 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
4706 /* Now set some default "current_dev" */
4707 if (!wl->current_dev)
4708 wl->current_dev = dev;
4709 INIT_WORK(&dev->restart_work, b43_chip_reset);
4711 dev->phy.ops->switch_analog(dev, 0);
4712 ssb_device_disable(dev->dev, 0);
4713 ssb_bus_may_powerdown(bus);
4721 ssb_bus_may_powerdown(bus);
4725 static void b43_one_core_detach(struct ssb_device *dev)
4727 struct b43_wldev *wldev;
4730 /* Do not cancel ieee80211-workqueue based work here.
4731 * See comment in b43_remove(). */
4733 wldev = ssb_get_drvdata(dev);
4735 b43_debugfs_remove_device(wldev);
4736 b43_wireless_core_detach(wldev);
4737 list_del(&wldev->list);
4739 ssb_set_drvdata(dev, NULL);
4743 static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
4745 struct b43_wldev *wldev;
4746 struct pci_dev *pdev;
4749 if (!list_empty(&wl->devlist)) {
4750 /* We are not the first core on this chip. */
4751 pdev = dev->bus->host_pci;
4752 /* Only special chips support more than one wireless
4753 * core, although some of the other chips have more than
4754 * one wireless core as well. Check for this and
4758 ((pdev->device != 0x4321) &&
4759 (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
4760 b43dbg(wl, "Ignoring unconnected 802.11 core\n");
4765 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
4771 b43_set_status(wldev, B43_STAT_UNINIT);
4772 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
4773 INIT_LIST_HEAD(&wldev->list);
4775 err = b43_wireless_core_attach(wldev);
4777 goto err_kfree_wldev;
4779 list_add(&wldev->list, &wl->devlist);
4781 ssb_set_drvdata(dev, wldev);
4782 b43_debugfs_add_device(wldev);
4792 #define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
4793 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
4794 (pdev->device == _device) && \
4795 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
4796 (pdev->subsystem_device == _subdevice) )
4798 static void b43_sprom_fixup(struct ssb_bus *bus)
4800 struct pci_dev *pdev;
4802 /* boardflags workarounds */
4803 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
4804 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
4805 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
4806 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
4807 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
4808 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
4809 if (bus->bustype == SSB_BUSTYPE_PCI) {
4810 pdev = bus->host_pci;
4811 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
4812 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) ||
4813 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) ||
4814 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
4815 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
4816 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
4817 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
4818 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
4822 static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
4824 struct ieee80211_hw *hw = wl->hw;
4826 ssb_set_devtypedata(dev, NULL);
4827 ieee80211_free_hw(hw);
4830 static int b43_wireless_init(struct ssb_device *dev)
4832 struct ssb_sprom *sprom = &dev->bus->sprom;
4833 struct ieee80211_hw *hw;
4837 b43_sprom_fixup(dev->bus);
4839 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
4841 b43err(NULL, "Could not allocate ieee80211 device\n");
4844 wl = hw_to_b43_wl(hw);
4847 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
4848 IEEE80211_HW_SIGNAL_DBM |
4849 IEEE80211_HW_NOISE_DBM;
4851 hw->wiphy->interface_modes =
4852 BIT(NL80211_IFTYPE_AP) |
4853 BIT(NL80211_IFTYPE_MESH_POINT) |
4854 BIT(NL80211_IFTYPE_STATION) |
4855 BIT(NL80211_IFTYPE_WDS) |
4856 BIT(NL80211_IFTYPE_ADHOC);
4858 hw->queues = modparam_qos ? 4 : 1;
4859 wl->mac80211_initially_registered_queues = hw->queues;
4861 SET_IEEE80211_DEV(hw, dev->dev);
4862 if (is_valid_ether_addr(sprom->et1mac))
4863 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
4865 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
4867 /* Initialize struct b43_wl */
4869 spin_lock_init(&wl->leds_lock);
4870 spin_lock_init(&wl->shm_lock);
4871 mutex_init(&wl->mutex);
4872 spin_lock_init(&wl->hardirq_lock);
4873 INIT_LIST_HEAD(&wl->devlist);
4874 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
4875 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
4876 INIT_WORK(&wl->tx_work, b43_tx_work);
4877 skb_queue_head_init(&wl->tx_queue);
4879 ssb_set_devtypedata(dev, wl);
4880 b43info(wl, "Broadcom %04X WLAN found (core revision %u)\n",
4881 dev->bus->chip_id, dev->id.revision);
4887 static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
4893 wl = ssb_get_devtypedata(dev);
4895 /* Probing the first core. Must setup common struct b43_wl */
4897 err = b43_wireless_init(dev);
4900 wl = ssb_get_devtypedata(dev);
4903 err = b43_one_core_attach(dev, wl);
4905 goto err_wireless_exit;
4908 err = ieee80211_register_hw(wl->hw);
4910 goto err_one_core_detach;
4916 err_one_core_detach:
4917 b43_one_core_detach(dev);
4920 b43_wireless_exit(dev, wl);
4924 static void b43_remove(struct ssb_device *dev)
4926 struct b43_wl *wl = ssb_get_devtypedata(dev);
4927 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4929 /* We must cancel any work here before unregistering from ieee80211,
4930 * as the ieee80211 unreg will destroy the workqueue. */
4931 cancel_work_sync(&wldev->restart_work);
4934 if (wl->current_dev == wldev) {
4935 /* Restore the queues count before unregistering, because firmware detect
4936 * might have modified it. Restoring is important, so the networking
4937 * stack can properly free resources. */
4938 wl->hw->queues = wl->mac80211_initially_registered_queues;
4939 ieee80211_unregister_hw(wl->hw);
4942 b43_one_core_detach(dev);
4944 if (list_empty(&wl->devlist)) {
4945 /* Last core on the chip unregistered.
4946 * We can destroy common struct b43_wl.
4948 b43_wireless_exit(dev, wl);
4952 /* Perform a hardware reset. This can be called from any context. */
4953 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
4955 /* Must avoid requeueing, if we are in shutdown. */
4956 if (b43_status(dev) < B43_STAT_INITIALIZED)
4958 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
4959 ieee80211_queue_work(dev->wl->hw, &dev->restart_work);
4964 static int b43_suspend(struct ssb_device *dev, pm_message_t state)
4966 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4967 struct b43_wl *wl = wldev->wl;
4969 b43dbg(wl, "Suspending...\n");
4971 mutex_lock(&wl->mutex);
4972 wldev->suspend_in_progress = true;
4973 wldev->suspend_init_status = b43_status(wldev);
4974 if (wldev->suspend_init_status >= B43_STAT_STARTED)
4975 wldev = b43_wireless_core_stop(wldev);
4976 if (wldev && wldev->suspend_init_status >= B43_STAT_INITIALIZED)
4977 b43_wireless_core_exit(wldev);
4978 mutex_unlock(&wl->mutex);
4980 b43dbg(wl, "Device suspended.\n");
4985 static int b43_resume(struct ssb_device *dev)
4987 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4988 struct b43_wl *wl = wldev->wl;
4991 b43dbg(wl, "Resuming...\n");
4993 mutex_lock(&wl->mutex);
4994 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
4995 err = b43_wireless_core_init(wldev);
4997 b43err(wl, "Resume failed at core init\n");
5001 if (wldev->suspend_init_status >= B43_STAT_STARTED) {
5002 err = b43_wireless_core_start(wldev);
5004 b43_leds_exit(wldev);
5005 b43_rng_exit(wldev->wl);
5006 b43_wireless_core_exit(wldev);
5007 b43err(wl, "Resume failed at core start\n");
5011 b43dbg(wl, "Device resumed.\n");
5013 wldev->suspend_in_progress = false;
5014 mutex_unlock(&wl->mutex);
5018 #else /* CONFIG_PM */
5019 # define b43_suspend NULL
5020 # define b43_resume NULL
5021 #endif /* CONFIG_PM */
5023 static struct ssb_driver b43_ssb_driver = {
5024 .name = KBUILD_MODNAME,
5025 .id_table = b43_ssb_tbl,
5027 .remove = b43_remove,
5028 .suspend = b43_suspend,
5029 .resume = b43_resume,
5032 static void b43_print_driverinfo(void)
5034 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
5037 #ifdef CONFIG_B43_PCI_AUTOSELECT
5040 #ifdef CONFIG_B43_PCMCIA
5043 #ifdef CONFIG_B43_NPHY
5046 #ifdef CONFIG_B43_LEDS
5049 printk(KERN_INFO "Broadcom 43xx driver loaded "
5050 "[ Features: %s%s%s%s, Firmware-ID: "
5051 B43_SUPPORTED_FIRMWARE_ID " ]\n",
5052 feat_pci, feat_pcmcia, feat_nphy,
5056 static int __init b43_init(void)
5061 err = b43_pcmcia_init();
5064 err = ssb_driver_register(&b43_ssb_driver);
5066 goto err_pcmcia_exit;
5067 b43_print_driverinfo();
5078 static void __exit b43_exit(void)
5080 ssb_driver_unregister(&b43_ssb_driver);
5085 module_init(b43_init)
5086 module_exit(b43_exit)