3 Broadcom B43 wireless driver
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
31 #include <linux/delay.h>
32 #include <linux/init.h>
33 #include <linux/moduleparam.h>
34 #include <linux/if_arp.h>
35 #include <linux/etherdevice.h>
36 #include <linux/version.h>
37 #include <linux/firmware.h>
38 #include <linux/wireless.h>
39 #include <linux/workqueue.h>
40 #include <linux/skbuff.h>
41 #include <linux/dma-mapping.h>
42 #include <asm/unaligned.h>
54 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
55 MODULE_AUTHOR("Martin Langer");
56 MODULE_AUTHOR("Stefano Brivio");
57 MODULE_AUTHOR("Michael Buesch");
58 MODULE_LICENSE("GPL");
61 static int modparam_bad_frames_preempt;
62 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
63 MODULE_PARM_DESC(bad_frames_preempt,
64 "enable(1) / disable(0) Bad Frames Preemption");
66 static char modparam_fwpostfix[16];
67 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
68 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
70 static int modparam_hwpctl;
71 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
72 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
74 static int modparam_nohwcrypt;
75 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
76 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
78 static const struct ssb_device_id b43_ssb_tbl[] = {
79 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
80 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
81 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
82 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
83 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
84 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
85 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
89 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
91 /* Channel and ratetables are shared for all devices.
92 * They can't be const, because ieee80211 puts some precalculated
93 * data in there. This data is the same for all devices, so we don't
94 * get concurrency issues */
95 #define RATETAB_ENT(_rateid, _flags) \
97 .rate = B43_RATE_TO_BASE100KBPS(_rateid), \
102 static struct ieee80211_rate __b43_ratetable[] = {
103 RATETAB_ENT(B43_CCK_RATE_1MB, IEEE80211_RATE_CCK),
104 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_CCK_2),
105 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_CCK_2),
106 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_CCK_2),
107 RATETAB_ENT(B43_OFDM_RATE_6MB, IEEE80211_RATE_OFDM),
108 RATETAB_ENT(B43_OFDM_RATE_9MB, IEEE80211_RATE_OFDM),
109 RATETAB_ENT(B43_OFDM_RATE_12MB, IEEE80211_RATE_OFDM),
110 RATETAB_ENT(B43_OFDM_RATE_18MB, IEEE80211_RATE_OFDM),
111 RATETAB_ENT(B43_OFDM_RATE_24MB, IEEE80211_RATE_OFDM),
112 RATETAB_ENT(B43_OFDM_RATE_36MB, IEEE80211_RATE_OFDM),
113 RATETAB_ENT(B43_OFDM_RATE_48MB, IEEE80211_RATE_OFDM),
114 RATETAB_ENT(B43_OFDM_RATE_54MB, IEEE80211_RATE_OFDM),
117 #define b43_a_ratetable (__b43_ratetable + 4)
118 #define b43_a_ratetable_size 8
119 #define b43_b_ratetable (__b43_ratetable + 0)
120 #define b43_b_ratetable_size 4
121 #define b43_g_ratetable (__b43_ratetable + 0)
122 #define b43_g_ratetable_size 12
124 #define CHANTAB_ENT(_chanid, _freq) \
129 .flag = IEEE80211_CHAN_W_SCAN | \
130 IEEE80211_CHAN_W_ACTIVE_SCAN | \
131 IEEE80211_CHAN_W_IBSS, \
132 .power_level = 0xFF, \
133 .antenna_max = 0xFF, \
135 static struct ieee80211_channel b43_2ghz_chantable[] = {
136 CHANTAB_ENT(1, 2412),
137 CHANTAB_ENT(2, 2417),
138 CHANTAB_ENT(3, 2422),
139 CHANTAB_ENT(4, 2427),
140 CHANTAB_ENT(5, 2432),
141 CHANTAB_ENT(6, 2437),
142 CHANTAB_ENT(7, 2442),
143 CHANTAB_ENT(8, 2447),
144 CHANTAB_ENT(9, 2452),
145 CHANTAB_ENT(10, 2457),
146 CHANTAB_ENT(11, 2462),
147 CHANTAB_ENT(12, 2467),
148 CHANTAB_ENT(13, 2472),
149 CHANTAB_ENT(14, 2484),
151 #define b43_2ghz_chantable_size ARRAY_SIZE(b43_2ghz_chantable)
154 static struct ieee80211_channel b43_5ghz_chantable[] = {
155 CHANTAB_ENT(36, 5180),
156 CHANTAB_ENT(40, 5200),
157 CHANTAB_ENT(44, 5220),
158 CHANTAB_ENT(48, 5240),
159 CHANTAB_ENT(52, 5260),
160 CHANTAB_ENT(56, 5280),
161 CHANTAB_ENT(60, 5300),
162 CHANTAB_ENT(64, 5320),
163 CHANTAB_ENT(149, 5745),
164 CHANTAB_ENT(153, 5765),
165 CHANTAB_ENT(157, 5785),
166 CHANTAB_ENT(161, 5805),
167 CHANTAB_ENT(165, 5825),
169 #define b43_5ghz_chantable_size ARRAY_SIZE(b43_5ghz_chantable)
172 static void b43_wireless_core_exit(struct b43_wldev *dev);
173 static int b43_wireless_core_init(struct b43_wldev *dev);
174 static void b43_wireless_core_stop(struct b43_wldev *dev);
175 static int b43_wireless_core_start(struct b43_wldev *dev);
177 static int b43_ratelimit(struct b43_wl *wl)
179 if (!wl || !wl->current_dev)
181 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
183 /* We are up and running.
184 * Ratelimit the messages to avoid DoS over the net. */
185 return net_ratelimit();
188 void b43info(struct b43_wl *wl, const char *fmt, ...)
192 if (!b43_ratelimit(wl))
195 printk(KERN_INFO "b43-%s: ",
196 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
201 void b43err(struct b43_wl *wl, const char *fmt, ...)
205 if (!b43_ratelimit(wl))
208 printk(KERN_ERR "b43-%s ERROR: ",
209 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
214 void b43warn(struct b43_wl *wl, const char *fmt, ...)
218 if (!b43_ratelimit(wl))
221 printk(KERN_WARNING "b43-%s warning: ",
222 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
228 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
233 printk(KERN_DEBUG "b43-%s debug: ",
234 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
240 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
244 B43_WARN_ON(offset % 4 != 0);
246 macctl = b43_read32(dev, B43_MMIO_MACCTL);
247 if (macctl & B43_MACCTL_BE)
250 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
252 b43_write32(dev, B43_MMIO_RAM_DATA, val);
256 void b43_shm_control_word(struct b43_wldev *dev, u16 routing, u16 offset)
260 /* "offset" is the WORD offset. */
265 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
268 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
272 if (routing == B43_SHM_SHARED) {
273 B43_WARN_ON(offset & 0x0001);
274 if (offset & 0x0003) {
275 /* Unaligned access */
276 b43_shm_control_word(dev, routing, offset >> 2);
277 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
279 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
280 ret |= b43_read16(dev, B43_MMIO_SHM_DATA);
286 b43_shm_control_word(dev, routing, offset);
287 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
292 u16 b43_shm_read16(struct b43_wldev * dev, u16 routing, u16 offset)
296 if (routing == B43_SHM_SHARED) {
297 B43_WARN_ON(offset & 0x0001);
298 if (offset & 0x0003) {
299 /* Unaligned access */
300 b43_shm_control_word(dev, routing, offset >> 2);
301 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
307 b43_shm_control_word(dev, routing, offset);
308 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
313 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
315 if (routing == B43_SHM_SHARED) {
316 B43_WARN_ON(offset & 0x0001);
317 if (offset & 0x0003) {
318 /* Unaligned access */
319 b43_shm_control_word(dev, routing, offset >> 2);
321 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
322 (value >> 16) & 0xffff);
324 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
326 b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
331 b43_shm_control_word(dev, routing, offset);
333 b43_write32(dev, B43_MMIO_SHM_DATA, value);
336 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
338 if (routing == B43_SHM_SHARED) {
339 B43_WARN_ON(offset & 0x0001);
340 if (offset & 0x0003) {
341 /* Unaligned access */
342 b43_shm_control_word(dev, routing, offset >> 2);
344 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
349 b43_shm_control_word(dev, routing, offset);
351 b43_write16(dev, B43_MMIO_SHM_DATA, value);
355 u32 b43_hf_read(struct b43_wldev * dev)
359 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
361 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
366 /* Write HostFlags */
367 void b43_hf_write(struct b43_wldev *dev, u32 value)
369 b43_shm_write16(dev, B43_SHM_SHARED,
370 B43_SHM_SH_HOSTFLO, (value & 0x0000FFFF));
371 b43_shm_write16(dev, B43_SHM_SHARED,
372 B43_SHM_SH_HOSTFHI, ((value & 0xFFFF0000) >> 16));
375 void b43_tsf_read(struct b43_wldev *dev, u64 * tsf)
377 /* We need to be careful. As we read the TSF from multiple
378 * registers, we should take care of register overflows.
379 * In theory, the whole tsf read process should be atomic.
380 * We try to be atomic here, by restaring the read process,
381 * if any of the high registers changed (overflew).
383 if (dev->dev->id.revision >= 3) {
384 u32 low, high, high2;
387 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
388 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
389 high2 = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
390 } while (unlikely(high != high2));
398 u16 test1, test2, test3;
401 v3 = b43_read16(dev, B43_MMIO_TSF_3);
402 v2 = b43_read16(dev, B43_MMIO_TSF_2);
403 v1 = b43_read16(dev, B43_MMIO_TSF_1);
404 v0 = b43_read16(dev, B43_MMIO_TSF_0);
406 test3 = b43_read16(dev, B43_MMIO_TSF_3);
407 test2 = b43_read16(dev, B43_MMIO_TSF_2);
408 test1 = b43_read16(dev, B43_MMIO_TSF_1);
409 } while (v3 != test3 || v2 != test2 || v1 != test1);
423 static void b43_time_lock(struct b43_wldev *dev)
427 macctl = b43_read32(dev, B43_MMIO_MACCTL);
428 macctl |= B43_MACCTL_TBTTHOLD;
429 b43_write32(dev, B43_MMIO_MACCTL, macctl);
430 /* Commit the write */
431 b43_read32(dev, B43_MMIO_MACCTL);
434 static void b43_time_unlock(struct b43_wldev *dev)
438 macctl = b43_read32(dev, B43_MMIO_MACCTL);
439 macctl &= ~B43_MACCTL_TBTTHOLD;
440 b43_write32(dev, B43_MMIO_MACCTL, macctl);
441 /* Commit the write */
442 b43_read32(dev, B43_MMIO_MACCTL);
445 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
447 /* Be careful with the in-progress timer.
448 * First zero out the low register, so we have a full
449 * register-overflow duration to complete the operation.
451 if (dev->dev->id.revision >= 3) {
452 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
453 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
455 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, 0);
457 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, hi);
459 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, lo);
461 u16 v0 = (tsf & 0x000000000000FFFFULL);
462 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
463 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
464 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
466 b43_write16(dev, B43_MMIO_TSF_0, 0);
468 b43_write16(dev, B43_MMIO_TSF_3, v3);
470 b43_write16(dev, B43_MMIO_TSF_2, v2);
472 b43_write16(dev, B43_MMIO_TSF_1, v1);
474 b43_write16(dev, B43_MMIO_TSF_0, v0);
478 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
481 b43_tsf_write_locked(dev, tsf);
482 b43_time_unlock(dev);
486 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac)
488 static const u8 zero_addr[ETH_ALEN] = { 0 };
495 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
499 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
502 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
505 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
508 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
512 u8 mac_bssid[ETH_ALEN * 2];
516 bssid = dev->wl->bssid;
517 mac = dev->wl->mac_addr;
519 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
521 memcpy(mac_bssid, mac, ETH_ALEN);
522 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
524 /* Write our MAC address and BSSID to template ram */
525 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
526 tmp = (u32) (mac_bssid[i + 0]);
527 tmp |= (u32) (mac_bssid[i + 1]) << 8;
528 tmp |= (u32) (mac_bssid[i + 2]) << 16;
529 tmp |= (u32) (mac_bssid[i + 3]) << 24;
530 b43_ram_write(dev, 0x20 + i, tmp);
534 static void b43_upload_card_macaddress(struct b43_wldev *dev)
536 b43_write_mac_bssid_templates(dev);
537 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
540 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
542 /* slot_time is in usec. */
543 if (dev->phy.type != B43_PHYTYPE_G)
545 b43_write16(dev, 0x684, 510 + slot_time);
546 b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
549 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
551 b43_set_slot_time(dev, 9);
555 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
557 b43_set_slot_time(dev, 20);
561 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
562 * Returns the _previously_ enabled IRQ mask.
564 static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask)
568 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
569 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask);
574 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
575 * Returns the _previously_ enabled IRQ mask.
577 static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask)
581 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
582 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
587 /* Synchronize IRQ top- and bottom-half.
588 * IRQs must be masked before calling this.
589 * This must not be called with the irq_lock held.
591 static void b43_synchronize_irq(struct b43_wldev *dev)
593 synchronize_irq(dev->dev->irq);
594 tasklet_kill(&dev->isr_tasklet);
597 /* DummyTransmission function, as documented on
598 * http://bcm-specs.sipsolutions.net/DummyTransmission
600 void b43_dummy_transmission(struct b43_wldev *dev)
602 struct b43_phy *phy = &dev->phy;
603 unsigned int i, max_loop;
616 buffer[0] = 0x000201CC;
621 buffer[0] = 0x000B846E;
628 for (i = 0; i < 5; i++)
629 b43_ram_write(dev, i * 4, buffer[i]);
632 b43_read32(dev, B43_MMIO_MACCTL);
634 b43_write16(dev, 0x0568, 0x0000);
635 b43_write16(dev, 0x07C0, 0x0000);
636 value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0);
637 b43_write16(dev, 0x050C, value);
638 b43_write16(dev, 0x0508, 0x0000);
639 b43_write16(dev, 0x050A, 0x0000);
640 b43_write16(dev, 0x054C, 0x0000);
641 b43_write16(dev, 0x056A, 0x0014);
642 b43_write16(dev, 0x0568, 0x0826);
643 b43_write16(dev, 0x0500, 0x0000);
644 b43_write16(dev, 0x0502, 0x0030);
646 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
647 b43_radio_write16(dev, 0x0051, 0x0017);
648 for (i = 0x00; i < max_loop; i++) {
649 value = b43_read16(dev, 0x050E);
654 for (i = 0x00; i < 0x0A; i++) {
655 value = b43_read16(dev, 0x050E);
660 for (i = 0x00; i < 0x0A; i++) {
661 value = b43_read16(dev, 0x0690);
662 if (!(value & 0x0100))
666 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
667 b43_radio_write16(dev, 0x0051, 0x0037);
670 static void key_write(struct b43_wldev *dev,
671 u8 index, u8 algorithm, const u8 * key)
678 /* Key index/algo block */
679 kidx = b43_kidx_to_fw(dev, index);
680 value = ((kidx << 4) | algorithm);
681 b43_shm_write16(dev, B43_SHM_SHARED,
682 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
684 /* Write the key to the Key Table Pointer offset */
685 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
686 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
688 value |= (u16) (key[i + 1]) << 8;
689 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
693 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr)
695 u32 addrtmp[2] = { 0, 0, };
696 u8 per_sta_keys_start = 8;
698 if (b43_new_kidx_api(dev))
699 per_sta_keys_start = 4;
701 B43_WARN_ON(index < per_sta_keys_start);
702 /* We have two default TX keys and possibly two default RX keys.
703 * Physical mac 0 is mapped to physical key 4 or 8, depending
704 * on the firmware version.
705 * So we must adjust the index here.
707 index -= per_sta_keys_start;
710 addrtmp[0] = addr[0];
711 addrtmp[0] |= ((u32) (addr[1]) << 8);
712 addrtmp[0] |= ((u32) (addr[2]) << 16);
713 addrtmp[0] |= ((u32) (addr[3]) << 24);
714 addrtmp[1] = addr[4];
715 addrtmp[1] |= ((u32) (addr[5]) << 8);
718 if (dev->dev->id.revision >= 5) {
719 /* Receive match transmitter address mechanism */
720 b43_shm_write32(dev, B43_SHM_RCMTA,
721 (index * 2) + 0, addrtmp[0]);
722 b43_shm_write16(dev, B43_SHM_RCMTA,
723 (index * 2) + 1, addrtmp[1]);
725 /* RXE (Receive Engine) and
726 * PSM (Programmable State Machine) mechanism
729 /* TODO write to RCM 16, 19, 22 and 25 */
731 b43_shm_write32(dev, B43_SHM_SHARED,
732 B43_SHM_SH_PSM + (index * 6) + 0,
734 b43_shm_write16(dev, B43_SHM_SHARED,
735 B43_SHM_SH_PSM + (index * 6) + 4,
741 static void do_key_write(struct b43_wldev *dev,
742 u8 index, u8 algorithm,
743 const u8 * key, size_t key_len, const u8 * mac_addr)
745 u8 buf[B43_SEC_KEYSIZE] = { 0, };
746 u8 per_sta_keys_start = 8;
748 if (b43_new_kidx_api(dev))
749 per_sta_keys_start = 4;
751 B43_WARN_ON(index >= dev->max_nr_keys);
752 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
754 if (index >= per_sta_keys_start)
755 keymac_write(dev, index, NULL); /* First zero out mac. */
757 memcpy(buf, key, key_len);
758 key_write(dev, index, algorithm, buf);
759 if (index >= per_sta_keys_start)
760 keymac_write(dev, index, mac_addr);
762 dev->key[index].algorithm = algorithm;
765 static int b43_key_write(struct b43_wldev *dev,
766 int index, u8 algorithm,
767 const u8 * key, size_t key_len,
769 struct ieee80211_key_conf *keyconf)
774 if (key_len > B43_SEC_KEYSIZE)
776 for (i = 0; i < dev->max_nr_keys; i++) {
777 /* Check that we don't already have this key. */
778 B43_WARN_ON(dev->key[i].keyconf == keyconf);
781 /* Either pairwise key or address is 00:00:00:00:00:00
782 * for transmit-only keys. Search the index. */
783 if (b43_new_kidx_api(dev))
787 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
788 if (!dev->key[i].keyconf) {
795 b43err(dev->wl, "Out of hardware key memory\n");
799 B43_WARN_ON(index > 3);
801 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
802 if ((index <= 3) && !b43_new_kidx_api(dev)) {
804 B43_WARN_ON(mac_addr);
805 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
807 keyconf->hw_key_idx = index;
808 dev->key[index].keyconf = keyconf;
813 static int b43_key_clear(struct b43_wldev *dev, int index)
815 if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys)))
817 do_key_write(dev, index, B43_SEC_ALGO_NONE,
818 NULL, B43_SEC_KEYSIZE, NULL);
819 if ((index <= 3) && !b43_new_kidx_api(dev)) {
820 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
821 NULL, B43_SEC_KEYSIZE, NULL);
823 dev->key[index].keyconf = NULL;
828 static void b43_clear_keys(struct b43_wldev *dev)
832 for (i = 0; i < dev->max_nr_keys; i++)
833 b43_key_clear(dev, i);
836 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
844 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
845 (ps_flags & B43_PS_DISABLED));
846 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
848 if (ps_flags & B43_PS_ENABLED) {
850 } else if (ps_flags & B43_PS_DISABLED) {
853 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
854 // and thus is not an AP and we are associated, set bit 25
856 if (ps_flags & B43_PS_AWAKE) {
858 } else if (ps_flags & B43_PS_ASLEEP) {
861 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
862 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
863 // successful, set bit26
866 /* FIXME: For now we force awake-on and hwps-off */
870 macctl = b43_read32(dev, B43_MMIO_MACCTL);
872 macctl |= B43_MACCTL_HWPS;
874 macctl &= ~B43_MACCTL_HWPS;
876 macctl |= B43_MACCTL_AWAKE;
878 macctl &= ~B43_MACCTL_AWAKE;
879 b43_write32(dev, B43_MMIO_MACCTL, macctl);
881 b43_read32(dev, B43_MMIO_MACCTL);
882 if (awake && dev->dev->id.revision >= 5) {
883 /* Wait for the microcode to wake up. */
884 for (i = 0; i < 100; i++) {
885 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
886 B43_SHM_SH_UCODESTAT);
887 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
894 /* Turn the Analog ON/OFF */
895 static void b43_switch_analog(struct b43_wldev *dev, int on)
897 b43_write16(dev, B43_MMIO_PHY0, on ? 0 : 0xF4);
900 void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
905 flags |= B43_TMSLOW_PHYCLKEN;
906 flags |= B43_TMSLOW_PHYRESET;
907 ssb_device_enable(dev->dev, flags);
908 msleep(2); /* Wait for the PLL to turn on. */
910 /* Now take the PHY out of Reset again */
911 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
912 tmslow |= SSB_TMSLOW_FGC;
913 tmslow &= ~B43_TMSLOW_PHYRESET;
914 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
915 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
917 tmslow &= ~SSB_TMSLOW_FGC;
918 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
919 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
923 b43_switch_analog(dev, 1);
925 macctl = b43_read32(dev, B43_MMIO_MACCTL);
926 macctl &= ~B43_MACCTL_GMODE;
927 if (flags & B43_TMSLOW_GMODE)
928 macctl |= B43_MACCTL_GMODE;
929 macctl |= B43_MACCTL_IHR_ENABLED;
930 b43_write32(dev, B43_MMIO_MACCTL, macctl);
933 static void handle_irq_transmit_status(struct b43_wldev *dev)
937 struct b43_txstatus stat;
940 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
941 if (!(v0 & 0x00000001))
943 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
945 stat.cookie = (v0 >> 16);
946 stat.seq = (v1 & 0x0000FFFF);
947 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
948 tmp = (v0 & 0x0000FFFF);
949 stat.frame_count = ((tmp & 0xF000) >> 12);
950 stat.rts_count = ((tmp & 0x0F00) >> 8);
951 stat.supp_reason = ((tmp & 0x001C) >> 2);
952 stat.pm_indicated = !!(tmp & 0x0080);
953 stat.intermediate = !!(tmp & 0x0040);
954 stat.for_ampdu = !!(tmp & 0x0020);
955 stat.acked = !!(tmp & 0x0002);
957 b43_handle_txstatus(dev, &stat);
961 static void drain_txstatus_queue(struct b43_wldev *dev)
965 if (dev->dev->id.revision < 5)
967 /* Read all entries from the microcode TXstatus FIFO
968 * and throw them away.
971 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
972 if (!(dummy & 0x00000001))
974 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
978 static u32 b43_jssi_read(struct b43_wldev *dev)
982 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
984 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
989 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
991 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
992 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
995 static void b43_generate_noise_sample(struct b43_wldev *dev)
997 b43_jssi_write(dev, 0x7F7F7F7F);
998 b43_write32(dev, B43_MMIO_MACCMD,
999 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
1000 B43_WARN_ON(dev->noisecalc.channel_at_start != dev->phy.channel);
1003 static void b43_calculate_link_quality(struct b43_wldev *dev)
1005 /* Top half of Link Quality calculation. */
1007 if (dev->noisecalc.calculation_running)
1009 dev->noisecalc.channel_at_start = dev->phy.channel;
1010 dev->noisecalc.calculation_running = 1;
1011 dev->noisecalc.nr_samples = 0;
1013 b43_generate_noise_sample(dev);
1016 static void handle_irq_noise(struct b43_wldev *dev)
1018 struct b43_phy *phy = &dev->phy;
1024 /* Bottom half of Link Quality calculation. */
1026 B43_WARN_ON(!dev->noisecalc.calculation_running);
1027 if (dev->noisecalc.channel_at_start != phy->channel)
1028 goto drop_calculation;
1029 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1030 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1031 noise[2] == 0x7F || noise[3] == 0x7F)
1034 /* Get the noise samples. */
1035 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1036 i = dev->noisecalc.nr_samples;
1037 noise[0] = limit_value(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1038 noise[1] = limit_value(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1039 noise[2] = limit_value(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1040 noise[3] = limit_value(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1041 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1042 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1043 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1044 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1045 dev->noisecalc.nr_samples++;
1046 if (dev->noisecalc.nr_samples == 8) {
1047 /* Calculate the Link Quality by the noise samples. */
1049 for (i = 0; i < 8; i++) {
1050 for (j = 0; j < 4; j++)
1051 average += dev->noisecalc.samples[i][j];
1057 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1058 tmp = (tmp / 128) & 0x1F;
1068 dev->stats.link_noise = average;
1070 dev->noisecalc.calculation_running = 0;
1074 b43_generate_noise_sample(dev);
1077 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1079 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_AP)) {
1082 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1083 b43_power_saving_ctl_bits(dev, 0);
1085 if (b43_is_mode(dev->wl, IEEE80211_IF_TYPE_IBSS))
1089 static void handle_irq_atim_end(struct b43_wldev *dev)
1091 if (dev->dfq_valid) {
1092 b43_write32(dev, B43_MMIO_MACCMD,
1093 b43_read32(dev, B43_MMIO_MACCMD)
1094 | B43_MACCMD_DFQ_VALID);
1099 static void handle_irq_pmq(struct b43_wldev *dev)
1106 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1107 if (!(tmp & 0x00000008))
1110 /* 16bit write is odd, but correct. */
1111 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1114 static void b43_write_template_common(struct b43_wldev *dev,
1115 const u8 * data, u16 size,
1117 u16 shm_size_offset, u8 rate)
1120 struct b43_plcp_hdr4 plcp;
1123 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1124 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1125 ram_offset += sizeof(u32);
1126 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1127 * So leave the first two bytes of the next write blank.
1129 tmp = (u32) (data[0]) << 16;
1130 tmp |= (u32) (data[1]) << 24;
1131 b43_ram_write(dev, ram_offset, tmp);
1132 ram_offset += sizeof(u32);
1133 for (i = 2; i < size; i += sizeof(u32)) {
1134 tmp = (u32) (data[i + 0]);
1136 tmp |= (u32) (data[i + 1]) << 8;
1138 tmp |= (u32) (data[i + 2]) << 16;
1140 tmp |= (u32) (data[i + 3]) << 24;
1141 b43_ram_write(dev, ram_offset + i - 2, tmp);
1143 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1144 size + sizeof(struct b43_plcp_hdr6));
1147 static void b43_write_beacon_template(struct b43_wldev *dev,
1149 u16 shm_size_offset, u8 rate)
1152 const struct ieee80211_mgmt *bcn;
1156 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1157 len = min((size_t) dev->wl->current_beacon->len,
1158 0x200 - sizeof(struct b43_plcp_hdr6));
1160 b43_write_template_common(dev, (const u8 *)bcn,
1161 len, ram_offset, shm_size_offset, rate);
1163 /* Find the position of the TIM and the DTIM_period value
1164 * and write them to SHM. */
1165 ie = bcn->u.beacon.variable;
1166 for (i = 0; i < len - 2; ) {
1167 uint8_t ie_id, ie_len;
1174 /* This is the TIM Information Element */
1176 /* Check whether the ie_len is in the beacon data range. */
1177 if (len < ie_len + 2 + i)
1179 /* A valid TIM is at least 4 bytes long. */
1184 tim_position = sizeof(struct b43_plcp_hdr6);
1185 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1188 dtim_period = ie[i + 3];
1190 b43_shm_write16(dev, B43_SHM_SHARED,
1191 B43_SHM_SH_TIMBPOS, tim_position);
1192 b43_shm_write16(dev, B43_SHM_SHARED,
1193 B43_SHM_SH_DTIMPER, dtim_period);
1199 b43warn(dev->wl, "Did not find a valid TIM IE in "
1200 "the beacon template packet. AP or IBSS operation "
1201 "may be broken.\n");
1205 static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
1206 u16 shm_offset, u16 size, u8 rate)
1208 struct b43_plcp_hdr4 plcp;
1213 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1214 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1216 B43_RATE_TO_BASE100KBPS(rate));
1217 /* Write PLCP in two parts and timing for packet transfer */
1218 tmp = le32_to_cpu(plcp.data);
1219 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF);
1220 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16);
1221 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur));
1224 /* Instead of using custom probe response template, this function
1225 * just patches custom beacon template by:
1226 * 1) Changing packet type
1227 * 2) Patching duration field
1230 static const u8 * b43_generate_probe_resp(struct b43_wldev *dev,
1231 u16 *dest_size, u8 rate)
1235 u16 src_size, elem_size, src_pos, dest_pos;
1237 struct ieee80211_hdr *hdr;
1240 src_size = dev->wl->current_beacon->len;
1241 src_data = (const u8 *)dev->wl->current_beacon->data;
1243 /* Get the start offset of the variable IEs in the packet. */
1244 ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
1245 B43_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt, u.beacon.variable));
1247 if (B43_WARN_ON(src_size < ie_start))
1250 dest_data = kmalloc(src_size, GFP_ATOMIC);
1251 if (unlikely(!dest_data))
1254 /* Copy the static data and all Information Elements, except the TIM. */
1255 memcpy(dest_data, src_data, ie_start);
1257 dest_pos = ie_start;
1258 for ( ; src_pos < src_size - 2; src_pos += elem_size) {
1259 elem_size = src_data[src_pos + 1] + 2;
1260 if (src_data[src_pos] == 5) {
1261 /* This is the TIM. */
1264 memcpy(dest_data + dest_pos, src_data + src_pos,
1266 dest_pos += elem_size;
1268 *dest_size = dest_pos;
1269 hdr = (struct ieee80211_hdr *)dest_data;
1271 /* Set the frame control. */
1272 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1273 IEEE80211_STYPE_PROBE_RESP);
1274 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1275 dev->wl->vif, *dest_size,
1276 B43_RATE_TO_BASE100KBPS(rate));
1277 hdr->duration_id = dur;
1282 static void b43_write_probe_resp_template(struct b43_wldev *dev,
1284 u16 shm_size_offset, u8 rate)
1286 const u8 *probe_resp_data;
1289 size = dev->wl->current_beacon->len;
1290 probe_resp_data = b43_generate_probe_resp(dev, &size, rate);
1291 if (unlikely(!probe_resp_data))
1294 /* Looks like PLCP headers plus packet timings are stored for
1295 * all possible basic rates
1297 b43_write_probe_resp_plcp(dev, 0x31A, size, B43_CCK_RATE_1MB);
1298 b43_write_probe_resp_plcp(dev, 0x32C, size, B43_CCK_RATE_2MB);
1299 b43_write_probe_resp_plcp(dev, 0x33E, size, B43_CCK_RATE_5MB);
1300 b43_write_probe_resp_plcp(dev, 0x350, size, B43_CCK_RATE_11MB);
1302 size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6));
1303 b43_write_template_common(dev, probe_resp_data,
1304 size, ram_offset, shm_size_offset, rate);
1305 kfree(probe_resp_data);
1308 /* Asynchronously update the packet templates in template RAM. */
1309 static void b43_update_templates(struct b43_wl *wl, struct sk_buff *beacon)
1311 unsigned long flags;
1313 /* This is the top half of the ansynchronous beacon update.
1314 * The bottom half is the beacon IRQ.
1315 * Beacon update must be asynchronous to avoid sending an
1316 * invalid beacon. This can happen for example, if the firmware
1317 * transmits a beacon while we are updating it. */
1319 spin_lock_irqsave(&wl->irq_lock, flags);
1321 if (wl->current_beacon)
1322 dev_kfree_skb_any(wl->current_beacon);
1323 wl->current_beacon = beacon;
1324 wl->beacon0_uploaded = 0;
1325 wl->beacon1_uploaded = 0;
1327 spin_unlock_irqrestore(&wl->irq_lock, flags);
1330 static void b43_set_ssid(struct b43_wldev *dev, const u8 * ssid, u8 ssid_len)
1335 len = min((u16) ssid_len, (u16) 0x100);
1336 for (i = 0; i < len; i += sizeof(u32)) {
1337 tmp = (u32) (ssid[i + 0]);
1339 tmp |= (u32) (ssid[i + 1]) << 8;
1341 tmp |= (u32) (ssid[i + 2]) << 16;
1343 tmp |= (u32) (ssid[i + 3]) << 24;
1344 b43_shm_write32(dev, B43_SHM_SHARED, 0x380 + i, tmp);
1346 b43_shm_write16(dev, B43_SHM_SHARED, 0x48, len);
1349 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1352 if (dev->dev->id.revision >= 3) {
1353 b43_write32(dev, 0x188, (beacon_int << 16));
1355 b43_write16(dev, 0x606, (beacon_int >> 6));
1356 b43_write16(dev, 0x610, beacon_int);
1358 b43_time_unlock(dev);
1361 static void handle_irq_beacon(struct b43_wldev *dev)
1363 struct b43_wl *wl = dev->wl;
1366 if (!b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
1369 /* This is the bottom half of the asynchronous beacon update. */
1371 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1372 if (!(cmd & B43_MACCMD_BEACON0_VALID)) {
1373 if (!wl->beacon0_uploaded) {
1374 b43_write_beacon_template(dev, 0x68, 0x18,
1376 b43_write_probe_resp_template(dev, 0x268, 0x4A,
1378 wl->beacon0_uploaded = 1;
1380 cmd |= B43_MACCMD_BEACON0_VALID;
1382 if (!(cmd & B43_MACCMD_BEACON1_VALID)) {
1383 if (!wl->beacon1_uploaded) {
1384 b43_write_beacon_template(dev, 0x468, 0x1A,
1386 wl->beacon1_uploaded = 1;
1388 cmd |= B43_MACCMD_BEACON1_VALID;
1390 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1393 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1398 /* Interrupt handler bottom-half */
1399 static void b43_interrupt_tasklet(struct b43_wldev *dev)
1402 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1403 u32 merged_dma_reason = 0;
1405 unsigned long flags;
1407 spin_lock_irqsave(&dev->wl->irq_lock, flags);
1409 B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
1411 reason = dev->irq_reason;
1412 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1413 dma_reason[i] = dev->dma_reason[i];
1414 merged_dma_reason |= dma_reason[i];
1417 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1418 b43err(dev->wl, "MAC transmission error\n");
1420 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1421 b43err(dev->wl, "PHY transmission error\n");
1423 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1424 atomic_set(&dev->phy.txerr_cnt,
1425 B43_PHY_TX_BADNESS_LIMIT);
1426 b43err(dev->wl, "Too many PHY TX errors, "
1427 "restarting the controller\n");
1428 b43_controller_restart(dev, "PHY TX errors");
1432 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1433 B43_DMAIRQ_NONFATALMASK))) {
1434 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1435 b43err(dev->wl, "Fatal DMA error: "
1436 "0x%08X, 0x%08X, 0x%08X, "
1437 "0x%08X, 0x%08X, 0x%08X\n",
1438 dma_reason[0], dma_reason[1],
1439 dma_reason[2], dma_reason[3],
1440 dma_reason[4], dma_reason[5]);
1441 b43_controller_restart(dev, "DMA error");
1443 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1446 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1447 b43err(dev->wl, "DMA error: "
1448 "0x%08X, 0x%08X, 0x%08X, "
1449 "0x%08X, 0x%08X, 0x%08X\n",
1450 dma_reason[0], dma_reason[1],
1451 dma_reason[2], dma_reason[3],
1452 dma_reason[4], dma_reason[5]);
1456 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1457 handle_irq_ucode_debug(dev);
1458 if (reason & B43_IRQ_TBTT_INDI)
1459 handle_irq_tbtt_indication(dev);
1460 if (reason & B43_IRQ_ATIM_END)
1461 handle_irq_atim_end(dev);
1462 if (reason & B43_IRQ_BEACON)
1463 handle_irq_beacon(dev);
1464 if (reason & B43_IRQ_PMQ)
1465 handle_irq_pmq(dev);
1466 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1468 if (reason & B43_IRQ_NOISESAMPLE_OK)
1469 handle_irq_noise(dev);
1471 /* Check the DMA reason registers for received data. */
1472 if (dma_reason[0] & B43_DMAIRQ_RX_DONE)
1473 b43_dma_rx(dev->dma.rx_ring0);
1474 if (dma_reason[3] & B43_DMAIRQ_RX_DONE)
1475 b43_dma_rx(dev->dma.rx_ring3);
1476 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1477 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1478 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1479 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1481 if (reason & B43_IRQ_TX_OK)
1482 handle_irq_transmit_status(dev);
1484 b43_interrupt_enable(dev, dev->irq_savedstate);
1486 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1489 static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
1491 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1493 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1494 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1495 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1496 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1497 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1498 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1501 /* Interrupt handler top-half */
1502 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1504 irqreturn_t ret = IRQ_NONE;
1505 struct b43_wldev *dev = dev_id;
1511 spin_lock(&dev->wl->irq_lock);
1513 if (b43_status(dev) < B43_STAT_STARTED)
1515 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1516 if (reason == 0xffffffff) /* shared IRQ */
1519 reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1523 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1525 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1527 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1529 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1531 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1533 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1536 b43_interrupt_ack(dev, reason);
1537 /* disable all IRQs. They are enabled again in the bottom half. */
1538 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
1539 /* save the reason code and call our bottom half. */
1540 dev->irq_reason = reason;
1541 tasklet_schedule(&dev->isr_tasklet);
1544 spin_unlock(&dev->wl->irq_lock);
1549 static void b43_release_firmware(struct b43_wldev *dev)
1551 release_firmware(dev->fw.ucode);
1552 dev->fw.ucode = NULL;
1553 release_firmware(dev->fw.pcm);
1555 release_firmware(dev->fw.initvals);
1556 dev->fw.initvals = NULL;
1557 release_firmware(dev->fw.initvals_band);
1558 dev->fw.initvals_band = NULL;
1561 static void b43_print_fw_helptext(struct b43_wl *wl)
1563 b43err(wl, "You must go to "
1564 "http://linuxwireless.org/en/users/Drivers/b43#devicefirmware "
1565 "and download the correct firmware (version 4).\n");
1568 static int do_request_fw(struct b43_wldev *dev,
1570 const struct firmware **fw)
1572 char path[sizeof(modparam_fwpostfix) + 32];
1573 struct b43_fw_header *hdr;
1580 snprintf(path, ARRAY_SIZE(path),
1582 modparam_fwpostfix, name);
1583 err = request_firmware(fw, path, dev->dev->dev);
1585 b43err(dev->wl, "Firmware file \"%s\" not found "
1586 "or load failed.\n", path);
1589 if ((*fw)->size < sizeof(struct b43_fw_header))
1591 hdr = (struct b43_fw_header *)((*fw)->data);
1592 switch (hdr->type) {
1593 case B43_FW_TYPE_UCODE:
1594 case B43_FW_TYPE_PCM:
1595 size = be32_to_cpu(hdr->size);
1596 if (size != (*fw)->size - sizeof(struct b43_fw_header))
1599 case B43_FW_TYPE_IV:
1610 b43err(dev->wl, "Firmware file \"%s\" format error.\n", path);
1614 static int b43_request_firmware(struct b43_wldev *dev)
1616 struct b43_firmware *fw = &dev->fw;
1617 const u8 rev = dev->dev->id.revision;
1618 const char *filename;
1622 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
1624 if ((rev >= 5) && (rev <= 10))
1625 filename = "ucode5";
1626 else if ((rev >= 11) && (rev <= 12))
1627 filename = "ucode11";
1629 filename = "ucode13";
1632 err = do_request_fw(dev, filename, &fw->ucode);
1637 if ((rev >= 5) && (rev <= 10))
1643 err = do_request_fw(dev, filename, &fw->pcm);
1647 if (!fw->initvals) {
1648 switch (dev->phy.type) {
1650 if ((rev >= 5) && (rev <= 10)) {
1651 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
1652 filename = "a0g1initvals5";
1654 filename = "a0g0initvals5";
1656 goto err_no_initvals;
1659 if ((rev >= 5) && (rev <= 10))
1660 filename = "b0g0initvals5";
1662 filename = "lp0initvals13";
1664 goto err_no_initvals;
1667 goto err_no_initvals;
1669 err = do_request_fw(dev, filename, &fw->initvals);
1673 if (!fw->initvals_band) {
1674 switch (dev->phy.type) {
1676 if ((rev >= 5) && (rev <= 10)) {
1677 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
1678 filename = "a0g1bsinitvals5";
1680 filename = "a0g0bsinitvals5";
1681 } else if (rev >= 11)
1684 goto err_no_initvals;
1687 if ((rev >= 5) && (rev <= 10))
1688 filename = "b0g0bsinitvals5";
1692 goto err_no_initvals;
1695 goto err_no_initvals;
1697 err = do_request_fw(dev, filename, &fw->initvals_band);
1705 b43_print_fw_helptext(dev->wl);
1710 b43err(dev->wl, "No microcode available for core rev %u\n", rev);
1715 b43err(dev->wl, "No PCM available for core rev %u\n", rev);
1720 b43err(dev->wl, "No Initial Values firmware file for PHY %u, "
1721 "core rev %u\n", dev->phy.type, rev);
1725 b43_release_firmware(dev);
1729 static int b43_upload_microcode(struct b43_wldev *dev)
1731 const size_t hdr_len = sizeof(struct b43_fw_header);
1733 unsigned int i, len;
1734 u16 fwrev, fwpatch, fwdate, fwtime;
1738 /* Upload Microcode. */
1739 data = (__be32 *) (dev->fw.ucode->data + hdr_len);
1740 len = (dev->fw.ucode->size - hdr_len) / sizeof(__be32);
1741 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
1742 for (i = 0; i < len; i++) {
1743 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1748 /* Upload PCM data. */
1749 data = (__be32 *) (dev->fw.pcm->data + hdr_len);
1750 len = (dev->fw.pcm->size - hdr_len) / sizeof(__be32);
1751 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
1752 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
1753 /* No need for autoinc bit in SHM_HW */
1754 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
1755 for (i = 0; i < len; i++) {
1756 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
1761 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
1762 b43_write32(dev, B43_MMIO_MACCTL,
1763 B43_MACCTL_PSM_RUN |
1764 B43_MACCTL_IHR_ENABLED | B43_MACCTL_INFRA);
1766 /* Wait for the microcode to load and respond */
1769 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1770 if (tmp == B43_IRQ_MAC_SUSPENDED)
1774 b43err(dev->wl, "Microcode not responding\n");
1775 b43_print_fw_helptext(dev->wl);
1781 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
1783 /* Get and check the revisions. */
1784 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
1785 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
1786 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
1787 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
1789 if (fwrev <= 0x128) {
1790 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
1791 "binary drivers older than version 4.x is unsupported. "
1792 "You must upgrade your firmware files.\n");
1793 b43_print_fw_helptext(dev->wl);
1794 b43_write32(dev, B43_MMIO_MACCTL, 0);
1798 b43dbg(dev->wl, "Loading firmware version %u.%u "
1799 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
1801 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
1802 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
1804 dev->fw.rev = fwrev;
1805 dev->fw.patch = fwpatch;
1811 static int b43_write_initvals(struct b43_wldev *dev,
1812 const struct b43_iv *ivals,
1816 const struct b43_iv *iv;
1821 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
1823 for (i = 0; i < count; i++) {
1824 if (array_size < sizeof(iv->offset_size))
1826 array_size -= sizeof(iv->offset_size);
1827 offset = be16_to_cpu(iv->offset_size);
1828 bit32 = !!(offset & B43_IV_32BIT);
1829 offset &= B43_IV_OFFSET_MASK;
1830 if (offset >= 0x1000)
1835 if (array_size < sizeof(iv->data.d32))
1837 array_size -= sizeof(iv->data.d32);
1839 value = be32_to_cpu(get_unaligned(&iv->data.d32));
1840 b43_write32(dev, offset, value);
1842 iv = (const struct b43_iv *)((const uint8_t *)iv +
1848 if (array_size < sizeof(iv->data.d16))
1850 array_size -= sizeof(iv->data.d16);
1852 value = be16_to_cpu(iv->data.d16);
1853 b43_write16(dev, offset, value);
1855 iv = (const struct b43_iv *)((const uint8_t *)iv +
1866 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
1867 b43_print_fw_helptext(dev->wl);
1872 static int b43_upload_initvals(struct b43_wldev *dev)
1874 const size_t hdr_len = sizeof(struct b43_fw_header);
1875 const struct b43_fw_header *hdr;
1876 struct b43_firmware *fw = &dev->fw;
1877 const struct b43_iv *ivals;
1881 hdr = (const struct b43_fw_header *)(fw->initvals->data);
1882 ivals = (const struct b43_iv *)(fw->initvals->data + hdr_len);
1883 count = be32_to_cpu(hdr->size);
1884 err = b43_write_initvals(dev, ivals, count,
1885 fw->initvals->size - hdr_len);
1888 if (fw->initvals_band) {
1889 hdr = (const struct b43_fw_header *)(fw->initvals_band->data);
1890 ivals = (const struct b43_iv *)(fw->initvals_band->data + hdr_len);
1891 count = be32_to_cpu(hdr->size);
1892 err = b43_write_initvals(dev, ivals, count,
1893 fw->initvals_band->size - hdr_len);
1902 /* Initialize the GPIOs
1903 * http://bcm-specs.sipsolutions.net/GPIO
1905 static int b43_gpio_init(struct b43_wldev *dev)
1907 struct ssb_bus *bus = dev->dev->bus;
1908 struct ssb_device *gpiodev, *pcidev = NULL;
1911 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
1912 & ~B43_MACCTL_GPOUTSMSK);
1914 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
1919 if (dev->dev->bus->chip_id == 0x4301) {
1923 if (0 /* FIXME: conditional unknown */ ) {
1924 b43_write16(dev, B43_MMIO_GPIO_MASK,
1925 b43_read16(dev, B43_MMIO_GPIO_MASK)
1930 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
1931 b43_write16(dev, B43_MMIO_GPIO_MASK,
1932 b43_read16(dev, B43_MMIO_GPIO_MASK)
1937 if (dev->dev->id.revision >= 2)
1938 mask |= 0x0010; /* FIXME: This is redundant. */
1940 #ifdef CONFIG_SSB_DRIVER_PCICORE
1941 pcidev = bus->pcicore.dev;
1943 gpiodev = bus->chipco.dev ? : pcidev;
1946 ssb_write32(gpiodev, B43_GPIO_CONTROL,
1947 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
1953 /* Turn off all GPIO stuff. Call this on module unload, for example. */
1954 static void b43_gpio_cleanup(struct b43_wldev *dev)
1956 struct ssb_bus *bus = dev->dev->bus;
1957 struct ssb_device *gpiodev, *pcidev = NULL;
1959 #ifdef CONFIG_SSB_DRIVER_PCICORE
1960 pcidev = bus->pcicore.dev;
1962 gpiodev = bus->chipco.dev ? : pcidev;
1965 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
1968 /* http://bcm-specs.sipsolutions.net/EnableMac */
1969 void b43_mac_enable(struct b43_wldev *dev)
1971 dev->mac_suspended--;
1972 B43_WARN_ON(dev->mac_suspended < 0);
1973 B43_WARN_ON(irqs_disabled());
1974 if (dev->mac_suspended == 0) {
1975 b43_write32(dev, B43_MMIO_MACCTL,
1976 b43_read32(dev, B43_MMIO_MACCTL)
1977 | B43_MACCTL_ENABLED);
1978 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
1979 B43_IRQ_MAC_SUSPENDED);
1981 b43_read32(dev, B43_MMIO_MACCTL);
1982 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1983 b43_power_saving_ctl_bits(dev, 0);
1985 /* Re-enable IRQs. */
1986 spin_lock_irq(&dev->wl->irq_lock);
1987 b43_interrupt_enable(dev, dev->irq_savedstate);
1988 spin_unlock_irq(&dev->wl->irq_lock);
1992 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
1993 void b43_mac_suspend(struct b43_wldev *dev)
1999 B43_WARN_ON(irqs_disabled());
2000 B43_WARN_ON(dev->mac_suspended < 0);
2002 if (dev->mac_suspended == 0) {
2003 /* Mask IRQs before suspending MAC. Otherwise
2004 * the MAC stays busy and won't suspend. */
2005 spin_lock_irq(&dev->wl->irq_lock);
2006 tmp = b43_interrupt_disable(dev, B43_IRQ_ALL);
2007 spin_unlock_irq(&dev->wl->irq_lock);
2008 b43_synchronize_irq(dev);
2009 dev->irq_savedstate = tmp;
2011 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2012 b43_write32(dev, B43_MMIO_MACCTL,
2013 b43_read32(dev, B43_MMIO_MACCTL)
2014 & ~B43_MACCTL_ENABLED);
2015 /* force pci to flush the write */
2016 b43_read32(dev, B43_MMIO_MACCTL);
2017 for (i = 40; i; i--) {
2018 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2019 if (tmp & B43_IRQ_MAC_SUSPENDED)
2023 b43err(dev->wl, "MAC suspend failed\n");
2026 dev->mac_suspended++;
2029 static void b43_adjust_opmode(struct b43_wldev *dev)
2031 struct b43_wl *wl = dev->wl;
2035 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2036 /* Reset status to STA infrastructure mode. */
2037 ctl &= ~B43_MACCTL_AP;
2038 ctl &= ~B43_MACCTL_KEEP_CTL;
2039 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2040 ctl &= ~B43_MACCTL_KEEP_BAD;
2041 ctl &= ~B43_MACCTL_PROMISC;
2042 ctl &= ~B43_MACCTL_BEACPROMISC;
2043 ctl |= B43_MACCTL_INFRA;
2045 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2046 ctl |= B43_MACCTL_AP;
2047 else if (b43_is_mode(wl, IEEE80211_IF_TYPE_IBSS))
2048 ctl &= ~B43_MACCTL_INFRA;
2050 if (wl->filter_flags & FIF_CONTROL)
2051 ctl |= B43_MACCTL_KEEP_CTL;
2052 if (wl->filter_flags & FIF_FCSFAIL)
2053 ctl |= B43_MACCTL_KEEP_BAD;
2054 if (wl->filter_flags & FIF_PLCPFAIL)
2055 ctl |= B43_MACCTL_KEEP_BADPLCP;
2056 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2057 ctl |= B43_MACCTL_PROMISC;
2058 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2059 ctl |= B43_MACCTL_BEACPROMISC;
2061 /* Workaround: On old hardware the HW-MAC-address-filter
2062 * doesn't work properly, so always run promisc in filter
2063 * it in software. */
2064 if (dev->dev->id.revision <= 4)
2065 ctl |= B43_MACCTL_PROMISC;
2067 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2070 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2071 if (dev->dev->bus->chip_id == 0x4306 &&
2072 dev->dev->bus->chip_rev == 3)
2077 b43_write16(dev, 0x612, cfp_pretbtt);
2080 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2086 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2089 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2091 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2092 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2095 static void b43_rate_memory_init(struct b43_wldev *dev)
2097 switch (dev->phy.type) {
2100 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2101 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2102 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2103 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2104 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2105 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2106 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2107 if (dev->phy.type == B43_PHYTYPE_A)
2111 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2112 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2113 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2114 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2121 /* Set the TX-Antenna for management frames sent by firmware. */
2122 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2129 ant |= B43_TX4_PHY_ANT0;
2132 ant |= B43_TX4_PHY_ANT1;
2134 case B43_ANTENNA_AUTO:
2135 ant |= B43_TX4_PHY_ANTLAST;
2141 /* FIXME We also need to set the other flags of the PHY control field somewhere. */
2144 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
2145 tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2146 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, tmp);
2148 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
2149 tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2150 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2151 /* For Probe Resposes */
2152 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
2153 tmp = (tmp & ~B43_TX4_PHY_ANT) | ant;
2154 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2157 /* This is the opposite of b43_chip_init() */
2158 static void b43_chip_exit(struct b43_wldev *dev)
2160 b43_radio_turn_off(dev, 1);
2161 b43_gpio_cleanup(dev);
2162 /* firmware is released later */
2165 /* Initialize the chip
2166 * http://bcm-specs.sipsolutions.net/ChipInit
2168 static int b43_chip_init(struct b43_wldev *dev)
2170 struct b43_phy *phy = &dev->phy;
2175 b43_write32(dev, B43_MMIO_MACCTL,
2176 B43_MACCTL_PSM_JMP0 | B43_MACCTL_IHR_ENABLED);
2178 err = b43_request_firmware(dev);
2181 err = b43_upload_microcode(dev);
2183 goto out; /* firmware is released later */
2185 err = b43_gpio_init(dev);
2187 goto out; /* firmware is released later */
2189 err = b43_upload_initvals(dev);
2191 goto err_gpio_clean;
2192 b43_radio_turn_on(dev);
2194 b43_write16(dev, 0x03E6, 0x0000);
2195 err = b43_phy_init(dev);
2199 /* Select initial Interference Mitigation. */
2200 tmp = phy->interfmode;
2201 phy->interfmode = B43_INTERFMODE_NONE;
2202 b43_radio_set_interference_mitigation(dev, tmp);
2204 b43_set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2205 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2207 if (phy->type == B43_PHYTYPE_B) {
2208 value16 = b43_read16(dev, 0x005E);
2210 b43_write16(dev, 0x005E, value16);
2212 b43_write32(dev, 0x0100, 0x01000000);
2213 if (dev->dev->id.revision < 5)
2214 b43_write32(dev, 0x010C, 0x01000000);
2216 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2217 & ~B43_MACCTL_INFRA);
2218 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2219 | B43_MACCTL_INFRA);
2221 /* Probe Response Timeout value */
2222 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2223 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2225 /* Initially set the wireless operation mode. */
2226 b43_adjust_opmode(dev);
2228 if (dev->dev->id.revision < 3) {
2229 b43_write16(dev, 0x060E, 0x0000);
2230 b43_write16(dev, 0x0610, 0x8000);
2231 b43_write16(dev, 0x0604, 0x0000);
2232 b43_write16(dev, 0x0606, 0x0200);
2234 b43_write32(dev, 0x0188, 0x80000000);
2235 b43_write32(dev, 0x018C, 0x02000000);
2237 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2238 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2239 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2240 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2241 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2242 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2243 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2245 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2246 value32 |= 0x00100000;
2247 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2249 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2250 dev->dev->bus->chipco.fast_pwrup_delay);
2253 b43dbg(dev->wl, "Chip initialized\n");
2258 b43_radio_turn_off(dev, 1);
2260 b43_gpio_cleanup(dev);
2264 static void b43_periodic_every120sec(struct b43_wldev *dev)
2266 struct b43_phy *phy = &dev->phy;
2268 if (phy->type != B43_PHYTYPE_G || phy->rev < 2)
2271 b43_mac_suspend(dev);
2272 b43_lo_g_measure(dev);
2273 b43_mac_enable(dev);
2274 if (b43_has_hardware_pctl(phy))
2275 b43_lo_g_ctl_mark_all_unused(dev);
2278 static void b43_periodic_every60sec(struct b43_wldev *dev)
2280 struct b43_phy *phy = &dev->phy;
2282 if (!b43_has_hardware_pctl(phy))
2283 b43_lo_g_ctl_mark_all_unused(dev);
2284 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_RSSI) {
2285 b43_mac_suspend(dev);
2286 b43_calc_nrssi_slope(dev);
2287 if ((phy->radio_ver == 0x2050) && (phy->radio_rev == 8)) {
2288 u8 old_chan = phy->channel;
2290 /* VCO Calibration */
2292 b43_radio_selectchannel(dev, 1, 0);
2294 b43_radio_selectchannel(dev, 13, 0);
2295 b43_radio_selectchannel(dev, old_chan, 0);
2297 b43_mac_enable(dev);
2301 static void b43_periodic_every30sec(struct b43_wldev *dev)
2303 /* Update device statistics. */
2304 b43_calculate_link_quality(dev);
2307 static void b43_periodic_every15sec(struct b43_wldev *dev)
2309 struct b43_phy *phy = &dev->phy;
2311 if (phy->type == B43_PHYTYPE_G) {
2312 //TODO: update_aci_moving_average
2313 if (phy->aci_enable && phy->aci_wlan_automatic) {
2314 b43_mac_suspend(dev);
2315 if (!phy->aci_enable && 1 /*TODO: not scanning? */ ) {
2316 if (0 /*TODO: bunch of conditions */ ) {
2317 b43_radio_set_interference_mitigation
2318 (dev, B43_INTERFMODE_MANUALWLAN);
2320 } else if (1 /*TODO*/) {
2322 if ((aci_average > 1000) && !(b43_radio_aci_scan(dev))) {
2323 b43_radio_set_interference_mitigation(dev,
2324 B43_INTERFMODE_NONE);
2328 b43_mac_enable(dev);
2329 } else if (phy->interfmode == B43_INTERFMODE_NONWLAN &&
2331 //TODO: implement rev1 workaround
2334 b43_phy_xmitpower(dev); //FIXME: unless scanning?
2335 //TODO for APHY (temperature?)
2337 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2341 static void do_periodic_work(struct b43_wldev *dev)
2345 state = dev->periodic_state;
2347 b43_periodic_every120sec(dev);
2349 b43_periodic_every60sec(dev);
2351 b43_periodic_every30sec(dev);
2352 b43_periodic_every15sec(dev);
2355 /* Periodic work locking policy:
2356 * The whole periodic work handler is protected by
2357 * wl->mutex. If another lock is needed somewhere in the
2358 * pwork callchain, it's aquired in-place, where it's needed.
2360 static void b43_periodic_work_handler(struct work_struct *work)
2362 struct b43_wldev *dev = container_of(work, struct b43_wldev,
2363 periodic_work.work);
2364 struct b43_wl *wl = dev->wl;
2365 unsigned long delay;
2367 mutex_lock(&wl->mutex);
2369 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2371 if (b43_debug(dev, B43_DBG_PWORK_STOP))
2374 do_periodic_work(dev);
2376 dev->periodic_state++;
2378 if (b43_debug(dev, B43_DBG_PWORK_FAST))
2379 delay = msecs_to_jiffies(50);
2381 delay = round_jiffies_relative(HZ * 15);
2382 queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
2384 mutex_unlock(&wl->mutex);
2387 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2389 struct delayed_work *work = &dev->periodic_work;
2391 dev->periodic_state = 0;
2392 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
2393 queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2396 /* Check if communication with the device works correctly. */
2397 static int b43_validate_chipaccess(struct b43_wldev *dev)
2401 backup = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2403 /* Check for read/write and endianness problems. */
2404 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2405 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2407 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2408 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
2411 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup);
2413 if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
2414 /* The 32bit register shadows the two 16bit registers
2415 * with update sideeffects. Validate this. */
2416 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
2417 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
2418 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
2420 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
2423 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
2425 v = b43_read32(dev, B43_MMIO_MACCTL);
2426 v |= B43_MACCTL_GMODE;
2427 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
2432 b43err(dev->wl, "Failed to validate the chipaccess\n");
2436 static void b43_security_init(struct b43_wldev *dev)
2438 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2439 B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2440 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
2441 /* KTP is a word address, but we address SHM bytewise.
2442 * So multiply by two.
2445 if (dev->dev->id.revision >= 5) {
2446 /* Number of RCMTA address slots */
2447 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8);
2449 b43_clear_keys(dev);
2452 static int b43_rng_read(struct hwrng *rng, u32 * data)
2454 struct b43_wl *wl = (struct b43_wl *)rng->priv;
2455 unsigned long flags;
2457 /* Don't take wl->mutex here, as it could deadlock with
2458 * hwrng internal locking. It's not needed to take
2459 * wl->mutex here, anyway. */
2461 spin_lock_irqsave(&wl->irq_lock, flags);
2462 *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
2463 spin_unlock_irqrestore(&wl->irq_lock, flags);
2465 return (sizeof(u16));
2468 static void b43_rng_exit(struct b43_wl *wl)
2470 if (wl->rng_initialized)
2471 hwrng_unregister(&wl->rng);
2474 static int b43_rng_init(struct b43_wl *wl)
2478 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2479 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2480 wl->rng.name = wl->rng_name;
2481 wl->rng.data_read = b43_rng_read;
2482 wl->rng.priv = (unsigned long)wl;
2483 wl->rng_initialized = 1;
2484 err = hwrng_register(&wl->rng);
2486 wl->rng_initialized = 0;
2487 b43err(wl, "Failed to register the random "
2488 "number generator (%d)\n", err);
2494 static int b43_op_tx(struct ieee80211_hw *hw,
2495 struct sk_buff *skb,
2496 struct ieee80211_tx_control *ctl)
2498 struct b43_wl *wl = hw_to_b43_wl(hw);
2499 struct b43_wldev *dev = wl->current_dev;
2504 if (unlikely(b43_status(dev) < B43_STAT_STARTED))
2506 /* DMA-TX is done without a global lock. */
2507 err = b43_dma_tx(dev, skb, ctl);
2510 return NETDEV_TX_BUSY;
2511 return NETDEV_TX_OK;
2514 static int b43_op_conf_tx(struct ieee80211_hw *hw,
2516 const struct ieee80211_tx_queue_params *params)
2521 static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
2522 struct ieee80211_tx_queue_stats *stats)
2524 struct b43_wl *wl = hw_to_b43_wl(hw);
2525 struct b43_wldev *dev = wl->current_dev;
2526 unsigned long flags;
2531 spin_lock_irqsave(&wl->irq_lock, flags);
2532 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
2533 b43_dma_get_tx_stats(dev, stats);
2536 spin_unlock_irqrestore(&wl->irq_lock, flags);
2541 static int b43_op_get_stats(struct ieee80211_hw *hw,
2542 struct ieee80211_low_level_stats *stats)
2544 struct b43_wl *wl = hw_to_b43_wl(hw);
2545 unsigned long flags;
2547 spin_lock_irqsave(&wl->irq_lock, flags);
2548 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
2549 spin_unlock_irqrestore(&wl->irq_lock, flags);
2554 static const char *phymode_to_string(unsigned int phymode)
2569 static int find_wldev_for_phymode(struct b43_wl *wl,
2570 unsigned int phymode,
2571 struct b43_wldev **dev, bool * gmode)
2573 struct b43_wldev *d;
2575 list_for_each_entry(d, &wl->devlist, list) {
2576 if (d->phy.possible_phymodes & phymode) {
2577 /* Ok, this device supports the PHY-mode.
2578 * Now figure out how the gmode bit has to be
2579 * set to support it. */
2580 if (phymode == B43_PHYMODE_A)
2593 static void b43_put_phy_into_reset(struct b43_wldev *dev)
2595 struct ssb_device *sdev = dev->dev;
2598 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2599 tmslow &= ~B43_TMSLOW_GMODE;
2600 tmslow |= B43_TMSLOW_PHYRESET;
2601 tmslow |= SSB_TMSLOW_FGC;
2602 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2605 tmslow = ssb_read32(sdev, SSB_TMSLOW);
2606 tmslow &= ~SSB_TMSLOW_FGC;
2607 tmslow |= B43_TMSLOW_PHYRESET;
2608 ssb_write32(sdev, SSB_TMSLOW, tmslow);
2612 /* Expects wl->mutex locked */
2613 static int b43_switch_phymode(struct b43_wl *wl, unsigned int new_mode)
2615 struct b43_wldev *up_dev;
2616 struct b43_wldev *down_dev;
2621 err = find_wldev_for_phymode(wl, new_mode, &up_dev, &gmode);
2623 b43err(wl, "Could not find a device for %s-PHY mode\n",
2624 phymode_to_string(new_mode));
2627 if ((up_dev == wl->current_dev) &&
2628 (!!wl->current_dev->phy.gmode == !!gmode)) {
2629 /* This device is already running. */
2632 b43dbg(wl, "Reconfiguring PHYmode to %s-PHY\n",
2633 phymode_to_string(new_mode));
2634 down_dev = wl->current_dev;
2636 prev_status = b43_status(down_dev);
2637 /* Shutdown the currently running core. */
2638 if (prev_status >= B43_STAT_STARTED)
2639 b43_wireless_core_stop(down_dev);
2640 if (prev_status >= B43_STAT_INITIALIZED)
2641 b43_wireless_core_exit(down_dev);
2643 if (down_dev != up_dev) {
2644 /* We switch to a different core, so we put PHY into
2645 * RESET on the old core. */
2646 b43_put_phy_into_reset(down_dev);
2649 /* Now start the new core. */
2650 up_dev->phy.gmode = gmode;
2651 if (prev_status >= B43_STAT_INITIALIZED) {
2652 err = b43_wireless_core_init(up_dev);
2654 b43err(wl, "Fatal: Could not initialize device for "
2655 "newly selected %s-PHY mode\n",
2656 phymode_to_string(new_mode));
2660 if (prev_status >= B43_STAT_STARTED) {
2661 err = b43_wireless_core_start(up_dev);
2663 b43err(wl, "Fatal: Coult not start device for "
2664 "newly selected %s-PHY mode\n",
2665 phymode_to_string(new_mode));
2666 b43_wireless_core_exit(up_dev);
2670 B43_WARN_ON(b43_status(up_dev) != prev_status);
2672 wl->current_dev = up_dev;
2676 /* Whoops, failed to init the new core. No core is operating now. */
2677 wl->current_dev = NULL;
2681 /* Check if the use of the antenna that ieee80211 told us to
2682 * use is possible. This will fall back to DEFAULT.
2683 * "antenna_nr" is the antenna identifier we got from ieee80211. */
2684 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
2689 if (antenna_nr == 0) {
2690 /* Zero means "use default antenna". That's always OK. */
2694 /* Get the mask of available antennas. */
2696 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
2698 antenna_mask = dev->dev->bus->sprom.ant_available_a;
2700 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
2701 /* This antenna is not available. Fall back to default. */
2708 static int b43_antenna_from_ieee80211(struct b43_wldev *dev, u8 antenna)
2710 antenna = b43_ieee80211_antenna_sanitize(dev, antenna);
2712 case 0: /* default/diversity */
2713 return B43_ANTENNA_DEFAULT;
2714 case 1: /* Antenna 0 */
2715 return B43_ANTENNA0;
2716 case 2: /* Antenna 1 */
2717 return B43_ANTENNA1;
2719 return B43_ANTENNA_DEFAULT;
2723 static int b43_op_config(struct ieee80211_hw *hw, struct ieee80211_conf *conf)
2725 struct b43_wl *wl = hw_to_b43_wl(hw);
2726 struct b43_wldev *dev;
2727 struct b43_phy *phy;
2728 unsigned long flags;
2729 unsigned int new_phymode = 0xFFFF;
2734 mutex_lock(&wl->mutex);
2736 /* Switch the PHY mode (if necessary). */
2737 switch (conf->phymode) {
2738 case MODE_IEEE80211A:
2739 new_phymode = B43_PHYMODE_A;
2741 case MODE_IEEE80211B:
2742 new_phymode = B43_PHYMODE_B;
2744 case MODE_IEEE80211G:
2745 new_phymode = B43_PHYMODE_G;
2750 err = b43_switch_phymode(wl, new_phymode);
2752 goto out_unlock_mutex;
2753 dev = wl->current_dev;
2756 /* Disable IRQs while reconfiguring the device.
2757 * This makes it possible to drop the spinlock throughout
2758 * the reconfiguration process. */
2759 spin_lock_irqsave(&wl->irq_lock, flags);
2760 if (b43_status(dev) < B43_STAT_STARTED) {
2761 spin_unlock_irqrestore(&wl->irq_lock, flags);
2762 goto out_unlock_mutex;
2764 savedirqs = b43_interrupt_disable(dev, B43_IRQ_ALL);
2765 spin_unlock_irqrestore(&wl->irq_lock, flags);
2766 b43_synchronize_irq(dev);
2768 /* Switch to the requested channel.
2769 * The firmware takes care of races with the TX handler. */
2770 if (conf->channel_val != phy->channel)
2771 b43_radio_selectchannel(dev, conf->channel_val, 0);
2773 /* Enable/Disable ShortSlot timing. */
2774 if ((!!(conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)) !=
2776 B43_WARN_ON(phy->type != B43_PHYTYPE_G);
2777 if (conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME)
2778 b43_short_slot_timing_enable(dev);
2780 b43_short_slot_timing_disable(dev);
2783 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
2785 /* Adjust the desired TX power level. */
2786 if (conf->power_level != 0) {
2787 if (conf->power_level != phy->power_level) {
2788 phy->power_level = conf->power_level;
2789 b43_phy_xmitpower(dev);
2793 /* Antennas for RX and management frame TX. */
2794 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_tx);
2795 b43_mgmtframe_txantenna(dev, antenna);
2796 antenna = b43_antenna_from_ieee80211(dev, conf->antenna_sel_rx);
2797 b43_set_rx_antenna(dev, antenna);
2799 /* Update templates for AP mode. */
2800 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP))
2801 b43_set_beacon_int(dev, conf->beacon_int);
2803 if (!!conf->radio_enabled != phy->radio_on) {
2804 if (conf->radio_enabled) {
2805 b43_radio_turn_on(dev);
2806 b43info(dev->wl, "Radio turned on by software\n");
2807 if (!dev->radio_hw_enable) {
2808 b43info(dev->wl, "The hardware RF-kill button "
2809 "still turns the radio physically off. "
2810 "Press the button to turn it on.\n");
2813 b43_radio_turn_off(dev, 0);
2814 b43info(dev->wl, "Radio turned off by software\n");
2818 spin_lock_irqsave(&wl->irq_lock, flags);
2819 b43_interrupt_enable(dev, savedirqs);
2821 spin_unlock_irqrestore(&wl->irq_lock, flags);
2823 mutex_unlock(&wl->mutex);
2828 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2829 const u8 *local_addr, const u8 *addr,
2830 struct ieee80211_key_conf *key)
2832 struct b43_wl *wl = hw_to_b43_wl(hw);
2833 struct b43_wldev *dev;
2834 unsigned long flags;
2838 DECLARE_MAC_BUF(mac);
2840 if (modparam_nohwcrypt)
2841 return -ENOSPC; /* User disabled HW-crypto */
2843 mutex_lock(&wl->mutex);
2844 spin_lock_irqsave(&wl->irq_lock, flags);
2846 dev = wl->current_dev;
2848 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
2854 if (key->keylen == 5)
2855 algorithm = B43_SEC_ALGO_WEP40;
2857 algorithm = B43_SEC_ALGO_WEP104;
2860 algorithm = B43_SEC_ALGO_TKIP;
2863 algorithm = B43_SEC_ALGO_AES;
2869 index = (u8) (key->keyidx);
2875 if (algorithm == B43_SEC_ALGO_TKIP) {
2876 /* FIXME: No TKIP hardware encryption for now. */
2881 if (is_broadcast_ether_addr(addr)) {
2882 /* addr is FF:FF:FF:FF:FF:FF for default keys */
2883 err = b43_key_write(dev, index, algorithm,
2884 key->key, key->keylen, NULL, key);
2887 * either pairwise key or address is 00:00:00:00:00:00
2888 * for transmit-only keys
2890 err = b43_key_write(dev, -1, algorithm,
2891 key->key, key->keylen, addr, key);
2896 if (algorithm == B43_SEC_ALGO_WEP40 ||
2897 algorithm == B43_SEC_ALGO_WEP104) {
2898 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
2901 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
2903 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2906 err = b43_key_clear(dev, key->hw_key_idx);
2915 spin_unlock_irqrestore(&wl->irq_lock, flags);
2916 mutex_unlock(&wl->mutex);
2918 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
2920 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
2921 print_mac(mac, addr));
2926 static void b43_op_configure_filter(struct ieee80211_hw *hw,
2927 unsigned int changed, unsigned int *fflags,
2928 int mc_count, struct dev_addr_list *mc_list)
2930 struct b43_wl *wl = hw_to_b43_wl(hw);
2931 struct b43_wldev *dev = wl->current_dev;
2932 unsigned long flags;
2939 spin_lock_irqsave(&wl->irq_lock, flags);
2940 *fflags &= FIF_PROMISC_IN_BSS |
2946 FIF_BCN_PRBRESP_PROMISC;
2948 changed &= FIF_PROMISC_IN_BSS |
2954 FIF_BCN_PRBRESP_PROMISC;
2956 wl->filter_flags = *fflags;
2958 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
2959 b43_adjust_opmode(dev);
2960 spin_unlock_irqrestore(&wl->irq_lock, flags);
2963 static int b43_op_config_interface(struct ieee80211_hw *hw,
2964 struct ieee80211_vif *vif,
2965 struct ieee80211_if_conf *conf)
2967 struct b43_wl *wl = hw_to_b43_wl(hw);
2968 struct b43_wldev *dev = wl->current_dev;
2969 unsigned long flags;
2973 mutex_lock(&wl->mutex);
2974 spin_lock_irqsave(&wl->irq_lock, flags);
2975 B43_WARN_ON(wl->vif != vif);
2977 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
2979 memset(wl->bssid, 0, ETH_ALEN);
2980 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
2981 if (b43_is_mode(wl, IEEE80211_IF_TYPE_AP)) {
2982 B43_WARN_ON(conf->type != IEEE80211_IF_TYPE_AP);
2983 b43_set_ssid(dev, conf->ssid, conf->ssid_len);
2985 b43_update_templates(wl, conf->beacon);
2987 b43_write_mac_bssid_templates(dev);
2989 spin_unlock_irqrestore(&wl->irq_lock, flags);
2990 mutex_unlock(&wl->mutex);
2995 /* Locking: wl->mutex */
2996 static void b43_wireless_core_stop(struct b43_wldev *dev)
2998 struct b43_wl *wl = dev->wl;
2999 unsigned long flags;
3001 if (b43_status(dev) < B43_STAT_STARTED)
3004 /* Disable and sync interrupts. We must do this before than
3005 * setting the status to INITIALIZED, as the interrupt handler
3006 * won't care about IRQs then. */
3007 spin_lock_irqsave(&wl->irq_lock, flags);
3008 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
3009 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
3010 spin_unlock_irqrestore(&wl->irq_lock, flags);
3011 b43_synchronize_irq(dev);
3013 b43_set_status(dev, B43_STAT_INITIALIZED);
3015 mutex_unlock(&wl->mutex);
3016 /* Must unlock as it would otherwise deadlock. No races here.
3017 * Cancel the possibly running self-rearming periodic work. */
3018 cancel_delayed_work_sync(&dev->periodic_work);
3019 mutex_lock(&wl->mutex);
3021 ieee80211_stop_queues(wl->hw); //FIXME this could cause a deadlock, as mac80211 seems buggy.
3023 b43_mac_suspend(dev);
3024 free_irq(dev->dev->irq, dev);
3025 b43dbg(wl, "Wireless interface stopped\n");
3028 /* Locking: wl->mutex */
3029 static int b43_wireless_core_start(struct b43_wldev *dev)
3033 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3035 drain_txstatus_queue(dev);
3036 err = request_irq(dev->dev->irq, b43_interrupt_handler,
3037 IRQF_SHARED, KBUILD_MODNAME, dev);
3039 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3043 /* We are ready to run. */
3044 b43_set_status(dev, B43_STAT_STARTED);
3046 /* Start data flow (TX/RX). */
3047 b43_mac_enable(dev);
3048 b43_interrupt_enable(dev, dev->irq_savedstate);
3049 ieee80211_start_queues(dev->wl->hw);
3051 /* Start maintainance work */
3052 b43_periodic_tasks_setup(dev);
3054 b43dbg(dev->wl, "Wireless interface started\n");
3059 /* Get PHY and RADIO versioning numbers */
3060 static int b43_phy_versioning(struct b43_wldev *dev)
3062 struct b43_phy *phy = &dev->phy;
3070 int unsupported = 0;
3072 /* Get PHY versioning */
3073 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3074 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3075 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3076 phy_rev = (tmp & B43_PHYVER_VERSION);
3083 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3091 #ifdef CONFIG_B43_NPHY
3101 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3102 "(Analog %u, Type %u, Revision %u)\n",
3103 analog_type, phy_type, phy_rev);
3106 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3107 analog_type, phy_type, phy_rev);
3109 /* Get RADIO versioning */
3110 if (dev->dev->bus->chip_id == 0x4317) {
3111 if (dev->dev->bus->chip_rev == 0)
3113 else if (dev->dev->bus->chip_rev == 1)
3118 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3119 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH);
3121 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3122 tmp |= b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3124 radio_manuf = (tmp & 0x00000FFF);
3125 radio_ver = (tmp & 0x0FFFF000) >> 12;
3126 radio_rev = (tmp & 0xF0000000) >> 28;
3127 if (radio_manuf != 0x17F /* Broadcom */)
3131 if (radio_ver != 0x2060)
3135 if (radio_manuf != 0x17F)
3139 if ((radio_ver & 0xFFF0) != 0x2050)
3143 if (radio_ver != 0x2050)
3154 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
3155 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3156 radio_manuf, radio_ver, radio_rev);
3159 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3160 radio_manuf, radio_ver, radio_rev);
3162 phy->radio_manuf = radio_manuf;
3163 phy->radio_ver = radio_ver;
3164 phy->radio_rev = radio_rev;
3166 phy->analog = analog_type;
3167 phy->type = phy_type;
3173 static void setup_struct_phy_for_init(struct b43_wldev *dev,
3174 struct b43_phy *phy)
3176 struct b43_txpower_lo_control *lo;
3179 memset(phy->minlowsig, 0xFF, sizeof(phy->minlowsig));
3180 memset(phy->minlowsigpos, 0, sizeof(phy->minlowsigpos));
3182 phy->aci_enable = 0;
3183 phy->aci_wlan_automatic = 0;
3184 phy->aci_hw_rssi = 0;
3186 phy->radio_off_context.valid = 0;
3188 lo = phy->lo_control;
3190 memset(lo, 0, sizeof(*(phy->lo_control)));
3194 phy->max_lb_gain = 0;
3195 phy->trsw_rx_gain = 0;
3196 phy->txpwr_offset = 0;
3199 phy->nrssislope = 0;
3200 for (i = 0; i < ARRAY_SIZE(phy->nrssi); i++)
3201 phy->nrssi[i] = -1000;
3202 for (i = 0; i < ARRAY_SIZE(phy->nrssi_lt); i++)
3203 phy->nrssi_lt[i] = i;
3205 phy->lofcal = 0xFFFF;
3206 phy->initval = 0xFFFF;
3208 phy->interfmode = B43_INTERFMODE_NONE;
3209 phy->channel = 0xFF;
3211 phy->hardware_power_control = !!modparam_hwpctl;
3213 /* PHY TX errors counter. */
3214 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3216 /* OFDM-table address caching. */
3217 phy->ofdmtab_addr_direction = B43_OFDMTAB_DIRECTION_UNKNOWN;
3220 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
3224 /* Assume the radio is enabled. If it's not enabled, the state will
3225 * immediately get fixed on the first periodic work run. */
3226 dev->radio_hw_enable = 1;
3229 memset(&dev->stats, 0, sizeof(dev->stats));
3231 setup_struct_phy_for_init(dev, &dev->phy);
3233 /* IRQ related flags */
3234 dev->irq_reason = 0;
3235 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3236 dev->irq_savedstate = B43_IRQ_MASKTEMPLATE;
3238 dev->mac_suspended = 1;
3240 /* Noise calculation context */
3241 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3244 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
3246 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3249 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
3251 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
3254 hf = b43_hf_read(dev);
3255 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
3256 hf |= B43_HF_BTCOEXALT;
3258 hf |= B43_HF_BTCOEX;
3259 b43_hf_write(dev, hf);
3263 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
3267 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
3269 #ifdef CONFIG_SSB_DRIVER_PCICORE
3270 struct ssb_bus *bus = dev->dev->bus;
3273 if (bus->pcicore.dev &&
3274 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
3275 bus->pcicore.dev->id.revision <= 5) {
3276 /* IMCFGLO timeouts workaround. */
3277 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
3278 tmp &= ~SSB_IMCFGLO_REQTO;
3279 tmp &= ~SSB_IMCFGLO_SERTO;
3280 switch (bus->bustype) {
3281 case SSB_BUSTYPE_PCI:
3282 case SSB_BUSTYPE_PCMCIA:
3285 case SSB_BUSTYPE_SSB:
3289 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
3291 #endif /* CONFIG_SSB_DRIVER_PCICORE */
3294 /* Write the short and long frame retry limit values. */
3295 static void b43_set_retry_limits(struct b43_wldev *dev,
3296 unsigned int short_retry,
3297 unsigned int long_retry)
3299 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3300 * the chip-internal counter. */
3301 short_retry = min(short_retry, (unsigned int)0xF);
3302 long_retry = min(long_retry, (unsigned int)0xF);
3304 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3306 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3310 /* Shutdown a wireless core */
3311 /* Locking: wl->mutex */
3312 static void b43_wireless_core_exit(struct b43_wldev *dev)
3314 struct b43_phy *phy = &dev->phy;
3316 B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
3317 if (b43_status(dev) != B43_STAT_INITIALIZED)
3319 b43_set_status(dev, B43_STAT_UNINIT);
3322 b43_rng_exit(dev->wl);
3325 b43_radio_turn_off(dev, 1);
3326 b43_switch_analog(dev, 0);
3327 if (phy->dyn_tssi_tbl)
3328 kfree(phy->tssi2dbm);
3329 kfree(phy->lo_control);
3330 phy->lo_control = NULL;
3331 if (dev->wl->current_beacon) {
3332 dev_kfree_skb_any(dev->wl->current_beacon);
3333 dev->wl->current_beacon = NULL;
3336 ssb_device_disable(dev->dev, 0);
3337 ssb_bus_may_powerdown(dev->dev->bus);
3340 /* Initialize a wireless core */
3341 static int b43_wireless_core_init(struct b43_wldev *dev)
3343 struct b43_wl *wl = dev->wl;
3344 struct ssb_bus *bus = dev->dev->bus;
3345 struct ssb_sprom *sprom = &bus->sprom;
3346 struct b43_phy *phy = &dev->phy;
3350 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3352 err = ssb_bus_powerup(bus, 0);
3355 if (!ssb_device_is_enabled(dev->dev)) {
3356 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
3357 b43_wireless_core_reset(dev, tmp);
3360 if ((phy->type == B43_PHYTYPE_B) || (phy->type == B43_PHYTYPE_G)) {
3362 kzalloc(sizeof(*(phy->lo_control)), GFP_KERNEL);
3363 if (!phy->lo_control) {
3368 setup_struct_wldev_for_init(dev);
3370 err = b43_phy_init_tssi2dbm_table(dev);
3372 goto err_kfree_lo_control;
3374 /* Enable IRQ routing to this device. */
3375 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
3377 b43_imcfglo_timeouts_workaround(dev);
3378 b43_bluetooth_coext_disable(dev);
3379 b43_phy_early_init(dev);
3380 err = b43_chip_init(dev);
3382 goto err_kfree_tssitbl;
3383 b43_shm_write16(dev, B43_SHM_SHARED,
3384 B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
3385 hf = b43_hf_read(dev);
3386 if (phy->type == B43_PHYTYPE_G) {
3390 if (sprom->boardflags_lo & B43_BFL_PACTRL)
3391 hf |= B43_HF_OFDMPABOOST;
3392 } else if (phy->type == B43_PHYTYPE_B) {
3394 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
3397 b43_hf_write(dev, hf);
3399 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
3400 B43_DEFAULT_LONG_RETRY_LIMIT);
3401 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
3402 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
3404 /* Disable sending probe responses from firmware.
3405 * Setting the MaxTime to one usec will always trigger
3406 * a timeout, so we never send any probe resp.
3407 * A timeout of zero is infinite. */
3408 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
3410 b43_rate_memory_init(dev);
3412 /* Minimum Contention Window */
3413 if (phy->type == B43_PHYTYPE_B) {
3414 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
3416 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
3418 /* Maximum Contention Window */
3419 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
3421 err = b43_dma_init(dev);
3428 b43_write16(dev, 0x0612, 0x0050);
3429 b43_shm_write16(dev, B43_SHM_SHARED, 0x0416, 0x0050);
3430 b43_shm_write16(dev, B43_SHM_SHARED, 0x0414, 0x01F4);
3433 b43_bluetooth_coext_enable(dev);
3435 ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
3436 memset(wl->bssid, 0, ETH_ALEN);
3437 memset(wl->mac_addr, 0, ETH_ALEN);
3438 b43_upload_card_macaddress(dev);
3439 b43_security_init(dev);
3442 b43_set_status(dev, B43_STAT_INITIALIZED);
3451 if (phy->dyn_tssi_tbl)
3452 kfree(phy->tssi2dbm);
3453 err_kfree_lo_control:
3454 kfree(phy->lo_control);
3455 phy->lo_control = NULL;
3457 ssb_bus_may_powerdown(bus);
3458 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3462 static int b43_op_add_interface(struct ieee80211_hw *hw,
3463 struct ieee80211_if_init_conf *conf)
3465 struct b43_wl *wl = hw_to_b43_wl(hw);
3466 struct b43_wldev *dev;
3467 unsigned long flags;
3468 int err = -EOPNOTSUPP;
3470 /* TODO: allow WDS/AP devices to coexist */
3472 if (conf->type != IEEE80211_IF_TYPE_AP &&
3473 conf->type != IEEE80211_IF_TYPE_STA &&
3474 conf->type != IEEE80211_IF_TYPE_WDS &&
3475 conf->type != IEEE80211_IF_TYPE_IBSS)
3478 mutex_lock(&wl->mutex);
3480 goto out_mutex_unlock;
3482 b43dbg(wl, "Adding Interface type %d\n", conf->type);
3484 dev = wl->current_dev;
3486 wl->vif = conf->vif;
3487 wl->if_type = conf->type;
3488 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
3490 spin_lock_irqsave(&wl->irq_lock, flags);
3491 b43_adjust_opmode(dev);
3492 b43_upload_card_macaddress(dev);
3493 spin_unlock_irqrestore(&wl->irq_lock, flags);
3497 mutex_unlock(&wl->mutex);
3502 static void b43_op_remove_interface(struct ieee80211_hw *hw,
3503 struct ieee80211_if_init_conf *conf)
3505 struct b43_wl *wl = hw_to_b43_wl(hw);
3506 struct b43_wldev *dev = wl->current_dev;
3507 unsigned long flags;
3509 b43dbg(wl, "Removing Interface type %d\n", conf->type);
3511 mutex_lock(&wl->mutex);
3513 B43_WARN_ON(!wl->operating);
3514 B43_WARN_ON(wl->vif != conf->vif);
3519 spin_lock_irqsave(&wl->irq_lock, flags);
3520 b43_adjust_opmode(dev);
3521 memset(wl->mac_addr, 0, ETH_ALEN);
3522 b43_upload_card_macaddress(dev);
3523 spin_unlock_irqrestore(&wl->irq_lock, flags);
3525 mutex_unlock(&wl->mutex);
3528 static int b43_op_start(struct ieee80211_hw *hw)
3530 struct b43_wl *wl = hw_to_b43_wl(hw);
3531 struct b43_wldev *dev = wl->current_dev;
3535 /* First register RFkill.
3536 * LEDs that are registered later depend on it. */
3537 b43_rfkill_init(dev);
3539 mutex_lock(&wl->mutex);
3541 if (b43_status(dev) < B43_STAT_INITIALIZED) {
3542 err = b43_wireless_core_init(dev);
3544 goto out_mutex_unlock;
3548 if (b43_status(dev) < B43_STAT_STARTED) {
3549 err = b43_wireless_core_start(dev);
3552 b43_wireless_core_exit(dev);
3553 goto out_mutex_unlock;
3558 mutex_unlock(&wl->mutex);
3563 static void b43_op_stop(struct ieee80211_hw *hw)
3565 struct b43_wl *wl = hw_to_b43_wl(hw);
3566 struct b43_wldev *dev = wl->current_dev;
3568 b43_rfkill_exit(dev);
3570 mutex_lock(&wl->mutex);
3571 if (b43_status(dev) >= B43_STAT_STARTED)
3572 b43_wireless_core_stop(dev);
3573 b43_wireless_core_exit(dev);
3574 mutex_unlock(&wl->mutex);
3577 static int b43_op_set_retry_limit(struct ieee80211_hw *hw,
3578 u32 short_retry_limit, u32 long_retry_limit)
3580 struct b43_wl *wl = hw_to_b43_wl(hw);
3581 struct b43_wldev *dev;
3584 mutex_lock(&wl->mutex);
3585 dev = wl->current_dev;
3586 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED))) {
3590 b43_set_retry_limits(dev, short_retry_limit, long_retry_limit);
3592 mutex_unlock(&wl->mutex);
3597 static int b43_op_beacon_set_tim(struct ieee80211_hw *hw, int aid, int set)
3599 struct b43_wl *wl = hw_to_b43_wl(hw);
3600 struct sk_buff *beacon;
3602 /* We could modify the existing beacon and set the aid bit in
3603 * the TIM field, but that would probably require resizing and
3604 * moving of data within the beacon template.
3605 * Simply request a new beacon and let mac80211 do the hard work. */
3606 beacon = ieee80211_beacon_get(hw, wl->vif, NULL);
3607 if (unlikely(!beacon))
3609 b43_update_templates(wl, beacon);
3614 static int b43_op_ibss_beacon_update(struct ieee80211_hw *hw,
3615 struct sk_buff *beacon,
3616 struct ieee80211_tx_control *ctl)
3618 struct b43_wl *wl = hw_to_b43_wl(hw);
3620 b43_update_templates(wl, beacon);
3625 static const struct ieee80211_ops b43_hw_ops = {
3627 .conf_tx = b43_op_conf_tx,
3628 .add_interface = b43_op_add_interface,
3629 .remove_interface = b43_op_remove_interface,
3630 .config = b43_op_config,
3631 .config_interface = b43_op_config_interface,
3632 .configure_filter = b43_op_configure_filter,
3633 .set_key = b43_op_set_key,
3634 .get_stats = b43_op_get_stats,
3635 .get_tx_stats = b43_op_get_tx_stats,
3636 .start = b43_op_start,
3637 .stop = b43_op_stop,
3638 .set_retry_limit = b43_op_set_retry_limit,
3639 .set_tim = b43_op_beacon_set_tim,
3640 .beacon_update = b43_op_ibss_beacon_update,
3643 /* Hard-reset the chip. Do not call this directly.
3644 * Use b43_controller_restart()
3646 static void b43_chip_reset(struct work_struct *work)
3648 struct b43_wldev *dev =
3649 container_of(work, struct b43_wldev, restart_work);
3650 struct b43_wl *wl = dev->wl;
3654 mutex_lock(&wl->mutex);
3656 prev_status = b43_status(dev);
3657 /* Bring the device down... */
3658 if (prev_status >= B43_STAT_STARTED)
3659 b43_wireless_core_stop(dev);
3660 if (prev_status >= B43_STAT_INITIALIZED)
3661 b43_wireless_core_exit(dev);
3663 /* ...and up again. */
3664 if (prev_status >= B43_STAT_INITIALIZED) {
3665 err = b43_wireless_core_init(dev);
3669 if (prev_status >= B43_STAT_STARTED) {
3670 err = b43_wireless_core_start(dev);
3672 b43_wireless_core_exit(dev);
3677 mutex_unlock(&wl->mutex);
3679 b43err(wl, "Controller restart FAILED\n");
3681 b43info(wl, "Controller restarted\n");
3684 static int b43_setup_modes(struct b43_wldev *dev,
3685 bool have_2ghz_phy, bool have_5ghz_phy)
3687 struct ieee80211_hw *hw = dev->wl->hw;
3688 struct ieee80211_hw_mode *mode;
3689 struct b43_phy *phy = &dev->phy;
3692 /* XXX: This function will go away soon, when mac80211
3693 * band stuff is rewritten. So this is just a hack.
3694 * For now we always claim GPHY mode, as there is no
3695 * support for NPHY and APHY in the device, yet.
3696 * This assumption is OK, as any B, N or A PHY will already
3697 * have died a horrible sanity check death earlier. */
3699 mode = &phy->hwmodes[0];
3700 mode->mode = MODE_IEEE80211G;
3701 mode->num_channels = b43_2ghz_chantable_size;
3702 mode->channels = b43_2ghz_chantable;
3703 mode->num_rates = b43_g_ratetable_size;
3704 mode->rates = b43_g_ratetable;
3705 err = ieee80211_register_hwmode(hw, mode);
3708 phy->possible_phymodes |= B43_PHYMODE_G;
3713 static void b43_wireless_core_detach(struct b43_wldev *dev)
3715 /* We release firmware that late to not be required to re-request
3716 * is all the time when we reinit the core. */
3717 b43_release_firmware(dev);
3720 static int b43_wireless_core_attach(struct b43_wldev *dev)
3722 struct b43_wl *wl = dev->wl;
3723 struct ssb_bus *bus = dev->dev->bus;
3724 struct pci_dev *pdev = bus->host_pci;
3726 bool have_2ghz_phy = 0, have_5ghz_phy = 0;
3729 /* Do NOT do any device initialization here.
3730 * Do it in wireless_core_init() instead.
3731 * This function is for gathering basic information about the HW, only.
3732 * Also some structs may be set up here. But most likely you want to have
3733 * that in core_init(), too.
3736 err = ssb_bus_powerup(bus, 0);
3738 b43err(wl, "Bus powerup failed\n");
3741 /* Get the PHY type. */
3742 if (dev->dev->id.revision >= 5) {
3745 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
3746 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
3747 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
3751 dev->phy.gmode = have_2ghz_phy;
3752 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3753 b43_wireless_core_reset(dev, tmp);
3755 err = b43_phy_versioning(dev);
3758 /* Check if this device supports multiband. */
3760 (pdev->device != 0x4312 &&
3761 pdev->device != 0x4319 && pdev->device != 0x4324)) {
3762 /* No multiband support. */
3765 switch (dev->phy.type) {
3777 if (dev->phy.type == B43_PHYTYPE_A) {
3779 b43err(wl, "IEEE 802.11a devices are unsupported\n");
3783 dev->phy.gmode = have_2ghz_phy;
3784 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
3785 b43_wireless_core_reset(dev, tmp);
3787 err = b43_validate_chipaccess(dev);
3790 err = b43_setup_modes(dev, have_2ghz_phy, have_5ghz_phy);
3794 /* Now set some default "current_dev" */
3795 if (!wl->current_dev)
3796 wl->current_dev = dev;
3797 INIT_WORK(&dev->restart_work, b43_chip_reset);
3799 b43_radio_turn_off(dev, 1);
3800 b43_switch_analog(dev, 0);
3801 ssb_device_disable(dev->dev, 0);
3802 ssb_bus_may_powerdown(bus);
3808 ssb_bus_may_powerdown(bus);
3812 static void b43_one_core_detach(struct ssb_device *dev)
3814 struct b43_wldev *wldev;
3817 wldev = ssb_get_drvdata(dev);
3819 cancel_work_sync(&wldev->restart_work);
3820 b43_debugfs_remove_device(wldev);
3821 b43_wireless_core_detach(wldev);
3822 list_del(&wldev->list);
3824 ssb_set_drvdata(dev, NULL);
3828 static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
3830 struct b43_wldev *wldev;
3831 struct pci_dev *pdev;
3834 if (!list_empty(&wl->devlist)) {
3835 /* We are not the first core on this chip. */
3836 pdev = dev->bus->host_pci;
3837 /* Only special chips support more than one wireless
3838 * core, although some of the other chips have more than
3839 * one wireless core as well. Check for this and
3843 ((pdev->device != 0x4321) &&
3844 (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
3845 b43dbg(wl, "Ignoring unconnected 802.11 core\n");
3850 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
3856 b43_set_status(wldev, B43_STAT_UNINIT);
3857 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
3858 tasklet_init(&wldev->isr_tasklet,
3859 (void (*)(unsigned long))b43_interrupt_tasklet,
3860 (unsigned long)wldev);
3861 INIT_LIST_HEAD(&wldev->list);
3863 err = b43_wireless_core_attach(wldev);
3865 goto err_kfree_wldev;
3867 list_add(&wldev->list, &wl->devlist);
3869 ssb_set_drvdata(dev, wldev);
3870 b43_debugfs_add_device(wldev);
3880 static void b43_sprom_fixup(struct ssb_bus *bus)
3882 /* boardflags workarounds */
3883 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
3884 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
3885 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
3886 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3887 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
3888 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
3891 static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
3893 struct ieee80211_hw *hw = wl->hw;
3895 ssb_set_devtypedata(dev, NULL);
3896 ieee80211_free_hw(hw);
3899 static int b43_wireless_init(struct ssb_device *dev)
3901 struct ssb_sprom *sprom = &dev->bus->sprom;
3902 struct ieee80211_hw *hw;
3906 b43_sprom_fixup(dev->bus);
3908 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
3910 b43err(NULL, "Could not allocate ieee80211 device\n");
3915 hw->flags = IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
3916 IEEE80211_HW_RX_INCLUDES_FCS;
3917 hw->max_signal = 100;
3918 hw->max_rssi = -110;
3919 hw->max_noise = -110;
3920 hw->queues = 1; /* FIXME: hardware has more queues */
3921 SET_IEEE80211_DEV(hw, dev->dev);
3922 if (is_valid_ether_addr(sprom->et1mac))
3923 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
3925 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
3927 /* Get and initialize struct b43_wl */
3928 wl = hw_to_b43_wl(hw);
3929 memset(wl, 0, sizeof(*wl));
3931 spin_lock_init(&wl->irq_lock);
3932 spin_lock_init(&wl->leds_lock);
3933 mutex_init(&wl->mutex);
3934 INIT_LIST_HEAD(&wl->devlist);
3936 ssb_set_devtypedata(dev, wl);
3937 b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
3943 static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
3949 wl = ssb_get_devtypedata(dev);
3951 /* Probing the first core. Must setup common struct b43_wl */
3953 err = b43_wireless_init(dev);
3956 wl = ssb_get_devtypedata(dev);
3959 err = b43_one_core_attach(dev, wl);
3961 goto err_wireless_exit;
3964 err = ieee80211_register_hw(wl->hw);
3966 goto err_one_core_detach;
3972 err_one_core_detach:
3973 b43_one_core_detach(dev);
3976 b43_wireless_exit(dev, wl);
3980 static void b43_remove(struct ssb_device *dev)
3982 struct b43_wl *wl = ssb_get_devtypedata(dev);
3983 struct b43_wldev *wldev = ssb_get_drvdata(dev);
3986 if (wl->current_dev == wldev)
3987 ieee80211_unregister_hw(wl->hw);
3989 b43_one_core_detach(dev);
3991 if (list_empty(&wl->devlist)) {
3992 /* Last core on the chip unregistered.
3993 * We can destroy common struct b43_wl.
3995 b43_wireless_exit(dev, wl);
3999 /* Perform a hardware reset. This can be called from any context. */
4000 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
4002 /* Must avoid requeueing, if we are in shutdown. */
4003 if (b43_status(dev) < B43_STAT_INITIALIZED)
4005 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
4006 queue_work(dev->wl->hw->workqueue, &dev->restart_work);
4011 static int b43_suspend(struct ssb_device *dev, pm_message_t state)
4013 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4014 struct b43_wl *wl = wldev->wl;
4016 b43dbg(wl, "Suspending...\n");
4018 mutex_lock(&wl->mutex);
4019 wldev->suspend_init_status = b43_status(wldev);
4020 if (wldev->suspend_init_status >= B43_STAT_STARTED)
4021 b43_wireless_core_stop(wldev);
4022 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED)
4023 b43_wireless_core_exit(wldev);
4024 mutex_unlock(&wl->mutex);
4026 b43dbg(wl, "Device suspended.\n");
4031 static int b43_resume(struct ssb_device *dev)
4033 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4034 struct b43_wl *wl = wldev->wl;
4037 b43dbg(wl, "Resuming...\n");
4039 mutex_lock(&wl->mutex);
4040 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
4041 err = b43_wireless_core_init(wldev);
4043 b43err(wl, "Resume failed at core init\n");
4047 if (wldev->suspend_init_status >= B43_STAT_STARTED) {
4048 err = b43_wireless_core_start(wldev);
4050 b43_wireless_core_exit(wldev);
4051 b43err(wl, "Resume failed at core start\n");
4055 mutex_unlock(&wl->mutex);
4057 b43dbg(wl, "Device resumed.\n");
4062 #else /* CONFIG_PM */
4063 # define b43_suspend NULL
4064 # define b43_resume NULL
4065 #endif /* CONFIG_PM */
4067 static struct ssb_driver b43_ssb_driver = {
4068 .name = KBUILD_MODNAME,
4069 .id_table = b43_ssb_tbl,
4071 .remove = b43_remove,
4072 .suspend = b43_suspend,
4073 .resume = b43_resume,
4076 static int __init b43_init(void)
4081 err = b43_pcmcia_init();
4084 err = ssb_driver_register(&b43_ssb_driver);
4086 goto err_pcmcia_exit;
4097 static void __exit b43_exit(void)
4099 ssb_driver_unregister(&b43_ssb_driver);
4104 module_init(b43_init)
4105 module_exit(b43_exit)