3 Broadcom B43 wireless driver
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <stefano.brivio@polimi.it>
7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
31 #include <linux/delay.h>
32 #include <linux/init.h>
33 #include <linux/moduleparam.h>
34 #include <linux/if_arp.h>
35 #include <linux/etherdevice.h>
36 #include <linux/firmware.h>
37 #include <linux/wireless.h>
38 #include <linux/workqueue.h>
39 #include <linux/skbuff.h>
41 #include <linux/dma-mapping.h>
42 #include <asm/unaligned.h>
47 #include "phy_common.h"
57 MODULE_DESCRIPTION("Broadcom B43 wireless driver");
58 MODULE_AUTHOR("Martin Langer");
59 MODULE_AUTHOR("Stefano Brivio");
60 MODULE_AUTHOR("Michael Buesch");
61 MODULE_LICENSE("GPL");
63 MODULE_FIRMWARE(B43_SUPPORTED_FIRMWARE_ID);
66 static int modparam_bad_frames_preempt;
67 module_param_named(bad_frames_preempt, modparam_bad_frames_preempt, int, 0444);
68 MODULE_PARM_DESC(bad_frames_preempt,
69 "enable(1) / disable(0) Bad Frames Preemption");
71 static char modparam_fwpostfix[16];
72 module_param_string(fwpostfix, modparam_fwpostfix, 16, 0444);
73 MODULE_PARM_DESC(fwpostfix, "Postfix for the .fw files to load.");
75 static int modparam_hwpctl;
76 module_param_named(hwpctl, modparam_hwpctl, int, 0444);
77 MODULE_PARM_DESC(hwpctl, "Enable hardware-side power control (default off)");
79 static int modparam_nohwcrypt;
80 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
81 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
83 int b43_modparam_qos = 1;
84 module_param_named(qos, b43_modparam_qos, int, 0444);
85 MODULE_PARM_DESC(qos, "Enable QOS support (default on)");
87 static int modparam_btcoex = 1;
88 module_param_named(btcoex, modparam_btcoex, int, 0444);
89 MODULE_PARM_DESC(btcoex, "Enable Bluetooth coexistance (default on)");
92 static const struct ssb_device_id b43_ssb_tbl[] = {
93 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 5),
94 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 6),
95 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 7),
96 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 9),
97 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 10),
98 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 11),
99 SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_80211, 13),
103 MODULE_DEVICE_TABLE(ssb, b43_ssb_tbl);
105 /* Channel and ratetables are shared for all devices.
106 * They can't be const, because ieee80211 puts some precalculated
107 * data in there. This data is the same for all devices, so we don't
108 * get concurrency issues */
109 #define RATETAB_ENT(_rateid, _flags) \
111 .bitrate = B43_RATE_TO_BASE100KBPS(_rateid), \
112 .hw_value = (_rateid), \
117 * NOTE: When changing this, sync with xmit.c's
118 * b43_plcp_get_bitrate_idx_* functions!
120 static struct ieee80211_rate __b43_ratetable[] = {
121 RATETAB_ENT(B43_CCK_RATE_1MB, 0),
122 RATETAB_ENT(B43_CCK_RATE_2MB, IEEE80211_RATE_SHORT_PREAMBLE),
123 RATETAB_ENT(B43_CCK_RATE_5MB, IEEE80211_RATE_SHORT_PREAMBLE),
124 RATETAB_ENT(B43_CCK_RATE_11MB, IEEE80211_RATE_SHORT_PREAMBLE),
125 RATETAB_ENT(B43_OFDM_RATE_6MB, 0),
126 RATETAB_ENT(B43_OFDM_RATE_9MB, 0),
127 RATETAB_ENT(B43_OFDM_RATE_12MB, 0),
128 RATETAB_ENT(B43_OFDM_RATE_18MB, 0),
129 RATETAB_ENT(B43_OFDM_RATE_24MB, 0),
130 RATETAB_ENT(B43_OFDM_RATE_36MB, 0),
131 RATETAB_ENT(B43_OFDM_RATE_48MB, 0),
132 RATETAB_ENT(B43_OFDM_RATE_54MB, 0),
135 #define b43_a_ratetable (__b43_ratetable + 4)
136 #define b43_a_ratetable_size 8
137 #define b43_b_ratetable (__b43_ratetable + 0)
138 #define b43_b_ratetable_size 4
139 #define b43_g_ratetable (__b43_ratetable + 0)
140 #define b43_g_ratetable_size 12
142 #define CHAN4G(_channel, _freq, _flags) { \
143 .band = IEEE80211_BAND_2GHZ, \
144 .center_freq = (_freq), \
145 .hw_value = (_channel), \
147 .max_antenna_gain = 0, \
150 static struct ieee80211_channel b43_2ghz_chantable[] = {
168 #define CHAN5G(_channel, _flags) { \
169 .band = IEEE80211_BAND_5GHZ, \
170 .center_freq = 5000 + (5 * (_channel)), \
171 .hw_value = (_channel), \
173 .max_antenna_gain = 0, \
176 static struct ieee80211_channel b43_5ghz_nphy_chantable[] = {
177 CHAN5G(32, 0), CHAN5G(34, 0),
178 CHAN5G(36, 0), CHAN5G(38, 0),
179 CHAN5G(40, 0), CHAN5G(42, 0),
180 CHAN5G(44, 0), CHAN5G(46, 0),
181 CHAN5G(48, 0), CHAN5G(50, 0),
182 CHAN5G(52, 0), CHAN5G(54, 0),
183 CHAN5G(56, 0), CHAN5G(58, 0),
184 CHAN5G(60, 0), CHAN5G(62, 0),
185 CHAN5G(64, 0), CHAN5G(66, 0),
186 CHAN5G(68, 0), CHAN5G(70, 0),
187 CHAN5G(72, 0), CHAN5G(74, 0),
188 CHAN5G(76, 0), CHAN5G(78, 0),
189 CHAN5G(80, 0), CHAN5G(82, 0),
190 CHAN5G(84, 0), CHAN5G(86, 0),
191 CHAN5G(88, 0), CHAN5G(90, 0),
192 CHAN5G(92, 0), CHAN5G(94, 0),
193 CHAN5G(96, 0), CHAN5G(98, 0),
194 CHAN5G(100, 0), CHAN5G(102, 0),
195 CHAN5G(104, 0), CHAN5G(106, 0),
196 CHAN5G(108, 0), CHAN5G(110, 0),
197 CHAN5G(112, 0), CHAN5G(114, 0),
198 CHAN5G(116, 0), CHAN5G(118, 0),
199 CHAN5G(120, 0), CHAN5G(122, 0),
200 CHAN5G(124, 0), CHAN5G(126, 0),
201 CHAN5G(128, 0), CHAN5G(130, 0),
202 CHAN5G(132, 0), CHAN5G(134, 0),
203 CHAN5G(136, 0), CHAN5G(138, 0),
204 CHAN5G(140, 0), CHAN5G(142, 0),
205 CHAN5G(144, 0), CHAN5G(145, 0),
206 CHAN5G(146, 0), CHAN5G(147, 0),
207 CHAN5G(148, 0), CHAN5G(149, 0),
208 CHAN5G(150, 0), CHAN5G(151, 0),
209 CHAN5G(152, 0), CHAN5G(153, 0),
210 CHAN5G(154, 0), CHAN5G(155, 0),
211 CHAN5G(156, 0), CHAN5G(157, 0),
212 CHAN5G(158, 0), CHAN5G(159, 0),
213 CHAN5G(160, 0), CHAN5G(161, 0),
214 CHAN5G(162, 0), CHAN5G(163, 0),
215 CHAN5G(164, 0), CHAN5G(165, 0),
216 CHAN5G(166, 0), CHAN5G(168, 0),
217 CHAN5G(170, 0), CHAN5G(172, 0),
218 CHAN5G(174, 0), CHAN5G(176, 0),
219 CHAN5G(178, 0), CHAN5G(180, 0),
220 CHAN5G(182, 0), CHAN5G(184, 0),
221 CHAN5G(186, 0), CHAN5G(188, 0),
222 CHAN5G(190, 0), CHAN5G(192, 0),
223 CHAN5G(194, 0), CHAN5G(196, 0),
224 CHAN5G(198, 0), CHAN5G(200, 0),
225 CHAN5G(202, 0), CHAN5G(204, 0),
226 CHAN5G(206, 0), CHAN5G(208, 0),
227 CHAN5G(210, 0), CHAN5G(212, 0),
228 CHAN5G(214, 0), CHAN5G(216, 0),
229 CHAN5G(218, 0), CHAN5G(220, 0),
230 CHAN5G(222, 0), CHAN5G(224, 0),
231 CHAN5G(226, 0), CHAN5G(228, 0),
234 static struct ieee80211_channel b43_5ghz_aphy_chantable[] = {
235 CHAN5G(34, 0), CHAN5G(36, 0),
236 CHAN5G(38, 0), CHAN5G(40, 0),
237 CHAN5G(42, 0), CHAN5G(44, 0),
238 CHAN5G(46, 0), CHAN5G(48, 0),
239 CHAN5G(52, 0), CHAN5G(56, 0),
240 CHAN5G(60, 0), CHAN5G(64, 0),
241 CHAN5G(100, 0), CHAN5G(104, 0),
242 CHAN5G(108, 0), CHAN5G(112, 0),
243 CHAN5G(116, 0), CHAN5G(120, 0),
244 CHAN5G(124, 0), CHAN5G(128, 0),
245 CHAN5G(132, 0), CHAN5G(136, 0),
246 CHAN5G(140, 0), CHAN5G(149, 0),
247 CHAN5G(153, 0), CHAN5G(157, 0),
248 CHAN5G(161, 0), CHAN5G(165, 0),
249 CHAN5G(184, 0), CHAN5G(188, 0),
250 CHAN5G(192, 0), CHAN5G(196, 0),
251 CHAN5G(200, 0), CHAN5G(204, 0),
252 CHAN5G(208, 0), CHAN5G(212, 0),
257 static struct ieee80211_supported_band b43_band_5GHz_nphy = {
258 .band = IEEE80211_BAND_5GHZ,
259 .channels = b43_5ghz_nphy_chantable,
260 .n_channels = ARRAY_SIZE(b43_5ghz_nphy_chantable),
261 .bitrates = b43_a_ratetable,
262 .n_bitrates = b43_a_ratetable_size,
265 static struct ieee80211_supported_band b43_band_5GHz_aphy = {
266 .band = IEEE80211_BAND_5GHZ,
267 .channels = b43_5ghz_aphy_chantable,
268 .n_channels = ARRAY_SIZE(b43_5ghz_aphy_chantable),
269 .bitrates = b43_a_ratetable,
270 .n_bitrates = b43_a_ratetable_size,
273 static struct ieee80211_supported_band b43_band_2GHz = {
274 .band = IEEE80211_BAND_2GHZ,
275 .channels = b43_2ghz_chantable,
276 .n_channels = ARRAY_SIZE(b43_2ghz_chantable),
277 .bitrates = b43_g_ratetable,
278 .n_bitrates = b43_g_ratetable_size,
281 static void b43_wireless_core_exit(struct b43_wldev *dev);
282 static int b43_wireless_core_init(struct b43_wldev *dev);
283 static void b43_wireless_core_stop(struct b43_wldev *dev);
284 static int b43_wireless_core_start(struct b43_wldev *dev);
286 static int b43_ratelimit(struct b43_wl *wl)
288 if (!wl || !wl->current_dev)
290 if (b43_status(wl->current_dev) < B43_STAT_STARTED)
292 /* We are up and running.
293 * Ratelimit the messages to avoid DoS over the net. */
294 return net_ratelimit();
297 void b43info(struct b43_wl *wl, const char *fmt, ...)
301 if (!b43_ratelimit(wl))
304 printk(KERN_INFO "b43-%s: ",
305 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
310 void b43err(struct b43_wl *wl, const char *fmt, ...)
314 if (!b43_ratelimit(wl))
317 printk(KERN_ERR "b43-%s ERROR: ",
318 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
323 void b43warn(struct b43_wl *wl, const char *fmt, ...)
327 if (!b43_ratelimit(wl))
330 printk(KERN_WARNING "b43-%s warning: ",
331 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
337 void b43dbg(struct b43_wl *wl, const char *fmt, ...)
342 printk(KERN_DEBUG "b43-%s debug: ",
343 (wl && wl->hw) ? wiphy_name(wl->hw->wiphy) : "wlan");
349 static void b43_ram_write(struct b43_wldev *dev, u16 offset, u32 val)
353 B43_WARN_ON(offset % 4 != 0);
355 macctl = b43_read32(dev, B43_MMIO_MACCTL);
356 if (macctl & B43_MACCTL_BE)
359 b43_write32(dev, B43_MMIO_RAM_CONTROL, offset);
361 b43_write32(dev, B43_MMIO_RAM_DATA, val);
364 static inline void b43_shm_control_word(struct b43_wldev *dev,
365 u16 routing, u16 offset)
369 /* "offset" is the WORD offset. */
373 b43_write32(dev, B43_MMIO_SHM_CONTROL, control);
376 u32 __b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
380 if (routing == B43_SHM_SHARED) {
381 B43_WARN_ON(offset & 0x0001);
382 if (offset & 0x0003) {
383 /* Unaligned access */
384 b43_shm_control_word(dev, routing, offset >> 2);
385 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
387 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
388 ret |= b43_read16(dev, B43_MMIO_SHM_DATA);
394 b43_shm_control_word(dev, routing, offset);
395 ret = b43_read32(dev, B43_MMIO_SHM_DATA);
400 u32 b43_shm_read32(struct b43_wldev *dev, u16 routing, u16 offset)
402 struct b43_wl *wl = dev->wl;
406 spin_lock_irqsave(&wl->shm_lock, flags);
407 ret = __b43_shm_read32(dev, routing, offset);
408 spin_unlock_irqrestore(&wl->shm_lock, flags);
413 u16 __b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
417 if (routing == B43_SHM_SHARED) {
418 B43_WARN_ON(offset & 0x0001);
419 if (offset & 0x0003) {
420 /* Unaligned access */
421 b43_shm_control_word(dev, routing, offset >> 2);
422 ret = b43_read16(dev, B43_MMIO_SHM_DATA_UNALIGNED);
428 b43_shm_control_word(dev, routing, offset);
429 ret = b43_read16(dev, B43_MMIO_SHM_DATA);
434 u16 b43_shm_read16(struct b43_wldev *dev, u16 routing, u16 offset)
436 struct b43_wl *wl = dev->wl;
440 spin_lock_irqsave(&wl->shm_lock, flags);
441 ret = __b43_shm_read16(dev, routing, offset);
442 spin_unlock_irqrestore(&wl->shm_lock, flags);
447 void __b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
449 if (routing == B43_SHM_SHARED) {
450 B43_WARN_ON(offset & 0x0001);
451 if (offset & 0x0003) {
452 /* Unaligned access */
453 b43_shm_control_word(dev, routing, offset >> 2);
454 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED,
455 (value >> 16) & 0xffff);
456 b43_shm_control_word(dev, routing, (offset >> 2) + 1);
457 b43_write16(dev, B43_MMIO_SHM_DATA, value & 0xffff);
462 b43_shm_control_word(dev, routing, offset);
463 b43_write32(dev, B43_MMIO_SHM_DATA, value);
466 void b43_shm_write32(struct b43_wldev *dev, u16 routing, u16 offset, u32 value)
468 struct b43_wl *wl = dev->wl;
471 spin_lock_irqsave(&wl->shm_lock, flags);
472 __b43_shm_write32(dev, routing, offset, value);
473 spin_unlock_irqrestore(&wl->shm_lock, flags);
476 void __b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
478 if (routing == B43_SHM_SHARED) {
479 B43_WARN_ON(offset & 0x0001);
480 if (offset & 0x0003) {
481 /* Unaligned access */
482 b43_shm_control_word(dev, routing, offset >> 2);
483 b43_write16(dev, B43_MMIO_SHM_DATA_UNALIGNED, value);
488 b43_shm_control_word(dev, routing, offset);
489 b43_write16(dev, B43_MMIO_SHM_DATA, value);
492 void b43_shm_write16(struct b43_wldev *dev, u16 routing, u16 offset, u16 value)
494 struct b43_wl *wl = dev->wl;
497 spin_lock_irqsave(&wl->shm_lock, flags);
498 __b43_shm_write16(dev, routing, offset, value);
499 spin_unlock_irqrestore(&wl->shm_lock, flags);
503 u64 b43_hf_read(struct b43_wldev * dev)
507 ret = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI);
509 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI);
511 ret |= b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO);
516 /* Write HostFlags */
517 void b43_hf_write(struct b43_wldev *dev, u64 value)
521 lo = (value & 0x00000000FFFFULL);
522 mi = (value & 0x0000FFFF0000ULL) >> 16;
523 hi = (value & 0xFFFF00000000ULL) >> 32;
524 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFLO, lo);
525 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFMI, mi);
526 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_HOSTFHI, hi);
529 void b43_tsf_read(struct b43_wldev *dev, u64 * tsf)
531 /* We need to be careful. As we read the TSF from multiple
532 * registers, we should take care of register overflows.
533 * In theory, the whole tsf read process should be atomic.
534 * We try to be atomic here, by restaring the read process,
535 * if any of the high registers changed (overflew).
537 if (dev->dev->id.revision >= 3) {
538 u32 low, high, high2;
541 high = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
542 low = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_LOW);
543 high2 = b43_read32(dev, B43_MMIO_REV3PLUS_TSF_HIGH);
544 } while (unlikely(high != high2));
552 u16 test1, test2, test3;
555 v3 = b43_read16(dev, B43_MMIO_TSF_3);
556 v2 = b43_read16(dev, B43_MMIO_TSF_2);
557 v1 = b43_read16(dev, B43_MMIO_TSF_1);
558 v0 = b43_read16(dev, B43_MMIO_TSF_0);
560 test3 = b43_read16(dev, B43_MMIO_TSF_3);
561 test2 = b43_read16(dev, B43_MMIO_TSF_2);
562 test1 = b43_read16(dev, B43_MMIO_TSF_1);
563 } while (v3 != test3 || v2 != test2 || v1 != test1);
577 static void b43_time_lock(struct b43_wldev *dev)
581 macctl = b43_read32(dev, B43_MMIO_MACCTL);
582 macctl |= B43_MACCTL_TBTTHOLD;
583 b43_write32(dev, B43_MMIO_MACCTL, macctl);
584 /* Commit the write */
585 b43_read32(dev, B43_MMIO_MACCTL);
588 static void b43_time_unlock(struct b43_wldev *dev)
592 macctl = b43_read32(dev, B43_MMIO_MACCTL);
593 macctl &= ~B43_MACCTL_TBTTHOLD;
594 b43_write32(dev, B43_MMIO_MACCTL, macctl);
595 /* Commit the write */
596 b43_read32(dev, B43_MMIO_MACCTL);
599 static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
601 /* Be careful with the in-progress timer.
602 * First zero out the low register, so we have a full
603 * register-overflow duration to complete the operation.
605 if (dev->dev->id.revision >= 3) {
606 u32 lo = (tsf & 0x00000000FFFFFFFFULL);
607 u32 hi = (tsf & 0xFFFFFFFF00000000ULL) >> 32;
609 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, 0);
611 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_HIGH, hi);
613 b43_write32(dev, B43_MMIO_REV3PLUS_TSF_LOW, lo);
615 u16 v0 = (tsf & 0x000000000000FFFFULL);
616 u16 v1 = (tsf & 0x00000000FFFF0000ULL) >> 16;
617 u16 v2 = (tsf & 0x0000FFFF00000000ULL) >> 32;
618 u16 v3 = (tsf & 0xFFFF000000000000ULL) >> 48;
620 b43_write16(dev, B43_MMIO_TSF_0, 0);
622 b43_write16(dev, B43_MMIO_TSF_3, v3);
624 b43_write16(dev, B43_MMIO_TSF_2, v2);
626 b43_write16(dev, B43_MMIO_TSF_1, v1);
628 b43_write16(dev, B43_MMIO_TSF_0, v0);
632 void b43_tsf_write(struct b43_wldev *dev, u64 tsf)
635 b43_tsf_write_locked(dev, tsf);
636 b43_time_unlock(dev);
640 void b43_macfilter_set(struct b43_wldev *dev, u16 offset, const u8 * mac)
642 static const u8 zero_addr[ETH_ALEN] = { 0 };
649 b43_write16(dev, B43_MMIO_MACFILTER_CONTROL, offset);
653 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
656 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
659 b43_write16(dev, B43_MMIO_MACFILTER_DATA, data);
662 static void b43_write_mac_bssid_templates(struct b43_wldev *dev)
666 u8 mac_bssid[ETH_ALEN * 2];
670 bssid = dev->wl->bssid;
671 mac = dev->wl->mac_addr;
673 b43_macfilter_set(dev, B43_MACFILTER_BSSID, bssid);
675 memcpy(mac_bssid, mac, ETH_ALEN);
676 memcpy(mac_bssid + ETH_ALEN, bssid, ETH_ALEN);
678 /* Write our MAC address and BSSID to template ram */
679 for (i = 0; i < ARRAY_SIZE(mac_bssid); i += sizeof(u32)) {
680 tmp = (u32) (mac_bssid[i + 0]);
681 tmp |= (u32) (mac_bssid[i + 1]) << 8;
682 tmp |= (u32) (mac_bssid[i + 2]) << 16;
683 tmp |= (u32) (mac_bssid[i + 3]) << 24;
684 b43_ram_write(dev, 0x20 + i, tmp);
688 static void b43_upload_card_macaddress(struct b43_wldev *dev)
690 b43_write_mac_bssid_templates(dev);
691 b43_macfilter_set(dev, B43_MACFILTER_SELF, dev->wl->mac_addr);
694 static void b43_set_slot_time(struct b43_wldev *dev, u16 slot_time)
696 /* slot_time is in usec. */
697 if (dev->phy.type != B43_PHYTYPE_G)
699 b43_write16(dev, 0x684, 510 + slot_time);
700 b43_shm_write16(dev, B43_SHM_SHARED, 0x0010, slot_time);
703 static void b43_short_slot_timing_enable(struct b43_wldev *dev)
705 b43_set_slot_time(dev, 9);
708 static void b43_short_slot_timing_disable(struct b43_wldev *dev)
710 b43_set_slot_time(dev, 20);
713 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
714 * Returns the _previously_ enabled IRQ mask.
716 static inline u32 b43_interrupt_enable(struct b43_wldev *dev, u32 mask)
720 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
721 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask | mask);
726 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
727 * Returns the _previously_ enabled IRQ mask.
729 static inline u32 b43_interrupt_disable(struct b43_wldev *dev, u32 mask)
733 old_mask = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
734 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK, old_mask & ~mask);
739 /* Synchronize IRQ top- and bottom-half.
740 * IRQs must be masked before calling this.
741 * This must not be called with the irq_lock held.
743 static void b43_synchronize_irq(struct b43_wldev *dev)
745 synchronize_irq(dev->dev->irq);
746 tasklet_kill(&dev->isr_tasklet);
749 /* DummyTransmission function, as documented on
750 * http://bcm-specs.sipsolutions.net/DummyTransmission
752 void b43_dummy_transmission(struct b43_wldev *dev)
754 struct b43_wl *wl = dev->wl;
755 struct b43_phy *phy = &dev->phy;
756 unsigned int i, max_loop;
769 buffer[0] = 0x000201CC;
774 buffer[0] = 0x000B846E;
781 spin_lock_irq(&wl->irq_lock);
782 write_lock(&wl->tx_lock);
784 for (i = 0; i < 5; i++)
785 b43_ram_write(dev, i * 4, buffer[i]);
788 b43_read32(dev, B43_MMIO_MACCTL);
790 b43_write16(dev, 0x0568, 0x0000);
791 b43_write16(dev, 0x07C0, 0x0000);
792 value = ((phy->type == B43_PHYTYPE_A) ? 1 : 0);
793 b43_write16(dev, 0x050C, value);
794 b43_write16(dev, 0x0508, 0x0000);
795 b43_write16(dev, 0x050A, 0x0000);
796 b43_write16(dev, 0x054C, 0x0000);
797 b43_write16(dev, 0x056A, 0x0014);
798 b43_write16(dev, 0x0568, 0x0826);
799 b43_write16(dev, 0x0500, 0x0000);
800 b43_write16(dev, 0x0502, 0x0030);
802 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
803 b43_radio_write16(dev, 0x0051, 0x0017);
804 for (i = 0x00; i < max_loop; i++) {
805 value = b43_read16(dev, 0x050E);
810 for (i = 0x00; i < 0x0A; i++) {
811 value = b43_read16(dev, 0x050E);
816 for (i = 0x00; i < 0x19; i++) {
817 value = b43_read16(dev, 0x0690);
818 if (!(value & 0x0100))
822 if (phy->radio_ver == 0x2050 && phy->radio_rev <= 0x5)
823 b43_radio_write16(dev, 0x0051, 0x0037);
825 write_unlock(&wl->tx_lock);
826 spin_unlock_irq(&wl->irq_lock);
829 static void key_write(struct b43_wldev *dev,
830 u8 index, u8 algorithm, const u8 * key)
837 /* Key index/algo block */
838 kidx = b43_kidx_to_fw(dev, index);
839 value = ((kidx << 4) | algorithm);
840 b43_shm_write16(dev, B43_SHM_SHARED,
841 B43_SHM_SH_KEYIDXBLOCK + (kidx * 2), value);
843 /* Write the key to the Key Table Pointer offset */
844 offset = dev->ktp + (index * B43_SEC_KEYSIZE);
845 for (i = 0; i < B43_SEC_KEYSIZE; i += 2) {
847 value |= (u16) (key[i + 1]) << 8;
848 b43_shm_write16(dev, B43_SHM_SHARED, offset + i, value);
852 static void keymac_write(struct b43_wldev *dev, u8 index, const u8 * addr)
854 u32 addrtmp[2] = { 0, 0, };
855 u8 per_sta_keys_start = 8;
857 if (b43_new_kidx_api(dev))
858 per_sta_keys_start = 4;
860 B43_WARN_ON(index < per_sta_keys_start);
861 /* We have two default TX keys and possibly two default RX keys.
862 * Physical mac 0 is mapped to physical key 4 or 8, depending
863 * on the firmware version.
864 * So we must adjust the index here.
866 index -= per_sta_keys_start;
869 addrtmp[0] = addr[0];
870 addrtmp[0] |= ((u32) (addr[1]) << 8);
871 addrtmp[0] |= ((u32) (addr[2]) << 16);
872 addrtmp[0] |= ((u32) (addr[3]) << 24);
873 addrtmp[1] = addr[4];
874 addrtmp[1] |= ((u32) (addr[5]) << 8);
877 if (dev->dev->id.revision >= 5) {
878 /* Receive match transmitter address mechanism */
879 b43_shm_write32(dev, B43_SHM_RCMTA,
880 (index * 2) + 0, addrtmp[0]);
881 b43_shm_write16(dev, B43_SHM_RCMTA,
882 (index * 2) + 1, addrtmp[1]);
884 /* RXE (Receive Engine) and
885 * PSM (Programmable State Machine) mechanism
888 /* TODO write to RCM 16, 19, 22 and 25 */
890 b43_shm_write32(dev, B43_SHM_SHARED,
891 B43_SHM_SH_PSM + (index * 6) + 0,
893 b43_shm_write16(dev, B43_SHM_SHARED,
894 B43_SHM_SH_PSM + (index * 6) + 4,
900 static void do_key_write(struct b43_wldev *dev,
901 u8 index, u8 algorithm,
902 const u8 * key, size_t key_len, const u8 * mac_addr)
904 u8 buf[B43_SEC_KEYSIZE] = { 0, };
905 u8 per_sta_keys_start = 8;
907 if (b43_new_kidx_api(dev))
908 per_sta_keys_start = 4;
910 B43_WARN_ON(index >= dev->max_nr_keys);
911 B43_WARN_ON(key_len > B43_SEC_KEYSIZE);
913 if (index >= per_sta_keys_start)
914 keymac_write(dev, index, NULL); /* First zero out mac. */
916 memcpy(buf, key, key_len);
917 key_write(dev, index, algorithm, buf);
918 if (index >= per_sta_keys_start)
919 keymac_write(dev, index, mac_addr);
921 dev->key[index].algorithm = algorithm;
924 static int b43_key_write(struct b43_wldev *dev,
925 int index, u8 algorithm,
926 const u8 * key, size_t key_len,
928 struct ieee80211_key_conf *keyconf)
933 if (key_len > B43_SEC_KEYSIZE)
935 for (i = 0; i < dev->max_nr_keys; i++) {
936 /* Check that we don't already have this key. */
937 B43_WARN_ON(dev->key[i].keyconf == keyconf);
940 /* Either pairwise key or address is 00:00:00:00:00:00
941 * for transmit-only keys. Search the index. */
942 if (b43_new_kidx_api(dev))
946 for (i = sta_keys_start; i < dev->max_nr_keys; i++) {
947 if (!dev->key[i].keyconf) {
954 b43err(dev->wl, "Out of hardware key memory\n");
958 B43_WARN_ON(index > 3);
960 do_key_write(dev, index, algorithm, key, key_len, mac_addr);
961 if ((index <= 3) && !b43_new_kidx_api(dev)) {
963 B43_WARN_ON(mac_addr);
964 do_key_write(dev, index + 4, algorithm, key, key_len, NULL);
966 keyconf->hw_key_idx = index;
967 dev->key[index].keyconf = keyconf;
972 static int b43_key_clear(struct b43_wldev *dev, int index)
974 if (B43_WARN_ON((index < 0) || (index >= dev->max_nr_keys)))
976 do_key_write(dev, index, B43_SEC_ALGO_NONE,
977 NULL, B43_SEC_KEYSIZE, NULL);
978 if ((index <= 3) && !b43_new_kidx_api(dev)) {
979 do_key_write(dev, index + 4, B43_SEC_ALGO_NONE,
980 NULL, B43_SEC_KEYSIZE, NULL);
982 dev->key[index].keyconf = NULL;
987 static void b43_clear_keys(struct b43_wldev *dev)
991 for (i = 0; i < dev->max_nr_keys; i++)
992 b43_key_clear(dev, i);
995 void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
1003 B43_WARN_ON((ps_flags & B43_PS_ENABLED) &&
1004 (ps_flags & B43_PS_DISABLED));
1005 B43_WARN_ON((ps_flags & B43_PS_AWAKE) && (ps_flags & B43_PS_ASLEEP));
1007 if (ps_flags & B43_PS_ENABLED) {
1009 } else if (ps_flags & B43_PS_DISABLED) {
1012 //TODO: If powersave is not off and FIXME is not set and we are not in adhoc
1013 // and thus is not an AP and we are associated, set bit 25
1015 if (ps_flags & B43_PS_AWAKE) {
1017 } else if (ps_flags & B43_PS_ASLEEP) {
1020 //TODO: If the device is awake or this is an AP, or we are scanning, or FIXME,
1021 // or we are associated, or FIXME, or the latest PS-Poll packet sent was
1022 // successful, set bit26
1025 /* FIXME: For now we force awake-on and hwps-off */
1029 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1031 macctl |= B43_MACCTL_HWPS;
1033 macctl &= ~B43_MACCTL_HWPS;
1035 macctl |= B43_MACCTL_AWAKE;
1037 macctl &= ~B43_MACCTL_AWAKE;
1038 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1040 b43_read32(dev, B43_MMIO_MACCTL);
1041 if (awake && dev->dev->id.revision >= 5) {
1042 /* Wait for the microcode to wake up. */
1043 for (i = 0; i < 100; i++) {
1044 ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
1045 B43_SHM_SH_UCODESTAT);
1046 if (ucstat != B43_SHM_SH_UCODESTAT_SLEEP)
1053 void b43_wireless_core_reset(struct b43_wldev *dev, u32 flags)
1058 flags |= B43_TMSLOW_PHYCLKEN;
1059 flags |= B43_TMSLOW_PHYRESET;
1060 ssb_device_enable(dev->dev, flags);
1061 msleep(2); /* Wait for the PLL to turn on. */
1063 /* Now take the PHY out of Reset again */
1064 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
1065 tmslow |= SSB_TMSLOW_FGC;
1066 tmslow &= ~B43_TMSLOW_PHYRESET;
1067 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1068 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1070 tmslow &= ~SSB_TMSLOW_FGC;
1071 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
1072 ssb_read32(dev->dev, SSB_TMSLOW); /* flush */
1075 /* Turn Analog ON, but only if we already know the PHY-type.
1076 * This protects against very early setup where we don't know the
1077 * PHY-type, yet. wireless_core_reset will be called once again later,
1078 * when we know the PHY-type. */
1080 dev->phy.ops->switch_analog(dev, 1);
1082 macctl = b43_read32(dev, B43_MMIO_MACCTL);
1083 macctl &= ~B43_MACCTL_GMODE;
1084 if (flags & B43_TMSLOW_GMODE)
1085 macctl |= B43_MACCTL_GMODE;
1086 macctl |= B43_MACCTL_IHR_ENABLED;
1087 b43_write32(dev, B43_MMIO_MACCTL, macctl);
1090 static void handle_irq_transmit_status(struct b43_wldev *dev)
1094 struct b43_txstatus stat;
1097 v0 = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1098 if (!(v0 & 0x00000001))
1100 v1 = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1102 stat.cookie = (v0 >> 16);
1103 stat.seq = (v1 & 0x0000FFFF);
1104 stat.phy_stat = ((v1 & 0x00FF0000) >> 16);
1105 tmp = (v0 & 0x0000FFFF);
1106 stat.frame_count = ((tmp & 0xF000) >> 12);
1107 stat.rts_count = ((tmp & 0x0F00) >> 8);
1108 stat.supp_reason = ((tmp & 0x001C) >> 2);
1109 stat.pm_indicated = !!(tmp & 0x0080);
1110 stat.intermediate = !!(tmp & 0x0040);
1111 stat.for_ampdu = !!(tmp & 0x0020);
1112 stat.acked = !!(tmp & 0x0002);
1114 b43_handle_txstatus(dev, &stat);
1118 static void drain_txstatus_queue(struct b43_wldev *dev)
1122 if (dev->dev->id.revision < 5)
1124 /* Read all entries from the microcode TXstatus FIFO
1125 * and throw them away.
1128 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_0);
1129 if (!(dummy & 0x00000001))
1131 dummy = b43_read32(dev, B43_MMIO_XMITSTAT_1);
1135 static u32 b43_jssi_read(struct b43_wldev *dev)
1139 val = b43_shm_read16(dev, B43_SHM_SHARED, 0x08A);
1141 val |= b43_shm_read16(dev, B43_SHM_SHARED, 0x088);
1146 static void b43_jssi_write(struct b43_wldev *dev, u32 jssi)
1148 b43_shm_write16(dev, B43_SHM_SHARED, 0x088, (jssi & 0x0000FFFF));
1149 b43_shm_write16(dev, B43_SHM_SHARED, 0x08A, (jssi & 0xFFFF0000) >> 16);
1152 static void b43_generate_noise_sample(struct b43_wldev *dev)
1154 b43_jssi_write(dev, 0x7F7F7F7F);
1155 b43_write32(dev, B43_MMIO_MACCMD,
1156 b43_read32(dev, B43_MMIO_MACCMD) | B43_MACCMD_BGNOISE);
1159 static void b43_calculate_link_quality(struct b43_wldev *dev)
1161 /* Top half of Link Quality calculation. */
1163 if (dev->phy.type != B43_PHYTYPE_G)
1165 if (dev->noisecalc.calculation_running)
1167 dev->noisecalc.calculation_running = 1;
1168 dev->noisecalc.nr_samples = 0;
1170 b43_generate_noise_sample(dev);
1173 static void handle_irq_noise(struct b43_wldev *dev)
1175 struct b43_phy_g *phy = dev->phy.g;
1181 /* Bottom half of Link Quality calculation. */
1183 if (dev->phy.type != B43_PHYTYPE_G)
1186 /* Possible race condition: It might be possible that the user
1187 * changed to a different channel in the meantime since we
1188 * started the calculation. We ignore that fact, since it's
1189 * not really that much of a problem. The background noise is
1190 * an estimation only anyway. Slightly wrong results will get damped
1191 * by the averaging of the 8 sample rounds. Additionally the
1192 * value is shortlived. So it will be replaced by the next noise
1193 * calculation round soon. */
1195 B43_WARN_ON(!dev->noisecalc.calculation_running);
1196 *((__le32 *)noise) = cpu_to_le32(b43_jssi_read(dev));
1197 if (noise[0] == 0x7F || noise[1] == 0x7F ||
1198 noise[2] == 0x7F || noise[3] == 0x7F)
1201 /* Get the noise samples. */
1202 B43_WARN_ON(dev->noisecalc.nr_samples >= 8);
1203 i = dev->noisecalc.nr_samples;
1204 noise[0] = clamp_val(noise[0], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1205 noise[1] = clamp_val(noise[1], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1206 noise[2] = clamp_val(noise[2], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1207 noise[3] = clamp_val(noise[3], 0, ARRAY_SIZE(phy->nrssi_lt) - 1);
1208 dev->noisecalc.samples[i][0] = phy->nrssi_lt[noise[0]];
1209 dev->noisecalc.samples[i][1] = phy->nrssi_lt[noise[1]];
1210 dev->noisecalc.samples[i][2] = phy->nrssi_lt[noise[2]];
1211 dev->noisecalc.samples[i][3] = phy->nrssi_lt[noise[3]];
1212 dev->noisecalc.nr_samples++;
1213 if (dev->noisecalc.nr_samples == 8) {
1214 /* Calculate the Link Quality by the noise samples. */
1216 for (i = 0; i < 8; i++) {
1217 for (j = 0; j < 4; j++)
1218 average += dev->noisecalc.samples[i][j];
1224 tmp = b43_shm_read16(dev, B43_SHM_SHARED, 0x40C);
1225 tmp = (tmp / 128) & 0x1F;
1235 dev->stats.link_noise = average;
1236 dev->noisecalc.calculation_running = 0;
1240 b43_generate_noise_sample(dev);
1243 static void handle_irq_tbtt_indication(struct b43_wldev *dev)
1245 if (b43_is_mode(dev->wl, NL80211_IFTYPE_AP)) {
1248 if (1 /*FIXME: the last PSpoll frame was sent successfully */ )
1249 b43_power_saving_ctl_bits(dev, 0);
1251 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC))
1255 static void handle_irq_atim_end(struct b43_wldev *dev)
1257 if (dev->dfq_valid) {
1258 b43_write32(dev, B43_MMIO_MACCMD,
1259 b43_read32(dev, B43_MMIO_MACCMD)
1260 | B43_MACCMD_DFQ_VALID);
1265 static void handle_irq_pmq(struct b43_wldev *dev)
1272 tmp = b43_read32(dev, B43_MMIO_PS_STATUS);
1273 if (!(tmp & 0x00000008))
1276 /* 16bit write is odd, but correct. */
1277 b43_write16(dev, B43_MMIO_PS_STATUS, 0x0002);
1280 static void b43_write_template_common(struct b43_wldev *dev,
1281 const u8 * data, u16 size,
1283 u16 shm_size_offset, u8 rate)
1286 struct b43_plcp_hdr4 plcp;
1289 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate);
1290 b43_ram_write(dev, ram_offset, le32_to_cpu(plcp.data));
1291 ram_offset += sizeof(u32);
1292 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1293 * So leave the first two bytes of the next write blank.
1295 tmp = (u32) (data[0]) << 16;
1296 tmp |= (u32) (data[1]) << 24;
1297 b43_ram_write(dev, ram_offset, tmp);
1298 ram_offset += sizeof(u32);
1299 for (i = 2; i < size; i += sizeof(u32)) {
1300 tmp = (u32) (data[i + 0]);
1302 tmp |= (u32) (data[i + 1]) << 8;
1304 tmp |= (u32) (data[i + 2]) << 16;
1306 tmp |= (u32) (data[i + 3]) << 24;
1307 b43_ram_write(dev, ram_offset + i - 2, tmp);
1309 b43_shm_write16(dev, B43_SHM_SHARED, shm_size_offset,
1310 size + sizeof(struct b43_plcp_hdr6));
1313 /* Check if the use of the antenna that ieee80211 told us to
1314 * use is possible. This will fall back to DEFAULT.
1315 * "antenna_nr" is the antenna identifier we got from ieee80211. */
1316 u8 b43_ieee80211_antenna_sanitize(struct b43_wldev *dev,
1321 if (antenna_nr == 0) {
1322 /* Zero means "use default antenna". That's always OK. */
1326 /* Get the mask of available antennas. */
1328 antenna_mask = dev->dev->bus->sprom.ant_available_bg;
1330 antenna_mask = dev->dev->bus->sprom.ant_available_a;
1332 if (!(antenna_mask & (1 << (antenna_nr - 1)))) {
1333 /* This antenna is not available. Fall back to default. */
1340 /* Convert a b43 antenna number value to the PHY TX control value. */
1341 static u16 b43_antenna_to_phyctl(int antenna)
1345 return B43_TXH_PHY_ANT0;
1347 return B43_TXH_PHY_ANT1;
1349 return B43_TXH_PHY_ANT2;
1351 return B43_TXH_PHY_ANT3;
1352 case B43_ANTENNA_AUTO:
1353 return B43_TXH_PHY_ANT01AUTO;
1359 static void b43_write_beacon_template(struct b43_wldev *dev,
1361 u16 shm_size_offset)
1363 unsigned int i, len, variable_len;
1364 const struct ieee80211_mgmt *bcn;
1370 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(dev->wl->current_beacon);
1372 bcn = (const struct ieee80211_mgmt *)(dev->wl->current_beacon->data);
1373 len = min((size_t) dev->wl->current_beacon->len,
1374 0x200 - sizeof(struct b43_plcp_hdr6));
1375 rate = ieee80211_get_tx_rate(dev->wl->hw, info)->hw_value;
1377 b43_write_template_common(dev, (const u8 *)bcn,
1378 len, ram_offset, shm_size_offset, rate);
1380 /* Write the PHY TX control parameters. */
1381 antenna = B43_ANTENNA_DEFAULT;
1382 antenna = b43_antenna_to_phyctl(antenna);
1383 ctl = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL);
1384 /* We can't send beacons with short preamble. Would get PHY errors. */
1385 ctl &= ~B43_TXH_PHY_SHORTPRMBL;
1386 ctl &= ~B43_TXH_PHY_ANT;
1387 ctl &= ~B43_TXH_PHY_ENC;
1389 if (b43_is_cck_rate(rate))
1390 ctl |= B43_TXH_PHY_ENC_CCK;
1392 ctl |= B43_TXH_PHY_ENC_OFDM;
1393 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
1395 /* Find the position of the TIM and the DTIM_period value
1396 * and write them to SHM. */
1397 ie = bcn->u.beacon.variable;
1398 variable_len = len - offsetof(struct ieee80211_mgmt, u.beacon.variable);
1399 for (i = 0; i < variable_len - 2; ) {
1400 uint8_t ie_id, ie_len;
1407 /* This is the TIM Information Element */
1409 /* Check whether the ie_len is in the beacon data range. */
1410 if (variable_len < ie_len + 2 + i)
1412 /* A valid TIM is at least 4 bytes long. */
1417 tim_position = sizeof(struct b43_plcp_hdr6);
1418 tim_position += offsetof(struct ieee80211_mgmt, u.beacon.variable);
1421 dtim_period = ie[i + 3];
1423 b43_shm_write16(dev, B43_SHM_SHARED,
1424 B43_SHM_SH_TIMBPOS, tim_position);
1425 b43_shm_write16(dev, B43_SHM_SHARED,
1426 B43_SHM_SH_DTIMPER, dtim_period);
1433 * If ucode wants to modify TIM do it behind the beacon, this
1434 * will happen, for example, when doing mesh networking.
1436 b43_shm_write16(dev, B43_SHM_SHARED,
1438 len + sizeof(struct b43_plcp_hdr6));
1439 b43_shm_write16(dev, B43_SHM_SHARED,
1440 B43_SHM_SH_DTIMPER, 0);
1442 b43dbg(dev->wl, "Updated beacon template at 0x%x\n", ram_offset);
1445 static void b43_write_probe_resp_plcp(struct b43_wldev *dev,
1446 u16 shm_offset, u16 size,
1447 struct ieee80211_rate *rate)
1449 struct b43_plcp_hdr4 plcp;
1454 b43_generate_plcp_hdr(&plcp, size + FCS_LEN, rate->hw_value);
1455 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1458 /* Write PLCP in two parts and timing for packet transfer */
1459 tmp = le32_to_cpu(plcp.data);
1460 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset, tmp & 0xFFFF);
1461 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 2, tmp >> 16);
1462 b43_shm_write16(dev, B43_SHM_SHARED, shm_offset + 6, le16_to_cpu(dur));
1465 /* Instead of using custom probe response template, this function
1466 * just patches custom beacon template by:
1467 * 1) Changing packet type
1468 * 2) Patching duration field
1471 static const u8 * b43_generate_probe_resp(struct b43_wldev *dev,
1473 struct ieee80211_rate *rate)
1477 u16 src_size, elem_size, src_pos, dest_pos;
1479 struct ieee80211_hdr *hdr;
1482 src_size = dev->wl->current_beacon->len;
1483 src_data = (const u8 *)dev->wl->current_beacon->data;
1485 /* Get the start offset of the variable IEs in the packet. */
1486 ie_start = offsetof(struct ieee80211_mgmt, u.probe_resp.variable);
1487 B43_WARN_ON(ie_start != offsetof(struct ieee80211_mgmt, u.beacon.variable));
1489 if (B43_WARN_ON(src_size < ie_start))
1492 dest_data = kmalloc(src_size, GFP_ATOMIC);
1493 if (unlikely(!dest_data))
1496 /* Copy the static data and all Information Elements, except the TIM. */
1497 memcpy(dest_data, src_data, ie_start);
1499 dest_pos = ie_start;
1500 for ( ; src_pos < src_size - 2; src_pos += elem_size) {
1501 elem_size = src_data[src_pos + 1] + 2;
1502 if (src_data[src_pos] == 5) {
1503 /* This is the TIM. */
1506 memcpy(dest_data + dest_pos, src_data + src_pos,
1508 dest_pos += elem_size;
1510 *dest_size = dest_pos;
1511 hdr = (struct ieee80211_hdr *)dest_data;
1513 /* Set the frame control. */
1514 hdr->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
1515 IEEE80211_STYPE_PROBE_RESP);
1516 dur = ieee80211_generic_frame_duration(dev->wl->hw,
1517 dev->wl->vif, *dest_size,
1519 hdr->duration_id = dur;
1524 static void b43_write_probe_resp_template(struct b43_wldev *dev,
1526 u16 shm_size_offset,
1527 struct ieee80211_rate *rate)
1529 const u8 *probe_resp_data;
1532 size = dev->wl->current_beacon->len;
1533 probe_resp_data = b43_generate_probe_resp(dev, &size, rate);
1534 if (unlikely(!probe_resp_data))
1537 /* Looks like PLCP headers plus packet timings are stored for
1538 * all possible basic rates
1540 b43_write_probe_resp_plcp(dev, 0x31A, size, &b43_b_ratetable[0]);
1541 b43_write_probe_resp_plcp(dev, 0x32C, size, &b43_b_ratetable[1]);
1542 b43_write_probe_resp_plcp(dev, 0x33E, size, &b43_b_ratetable[2]);
1543 b43_write_probe_resp_plcp(dev, 0x350, size, &b43_b_ratetable[3]);
1545 size = min((size_t) size, 0x200 - sizeof(struct b43_plcp_hdr6));
1546 b43_write_template_common(dev, probe_resp_data,
1547 size, ram_offset, shm_size_offset,
1549 kfree(probe_resp_data);
1552 static void b43_upload_beacon0(struct b43_wldev *dev)
1554 struct b43_wl *wl = dev->wl;
1556 if (wl->beacon0_uploaded)
1558 b43_write_beacon_template(dev, 0x68, 0x18);
1559 /* FIXME: Probe resp upload doesn't really belong here,
1560 * but we don't use that feature anyway. */
1561 b43_write_probe_resp_template(dev, 0x268, 0x4A,
1562 &__b43_ratetable[3]);
1563 wl->beacon0_uploaded = 1;
1566 static void b43_upload_beacon1(struct b43_wldev *dev)
1568 struct b43_wl *wl = dev->wl;
1570 if (wl->beacon1_uploaded)
1572 b43_write_beacon_template(dev, 0x468, 0x1A);
1573 wl->beacon1_uploaded = 1;
1576 static void handle_irq_beacon(struct b43_wldev *dev)
1578 struct b43_wl *wl = dev->wl;
1579 u32 cmd, beacon0_valid, beacon1_valid;
1581 if (!b43_is_mode(wl, NL80211_IFTYPE_AP) &&
1582 !b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
1585 /* This is the bottom half of the asynchronous beacon update. */
1587 /* Ignore interrupt in the future. */
1588 dev->irq_savedstate &= ~B43_IRQ_BEACON;
1590 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1591 beacon0_valid = (cmd & B43_MACCMD_BEACON0_VALID);
1592 beacon1_valid = (cmd & B43_MACCMD_BEACON1_VALID);
1594 /* Schedule interrupt manually, if busy. */
1595 if (beacon0_valid && beacon1_valid) {
1596 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_BEACON);
1597 dev->irq_savedstate |= B43_IRQ_BEACON;
1601 if (unlikely(wl->beacon_templates_virgin)) {
1602 /* We never uploaded a beacon before.
1603 * Upload both templates now, but only mark one valid. */
1604 wl->beacon_templates_virgin = 0;
1605 b43_upload_beacon0(dev);
1606 b43_upload_beacon1(dev);
1607 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1608 cmd |= B43_MACCMD_BEACON0_VALID;
1609 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1611 if (!beacon0_valid) {
1612 b43_upload_beacon0(dev);
1613 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1614 cmd |= B43_MACCMD_BEACON0_VALID;
1615 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1616 } else if (!beacon1_valid) {
1617 b43_upload_beacon1(dev);
1618 cmd = b43_read32(dev, B43_MMIO_MACCMD);
1619 cmd |= B43_MACCMD_BEACON1_VALID;
1620 b43_write32(dev, B43_MMIO_MACCMD, cmd);
1625 static void b43_beacon_update_trigger_work(struct work_struct *work)
1627 struct b43_wl *wl = container_of(work, struct b43_wl,
1628 beacon_update_trigger);
1629 struct b43_wldev *dev;
1631 mutex_lock(&wl->mutex);
1632 dev = wl->current_dev;
1633 if (likely(dev && (b43_status(dev) >= B43_STAT_INITIALIZED))) {
1634 spin_lock_irq(&wl->irq_lock);
1635 /* update beacon right away or defer to irq */
1636 dev->irq_savedstate = b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1637 handle_irq_beacon(dev);
1638 /* The handler might have updated the IRQ mask. */
1639 b43_write32(dev, B43_MMIO_GEN_IRQ_MASK,
1640 dev->irq_savedstate);
1642 spin_unlock_irq(&wl->irq_lock);
1644 mutex_unlock(&wl->mutex);
1647 /* Asynchronously update the packet templates in template RAM.
1648 * Locking: Requires wl->irq_lock to be locked. */
1649 static void b43_update_templates(struct b43_wl *wl)
1651 struct sk_buff *beacon;
1653 /* This is the top half of the ansynchronous beacon update.
1654 * The bottom half is the beacon IRQ.
1655 * Beacon update must be asynchronous to avoid sending an
1656 * invalid beacon. This can happen for example, if the firmware
1657 * transmits a beacon while we are updating it. */
1659 /* We could modify the existing beacon and set the aid bit in
1660 * the TIM field, but that would probably require resizing and
1661 * moving of data within the beacon template.
1662 * Simply request a new beacon and let mac80211 do the hard work. */
1663 beacon = ieee80211_beacon_get(wl->hw, wl->vif);
1664 if (unlikely(!beacon))
1667 if (wl->current_beacon)
1668 dev_kfree_skb_any(wl->current_beacon);
1669 wl->current_beacon = beacon;
1670 wl->beacon0_uploaded = 0;
1671 wl->beacon1_uploaded = 0;
1672 queue_work(wl->hw->workqueue, &wl->beacon_update_trigger);
1675 static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
1678 if (dev->dev->id.revision >= 3) {
1679 b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
1680 b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
1682 b43_write16(dev, 0x606, (beacon_int >> 6));
1683 b43_write16(dev, 0x610, beacon_int);
1685 b43_time_unlock(dev);
1686 b43dbg(dev->wl, "Set beacon interval to %u\n", beacon_int);
1689 static void b43_handle_firmware_panic(struct b43_wldev *dev)
1693 /* Read the register that contains the reason code for the panic. */
1694 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_FWPANIC_REASON_REG);
1695 b43err(dev->wl, "Whoopsy, firmware panic! Reason: %u\n", reason);
1699 b43dbg(dev->wl, "The panic reason is unknown.\n");
1701 case B43_FWPANIC_DIE:
1702 /* Do not restart the controller or firmware.
1703 * The device is nonfunctional from now on.
1704 * Restarting would result in this panic to trigger again,
1705 * so we avoid that recursion. */
1707 case B43_FWPANIC_RESTART:
1708 b43_controller_restart(dev, "Microcode panic");
1713 static void handle_irq_ucode_debug(struct b43_wldev *dev)
1715 unsigned int i, cnt;
1716 u16 reason, marker_id, marker_line;
1719 /* The proprietary firmware doesn't have this IRQ. */
1720 if (!dev->fw.opensource)
1723 /* Read the register that contains the reason code for this IRQ. */
1724 reason = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_DEBUGIRQ_REASON_REG);
1727 case B43_DEBUGIRQ_PANIC:
1728 b43_handle_firmware_panic(dev);
1730 case B43_DEBUGIRQ_DUMP_SHM:
1732 break; /* Only with driver debugging enabled. */
1733 buf = kmalloc(4096, GFP_ATOMIC);
1735 b43dbg(dev->wl, "SHM-dump: Failed to allocate memory\n");
1738 for (i = 0; i < 4096; i += 2) {
1739 u16 tmp = b43_shm_read16(dev, B43_SHM_SHARED, i);
1740 buf[i / 2] = cpu_to_le16(tmp);
1742 b43info(dev->wl, "Shared memory dump:\n");
1743 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET,
1744 16, 2, buf, 4096, 1);
1747 case B43_DEBUGIRQ_DUMP_REGS:
1749 break; /* Only with driver debugging enabled. */
1750 b43info(dev->wl, "Microcode register dump:\n");
1751 for (i = 0, cnt = 0; i < 64; i++) {
1752 u16 tmp = b43_shm_read16(dev, B43_SHM_SCRATCH, i);
1755 printk("r%02u: 0x%04X ", i, tmp);
1764 case B43_DEBUGIRQ_MARKER:
1766 break; /* Only with driver debugging enabled. */
1767 marker_id = b43_shm_read16(dev, B43_SHM_SCRATCH,
1769 marker_line = b43_shm_read16(dev, B43_SHM_SCRATCH,
1770 B43_MARKER_LINE_REG);
1771 b43info(dev->wl, "The firmware just executed the MARKER(%u) "
1772 "at line number %u\n",
1773 marker_id, marker_line);
1776 b43dbg(dev->wl, "Debug-IRQ triggered for unknown reason: %u\n",
1780 /* Acknowledge the debug-IRQ, so the firmware can continue. */
1781 b43_shm_write16(dev, B43_SHM_SCRATCH,
1782 B43_DEBUGIRQ_REASON_REG, B43_DEBUGIRQ_ACK);
1785 /* Interrupt handler bottom-half */
1786 static void b43_interrupt_tasklet(struct b43_wldev *dev)
1789 u32 dma_reason[ARRAY_SIZE(dev->dma_reason)];
1790 u32 merged_dma_reason = 0;
1792 unsigned long flags;
1794 spin_lock_irqsave(&dev->wl->irq_lock, flags);
1796 B43_WARN_ON(b43_status(dev) != B43_STAT_STARTED);
1798 reason = dev->irq_reason;
1799 for (i = 0; i < ARRAY_SIZE(dma_reason); i++) {
1800 dma_reason[i] = dev->dma_reason[i];
1801 merged_dma_reason |= dma_reason[i];
1804 if (unlikely(reason & B43_IRQ_MAC_TXERR))
1805 b43err(dev->wl, "MAC transmission error\n");
1807 if (unlikely(reason & B43_IRQ_PHY_TXERR)) {
1808 b43err(dev->wl, "PHY transmission error\n");
1810 if (unlikely(atomic_dec_and_test(&dev->phy.txerr_cnt))) {
1811 atomic_set(&dev->phy.txerr_cnt,
1812 B43_PHY_TX_BADNESS_LIMIT);
1813 b43err(dev->wl, "Too many PHY TX errors, "
1814 "restarting the controller\n");
1815 b43_controller_restart(dev, "PHY TX errors");
1819 if (unlikely(merged_dma_reason & (B43_DMAIRQ_FATALMASK |
1820 B43_DMAIRQ_NONFATALMASK))) {
1821 if (merged_dma_reason & B43_DMAIRQ_FATALMASK) {
1822 b43err(dev->wl, "Fatal DMA error: "
1823 "0x%08X, 0x%08X, 0x%08X, "
1824 "0x%08X, 0x%08X, 0x%08X\n",
1825 dma_reason[0], dma_reason[1],
1826 dma_reason[2], dma_reason[3],
1827 dma_reason[4], dma_reason[5]);
1828 b43_controller_restart(dev, "DMA error");
1830 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1833 if (merged_dma_reason & B43_DMAIRQ_NONFATALMASK) {
1834 b43err(dev->wl, "DMA error: "
1835 "0x%08X, 0x%08X, 0x%08X, "
1836 "0x%08X, 0x%08X, 0x%08X\n",
1837 dma_reason[0], dma_reason[1],
1838 dma_reason[2], dma_reason[3],
1839 dma_reason[4], dma_reason[5]);
1843 if (unlikely(reason & B43_IRQ_UCODE_DEBUG))
1844 handle_irq_ucode_debug(dev);
1845 if (reason & B43_IRQ_TBTT_INDI)
1846 handle_irq_tbtt_indication(dev);
1847 if (reason & B43_IRQ_ATIM_END)
1848 handle_irq_atim_end(dev);
1849 if (reason & B43_IRQ_BEACON)
1850 handle_irq_beacon(dev);
1851 if (reason & B43_IRQ_PMQ)
1852 handle_irq_pmq(dev);
1853 if (reason & B43_IRQ_TXFIFO_FLUSH_OK)
1855 if (reason & B43_IRQ_NOISESAMPLE_OK)
1856 handle_irq_noise(dev);
1858 /* Check the DMA reason registers for received data. */
1859 if (dma_reason[0] & B43_DMAIRQ_RX_DONE) {
1860 if (b43_using_pio_transfers(dev))
1861 b43_pio_rx(dev->pio.rx_queue);
1863 b43_dma_rx(dev->dma.rx_ring);
1865 B43_WARN_ON(dma_reason[1] & B43_DMAIRQ_RX_DONE);
1866 B43_WARN_ON(dma_reason[2] & B43_DMAIRQ_RX_DONE);
1867 B43_WARN_ON(dma_reason[3] & B43_DMAIRQ_RX_DONE);
1868 B43_WARN_ON(dma_reason[4] & B43_DMAIRQ_RX_DONE);
1869 B43_WARN_ON(dma_reason[5] & B43_DMAIRQ_RX_DONE);
1871 if (reason & B43_IRQ_TX_OK)
1872 handle_irq_transmit_status(dev);
1874 b43_interrupt_enable(dev, dev->irq_savedstate);
1876 spin_unlock_irqrestore(&dev->wl->irq_lock, flags);
1879 static void b43_interrupt_ack(struct b43_wldev *dev, u32 reason)
1881 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, reason);
1883 b43_write32(dev, B43_MMIO_DMA0_REASON, dev->dma_reason[0]);
1884 b43_write32(dev, B43_MMIO_DMA1_REASON, dev->dma_reason[1]);
1885 b43_write32(dev, B43_MMIO_DMA2_REASON, dev->dma_reason[2]);
1886 b43_write32(dev, B43_MMIO_DMA3_REASON, dev->dma_reason[3]);
1887 b43_write32(dev, B43_MMIO_DMA4_REASON, dev->dma_reason[4]);
1888 b43_write32(dev, B43_MMIO_DMA5_REASON, dev->dma_reason[5]);
1891 /* Interrupt handler top-half */
1892 static irqreturn_t b43_interrupt_handler(int irq, void *dev_id)
1894 irqreturn_t ret = IRQ_NONE;
1895 struct b43_wldev *dev = dev_id;
1901 spin_lock(&dev->wl->irq_lock);
1903 if (b43_status(dev) < B43_STAT_STARTED)
1905 reason = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
1906 if (reason == 0xffffffff) /* shared IRQ */
1909 reason &= b43_read32(dev, B43_MMIO_GEN_IRQ_MASK);
1913 dev->dma_reason[0] = b43_read32(dev, B43_MMIO_DMA0_REASON)
1915 dev->dma_reason[1] = b43_read32(dev, B43_MMIO_DMA1_REASON)
1917 dev->dma_reason[2] = b43_read32(dev, B43_MMIO_DMA2_REASON)
1919 dev->dma_reason[3] = b43_read32(dev, B43_MMIO_DMA3_REASON)
1921 dev->dma_reason[4] = b43_read32(dev, B43_MMIO_DMA4_REASON)
1923 dev->dma_reason[5] = b43_read32(dev, B43_MMIO_DMA5_REASON)
1926 b43_interrupt_ack(dev, reason);
1927 /* disable all IRQs. They are enabled again in the bottom half. */
1928 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
1929 /* save the reason code and call our bottom half. */
1930 dev->irq_reason = reason;
1931 tasklet_schedule(&dev->isr_tasklet);
1934 spin_unlock(&dev->wl->irq_lock);
1939 static void do_release_fw(struct b43_firmware_file *fw)
1941 release_firmware(fw->data);
1943 fw->filename = NULL;
1946 static void b43_release_firmware(struct b43_wldev *dev)
1948 do_release_fw(&dev->fw.ucode);
1949 do_release_fw(&dev->fw.pcm);
1950 do_release_fw(&dev->fw.initvals);
1951 do_release_fw(&dev->fw.initvals_band);
1954 static void b43_print_fw_helptext(struct b43_wl *wl, bool error)
1958 text = "You must go to "
1959 "http://linuxwireless.org/en/users/Drivers/b43#devicefirmware "
1960 "and download the latest firmware (version 4).\n";
1967 static int do_request_fw(struct b43_wldev *dev,
1969 struct b43_firmware_file *fw,
1972 char path[sizeof(modparam_fwpostfix) + 32];
1973 const struct firmware *blob;
1974 struct b43_fw_header *hdr;
1979 /* Don't fetch anything. Free possibly cached firmware. */
1984 if (strcmp(fw->filename, name) == 0)
1985 return 0; /* Already have this fw. */
1986 /* Free the cached firmware first. */
1990 snprintf(path, ARRAY_SIZE(path),
1992 modparam_fwpostfix, name);
1993 err = request_firmware(&blob, path, dev->dev->dev);
1994 if (err == -ENOENT) {
1996 b43err(dev->wl, "Firmware file \"%s\" not found\n",
2001 b43err(dev->wl, "Firmware file \"%s\" request failed (err=%d)\n",
2005 if (blob->size < sizeof(struct b43_fw_header))
2007 hdr = (struct b43_fw_header *)(blob->data);
2008 switch (hdr->type) {
2009 case B43_FW_TYPE_UCODE:
2010 case B43_FW_TYPE_PCM:
2011 size = be32_to_cpu(hdr->size);
2012 if (size != blob->size - sizeof(struct b43_fw_header))
2015 case B43_FW_TYPE_IV:
2024 fw->filename = name;
2029 b43err(dev->wl, "Firmware file \"%s\" format error.\n", path);
2030 release_firmware(blob);
2035 static int b43_request_firmware(struct b43_wldev *dev)
2037 struct b43_firmware *fw = &dev->fw;
2038 const u8 rev = dev->dev->id.revision;
2039 const char *filename;
2044 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
2045 if ((rev >= 5) && (rev <= 10))
2046 filename = "ucode5";
2047 else if ((rev >= 11) && (rev <= 12))
2048 filename = "ucode11";
2050 filename = "ucode13";
2053 err = do_request_fw(dev, filename, &fw->ucode, 0);
2058 if ((rev >= 5) && (rev <= 10))
2064 fw->pcm_request_failed = 0;
2065 err = do_request_fw(dev, filename, &fw->pcm, 1);
2066 if (err == -ENOENT) {
2067 /* We did not find a PCM file? Not fatal, but
2068 * core rev <= 10 must do without hwcrypto then. */
2069 fw->pcm_request_failed = 1;
2074 switch (dev->phy.type) {
2076 if ((rev >= 5) && (rev <= 10)) {
2077 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2078 filename = "a0g1initvals5";
2080 filename = "a0g0initvals5";
2082 goto err_no_initvals;
2085 if ((rev >= 5) && (rev <= 10))
2086 filename = "b0g0initvals5";
2088 filename = "b0g0initvals13";
2090 goto err_no_initvals;
2093 if ((rev >= 11) && (rev <= 12))
2094 filename = "n0initvals11";
2096 goto err_no_initvals;
2099 goto err_no_initvals;
2101 err = do_request_fw(dev, filename, &fw->initvals, 0);
2105 /* Get bandswitch initvals */
2106 switch (dev->phy.type) {
2108 if ((rev >= 5) && (rev <= 10)) {
2109 if (tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY)
2110 filename = "a0g1bsinitvals5";
2112 filename = "a0g0bsinitvals5";
2113 } else if (rev >= 11)
2116 goto err_no_initvals;
2119 if ((rev >= 5) && (rev <= 10))
2120 filename = "b0g0bsinitvals5";
2124 goto err_no_initvals;
2127 if ((rev >= 11) && (rev <= 12))
2128 filename = "n0bsinitvals11";
2130 goto err_no_initvals;
2133 goto err_no_initvals;
2135 err = do_request_fw(dev, filename, &fw->initvals_band, 0);
2142 b43_print_fw_helptext(dev->wl, 1);
2147 b43err(dev->wl, "No microcode available for core rev %u\n", rev);
2152 b43err(dev->wl, "No PCM available for core rev %u\n", rev);
2157 b43err(dev->wl, "No Initial Values firmware file for PHY %u, "
2158 "core rev %u\n", dev->phy.type, rev);
2162 b43_release_firmware(dev);
2166 static int b43_upload_microcode(struct b43_wldev *dev)
2168 const size_t hdr_len = sizeof(struct b43_fw_header);
2170 unsigned int i, len;
2171 u16 fwrev, fwpatch, fwdate, fwtime;
2175 /* Jump the microcode PSM to offset 0 */
2176 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2177 B43_WARN_ON(macctl & B43_MACCTL_PSM_RUN);
2178 macctl |= B43_MACCTL_PSM_JMP0;
2179 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2180 /* Zero out all microcode PSM registers and shared memory. */
2181 for (i = 0; i < 64; i++)
2182 b43_shm_write16(dev, B43_SHM_SCRATCH, i, 0);
2183 for (i = 0; i < 4096; i += 2)
2184 b43_shm_write16(dev, B43_SHM_SHARED, i, 0);
2186 /* Upload Microcode. */
2187 data = (__be32 *) (dev->fw.ucode.data->data + hdr_len);
2188 len = (dev->fw.ucode.data->size - hdr_len) / sizeof(__be32);
2189 b43_shm_control_word(dev, B43_SHM_UCODE | B43_SHM_AUTOINC_W, 0x0000);
2190 for (i = 0; i < len; i++) {
2191 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2195 if (dev->fw.pcm.data) {
2196 /* Upload PCM data. */
2197 data = (__be32 *) (dev->fw.pcm.data->data + hdr_len);
2198 len = (dev->fw.pcm.data->size - hdr_len) / sizeof(__be32);
2199 b43_shm_control_word(dev, B43_SHM_HW, 0x01EA);
2200 b43_write32(dev, B43_MMIO_SHM_DATA, 0x00004000);
2201 /* No need for autoinc bit in SHM_HW */
2202 b43_shm_control_word(dev, B43_SHM_HW, 0x01EB);
2203 for (i = 0; i < len; i++) {
2204 b43_write32(dev, B43_MMIO_SHM_DATA, be32_to_cpu(data[i]));
2209 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, B43_IRQ_ALL);
2211 /* Start the microcode PSM */
2212 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2213 macctl &= ~B43_MACCTL_PSM_JMP0;
2214 macctl |= B43_MACCTL_PSM_RUN;
2215 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2217 /* Wait for the microcode to load and respond */
2220 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2221 if (tmp == B43_IRQ_MAC_SUSPENDED)
2225 b43err(dev->wl, "Microcode not responding\n");
2226 b43_print_fw_helptext(dev->wl, 1);
2230 msleep_interruptible(50);
2231 if (signal_pending(current)) {
2236 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON); /* dummy read */
2238 /* Get and check the revisions. */
2239 fwrev = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEREV);
2240 fwpatch = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEPATCH);
2241 fwdate = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODEDATE);
2242 fwtime = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_UCODETIME);
2244 if (fwrev <= 0x128) {
2245 b43err(dev->wl, "YOUR FIRMWARE IS TOO OLD. Firmware from "
2246 "binary drivers older than version 4.x is unsupported. "
2247 "You must upgrade your firmware files.\n");
2248 b43_print_fw_helptext(dev->wl, 1);
2252 dev->fw.rev = fwrev;
2253 dev->fw.patch = fwpatch;
2254 dev->fw.opensource = (fwdate == 0xFFFF);
2256 if (dev->fw.opensource) {
2257 /* Patchlevel info is encoded in the "time" field. */
2258 dev->fw.patch = fwtime;
2259 b43info(dev->wl, "Loading OpenSource firmware version %u.%u%s\n",
2260 dev->fw.rev, dev->fw.patch,
2261 dev->fw.pcm_request_failed ? " (Hardware crypto not supported)" : "");
2263 b43info(dev->wl, "Loading firmware version %u.%u "
2264 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
2266 (fwdate >> 12) & 0xF, (fwdate >> 8) & 0xF, fwdate & 0xFF,
2267 (fwtime >> 11) & 0x1F, (fwtime >> 5) & 0x3F, fwtime & 0x1F);
2268 if (dev->fw.pcm_request_failed) {
2269 b43warn(dev->wl, "No \"pcm5.fw\" firmware file found. "
2270 "Hardware accelerated cryptography is disabled.\n");
2271 b43_print_fw_helptext(dev->wl, 0);
2275 if (b43_is_old_txhdr_format(dev)) {
2276 b43warn(dev->wl, "You are using an old firmware image. "
2277 "Support for old firmware will be removed in July 2008.\n");
2278 b43_print_fw_helptext(dev->wl, 0);
2284 macctl = b43_read32(dev, B43_MMIO_MACCTL);
2285 macctl &= ~B43_MACCTL_PSM_RUN;
2286 macctl |= B43_MACCTL_PSM_JMP0;
2287 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2292 static int b43_write_initvals(struct b43_wldev *dev,
2293 const struct b43_iv *ivals,
2297 const struct b43_iv *iv;
2302 BUILD_BUG_ON(sizeof(struct b43_iv) != 6);
2304 for (i = 0; i < count; i++) {
2305 if (array_size < sizeof(iv->offset_size))
2307 array_size -= sizeof(iv->offset_size);
2308 offset = be16_to_cpu(iv->offset_size);
2309 bit32 = !!(offset & B43_IV_32BIT);
2310 offset &= B43_IV_OFFSET_MASK;
2311 if (offset >= 0x1000)
2316 if (array_size < sizeof(iv->data.d32))
2318 array_size -= sizeof(iv->data.d32);
2320 value = get_unaligned_be32(&iv->data.d32);
2321 b43_write32(dev, offset, value);
2323 iv = (const struct b43_iv *)((const uint8_t *)iv +
2329 if (array_size < sizeof(iv->data.d16))
2331 array_size -= sizeof(iv->data.d16);
2333 value = be16_to_cpu(iv->data.d16);
2334 b43_write16(dev, offset, value);
2336 iv = (const struct b43_iv *)((const uint8_t *)iv +
2347 b43err(dev->wl, "Initial Values Firmware file-format error.\n");
2348 b43_print_fw_helptext(dev->wl, 1);
2353 static int b43_upload_initvals(struct b43_wldev *dev)
2355 const size_t hdr_len = sizeof(struct b43_fw_header);
2356 const struct b43_fw_header *hdr;
2357 struct b43_firmware *fw = &dev->fw;
2358 const struct b43_iv *ivals;
2362 hdr = (const struct b43_fw_header *)(fw->initvals.data->data);
2363 ivals = (const struct b43_iv *)(fw->initvals.data->data + hdr_len);
2364 count = be32_to_cpu(hdr->size);
2365 err = b43_write_initvals(dev, ivals, count,
2366 fw->initvals.data->size - hdr_len);
2369 if (fw->initvals_band.data) {
2370 hdr = (const struct b43_fw_header *)(fw->initvals_band.data->data);
2371 ivals = (const struct b43_iv *)(fw->initvals_band.data->data + hdr_len);
2372 count = be32_to_cpu(hdr->size);
2373 err = b43_write_initvals(dev, ivals, count,
2374 fw->initvals_band.data->size - hdr_len);
2383 /* Initialize the GPIOs
2384 * http://bcm-specs.sipsolutions.net/GPIO
2386 static int b43_gpio_init(struct b43_wldev *dev)
2388 struct ssb_bus *bus = dev->dev->bus;
2389 struct ssb_device *gpiodev, *pcidev = NULL;
2392 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2393 & ~B43_MACCTL_GPOUTSMSK);
2395 b43_write16(dev, B43_MMIO_GPIO_MASK, b43_read16(dev, B43_MMIO_GPIO_MASK)
2400 if (dev->dev->bus->chip_id == 0x4301) {
2404 if (0 /* FIXME: conditional unknown */ ) {
2405 b43_write16(dev, B43_MMIO_GPIO_MASK,
2406 b43_read16(dev, B43_MMIO_GPIO_MASK)
2411 if (dev->dev->bus->sprom.boardflags_lo & B43_BFL_PACTRL) {
2412 b43_write16(dev, B43_MMIO_GPIO_MASK,
2413 b43_read16(dev, B43_MMIO_GPIO_MASK)
2418 if (dev->dev->id.revision >= 2)
2419 mask |= 0x0010; /* FIXME: This is redundant. */
2421 #ifdef CONFIG_SSB_DRIVER_PCICORE
2422 pcidev = bus->pcicore.dev;
2424 gpiodev = bus->chipco.dev ? : pcidev;
2427 ssb_write32(gpiodev, B43_GPIO_CONTROL,
2428 (ssb_read32(gpiodev, B43_GPIO_CONTROL)
2434 /* Turn off all GPIO stuff. Call this on module unload, for example. */
2435 static void b43_gpio_cleanup(struct b43_wldev *dev)
2437 struct ssb_bus *bus = dev->dev->bus;
2438 struct ssb_device *gpiodev, *pcidev = NULL;
2440 #ifdef CONFIG_SSB_DRIVER_PCICORE
2441 pcidev = bus->pcicore.dev;
2443 gpiodev = bus->chipco.dev ? : pcidev;
2446 ssb_write32(gpiodev, B43_GPIO_CONTROL, 0);
2449 /* http://bcm-specs.sipsolutions.net/EnableMac */
2450 void b43_mac_enable(struct b43_wldev *dev)
2452 if (b43_debug(dev, B43_DBG_FIRMWARE)) {
2455 fwstate = b43_shm_read16(dev, B43_SHM_SHARED,
2456 B43_SHM_SH_UCODESTAT);
2457 if ((fwstate != B43_SHM_SH_UCODESTAT_SUSP) &&
2458 (fwstate != B43_SHM_SH_UCODESTAT_SLEEP)) {
2459 b43err(dev->wl, "b43_mac_enable(): The firmware "
2460 "should be suspended, but current state is %u\n",
2465 dev->mac_suspended--;
2466 B43_WARN_ON(dev->mac_suspended < 0);
2467 if (dev->mac_suspended == 0) {
2468 b43_write32(dev, B43_MMIO_MACCTL,
2469 b43_read32(dev, B43_MMIO_MACCTL)
2470 | B43_MACCTL_ENABLED);
2471 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON,
2472 B43_IRQ_MAC_SUSPENDED);
2474 b43_read32(dev, B43_MMIO_MACCTL);
2475 b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2476 b43_power_saving_ctl_bits(dev, 0);
2480 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
2481 void b43_mac_suspend(struct b43_wldev *dev)
2487 B43_WARN_ON(dev->mac_suspended < 0);
2489 if (dev->mac_suspended == 0) {
2490 b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
2491 b43_write32(dev, B43_MMIO_MACCTL,
2492 b43_read32(dev, B43_MMIO_MACCTL)
2493 & ~B43_MACCTL_ENABLED);
2494 /* force pci to flush the write */
2495 b43_read32(dev, B43_MMIO_MACCTL);
2496 for (i = 35; i; i--) {
2497 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2498 if (tmp & B43_IRQ_MAC_SUSPENDED)
2502 /* Hm, it seems this will take some time. Use msleep(). */
2503 for (i = 40; i; i--) {
2504 tmp = b43_read32(dev, B43_MMIO_GEN_IRQ_REASON);
2505 if (tmp & B43_IRQ_MAC_SUSPENDED)
2509 b43err(dev->wl, "MAC suspend failed\n");
2512 dev->mac_suspended++;
2515 static void b43_adjust_opmode(struct b43_wldev *dev)
2517 struct b43_wl *wl = dev->wl;
2521 ctl = b43_read32(dev, B43_MMIO_MACCTL);
2522 /* Reset status to STA infrastructure mode. */
2523 ctl &= ~B43_MACCTL_AP;
2524 ctl &= ~B43_MACCTL_KEEP_CTL;
2525 ctl &= ~B43_MACCTL_KEEP_BADPLCP;
2526 ctl &= ~B43_MACCTL_KEEP_BAD;
2527 ctl &= ~B43_MACCTL_PROMISC;
2528 ctl &= ~B43_MACCTL_BEACPROMISC;
2529 ctl |= B43_MACCTL_INFRA;
2531 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
2532 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
2533 ctl |= B43_MACCTL_AP;
2534 else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC))
2535 ctl &= ~B43_MACCTL_INFRA;
2537 if (wl->filter_flags & FIF_CONTROL)
2538 ctl |= B43_MACCTL_KEEP_CTL;
2539 if (wl->filter_flags & FIF_FCSFAIL)
2540 ctl |= B43_MACCTL_KEEP_BAD;
2541 if (wl->filter_flags & FIF_PLCPFAIL)
2542 ctl |= B43_MACCTL_KEEP_BADPLCP;
2543 if (wl->filter_flags & FIF_PROMISC_IN_BSS)
2544 ctl |= B43_MACCTL_PROMISC;
2545 if (wl->filter_flags & FIF_BCN_PRBRESP_PROMISC)
2546 ctl |= B43_MACCTL_BEACPROMISC;
2548 /* Workaround: On old hardware the HW-MAC-address-filter
2549 * doesn't work properly, so always run promisc in filter
2550 * it in software. */
2551 if (dev->dev->id.revision <= 4)
2552 ctl |= B43_MACCTL_PROMISC;
2554 b43_write32(dev, B43_MMIO_MACCTL, ctl);
2557 if ((ctl & B43_MACCTL_INFRA) && !(ctl & B43_MACCTL_AP)) {
2558 if (dev->dev->bus->chip_id == 0x4306 &&
2559 dev->dev->bus->chip_rev == 3)
2564 b43_write16(dev, 0x612, cfp_pretbtt);
2567 static void b43_rate_memory_write(struct b43_wldev *dev, u16 rate, int is_ofdm)
2573 offset += (b43_plcp_get_ratecode_ofdm(rate) & 0x000F) * 2;
2576 offset += (b43_plcp_get_ratecode_cck(rate) & 0x000F) * 2;
2578 b43_shm_write16(dev, B43_SHM_SHARED, offset + 0x20,
2579 b43_shm_read16(dev, B43_SHM_SHARED, offset));
2582 static void b43_rate_memory_init(struct b43_wldev *dev)
2584 switch (dev->phy.type) {
2588 b43_rate_memory_write(dev, B43_OFDM_RATE_6MB, 1);
2589 b43_rate_memory_write(dev, B43_OFDM_RATE_12MB, 1);
2590 b43_rate_memory_write(dev, B43_OFDM_RATE_18MB, 1);
2591 b43_rate_memory_write(dev, B43_OFDM_RATE_24MB, 1);
2592 b43_rate_memory_write(dev, B43_OFDM_RATE_36MB, 1);
2593 b43_rate_memory_write(dev, B43_OFDM_RATE_48MB, 1);
2594 b43_rate_memory_write(dev, B43_OFDM_RATE_54MB, 1);
2595 if (dev->phy.type == B43_PHYTYPE_A)
2599 b43_rate_memory_write(dev, B43_CCK_RATE_1MB, 0);
2600 b43_rate_memory_write(dev, B43_CCK_RATE_2MB, 0);
2601 b43_rate_memory_write(dev, B43_CCK_RATE_5MB, 0);
2602 b43_rate_memory_write(dev, B43_CCK_RATE_11MB, 0);
2609 /* Set the default values for the PHY TX Control Words. */
2610 static void b43_set_phytxctl_defaults(struct b43_wldev *dev)
2614 ctl |= B43_TXH_PHY_ENC_CCK;
2615 ctl |= B43_TXH_PHY_ANT01AUTO;
2616 ctl |= B43_TXH_PHY_TXPWR;
2618 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_BEACPHYCTL, ctl);
2619 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, ctl);
2620 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, ctl);
2623 /* Set the TX-Antenna for management frames sent by firmware. */
2624 static void b43_mgmtframe_txantenna(struct b43_wldev *dev, int antenna)
2629 ant = b43_antenna_to_phyctl(antenna);
2632 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL);
2633 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2634 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_ACKCTSPHYCTL, tmp);
2635 /* For Probe Resposes */
2636 tmp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL);
2637 tmp = (tmp & ~B43_TXH_PHY_ANT) | ant;
2638 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRPHYCTL, tmp);
2641 /* This is the opposite of b43_chip_init() */
2642 static void b43_chip_exit(struct b43_wldev *dev)
2645 b43_gpio_cleanup(dev);
2646 /* firmware is released later */
2649 /* Initialize the chip
2650 * http://bcm-specs.sipsolutions.net/ChipInit
2652 static int b43_chip_init(struct b43_wldev *dev)
2654 struct b43_phy *phy = &dev->phy;
2656 u32 value32, macctl;
2659 /* Initialize the MAC control */
2660 macctl = B43_MACCTL_IHR_ENABLED | B43_MACCTL_SHM_ENABLED;
2662 macctl |= B43_MACCTL_GMODE;
2663 macctl |= B43_MACCTL_INFRA;
2664 b43_write32(dev, B43_MMIO_MACCTL, macctl);
2666 err = b43_request_firmware(dev);
2669 err = b43_upload_microcode(dev);
2671 goto out; /* firmware is released later */
2673 err = b43_gpio_init(dev);
2675 goto out; /* firmware is released later */
2677 err = b43_upload_initvals(dev);
2679 goto err_gpio_clean;
2681 /* Turn the Analog on and initialize the PHY. */
2682 phy->ops->switch_analog(dev, 1);
2683 err = b43_phy_init(dev);
2685 goto err_gpio_clean;
2687 /* Disable Interference Mitigation. */
2688 if (phy->ops->interf_mitigation)
2689 phy->ops->interf_mitigation(dev, B43_INTERFMODE_NONE);
2691 /* Select the antennae */
2692 if (phy->ops->set_rx_antenna)
2693 phy->ops->set_rx_antenna(dev, B43_ANTENNA_DEFAULT);
2694 b43_mgmtframe_txantenna(dev, B43_ANTENNA_DEFAULT);
2696 if (phy->type == B43_PHYTYPE_B) {
2697 value16 = b43_read16(dev, 0x005E);
2699 b43_write16(dev, 0x005E, value16);
2701 b43_write32(dev, 0x0100, 0x01000000);
2702 if (dev->dev->id.revision < 5)
2703 b43_write32(dev, 0x010C, 0x01000000);
2705 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2706 & ~B43_MACCTL_INFRA);
2707 b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
2708 | B43_MACCTL_INFRA);
2710 /* Probe Response Timeout value */
2711 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2712 b43_shm_write16(dev, B43_SHM_SHARED, 0x0074, 0x0000);
2714 /* Initially set the wireless operation mode. */
2715 b43_adjust_opmode(dev);
2717 if (dev->dev->id.revision < 3) {
2718 b43_write16(dev, 0x060E, 0x0000);
2719 b43_write16(dev, 0x0610, 0x8000);
2720 b43_write16(dev, 0x0604, 0x0000);
2721 b43_write16(dev, 0x0606, 0x0200);
2723 b43_write32(dev, 0x0188, 0x80000000);
2724 b43_write32(dev, 0x018C, 0x02000000);
2726 b43_write32(dev, B43_MMIO_GEN_IRQ_REASON, 0x00004000);
2727 b43_write32(dev, B43_MMIO_DMA0_IRQ_MASK, 0x0001DC00);
2728 b43_write32(dev, B43_MMIO_DMA1_IRQ_MASK, 0x0000DC00);
2729 b43_write32(dev, B43_MMIO_DMA2_IRQ_MASK, 0x0000DC00);
2730 b43_write32(dev, B43_MMIO_DMA3_IRQ_MASK, 0x0001DC00);
2731 b43_write32(dev, B43_MMIO_DMA4_IRQ_MASK, 0x0000DC00);
2732 b43_write32(dev, B43_MMIO_DMA5_IRQ_MASK, 0x0000DC00);
2734 value32 = ssb_read32(dev->dev, SSB_TMSLOW);
2735 value32 |= 0x00100000;
2736 ssb_write32(dev->dev, SSB_TMSLOW, value32);
2738 b43_write16(dev, B43_MMIO_POWERUP_DELAY,
2739 dev->dev->bus->chipco.fast_pwrup_delay);
2742 b43dbg(dev->wl, "Chip initialized\n");
2747 b43_gpio_cleanup(dev);
2751 static void b43_periodic_every60sec(struct b43_wldev *dev)
2753 const struct b43_phy_operations *ops = dev->phy.ops;
2755 if (ops->pwork_60sec)
2756 ops->pwork_60sec(dev);
2758 /* Force check the TX power emission now. */
2759 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME);
2762 static void b43_periodic_every30sec(struct b43_wldev *dev)
2764 /* Update device statistics. */
2765 b43_calculate_link_quality(dev);
2768 static void b43_periodic_every15sec(struct b43_wldev *dev)
2770 struct b43_phy *phy = &dev->phy;
2773 if (dev->fw.opensource) {
2774 /* Check if the firmware is still alive.
2775 * It will reset the watchdog counter to 0 in its idle loop. */
2776 wdr = b43_shm_read16(dev, B43_SHM_SCRATCH, B43_WATCHDOG_REG);
2777 if (unlikely(wdr)) {
2778 b43err(dev->wl, "Firmware watchdog: The firmware died!\n");
2779 b43_controller_restart(dev, "Firmware watchdog");
2782 b43_shm_write16(dev, B43_SHM_SCRATCH,
2783 B43_WATCHDOG_REG, 1);
2787 if (phy->ops->pwork_15sec)
2788 phy->ops->pwork_15sec(dev);
2790 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
2794 static void do_periodic_work(struct b43_wldev *dev)
2798 state = dev->periodic_state;
2800 b43_periodic_every60sec(dev);
2802 b43_periodic_every30sec(dev);
2803 b43_periodic_every15sec(dev);
2806 /* Periodic work locking policy:
2807 * The whole periodic work handler is protected by
2808 * wl->mutex. If another lock is needed somewhere in the
2809 * pwork callchain, it's aquired in-place, where it's needed.
2811 static void b43_periodic_work_handler(struct work_struct *work)
2813 struct b43_wldev *dev = container_of(work, struct b43_wldev,
2814 periodic_work.work);
2815 struct b43_wl *wl = dev->wl;
2816 unsigned long delay;
2818 mutex_lock(&wl->mutex);
2820 if (unlikely(b43_status(dev) != B43_STAT_STARTED))
2822 if (b43_debug(dev, B43_DBG_PWORK_STOP))
2825 do_periodic_work(dev);
2827 dev->periodic_state++;
2829 if (b43_debug(dev, B43_DBG_PWORK_FAST))
2830 delay = msecs_to_jiffies(50);
2832 delay = round_jiffies_relative(HZ * 15);
2833 queue_delayed_work(wl->hw->workqueue, &dev->periodic_work, delay);
2835 mutex_unlock(&wl->mutex);
2838 static void b43_periodic_tasks_setup(struct b43_wldev *dev)
2840 struct delayed_work *work = &dev->periodic_work;
2842 dev->periodic_state = 0;
2843 INIT_DELAYED_WORK(work, b43_periodic_work_handler);
2844 queue_delayed_work(dev->wl->hw->workqueue, work, 0);
2847 /* Check if communication with the device works correctly. */
2848 static int b43_validate_chipaccess(struct b43_wldev *dev)
2852 backup = b43_shm_read32(dev, B43_SHM_SHARED, 0);
2854 /* Check for read/write and endianness problems. */
2855 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0x55AAAA55);
2856 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0x55AAAA55)
2858 b43_shm_write32(dev, B43_SHM_SHARED, 0, 0xAA5555AA);
2859 if (b43_shm_read32(dev, B43_SHM_SHARED, 0) != 0xAA5555AA)
2862 b43_shm_write32(dev, B43_SHM_SHARED, 0, backup);
2864 if ((dev->dev->id.revision >= 3) && (dev->dev->id.revision <= 10)) {
2865 /* The 32bit register shadows the two 16bit registers
2866 * with update sideeffects. Validate this. */
2867 b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
2868 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0xCCCCBBBB);
2869 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_LOW) != 0xBBBB)
2871 if (b43_read16(dev, B43_MMIO_TSF_CFP_START_HIGH) != 0xCCCC)
2874 b43_write32(dev, B43_MMIO_TSF_CFP_START, 0);
2876 v = b43_read32(dev, B43_MMIO_MACCTL);
2877 v |= B43_MACCTL_GMODE;
2878 if (v != (B43_MACCTL_GMODE | B43_MACCTL_IHR_ENABLED))
2883 b43err(dev->wl, "Failed to validate the chipaccess\n");
2887 static void b43_security_init(struct b43_wldev *dev)
2889 dev->max_nr_keys = (dev->dev->id.revision >= 5) ? 58 : 20;
2890 B43_WARN_ON(dev->max_nr_keys > ARRAY_SIZE(dev->key));
2891 dev->ktp = b43_shm_read16(dev, B43_SHM_SHARED, B43_SHM_SH_KTP);
2892 /* KTP is a word address, but we address SHM bytewise.
2893 * So multiply by two.
2896 if (dev->dev->id.revision >= 5) {
2897 /* Number of RCMTA address slots */
2898 b43_write16(dev, B43_MMIO_RCMTA_COUNT, dev->max_nr_keys - 8);
2900 b43_clear_keys(dev);
2903 static int b43_rng_read(struct hwrng *rng, u32 * data)
2905 struct b43_wl *wl = (struct b43_wl *)rng->priv;
2906 unsigned long flags;
2908 /* Don't take wl->mutex here, as it could deadlock with
2909 * hwrng internal locking. It's not needed to take
2910 * wl->mutex here, anyway. */
2912 spin_lock_irqsave(&wl->irq_lock, flags);
2913 *data = b43_read16(wl->current_dev, B43_MMIO_RNG);
2914 spin_unlock_irqrestore(&wl->irq_lock, flags);
2916 return (sizeof(u16));
2919 static void b43_rng_exit(struct b43_wl *wl)
2921 if (wl->rng_initialized)
2922 hwrng_unregister(&wl->rng);
2925 static int b43_rng_init(struct b43_wl *wl)
2929 snprintf(wl->rng_name, ARRAY_SIZE(wl->rng_name),
2930 "%s_%s", KBUILD_MODNAME, wiphy_name(wl->hw->wiphy));
2931 wl->rng.name = wl->rng_name;
2932 wl->rng.data_read = b43_rng_read;
2933 wl->rng.priv = (unsigned long)wl;
2934 wl->rng_initialized = 1;
2935 err = hwrng_register(&wl->rng);
2937 wl->rng_initialized = 0;
2938 b43err(wl, "Failed to register the random "
2939 "number generator (%d)\n", err);
2945 static int b43_op_tx(struct ieee80211_hw *hw,
2946 struct sk_buff *skb)
2948 struct b43_wl *wl = hw_to_b43_wl(hw);
2949 struct b43_wldev *dev = wl->current_dev;
2950 unsigned long flags;
2953 if (unlikely(skb->len < 2 + 2 + 6)) {
2954 /* Too short, this can't be a valid frame. */
2957 B43_WARN_ON(skb_shinfo(skb)->nr_frags);
2961 /* Transmissions on seperate queues can run concurrently. */
2962 read_lock_irqsave(&wl->tx_lock, flags);
2965 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
2966 if (b43_using_pio_transfers(dev))
2967 err = b43_pio_tx(dev, skb);
2969 err = b43_dma_tx(dev, skb);
2972 read_unlock_irqrestore(&wl->tx_lock, flags);
2976 return NETDEV_TX_OK;
2979 /* We can not transmit this packet. Drop it. */
2980 dev_kfree_skb_any(skb);
2981 return NETDEV_TX_OK;
2984 /* Locking: wl->irq_lock */
2985 static void b43_qos_params_upload(struct b43_wldev *dev,
2986 const struct ieee80211_tx_queue_params *p,
2989 u16 params[B43_NR_QOSPARAMS];
2993 bslots = b43_read16(dev, B43_MMIO_RNG) & p->cw_min;
2995 memset(¶ms, 0, sizeof(params));
2997 params[B43_QOSPARAM_TXOP] = p->txop * 32;
2998 params[B43_QOSPARAM_CWMIN] = p->cw_min;
2999 params[B43_QOSPARAM_CWMAX] = p->cw_max;
3000 params[B43_QOSPARAM_CWCUR] = p->cw_min;
3001 params[B43_QOSPARAM_AIFS] = p->aifs;
3002 params[B43_QOSPARAM_BSLOTS] = bslots;
3003 params[B43_QOSPARAM_REGGAP] = bslots + p->aifs;
3005 for (i = 0; i < ARRAY_SIZE(params); i++) {
3006 if (i == B43_QOSPARAM_STATUS) {
3007 tmp = b43_shm_read16(dev, B43_SHM_SHARED,
3008 shm_offset + (i * 2));
3009 /* Mark the parameters as updated. */
3011 b43_shm_write16(dev, B43_SHM_SHARED,
3012 shm_offset + (i * 2),
3015 b43_shm_write16(dev, B43_SHM_SHARED,
3016 shm_offset + (i * 2),
3022 /* Mapping of mac80211 queue numbers to b43 QoS SHM offsets. */
3023 static const u16 b43_qos_shm_offsets[] = {
3024 /* [mac80211-queue-nr] = SHM_OFFSET, */
3025 [0] = B43_QOS_VOICE,
3026 [1] = B43_QOS_VIDEO,
3027 [2] = B43_QOS_BESTEFFORT,
3028 [3] = B43_QOS_BACKGROUND,
3031 /* Update all QOS parameters in hardware. */
3032 static void b43_qos_upload_all(struct b43_wldev *dev)
3034 struct b43_wl *wl = dev->wl;
3035 struct b43_qos_params *params;
3038 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3039 ARRAY_SIZE(wl->qos_params));
3041 b43_mac_suspend(dev);
3042 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3043 params = &(wl->qos_params[i]);
3044 b43_qos_params_upload(dev, &(params->p),
3045 b43_qos_shm_offsets[i]);
3047 b43_mac_enable(dev);
3050 static void b43_qos_clear(struct b43_wl *wl)
3052 struct b43_qos_params *params;
3055 /* Initialize QoS parameters to sane defaults. */
3057 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3058 ARRAY_SIZE(wl->qos_params));
3060 for (i = 0; i < ARRAY_SIZE(wl->qos_params); i++) {
3061 params = &(wl->qos_params[i]);
3063 switch (b43_qos_shm_offsets[i]) {
3067 params->p.cw_min = 0x0001;
3068 params->p.cw_max = 0x0001;
3073 params->p.cw_min = 0x0001;
3074 params->p.cw_max = 0x0001;
3076 case B43_QOS_BESTEFFORT:
3079 params->p.cw_min = 0x0001;
3080 params->p.cw_max = 0x03FF;
3082 case B43_QOS_BACKGROUND:
3085 params->p.cw_min = 0x0001;
3086 params->p.cw_max = 0x03FF;
3094 /* Initialize the core's QOS capabilities */
3095 static void b43_qos_init(struct b43_wldev *dev)
3097 /* Upload the current QOS parameters. */
3098 b43_qos_upload_all(dev);
3100 /* Enable QOS support. */
3101 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_EDCF);
3102 b43_write16(dev, B43_MMIO_IFSCTL,
3103 b43_read16(dev, B43_MMIO_IFSCTL)
3104 | B43_MMIO_IFSCTL_USE_EDCF);
3107 static int b43_op_conf_tx(struct ieee80211_hw *hw, u16 _queue,
3108 const struct ieee80211_tx_queue_params *params)
3110 struct b43_wl *wl = hw_to_b43_wl(hw);
3111 struct b43_wldev *dev;
3112 unsigned int queue = (unsigned int)_queue;
3115 if (queue >= ARRAY_SIZE(wl->qos_params)) {
3116 /* Queue not available or don't support setting
3117 * params on this queue. Return success to not
3118 * confuse mac80211. */
3121 BUILD_BUG_ON(ARRAY_SIZE(b43_qos_shm_offsets) !=
3122 ARRAY_SIZE(wl->qos_params));
3124 mutex_lock(&wl->mutex);
3125 dev = wl->current_dev;
3126 if (unlikely(!dev || (b43_status(dev) < B43_STAT_INITIALIZED)))
3129 memcpy(&(wl->qos_params[queue].p), params, sizeof(*params));
3130 b43_mac_suspend(dev);
3131 b43_qos_params_upload(dev, &(wl->qos_params[queue].p),
3132 b43_qos_shm_offsets[queue]);
3133 b43_mac_enable(dev);
3137 mutex_unlock(&wl->mutex);
3142 static int b43_op_get_tx_stats(struct ieee80211_hw *hw,
3143 struct ieee80211_tx_queue_stats *stats)
3145 struct b43_wl *wl = hw_to_b43_wl(hw);
3146 struct b43_wldev *dev = wl->current_dev;
3147 unsigned long flags;
3152 spin_lock_irqsave(&wl->irq_lock, flags);
3153 if (likely(b43_status(dev) >= B43_STAT_STARTED)) {
3154 if (b43_using_pio_transfers(dev))
3155 b43_pio_get_tx_stats(dev, stats);
3157 b43_dma_get_tx_stats(dev, stats);
3160 spin_unlock_irqrestore(&wl->irq_lock, flags);
3165 static int b43_op_get_stats(struct ieee80211_hw *hw,
3166 struct ieee80211_low_level_stats *stats)
3168 struct b43_wl *wl = hw_to_b43_wl(hw);
3169 unsigned long flags;
3171 spin_lock_irqsave(&wl->irq_lock, flags);
3172 memcpy(stats, &wl->ieee_stats, sizeof(*stats));
3173 spin_unlock_irqrestore(&wl->irq_lock, flags);
3178 static void b43_put_phy_into_reset(struct b43_wldev *dev)
3180 struct ssb_device *sdev = dev->dev;
3183 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3184 tmslow &= ~B43_TMSLOW_GMODE;
3185 tmslow |= B43_TMSLOW_PHYRESET;
3186 tmslow |= SSB_TMSLOW_FGC;
3187 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3190 tmslow = ssb_read32(sdev, SSB_TMSLOW);
3191 tmslow &= ~SSB_TMSLOW_FGC;
3192 tmslow |= B43_TMSLOW_PHYRESET;
3193 ssb_write32(sdev, SSB_TMSLOW, tmslow);
3197 static const char * band_to_string(enum ieee80211_band band)
3200 case IEEE80211_BAND_5GHZ:
3202 case IEEE80211_BAND_2GHZ:
3211 /* Expects wl->mutex locked */
3212 static int b43_switch_band(struct b43_wl *wl, struct ieee80211_channel *chan)
3214 struct b43_wldev *up_dev = NULL;
3215 struct b43_wldev *down_dev;
3216 struct b43_wldev *d;
3221 /* Find a device and PHY which supports the band. */
3222 list_for_each_entry(d, &wl->devlist, list) {
3223 switch (chan->band) {
3224 case IEEE80211_BAND_5GHZ:
3225 if (d->phy.supports_5ghz) {
3230 case IEEE80211_BAND_2GHZ:
3231 if (d->phy.supports_2ghz) {
3244 b43err(wl, "Could not find a device for %s-GHz band operation\n",
3245 band_to_string(chan->band));
3248 if ((up_dev == wl->current_dev) &&
3249 (!!wl->current_dev->phy.gmode == !!gmode)) {
3250 /* This device is already running. */
3253 b43dbg(wl, "Switching to %s-GHz band\n",
3254 band_to_string(chan->band));
3255 down_dev = wl->current_dev;
3257 prev_status = b43_status(down_dev);
3258 /* Shutdown the currently running core. */
3259 if (prev_status >= B43_STAT_STARTED)
3260 b43_wireless_core_stop(down_dev);
3261 if (prev_status >= B43_STAT_INITIALIZED)
3262 b43_wireless_core_exit(down_dev);
3264 if (down_dev != up_dev) {
3265 /* We switch to a different core, so we put PHY into
3266 * RESET on the old core. */
3267 b43_put_phy_into_reset(down_dev);
3270 /* Now start the new core. */
3271 up_dev->phy.gmode = gmode;
3272 if (prev_status >= B43_STAT_INITIALIZED) {
3273 err = b43_wireless_core_init(up_dev);
3275 b43err(wl, "Fatal: Could not initialize device for "
3276 "selected %s-GHz band\n",
3277 band_to_string(chan->band));
3281 if (prev_status >= B43_STAT_STARTED) {
3282 err = b43_wireless_core_start(up_dev);
3284 b43err(wl, "Fatal: Coult not start device for "
3285 "selected %s-GHz band\n",
3286 band_to_string(chan->band));
3287 b43_wireless_core_exit(up_dev);
3291 B43_WARN_ON(b43_status(up_dev) != prev_status);
3293 wl->current_dev = up_dev;
3297 /* Whoops, failed to init the new core. No core is operating now. */
3298 wl->current_dev = NULL;
3302 /* Write the short and long frame retry limit values. */
3303 static void b43_set_retry_limits(struct b43_wldev *dev,
3304 unsigned int short_retry,
3305 unsigned int long_retry)
3307 /* The retry limit is a 4-bit counter. Enforce this to avoid overflowing
3308 * the chip-internal counter. */
3309 short_retry = min(short_retry, (unsigned int)0xF);
3310 long_retry = min(long_retry, (unsigned int)0xF);
3312 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_SRLIMIT,
3314 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_LRLIMIT,
3318 static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
3320 struct b43_wl *wl = hw_to_b43_wl(hw);
3321 struct b43_wldev *dev;
3322 struct b43_phy *phy;
3323 struct ieee80211_conf *conf = &hw->conf;
3324 unsigned long flags;
3328 mutex_lock(&wl->mutex);
3330 /* Switch the band (if necessary). This might change the active core. */
3331 err = b43_switch_band(wl, conf->channel);
3333 goto out_unlock_mutex;
3334 dev = wl->current_dev;
3337 b43_mac_suspend(dev);
3339 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
3340 b43_set_retry_limits(dev, conf->short_frame_max_tx_count,
3341 conf->long_frame_max_tx_count);
3342 changed &= ~IEEE80211_CONF_CHANGE_RETRY_LIMITS;
3344 goto out_mac_enable;
3346 /* Switch to the requested channel.
3347 * The firmware takes care of races with the TX handler. */
3348 if (conf->channel->hw_value != phy->channel)
3349 b43_switch_channel(dev, conf->channel->hw_value);
3351 dev->wl->radiotap_enabled = !!(conf->flags & IEEE80211_CONF_RADIOTAP);
3353 /* Adjust the desired TX power level. */
3354 if (conf->power_level != 0) {
3355 spin_lock_irqsave(&wl->irq_lock, flags);
3356 if (conf->power_level != phy->desired_txpower) {
3357 phy->desired_txpower = conf->power_level;
3358 b43_phy_txpower_check(dev, B43_TXPWR_IGNORE_TIME |
3359 B43_TXPWR_IGNORE_TSSI);
3361 spin_unlock_irqrestore(&wl->irq_lock, flags);
3364 /* Antennas for RX and management frame TX. */
3365 antenna = B43_ANTENNA_DEFAULT;
3366 b43_mgmtframe_txantenna(dev, antenna);
3367 antenna = B43_ANTENNA_DEFAULT;
3368 if (phy->ops->set_rx_antenna)
3369 phy->ops->set_rx_antenna(dev, antenna);
3371 /* Update templates for AP/mesh mode. */
3372 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3373 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT))
3374 b43_set_beacon_int(dev, conf->beacon_int);
3376 if (!!conf->radio_enabled != phy->radio_on) {
3377 if (conf->radio_enabled) {
3378 b43_software_rfkill(dev, RFKILL_STATE_UNBLOCKED);
3379 b43info(dev->wl, "Radio turned on by software\n");
3380 if (!dev->radio_hw_enable) {
3381 b43info(dev->wl, "The hardware RF-kill button "
3382 "still turns the radio physically off. "
3383 "Press the button to turn it on.\n");
3386 b43_software_rfkill(dev, RFKILL_STATE_SOFT_BLOCKED);
3387 b43info(dev->wl, "Radio turned off by software\n");
3392 b43_mac_enable(dev);
3394 mutex_unlock(&wl->mutex);
3399 static void b43_update_basic_rates(struct b43_wldev *dev, u64 brates)
3401 struct ieee80211_supported_band *sband =
3402 dev->wl->hw->wiphy->bands[b43_current_band(dev->wl)];
3403 struct ieee80211_rate *rate;
3405 u16 basic, direct, offset, basic_offset, rateptr;
3407 for (i = 0; i < sband->n_bitrates; i++) {
3408 rate = &sband->bitrates[i];
3410 if (b43_is_cck_rate(rate->hw_value)) {
3411 direct = B43_SHM_SH_CCKDIRECT;
3412 basic = B43_SHM_SH_CCKBASIC;
3413 offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3416 direct = B43_SHM_SH_OFDMDIRECT;
3417 basic = B43_SHM_SH_OFDMBASIC;
3418 offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3422 rate = ieee80211_get_response_rate(sband, brates, rate->bitrate);
3424 if (b43_is_cck_rate(rate->hw_value)) {
3425 basic_offset = b43_plcp_get_ratecode_cck(rate->hw_value);
3426 basic_offset &= 0xF;
3428 basic_offset = b43_plcp_get_ratecode_ofdm(rate->hw_value);
3429 basic_offset &= 0xF;
3433 * Get the pointer that we need to point to
3434 * from the direct map
3436 rateptr = b43_shm_read16(dev, B43_SHM_SHARED,
3437 direct + 2 * basic_offset);
3438 /* and write it to the basic map */
3439 b43_shm_write16(dev, B43_SHM_SHARED, basic + 2 * offset,
3444 static void b43_op_bss_info_changed(struct ieee80211_hw *hw,
3445 struct ieee80211_vif *vif,
3446 struct ieee80211_bss_conf *conf,
3449 struct b43_wl *wl = hw_to_b43_wl(hw);
3450 struct b43_wldev *dev;
3452 mutex_lock(&wl->mutex);
3454 dev = wl->current_dev;
3455 if (!dev || b43_status(dev) < B43_STAT_STARTED)
3456 goto out_unlock_mutex;
3457 b43_mac_suspend(dev);
3459 if (changed & BSS_CHANGED_BASIC_RATES)
3460 b43_update_basic_rates(dev, conf->basic_rates);
3462 if (changed & BSS_CHANGED_ERP_SLOT) {
3463 if (conf->use_short_slot)
3464 b43_short_slot_timing_enable(dev);
3466 b43_short_slot_timing_disable(dev);
3469 b43_mac_enable(dev);
3471 mutex_unlock(&wl->mutex);
3476 static int b43_op_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3477 const u8 *local_addr, const u8 *addr,
3478 struct ieee80211_key_conf *key)
3480 struct b43_wl *wl = hw_to_b43_wl(hw);
3481 struct b43_wldev *dev;
3482 unsigned long flags;
3487 if (modparam_nohwcrypt)
3488 return -ENOSPC; /* User disabled HW-crypto */
3490 mutex_lock(&wl->mutex);
3491 spin_lock_irqsave(&wl->irq_lock, flags);
3493 dev = wl->current_dev;
3495 if (!dev || b43_status(dev) < B43_STAT_INITIALIZED)
3498 if (dev->fw.pcm_request_failed) {
3499 /* We don't have firmware for the crypto engine.
3500 * Must use software-crypto. */
3508 if (key->keylen == 5)
3509 algorithm = B43_SEC_ALGO_WEP40;
3511 algorithm = B43_SEC_ALGO_WEP104;
3514 algorithm = B43_SEC_ALGO_TKIP;
3517 algorithm = B43_SEC_ALGO_AES;
3523 index = (u8) (key->keyidx);
3529 if (algorithm == B43_SEC_ALGO_TKIP) {
3530 /* FIXME: No TKIP hardware encryption for now. */
3535 if (is_broadcast_ether_addr(addr)) {
3536 /* addr is FF:FF:FF:FF:FF:FF for default keys */
3537 err = b43_key_write(dev, index, algorithm,
3538 key->key, key->keylen, NULL, key);
3541 * either pairwise key or address is 00:00:00:00:00:00
3542 * for transmit-only keys
3544 err = b43_key_write(dev, -1, algorithm,
3545 key->key, key->keylen, addr, key);
3550 if (algorithm == B43_SEC_ALGO_WEP40 ||
3551 algorithm == B43_SEC_ALGO_WEP104) {
3552 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_USEDEFKEYS);
3555 b43_hf_read(dev) & ~B43_HF_USEDEFKEYS);
3557 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
3560 err = b43_key_clear(dev, key->hw_key_idx);
3569 spin_unlock_irqrestore(&wl->irq_lock, flags);
3570 mutex_unlock(&wl->mutex);
3572 b43dbg(wl, "%s hardware based encryption for keyidx: %d, "
3574 cmd == SET_KEY ? "Using" : "Disabling", key->keyidx,
3580 static void b43_op_configure_filter(struct ieee80211_hw *hw,
3581 unsigned int changed, unsigned int *fflags,
3582 int mc_count, struct dev_addr_list *mc_list)
3584 struct b43_wl *wl = hw_to_b43_wl(hw);
3585 struct b43_wldev *dev = wl->current_dev;
3586 unsigned long flags;
3593 spin_lock_irqsave(&wl->irq_lock, flags);
3594 *fflags &= FIF_PROMISC_IN_BSS |
3600 FIF_BCN_PRBRESP_PROMISC;
3602 changed &= FIF_PROMISC_IN_BSS |
3608 FIF_BCN_PRBRESP_PROMISC;
3610 wl->filter_flags = *fflags;
3612 if (changed && b43_status(dev) >= B43_STAT_INITIALIZED)
3613 b43_adjust_opmode(dev);
3614 spin_unlock_irqrestore(&wl->irq_lock, flags);
3617 static int b43_op_config_interface(struct ieee80211_hw *hw,
3618 struct ieee80211_vif *vif,
3619 struct ieee80211_if_conf *conf)
3621 struct b43_wl *wl = hw_to_b43_wl(hw);
3622 struct b43_wldev *dev = wl->current_dev;
3623 unsigned long flags;
3627 mutex_lock(&wl->mutex);
3628 spin_lock_irqsave(&wl->irq_lock, flags);
3629 B43_WARN_ON(wl->vif != vif);
3631 memcpy(wl->bssid, conf->bssid, ETH_ALEN);
3633 memset(wl->bssid, 0, ETH_ALEN);
3634 if (b43_status(dev) >= B43_STAT_INITIALIZED) {
3635 if (b43_is_mode(wl, NL80211_IFTYPE_AP) ||
3636 b43_is_mode(wl, NL80211_IFTYPE_MESH_POINT)) {
3637 B43_WARN_ON(vif->type != wl->if_type);
3638 if (conf->changed & IEEE80211_IFCC_BEACON)
3639 b43_update_templates(wl);
3640 } else if (b43_is_mode(wl, NL80211_IFTYPE_ADHOC)) {
3641 if (conf->changed & IEEE80211_IFCC_BEACON)
3642 b43_update_templates(wl);
3644 b43_write_mac_bssid_templates(dev);
3646 spin_unlock_irqrestore(&wl->irq_lock, flags);
3647 mutex_unlock(&wl->mutex);
3652 /* Locking: wl->mutex */
3653 static void b43_wireless_core_stop(struct b43_wldev *dev)
3655 struct b43_wl *wl = dev->wl;
3656 unsigned long flags;
3658 if (b43_status(dev) < B43_STAT_STARTED)
3661 /* Disable and sync interrupts. We must do this before than
3662 * setting the status to INITIALIZED, as the interrupt handler
3663 * won't care about IRQs then. */
3664 spin_lock_irqsave(&wl->irq_lock, flags);
3665 dev->irq_savedstate = b43_interrupt_disable(dev, B43_IRQ_ALL);
3666 b43_read32(dev, B43_MMIO_GEN_IRQ_MASK); /* flush */
3667 spin_unlock_irqrestore(&wl->irq_lock, flags);
3668 b43_synchronize_irq(dev);
3670 write_lock_irqsave(&wl->tx_lock, flags);
3671 b43_set_status(dev, B43_STAT_INITIALIZED);
3672 write_unlock_irqrestore(&wl->tx_lock, flags);
3675 mutex_unlock(&wl->mutex);
3676 /* Must unlock as it would otherwise deadlock. No races here.
3677 * Cancel the possibly running self-rearming periodic work. */
3678 cancel_delayed_work_sync(&dev->periodic_work);
3679 mutex_lock(&wl->mutex);
3681 b43_mac_suspend(dev);
3682 free_irq(dev->dev->irq, dev);
3683 b43dbg(wl, "Wireless interface stopped\n");
3686 /* Locking: wl->mutex */
3687 static int b43_wireless_core_start(struct b43_wldev *dev)
3691 B43_WARN_ON(b43_status(dev) != B43_STAT_INITIALIZED);
3693 drain_txstatus_queue(dev);
3694 err = request_irq(dev->dev->irq, b43_interrupt_handler,
3695 IRQF_SHARED, KBUILD_MODNAME, dev);
3697 b43err(dev->wl, "Cannot request IRQ-%d\n", dev->dev->irq);
3701 /* We are ready to run. */
3702 b43_set_status(dev, B43_STAT_STARTED);
3704 /* Start data flow (TX/RX). */
3705 b43_mac_enable(dev);
3706 b43_interrupt_enable(dev, dev->irq_savedstate);
3708 /* Start maintainance work */
3709 b43_periodic_tasks_setup(dev);
3711 b43dbg(dev->wl, "Wireless interface started\n");
3716 /* Get PHY and RADIO versioning numbers */
3717 static int b43_phy_versioning(struct b43_wldev *dev)
3719 struct b43_phy *phy = &dev->phy;
3727 int unsupported = 0;
3729 /* Get PHY versioning */
3730 tmp = b43_read16(dev, B43_MMIO_PHY_VER);
3731 analog_type = (tmp & B43_PHYVER_ANALOG) >> B43_PHYVER_ANALOG_SHIFT;
3732 phy_type = (tmp & B43_PHYVER_TYPE) >> B43_PHYVER_TYPE_SHIFT;
3733 phy_rev = (tmp & B43_PHYVER_VERSION);
3740 if (phy_rev != 2 && phy_rev != 4 && phy_rev != 6
3748 #ifdef CONFIG_B43_NPHY
3758 b43err(dev->wl, "FOUND UNSUPPORTED PHY "
3759 "(Analog %u, Type %u, Revision %u)\n",
3760 analog_type, phy_type, phy_rev);
3763 b43dbg(dev->wl, "Found PHY: Analog %u, Type %u, Revision %u\n",
3764 analog_type, phy_type, phy_rev);
3766 /* Get RADIO versioning */
3767 if (dev->dev->bus->chip_id == 0x4317) {
3768 if (dev->dev->bus->chip_rev == 0)
3770 else if (dev->dev->bus->chip_rev == 1)
3775 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3776 tmp = b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3777 b43_write16(dev, B43_MMIO_RADIO_CONTROL, B43_RADIOCTL_ID);
3778 tmp |= (u32)b43_read16(dev, B43_MMIO_RADIO_DATA_HIGH) << 16;
3780 radio_manuf = (tmp & 0x00000FFF);
3781 radio_ver = (tmp & 0x0FFFF000) >> 12;
3782 radio_rev = (tmp & 0xF0000000) >> 28;
3783 if (radio_manuf != 0x17F /* Broadcom */)
3787 if (radio_ver != 0x2060)
3791 if (radio_manuf != 0x17F)
3795 if ((radio_ver & 0xFFF0) != 0x2050)
3799 if (radio_ver != 0x2050)
3803 if (radio_ver != 0x2055)
3810 b43err(dev->wl, "FOUND UNSUPPORTED RADIO "
3811 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3812 radio_manuf, radio_ver, radio_rev);
3815 b43dbg(dev->wl, "Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3816 radio_manuf, radio_ver, radio_rev);
3818 phy->radio_manuf = radio_manuf;
3819 phy->radio_ver = radio_ver;
3820 phy->radio_rev = radio_rev;
3822 phy->analog = analog_type;
3823 phy->type = phy_type;
3829 static void setup_struct_phy_for_init(struct b43_wldev *dev,
3830 struct b43_phy *phy)
3832 phy->hardware_power_control = !!modparam_hwpctl;
3833 phy->next_txpwr_check_time = jiffies;
3834 /* PHY TX errors counter. */
3835 atomic_set(&phy->txerr_cnt, B43_PHY_TX_BADNESS_LIMIT);
3838 static void setup_struct_wldev_for_init(struct b43_wldev *dev)
3842 /* Assume the radio is enabled. If it's not enabled, the state will
3843 * immediately get fixed on the first periodic work run. */
3844 dev->radio_hw_enable = 1;
3847 memset(&dev->stats, 0, sizeof(dev->stats));
3849 setup_struct_phy_for_init(dev, &dev->phy);
3851 /* IRQ related flags */
3852 dev->irq_reason = 0;
3853 memset(dev->dma_reason, 0, sizeof(dev->dma_reason));
3854 dev->irq_savedstate = B43_IRQ_MASKTEMPLATE;
3856 dev->mac_suspended = 1;
3858 /* Noise calculation context */
3859 memset(&dev->noisecalc, 0, sizeof(dev->noisecalc));
3862 static void b43_bluetooth_coext_enable(struct b43_wldev *dev)
3864 struct ssb_sprom *sprom = &dev->dev->bus->sprom;
3867 if (!modparam_btcoex)
3869 if (!(sprom->boardflags_lo & B43_BFL_BTCOEXIST))
3871 if (dev->phy.type != B43_PHYTYPE_B && !dev->phy.gmode)
3874 hf = b43_hf_read(dev);
3875 if (sprom->boardflags_lo & B43_BFL_BTCMOD)
3876 hf |= B43_HF_BTCOEXALT;
3878 hf |= B43_HF_BTCOEX;
3879 b43_hf_write(dev, hf);
3882 static void b43_bluetooth_coext_disable(struct b43_wldev *dev)
3884 if (!modparam_btcoex)
3889 static void b43_imcfglo_timeouts_workaround(struct b43_wldev *dev)
3891 #ifdef CONFIG_SSB_DRIVER_PCICORE
3892 struct ssb_bus *bus = dev->dev->bus;
3895 if (bus->pcicore.dev &&
3896 bus->pcicore.dev->id.coreid == SSB_DEV_PCI &&
3897 bus->pcicore.dev->id.revision <= 5) {
3898 /* IMCFGLO timeouts workaround. */
3899 tmp = ssb_read32(dev->dev, SSB_IMCFGLO);
3900 tmp &= ~SSB_IMCFGLO_REQTO;
3901 tmp &= ~SSB_IMCFGLO_SERTO;
3902 switch (bus->bustype) {
3903 case SSB_BUSTYPE_PCI:
3904 case SSB_BUSTYPE_PCMCIA:
3907 case SSB_BUSTYPE_SSB:
3911 ssb_write32(dev->dev, SSB_IMCFGLO, tmp);
3913 #endif /* CONFIG_SSB_DRIVER_PCICORE */
3916 static void b43_set_synth_pu_delay(struct b43_wldev *dev, bool idle)
3920 /* The time value is in microseconds. */
3921 if (dev->phy.type == B43_PHYTYPE_A)
3925 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC) || idle)
3927 if ((dev->phy.radio_ver == 0x2050) && (dev->phy.radio_rev == 8))
3928 pu_delay = max(pu_delay, (u16)2400);
3930 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SPUWKUP, pu_delay);
3933 /* Set the TSF CFP pre-TargetBeaconTransmissionTime. */
3934 static void b43_set_pretbtt(struct b43_wldev *dev)
3938 /* The time value is in microseconds. */
3939 if (b43_is_mode(dev->wl, NL80211_IFTYPE_ADHOC)) {
3942 if (dev->phy.type == B43_PHYTYPE_A)
3947 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRETBTT, pretbtt);
3948 b43_write16(dev, B43_MMIO_TSF_CFP_PRETBTT, pretbtt);
3951 /* Shutdown a wireless core */
3952 /* Locking: wl->mutex */
3953 static void b43_wireless_core_exit(struct b43_wldev *dev)
3957 B43_WARN_ON(b43_status(dev) > B43_STAT_INITIALIZED);
3958 if (b43_status(dev) != B43_STAT_INITIALIZED)
3960 b43_set_status(dev, B43_STAT_UNINIT);
3962 /* Stop the microcode PSM. */
3963 macctl = b43_read32(dev, B43_MMIO_MACCTL);
3964 macctl &= ~B43_MACCTL_PSM_RUN;
3965 macctl |= B43_MACCTL_PSM_JMP0;
3966 b43_write32(dev, B43_MMIO_MACCTL, macctl);
3968 if (!dev->suspend_in_progress) {
3970 b43_rng_exit(dev->wl);
3975 dev->phy.ops->switch_analog(dev, 0);
3976 if (dev->wl->current_beacon) {
3977 dev_kfree_skb_any(dev->wl->current_beacon);
3978 dev->wl->current_beacon = NULL;
3981 ssb_device_disable(dev->dev, 0);
3982 ssb_bus_may_powerdown(dev->dev->bus);
3985 /* Initialize a wireless core */
3986 static int b43_wireless_core_init(struct b43_wldev *dev)
3988 struct b43_wl *wl = dev->wl;
3989 struct ssb_bus *bus = dev->dev->bus;
3990 struct ssb_sprom *sprom = &bus->sprom;
3991 struct b43_phy *phy = &dev->phy;
3996 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
3998 err = ssb_bus_powerup(bus, 0);
4001 if (!ssb_device_is_enabled(dev->dev)) {
4002 tmp = phy->gmode ? B43_TMSLOW_GMODE : 0;
4003 b43_wireless_core_reset(dev, tmp);
4006 /* Reset all data structures. */
4007 setup_struct_wldev_for_init(dev);
4008 phy->ops->prepare_structs(dev);
4010 /* Enable IRQ routing to this device. */
4011 ssb_pcicore_dev_irqvecs_enable(&bus->pcicore, dev->dev);
4013 b43_imcfglo_timeouts_workaround(dev);
4014 b43_bluetooth_coext_disable(dev);
4015 if (phy->ops->prepare_hardware) {
4016 err = phy->ops->prepare_hardware(dev);
4020 err = b43_chip_init(dev);
4023 b43_shm_write16(dev, B43_SHM_SHARED,
4024 B43_SHM_SH_WLCOREREV, dev->dev->id.revision);
4025 hf = b43_hf_read(dev);
4026 if (phy->type == B43_PHYTYPE_G) {
4030 if (sprom->boardflags_lo & B43_BFL_PACTRL)
4031 hf |= B43_HF_OFDMPABOOST;
4032 } else if (phy->type == B43_PHYTYPE_B) {
4034 if (phy->rev >= 2 && phy->radio_ver == 0x2050)
4037 b43_hf_write(dev, hf);
4039 b43_set_retry_limits(dev, B43_DEFAULT_SHORT_RETRY_LIMIT,
4040 B43_DEFAULT_LONG_RETRY_LIMIT);
4041 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_SFFBLIM, 3);
4042 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_LFFBLIM, 2);
4044 /* Disable sending probe responses from firmware.
4045 * Setting the MaxTime to one usec will always trigger
4046 * a timeout, so we never send any probe resp.
4047 * A timeout of zero is infinite. */
4048 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_PRMAXTIME, 1);
4050 b43_rate_memory_init(dev);
4051 b43_set_phytxctl_defaults(dev);
4053 /* Minimum Contention Window */
4054 if (phy->type == B43_PHYTYPE_B) {
4055 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0x1F);
4057 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MINCONT, 0xF);
4059 /* Maximum Contention Window */
4060 b43_shm_write16(dev, B43_SHM_SCRATCH, B43_SHM_SC_MAXCONT, 0x3FF);
4062 if ((dev->dev->bus->bustype == SSB_BUSTYPE_PCMCIA) || B43_FORCE_PIO) {
4063 dev->__using_pio_transfers = 1;
4064 err = b43_pio_init(dev);
4066 dev->__using_pio_transfers = 0;
4067 err = b43_dma_init(dev);
4072 b43_set_synth_pu_delay(dev, 1);
4073 b43_bluetooth_coext_enable(dev);
4075 ssb_bus_powerup(bus, 1); /* Enable dynamic PCTL */
4076 b43_upload_card_macaddress(dev);
4077 b43_security_init(dev);
4078 if (!dev->suspend_in_progress)
4081 b43_set_status(dev, B43_STAT_INITIALIZED);
4083 if (!dev->suspend_in_progress)
4091 ssb_bus_may_powerdown(bus);
4092 B43_WARN_ON(b43_status(dev) != B43_STAT_UNINIT);
4096 static int b43_op_add_interface(struct ieee80211_hw *hw,
4097 struct ieee80211_if_init_conf *conf)
4099 struct b43_wl *wl = hw_to_b43_wl(hw);
4100 struct b43_wldev *dev;
4101 unsigned long flags;
4102 int err = -EOPNOTSUPP;
4104 /* TODO: allow WDS/AP devices to coexist */
4106 if (conf->type != NL80211_IFTYPE_AP &&
4107 conf->type != NL80211_IFTYPE_MESH_POINT &&
4108 conf->type != NL80211_IFTYPE_STATION &&
4109 conf->type != NL80211_IFTYPE_WDS &&
4110 conf->type != NL80211_IFTYPE_ADHOC)
4113 mutex_lock(&wl->mutex);
4115 goto out_mutex_unlock;
4117 b43dbg(wl, "Adding Interface type %d\n", conf->type);
4119 dev = wl->current_dev;
4121 wl->vif = conf->vif;
4122 wl->if_type = conf->type;
4123 memcpy(wl->mac_addr, conf->mac_addr, ETH_ALEN);
4125 spin_lock_irqsave(&wl->irq_lock, flags);
4126 b43_adjust_opmode(dev);
4127 b43_set_pretbtt(dev);
4128 b43_set_synth_pu_delay(dev, 0);
4129 b43_upload_card_macaddress(dev);
4130 spin_unlock_irqrestore(&wl->irq_lock, flags);
4134 mutex_unlock(&wl->mutex);
4139 static void b43_op_remove_interface(struct ieee80211_hw *hw,
4140 struct ieee80211_if_init_conf *conf)
4142 struct b43_wl *wl = hw_to_b43_wl(hw);
4143 struct b43_wldev *dev = wl->current_dev;
4144 unsigned long flags;
4146 b43dbg(wl, "Removing Interface type %d\n", conf->type);
4148 mutex_lock(&wl->mutex);
4150 B43_WARN_ON(!wl->operating);
4151 B43_WARN_ON(wl->vif != conf->vif);
4156 spin_lock_irqsave(&wl->irq_lock, flags);
4157 b43_adjust_opmode(dev);
4158 memset(wl->mac_addr, 0, ETH_ALEN);
4159 b43_upload_card_macaddress(dev);
4160 spin_unlock_irqrestore(&wl->irq_lock, flags);
4162 mutex_unlock(&wl->mutex);
4165 static int b43_op_start(struct ieee80211_hw *hw)
4167 struct b43_wl *wl = hw_to_b43_wl(hw);
4168 struct b43_wldev *dev = wl->current_dev;
4171 bool do_rfkill_exit = 0;
4173 /* Kill all old instance specific information to make sure
4174 * the card won't use it in the short timeframe between start
4175 * and mac80211 reconfiguring it. */
4176 memset(wl->bssid, 0, ETH_ALEN);
4177 memset(wl->mac_addr, 0, ETH_ALEN);
4178 wl->filter_flags = 0;
4179 wl->radiotap_enabled = 0;
4181 wl->beacon0_uploaded = 0;
4182 wl->beacon1_uploaded = 0;
4183 wl->beacon_templates_virgin = 1;
4185 /* First register RFkill.
4186 * LEDs that are registered later depend on it. */
4187 b43_rfkill_init(dev);
4189 mutex_lock(&wl->mutex);
4191 if (b43_status(dev) < B43_STAT_INITIALIZED) {
4192 err = b43_wireless_core_init(dev);
4195 goto out_mutex_unlock;
4200 if (b43_status(dev) < B43_STAT_STARTED) {
4201 err = b43_wireless_core_start(dev);
4204 b43_wireless_core_exit(dev);
4206 goto out_mutex_unlock;
4211 mutex_unlock(&wl->mutex);
4214 b43_rfkill_exit(dev);
4219 static void b43_op_stop(struct ieee80211_hw *hw)
4221 struct b43_wl *wl = hw_to_b43_wl(hw);
4222 struct b43_wldev *dev = wl->current_dev;
4224 b43_rfkill_exit(dev);
4225 cancel_work_sync(&(wl->beacon_update_trigger));
4227 mutex_lock(&wl->mutex);
4228 if (b43_status(dev) >= B43_STAT_STARTED)
4229 b43_wireless_core_stop(dev);
4230 b43_wireless_core_exit(dev);
4231 mutex_unlock(&wl->mutex);
4233 cancel_work_sync(&(wl->txpower_adjust_work));
4236 static int b43_op_beacon_set_tim(struct ieee80211_hw *hw,
4237 struct ieee80211_sta *sta, bool set)
4239 struct b43_wl *wl = hw_to_b43_wl(hw);
4240 unsigned long flags;
4242 spin_lock_irqsave(&wl->irq_lock, flags);
4243 b43_update_templates(wl);
4244 spin_unlock_irqrestore(&wl->irq_lock, flags);
4249 static void b43_op_sta_notify(struct ieee80211_hw *hw,
4250 struct ieee80211_vif *vif,
4251 enum sta_notify_cmd notify_cmd,
4252 struct ieee80211_sta *sta)
4254 struct b43_wl *wl = hw_to_b43_wl(hw);
4256 B43_WARN_ON(!vif || wl->vif != vif);
4259 static const struct ieee80211_ops b43_hw_ops = {
4261 .conf_tx = b43_op_conf_tx,
4262 .add_interface = b43_op_add_interface,
4263 .remove_interface = b43_op_remove_interface,
4264 .config = b43_op_config,
4265 .bss_info_changed = b43_op_bss_info_changed,
4266 .config_interface = b43_op_config_interface,
4267 .configure_filter = b43_op_configure_filter,
4268 .set_key = b43_op_set_key,
4269 .get_stats = b43_op_get_stats,
4270 .get_tx_stats = b43_op_get_tx_stats,
4271 .start = b43_op_start,
4272 .stop = b43_op_stop,
4273 .set_tim = b43_op_beacon_set_tim,
4274 .sta_notify = b43_op_sta_notify,
4277 /* Hard-reset the chip. Do not call this directly.
4278 * Use b43_controller_restart()
4280 static void b43_chip_reset(struct work_struct *work)
4282 struct b43_wldev *dev =
4283 container_of(work, struct b43_wldev, restart_work);
4284 struct b43_wl *wl = dev->wl;
4288 mutex_lock(&wl->mutex);
4290 prev_status = b43_status(dev);
4291 /* Bring the device down... */
4292 if (prev_status >= B43_STAT_STARTED)
4293 b43_wireless_core_stop(dev);
4294 if (prev_status >= B43_STAT_INITIALIZED)
4295 b43_wireless_core_exit(dev);
4297 /* ...and up again. */
4298 if (prev_status >= B43_STAT_INITIALIZED) {
4299 err = b43_wireless_core_init(dev);
4303 if (prev_status >= B43_STAT_STARTED) {
4304 err = b43_wireless_core_start(dev);
4306 b43_wireless_core_exit(dev);
4312 wl->current_dev = NULL; /* Failed to init the dev. */
4313 mutex_unlock(&wl->mutex);
4315 b43err(wl, "Controller restart FAILED\n");
4317 b43info(wl, "Controller restarted\n");
4320 static int b43_setup_bands(struct b43_wldev *dev,
4321 bool have_2ghz_phy, bool have_5ghz_phy)
4323 struct ieee80211_hw *hw = dev->wl->hw;
4326 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &b43_band_2GHz;
4327 if (dev->phy.type == B43_PHYTYPE_N) {
4329 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_nphy;
4332 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = &b43_band_5GHz_aphy;
4335 dev->phy.supports_2ghz = have_2ghz_phy;
4336 dev->phy.supports_5ghz = have_5ghz_phy;
4341 static void b43_wireless_core_detach(struct b43_wldev *dev)
4343 /* We release firmware that late to not be required to re-request
4344 * is all the time when we reinit the core. */
4345 b43_release_firmware(dev);
4349 static int b43_wireless_core_attach(struct b43_wldev *dev)
4351 struct b43_wl *wl = dev->wl;
4352 struct ssb_bus *bus = dev->dev->bus;
4353 struct pci_dev *pdev = bus->host_pci;
4355 bool have_2ghz_phy = 0, have_5ghz_phy = 0;
4358 /* Do NOT do any device initialization here.
4359 * Do it in wireless_core_init() instead.
4360 * This function is for gathering basic information about the HW, only.
4361 * Also some structs may be set up here. But most likely you want to have
4362 * that in core_init(), too.
4365 err = ssb_bus_powerup(bus, 0);
4367 b43err(wl, "Bus powerup failed\n");
4370 /* Get the PHY type. */
4371 if (dev->dev->id.revision >= 5) {
4374 tmshigh = ssb_read32(dev->dev, SSB_TMSHIGH);
4375 have_2ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_2GHZ_PHY);
4376 have_5ghz_phy = !!(tmshigh & B43_TMSHIGH_HAVE_5GHZ_PHY);
4380 dev->phy.gmode = have_2ghz_phy;
4381 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4382 b43_wireless_core_reset(dev, tmp);
4384 err = b43_phy_versioning(dev);
4387 /* Check if this device supports multiband. */
4389 (pdev->device != 0x4312 &&
4390 pdev->device != 0x4319 && pdev->device != 0x4324)) {
4391 /* No multiband support. */
4394 switch (dev->phy.type) {
4406 if (dev->phy.type == B43_PHYTYPE_A) {
4408 b43err(wl, "IEEE 802.11a devices are unsupported\n");
4412 if (1 /* disable A-PHY */) {
4413 /* FIXME: For now we disable the A-PHY on multi-PHY devices. */
4414 if (dev->phy.type != B43_PHYTYPE_N) {
4420 err = b43_phy_allocate(dev);
4424 dev->phy.gmode = have_2ghz_phy;
4425 tmp = dev->phy.gmode ? B43_TMSLOW_GMODE : 0;
4426 b43_wireless_core_reset(dev, tmp);
4428 err = b43_validate_chipaccess(dev);
4431 err = b43_setup_bands(dev, have_2ghz_phy, have_5ghz_phy);
4435 /* Now set some default "current_dev" */
4436 if (!wl->current_dev)
4437 wl->current_dev = dev;
4438 INIT_WORK(&dev->restart_work, b43_chip_reset);
4440 dev->phy.ops->switch_analog(dev, 0);
4441 ssb_device_disable(dev->dev, 0);
4442 ssb_bus_may_powerdown(bus);
4450 ssb_bus_may_powerdown(bus);
4454 static void b43_one_core_detach(struct ssb_device *dev)
4456 struct b43_wldev *wldev;
4459 /* Do not cancel ieee80211-workqueue based work here.
4460 * See comment in b43_remove(). */
4462 wldev = ssb_get_drvdata(dev);
4464 b43_debugfs_remove_device(wldev);
4465 b43_wireless_core_detach(wldev);
4466 list_del(&wldev->list);
4468 ssb_set_drvdata(dev, NULL);
4472 static int b43_one_core_attach(struct ssb_device *dev, struct b43_wl *wl)
4474 struct b43_wldev *wldev;
4475 struct pci_dev *pdev;
4478 if (!list_empty(&wl->devlist)) {
4479 /* We are not the first core on this chip. */
4480 pdev = dev->bus->host_pci;
4481 /* Only special chips support more than one wireless
4482 * core, although some of the other chips have more than
4483 * one wireless core as well. Check for this and
4487 ((pdev->device != 0x4321) &&
4488 (pdev->device != 0x4313) && (pdev->device != 0x431A))) {
4489 b43dbg(wl, "Ignoring unconnected 802.11 core\n");
4494 wldev = kzalloc(sizeof(*wldev), GFP_KERNEL);
4500 b43_set_status(wldev, B43_STAT_UNINIT);
4501 wldev->bad_frames_preempt = modparam_bad_frames_preempt;
4502 tasklet_init(&wldev->isr_tasklet,
4503 (void (*)(unsigned long))b43_interrupt_tasklet,
4504 (unsigned long)wldev);
4505 INIT_LIST_HEAD(&wldev->list);
4507 err = b43_wireless_core_attach(wldev);
4509 goto err_kfree_wldev;
4511 list_add(&wldev->list, &wl->devlist);
4513 ssb_set_drvdata(dev, wldev);
4514 b43_debugfs_add_device(wldev);
4524 #define IS_PDEV(pdev, _vendor, _device, _subvendor, _subdevice) ( \
4525 (pdev->vendor == PCI_VENDOR_ID_##_vendor) && \
4526 (pdev->device == _device) && \
4527 (pdev->subsystem_vendor == PCI_VENDOR_ID_##_subvendor) && \
4528 (pdev->subsystem_device == _subdevice) )
4530 static void b43_sprom_fixup(struct ssb_bus *bus)
4532 struct pci_dev *pdev;
4534 /* boardflags workarounds */
4535 if (bus->boardinfo.vendor == SSB_BOARDVENDOR_DELL &&
4536 bus->chip_id == 0x4301 && bus->boardinfo.rev == 0x74)
4537 bus->sprom.boardflags_lo |= B43_BFL_BTCOEXIST;
4538 if (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
4539 bus->boardinfo.type == 0x4E && bus->boardinfo.rev > 0x40)
4540 bus->sprom.boardflags_lo |= B43_BFL_PACTRL;
4541 if (bus->bustype == SSB_BUSTYPE_PCI) {
4542 pdev = bus->host_pci;
4543 if (IS_PDEV(pdev, BROADCOM, 0x4318, ASUSTEK, 0x100F) ||
4544 IS_PDEV(pdev, BROADCOM, 0x4320, DELL, 0x0003) ||
4545 IS_PDEV(pdev, BROADCOM, 0x4320, HP, 0x12f8) ||
4546 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0015) ||
4547 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0014) ||
4548 IS_PDEV(pdev, BROADCOM, 0x4320, LINKSYS, 0x0013) ||
4549 IS_PDEV(pdev, BROADCOM, 0x4320, MOTOROLA, 0x7010))
4550 bus->sprom.boardflags_lo &= ~B43_BFL_BTCOEXIST;
4554 static void b43_wireless_exit(struct ssb_device *dev, struct b43_wl *wl)
4556 struct ieee80211_hw *hw = wl->hw;
4558 ssb_set_devtypedata(dev, NULL);
4559 ieee80211_free_hw(hw);
4562 static int b43_wireless_init(struct ssb_device *dev)
4564 struct ssb_sprom *sprom = &dev->bus->sprom;
4565 struct ieee80211_hw *hw;
4569 b43_sprom_fixup(dev->bus);
4571 hw = ieee80211_alloc_hw(sizeof(*wl), &b43_hw_ops);
4573 b43err(NULL, "Could not allocate ieee80211 device\n");
4578 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
4579 IEEE80211_HW_SIGNAL_DBM |
4580 IEEE80211_HW_NOISE_DBM;
4582 hw->wiphy->interface_modes =
4583 BIT(NL80211_IFTYPE_AP) |
4584 BIT(NL80211_IFTYPE_MESH_POINT) |
4585 BIT(NL80211_IFTYPE_STATION) |
4586 BIT(NL80211_IFTYPE_WDS) |
4587 BIT(NL80211_IFTYPE_ADHOC);
4589 hw->queues = b43_modparam_qos ? 4 : 1;
4591 SET_IEEE80211_DEV(hw, dev->dev);
4592 if (is_valid_ether_addr(sprom->et1mac))
4593 SET_IEEE80211_PERM_ADDR(hw, sprom->et1mac);
4595 SET_IEEE80211_PERM_ADDR(hw, sprom->il0mac);
4597 /* Get and initialize struct b43_wl */
4598 wl = hw_to_b43_wl(hw);
4599 memset(wl, 0, sizeof(*wl));
4601 spin_lock_init(&wl->irq_lock);
4602 rwlock_init(&wl->tx_lock);
4603 spin_lock_init(&wl->leds_lock);
4604 spin_lock_init(&wl->shm_lock);
4605 mutex_init(&wl->mutex);
4606 INIT_LIST_HEAD(&wl->devlist);
4607 INIT_WORK(&wl->beacon_update_trigger, b43_beacon_update_trigger_work);
4608 INIT_WORK(&wl->txpower_adjust_work, b43_phy_txpower_adjust_work);
4610 ssb_set_devtypedata(dev, wl);
4611 b43info(wl, "Broadcom %04X WLAN found\n", dev->bus->chip_id);
4617 static int b43_probe(struct ssb_device *dev, const struct ssb_device_id *id)
4623 wl = ssb_get_devtypedata(dev);
4625 /* Probing the first core. Must setup common struct b43_wl */
4627 err = b43_wireless_init(dev);
4630 wl = ssb_get_devtypedata(dev);
4633 err = b43_one_core_attach(dev, wl);
4635 goto err_wireless_exit;
4638 err = ieee80211_register_hw(wl->hw);
4640 goto err_one_core_detach;
4646 err_one_core_detach:
4647 b43_one_core_detach(dev);
4650 b43_wireless_exit(dev, wl);
4654 static void b43_remove(struct ssb_device *dev)
4656 struct b43_wl *wl = ssb_get_devtypedata(dev);
4657 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4659 /* We must cancel any work here before unregistering from ieee80211,
4660 * as the ieee80211 unreg will destroy the workqueue. */
4661 cancel_work_sync(&wldev->restart_work);
4664 if (wl->current_dev == wldev)
4665 ieee80211_unregister_hw(wl->hw);
4667 b43_one_core_detach(dev);
4669 if (list_empty(&wl->devlist)) {
4670 /* Last core on the chip unregistered.
4671 * We can destroy common struct b43_wl.
4673 b43_wireless_exit(dev, wl);
4677 /* Perform a hardware reset. This can be called from any context. */
4678 void b43_controller_restart(struct b43_wldev *dev, const char *reason)
4680 /* Must avoid requeueing, if we are in shutdown. */
4681 if (b43_status(dev) < B43_STAT_INITIALIZED)
4683 b43info(dev->wl, "Controller RESET (%s) ...\n", reason);
4684 queue_work(dev->wl->hw->workqueue, &dev->restart_work);
4689 static int b43_suspend(struct ssb_device *dev, pm_message_t state)
4691 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4692 struct b43_wl *wl = wldev->wl;
4694 b43dbg(wl, "Suspending...\n");
4696 mutex_lock(&wl->mutex);
4697 wldev->suspend_in_progress = true;
4698 wldev->suspend_init_status = b43_status(wldev);
4699 if (wldev->suspend_init_status >= B43_STAT_STARTED)
4700 b43_wireless_core_stop(wldev);
4701 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED)
4702 b43_wireless_core_exit(wldev);
4703 mutex_unlock(&wl->mutex);
4705 b43dbg(wl, "Device suspended.\n");
4710 static int b43_resume(struct ssb_device *dev)
4712 struct b43_wldev *wldev = ssb_get_drvdata(dev);
4713 struct b43_wl *wl = wldev->wl;
4716 b43dbg(wl, "Resuming...\n");
4718 mutex_lock(&wl->mutex);
4719 if (wldev->suspend_init_status >= B43_STAT_INITIALIZED) {
4720 err = b43_wireless_core_init(wldev);
4722 b43err(wl, "Resume failed at core init\n");
4726 if (wldev->suspend_init_status >= B43_STAT_STARTED) {
4727 err = b43_wireless_core_start(wldev);
4729 b43_leds_exit(wldev);
4730 b43_rng_exit(wldev->wl);
4731 b43_wireless_core_exit(wldev);
4732 b43err(wl, "Resume failed at core start\n");
4736 b43dbg(wl, "Device resumed.\n");
4738 wldev->suspend_in_progress = false;
4739 mutex_unlock(&wl->mutex);
4743 #else /* CONFIG_PM */
4744 # define b43_suspend NULL
4745 # define b43_resume NULL
4746 #endif /* CONFIG_PM */
4748 static struct ssb_driver b43_ssb_driver = {
4749 .name = KBUILD_MODNAME,
4750 .id_table = b43_ssb_tbl,
4752 .remove = b43_remove,
4753 .suspend = b43_suspend,
4754 .resume = b43_resume,
4757 static void b43_print_driverinfo(void)
4759 const char *feat_pci = "", *feat_pcmcia = "", *feat_nphy = "",
4760 *feat_leds = "", *feat_rfkill = "";
4762 #ifdef CONFIG_B43_PCI_AUTOSELECT
4765 #ifdef CONFIG_B43_PCMCIA
4768 #ifdef CONFIG_B43_NPHY
4771 #ifdef CONFIG_B43_LEDS
4774 #ifdef CONFIG_B43_RFKILL
4777 printk(KERN_INFO "Broadcom 43xx driver loaded "
4778 "[ Features: %s%s%s%s%s, Firmware-ID: "
4779 B43_SUPPORTED_FIRMWARE_ID " ]\n",
4780 feat_pci, feat_pcmcia, feat_nphy,
4781 feat_leds, feat_rfkill);
4784 static int __init b43_init(void)
4789 err = b43_pcmcia_init();
4792 err = ssb_driver_register(&b43_ssb_driver);
4794 goto err_pcmcia_exit;
4795 b43_print_driverinfo();
4806 static void __exit b43_exit(void)
4808 ssb_driver_unregister(&b43_ssb_driver);
4813 module_init(b43_init)
4814 module_exit(b43_exit)