2 * Copyright (c) 2008 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 #define BITS_PER_BYTE 8
20 #define OFDM_PLCP_BITS 22
21 #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f)
22 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
28 #define HT_LTF(_ns) (4 * (_ns))
29 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
30 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
31 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
32 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
34 #define OFDM_SIFS_TIME 16
36 static u32 bits_per_symbol[][2] = {
38 { 26, 54 }, /* 0: BPSK */
39 { 52, 108 }, /* 1: QPSK 1/2 */
40 { 78, 162 }, /* 2: QPSK 3/4 */
41 { 104, 216 }, /* 3: 16-QAM 1/2 */
42 { 156, 324 }, /* 4: 16-QAM 3/4 */
43 { 208, 432 }, /* 5: 64-QAM 2/3 */
44 { 234, 486 }, /* 6: 64-QAM 3/4 */
45 { 260, 540 }, /* 7: 64-QAM 5/6 */
46 { 52, 108 }, /* 8: BPSK */
47 { 104, 216 }, /* 9: QPSK 1/2 */
48 { 156, 324 }, /* 10: QPSK 3/4 */
49 { 208, 432 }, /* 11: 16-QAM 1/2 */
50 { 312, 648 }, /* 12: 16-QAM 3/4 */
51 { 416, 864 }, /* 13: 64-QAM 2/3 */
52 { 468, 972 }, /* 14: 64-QAM 3/4 */
53 { 520, 1080 }, /* 15: 64-QAM 5/6 */
56 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
59 * Insert a chain of ath_buf (descriptors) on a txq and
60 * assume the descriptors are already chained together by caller.
61 * NB: must be called with txq lock held
64 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
65 struct list_head *head)
67 struct ath_hal *ah = sc->sc_ah;
71 * Insert the frame on the outbound list and
72 * pass it on to the hardware.
78 bf = list_first_entry(head, struct ath_buf, list);
80 list_splice_tail_init(head, &txq->axq_q);
82 txq->axq_totalqueued++;
83 txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list);
85 DPRINTF(sc, ATH_DBG_QUEUE,
86 "%s: txq depth = %d\n", __func__, txq->axq_depth);
88 if (txq->axq_link == NULL) {
89 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
90 DPRINTF(sc, ATH_DBG_XMIT,
91 "%s: TXDP[%u] = %llx (%p)\n",
92 __func__, txq->axq_qnum,
93 ito64(bf->bf_daddr), bf->bf_desc);
95 *txq->axq_link = bf->bf_daddr;
96 DPRINTF(sc, ATH_DBG_XMIT, "%s: link[%u] (%p)=%llx (%p)\n",
98 txq->axq_qnum, txq->axq_link,
99 ito64(bf->bf_daddr), bf->bf_desc);
101 txq->axq_link = &(bf->bf_lastbf->bf_desc->ds_link);
102 ath9k_hw_txstart(ah, txq->axq_qnum);
105 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
106 struct ath_xmit_status *tx_status)
108 struct ieee80211_hw *hw = sc->hw;
109 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
110 struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info);
112 DPRINTF(sc, ATH_DBG_XMIT,
113 "%s: TX complete: skb: %p\n", __func__, skb);
115 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK ||
116 tx_info->flags & IEEE80211_TX_STAT_TX_FILTERED) {
118 tx_info->rate_driver_data[0] = NULL;
121 if (tx_status->flags & ATH_TX_BAR) {
122 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
123 tx_status->flags &= ~ATH_TX_BAR;
126 if (!(tx_status->flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) {
127 /* Frame was ACKed */
128 tx_info->flags |= IEEE80211_TX_STAT_ACK;
131 tx_info->status.rates[0].count = tx_status->retries + 1;
133 ieee80211_tx_status(hw, skb);
136 /* Check if it's okay to send out aggregates */
138 static int ath_aggr_query(struct ath_softc *sc, struct ath_node *an, u8 tidno)
140 struct ath_atx_tid *tid;
141 tid = ATH_AN_2_TID(an, tidno);
143 if (tid->state & AGGR_ADDBA_COMPLETE ||
144 tid->state & AGGR_ADDBA_PROGRESS)
150 /* Calculate Atheros packet type from IEEE80211 packet header */
152 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
154 struct ieee80211_hdr *hdr;
155 enum ath9k_pkt_type htype;
158 hdr = (struct ieee80211_hdr *)skb->data;
159 fc = hdr->frame_control;
161 if (ieee80211_is_beacon(fc))
162 htype = ATH9K_PKT_TYPE_BEACON;
163 else if (ieee80211_is_probe_resp(fc))
164 htype = ATH9K_PKT_TYPE_PROBE_RESP;
165 else if (ieee80211_is_atim(fc))
166 htype = ATH9K_PKT_TYPE_ATIM;
167 else if (ieee80211_is_pspoll(fc))
168 htype = ATH9K_PKT_TYPE_PSPOLL;
170 htype = ATH9K_PKT_TYPE_NORMAL;
175 static bool is_pae(struct sk_buff *skb)
177 struct ieee80211_hdr *hdr;
180 hdr = (struct ieee80211_hdr *)skb->data;
181 fc = hdr->frame_control;
183 if (ieee80211_is_data(fc)) {
184 if (ieee80211_is_nullfunc(fc) ||
185 /* Port Access Entity (IEEE 802.1X) */
186 (skb->protocol == cpu_to_be16(ETH_P_PAE))) {
194 static int get_hw_crypto_keytype(struct sk_buff *skb)
196 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
198 if (tx_info->control.hw_key) {
199 if (tx_info->control.hw_key->alg == ALG_WEP)
200 return ATH9K_KEY_TYPE_WEP;
201 else if (tx_info->control.hw_key->alg == ALG_TKIP)
202 return ATH9K_KEY_TYPE_TKIP;
203 else if (tx_info->control.hw_key->alg == ALG_CCMP)
204 return ATH9K_KEY_TYPE_AES;
207 return ATH9K_KEY_TYPE_CLEAR;
210 /* Called only when tx aggregation is enabled and HT is supported */
212 static void assign_aggr_tid_seqno(struct sk_buff *skb,
215 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
216 struct ieee80211_hdr *hdr;
218 struct ath_atx_tid *tid;
222 if (!tx_info->control.sta)
225 an = (struct ath_node *)tx_info->control.sta->drv_priv;
226 hdr = (struct ieee80211_hdr *)skb->data;
227 fc = hdr->frame_control;
231 if (ieee80211_is_data_qos(fc)) {
232 qc = ieee80211_get_qos_ctl(hdr);
233 bf->bf_tidno = qc[0] & 0xf;
238 if (ieee80211_is_data(fc) && !is_pae(skb)) {
239 /* For HT capable stations, we save tidno for later use.
240 * We also override seqno set by upper layer with the one
241 * in tx aggregation state.
243 * If fragmentation is on, the sequence number is
244 * not overridden, since it has been
245 * incremented by the fragmentation routine.
247 * FIXME: check if the fragmentation threshold exceeds
250 tid = ATH_AN_2_TID(an, bf->bf_tidno);
251 hdr->seq_ctrl = cpu_to_le16(tid->seq_next <<
252 IEEE80211_SEQ_SEQ_SHIFT);
253 bf->bf_seqno = tid->seq_next;
254 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
258 static int setup_tx_flags(struct ath_softc *sc, struct sk_buff *skb,
261 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
264 flags |= ATH9K_TXDESC_CLRDMASK; /* needed for crypto errors */
265 flags |= ATH9K_TXDESC_INTREQ;
267 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
268 flags |= ATH9K_TXDESC_NOACK;
269 if (tx_info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS)
270 flags |= ATH9K_TXDESC_RTSENA;
275 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
277 struct ath_buf *bf = NULL;
279 spin_lock_bh(&sc->sc_txbuflock);
281 if (unlikely(list_empty(&sc->sc_txbuf))) {
282 spin_unlock_bh(&sc->sc_txbuflock);
286 bf = list_first_entry(&sc->sc_txbuf, struct ath_buf, list);
289 spin_unlock_bh(&sc->sc_txbuflock);
294 /* To complete a chain of buffers associated a frame */
296 static void ath_tx_complete_buf(struct ath_softc *sc,
298 struct list_head *bf_q,
299 int txok, int sendbar)
301 struct sk_buff *skb = bf->bf_mpdu;
302 struct ath_xmit_status tx_status;
305 * Set retry information.
306 * NB: Don't use the information in the descriptor, because the frame
307 * could be software retried.
309 tx_status.retries = bf->bf_retries;
313 tx_status.flags = ATH_TX_BAR;
316 tx_status.flags |= ATH_TX_ERROR;
318 if (bf_isxretried(bf))
319 tx_status.flags |= ATH_TX_XRETRY;
322 /* Unmap this frame */
323 pci_unmap_single(sc->pdev,
327 /* complete this frame */
328 ath_tx_complete(sc, skb, &tx_status);
331 * Return the list of ath_buf of this mpdu to free queue
333 spin_lock_bh(&sc->sc_txbuflock);
334 list_splice_tail_init(bf_q, &sc->sc_txbuf);
335 spin_unlock_bh(&sc->sc_txbuflock);
339 * queue up a dest/ac pair for tx scheduling
340 * NB: must be called with txq lock held
343 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
345 struct ath_atx_ac *ac = tid->ac;
348 * if tid is paused, hold off
354 * add tid to ac atmost once
360 list_add_tail(&tid->list, &ac->tid_q);
363 * add node ac to txq atmost once
369 list_add_tail(&ac->list, &txq->axq_acq);
374 static void ath_tx_pause_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
376 struct ath_txq *txq = &sc->sc_txq[tid->ac->qnum];
378 spin_lock_bh(&txq->axq_lock);
382 spin_unlock_bh(&txq->axq_lock);
385 /* resume a tid and schedule aggregate */
387 void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
389 struct ath_txq *txq = &sc->sc_txq[tid->ac->qnum];
391 ASSERT(tid->paused > 0);
392 spin_lock_bh(&txq->axq_lock);
399 if (list_empty(&tid->buf_q))
403 * Add this TID to scheduler and try to send out aggregates
405 ath_tx_queue_tid(txq, tid);
406 ath_txq_schedule(sc, txq);
408 spin_unlock_bh(&txq->axq_lock);
411 /* Compute the number of bad frames */
413 static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
416 struct ath_buf *bf_last = bf->bf_lastbf;
417 struct ath_desc *ds = bf_last->bf_desc;
419 u32 ba[WME_BA_BMP_SIZE >> 5];
424 if (ds->ds_txstat.ts_flags == ATH9K_TX_SW_ABORTED)
427 isaggr = bf_isaggr(bf);
429 seq_st = ATH_DS_BA_SEQ(ds);
430 memcpy(ba, ATH_DS_BA_BITMAP(ds), WME_BA_BMP_SIZE >> 3);
434 ba_index = ATH_BA_INDEX(seq_st, bf->bf_seqno);
435 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
444 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_buf *bf)
447 struct ieee80211_hdr *hdr;
449 bf->bf_state.bf_type |= BUF_RETRY;
453 hdr = (struct ieee80211_hdr *)skb->data;
454 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
457 /* Update block ack window */
459 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
464 index = ATH_BA_INDEX(tid->seq_start, seqno);
465 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
467 tid->tx_buf[cindex] = NULL;
469 while (tid->baw_head != tid->baw_tail && !tid->tx_buf[tid->baw_head]) {
470 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
471 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
476 * ath_pkt_dur - compute packet duration (NB: not NAV)
479 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
480 * width - 0 for 20 MHz, 1 for 40 MHz
481 * half_gi - to use 4us v/s 3.6 us for symbol time
483 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf,
484 int width, int half_gi, bool shortPreamble)
486 struct ath_rate_table *rate_table = sc->hw_rate_table[sc->sc_curmode];
487 u32 nbits, nsymbits, duration, nsymbols;
491 pktlen = bf_isaggr(bf) ? bf->bf_al : bf->bf_frmlen;
492 rc = rate_table->info[rix].ratecode;
494 /* for legacy rates, use old function to compute packet duration */
496 return ath9k_hw_computetxtime(sc->sc_ah, rate_table, pktlen,
499 /* find number of symbols: PLCP + data */
500 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
501 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width];
502 nsymbols = (nbits + nsymbits - 1) / nsymbits;
505 duration = SYMBOL_TIME(nsymbols);
507 duration = SYMBOL_TIME_HALFGI(nsymbols);
509 /* addup duration for legacy/ht training and signal fields */
510 streams = HT_RC_2_STREAMS(rc);
511 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
516 /* Rate module function to set rate related fields in tx descriptor */
518 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
520 struct ath_hal *ah = sc->sc_ah;
521 struct ath_rate_table *rt;
522 struct ath_desc *ds = bf->bf_desc;
523 struct ath_desc *lastds = bf->bf_lastbf->bf_desc;
524 struct ath9k_11n_rate_series series[4];
525 struct ath_node *an = NULL;
527 struct ieee80211_tx_info *tx_info;
528 struct ieee80211_tx_rate *rates;
529 struct ieee80211_hdr *hdr;
530 int i, flags, rtsctsena = 0;
532 u8 rix = 0, cix, ctsrate = 0;
535 memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4);
537 skb = (struct sk_buff *)bf->bf_mpdu;
538 hdr = (struct ieee80211_hdr *)skb->data;
539 fc = hdr->frame_control;
540 tx_info = IEEE80211_SKB_CB(skb);
541 rates = tx_info->control.rates;
543 if (tx_info->control.sta)
544 an = (struct ath_node *)tx_info->control.sta->drv_priv;
546 if (ieee80211_has_morefrags(fc) ||
547 (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG)) {
548 rates[1].count = rates[2].count = rates[3].count = 0;
549 rates[1].idx = rates[2].idx = rates[3].idx = 0;
550 rates[0].count = ATH_TXMAXTRY;
553 /* get the cix for the lowest valid rix */
554 rt = sc->hw_rate_table[sc->sc_curmode];
555 for (i = 3; i >= 0; i--) {
556 if (rates[i].count && (rates[i].idx >= 0)) {
562 flags = (bf->bf_flags & (ATH9K_TXDESC_RTSENA | ATH9K_TXDESC_CTSENA));
563 cix = rt->info[rix].ctrl_rate;
566 * If 802.11g protection is enabled, determine whether to use RTS/CTS or
567 * just CTS. Note that this is only done for OFDM/HT unicast frames.
569 if (sc->sc_protmode != PROT_M_NONE && !(bf->bf_flags & ATH9K_TXDESC_NOACK)
570 && (rt->info[rix].phy == WLAN_RC_PHY_OFDM ||
571 WLAN_RC_PHY_HT(rt->info[rix].phy))) {
572 if (sc->sc_protmode == PROT_M_RTSCTS)
573 flags = ATH9K_TXDESC_RTSENA;
574 else if (sc->sc_protmode == PROT_M_CTSONLY)
575 flags = ATH9K_TXDESC_CTSENA;
577 cix = rt->info[sc->sc_protrix].ctrl_rate;
581 /* For 11n, the default behavior is to enable RTS for hw retried frames.
582 * We enable the global flag here and let rate series flags determine
583 * which rates will actually use RTS.
585 if ((ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) && bf_isdata(bf)) {
586 /* 802.11g protection not needed, use our default behavior */
588 flags = ATH9K_TXDESC_RTSENA;
591 /* Set protection if aggregate protection on */
592 if (sc->sc_config.ath_aggr_prot &&
593 (!bf_isaggr(bf) || (bf_isaggr(bf) && bf->bf_al < 8192))) {
594 flags = ATH9K_TXDESC_RTSENA;
595 cix = rt->info[sc->sc_protrix].ctrl_rate;
599 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
600 if (bf_isaggr(bf) && (bf->bf_al > ah->ah_caps.rts_aggr_limit))
601 flags &= ~(ATH9K_TXDESC_RTSENA);
604 * CTS transmit rate is derived from the transmit rate by looking in the
605 * h/w rate table. We must also factor in whether or not a short
606 * preamble is to be used. NB: cix is set above where RTS/CTS is enabled
608 ctsrate = rt->info[cix].ratecode |
609 (bf_isshpreamble(bf) ? rt->info[cix].short_preamble : 0);
611 for (i = 0; i < 4; i++) {
612 if (!rates[i].count || (rates[i].idx < 0))
617 series[i].Rate = rt->info[rix].ratecode |
618 (bf_isshpreamble(bf) ? rt->info[rix].short_preamble : 0);
620 series[i].Tries = rates[i].count;
622 series[i].RateFlags = (
623 (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) ?
624 ATH9K_RATESERIES_RTS_CTS : 0) |
625 ((rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ?
626 ATH9K_RATESERIES_2040 : 0) |
627 ((rates[i].flags & IEEE80211_TX_RC_SHORT_GI) ?
628 ATH9K_RATESERIES_HALFGI : 0);
630 series[i].PktDuration = ath_pkt_duration(sc, rix, bf,
631 (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) != 0,
632 (rates[i].flags & IEEE80211_TX_RC_SHORT_GI),
633 bf_isshpreamble(bf));
635 if (bf_isht(bf) && an)
636 series[i].ChSel = ath_chainmask_sel_logic(sc, an);
638 series[i].ChSel = sc->sc_tx_chainmask;
641 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
644 /* set dur_update_en for l-sig computation except for PS-Poll frames */
645 ath9k_hw_set11n_ratescenario(ah, ds, lastds, !bf_ispspoll(bf),
646 ctsrate, ctsduration,
649 if (sc->sc_config.ath_aggr_prot && flags)
650 ath9k_hw_set11n_burstduration(ah, ds, 8192);
654 * Function to send a normal HT (non-AMPDU) frame
655 * NB: must be called with txq lock held
657 static int ath_tx_send_normal(struct ath_softc *sc,
659 struct ath_atx_tid *tid,
660 struct list_head *bf_head)
664 BUG_ON(list_empty(bf_head));
666 bf = list_first_entry(bf_head, struct ath_buf, list);
667 bf->bf_state.bf_type &= ~BUF_AMPDU; /* regular HT frame */
669 /* update starting sequence number for subsequent ADDBA request */
670 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
672 /* Queue to h/w without aggregation */
674 bf->bf_lastbf = bf->bf_lastfrm; /* one single frame */
675 ath_buf_set_rate(sc, bf);
676 ath_tx_txqaddbuf(sc, txq, bf_head);
681 /* flush tid's software queue and send frames as non-ampdu's */
683 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
685 struct ath_txq *txq = &sc->sc_txq[tid->ac->qnum];
687 struct list_head bf_head;
688 INIT_LIST_HEAD(&bf_head);
690 ASSERT(tid->paused > 0);
691 spin_lock_bh(&txq->axq_lock);
695 if (tid->paused > 0) {
696 spin_unlock_bh(&txq->axq_lock);
700 while (!list_empty(&tid->buf_q)) {
701 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
702 ASSERT(!bf_isretried(bf));
703 list_cut_position(&bf_head, &tid->buf_q, &bf->bf_lastfrm->list);
704 ath_tx_send_normal(sc, txq, tid, &bf_head);
707 spin_unlock_bh(&txq->axq_lock);
710 /* Completion routine of an aggregate */
712 static void ath_tx_complete_aggr_rifs(struct ath_softc *sc,
715 struct list_head *bf_q,
718 struct ath_node *an = NULL;
720 struct ieee80211_tx_info *tx_info;
721 struct ath_atx_tid *tid = NULL;
722 struct ath_buf *bf_last = bf->bf_lastbf;
723 struct ath_desc *ds = bf_last->bf_desc;
724 struct ath_buf *bf_next, *bf_lastq = NULL;
725 struct list_head bf_head, bf_pending;
727 u32 ba[WME_BA_BMP_SIZE >> 5];
728 int isaggr, txfail, txpending, sendbar = 0, needreset = 0;
730 skb = (struct sk_buff *)bf->bf_mpdu;
731 tx_info = IEEE80211_SKB_CB(skb);
733 if (tx_info->control.sta) {
734 an = (struct ath_node *)tx_info->control.sta->drv_priv;
735 tid = ATH_AN_2_TID(an, bf->bf_tidno);
738 isaggr = bf_isaggr(bf);
741 if (ATH_DS_TX_BA(ds)) {
743 * extract starting sequence and
746 seq_st = ATH_DS_BA_SEQ(ds);
748 ATH_DS_BA_BITMAP(ds),
749 WME_BA_BMP_SIZE >> 3);
751 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
754 * AR5416 can become deaf/mute when BA
755 * issue happens. Chip needs to be reset.
756 * But AP code may have sychronization issues
757 * when perform internal reset in this routine.
758 * Only enable reset in STA mode for now.
760 if (sc->sc_ah->ah_opmode == ATH9K_M_STA)
764 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
768 INIT_LIST_HEAD(&bf_pending);
769 INIT_LIST_HEAD(&bf_head);
772 txfail = txpending = 0;
773 bf_next = bf->bf_next;
775 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, bf->bf_seqno))) {
776 /* transmit completion, subframe is
777 * acked by block ack */
778 } else if (!isaggr && txok) {
779 /* transmit completion */
782 if (!(tid->state & AGGR_CLEANUP) &&
783 ds->ds_txstat.ts_flags != ATH9K_TX_SW_ABORTED) {
784 if (bf->bf_retries < ATH_MAX_SW_RETRIES) {
785 ath_tx_set_retry(sc, bf);
788 bf->bf_state.bf_type |= BUF_XRETRY;
794 * cleanup in progress, just fail
795 * the un-acked sub-frames
801 * Remove ath_buf's of this sub-frame from aggregate queue.
803 if (bf_next == NULL) { /* last subframe in the aggregate */
804 ASSERT(bf->bf_lastfrm == bf_last);
807 * The last descriptor of the last sub frame could be
808 * a holding descriptor for h/w. If that's the case,
809 * bf->bf_lastfrm won't be in the bf_q.
810 * Make sure we handle bf_q properly here.
813 if (!list_empty(bf_q)) {
814 bf_lastq = list_entry(bf_q->prev,
815 struct ath_buf, list);
816 list_cut_position(&bf_head,
817 bf_q, &bf_lastq->list);
820 * XXX: if the last subframe only has one
821 * descriptor which is also being used as
822 * a holding descriptor. Then the ath_buf
823 * is not in the bf_q at all.
825 INIT_LIST_HEAD(&bf_head);
828 ASSERT(!list_empty(bf_q));
829 list_cut_position(&bf_head,
830 bf_q, &bf->bf_lastfrm->list);
835 * complete the acked-ones/xretried ones; update
838 spin_lock_bh(&txq->axq_lock);
839 ath_tx_update_baw(sc, tid, bf->bf_seqno);
840 spin_unlock_bh(&txq->axq_lock);
842 /* complete this sub-frame */
843 ath_tx_complete_buf(sc, bf, &bf_head, !txfail, sendbar);
846 * retry the un-acked ones
849 * XXX: if the last descriptor is holding descriptor,
850 * in order to requeue the frame to software queue, we
851 * need to allocate a new descriptor and
852 * copy the content of holding descriptor to it.
854 if (bf->bf_next == NULL &&
855 bf_last->bf_status & ATH_BUFSTATUS_STALE) {
858 /* allocate new descriptor */
859 spin_lock_bh(&sc->sc_txbuflock);
860 ASSERT(!list_empty((&sc->sc_txbuf)));
861 tbf = list_first_entry(&sc->sc_txbuf,
862 struct ath_buf, list);
863 list_del(&tbf->list);
864 spin_unlock_bh(&sc->sc_txbuflock);
866 ATH_TXBUF_RESET(tbf);
868 /* copy descriptor content */
869 tbf->bf_mpdu = bf_last->bf_mpdu;
870 tbf->bf_buf_addr = bf_last->bf_buf_addr;
871 *(tbf->bf_desc) = *(bf_last->bf_desc);
873 /* link it to the frame */
875 bf_lastq->bf_desc->ds_link =
877 bf->bf_lastfrm = tbf;
878 ath9k_hw_cleartxdesc(sc->sc_ah,
879 bf->bf_lastfrm->bf_desc);
881 tbf->bf_state = bf_last->bf_state;
882 tbf->bf_lastfrm = tbf;
883 ath9k_hw_cleartxdesc(sc->sc_ah,
884 tbf->bf_lastfrm->bf_desc);
886 /* copy the DMA context */
888 bf_last->bf_dmacontext;
890 list_add_tail(&tbf->list, &bf_head);
893 * Clear descriptor status words for
896 ath9k_hw_cleartxdesc(sc->sc_ah,
897 bf->bf_lastfrm->bf_desc);
901 * Put this buffer to the temporary pending
902 * queue to retain ordering
904 list_splice_tail_init(&bf_head, &bf_pending);
910 if (tid->state & AGGR_CLEANUP) {
911 /* check to see if we're done with cleaning the h/w queue */
912 spin_lock_bh(&txq->axq_lock);
914 if (tid->baw_head == tid->baw_tail) {
915 tid->state &= ~AGGR_ADDBA_COMPLETE;
916 tid->addba_exchangeattempts = 0;
917 spin_unlock_bh(&txq->axq_lock);
919 tid->state &= ~AGGR_CLEANUP;
921 /* send buffered frames as singles */
922 ath_tx_flush_tid(sc, tid);
924 spin_unlock_bh(&txq->axq_lock);
930 * prepend un-acked frames to the beginning of the pending frame queue
932 if (!list_empty(&bf_pending)) {
933 spin_lock_bh(&txq->axq_lock);
934 /* Note: we _prepend_, we _do_not_ at to
935 * the end of the queue ! */
936 list_splice(&bf_pending, &tid->buf_q);
937 ath_tx_queue_tid(txq, tid);
938 spin_unlock_bh(&txq->axq_lock);
942 ath_reset(sc, false);
947 static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds, int nbad)
949 struct sk_buff *skb = (struct sk_buff *)bf->bf_mpdu;
950 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
951 struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info);
953 tx_info_priv->update_rc = false;
954 if (ds->ds_txstat.ts_status & ATH9K_TXERR_FILT)
955 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
957 if ((ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) == 0 &&
958 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0) {
960 memcpy(&tx_info_priv->tx, &ds->ds_txstat,
961 sizeof(tx_info_priv->tx));
962 tx_info_priv->n_frames = bf->bf_nframes;
963 tx_info_priv->n_bad_frames = nbad;
964 tx_info_priv->update_rc = true;
969 /* Process completed xmit descriptors from the specified queue */
971 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
973 struct ath_hal *ah = sc->sc_ah;
974 struct ath_buf *bf, *lastbf, *bf_held = NULL;
975 struct list_head bf_head;
980 DPRINTF(sc, ATH_DBG_QUEUE,
981 "%s: tx queue %d (%x), link %p\n", __func__,
982 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
986 spin_lock_bh(&txq->axq_lock);
987 if (list_empty(&txq->axq_q)) {
988 txq->axq_link = NULL;
989 txq->axq_linkbuf = NULL;
990 spin_unlock_bh(&txq->axq_lock);
993 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
996 * There is a race condition that a BH gets scheduled
997 * after sw writes TxE and before hw re-load the last
998 * descriptor to get the newly chained one.
999 * Software must keep the last DONE descriptor as a
1000 * holding descriptor - software does so by marking
1001 * it with the STALE flag.
1004 if (bf->bf_status & ATH_BUFSTATUS_STALE) {
1006 if (list_is_last(&bf_held->list, &txq->axq_q)) {
1008 * The holding descriptor is the last
1009 * descriptor in queue. It's safe to remove
1010 * the last holding descriptor in BH context.
1012 spin_unlock_bh(&txq->axq_lock);
1015 /* Lets work with the next buffer now */
1016 bf = list_entry(bf_held->list.next,
1017 struct ath_buf, list);
1021 lastbf = bf->bf_lastbf;
1022 ds = lastbf->bf_desc; /* NB: last decriptor */
1024 status = ath9k_hw_txprocdesc(ah, ds);
1025 if (status == -EINPROGRESS) {
1026 spin_unlock_bh(&txq->axq_lock);
1029 if (bf->bf_desc == txq->axq_lastdsWithCTS)
1030 txq->axq_lastdsWithCTS = NULL;
1031 if (ds == txq->axq_gatingds)
1032 txq->axq_gatingds = NULL;
1035 * Remove ath_buf's of the same transmit unit from txq,
1036 * however leave the last descriptor back as the holding
1037 * descriptor for hw.
1039 lastbf->bf_status |= ATH_BUFSTATUS_STALE;
1040 INIT_LIST_HEAD(&bf_head);
1042 if (!list_is_singular(&lastbf->list))
1043 list_cut_position(&bf_head,
1044 &txq->axq_q, lastbf->list.prev);
1049 txq->axq_aggr_depth--;
1051 txok = (ds->ds_txstat.ts_status == 0);
1053 spin_unlock_bh(&txq->axq_lock);
1056 list_del(&bf_held->list);
1057 spin_lock_bh(&sc->sc_txbuflock);
1058 list_add_tail(&bf_held->list, &sc->sc_txbuf);
1059 spin_unlock_bh(&sc->sc_txbuflock);
1062 if (!bf_isampdu(bf)) {
1064 * This frame is sent out as a single frame.
1065 * Use hardware retry status for this frame.
1067 bf->bf_retries = ds->ds_txstat.ts_longretry;
1068 if (ds->ds_txstat.ts_status & ATH9K_TXERR_XRETRY)
1069 bf->bf_state.bf_type |= BUF_XRETRY;
1072 nbad = ath_tx_num_badfrms(sc, bf, txok);
1075 ath_tx_rc_status(bf, ds, nbad);
1078 * Complete this transmit unit
1081 ath_tx_complete_aggr_rifs(sc, txq, bf, &bf_head, txok);
1083 ath_tx_complete_buf(sc, bf, &bf_head, txok, 0);
1085 /* Wake up mac80211 queue */
1087 spin_lock_bh(&txq->axq_lock);
1088 if (txq->stopped && ath_txq_depth(sc, txq->axq_qnum) <=
1091 qnum = ath_get_mac80211_qnum(txq->axq_qnum, sc);
1093 ieee80211_wake_queue(sc->hw, qnum);
1100 * schedule any pending packets if aggregation is enabled
1102 if (sc->sc_flags & SC_OP_TXAGGR)
1103 ath_txq_schedule(sc, txq);
1104 spin_unlock_bh(&txq->axq_lock);
1108 static void ath_tx_stopdma(struct ath_softc *sc, struct ath_txq *txq)
1110 struct ath_hal *ah = sc->sc_ah;
1112 (void) ath9k_hw_stoptxdma(ah, txq->axq_qnum);
1113 DPRINTF(sc, ATH_DBG_XMIT, "%s: tx queue [%u] %x, link %p\n",
1114 __func__, txq->axq_qnum,
1115 ath9k_hw_gettxbuf(ah, txq->axq_qnum), txq->axq_link);
1118 /* Drain only the data queues */
1120 static void ath_drain_txdataq(struct ath_softc *sc, bool retry_tx)
1122 struct ath_hal *ah = sc->sc_ah;
1123 int i, status, npend = 0;
1125 if (!(sc->sc_flags & SC_OP_INVALID)) {
1126 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1127 if (ATH_TXQ_SETUP(sc, i)) {
1128 ath_tx_stopdma(sc, &sc->sc_txq[i]);
1129 /* The TxDMA may not really be stopped.
1130 * Double check the hal tx pending count */
1131 npend += ath9k_hw_numtxpending(ah,
1132 sc->sc_txq[i].axq_qnum);
1138 /* TxDMA not stopped, reset the hal */
1139 DPRINTF(sc, ATH_DBG_XMIT,
1140 "%s: Unable to stop TxDMA. Reset HAL!\n", __func__);
1142 spin_lock_bh(&sc->sc_resetlock);
1143 if (!ath9k_hw_reset(ah,
1144 sc->sc_ah->ah_curchan,
1145 sc->sc_ht_info.tx_chan_width,
1146 sc->sc_tx_chainmask, sc->sc_rx_chainmask,
1147 sc->sc_ht_extprotspacing, true, &status)) {
1149 DPRINTF(sc, ATH_DBG_FATAL,
1150 "%s: unable to reset hardware; hal status %u\n",
1154 spin_unlock_bh(&sc->sc_resetlock);
1157 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1158 if (ATH_TXQ_SETUP(sc, i))
1159 ath_tx_draintxq(sc, &sc->sc_txq[i], retry_tx);
1163 /* Add a sub-frame to block ack window */
1165 static void ath_tx_addto_baw(struct ath_softc *sc,
1166 struct ath_atx_tid *tid,
1171 if (bf_isretried(bf))
1174 index = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno);
1175 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
1177 ASSERT(tid->tx_buf[cindex] == NULL);
1178 tid->tx_buf[cindex] = bf;
1180 if (index >= ((tid->baw_tail - tid->baw_head) &
1181 (ATH_TID_MAX_BUFS - 1))) {
1182 tid->baw_tail = cindex;
1183 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
1188 * Function to send an A-MPDU
1189 * NB: must be called with txq lock held
1192 static int ath_tx_send_ampdu(struct ath_softc *sc,
1193 struct ath_atx_tid *tid,
1194 struct list_head *bf_head,
1195 struct ath_tx_control *txctl)
1199 BUG_ON(list_empty(bf_head));
1201 bf = list_first_entry(bf_head, struct ath_buf, list);
1202 bf->bf_state.bf_type |= BUF_AMPDU;
1205 * Do not queue to h/w when any of the following conditions is true:
1206 * - there are pending frames in software queue
1207 * - the TID is currently paused for ADDBA/BAR request
1208 * - seqno is not within block-ack window
1209 * - h/w queue depth exceeds low water mark
1211 if (!list_empty(&tid->buf_q) || tid->paused ||
1212 !BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno) ||
1213 txctl->txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) {
1215 * Add this frame to software queue for scheduling later
1218 list_splice_tail_init(bf_head, &tid->buf_q);
1219 ath_tx_queue_tid(txctl->txq, tid);
1223 /* Add sub-frame to BAW */
1224 ath_tx_addto_baw(sc, tid, bf);
1226 /* Queue to h/w without aggregation */
1228 bf->bf_lastbf = bf->bf_lastfrm; /* one single frame */
1229 ath_buf_set_rate(sc, bf);
1230 ath_tx_txqaddbuf(sc, txctl->txq, bf_head);
1237 * returns aggr limit based on lowest of the rates
1240 static u32 ath_lookup_rate(struct ath_softc *sc,
1242 struct ath_atx_tid *tid)
1244 struct ath_rate_table *rate_table = sc->hw_rate_table[sc->sc_curmode];
1245 struct sk_buff *skb;
1246 struct ieee80211_tx_info *tx_info;
1247 struct ieee80211_tx_rate *rates;
1248 struct ath_tx_info_priv *tx_info_priv;
1249 u32 max_4ms_framelen, frame_length;
1250 u16 aggr_limit, legacy = 0, maxampdu;
1253 skb = (struct sk_buff *)bf->bf_mpdu;
1254 tx_info = IEEE80211_SKB_CB(skb);
1255 rates = tx_info->control.rates;
1257 (struct ath_tx_info_priv *)tx_info->rate_driver_data[0];
1260 * Find the lowest frame length among the rate series that will have a
1261 * 4ms transmit duration.
1262 * TODO - TXOP limit needs to be considered.
1264 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
1266 for (i = 0; i < 4; i++) {
1267 if (rates[i].count) {
1268 if (!WLAN_RC_PHY_HT(rate_table->info[rates[i].idx].phy)) {
1274 rate_table->info[rates[i].idx].max_4ms_framelen;
1275 max_4ms_framelen = min(max_4ms_framelen, frame_length);
1280 * limit aggregate size by the minimum rate if rate selected is
1281 * not a probe rate, if rate selected is a probe rate then
1282 * avoid aggregation of this packet.
1284 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
1287 aggr_limit = min(max_4ms_framelen,
1288 (u32)ATH_AMPDU_LIMIT_DEFAULT);
1291 * h/w can accept aggregates upto 16 bit lengths (65535).
1292 * The IE, however can hold upto 65536, which shows up here
1293 * as zero. Ignore 65536 since we are constrained by hw.
1295 maxampdu = tid->an->maxampdu;
1297 aggr_limit = min(aggr_limit, maxampdu);
1303 * returns the number of delimiters to be added to
1304 * meet the minimum required mpdudensity.
1305 * caller should make sure that the rate is HT rate .
1308 static int ath_compute_num_delims(struct ath_softc *sc,
1309 struct ath_atx_tid *tid,
1313 struct ath_rate_table *rt = sc->hw_rate_table[sc->sc_curmode];
1314 struct sk_buff *skb = bf->bf_mpdu;
1315 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1316 u32 nsymbits, nsymbols, mpdudensity;
1319 int width, half_gi, ndelim, mindelim;
1321 /* Select standard number of delimiters based on frame length alone */
1322 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
1325 * If encryption enabled, hardware requires some more padding between
1327 * TODO - this could be improved to be dependent on the rate.
1328 * The hardware can keep up at lower rates, but not higher rates
1330 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR)
1331 ndelim += ATH_AGGR_ENCRYPTDELIM;
1334 * Convert desired mpdu density from microeconds to bytes based
1335 * on highest rate in rate series (i.e. first rate) to determine
1336 * required minimum length for subframe. Take into account
1337 * whether high rate is 20 or 40Mhz and half or full GI.
1339 mpdudensity = tid->an->mpdudensity;
1342 * If there is no mpdu density restriction, no further calculation
1345 if (mpdudensity == 0)
1348 rix = tx_info->control.rates[0].idx;
1349 flags = tx_info->control.rates[0].flags;
1350 rc = rt->info[rix].ratecode;
1351 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
1352 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
1355 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(mpdudensity);
1357 nsymbols = NUM_SYMBOLS_PER_USEC(mpdudensity);
1362 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width];
1363 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
1365 /* Is frame shorter than required minimum length? */
1366 if (frmlen < minlen) {
1367 /* Get the minimum number of delimiters required. */
1368 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
1369 ndelim = max(mindelim, ndelim);
1376 * For aggregation from software buffer queue.
1377 * NB: must be called with txq lock held
1380 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
1381 struct ath_atx_tid *tid,
1382 struct list_head *bf_q,
1383 struct ath_buf **bf_last,
1384 struct aggr_rifs_param *param,
1387 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
1388 struct ath_buf *bf, *tbf, *bf_first, *bf_prev = NULL;
1389 struct list_head bf_head;
1390 int rl = 0, nframes = 0, ndelim;
1391 u16 aggr_limit = 0, al = 0, bpad = 0,
1392 al_delta, h_baw = tid->baw_size / 2;
1393 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
1395 INIT_LIST_HEAD(&bf_head);
1397 BUG_ON(list_empty(&tid->buf_q));
1399 bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list);
1402 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
1405 * do not step over block-ack window
1407 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno)) {
1408 status = ATH_AGGR_BAW_CLOSED;
1413 aggr_limit = ath_lookup_rate(sc, bf, tid);
1418 * do not exceed aggregation limit
1420 al_delta = ATH_AGGR_DELIM_SZ + bf->bf_frmlen;
1422 if (nframes && (aggr_limit <
1423 (al + bpad + al_delta + prev_al))) {
1424 status = ATH_AGGR_LIMITED;
1429 * do not exceed subframe limit
1431 if ((nframes + *prev_frames) >=
1432 min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
1433 status = ATH_AGGR_LIMITED;
1438 * add padding for previous frame to aggregation length
1440 al += bpad + al_delta;
1443 * Get the delimiters needed to meet the MPDU
1444 * density for this node.
1446 ndelim = ath_compute_num_delims(sc, tid, bf_first, bf->bf_frmlen);
1448 bpad = PADBYTES(al_delta) + (ndelim << 2);
1451 bf->bf_lastfrm->bf_desc->ds_link = 0;
1454 * this packet is part of an aggregate
1455 * - remove all descriptors belonging to this frame from
1457 * - add it to block ack window
1458 * - set up descriptors for aggregation
1460 list_cut_position(&bf_head, &tid->buf_q, &bf->bf_lastfrm->list);
1461 ath_tx_addto_baw(sc, tid, bf);
1463 list_for_each_entry(tbf, &bf_head, list) {
1464 ath9k_hw_set11n_aggr_middle(sc->sc_ah,
1465 tbf->bf_desc, ndelim);
1469 * link buffers of this frame to the aggregate
1471 list_splice_tail_init(&bf_head, bf_q);
1475 bf_prev->bf_next = bf;
1476 bf_prev->bf_lastfrm->bf_desc->ds_link = bf->bf_daddr;
1482 * terminate aggregation on a small packet boundary
1484 if (bf->bf_frmlen < ATH_AGGR_MINPLEN) {
1485 status = ATH_AGGR_SHORTPKT;
1489 } while (!list_empty(&tid->buf_q));
1491 bf_first->bf_al = al;
1492 bf_first->bf_nframes = nframes;
1499 * process pending frames possibly doing a-mpdu aggregation
1500 * NB: must be called with txq lock held
1503 static void ath_tx_sched_aggr(struct ath_softc *sc,
1504 struct ath_txq *txq, struct ath_atx_tid *tid)
1506 struct ath_buf *bf, *tbf, *bf_last, *bf_lastaggr = NULL;
1507 enum ATH_AGGR_STATUS status;
1508 struct list_head bf_q;
1509 struct aggr_rifs_param param = {0, 0, 0, 0, NULL};
1510 int prev_frames = 0;
1513 if (list_empty(&tid->buf_q))
1516 INIT_LIST_HEAD(&bf_q);
1518 status = ath_tx_form_aggr(sc, tid, &bf_q, &bf_lastaggr, ¶m,
1522 * no frames picked up to be aggregated; block-ack
1523 * window is not open
1525 if (list_empty(&bf_q))
1528 bf = list_first_entry(&bf_q, struct ath_buf, list);
1529 bf_last = list_entry(bf_q.prev, struct ath_buf, list);
1530 bf->bf_lastbf = bf_last;
1533 * if only one frame, send as non-aggregate
1535 if (bf->bf_nframes == 1) {
1536 ASSERT(bf->bf_lastfrm == bf_last);
1538 bf->bf_state.bf_type &= ~BUF_AGGR;
1540 * clear aggr bits for every descriptor
1541 * XXX TODO: is there a way to optimize it?
1543 list_for_each_entry(tbf, &bf_q, list) {
1544 ath9k_hw_clr11n_aggr(sc->sc_ah, tbf->bf_desc);
1547 ath_buf_set_rate(sc, bf);
1548 ath_tx_txqaddbuf(sc, txq, &bf_q);
1553 * setup first desc with rate and aggr info
1555 bf->bf_state.bf_type |= BUF_AGGR;
1556 ath_buf_set_rate(sc, bf);
1557 ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al);
1560 * anchor last frame of aggregate correctly
1562 ASSERT(bf_lastaggr);
1563 ASSERT(bf_lastaggr->bf_lastfrm == bf_last);
1565 ath9k_hw_set11n_aggr_last(sc->sc_ah, tbf->bf_desc);
1567 /* XXX: We don't enter into this loop, consider removing this */
1568 while (!list_empty(&bf_q) && !list_is_last(&tbf->list, &bf_q)) {
1569 tbf = list_entry(tbf->list.next, struct ath_buf, list);
1570 ath9k_hw_set11n_aggr_last(sc->sc_ah, tbf->bf_desc);
1573 txq->axq_aggr_depth++;
1576 * Normal aggregate, queue to hardware
1578 ath_tx_txqaddbuf(sc, txq, &bf_q);
1580 } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH &&
1581 status != ATH_AGGR_BAW_CLOSED);
1584 /* Called with txq lock held */
1586 static void ath_tid_drain(struct ath_softc *sc,
1587 struct ath_txq *txq,
1588 struct ath_atx_tid *tid)
1592 struct list_head bf_head;
1593 INIT_LIST_HEAD(&bf_head);
1596 if (list_empty(&tid->buf_q))
1598 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
1600 list_cut_position(&bf_head, &tid->buf_q, &bf->bf_lastfrm->list);
1602 /* update baw for software retried frame */
1603 if (bf_isretried(bf))
1604 ath_tx_update_baw(sc, tid, bf->bf_seqno);
1607 * do not indicate packets while holding txq spinlock.
1608 * unlock is intentional here
1610 spin_unlock(&txq->axq_lock);
1612 /* complete this sub-frame */
1613 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
1615 spin_lock(&txq->axq_lock);
1619 * TODO: For frame(s) that are in the retry state, we will reuse the
1620 * sequence number(s) without setting the retry bit. The
1621 * alternative is to give up on these and BAR the receiver's window
1624 tid->seq_next = tid->seq_start;
1625 tid->baw_tail = tid->baw_head;
1629 * Drain all pending buffers
1630 * NB: must be called with txq lock held
1633 static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
1634 struct ath_txq *txq)
1636 struct ath_atx_ac *ac, *ac_tmp;
1637 struct ath_atx_tid *tid, *tid_tmp;
1639 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
1640 list_del(&ac->list);
1642 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
1643 list_del(&tid->list);
1645 ath_tid_drain(sc, txq, tid);
1650 static void ath_tx_setup_buffer(struct ath_softc *sc, struct ath_buf *bf,
1651 struct sk_buff *skb,
1652 struct ath_tx_control *txctl)
1654 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1655 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1656 struct ath_tx_info_priv *tx_info_priv;
1660 tx_info_priv = kzalloc(sizeof(*tx_info_priv), GFP_KERNEL);
1661 tx_info->rate_driver_data[0] = tx_info_priv;
1662 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1663 fc = hdr->frame_control;
1665 ATH_TXBUF_RESET(bf);
1669 bf->bf_frmlen = skb->len + FCS_LEN - (hdrlen & 3);
1671 ieee80211_is_data(fc) ?
1672 (bf->bf_state.bf_type |= BUF_DATA) :
1673 (bf->bf_state.bf_type &= ~BUF_DATA);
1674 ieee80211_is_back_req(fc) ?
1675 (bf->bf_state.bf_type |= BUF_BAR) :
1676 (bf->bf_state.bf_type &= ~BUF_BAR);
1677 ieee80211_is_pspoll(fc) ?
1678 (bf->bf_state.bf_type |= BUF_PSPOLL) :
1679 (bf->bf_state.bf_type &= ~BUF_PSPOLL);
1680 (sc->sc_flags & SC_OP_PREAMBLE_SHORT) ?
1681 (bf->bf_state.bf_type |= BUF_SHORT_PREAMBLE) :
1682 (bf->bf_state.bf_type &= ~BUF_SHORT_PREAMBLE);
1683 (sc->hw->conf.ht.enabled && !is_pae(skb) &&
1684 (tx_info->flags & IEEE80211_TX_CTL_AMPDU)) ?
1685 (bf->bf_state.bf_type |= BUF_HT) :
1686 (bf->bf_state.bf_type &= ~BUF_HT);
1688 bf->bf_flags = setup_tx_flags(sc, skb, txctl->txq);
1692 bf->bf_keytype = get_hw_crypto_keytype(skb);
1694 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) {
1695 bf->bf_frmlen += tx_info->control.hw_key->icv_len;
1696 bf->bf_keyix = tx_info->control.hw_key->hw_key_idx;
1698 bf->bf_keyix = ATH9K_TXKEYIX_INVALID;
1701 /* Assign seqno, tidno */
1703 if (bf_isht(bf) && (sc->sc_flags & SC_OP_TXAGGR))
1704 assign_aggr_tid_seqno(skb, bf);
1709 bf->bf_dmacontext = pci_map_single(sc->pdev, skb->data,
1710 skb->len, PCI_DMA_TODEVICE);
1711 bf->bf_buf_addr = bf->bf_dmacontext;
1714 /* FIXME: tx power */
1715 static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
1716 struct ath_tx_control *txctl)
1718 struct sk_buff *skb = (struct sk_buff *)bf->bf_mpdu;
1719 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1720 struct ath_node *an = NULL;
1721 struct list_head bf_head;
1722 struct ath_desc *ds;
1723 struct ath_atx_tid *tid;
1724 struct ath_hal *ah = sc->sc_ah;
1727 frm_type = get_hw_packet_type(skb);
1729 INIT_LIST_HEAD(&bf_head);
1730 list_add_tail(&bf->list, &bf_head);
1732 /* setup descriptor */
1736 ds->ds_data = bf->bf_buf_addr;
1738 /* Formulate first tx descriptor with tx controls */
1740 ath9k_hw_set11n_txdesc(ah, ds, bf->bf_frmlen, frm_type, MAX_RATE_POWER,
1741 bf->bf_keyix, bf->bf_keytype, bf->bf_flags);
1743 ath9k_hw_filltxdesc(ah, ds,
1744 skb->len, /* segment length */
1745 true, /* first segment */
1746 true, /* last segment */
1747 ds); /* first descriptor */
1749 bf->bf_lastfrm = bf;
1751 spin_lock_bh(&txctl->txq->axq_lock);
1753 if (bf_isht(bf) && (sc->sc_flags & SC_OP_TXAGGR) &&
1754 tx_info->control.sta) {
1755 an = (struct ath_node *)tx_info->control.sta->drv_priv;
1756 tid = ATH_AN_2_TID(an, bf->bf_tidno);
1758 if (ath_aggr_query(sc, an, bf->bf_tidno)) {
1760 * Try aggregation if it's a unicast data frame
1761 * and the destination is HT capable.
1763 ath_tx_send_ampdu(sc, tid, &bf_head, txctl);
1766 * Send this frame as regular when ADDBA
1767 * exchange is neither complete nor pending.
1769 ath_tx_send_normal(sc, txctl->txq,
1776 ath_buf_set_rate(sc, bf);
1777 ath_tx_txqaddbuf(sc, txctl->txq, &bf_head);
1780 spin_unlock_bh(&txctl->txq->axq_lock);
1783 int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb,
1784 struct ath_tx_control *txctl)
1788 /* Check if a tx buffer is available */
1790 bf = ath_tx_get_buffer(sc);
1792 DPRINTF(sc, ATH_DBG_XMIT, "%s: TX buffers are full\n",
1797 ath_tx_setup_buffer(sc, bf, skb, txctl);
1798 ath_tx_start_dma(sc, bf, txctl);
1803 /* Initialize TX queue and h/w */
1805 int ath_tx_init(struct ath_softc *sc, int nbufs)
1810 spin_lock_init(&sc->sc_txbuflock);
1812 /* Setup tx descriptors */
1813 error = ath_descdma_setup(sc, &sc->sc_txdma, &sc->sc_txbuf,
1816 DPRINTF(sc, ATH_DBG_FATAL,
1817 "%s: failed to allocate tx descriptors: %d\n",
1822 /* XXX allocate beacon state together with vap */
1823 error = ath_descdma_setup(sc, &sc->sc_bdma, &sc->sc_bbuf,
1824 "beacon", ATH_BCBUF, 1);
1826 DPRINTF(sc, ATH_DBG_FATAL,
1827 "%s: failed to allocate "
1828 "beacon descripotrs: %d\n",
1841 /* Reclaim all tx queue resources */
1843 int ath_tx_cleanup(struct ath_softc *sc)
1845 /* cleanup beacon descriptors */
1846 if (sc->sc_bdma.dd_desc_len != 0)
1847 ath_descdma_cleanup(sc, &sc->sc_bdma, &sc->sc_bbuf);
1849 /* cleanup tx descriptors */
1850 if (sc->sc_txdma.dd_desc_len != 0)
1851 ath_descdma_cleanup(sc, &sc->sc_txdma, &sc->sc_txbuf);
1856 /* Setup a h/w transmit queue */
1858 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1860 struct ath_hal *ah = sc->sc_ah;
1861 struct ath9k_tx_queue_info qi;
1864 memset(&qi, 0, sizeof(qi));
1865 qi.tqi_subtype = subtype;
1866 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1867 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1868 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1869 qi.tqi_physCompBuf = 0;
1872 * Enable interrupts only for EOL and DESC conditions.
1873 * We mark tx descriptors to receive a DESC interrupt
1874 * when a tx queue gets deep; otherwise waiting for the
1875 * EOL to reap descriptors. Note that this is done to
1876 * reduce interrupt load and this only defers reaping
1877 * descriptors, never transmitting frames. Aside from
1878 * reducing interrupts this also permits more concurrency.
1879 * The only potential downside is if the tx queue backs
1880 * up in which case the top half of the kernel may backup
1881 * due to a lack of tx descriptors.
1883 * The UAPSD queue is an exception, since we take a desc-
1884 * based intr on the EOSP frames.
1886 if (qtype == ATH9K_TX_QUEUE_UAPSD)
1887 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1889 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1890 TXQ_FLAG_TXDESCINT_ENABLE;
1891 qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1894 * NB: don't print a message, this happens
1895 * normally on parts with too few tx queues
1899 if (qnum >= ARRAY_SIZE(sc->sc_txq)) {
1900 DPRINTF(sc, ATH_DBG_FATAL,
1901 "%s: hal qnum %u out of range, max %u!\n",
1902 __func__, qnum, (unsigned int)ARRAY_SIZE(sc->sc_txq));
1903 ath9k_hw_releasetxqueue(ah, qnum);
1906 if (!ATH_TXQ_SETUP(sc, qnum)) {
1907 struct ath_txq *txq = &sc->sc_txq[qnum];
1909 txq->axq_qnum = qnum;
1910 txq->axq_link = NULL;
1911 INIT_LIST_HEAD(&txq->axq_q);
1912 INIT_LIST_HEAD(&txq->axq_acq);
1913 spin_lock_init(&txq->axq_lock);
1915 txq->axq_aggr_depth = 0;
1916 txq->axq_totalqueued = 0;
1917 txq->axq_linkbuf = NULL;
1918 sc->sc_txqsetup |= 1<<qnum;
1920 return &sc->sc_txq[qnum];
1923 /* Reclaim resources for a setup queue */
1925 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1927 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1928 sc->sc_txqsetup &= ~(1<<txq->axq_qnum);
1932 * Setup a hardware data transmit queue for the specified
1933 * access control. The hal may not support all requested
1934 * queues in which case it will return a reference to a
1935 * previously setup queue. We record the mapping from ac's
1936 * to h/w queues for use by ath_tx_start and also track
1937 * the set of h/w queues being used to optimize work in the
1938 * transmit interrupt handler and related routines.
1941 int ath_tx_setup(struct ath_softc *sc, int haltype)
1943 struct ath_txq *txq;
1945 if (haltype >= ARRAY_SIZE(sc->sc_haltype2q)) {
1946 DPRINTF(sc, ATH_DBG_FATAL,
1947 "%s: HAL AC %u out of range, max %zu!\n",
1948 __func__, haltype, ARRAY_SIZE(sc->sc_haltype2q));
1951 txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype);
1953 sc->sc_haltype2q[haltype] = txq->axq_qnum;
1959 int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype)
1964 case ATH9K_TX_QUEUE_DATA:
1965 if (haltype >= ARRAY_SIZE(sc->sc_haltype2q)) {
1966 DPRINTF(sc, ATH_DBG_FATAL,
1967 "%s: HAL AC %u out of range, max %zu!\n",
1969 haltype, ARRAY_SIZE(sc->sc_haltype2q));
1972 qnum = sc->sc_haltype2q[haltype];
1974 case ATH9K_TX_QUEUE_BEACON:
1975 qnum = sc->sc_bhalq;
1977 case ATH9K_TX_QUEUE_CAB:
1978 qnum = sc->sc_cabq->axq_qnum;
1986 /* Get a transmit queue, if available */
1988 struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb)
1990 struct ath_txq *txq = NULL;
1993 qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc);
1994 txq = &sc->sc_txq[qnum];
1996 spin_lock_bh(&txq->axq_lock);
1998 /* Try to avoid running out of descriptors */
1999 if (txq->axq_depth >= (ATH_TXBUF - 20)) {
2000 DPRINTF(sc, ATH_DBG_FATAL,
2001 "%s: TX queue: %d is full, depth: %d\n",
2002 __func__, qnum, txq->axq_depth);
2003 ieee80211_stop_queue(sc->hw, skb_get_queue_mapping(skb));
2005 spin_unlock_bh(&txq->axq_lock);
2009 spin_unlock_bh(&txq->axq_lock);
2014 /* Update parameters for a transmit queue */
2016 int ath_txq_update(struct ath_softc *sc, int qnum,
2017 struct ath9k_tx_queue_info *qinfo)
2019 struct ath_hal *ah = sc->sc_ah;
2021 struct ath9k_tx_queue_info qi;
2023 if (qnum == sc->sc_bhalq) {
2025 * XXX: for beacon queue, we just save the parameter.
2026 * It will be picked up by ath_beaconq_config when
2029 sc->sc_beacon_qi = *qinfo;
2033 ASSERT(sc->sc_txq[qnum].axq_qnum == qnum);
2035 ath9k_hw_get_txq_props(ah, qnum, &qi);
2036 qi.tqi_aifs = qinfo->tqi_aifs;
2037 qi.tqi_cwmin = qinfo->tqi_cwmin;
2038 qi.tqi_cwmax = qinfo->tqi_cwmax;
2039 qi.tqi_burstTime = qinfo->tqi_burstTime;
2040 qi.tqi_readyTime = qinfo->tqi_readyTime;
2042 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
2043 DPRINTF(sc, ATH_DBG_FATAL,
2044 "%s: unable to update hardware queue %u!\n",
2048 ath9k_hw_resettxqueue(ah, qnum); /* push to h/w */
2054 int ath_cabq_update(struct ath_softc *sc)
2056 struct ath9k_tx_queue_info qi;
2057 int qnum = sc->sc_cabq->axq_qnum;
2058 struct ath_beacon_config conf;
2060 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
2062 * Ensure the readytime % is within the bounds.
2064 if (sc->sc_config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
2065 sc->sc_config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
2066 else if (sc->sc_config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
2067 sc->sc_config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
2069 ath_get_beaconconfig(sc, ATH_IF_ID_ANY, &conf);
2071 (conf.beacon_interval * sc->sc_config.cabqReadytime) / 100;
2072 ath_txq_update(sc, qnum, &qi);
2077 /* Deferred processing of transmit interrupt */
2079 void ath_tx_tasklet(struct ath_softc *sc)
2082 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
2084 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
2087 * Process each active queue.
2089 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2090 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2091 ath_tx_processq(sc, &sc->sc_txq[i]);
2095 void ath_tx_draintxq(struct ath_softc *sc,
2096 struct ath_txq *txq, bool retry_tx)
2098 struct ath_buf *bf, *lastbf;
2099 struct list_head bf_head;
2101 INIT_LIST_HEAD(&bf_head);
2104 * NB: this assumes output has been stopped and
2105 * we do not need to block ath_tx_tasklet
2108 spin_lock_bh(&txq->axq_lock);
2110 if (list_empty(&txq->axq_q)) {
2111 txq->axq_link = NULL;
2112 txq->axq_linkbuf = NULL;
2113 spin_unlock_bh(&txq->axq_lock);
2117 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2119 if (bf->bf_status & ATH_BUFSTATUS_STALE) {
2120 list_del(&bf->list);
2121 spin_unlock_bh(&txq->axq_lock);
2123 spin_lock_bh(&sc->sc_txbuflock);
2124 list_add_tail(&bf->list, &sc->sc_txbuf);
2125 spin_unlock_bh(&sc->sc_txbuflock);
2129 lastbf = bf->bf_lastbf;
2131 lastbf->bf_desc->ds_txstat.ts_flags =
2132 ATH9K_TX_SW_ABORTED;
2134 /* remove ath_buf's of the same mpdu from txq */
2135 list_cut_position(&bf_head, &txq->axq_q, &lastbf->list);
2138 spin_unlock_bh(&txq->axq_lock);
2141 ath_tx_complete_aggr_rifs(sc, txq, bf, &bf_head, 0);
2143 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
2146 /* flush any pending frames if aggregation is enabled */
2147 if (sc->sc_flags & SC_OP_TXAGGR) {
2149 spin_lock_bh(&txq->axq_lock);
2150 ath_txq_drain_pending_buffers(sc, txq);
2151 spin_unlock_bh(&txq->axq_lock);
2156 /* Drain the transmit queues and reclaim resources */
2158 void ath_draintxq(struct ath_softc *sc, bool retry_tx)
2160 /* stop beacon queue. The beacon will be freed when
2161 * we go to INIT state */
2162 if (!(sc->sc_flags & SC_OP_INVALID)) {
2163 (void) ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
2164 DPRINTF(sc, ATH_DBG_XMIT, "%s: beacon queue %x\n", __func__,
2165 ath9k_hw_gettxbuf(sc->sc_ah, sc->sc_bhalq));
2168 ath_drain_txdataq(sc, retry_tx);
2171 u32 ath_txq_depth(struct ath_softc *sc, int qnum)
2173 return sc->sc_txq[qnum].axq_depth;
2176 u32 ath_txq_aggr_depth(struct ath_softc *sc, int qnum)
2178 return sc->sc_txq[qnum].axq_aggr_depth;
2181 bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno)
2183 struct ath_atx_tid *txtid;
2185 if (!(sc->sc_flags & SC_OP_TXAGGR))
2188 txtid = ATH_AN_2_TID(an, tidno);
2190 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
2191 if (!(txtid->state & AGGR_ADDBA_PROGRESS) &&
2192 (txtid->addba_exchangeattempts < ADDBA_EXCHANGE_ATTEMPTS)) {
2193 txtid->addba_exchangeattempts++;
2201 /* Start TX aggregation */
2203 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
2206 struct ath_atx_tid *txtid;
2207 struct ath_node *an;
2209 an = (struct ath_node *)sta->drv_priv;
2211 if (sc->sc_flags & SC_OP_TXAGGR) {
2212 txtid = ATH_AN_2_TID(an, tid);
2213 txtid->state |= AGGR_ADDBA_PROGRESS;
2214 ath_tx_pause_tid(sc, txtid);
2220 /* Stop tx aggregation */
2222 int ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
2224 struct ath_node *an = (struct ath_node *)sta->drv_priv;
2226 ath_tx_aggr_teardown(sc, an, tid);
2230 /* Resume tx aggregation */
2232 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
2234 struct ath_atx_tid *txtid;
2235 struct ath_node *an;
2237 an = (struct ath_node *)sta->drv_priv;
2239 if (sc->sc_flags & SC_OP_TXAGGR) {
2240 txtid = ATH_AN_2_TID(an, tid);
2242 IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
2243 txtid->state |= AGGR_ADDBA_COMPLETE;
2244 txtid->state &= ~AGGR_ADDBA_PROGRESS;
2245 ath_tx_resume_tid(sc, txtid);
2250 * Performs transmit side cleanup when TID changes from aggregated to
2252 * - Pause the TID and mark cleanup in progress
2253 * - Discard all retry frames from the s/w queue.
2256 void ath_tx_aggr_teardown(struct ath_softc *sc, struct ath_node *an, u8 tid)
2258 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
2259 struct ath_txq *txq = &sc->sc_txq[txtid->ac->qnum];
2261 struct list_head bf_head;
2262 INIT_LIST_HEAD(&bf_head);
2264 DPRINTF(sc, ATH_DBG_AGGR, "%s: teardown TX aggregation\n", __func__);
2266 if (txtid->state & AGGR_CLEANUP) /* cleanup is in progress */
2269 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
2270 txtid->addba_exchangeattempts = 0;
2274 /* TID must be paused first */
2275 ath_tx_pause_tid(sc, txtid);
2277 /* drop all software retried frames and mark this TID */
2278 spin_lock_bh(&txq->axq_lock);
2279 while (!list_empty(&txtid->buf_q)) {
2280 bf = list_first_entry(&txtid->buf_q, struct ath_buf, list);
2281 if (!bf_isretried(bf)) {
2283 * NB: it's based on the assumption that
2284 * software retried frame will always stay
2285 * at the head of software queue.
2289 list_cut_position(&bf_head,
2290 &txtid->buf_q, &bf->bf_lastfrm->list);
2291 ath_tx_update_baw(sc, txtid, bf->bf_seqno);
2293 /* complete this sub-frame */
2294 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
2297 if (txtid->baw_head != txtid->baw_tail) {
2298 spin_unlock_bh(&txq->axq_lock);
2299 txtid->state |= AGGR_CLEANUP;
2301 txtid->state &= ~AGGR_ADDBA_COMPLETE;
2302 txtid->addba_exchangeattempts = 0;
2303 spin_unlock_bh(&txq->axq_lock);
2304 ath_tx_flush_tid(sc, txtid);
2309 * Tx scheduling logic
2310 * NB: must be called with txq lock held
2313 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
2315 struct ath_atx_ac *ac;
2316 struct ath_atx_tid *tid;
2318 /* nothing to schedule */
2319 if (list_empty(&txq->axq_acq))
2322 * get the first node/ac pair on the queue
2324 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
2325 list_del(&ac->list);
2329 * process a single tid per destination
2332 /* nothing to schedule */
2333 if (list_empty(&ac->tid_q))
2336 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, list);
2337 list_del(&tid->list);
2340 if (tid->paused) /* check next tid to keep h/w busy */
2343 if ((txq->axq_depth % 2) == 0)
2344 ath_tx_sched_aggr(sc, txq, tid);
2347 * add tid to round-robin queue if more frames
2348 * are pending for the tid
2350 if (!list_empty(&tid->buf_q))
2351 ath_tx_queue_tid(txq, tid);
2353 /* only schedule one TID at a time */
2355 } while (!list_empty(&ac->tid_q));
2358 * schedule AC if more TIDs need processing
2360 if (!list_empty(&ac->tid_q)) {
2362 * add dest ac to txq if not already added
2366 list_add_tail(&ac->list, &txq->axq_acq);
2371 /* Initialize per-node transmit state */
2373 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2375 struct ath_atx_tid *tid;
2376 struct ath_atx_ac *ac;
2380 * Init per tid tx state
2382 for (tidno = 0, tid = &an->an_aggr.tx.tid[tidno];
2383 tidno < WME_NUM_TID;
2387 tid->seq_start = tid->seq_next = 0;
2388 tid->baw_size = WME_MAX_BA;
2389 tid->baw_head = tid->baw_tail = 0;
2391 tid->paused = false;
2392 tid->state &= ~AGGR_CLEANUP;
2393 INIT_LIST_HEAD(&tid->buf_q);
2395 acno = TID_TO_WME_AC(tidno);
2396 tid->ac = &an->an_aggr.tx.ac[acno];
2399 tid->state &= ~AGGR_ADDBA_COMPLETE;
2400 tid->state &= ~AGGR_ADDBA_PROGRESS;
2401 tid->addba_exchangeattempts = 0;
2405 * Init per ac tx state
2407 for (acno = 0, ac = &an->an_aggr.tx.ac[acno];
2408 acno < WME_NUM_AC; acno++, ac++) {
2410 INIT_LIST_HEAD(&ac->tid_q);
2414 ac->qnum = ath_tx_get_qnum(sc,
2415 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
2418 ac->qnum = ath_tx_get_qnum(sc,
2419 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BK);
2422 ac->qnum = ath_tx_get_qnum(sc,
2423 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VI);
2426 ac->qnum = ath_tx_get_qnum(sc,
2427 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VO);
2433 /* Cleanupthe pending buffers for the node. */
2435 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2438 struct ath_atx_ac *ac, *ac_tmp;
2439 struct ath_atx_tid *tid, *tid_tmp;
2440 struct ath_txq *txq;
2441 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2442 if (ATH_TXQ_SETUP(sc, i)) {
2443 txq = &sc->sc_txq[i];
2445 spin_lock(&txq->axq_lock);
2447 list_for_each_entry_safe(ac,
2448 ac_tmp, &txq->axq_acq, list) {
2449 tid = list_first_entry(&ac->tid_q,
2450 struct ath_atx_tid, list);
2451 if (tid && tid->an != an)
2453 list_del(&ac->list);
2456 list_for_each_entry_safe(tid,
2457 tid_tmp, &ac->tid_q, list) {
2458 list_del(&tid->list);
2460 ath_tid_drain(sc, txq, tid);
2461 tid->state &= ~AGGR_ADDBA_COMPLETE;
2462 tid->addba_exchangeattempts = 0;
2463 tid->state &= ~AGGR_CLEANUP;
2467 spin_unlock(&txq->axq_lock);
2472 void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb)
2474 int hdrlen, padsize;
2475 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2476 struct ath_tx_control txctl;
2478 memset(&txctl, 0, sizeof(struct ath_tx_control));
2481 * As a temporary workaround, assign seq# here; this will likely need
2482 * to be cleaned up to work better with Beacon transmission and virtual
2485 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2486 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2487 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2489 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2490 hdr->seq_ctrl |= cpu_to_le16(sc->seq_no);
2493 /* Add the padding after the header if this is not already done */
2494 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2496 padsize = hdrlen % 4;
2497 if (skb_headroom(skb) < padsize) {
2498 DPRINTF(sc, ATH_DBG_XMIT, "%s: TX CABQ padding "
2499 "failed\n", __func__);
2500 dev_kfree_skb_any(skb);
2503 skb_push(skb, padsize);
2504 memmove(skb->data, skb->data + padsize, hdrlen);
2507 txctl.txq = sc->sc_cabq;
2509 DPRINTF(sc, ATH_DBG_XMIT, "%s: transmitting CABQ packet, skb: %p\n",
2513 if (ath_tx_start(sc, skb, &txctl) != 0) {
2514 DPRINTF(sc, ATH_DBG_XMIT, "%s: TX failed\n", __func__);
2520 dev_kfree_skb_any(skb);