2 * Copyright (c) 2008 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 #define BITS_PER_BYTE 8
20 #define OFDM_PLCP_BITS 22
21 #define HT_RC_2_MCS(_rc) ((_rc) & 0x0f)
22 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
28 #define HT_LTF(_ns) (4 * (_ns))
29 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
30 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
31 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
32 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
34 #define OFDM_SIFS_TIME 16
36 static u32 bits_per_symbol[][2] = {
38 { 26, 54 }, /* 0: BPSK */
39 { 52, 108 }, /* 1: QPSK 1/2 */
40 { 78, 162 }, /* 2: QPSK 3/4 */
41 { 104, 216 }, /* 3: 16-QAM 1/2 */
42 { 156, 324 }, /* 4: 16-QAM 3/4 */
43 { 208, 432 }, /* 5: 64-QAM 2/3 */
44 { 234, 486 }, /* 6: 64-QAM 3/4 */
45 { 260, 540 }, /* 7: 64-QAM 5/6 */
46 { 52, 108 }, /* 8: BPSK */
47 { 104, 216 }, /* 9: QPSK 1/2 */
48 { 156, 324 }, /* 10: QPSK 3/4 */
49 { 208, 432 }, /* 11: 16-QAM 1/2 */
50 { 312, 648 }, /* 12: 16-QAM 3/4 */
51 { 416, 864 }, /* 13: 64-QAM 2/3 */
52 { 468, 972 }, /* 14: 64-QAM 3/4 */
53 { 520, 1080 }, /* 15: 64-QAM 5/6 */
56 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
58 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
59 struct ath_atx_tid *tid,
60 struct list_head *bf_head);
61 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
62 struct list_head *bf_q,
63 int txok, int sendbar);
64 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
65 struct list_head *head);
66 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf);
68 /*********************/
69 /* Aggregation logic */
70 /*********************/
72 static int ath_aggr_query(struct ath_softc *sc, struct ath_node *an, u8 tidno)
74 struct ath_atx_tid *tid;
75 tid = ATH_AN_2_TID(an, tidno);
77 if (tid->state & AGGR_ADDBA_COMPLETE ||
78 tid->state & AGGR_ADDBA_PROGRESS)
84 static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
86 struct ath_atx_ac *ac = tid->ac;
95 list_add_tail(&tid->list, &ac->tid_q);
101 list_add_tail(&ac->list, &txq->axq_acq);
104 static void ath_tx_pause_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
106 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
108 spin_lock_bh(&txq->axq_lock);
110 spin_unlock_bh(&txq->axq_lock);
113 static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
115 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
117 ASSERT(tid->paused > 0);
118 spin_lock_bh(&txq->axq_lock);
125 if (list_empty(&tid->buf_q))
128 ath_tx_queue_tid(txq, tid);
129 ath_txq_schedule(sc, txq);
131 spin_unlock_bh(&txq->axq_lock);
134 static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
136 struct ath_txq *txq = &sc->tx.txq[tid->ac->qnum];
138 struct list_head bf_head;
139 INIT_LIST_HEAD(&bf_head);
141 ASSERT(tid->paused > 0);
142 spin_lock_bh(&txq->axq_lock);
146 if (tid->paused > 0) {
147 spin_unlock_bh(&txq->axq_lock);
151 while (!list_empty(&tid->buf_q)) {
152 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
153 ASSERT(!bf_isretried(bf));
154 list_move_tail(&bf->list, &bf_head);
155 ath_tx_send_normal(sc, txq, tid, &bf_head);
158 spin_unlock_bh(&txq->axq_lock);
161 static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
166 index = ATH_BA_INDEX(tid->seq_start, seqno);
167 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
169 tid->tx_buf[cindex] = NULL;
171 while (tid->baw_head != tid->baw_tail && !tid->tx_buf[tid->baw_head]) {
172 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
173 INCR(tid->baw_head, ATH_TID_MAX_BUFS);
177 static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
182 if (bf_isretried(bf))
185 index = ATH_BA_INDEX(tid->seq_start, bf->bf_seqno);
186 cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
188 ASSERT(tid->tx_buf[cindex] == NULL);
189 tid->tx_buf[cindex] = bf;
191 if (index >= ((tid->baw_tail - tid->baw_head) &
192 (ATH_TID_MAX_BUFS - 1))) {
193 tid->baw_tail = cindex;
194 INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
199 * TODO: For frame(s) that are in the retry state, we will reuse the
200 * sequence number(s) without setting the retry bit. The
201 * alternative is to give up on these and BAR the receiver's window
204 static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
205 struct ath_atx_tid *tid)
209 struct list_head bf_head;
210 INIT_LIST_HEAD(&bf_head);
213 if (list_empty(&tid->buf_q))
216 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
217 list_move_tail(&bf->list, &bf_head);
219 if (bf_isretried(bf))
220 ath_tx_update_baw(sc, tid, bf->bf_seqno);
222 spin_unlock(&txq->axq_lock);
223 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
224 spin_lock(&txq->axq_lock);
227 tid->seq_next = tid->seq_start;
228 tid->baw_tail = tid->baw_head;
231 static void ath_tx_set_retry(struct ath_softc *sc, struct ath_buf *bf)
234 struct ieee80211_hdr *hdr;
236 bf->bf_state.bf_type |= BUF_RETRY;
240 hdr = (struct ieee80211_hdr *)skb->data;
241 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
244 static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
248 spin_lock_bh(&sc->tx.txbuflock);
249 ASSERT(!list_empty((&sc->tx.txbuf)));
250 tbf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
251 list_del(&tbf->list);
252 spin_unlock_bh(&sc->tx.txbuflock);
254 ATH_TXBUF_RESET(tbf);
256 tbf->bf_mpdu = bf->bf_mpdu;
257 tbf->bf_buf_addr = bf->bf_buf_addr;
258 *(tbf->bf_desc) = *(bf->bf_desc);
259 tbf->bf_state = bf->bf_state;
260 tbf->bf_dmacontext = bf->bf_dmacontext;
265 static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
266 struct ath_buf *bf, struct list_head *bf_q,
269 struct ath_node *an = NULL;
271 struct ieee80211_sta *sta;
272 struct ieee80211_hdr *hdr;
273 struct ath_atx_tid *tid = NULL;
274 struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
275 struct ath_desc *ds = bf_last->bf_desc;
276 struct list_head bf_head, bf_pending;
278 u32 ba[WME_BA_BMP_SIZE >> 5];
279 int isaggr, txfail, txpending, sendbar = 0, needreset = 0;
281 skb = (struct sk_buff *)bf->bf_mpdu;
282 hdr = (struct ieee80211_hdr *)skb->data;
286 sta = ieee80211_find_sta(sc->hw, hdr->addr1);
292 an = (struct ath_node *)sta->drv_priv;
293 tid = ATH_AN_2_TID(an, bf->bf_tidno);
295 isaggr = bf_isaggr(bf);
296 memset(ba, 0, WME_BA_BMP_SIZE >> 3);
298 if (isaggr && txok) {
299 if (ATH_DS_TX_BA(ds)) {
300 seq_st = ATH_DS_BA_SEQ(ds);
301 memcpy(ba, ATH_DS_BA_BITMAP(ds),
302 WME_BA_BMP_SIZE >> 3);
305 * AR5416 can become deaf/mute when BA
306 * issue happens. Chip needs to be reset.
307 * But AP code may have sychronization issues
308 * when perform internal reset in this routine.
309 * Only enable reset in STA mode for now.
311 if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
316 INIT_LIST_HEAD(&bf_pending);
317 INIT_LIST_HEAD(&bf_head);
320 txfail = txpending = 0;
321 bf_next = bf->bf_next;
323 if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, bf->bf_seqno))) {
324 /* transmit completion, subframe is
325 * acked by block ack */
326 } else if (!isaggr && txok) {
327 /* transmit completion */
329 if (!(tid->state & AGGR_CLEANUP) &&
330 ds->ds_txstat.ts_flags != ATH9K_TX_SW_ABORTED) {
331 if (bf->bf_retries < ATH_MAX_SW_RETRIES) {
332 ath_tx_set_retry(sc, bf);
335 bf->bf_state.bf_type |= BUF_XRETRY;
341 * cleanup in progress, just fail
342 * the un-acked sub-frames
348 if (bf_next == NULL) {
349 INIT_LIST_HEAD(&bf_head);
351 ASSERT(!list_empty(bf_q));
352 list_move_tail(&bf->list, &bf_head);
357 * complete the acked-ones/xretried ones; update
360 spin_lock_bh(&txq->axq_lock);
361 ath_tx_update_baw(sc, tid, bf->bf_seqno);
362 spin_unlock_bh(&txq->axq_lock);
364 ath_tx_complete_buf(sc, bf, &bf_head, !txfail, sendbar);
366 /* retry the un-acked ones */
367 if (bf->bf_next == NULL &&
368 bf_last->bf_status & ATH_BUFSTATUS_STALE) {
371 tbf = ath_clone_txbuf(sc, bf_last);
372 ath9k_hw_cleartxdesc(sc->sc_ah, tbf->bf_desc);
373 list_add_tail(&tbf->list, &bf_head);
376 * Clear descriptor status words for
379 ath9k_hw_cleartxdesc(sc->sc_ah, bf->bf_desc);
383 * Put this buffer to the temporary pending
384 * queue to retain ordering
386 list_splice_tail_init(&bf_head, &bf_pending);
392 if (tid->state & AGGR_CLEANUP) {
393 if (tid->baw_head == tid->baw_tail) {
394 tid->state &= ~AGGR_ADDBA_COMPLETE;
395 tid->addba_exchangeattempts = 0;
396 tid->state &= ~AGGR_CLEANUP;
398 /* send buffered frames as singles */
399 ath_tx_flush_tid(sc, tid);
405 /* prepend un-acked frames to the beginning of the pending frame queue */
406 if (!list_empty(&bf_pending)) {
407 spin_lock_bh(&txq->axq_lock);
408 list_splice(&bf_pending, &tid->buf_q);
409 ath_tx_queue_tid(txq, tid);
410 spin_unlock_bh(&txq->axq_lock);
416 ath_reset(sc, false);
419 static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
420 struct ath_atx_tid *tid)
422 struct ath_rate_table *rate_table = sc->cur_rate_table;
424 struct ieee80211_tx_info *tx_info;
425 struct ieee80211_tx_rate *rates;
426 struct ath_tx_info_priv *tx_info_priv;
427 u32 max_4ms_framelen, frmlen;
428 u16 aggr_limit, legacy = 0, maxampdu;
431 skb = (struct sk_buff *)bf->bf_mpdu;
432 tx_info = IEEE80211_SKB_CB(skb);
433 rates = tx_info->control.rates;
434 tx_info_priv = (struct ath_tx_info_priv *)tx_info->rate_driver_data[0];
437 * Find the lowest frame length among the rate series that will have a
438 * 4ms transmit duration.
439 * TODO - TXOP limit needs to be considered.
441 max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
443 for (i = 0; i < 4; i++) {
444 if (rates[i].count) {
445 if (!WLAN_RC_PHY_HT(rate_table->info[rates[i].idx].phy)) {
450 frmlen = rate_table->info[rates[i].idx].max_4ms_framelen;
451 max_4ms_framelen = min(max_4ms_framelen, frmlen);
456 * limit aggregate size by the minimum rate if rate selected is
457 * not a probe rate, if rate selected is a probe rate then
458 * avoid aggregation of this packet.
460 if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
463 aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_DEFAULT);
466 * h/w can accept aggregates upto 16 bit lengths (65535).
467 * The IE, however can hold upto 65536, which shows up here
468 * as zero. Ignore 65536 since we are constrained by hw.
470 maxampdu = tid->an->maxampdu;
472 aggr_limit = min(aggr_limit, maxampdu);
478 * Returns the number of delimiters to be added to
479 * meet the minimum required mpdudensity.
480 * caller should make sure that the rate is HT rate .
482 static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
483 struct ath_buf *bf, u16 frmlen)
485 struct ath_rate_table *rt = sc->cur_rate_table;
486 struct sk_buff *skb = bf->bf_mpdu;
487 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
488 u32 nsymbits, nsymbols, mpdudensity;
491 int width, half_gi, ndelim, mindelim;
493 /* Select standard number of delimiters based on frame length alone */
494 ndelim = ATH_AGGR_GET_NDELIM(frmlen);
497 * If encryption enabled, hardware requires some more padding between
499 * TODO - this could be improved to be dependent on the rate.
500 * The hardware can keep up at lower rates, but not higher rates
502 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR)
503 ndelim += ATH_AGGR_ENCRYPTDELIM;
506 * Convert desired mpdu density from microeconds to bytes based
507 * on highest rate in rate series (i.e. first rate) to determine
508 * required minimum length for subframe. Take into account
509 * whether high rate is 20 or 40Mhz and half or full GI.
511 mpdudensity = tid->an->mpdudensity;
514 * If there is no mpdu density restriction, no further calculation
517 if (mpdudensity == 0)
520 rix = tx_info->control.rates[0].idx;
521 flags = tx_info->control.rates[0].flags;
522 rc = rt->info[rix].ratecode;
523 width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
524 half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
527 nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(mpdudensity);
529 nsymbols = NUM_SYMBOLS_PER_USEC(mpdudensity);
534 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width];
535 minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
537 if (frmlen < minlen) {
538 mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
539 ndelim = max(mindelim, ndelim);
545 static enum ATH_AGGR_STATUS ath_tx_form_aggr(struct ath_softc *sc,
546 struct ath_atx_tid *tid,
547 struct list_head *bf_q)
549 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
550 struct ath_buf *bf, *bf_first, *bf_prev = NULL;
551 int rl = 0, nframes = 0, ndelim, prev_al = 0;
552 u16 aggr_limit = 0, al = 0, bpad = 0,
553 al_delta, h_baw = tid->baw_size / 2;
554 enum ATH_AGGR_STATUS status = ATH_AGGR_DONE;
556 bf_first = list_first_entry(&tid->buf_q, struct ath_buf, list);
559 bf = list_first_entry(&tid->buf_q, struct ath_buf, list);
561 /* do not step over block-ack window */
562 if (!BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno)) {
563 status = ATH_AGGR_BAW_CLOSED;
568 aggr_limit = ath_lookup_rate(sc, bf, tid);
572 /* do not exceed aggregation limit */
573 al_delta = ATH_AGGR_DELIM_SZ + bf->bf_frmlen;
576 (aggr_limit < (al + bpad + al_delta + prev_al))) {
577 status = ATH_AGGR_LIMITED;
581 /* do not exceed subframe limit */
582 if (nframes >= min((int)h_baw, ATH_AMPDU_SUBFRAME_DEFAULT)) {
583 status = ATH_AGGR_LIMITED;
588 /* add padding for previous frame to aggregation length */
589 al += bpad + al_delta;
592 * Get the delimiters needed to meet the MPDU
593 * density for this node.
595 ndelim = ath_compute_num_delims(sc, tid, bf_first, bf->bf_frmlen);
596 bpad = PADBYTES(al_delta) + (ndelim << 2);
599 bf->bf_desc->ds_link = 0;
601 /* link buffers of this frame to the aggregate */
602 ath_tx_addto_baw(sc, tid, bf);
603 ath9k_hw_set11n_aggr_middle(sc->sc_ah, bf->bf_desc, ndelim);
604 list_move_tail(&bf->list, bf_q);
606 bf_prev->bf_next = bf;
607 bf_prev->bf_desc->ds_link = bf->bf_daddr;
610 } while (!list_empty(&tid->buf_q));
612 bf_first->bf_al = al;
613 bf_first->bf_nframes = nframes;
619 static void ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
620 struct ath_atx_tid *tid)
623 enum ATH_AGGR_STATUS status;
624 struct list_head bf_q;
627 if (list_empty(&tid->buf_q))
630 INIT_LIST_HEAD(&bf_q);
632 status = ath_tx_form_aggr(sc, tid, &bf_q);
635 * no frames picked up to be aggregated;
636 * block-ack window is not open.
638 if (list_empty(&bf_q))
641 bf = list_first_entry(&bf_q, struct ath_buf, list);
642 bf->bf_lastbf = list_entry(bf_q.prev, struct ath_buf, list);
644 /* if only one frame, send as non-aggregate */
645 if (bf->bf_nframes == 1) {
646 bf->bf_state.bf_type &= ~BUF_AGGR;
647 ath9k_hw_clr11n_aggr(sc->sc_ah, bf->bf_desc);
648 ath_buf_set_rate(sc, bf);
649 ath_tx_txqaddbuf(sc, txq, &bf_q);
653 /* setup first desc of aggregate */
654 bf->bf_state.bf_type |= BUF_AGGR;
655 ath_buf_set_rate(sc, bf);
656 ath9k_hw_set11n_aggr_first(sc->sc_ah, bf->bf_desc, bf->bf_al);
658 /* anchor last desc of aggregate */
659 ath9k_hw_set11n_aggr_last(sc->sc_ah, bf->bf_lastbf->bf_desc);
661 txq->axq_aggr_depth++;
662 ath_tx_txqaddbuf(sc, txq, &bf_q);
664 } while (txq->axq_depth < ATH_AGGR_MIN_QDEPTH &&
665 status != ATH_AGGR_BAW_CLOSED);
668 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
671 struct ath_atx_tid *txtid;
674 an = (struct ath_node *)sta->drv_priv;
676 if (sc->sc_flags & SC_OP_TXAGGR) {
677 txtid = ATH_AN_2_TID(an, tid);
678 txtid->state |= AGGR_ADDBA_PROGRESS;
679 ath_tx_pause_tid(sc, txtid);
680 *ssn = txtid->seq_start;
686 int ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
688 struct ath_node *an = (struct ath_node *)sta->drv_priv;
689 struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
690 struct ath_txq *txq = &sc->tx.txq[txtid->ac->qnum];
692 struct list_head bf_head;
693 INIT_LIST_HEAD(&bf_head);
695 if (txtid->state & AGGR_CLEANUP)
698 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
699 txtid->addba_exchangeattempts = 0;
703 ath_tx_pause_tid(sc, txtid);
705 /* drop all software retried frames and mark this TID */
706 spin_lock_bh(&txq->axq_lock);
707 while (!list_empty(&txtid->buf_q)) {
708 bf = list_first_entry(&txtid->buf_q, struct ath_buf, list);
709 if (!bf_isretried(bf)) {
711 * NB: it's based on the assumption that
712 * software retried frame will always stay
713 * at the head of software queue.
717 list_move_tail(&bf->list, &bf_head);
718 ath_tx_update_baw(sc, txtid, bf->bf_seqno);
719 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
721 spin_unlock_bh(&txq->axq_lock);
723 if (txtid->baw_head != txtid->baw_tail) {
724 txtid->state |= AGGR_CLEANUP;
726 txtid->state &= ~AGGR_ADDBA_COMPLETE;
727 txtid->addba_exchangeattempts = 0;
728 ath_tx_flush_tid(sc, txtid);
734 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
736 struct ath_atx_tid *txtid;
739 an = (struct ath_node *)sta->drv_priv;
741 if (sc->sc_flags & SC_OP_TXAGGR) {
742 txtid = ATH_AN_2_TID(an, tid);
744 IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
745 txtid->state |= AGGR_ADDBA_COMPLETE;
746 txtid->state &= ~AGGR_ADDBA_PROGRESS;
747 ath_tx_resume_tid(sc, txtid);
751 bool ath_tx_aggr_check(struct ath_softc *sc, struct ath_node *an, u8 tidno)
753 struct ath_atx_tid *txtid;
755 if (!(sc->sc_flags & SC_OP_TXAGGR))
758 txtid = ATH_AN_2_TID(an, tidno);
760 if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
761 if (!(txtid->state & AGGR_ADDBA_PROGRESS) &&
762 (txtid->addba_exchangeattempts < ADDBA_EXCHANGE_ATTEMPTS)) {
763 txtid->addba_exchangeattempts++;
771 /********************/
772 /* Queue Management */
773 /********************/
775 static void ath_get_beaconconfig(struct ath_softc *sc, int if_id,
776 struct ath_beacon_config *conf)
778 struct ieee80211_hw *hw = sc->hw;
780 /* fill in beacon config data */
782 conf->beacon_interval = hw->conf.beacon_int;
783 conf->listen_interval = 100;
784 conf->dtim_count = 1;
785 conf->bmiss_timeout = ATH_DEFAULT_BMISS_LIMIT * conf->listen_interval;
788 static void ath_txq_drain_pending_buffers(struct ath_softc *sc,
791 struct ath_atx_ac *ac, *ac_tmp;
792 struct ath_atx_tid *tid, *tid_tmp;
794 list_for_each_entry_safe(ac, ac_tmp, &txq->axq_acq, list) {
797 list_for_each_entry_safe(tid, tid_tmp, &ac->tid_q, list) {
798 list_del(&tid->list);
800 ath_tid_drain(sc, txq, tid);
805 struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
807 struct ath_hw *ah = sc->sc_ah;
808 struct ath9k_tx_queue_info qi;
811 memset(&qi, 0, sizeof(qi));
812 qi.tqi_subtype = subtype;
813 qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
814 qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
815 qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
816 qi.tqi_physCompBuf = 0;
819 * Enable interrupts only for EOL and DESC conditions.
820 * We mark tx descriptors to receive a DESC interrupt
821 * when a tx queue gets deep; otherwise waiting for the
822 * EOL to reap descriptors. Note that this is done to
823 * reduce interrupt load and this only defers reaping
824 * descriptors, never transmitting frames. Aside from
825 * reducing interrupts this also permits more concurrency.
826 * The only potential downside is if the tx queue backs
827 * up in which case the top half of the kernel may backup
828 * due to a lack of tx descriptors.
830 * The UAPSD queue is an exception, since we take a desc-
831 * based intr on the EOSP frames.
833 if (qtype == ATH9K_TX_QUEUE_UAPSD)
834 qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
836 qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
837 TXQ_FLAG_TXDESCINT_ENABLE;
838 qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
841 * NB: don't print a message, this happens
842 * normally on parts with too few tx queues
846 if (qnum >= ARRAY_SIZE(sc->tx.txq)) {
847 DPRINTF(sc, ATH_DBG_FATAL,
848 "qnum %u out of range, max %u!\n",
849 qnum, (unsigned int)ARRAY_SIZE(sc->tx.txq));
850 ath9k_hw_releasetxqueue(ah, qnum);
853 if (!ATH_TXQ_SETUP(sc, qnum)) {
854 struct ath_txq *txq = &sc->tx.txq[qnum];
856 txq->axq_qnum = qnum;
857 txq->axq_link = NULL;
858 INIT_LIST_HEAD(&txq->axq_q);
859 INIT_LIST_HEAD(&txq->axq_acq);
860 spin_lock_init(&txq->axq_lock);
862 txq->axq_aggr_depth = 0;
863 txq->axq_totalqueued = 0;
864 txq->axq_linkbuf = NULL;
865 sc->tx.txqsetup |= 1<<qnum;
867 return &sc->tx.txq[qnum];
870 static int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype)
875 case ATH9K_TX_QUEUE_DATA:
876 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
877 DPRINTF(sc, ATH_DBG_FATAL,
878 "HAL AC %u out of range, max %zu!\n",
879 haltype, ARRAY_SIZE(sc->tx.hwq_map));
882 qnum = sc->tx.hwq_map[haltype];
884 case ATH9K_TX_QUEUE_BEACON:
885 qnum = sc->beacon.beaconq;
887 case ATH9K_TX_QUEUE_CAB:
888 qnum = sc->beacon.cabq->axq_qnum;
896 struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb)
898 struct ath_txq *txq = NULL;
901 qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc);
902 txq = &sc->tx.txq[qnum];
904 spin_lock_bh(&txq->axq_lock);
906 if (txq->axq_depth >= (ATH_TXBUF - 20)) {
907 DPRINTF(sc, ATH_DBG_FATAL,
908 "TX queue: %d is full, depth: %d\n",
909 qnum, txq->axq_depth);
910 ieee80211_stop_queue(sc->hw, skb_get_queue_mapping(skb));
912 spin_unlock_bh(&txq->axq_lock);
916 spin_unlock_bh(&txq->axq_lock);
921 int ath_txq_update(struct ath_softc *sc, int qnum,
922 struct ath9k_tx_queue_info *qinfo)
924 struct ath_hw *ah = sc->sc_ah;
926 struct ath9k_tx_queue_info qi;
928 if (qnum == sc->beacon.beaconq) {
930 * XXX: for beacon queue, we just save the parameter.
931 * It will be picked up by ath_beaconq_config when
934 sc->beacon.beacon_qi = *qinfo;
938 ASSERT(sc->tx.txq[qnum].axq_qnum == qnum);
940 ath9k_hw_get_txq_props(ah, qnum, &qi);
941 qi.tqi_aifs = qinfo->tqi_aifs;
942 qi.tqi_cwmin = qinfo->tqi_cwmin;
943 qi.tqi_cwmax = qinfo->tqi_cwmax;
944 qi.tqi_burstTime = qinfo->tqi_burstTime;
945 qi.tqi_readyTime = qinfo->tqi_readyTime;
947 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
948 DPRINTF(sc, ATH_DBG_FATAL,
949 "Unable to update hardware queue %u!\n", qnum);
952 ath9k_hw_resettxqueue(ah, qnum);
958 int ath_cabq_update(struct ath_softc *sc)
960 struct ath9k_tx_queue_info qi;
961 int qnum = sc->beacon.cabq->axq_qnum;
962 struct ath_beacon_config conf;
964 ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
966 * Ensure the readytime % is within the bounds.
968 if (sc->config.cabqReadytime < ATH9K_READY_TIME_LO_BOUND)
969 sc->config.cabqReadytime = ATH9K_READY_TIME_LO_BOUND;
970 else if (sc->config.cabqReadytime > ATH9K_READY_TIME_HI_BOUND)
971 sc->config.cabqReadytime = ATH9K_READY_TIME_HI_BOUND;
973 ath_get_beaconconfig(sc, ATH_IF_ID_ANY, &conf);
975 (conf.beacon_interval * sc->config.cabqReadytime) / 100;
976 ath_txq_update(sc, qnum, &qi);
982 * Drain a given TX queue (could be Beacon or Data)
984 * This assumes output has been stopped and
985 * we do not need to block ath_tx_tasklet.
987 void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq, bool retry_tx)
989 struct ath_buf *bf, *lastbf;
990 struct list_head bf_head;
992 INIT_LIST_HEAD(&bf_head);
995 spin_lock_bh(&txq->axq_lock);
997 if (list_empty(&txq->axq_q)) {
998 txq->axq_link = NULL;
999 txq->axq_linkbuf = NULL;
1000 spin_unlock_bh(&txq->axq_lock);
1004 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
1006 if (bf->bf_status & ATH_BUFSTATUS_STALE) {
1007 list_del(&bf->list);
1008 spin_unlock_bh(&txq->axq_lock);
1010 spin_lock_bh(&sc->tx.txbuflock);
1011 list_add_tail(&bf->list, &sc->tx.txbuf);
1012 spin_unlock_bh(&sc->tx.txbuflock);
1016 lastbf = bf->bf_lastbf;
1018 lastbf->bf_desc->ds_txstat.ts_flags =
1019 ATH9K_TX_SW_ABORTED;
1021 /* remove ath_buf's of the same mpdu from txq */
1022 list_cut_position(&bf_head, &txq->axq_q, &lastbf->list);
1025 spin_unlock_bh(&txq->axq_lock);
1028 ath_tx_complete_aggr(sc, txq, bf, &bf_head, 0);
1030 ath_tx_complete_buf(sc, bf, &bf_head, 0, 0);
1033 /* flush any pending frames if aggregation is enabled */
1034 if (sc->sc_flags & SC_OP_TXAGGR) {
1036 spin_lock_bh(&txq->axq_lock);
1037 ath_txq_drain_pending_buffers(sc, txq);
1038 spin_unlock_bh(&txq->axq_lock);
1043 void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1045 struct ath_hw *ah = sc->sc_ah;
1046 struct ath_txq *txq;
1049 if (sc->sc_flags & SC_OP_INVALID)
1052 /* Stop beacon queue */
1053 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
1055 /* Stop data queues */
1056 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1057 if (ATH_TXQ_SETUP(sc, i)) {
1058 txq = &sc->tx.txq[i];
1059 ath9k_hw_stoptxdma(ah, txq->axq_qnum);
1060 npend += ath9k_hw_numtxpending(ah, txq->axq_qnum);
1067 DPRINTF(sc, ATH_DBG_XMIT, "Unable to stop TxDMA. Reset HAL!\n");
1069 spin_lock_bh(&sc->sc_resetlock);
1070 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, true);
1072 DPRINTF(sc, ATH_DBG_FATAL,
1073 "Unable to reset hardware; reset status %u\n",
1075 spin_unlock_bh(&sc->sc_resetlock);
1078 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1079 if (ATH_TXQ_SETUP(sc, i))
1080 ath_draintxq(sc, &sc->tx.txq[i], retry_tx);
1084 void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1086 ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1087 sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1090 void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1092 struct ath_atx_ac *ac;
1093 struct ath_atx_tid *tid;
1095 if (list_empty(&txq->axq_acq))
1098 ac = list_first_entry(&txq->axq_acq, struct ath_atx_ac, list);
1099 list_del(&ac->list);
1103 if (list_empty(&ac->tid_q))
1106 tid = list_first_entry(&ac->tid_q, struct ath_atx_tid, list);
1107 list_del(&tid->list);
1113 if ((txq->axq_depth % 2) == 0)
1114 ath_tx_sched_aggr(sc, txq, tid);
1117 * add tid to round-robin queue if more frames
1118 * are pending for the tid
1120 if (!list_empty(&tid->buf_q))
1121 ath_tx_queue_tid(txq, tid);
1124 } while (!list_empty(&ac->tid_q));
1126 if (!list_empty(&ac->tid_q)) {
1129 list_add_tail(&ac->list, &txq->axq_acq);
1134 int ath_tx_setup(struct ath_softc *sc, int haltype)
1136 struct ath_txq *txq;
1138 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
1139 DPRINTF(sc, ATH_DBG_FATAL,
1140 "HAL AC %u out of range, max %zu!\n",
1141 haltype, ARRAY_SIZE(sc->tx.hwq_map));
1144 txq = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, haltype);
1146 sc->tx.hwq_map[haltype] = txq->axq_qnum;
1157 * Insert a chain of ath_buf (descriptors) on a txq and
1158 * assume the descriptors are already chained together by caller.
1160 static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1161 struct list_head *head)
1163 struct ath_hw *ah = sc->sc_ah;
1167 * Insert the frame on the outbound list and
1168 * pass it on to the hardware.
1171 if (list_empty(head))
1174 bf = list_first_entry(head, struct ath_buf, list);
1176 list_splice_tail_init(head, &txq->axq_q);
1178 txq->axq_totalqueued++;
1179 txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list);
1181 DPRINTF(sc, ATH_DBG_QUEUE,
1182 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
1184 if (txq->axq_link == NULL) {
1185 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1186 DPRINTF(sc, ATH_DBG_XMIT,
1187 "TXDP[%u] = %llx (%p)\n",
1188 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1190 *txq->axq_link = bf->bf_daddr;
1191 DPRINTF(sc, ATH_DBG_XMIT, "link[%u] (%p)=%llx (%p)\n",
1192 txq->axq_qnum, txq->axq_link,
1193 ito64(bf->bf_daddr), bf->bf_desc);
1195 txq->axq_link = &(bf->bf_lastbf->bf_desc->ds_link);
1196 ath9k_hw_txstart(ah, txq->axq_qnum);
1199 static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
1201 struct ath_buf *bf = NULL;
1203 spin_lock_bh(&sc->tx.txbuflock);
1205 if (unlikely(list_empty(&sc->tx.txbuf))) {
1206 spin_unlock_bh(&sc->tx.txbuflock);
1210 bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
1211 list_del(&bf->list);
1213 spin_unlock_bh(&sc->tx.txbuflock);
1218 static void ath_tx_send_ampdu(struct ath_softc *sc, struct ath_atx_tid *tid,
1219 struct list_head *bf_head,
1220 struct ath_tx_control *txctl)
1224 bf = list_first_entry(bf_head, struct ath_buf, list);
1225 bf->bf_state.bf_type |= BUF_AMPDU;
1228 * Do not queue to h/w when any of the following conditions is true:
1229 * - there are pending frames in software queue
1230 * - the TID is currently paused for ADDBA/BAR request
1231 * - seqno is not within block-ack window
1232 * - h/w queue depth exceeds low water mark
1234 if (!list_empty(&tid->buf_q) || tid->paused ||
1235 !BAW_WITHIN(tid->seq_start, tid->baw_size, bf->bf_seqno) ||
1236 txctl->txq->axq_depth >= ATH_AGGR_MIN_QDEPTH) {
1238 * Add this frame to software queue for scheduling later
1241 list_move_tail(&bf->list, &tid->buf_q);
1242 ath_tx_queue_tid(txctl->txq, tid);
1246 /* Add sub-frame to BAW */
1247 ath_tx_addto_baw(sc, tid, bf);
1249 /* Queue to h/w without aggregation */
1252 ath_buf_set_rate(sc, bf);
1253 ath_tx_txqaddbuf(sc, txctl->txq, bf_head);
1256 static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
1257 struct ath_atx_tid *tid,
1258 struct list_head *bf_head)
1262 bf = list_first_entry(bf_head, struct ath_buf, list);
1263 bf->bf_state.bf_type &= ~BUF_AMPDU;
1265 /* update starting sequence number for subsequent ADDBA request */
1266 INCR(tid->seq_start, IEEE80211_SEQ_MAX);
1270 ath_buf_set_rate(sc, bf);
1271 ath_tx_txqaddbuf(sc, txq, bf_head);
1274 static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1276 struct ieee80211_hdr *hdr;
1277 enum ath9k_pkt_type htype;
1280 hdr = (struct ieee80211_hdr *)skb->data;
1281 fc = hdr->frame_control;
1283 if (ieee80211_is_beacon(fc))
1284 htype = ATH9K_PKT_TYPE_BEACON;
1285 else if (ieee80211_is_probe_resp(fc))
1286 htype = ATH9K_PKT_TYPE_PROBE_RESP;
1287 else if (ieee80211_is_atim(fc))
1288 htype = ATH9K_PKT_TYPE_ATIM;
1289 else if (ieee80211_is_pspoll(fc))
1290 htype = ATH9K_PKT_TYPE_PSPOLL;
1292 htype = ATH9K_PKT_TYPE_NORMAL;
1297 static bool is_pae(struct sk_buff *skb)
1299 struct ieee80211_hdr *hdr;
1302 hdr = (struct ieee80211_hdr *)skb->data;
1303 fc = hdr->frame_control;
1305 if (ieee80211_is_data(fc)) {
1306 if (ieee80211_is_nullfunc(fc) ||
1307 /* Port Access Entity (IEEE 802.1X) */
1308 (skb->protocol == cpu_to_be16(ETH_P_PAE))) {
1316 static int get_hw_crypto_keytype(struct sk_buff *skb)
1318 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1320 if (tx_info->control.hw_key) {
1321 if (tx_info->control.hw_key->alg == ALG_WEP)
1322 return ATH9K_KEY_TYPE_WEP;
1323 else if (tx_info->control.hw_key->alg == ALG_TKIP)
1324 return ATH9K_KEY_TYPE_TKIP;
1325 else if (tx_info->control.hw_key->alg == ALG_CCMP)
1326 return ATH9K_KEY_TYPE_AES;
1329 return ATH9K_KEY_TYPE_CLEAR;
1332 static void assign_aggr_tid_seqno(struct sk_buff *skb,
1335 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1336 struct ieee80211_hdr *hdr;
1337 struct ath_node *an;
1338 struct ath_atx_tid *tid;
1342 if (!tx_info->control.sta)
1345 an = (struct ath_node *)tx_info->control.sta->drv_priv;
1346 hdr = (struct ieee80211_hdr *)skb->data;
1347 fc = hdr->frame_control;
1349 if (ieee80211_is_data_qos(fc)) {
1350 qc = ieee80211_get_qos_ctl(hdr);
1351 bf->bf_tidno = qc[0] & 0xf;
1355 * For HT capable stations, we save tidno for later use.
1356 * We also override seqno set by upper layer with the one
1357 * in tx aggregation state.
1359 * If fragmentation is on, the sequence number is
1360 * not overridden, since it has been
1361 * incremented by the fragmentation routine.
1363 * FIXME: check if the fragmentation threshold exceeds
1366 tid = ATH_AN_2_TID(an, bf->bf_tidno);
1367 hdr->seq_ctrl = cpu_to_le16(tid->seq_next <<
1368 IEEE80211_SEQ_SEQ_SHIFT);
1369 bf->bf_seqno = tid->seq_next;
1370 INCR(tid->seq_next, IEEE80211_SEQ_MAX);
1373 static int setup_tx_flags(struct ath_softc *sc, struct sk_buff *skb,
1374 struct ath_txq *txq)
1376 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1379 flags |= ATH9K_TXDESC_CLRDMASK; /* needed for crypto errors */
1380 flags |= ATH9K_TXDESC_INTREQ;
1382 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1383 flags |= ATH9K_TXDESC_NOACK;
1390 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1391 * width - 0 for 20 MHz, 1 for 40 MHz
1392 * half_gi - to use 4us v/s 3.6 us for symbol time
1394 static u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, struct ath_buf *bf,
1395 int width, int half_gi, bool shortPreamble)
1397 struct ath_rate_table *rate_table = sc->cur_rate_table;
1398 u32 nbits, nsymbits, duration, nsymbols;
1400 int streams, pktlen;
1402 pktlen = bf_isaggr(bf) ? bf->bf_al : bf->bf_frmlen;
1403 rc = rate_table->info[rix].ratecode;
1405 /* for legacy rates, use old function to compute packet duration */
1406 if (!IS_HT_RATE(rc))
1407 return ath9k_hw_computetxtime(sc->sc_ah, rate_table, pktlen,
1408 rix, shortPreamble);
1410 /* find number of symbols: PLCP + data */
1411 nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1412 nsymbits = bits_per_symbol[HT_RC_2_MCS(rc)][width];
1413 nsymbols = (nbits + nsymbits - 1) / nsymbits;
1416 duration = SYMBOL_TIME(nsymbols);
1418 duration = SYMBOL_TIME_HALFGI(nsymbols);
1420 /* addup duration for legacy/ht training and signal fields */
1421 streams = HT_RC_2_STREAMS(rc);
1422 duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1427 static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf)
1429 struct ath_rate_table *rt = sc->cur_rate_table;
1430 struct ath9k_11n_rate_series series[4];
1431 struct sk_buff *skb;
1432 struct ieee80211_tx_info *tx_info;
1433 struct ieee80211_tx_rate *rates;
1434 struct ieee80211_hdr *hdr;
1436 u8 rix = 0, ctsrate = 0;
1439 memset(series, 0, sizeof(struct ath9k_11n_rate_series) * 4);
1441 skb = (struct sk_buff *)bf->bf_mpdu;
1442 tx_info = IEEE80211_SKB_CB(skb);
1443 rates = tx_info->control.rates;
1444 hdr = (struct ieee80211_hdr *)skb->data;
1445 is_pspoll = ieee80211_is_pspoll(hdr->frame_control);
1448 * We check if Short Preamble is needed for the CTS rate by
1449 * checking the BSS's global flag.
1450 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
1452 if (sc->sc_flags & SC_OP_PREAMBLE_SHORT)
1453 ctsrate = rt->info[tx_info->control.rts_cts_rate_idx].ratecode |
1454 rt->info[tx_info->control.rts_cts_rate_idx].short_preamble;
1456 ctsrate = rt->info[tx_info->control.rts_cts_rate_idx].ratecode;
1459 * ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive.
1460 * Check the first rate in the series to decide whether RTS/CTS
1461 * or CTS-to-self has to be used.
1463 if (rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT)
1464 flags = ATH9K_TXDESC_CTSENA;
1465 else if (rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS)
1466 flags = ATH9K_TXDESC_RTSENA;
1468 /* FIXME: Handle aggregation protection */
1469 if (sc->config.ath_aggr_prot &&
1470 (!bf_isaggr(bf) || (bf_isaggr(bf) && bf->bf_al < 8192))) {
1471 flags = ATH9K_TXDESC_RTSENA;
1474 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1475 if (bf_isaggr(bf) && (bf->bf_al > sc->sc_ah->caps.rts_aggr_limit))
1476 flags &= ~(ATH9K_TXDESC_RTSENA);
1478 for (i = 0; i < 4; i++) {
1479 if (!rates[i].count || (rates[i].idx < 0))
1483 series[i].Tries = rates[i].count;
1484 series[i].ChSel = sc->tx_chainmask;
1486 if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1487 series[i].Rate = rt->info[rix].ratecode |
1488 rt->info[rix].short_preamble;
1490 series[i].Rate = rt->info[rix].ratecode;
1492 if (rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS)
1493 series[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1494 if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1495 series[i].RateFlags |= ATH9K_RATESERIES_2040;
1496 if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1497 series[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1499 series[i].PktDuration = ath_pkt_duration(sc, rix, bf,
1500 (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH) != 0,
1501 (rates[i].flags & IEEE80211_TX_RC_SHORT_GI),
1502 (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE));
1505 /* set dur_update_en for l-sig computation except for PS-Poll frames */
1506 ath9k_hw_set11n_ratescenario(sc->sc_ah, bf->bf_desc,
1507 bf->bf_lastbf->bf_desc,
1508 !is_pspoll, ctsrate,
1509 0, series, 4, flags);
1511 if (sc->config.ath_aggr_prot && flags)
1512 ath9k_hw_set11n_burstduration(sc->sc_ah, bf->bf_desc, 8192);
1515 static int ath_tx_setup_buffer(struct ath_softc *sc, struct ath_buf *bf,
1516 struct sk_buff *skb,
1517 struct ath_tx_control *txctl)
1519 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1520 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1521 struct ath_tx_info_priv *tx_info_priv;
1525 tx_info_priv = kzalloc(sizeof(*tx_info_priv), GFP_ATOMIC);
1526 if (unlikely(!tx_info_priv))
1528 tx_info->rate_driver_data[0] = tx_info_priv;
1529 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1530 fc = hdr->frame_control;
1532 ATH_TXBUF_RESET(bf);
1534 bf->bf_frmlen = skb->len + FCS_LEN - (hdrlen & 3);
1536 if ((conf_is_ht(&sc->hw->conf) && !is_pae(skb) &&
1537 (tx_info->flags & IEEE80211_TX_CTL_AMPDU)))
1538 bf->bf_state.bf_type |= BUF_HT;
1540 bf->bf_flags = setup_tx_flags(sc, skb, txctl->txq);
1542 bf->bf_keytype = get_hw_crypto_keytype(skb);
1543 if (bf->bf_keytype != ATH9K_KEY_TYPE_CLEAR) {
1544 bf->bf_frmlen += tx_info->control.hw_key->icv_len;
1545 bf->bf_keyix = tx_info->control.hw_key->hw_key_idx;
1547 bf->bf_keyix = ATH9K_TXKEYIX_INVALID;
1550 if (ieee80211_is_data_qos(fc) && (sc->sc_flags & SC_OP_TXAGGR))
1551 assign_aggr_tid_seqno(skb, bf);
1555 bf->bf_dmacontext = dma_map_single(sc->dev, skb->data,
1556 skb->len, DMA_TO_DEVICE);
1557 if (unlikely(dma_mapping_error(sc->dev, bf->bf_dmacontext))) {
1559 DPRINTF(sc, ATH_DBG_CONFIG,
1560 "dma_mapping_error() on TX\n");
1564 bf->bf_buf_addr = bf->bf_dmacontext;
1568 /* FIXME: tx power */
1569 static void ath_tx_start_dma(struct ath_softc *sc, struct ath_buf *bf,
1570 struct ath_tx_control *txctl)
1572 struct sk_buff *skb = (struct sk_buff *)bf->bf_mpdu;
1573 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1574 struct ath_node *an = NULL;
1575 struct list_head bf_head;
1576 struct ath_desc *ds;
1577 struct ath_atx_tid *tid;
1578 struct ath_hw *ah = sc->sc_ah;
1581 frm_type = get_hw_packet_type(skb);
1583 INIT_LIST_HEAD(&bf_head);
1584 list_add_tail(&bf->list, &bf_head);
1588 ds->ds_data = bf->bf_buf_addr;
1590 ath9k_hw_set11n_txdesc(ah, ds, bf->bf_frmlen, frm_type, MAX_RATE_POWER,
1591 bf->bf_keyix, bf->bf_keytype, bf->bf_flags);
1593 ath9k_hw_filltxdesc(ah, ds,
1594 skb->len, /* segment length */
1595 true, /* first segment */
1596 true, /* last segment */
1597 ds); /* first descriptor */
1599 spin_lock_bh(&txctl->txq->axq_lock);
1601 if (bf_isht(bf) && (sc->sc_flags & SC_OP_TXAGGR) &&
1602 tx_info->control.sta) {
1603 an = (struct ath_node *)tx_info->control.sta->drv_priv;
1604 tid = ATH_AN_2_TID(an, bf->bf_tidno);
1606 if (ath_aggr_query(sc, an, bf->bf_tidno)) {
1608 * Try aggregation if it's a unicast data frame
1609 * and the destination is HT capable.
1611 ath_tx_send_ampdu(sc, tid, &bf_head, txctl);
1614 * Send this frame as regular when ADDBA
1615 * exchange is neither complete nor pending.
1617 ath_tx_send_normal(sc, txctl->txq,
1624 ath_buf_set_rate(sc, bf);
1625 ath_tx_txqaddbuf(sc, txctl->txq, &bf_head);
1628 spin_unlock_bh(&txctl->txq->axq_lock);
1631 /* Upon failure caller should free skb */
1632 int ath_tx_start(struct ath_softc *sc, struct sk_buff *skb,
1633 struct ath_tx_control *txctl)
1638 bf = ath_tx_get_buffer(sc);
1640 DPRINTF(sc, ATH_DBG_XMIT, "TX buffers are full\n");
1644 r = ath_tx_setup_buffer(sc, bf, skb, txctl);
1646 struct ath_txq *txq = txctl->txq;
1648 DPRINTF(sc, ATH_DBG_FATAL, "TX mem alloc failure\n");
1650 /* upon ath_tx_processq() this TX queue will be resumed, we
1651 * guarantee this will happen by knowing beforehand that
1652 * we will at least have to run TX completionon one buffer
1654 spin_lock_bh(&txq->axq_lock);
1655 if (sc->tx.txq[txq->axq_qnum].axq_depth > 1) {
1656 ieee80211_stop_queue(sc->hw,
1657 skb_get_queue_mapping(skb));
1660 spin_unlock_bh(&txq->axq_lock);
1662 spin_lock_bh(&sc->tx.txbuflock);
1663 list_add_tail(&bf->list, &sc->tx.txbuf);
1664 spin_unlock_bh(&sc->tx.txbuflock);
1669 ath_tx_start_dma(sc, bf, txctl);
1674 void ath_tx_cabq(struct ath_softc *sc, struct sk_buff *skb)
1676 int hdrlen, padsize;
1677 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1678 struct ath_tx_control txctl;
1680 memset(&txctl, 0, sizeof(struct ath_tx_control));
1683 * As a temporary workaround, assign seq# here; this will likely need
1684 * to be cleaned up to work better with Beacon transmission and virtual
1687 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1688 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1689 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1690 sc->tx.seq_no += 0x10;
1691 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1692 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
1695 /* Add the padding after the header if this is not already done */
1696 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1698 padsize = hdrlen % 4;
1699 if (skb_headroom(skb) < padsize) {
1700 DPRINTF(sc, ATH_DBG_XMIT, "TX CABQ padding failed\n");
1701 dev_kfree_skb_any(skb);
1704 skb_push(skb, padsize);
1705 memmove(skb->data, skb->data + padsize, hdrlen);
1708 txctl.txq = sc->beacon.cabq;
1710 DPRINTF(sc, ATH_DBG_XMIT, "transmitting CABQ packet, skb: %p\n", skb);
1712 if (ath_tx_start(sc, skb, &txctl) != 0) {
1713 DPRINTF(sc, ATH_DBG_XMIT, "CABQ TX failed\n");
1719 dev_kfree_skb_any(skb);
1726 static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1727 struct ath_xmit_status *tx_status)
1729 struct ieee80211_hw *hw = sc->hw;
1730 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1731 struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info);
1732 int hdrlen, padsize;
1734 DPRINTF(sc, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
1736 if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK ||
1737 tx_info->flags & IEEE80211_TX_STAT_TX_FILTERED) {
1738 kfree(tx_info_priv);
1739 tx_info->rate_driver_data[0] = NULL;
1742 if (tx_status->flags & ATH_TX_BAR) {
1743 tx_info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1744 tx_status->flags &= ~ATH_TX_BAR;
1747 if (!(tx_status->flags & (ATH_TX_ERROR | ATH_TX_XRETRY))) {
1748 /* Frame was ACKed */
1749 tx_info->flags |= IEEE80211_TX_STAT_ACK;
1752 tx_info->status.rates[0].count = tx_status->retries + 1;
1754 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1755 padsize = hdrlen & 3;
1756 if (padsize && hdrlen >= 24) {
1758 * Remove MAC header padding before giving the frame back to
1761 memmove(skb->data + padsize, skb->data, hdrlen);
1762 skb_pull(skb, padsize);
1765 ieee80211_tx_status(hw, skb);
1768 static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
1769 struct list_head *bf_q,
1770 int txok, int sendbar)
1772 struct sk_buff *skb = bf->bf_mpdu;
1773 struct ath_xmit_status tx_status;
1774 unsigned long flags;
1777 * Set retry information.
1778 * NB: Don't use the information in the descriptor, because the frame
1779 * could be software retried.
1781 tx_status.retries = bf->bf_retries;
1782 tx_status.flags = 0;
1785 tx_status.flags = ATH_TX_BAR;
1788 tx_status.flags |= ATH_TX_ERROR;
1790 if (bf_isxretried(bf))
1791 tx_status.flags |= ATH_TX_XRETRY;
1794 dma_unmap_single(sc->dev, bf->bf_dmacontext, skb->len, DMA_TO_DEVICE);
1795 ath_tx_complete(sc, skb, &tx_status);
1798 * Return the list of ath_buf of this mpdu to free queue
1800 spin_lock_irqsave(&sc->tx.txbuflock, flags);
1801 list_splice_tail_init(bf_q, &sc->tx.txbuf);
1802 spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
1805 static int ath_tx_num_badfrms(struct ath_softc *sc, struct ath_buf *bf,
1808 struct ath_buf *bf_last = bf->bf_lastbf;
1809 struct ath_desc *ds = bf_last->bf_desc;
1811 u32 ba[WME_BA_BMP_SIZE >> 5];
1816 if (ds->ds_txstat.ts_flags == ATH9K_TX_SW_ABORTED)
1819 isaggr = bf_isaggr(bf);
1821 seq_st = ATH_DS_BA_SEQ(ds);
1822 memcpy(ba, ATH_DS_BA_BITMAP(ds), WME_BA_BMP_SIZE >> 3);
1826 ba_index = ATH_BA_INDEX(seq_st, bf->bf_seqno);
1827 if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
1836 static void ath_tx_rc_status(struct ath_buf *bf, struct ath_desc *ds, int nbad)
1838 struct sk_buff *skb = (struct sk_buff *)bf->bf_mpdu;
1839 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
1840 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1841 struct ath_tx_info_priv *tx_info_priv = ATH_TX_INFO_PRIV(tx_info);
1843 tx_info_priv->update_rc = false;
1844 if (ds->ds_txstat.ts_status & ATH9K_TXERR_FILT)
1845 tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1847 if ((ds->ds_txstat.ts_status & ATH9K_TXERR_FILT) == 0 &&
1848 (bf->bf_flags & ATH9K_TXDESC_NOACK) == 0) {
1849 if (ieee80211_is_data(hdr->frame_control)) {
1850 memcpy(&tx_info_priv->tx, &ds->ds_txstat,
1851 sizeof(tx_info_priv->tx));
1852 tx_info_priv->n_frames = bf->bf_nframes;
1853 tx_info_priv->n_bad_frames = nbad;
1854 tx_info_priv->update_rc = true;
1859 static void ath_wake_mac80211_queue(struct ath_softc *sc, struct ath_txq *txq)
1863 spin_lock_bh(&txq->axq_lock);
1865 sc->tx.txq[txq->axq_qnum].axq_depth <= (ATH_TXBUF - 20)) {
1866 qnum = ath_get_mac80211_qnum(txq->axq_qnum, sc);
1868 ieee80211_wake_queue(sc->hw, qnum);
1872 spin_unlock_bh(&txq->axq_lock);
1875 static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
1877 struct ath_hw *ah = sc->sc_ah;
1878 struct ath_buf *bf, *lastbf, *bf_held = NULL;
1879 struct list_head bf_head;
1880 struct ath_desc *ds;
1884 DPRINTF(sc, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
1885 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
1889 spin_lock_bh(&txq->axq_lock);
1890 if (list_empty(&txq->axq_q)) {
1891 txq->axq_link = NULL;
1892 txq->axq_linkbuf = NULL;
1893 spin_unlock_bh(&txq->axq_lock);
1896 bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
1899 * There is a race condition that a BH gets scheduled
1900 * after sw writes TxE and before hw re-load the last
1901 * descriptor to get the newly chained one.
1902 * Software must keep the last DONE descriptor as a
1903 * holding descriptor - software does so by marking
1904 * it with the STALE flag.
1907 if (bf->bf_status & ATH_BUFSTATUS_STALE) {
1909 if (list_is_last(&bf_held->list, &txq->axq_q)) {
1910 txq->axq_link = NULL;
1911 txq->axq_linkbuf = NULL;
1912 spin_unlock_bh(&txq->axq_lock);
1915 * The holding descriptor is the last
1916 * descriptor in queue. It's safe to remove
1917 * the last holding descriptor in BH context.
1919 spin_lock_bh(&sc->tx.txbuflock);
1920 list_move_tail(&bf_held->list, &sc->tx.txbuf);
1921 spin_unlock_bh(&sc->tx.txbuflock);
1925 bf = list_entry(bf_held->list.next,
1926 struct ath_buf, list);
1930 lastbf = bf->bf_lastbf;
1931 ds = lastbf->bf_desc;
1933 status = ath9k_hw_txprocdesc(ah, ds);
1934 if (status == -EINPROGRESS) {
1935 spin_unlock_bh(&txq->axq_lock);
1938 if (bf->bf_desc == txq->axq_lastdsWithCTS)
1939 txq->axq_lastdsWithCTS = NULL;
1940 if (ds == txq->axq_gatingds)
1941 txq->axq_gatingds = NULL;
1944 * Remove ath_buf's of the same transmit unit from txq,
1945 * however leave the last descriptor back as the holding
1946 * descriptor for hw.
1948 lastbf->bf_status |= ATH_BUFSTATUS_STALE;
1949 INIT_LIST_HEAD(&bf_head);
1950 if (!list_is_singular(&lastbf->list))
1951 list_cut_position(&bf_head,
1952 &txq->axq_q, lastbf->list.prev);
1956 txq->axq_aggr_depth--;
1958 txok = (ds->ds_txstat.ts_status == 0);
1959 spin_unlock_bh(&txq->axq_lock);
1962 spin_lock_bh(&sc->tx.txbuflock);
1963 list_move_tail(&bf_held->list, &sc->tx.txbuf);
1964 spin_unlock_bh(&sc->tx.txbuflock);
1967 if (!bf_isampdu(bf)) {
1969 * This frame is sent out as a single frame.
1970 * Use hardware retry status for this frame.
1972 bf->bf_retries = ds->ds_txstat.ts_longretry;
1973 if (ds->ds_txstat.ts_status & ATH9K_TXERR_XRETRY)
1974 bf->bf_state.bf_type |= BUF_XRETRY;
1977 nbad = ath_tx_num_badfrms(sc, bf, txok);
1980 ath_tx_rc_status(bf, ds, nbad);
1983 ath_tx_complete_aggr(sc, txq, bf, &bf_head, txok);
1985 ath_tx_complete_buf(sc, bf, &bf_head, txok, 0);
1987 ath_wake_mac80211_queue(sc, txq);
1989 spin_lock_bh(&txq->axq_lock);
1990 if (sc->sc_flags & SC_OP_TXAGGR)
1991 ath_txq_schedule(sc, txq);
1992 spin_unlock_bh(&txq->axq_lock);
1997 void ath_tx_tasklet(struct ath_softc *sc)
2000 u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1);
2002 ath9k_hw_gettxintrtxqs(sc->sc_ah, &qcumask);
2004 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2005 if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2006 ath_tx_processq(sc, &sc->tx.txq[i]);
2014 int ath_tx_init(struct ath_softc *sc, int nbufs)
2019 spin_lock_init(&sc->tx.txbuflock);
2021 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2024 DPRINTF(sc, ATH_DBG_FATAL,
2025 "Failed to allocate tx descriptors: %d\n",
2030 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2031 "beacon", ATH_BCBUF, 1);
2033 DPRINTF(sc, ATH_DBG_FATAL,
2034 "Failed to allocate beacon descriptors: %d\n",
2047 int ath_tx_cleanup(struct ath_softc *sc)
2049 if (sc->beacon.bdma.dd_desc_len != 0)
2050 ath_descdma_cleanup(sc, &sc->beacon.bdma, &sc->beacon.bbuf);
2052 if (sc->tx.txdma.dd_desc_len != 0)
2053 ath_descdma_cleanup(sc, &sc->tx.txdma, &sc->tx.txbuf);
2058 void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2060 struct ath_atx_tid *tid;
2061 struct ath_atx_ac *ac;
2064 for (tidno = 0, tid = &an->tid[tidno];
2065 tidno < WME_NUM_TID;
2069 tid->seq_start = tid->seq_next = 0;
2070 tid->baw_size = WME_MAX_BA;
2071 tid->baw_head = tid->baw_tail = 0;
2073 tid->paused = false;
2074 tid->state &= ~AGGR_CLEANUP;
2075 INIT_LIST_HEAD(&tid->buf_q);
2076 acno = TID_TO_WME_AC(tidno);
2077 tid->ac = &an->ac[acno];
2078 tid->state &= ~AGGR_ADDBA_COMPLETE;
2079 tid->state &= ~AGGR_ADDBA_PROGRESS;
2080 tid->addba_exchangeattempts = 0;
2083 for (acno = 0, ac = &an->ac[acno];
2084 acno < WME_NUM_AC; acno++, ac++) {
2086 INIT_LIST_HEAD(&ac->tid_q);
2090 ac->qnum = ath_tx_get_qnum(sc,
2091 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
2094 ac->qnum = ath_tx_get_qnum(sc,
2095 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BK);
2098 ac->qnum = ath_tx_get_qnum(sc,
2099 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VI);
2102 ac->qnum = ath_tx_get_qnum(sc,
2103 ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_VO);
2109 void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2112 struct ath_atx_ac *ac, *ac_tmp;
2113 struct ath_atx_tid *tid, *tid_tmp;
2114 struct ath_txq *txq;
2116 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2117 if (ATH_TXQ_SETUP(sc, i)) {
2118 txq = &sc->tx.txq[i];
2120 spin_lock(&txq->axq_lock);
2122 list_for_each_entry_safe(ac,
2123 ac_tmp, &txq->axq_acq, list) {
2124 tid = list_first_entry(&ac->tid_q,
2125 struct ath_atx_tid, list);
2126 if (tid && tid->an != an)
2128 list_del(&ac->list);
2131 list_for_each_entry_safe(tid,
2132 tid_tmp, &ac->tid_q, list) {
2133 list_del(&tid->list);
2135 ath_tid_drain(sc, txq, tid);
2136 tid->state &= ~AGGR_ADDBA_COMPLETE;
2137 tid->addba_exchangeattempts = 0;
2138 tid->state &= ~AGGR_CLEANUP;
2142 spin_unlock(&txq->axq_lock);