SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/ath9k/main.c

   1 /*
   2  * Copyright (c) 2008 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/nl80211.h>
  18 #include "core.h"
  19 #include "reg.h"
  20
  21 #define ATH_PCI_VERSION "0.1"
  22
  23 static char *dev_info = "ath9k";
  24
  25 MODULE_AUTHOR("Atheros Communications");
  26 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  27 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  28 MODULE_LICENSE("Dual BSD/GPL");
  29
  30 static struct pci_device_id ath_pci_id_table[] __devinitdata = {
  31         { PCI_VDEVICE(ATHEROS, 0x0023) }, /* PCI   */
  32         { PCI_VDEVICE(ATHEROS, 0x0024) }, /* PCI-E */
  33         { PCI_VDEVICE(ATHEROS, 0x0027) }, /* PCI   */
  34         { PCI_VDEVICE(ATHEROS, 0x0029) }, /* PCI   */
  35         { PCI_VDEVICE(ATHEROS, 0x002A) }, /* PCI-E */
  36         { 0 }
  37 };
  38
  39 static void ath_detach(struct ath_softc *sc);
  40
  41 /* return bus cachesize in 4B word units */
  42
  43 static void bus_read_cachesize(struct ath_softc *sc, int *csz)
  44 {
  45         u8 u8tmp;
  46
  47         pci_read_config_byte(sc->pdev, PCI_CACHE_LINE_SIZE, (u8 *)&u8tmp);
  48         *csz = (int)u8tmp;
  49
  50         /*
  51          * This check was put in to avoid "unplesant" consequences if
  52          * the bootrom has not fully initialized all PCI devices.
  53          * Sometimes the cache line size register is not set
  54          */
  55
  56         if (*csz == 0)
  57                 *csz = DEFAULT_CACHELINE >> 2;   /* Use the default size */
  58 }
  59
  60 static void ath_setcurmode(struct ath_softc *sc, enum wireless_mode mode)
  61 {
  62         sc->sc_curmode = mode;
  63         /*
  64          * All protection frames are transmited at 2Mb/s for
  65          * 11g, otherwise at 1Mb/s.
  66          * XXX select protection rate index from rate table.
  67          */
  68         sc->sc_protrix = (mode == ATH9K_MODE_11G ? 1 : 0);
  69 }
  70
  71 static enum wireless_mode ath_chan2mode(struct ath9k_channel *chan)
  72 {
  73         if (chan->chanmode == CHANNEL_A)
  74                 return ATH9K_MODE_11A;
  75         else if (chan->chanmode == CHANNEL_G)
  76                 return ATH9K_MODE_11G;
  77         else if (chan->chanmode == CHANNEL_B)
  78                 return ATH9K_MODE_11B;
  79         else if (chan->chanmode == CHANNEL_A_HT20)
  80                 return ATH9K_MODE_11NA_HT20;
  81         else if (chan->chanmode == CHANNEL_G_HT20)
  82                 return ATH9K_MODE_11NG_HT20;
  83         else if (chan->chanmode == CHANNEL_A_HT40PLUS)
  84                 return ATH9K_MODE_11NA_HT40PLUS;
  85         else if (chan->chanmode == CHANNEL_A_HT40MINUS)
  86                 return ATH9K_MODE_11NA_HT40MINUS;
  87         else if (chan->chanmode == CHANNEL_G_HT40PLUS)
  88                 return ATH9K_MODE_11NG_HT40PLUS;
  89         else if (chan->chanmode == CHANNEL_G_HT40MINUS)
  90                 return ATH9K_MODE_11NG_HT40MINUS;
  91
  92         WARN_ON(1); /* should not get here */
  93
  94         return ATH9K_MODE_11B;
  95 }
  96
  97 static void ath_update_txpow(struct ath_softc *sc)
  98 {
  99         struct ath_hal *ah = sc->sc_ah;
 100         u32 txpow;
 101
 102         if (sc->sc_curtxpow != sc->sc_config.txpowlimit) {
 103                 ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit);
 104                 /* read back in case value is clamped */
 105                 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
 106                 sc->sc_curtxpow = txpow;
 107         }
 108 }
 109
 110 static u8 parse_mpdudensity(u8 mpdudensity)
 111 {
 112         /*
 113          * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
 114          *   0 for no restriction
 115          *   1 for 1/4 us
 116          *   2 for 1/2 us
 117          *   3 for 1 us
 118          *   4 for 2 us
 119          *   5 for 4 us
 120          *   6 for 8 us
 121          *   7 for 16 us
 122          */
 123         switch (mpdudensity) {
 124         case 0:
 125                 return 0;
 126         case 1:
 127         case 2:
 128         case 3:
 129                 /* Our lower layer calculations limit our precision to
 130                    1 microsecond */
 131                 return 1;
 132         case 4:
 133                 return 2;
 134         case 5:
 135                 return 4;
 136         case 6:
 137                 return 8;
 138         case 7:
 139                 return 16;
 140         default:
 141                 return 0;
 142         }
 143 }
 144
 145 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
 146 {
 147         struct ath_rate_table *rate_table = NULL;
 148         struct ieee80211_supported_band *sband;
 149         struct ieee80211_rate *rate;
 150         int i, maxrates;
 151
 152         switch (band) {
 153         case IEEE80211_BAND_2GHZ:
 154                 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
 155                 break;
 156         case IEEE80211_BAND_5GHZ:
 157                 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
 158                 break;
 159         default:
 160                 break;
 161         }
 162
 163         if (rate_table == NULL)
 164                 return;
 165
 166         sband = &sc->sbands[band];
 167         rate = sc->rates[band];
 168
 169         if (rate_table->rate_cnt > ATH_RATE_MAX)
 170                 maxrates = ATH_RATE_MAX;
 171         else
 172                 maxrates = rate_table->rate_cnt;
 173
 174         for (i = 0; i < maxrates; i++) {
 175                 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
 176                 rate[i].hw_value = rate_table->info[i].ratecode;
 177                 sband->n_bitrates++;
 178                 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Rate: %2dMbps, ratecode: %2d\n",
 179                         __func__, rate[i].bitrate / 10, rate[i].hw_value);
 180         }
 181 }
 182
 183 static int ath_setup_channels(struct ath_softc *sc)
 184 {
 185         struct ath_hal *ah = sc->sc_ah;
 186         int nchan, i, a = 0, b = 0;
 187         u8 regclassids[ATH_REGCLASSIDS_MAX];
 188         u32 nregclass = 0;
 189         struct ieee80211_supported_band *band_2ghz;
 190         struct ieee80211_supported_band *band_5ghz;
 191         struct ieee80211_channel *chan_2ghz;
 192         struct ieee80211_channel *chan_5ghz;
 193         struct ath9k_channel *c;
 194
 195         /* Fill in ah->ah_channels */
 196         if (!ath9k_regd_init_channels(ah, ATH_CHAN_MAX, (u32 *)&nchan,
 197                                       regclassids, ATH_REGCLASSIDS_MAX,
 198                                       &nregclass, CTRY_DEFAULT, false, 1)) {
 199                 u32 rd = ah->ah_currentRD;
 200                 DPRINTF(sc, ATH_DBG_FATAL,
 201                         "%s: unable to collect channel list; "
 202                         "regdomain likely %u country code %u\n",
 203                         __func__, rd, CTRY_DEFAULT);
 204                 return -EINVAL;
 205         }
 206
 207         band_2ghz = &sc->sbands[IEEE80211_BAND_2GHZ];
 208         band_5ghz = &sc->sbands[IEEE80211_BAND_5GHZ];
 209         chan_2ghz = sc->channels[IEEE80211_BAND_2GHZ];
 210         chan_5ghz = sc->channels[IEEE80211_BAND_5GHZ];
 211
 212         for (i = 0; i < nchan; i++) {
 213                 c = &ah->ah_channels[i];
 214                 if (IS_CHAN_2GHZ(c)) {
 215                         chan_2ghz[a].band = IEEE80211_BAND_2GHZ;
 216                         chan_2ghz[a].center_freq = c->channel;
 217                         chan_2ghz[a].max_power = c->maxTxPower;
 218
 219                         if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
 220                                 chan_2ghz[a].flags |= IEEE80211_CHAN_NO_IBSS;
 221                         if (c->channelFlags & CHANNEL_PASSIVE)
 222                                 chan_2ghz[a].flags |= IEEE80211_CHAN_PASSIVE_SCAN;
 223
 224                         band_2ghz->n_channels = ++a;
 225
 226                         DPRINTF(sc, ATH_DBG_CONFIG, "%s: 2MHz channel: %d, "
 227                                 "channelFlags: 0x%x\n",
 228                                 __func__, c->channel, c->channelFlags);
 229                 } else if (IS_CHAN_5GHZ(c)) {
 230                         chan_5ghz[b].band = IEEE80211_BAND_5GHZ;
 231                         chan_5ghz[b].center_freq = c->channel;
 232                         chan_5ghz[b].max_power = c->maxTxPower;
 233
 234                         if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
 235                                 chan_5ghz[b].flags |= IEEE80211_CHAN_NO_IBSS;
 236                         if (c->channelFlags & CHANNEL_PASSIVE)
 237                                 chan_5ghz[b].flags |= IEEE80211_CHAN_PASSIVE_SCAN;
 238
 239                         band_5ghz->n_channels = ++b;
 240
 241                         DPRINTF(sc, ATH_DBG_CONFIG, "%s: 5MHz channel: %d, "
 242                                 "channelFlags: 0x%x\n",
 243                                 __func__, c->channel, c->channelFlags);
 244                 }
 245         }
 246
 247         return 0;
 248 }
 249
 250 /*
 251  * Set/change channels.  If the channel is really being changed, it's done
 252  * by reseting the chip.  To accomplish this we must first cleanup any pending
 253  * DMA, then restart stuff.
 254 */
 255 static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
 256 {
 257         struct ath_hal *ah = sc->sc_ah;
 258         bool fastcc = true, stopped;
 259
 260         if (sc->sc_flags & SC_OP_INVALID)
 261                 return -EIO;
 262
 263         DPRINTF(sc, ATH_DBG_CONFIG,
 264                 "%s: %u (%u MHz) -> %u (%u MHz), cflags:%x\n",
 265                 __func__,
 266                 ath9k_hw_mhz2ieee(ah, sc->sc_ah->ah_curchan->channel,
 267                                   sc->sc_ah->ah_curchan->channelFlags),
 268                 sc->sc_ah->ah_curchan->channel,
 269                 ath9k_hw_mhz2ieee(ah, hchan->channel, hchan->channelFlags),
 270                 hchan->channel, hchan->channelFlags);
 271
 272         if (hchan->channel != sc->sc_ah->ah_curchan->channel ||
 273             hchan->channelFlags != sc->sc_ah->ah_curchan->channelFlags ||
 274             (sc->sc_flags & SC_OP_CHAINMASK_UPDATE) ||
 275             (sc->sc_flags & SC_OP_FULL_RESET)) {
 276                 int status;
 277                 /*
 278                  * This is only performed if the channel settings have
 279                  * actually changed.
 280                  *
 281                  * To switch channels clear any pending DMA operations;
 282                  * wait long enough for the RX fifo to drain, reset the
 283                  * hardware at the new frequency, and then re-enable
 284                  * the relevant bits of the h/w.
 285                  */
 286                 ath9k_hw_set_interrupts(ah, 0); /* disable interrupts */
 287                 ath_draintxq(sc, false);        /* clear pending tx frames */
 288                 stopped = ath_stoprecv(sc);     /* turn off frame recv */
 289
 290                 /* XXX: do not flush receive queue here. We don't want
 291                  * to flush data frames already in queue because of
 292                  * changing channel. */
 293
 294                 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
 295                         fastcc = false;
 296
 297                 spin_lock_bh(&sc->sc_resetlock);
 298                 if (!ath9k_hw_reset(ah, hchan, sc->sc_ht_info.tx_chan_width,
 299                                     sc->sc_tx_chainmask, sc->sc_rx_chainmask,
 300                                     sc->sc_ht_extprotspacing, fastcc, &status)) {
 301                         DPRINTF(sc, ATH_DBG_FATAL,
 302                                 "%s: unable to reset channel %u (%uMhz) "
 303                                 "flags 0x%x hal status %u\n", __func__,
 304                                 ath9k_hw_mhz2ieee(ah, hchan->channel,
 305                                                   hchan->channelFlags),
 306                                 hchan->channel, hchan->channelFlags, status);
 307                         spin_unlock_bh(&sc->sc_resetlock);
 308                         return -EIO;
 309                 }
 310                 spin_unlock_bh(&sc->sc_resetlock);
 311
 312                 sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
 313                 sc->sc_flags &= ~SC_OP_FULL_RESET;
 314
 315                 if (ath_startrecv(sc) != 0) {
 316                         DPRINTF(sc, ATH_DBG_FATAL,
 317                                 "%s: unable to restart recv logic\n", __func__);
 318                         return -EIO;
 319                 }
 320
 321                 ath_setcurmode(sc, ath_chan2mode(hchan));
 322                 ath_update_txpow(sc);
 323                 ath9k_hw_set_interrupts(ah, sc->sc_imask);
 324         }
 325         return 0;
 326 }
 327
 328 /*
 329  *  This routine performs the periodic noise floor calibration function
 330  *  that is used to adjust and optimize the chip performance.  This
 331  *  takes environmental changes (location, temperature) into account.
 332  *  When the task is complete, it reschedules itself depending on the
 333  *  appropriate interval that was calculated.
 334  */
 335 static void ath_ani_calibrate(unsigned long data)
 336 {
 337         struct ath_softc *sc;
 338         struct ath_hal *ah;
 339         bool longcal = false;
 340         bool shortcal = false;
 341         bool aniflag = false;
 342         unsigned int timestamp = jiffies_to_msecs(jiffies);
 343         u32 cal_interval;
 344
 345         sc = (struct ath_softc *)data;
 346         ah = sc->sc_ah;
 347
 348         /*
 349         * don't calibrate when we're scanning.
 350         * we are most likely not on our home channel.
 351         */
 352         if (sc->rx_filter & FIF_BCN_PRBRESP_PROMISC)
 353                 return;
 354
 355         /* Long calibration runs independently of short calibration. */
 356         if ((timestamp - sc->sc_ani.sc_longcal_timer) >= ATH_LONG_CALINTERVAL) {
 357                 longcal = true;
 358                 DPRINTF(sc, ATH_DBG_ANI, "%s: longcal @%lu\n",
 359                         __func__, jiffies);
 360                 sc->sc_ani.sc_longcal_timer = timestamp;
 361         }
 362
 363         /* Short calibration applies only while sc_caldone is false */
 364         if (!sc->sc_ani.sc_caldone) {
 365                 if ((timestamp - sc->sc_ani.sc_shortcal_timer) >=
 366                     ATH_SHORT_CALINTERVAL) {
 367                         shortcal = true;
 368                         DPRINTF(sc, ATH_DBG_ANI, "%s: shortcal @%lu\n",
 369                                __func__, jiffies);
 370                         sc->sc_ani.sc_shortcal_timer = timestamp;
 371                         sc->sc_ani.sc_resetcal_timer = timestamp;
 372                 }
 373         } else {
 374                 if ((timestamp - sc->sc_ani.sc_resetcal_timer) >=
 375                     ATH_RESTART_CALINTERVAL) {
 376                         ath9k_hw_reset_calvalid(ah, ah->ah_curchan,
 377                                                 &sc->sc_ani.sc_caldone);
 378                         if (sc->sc_ani.sc_caldone)
 379                                 sc->sc_ani.sc_resetcal_timer = timestamp;
 380                 }
 381         }
 382
 383         /* Verify whether we must check ANI */
 384         if ((timestamp - sc->sc_ani.sc_checkani_timer) >=
 385            ATH_ANI_POLLINTERVAL) {
 386                 aniflag = true;
 387                 sc->sc_ani.sc_checkani_timer = timestamp;
 388         }
 389
 390         /* Skip all processing if there's nothing to do. */
 391         if (longcal || shortcal || aniflag) {
 392                 /* Call ANI routine if necessary */
 393                 if (aniflag)
 394                         ath9k_hw_ani_monitor(ah, &sc->sc_halstats,
 395                                              ah->ah_curchan);
 396
 397                 /* Perform calibration if necessary */
 398                 if (longcal || shortcal) {
 399                         bool iscaldone = false;
 400
 401                         if (ath9k_hw_calibrate(ah, ah->ah_curchan,
 402                                                sc->sc_rx_chainmask, longcal,
 403                                                &iscaldone)) {
 404                                 if (longcal)
 405                                         sc->sc_ani.sc_noise_floor =
 406                                                 ath9k_hw_getchan_noise(ah,
 407                                                                ah->ah_curchan);
 408
 409                                 DPRINTF(sc, ATH_DBG_ANI,
 410                                         "%s: calibrate chan %u/%x nf: %d\n",
 411                                          __func__,
 412                                         ah->ah_curchan->channel,
 413                                         ah->ah_curchan->channelFlags,
 414                                         sc->sc_ani.sc_noise_floor);
 415                         } else {
 416                                 DPRINTF(sc, ATH_DBG_ANY,
 417                                         "%s: calibrate chan %u/%x failed\n",
 418                                          __func__,
 419                                         ah->ah_curchan->channel,
 420                                         ah->ah_curchan->channelFlags);
 421                         }
 422                         sc->sc_ani.sc_caldone = iscaldone;
 423                 }
 424         }
 425
 426         /*
 427         * Set timer interval based on previous results.
 428         * The interval must be the shortest necessary to satisfy ANI,
 429         * short calibration and long calibration.
 430         */
 431
 432         cal_interval = ATH_ANI_POLLINTERVAL;
 433         if (!sc->sc_ani.sc_caldone)
 434                 cal_interval = min(cal_interval, (u32)ATH_SHORT_CALINTERVAL);
 435
 436         mod_timer(&sc->sc_ani.timer, jiffies + msecs_to_jiffies(cal_interval));
 437 }
 438
 439 /*
 440  * Update tx/rx chainmask. For legacy association,
 441  * hard code chainmask to 1x1, for 11n association, use
 442  * the chainmask configuration.
 443  */
 444 static void ath_update_chainmask(struct ath_softc *sc, int is_ht)
 445 {
 446         sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
 447         if (is_ht) {
 448                 sc->sc_tx_chainmask = sc->sc_ah->ah_caps.tx_chainmask;
 449                 sc->sc_rx_chainmask = sc->sc_ah->ah_caps.rx_chainmask;
 450         } else {
 451                 sc->sc_tx_chainmask = 1;
 452                 sc->sc_rx_chainmask = 1;
 453         }
 454
 455         DPRINTF(sc, ATH_DBG_CONFIG, "%s: tx chmask: %d, rx chmask: %d\n",
 456                 __func__, sc->sc_tx_chainmask, sc->sc_rx_chainmask);
 457 }
 458
 459 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
 460 {
 461         struct ath_node *an;
 462
 463         an = (struct ath_node *)sta->drv_priv;
 464
 465         if (sc->sc_flags & SC_OP_TXAGGR)
 466                 ath_tx_node_init(sc, an);
 467
 468         an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
 469                              sta->ht_cap.ampdu_factor);
 470         an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
 471 }
 472
 473 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
 474 {
 475         struct ath_node *an = (struct ath_node *)sta->drv_priv;
 476
 477         if (sc->sc_flags & SC_OP_TXAGGR)
 478                 ath_tx_node_cleanup(sc, an);
 479 }
 480
 481 static void ath9k_tasklet(unsigned long data)
 482 {
 483         struct ath_softc *sc = (struct ath_softc *)data;
 484         u32 status = sc->sc_intrstatus;
 485
 486         if (status & ATH9K_INT_FATAL) {
 487                 /* need a chip reset */
 488                 ath_reset(sc, false);
 489                 return;
 490         } else {
 491
 492                 if (status &
 493                     (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
 494                         spin_lock_bh(&sc->sc_rxflushlock);
 495                         ath_rx_tasklet(sc, 0);
 496                         spin_unlock_bh(&sc->sc_rxflushlock);
 497                 }
 498                 /* XXX: optimize this */
 499                 if (status & ATH9K_INT_TX)
 500                         ath_tx_tasklet(sc);
 501         }
 502
 503         /* re-enable hardware interrupt */
 504         ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
 505 }
 506
 507 static irqreturn_t ath_isr(int irq, void *dev)
 508 {
 509         struct ath_softc *sc = dev;
 510         struct ath_hal *ah = sc->sc_ah;
 511         enum ath9k_int status;
 512         bool sched = false;
 513
 514         do {
 515                 if (sc->sc_flags & SC_OP_INVALID) {
 516                         /*
 517                          * The hardware is not ready/present, don't
 518                          * touch anything. Note this can happen early
 519                          * on if the IRQ is shared.
 520                          */
 521                         return IRQ_NONE;
 522                 }
 523                 if (!ath9k_hw_intrpend(ah)) {   /* shared irq, not for us */
 524                         return IRQ_NONE;
 525                 }
 526
 527                 /*
 528                  * Figure out the reason(s) for the interrupt.  Note
 529                  * that the hal returns a pseudo-ISR that may include
 530                  * bits we haven't explicitly enabled so we mask the
 531                  * value to insure we only process bits we requested.
 532                  */
 533                 ath9k_hw_getisr(ah, &status);   /* NB: clears ISR too */
 534
 535                 status &= sc->sc_imask; /* discard unasked-for bits */
 536
 537                 /*
 538                  * If there are no status bits set, then this interrupt was not
 539                  * for me (should have been caught above).
 540                  */
 541                 if (!status)
 542                         return IRQ_NONE;
 543
 544                 sc->sc_intrstatus = status;
 545
 546                 if (status & ATH9K_INT_FATAL) {
 547                         /* need a chip reset */
 548                         sched = true;
 549                 } else if (status & ATH9K_INT_RXORN) {
 550                         /* need a chip reset */
 551                         sched = true;
 552                 } else {
 553                         if (status & ATH9K_INT_SWBA) {
 554                                 /* schedule a tasklet for beacon handling */
 555                                 tasklet_schedule(&sc->bcon_tasklet);
 556                         }
 557                         if (status & ATH9K_INT_RXEOL) {
 558                                 /*
 559                                  * NB: the hardware should re-read the link when
 560                                  *     RXE bit is written, but it doesn't work
 561                                  *     at least on older hardware revs.
 562                                  */
 563                                 sched = true;
 564                         }
 565
 566                         if (status & ATH9K_INT_TXURN)
 567                                 /* bump tx trigger level */
 568                                 ath9k_hw_updatetxtriglevel(ah, true);
 569                         /* XXX: optimize this */
 570                         if (status & ATH9K_INT_RX)
 571                                 sched = true;
 572                         if (status & ATH9K_INT_TX)
 573                                 sched = true;
 574                         if (status & ATH9K_INT_BMISS)
 575                                 sched = true;
 576                         /* carrier sense timeout */
 577                         if (status & ATH9K_INT_CST)
 578                                 sched = true;
 579                         if (status & ATH9K_INT_MIB) {
 580                                 /*
 581                                  * Disable interrupts until we service the MIB
 582                                  * interrupt; otherwise it will continue to
 583                                  * fire.
 584                                  */
 585                                 ath9k_hw_set_interrupts(ah, 0);
 586                                 /*
 587                                  * Let the hal handle the event. We assume
 588                                  * it will clear whatever condition caused
 589                                  * the interrupt.
 590                                  */
 591                                 ath9k_hw_procmibevent(ah, &sc->sc_halstats);
 592                                 ath9k_hw_set_interrupts(ah, sc->sc_imask);
 593                         }
 594                         if (status & ATH9K_INT_TIM_TIMER) {
 595                                 if (!(ah->ah_caps.hw_caps &
 596                                       ATH9K_HW_CAP_AUTOSLEEP)) {
 597                                         /* Clear RxAbort bit so that we can
 598                                          * receive frames */
 599                                         ath9k_hw_setrxabort(ah, 0);
 600                                         sched = true;
 601                                 }
 602                         }
 603                 }
 604         } while (0);
 605
 606         if (sched) {
 607                 /* turn off every interrupt except SWBA */
 608                 ath9k_hw_set_interrupts(ah, (sc->sc_imask & ATH9K_INT_SWBA));
 609                 tasklet_schedule(&sc->intr_tq);
 610         }
 611
 612         return IRQ_HANDLED;
 613 }
 614
 615 static int ath_get_channel(struct ath_softc *sc,
 616                            struct ieee80211_channel *chan)
 617 {
 618         int i;
 619
 620         for (i = 0; i < sc->sc_ah->ah_nchan; i++) {
 621                 if (sc->sc_ah->ah_channels[i].channel == chan->center_freq)
 622                         return i;
 623         }
 624
 625         return -1;
 626 }
 627
 628 static u32 ath_get_extchanmode(struct ath_softc *sc,
 629                                      struct ieee80211_channel *chan)
 630 {
 631         u32 chanmode = 0;
 632         u8 ext_chan_offset = sc->sc_ht_info.ext_chan_offset;
 633         enum ath9k_ht_macmode tx_chan_width = sc->sc_ht_info.tx_chan_width;
 634
 635         switch (chan->band) {
 636         case IEEE80211_BAND_2GHZ:
 637                 if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_NONE) &&
 638                     (tx_chan_width == ATH9K_HT_MACMODE_20))
 639                         chanmode = CHANNEL_G_HT20;
 640                 if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE) &&
 641                     (tx_chan_width == ATH9K_HT_MACMODE_2040))
 642                         chanmode = CHANNEL_G_HT40PLUS;
 643                 if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW) &&
 644                     (tx_chan_width == ATH9K_HT_MACMODE_2040))
 645                         chanmode = CHANNEL_G_HT40MINUS;
 646                 break;
 647         case IEEE80211_BAND_5GHZ:
 648                 if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_NONE) &&
 649                     (tx_chan_width == ATH9K_HT_MACMODE_20))
 650                         chanmode = CHANNEL_A_HT20;
 651                 if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_ABOVE) &&
 652                     (tx_chan_width == ATH9K_HT_MACMODE_2040))
 653                         chanmode = CHANNEL_A_HT40PLUS;
 654                 if ((ext_chan_offset == IEEE80211_HT_PARAM_CHA_SEC_BELOW) &&
 655                     (tx_chan_width == ATH9K_HT_MACMODE_2040))
 656                         chanmode = CHANNEL_A_HT40MINUS;
 657                 break;
 658         default:
 659                 break;
 660         }
 661
 662         return chanmode;
 663 }
 664
 665 static void ath_key_reset(struct ath_softc *sc, u16 keyix, int freeslot)
 666 {
 667         ath9k_hw_keyreset(sc->sc_ah, keyix);
 668         if (freeslot)
 669                 clear_bit(keyix, sc->sc_keymap);
 670 }
 671
 672 static int ath_keyset(struct ath_softc *sc, u16 keyix,
 673                struct ath9k_keyval *hk, const u8 mac[ETH_ALEN])
 674 {
 675         bool status;
 676
 677         status = ath9k_hw_set_keycache_entry(sc->sc_ah,
 678                 keyix, hk, mac, false);
 679
 680         return status != false;
 681 }
 682
 683 static int ath_setkey_tkip(struct ath_softc *sc,
 684                            struct ieee80211_key_conf *key,
 685                            struct ath9k_keyval *hk,
 686                            const u8 *addr)
 687 {
 688         u8 *key_rxmic = NULL;
 689         u8 *key_txmic = NULL;
 690
 691         key_txmic = key->key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
 692         key_rxmic = key->key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
 693
 694         if (addr == NULL) {
 695                 /* Group key installation */
 696                 memcpy(hk->kv_mic,  key_rxmic, sizeof(hk->kv_mic));
 697                 return ath_keyset(sc, key->keyidx, hk, addr);
 698         }
 699         if (!sc->sc_splitmic) {
 700                 /*
 701                  * data key goes at first index,
 702                  * the hal handles the MIC keys at index+64.
 703                  */
 704                 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 705                 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
 706                 return ath_keyset(sc, key->keyidx, hk, addr);
 707         }
 708         /*
 709          * TX key goes at first index, RX key at +32.
 710          * The hal handles the MIC keys at index+64.
 711          */
 712         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
 713         if (!ath_keyset(sc, key->keyidx, hk, NULL)) {
 714                 /* Txmic entry failed. No need to proceed further */
 715                 DPRINTF(sc, ATH_DBG_KEYCACHE,
 716                         "%s Setting TX MIC Key Failed\n", __func__);
 717                 return 0;
 718         }
 719
 720         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 721         /* XXX delete tx key on failure? */
 722         return ath_keyset(sc, key->keyidx+32, hk, addr);
 723 }
 724
 725 static int ath_key_config(struct ath_softc *sc,
 726                           const u8 *addr,
 727                           struct ieee80211_key_conf *key)
 728 {
 729         struct ieee80211_vif *vif;
 730         struct ath9k_keyval hk;
 731         const u8 *mac = NULL;
 732         int ret = 0;
 733         enum nl80211_iftype opmode;
 734
 735         memset(&hk, 0, sizeof(hk));
 736
 737         switch (key->alg) {
 738         case ALG_WEP:
 739                 hk.kv_type = ATH9K_CIPHER_WEP;
 740                 break;
 741         case ALG_TKIP:
 742                 hk.kv_type = ATH9K_CIPHER_TKIP;
 743                 break;
 744         case ALG_CCMP:
 745                 hk.kv_type = ATH9K_CIPHER_AES_CCM;
 746                 break;
 747         default:
 748                 return -EINVAL;
 749         }
 750
 751         hk.kv_len  = key->keylen;
 752         memcpy(hk.kv_val, key->key, key->keylen);
 753
 754         if (!sc->sc_vaps[0])
 755                 return -EIO;
 756
 757         vif = sc->sc_vaps[0];
 758         opmode = vif->type;
 759
 760         /*
 761          *  Strategy:
 762          *   For _M_STA mc tx, we will not setup a key at all since we never
 763          *   tx mc.
 764          *   _M_STA mc rx, we will use the keyID.
 765          *   for _M_IBSS mc tx, we will use the keyID, and no macaddr.
 766          *   for _M_IBSS mc rx, we will alloc a slot and plumb the mac of the
 767          *   peer node. BUT we will plumb a cleartext key so that we can do
 768          *   perSta default key table lookup in software.
 769          */
 770         if (is_broadcast_ether_addr(addr)) {
 771                 switch (opmode) {
 772                 case NL80211_IFTYPE_STATION:
 773                         /* default key:  could be group WPA key
 774                          * or could be static WEP key */
 775                         mac = NULL;
 776                         break;
 777                 case NL80211_IFTYPE_ADHOC:
 778                         break;
 779                 case NL80211_IFTYPE_AP:
 780                         break;
 781                 default:
 782                         ASSERT(0);
 783                         break;
 784                 }
 785         } else {
 786                 mac = addr;
 787         }
 788
 789         if (key->alg == ALG_TKIP)
 790                 ret = ath_setkey_tkip(sc, key, &hk, mac);
 791         else
 792                 ret = ath_keyset(sc, key->keyidx, &hk, mac);
 793
 794         if (!ret)
 795                 return -EIO;
 796
 797         return 0;
 798 }
 799
 800 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
 801 {
 802         int freeslot;
 803
 804         freeslot = (key->keyidx >= 4) ? 1 : 0;
 805         ath_key_reset(sc, key->keyidx, freeslot);
 806 }
 807
 808 static void setup_ht_cap(struct ieee80211_sta_ht_cap *ht_info)
 809 {
 810 #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3       /* 2 ^ 16 */
 811 #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6          /* 8 usec */
 812
 813         ht_info->ht_supported = true;
 814         ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
 815                        IEEE80211_HT_CAP_SM_PS |
 816                        IEEE80211_HT_CAP_SGI_40 |
 817                        IEEE80211_HT_CAP_DSSSCCK40;
 818
 819         ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
 820         ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
 821         /* set up supported mcs set */
 822         memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
 823         ht_info->mcs.rx_mask[0] = 0xff;
 824         ht_info->mcs.rx_mask[1] = 0xff;
 825         ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
 826 }
 827
 828 static void ath9k_ht_conf(struct ath_softc *sc,
 829                           struct ieee80211_bss_conf *bss_conf)
 830 {
 831         struct ath_ht_info *ht_info = &sc->sc_ht_info;
 832
 833         if (sc->hw->conf.ht.enabled) {
 834                 ht_info->ext_chan_offset = bss_conf->ht.secondary_channel_offset;
 835
 836                 if (bss_conf->ht.width_40_ok)
 837                         ht_info->tx_chan_width = ATH9K_HT_MACMODE_2040;
 838                 else
 839                         ht_info->tx_chan_width = ATH9K_HT_MACMODE_20;
 840
 841                 ath9k_hw_set11nmac2040(sc->sc_ah, ht_info->tx_chan_width);
 842         }
 843 }
 844
 845 static void ath9k_bss_assoc_info(struct ath_softc *sc,
 846                                  struct ieee80211_vif *vif,
 847                                  struct ieee80211_bss_conf *bss_conf)
 848 {
 849         struct ieee80211_hw *hw = sc->hw;
 850         struct ieee80211_channel *curchan = hw->conf.channel;
 851         struct ath_vap *avp = (void *)vif->drv_priv;
 852         int pos;
 853
 854         if (bss_conf->assoc) {
 855                 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Bss Info ASSOC %d\n",
 856                         __func__,
 857                         bss_conf->aid);
 858
 859                 /* New association, store aid */
 860                 if (avp->av_opmode == ATH9K_M_STA) {
 861                         sc->sc_curaid = bss_conf->aid;
 862                         ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
 863                                                sc->sc_curaid);
 864                 }
 865
 866                 /* Configure the beacon */
 867                 ath_beacon_config(sc, 0);
 868                 sc->sc_flags |= SC_OP_BEACONS;
 869
 870                 /* Reset rssi stats */
 871                 sc->sc_halstats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
 872                 sc->sc_halstats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
 873                 sc->sc_halstats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
 874                 sc->sc_halstats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
 875
 876                 /* Update chainmask */
 877                 ath_update_chainmask(sc, hw->conf.ht.enabled);
 878
 879                 DPRINTF(sc, ATH_DBG_CONFIG,
 880                         "%s: bssid %pM aid 0x%x\n",
 881                         __func__,
 882                         sc->sc_curbssid, sc->sc_curaid);
 883
 884                 DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set channel: %d MHz\n",
 885                         __func__,
 886                         curchan->center_freq);
 887
 888                 pos = ath_get_channel(sc, curchan);
 889                 if (pos == -1) {
 890                         DPRINTF(sc, ATH_DBG_FATAL,
 891                                 "%s: Invalid channel\n", __func__);
 892                         return;
 893                 }
 894
 895                 if (hw->conf.ht.enabled)
 896                         sc->sc_ah->ah_channels[pos].chanmode =
 897                                 ath_get_extchanmode(sc, curchan);
 898                 else
 899                         sc->sc_ah->ah_channels[pos].chanmode =
 900                                 (curchan->band == IEEE80211_BAND_2GHZ) ?
 901                                 CHANNEL_G : CHANNEL_A;
 902
 903                 /* set h/w channel */
 904                 if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0)
 905                         DPRINTF(sc, ATH_DBG_FATAL,
 906                                 "%s: Unable to set channel\n",
 907                                 __func__);
 908                 /* Start ANI */
 909                 mod_timer(&sc->sc_ani.timer,
 910                         jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
 911
 912         } else {
 913                 DPRINTF(sc, ATH_DBG_CONFIG,
 914                 "%s: Bss Info DISSOC\n", __func__);
 915                 sc->sc_curaid = 0;
 916         }
 917 }
 918
 919 /********************************/
 920 /*       LED functions          */
 921 /********************************/
 922
 923 static void ath_led_brightness(struct led_classdev *led_cdev,
 924                                enum led_brightness brightness)
 925 {
 926         struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
 927         struct ath_softc *sc = led->sc;
 928
 929         switch (brightness) {
 930         case LED_OFF:
 931                 if (led->led_type == ATH_LED_ASSOC ||
 932                     led->led_type == ATH_LED_RADIO)
 933                         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
 934                 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
 935                                 (led->led_type == ATH_LED_RADIO) ? 1 :
 936                                 !!(sc->sc_flags & SC_OP_LED_ASSOCIATED));
 937                 break;
 938         case LED_FULL:
 939                 if (led->led_type == ATH_LED_ASSOC)
 940                         sc->sc_flags |= SC_OP_LED_ASSOCIATED;
 941                 ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
 942                 break;
 943         default:
 944                 break;
 945         }
 946 }
 947
 948 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
 949                             char *trigger)
 950 {
 951         int ret;
 952
 953         led->sc = sc;
 954         led->led_cdev.name = led->name;
 955         led->led_cdev.default_trigger = trigger;
 956         led->led_cdev.brightness_set = ath_led_brightness;
 957
 958         ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
 959         if (ret)
 960                 DPRINTF(sc, ATH_DBG_FATAL,
 961                         "Failed to register led:%s", led->name);
 962         else
 963                 led->registered = 1;
 964         return ret;
 965 }
 966
 967 static void ath_unregister_led(struct ath_led *led)
 968 {
 969         if (led->registered) {
 970                 led_classdev_unregister(&led->led_cdev);
 971                 led->registered = 0;
 972         }
 973 }
 974
 975 static void ath_deinit_leds(struct ath_softc *sc)
 976 {
 977         ath_unregister_led(&sc->assoc_led);
 978         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
 979         ath_unregister_led(&sc->tx_led);
 980         ath_unregister_led(&sc->rx_led);
 981         ath_unregister_led(&sc->radio_led);
 982         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
 983 }
 984
 985 static void ath_init_leds(struct ath_softc *sc)
 986 {
 987         char *trigger;
 988         int ret;
 989
 990         /* Configure gpio 1 for output */
 991         ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
 992                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
 993         /* LED off, active low */
 994         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
 995
 996         trigger = ieee80211_get_radio_led_name(sc->hw);
 997         snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
 998                 "ath9k-%s:radio", wiphy_name(sc->hw->wiphy));
 999         ret = ath_register_led(sc, &sc->radio_led, trigger);
1000         sc->radio_led.led_type = ATH_LED_RADIO;
1001         if (ret)
1002                 goto fail;
1003
1004         trigger = ieee80211_get_assoc_led_name(sc->hw);
1005         snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1006                 "ath9k-%s:assoc", wiphy_name(sc->hw->wiphy));
1007         ret = ath_register_led(sc, &sc->assoc_led, trigger);
1008         sc->assoc_led.led_type = ATH_LED_ASSOC;
1009         if (ret)
1010                 goto fail;
1011
1012         trigger = ieee80211_get_tx_led_name(sc->hw);
1013         snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1014                 "ath9k-%s:tx", wiphy_name(sc->hw->wiphy));
1015         ret = ath_register_led(sc, &sc->tx_led, trigger);
1016         sc->tx_led.led_type = ATH_LED_TX;
1017         if (ret)
1018                 goto fail;
1019
1020         trigger = ieee80211_get_rx_led_name(sc->hw);
1021         snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1022                 "ath9k-%s:rx", wiphy_name(sc->hw->wiphy));
1023         ret = ath_register_led(sc, &sc->rx_led, trigger);
1024         sc->rx_led.led_type = ATH_LED_RX;
1025         if (ret)
1026                 goto fail;
1027
1028         return;
1029
1030 fail:
1031         ath_deinit_leds(sc);
1032 }
1033
1034 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1035
1036 /*******************/
1037 /*      Rfkill     */
1038 /*******************/
1039
1040 static void ath_radio_enable(struct ath_softc *sc)
1041 {
1042         struct ath_hal *ah = sc->sc_ah;
1043         int status;
1044
1045         spin_lock_bh(&sc->sc_resetlock);
1046         if (!ath9k_hw_reset(ah, ah->ah_curchan,
1047                             sc->sc_ht_info.tx_chan_width,
1048                             sc->sc_tx_chainmask,
1049                             sc->sc_rx_chainmask,
1050                             sc->sc_ht_extprotspacing,
1051                             false, &status)) {
1052                 DPRINTF(sc, ATH_DBG_FATAL,
1053                         "%s: unable to reset channel %u (%uMhz) "
1054                         "flags 0x%x hal status %u\n", __func__,
1055                         ath9k_hw_mhz2ieee(ah,
1056                                           ah->ah_curchan->channel,
1057                                           ah->ah_curchan->channelFlags),
1058                         ah->ah_curchan->channel,
1059                         ah->ah_curchan->channelFlags, status);
1060         }
1061         spin_unlock_bh(&sc->sc_resetlock);
1062
1063         ath_update_txpow(sc);
1064         if (ath_startrecv(sc) != 0) {
1065                 DPRINTF(sc, ATH_DBG_FATAL,
1066                         "%s: unable to restart recv logic\n", __func__);
1067                 return;
1068         }
1069
1070         if (sc->sc_flags & SC_OP_BEACONS)
1071                 ath_beacon_config(sc, ATH_IF_ID_ANY);   /* restart beacons */
1072
1073         /* Re-Enable  interrupts */
1074         ath9k_hw_set_interrupts(ah, sc->sc_imask);
1075
1076         /* Enable LED */
1077         ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1078                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1079         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1080
1081         ieee80211_wake_queues(sc->hw);
1082 }
1083
1084 static void ath_radio_disable(struct ath_softc *sc)
1085 {
1086         struct ath_hal *ah = sc->sc_ah;
1087         int status;
1088
1089
1090         ieee80211_stop_queues(sc->hw);
1091
1092         /* Disable LED */
1093         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1094         ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1095
1096         /* Disable interrupts */
1097         ath9k_hw_set_interrupts(ah, 0);
1098
1099         ath_draintxq(sc, false);        /* clear pending tx frames */
1100         ath_stoprecv(sc);               /* turn off frame recv */
1101         ath_flushrecv(sc);              /* flush recv queue */
1102
1103         spin_lock_bh(&sc->sc_resetlock);
1104         if (!ath9k_hw_reset(ah, ah->ah_curchan,
1105                             sc->sc_ht_info.tx_chan_width,
1106                             sc->sc_tx_chainmask,
1107                             sc->sc_rx_chainmask,
1108                             sc->sc_ht_extprotspacing,
1109                             false, &status)) {
1110                 DPRINTF(sc, ATH_DBG_FATAL,
1111                         "%s: unable to reset channel %u (%uMhz) "
1112                         "flags 0x%x hal status %u\n", __func__,
1113                         ath9k_hw_mhz2ieee(ah,
1114                                 ah->ah_curchan->channel,
1115                                 ah->ah_curchan->channelFlags),
1116                         ah->ah_curchan->channel,
1117                         ah->ah_curchan->channelFlags, status);
1118         }
1119         spin_unlock_bh(&sc->sc_resetlock);
1120
1121         ath9k_hw_phy_disable(ah);
1122         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1123 }
1124
1125 static bool ath_is_rfkill_set(struct ath_softc *sc)
1126 {
1127         struct ath_hal *ah = sc->sc_ah;
1128
1129         return ath9k_hw_gpio_get(ah, ah->ah_rfkill_gpio) ==
1130                                   ah->ah_rfkill_polarity;
1131 }
1132
1133 /* h/w rfkill poll function */
1134 static void ath_rfkill_poll(struct work_struct *work)
1135 {
1136         struct ath_softc *sc = container_of(work, struct ath_softc,
1137                                             rf_kill.rfkill_poll.work);
1138         bool radio_on;
1139
1140         if (sc->sc_flags & SC_OP_INVALID)
1141                 return;
1142
1143         radio_on = !ath_is_rfkill_set(sc);
1144
1145         /*
1146          * enable/disable radio only when there is a
1147          * state change in RF switch
1148          */
1149         if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1150                 enum rfkill_state state;
1151
1152                 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1153                         state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1154                                 : RFKILL_STATE_HARD_BLOCKED;
1155                 } else if (radio_on) {
1156                         ath_radio_enable(sc);
1157                         state = RFKILL_STATE_UNBLOCKED;
1158                 } else {
1159                         ath_radio_disable(sc);
1160                         state = RFKILL_STATE_HARD_BLOCKED;
1161                 }
1162
1163                 if (state == RFKILL_STATE_HARD_BLOCKED)
1164                         sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1165                 else
1166                         sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1167
1168                 rfkill_force_state(sc->rf_kill.rfkill, state);
1169         }
1170
1171         queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1172                            msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1173 }
1174
1175 /* s/w rfkill handler */
1176 static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1177 {
1178         struct ath_softc *sc = data;
1179
1180         switch (state) {
1181         case RFKILL_STATE_SOFT_BLOCKED:
1182                 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1183                     SC_OP_RFKILL_SW_BLOCKED)))
1184                         ath_radio_disable(sc);
1185                 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1186                 return 0;
1187         case RFKILL_STATE_UNBLOCKED:
1188                 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1189                         sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1190                         if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1191                                 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
1192                                         "radio as it is disabled by h/w \n");
1193                                 return -EPERM;
1194                         }
1195                         ath_radio_enable(sc);
1196                 }
1197                 return 0;
1198         default:
1199                 return -EINVAL;
1200         }
1201 }
1202
1203 /* Init s/w rfkill */
1204 static int ath_init_sw_rfkill(struct ath_softc *sc)
1205 {
1206         sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1207                                              RFKILL_TYPE_WLAN);
1208         if (!sc->rf_kill.rfkill) {
1209                 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1210                 return -ENOMEM;
1211         }
1212
1213         snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1214                 "ath9k-%s:rfkill", wiphy_name(sc->hw->wiphy));
1215         sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1216         sc->rf_kill.rfkill->data = sc;
1217         sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1218         sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1219         sc->rf_kill.rfkill->user_claim_unsupported = 1;
1220
1221         return 0;
1222 }
1223
1224 /* Deinitialize rfkill */
1225 static void ath_deinit_rfkill(struct ath_softc *sc)
1226 {
1227         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1228                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1229
1230         if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1231                 rfkill_unregister(sc->rf_kill.rfkill);
1232                 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1233                 sc->rf_kill.rfkill = NULL;
1234         }
1235 }
1236
1237 static int ath_start_rfkill_poll(struct ath_softc *sc)
1238 {
1239         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1240                 queue_delayed_work(sc->hw->workqueue,
1241                                    &sc->rf_kill.rfkill_poll, 0);
1242
1243         if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1244                 if (rfkill_register(sc->rf_kill.rfkill)) {
1245                         DPRINTF(sc, ATH_DBG_FATAL,
1246                                 "Unable to register rfkill\n");
1247                         rfkill_free(sc->rf_kill.rfkill);
1248
1249                         /* Deinitialize the device */
1250                         ath_detach(sc);
1251                         if (sc->pdev->irq)
1252                                 free_irq(sc->pdev->irq, sc);
1253                         pci_iounmap(sc->pdev, sc->mem);
1254                         pci_release_region(sc->pdev, 0);
1255                         pci_disable_device(sc->pdev);
1256                         ieee80211_free_hw(sc->hw);
1257                         return -EIO;
1258                 } else {
1259                         sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1260                 }
1261         }
1262
1263         return 0;
1264 }
1265 #endif /* CONFIG_RFKILL */
1266
1267 static void ath_detach(struct ath_softc *sc)
1268 {
1269         struct ieee80211_hw *hw = sc->hw;
1270         int i = 0;
1271
1272         DPRINTF(sc, ATH_DBG_CONFIG, "%s: Detach ATH hw\n", __func__);
1273
1274 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1275         ath_deinit_rfkill(sc);
1276 #endif
1277         ath_deinit_leds(sc);
1278
1279         ieee80211_unregister_hw(hw);
1280
1281         ath_rate_control_unregister();
1282
1283         ath_rx_cleanup(sc);
1284         ath_tx_cleanup(sc);
1285
1286         tasklet_kill(&sc->intr_tq);
1287         tasklet_kill(&sc->bcon_tasklet);
1288
1289         if (!(sc->sc_flags & SC_OP_INVALID))
1290                 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1291
1292         /* cleanup tx queues */
1293         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1294                 if (ATH_TXQ_SETUP(sc, i))
1295                         ath_tx_cleanupq(sc, &sc->sc_txq[i]);
1296
1297         ath9k_hw_detach(sc->sc_ah);
1298 }
1299
1300 static int ath_init(u16 devid, struct ath_softc *sc)
1301 {
1302         struct ath_hal *ah = NULL;
1303         int status;
1304         int error = 0, i;
1305         int csz = 0;
1306
1307         /* XXX: hardware will not be ready until ath_open() being called */
1308         sc->sc_flags |= SC_OP_INVALID;
1309         sc->sc_debug = DBG_DEFAULT;
1310
1311         spin_lock_init(&sc->sc_resetlock);
1312         tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1313         tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
1314                      (unsigned long)sc);
1315
1316         /*
1317          * Cache line size is used to size and align various
1318          * structures used to communicate with the hardware.
1319          */
1320         bus_read_cachesize(sc, &csz);
1321         /* XXX assert csz is non-zero */
1322         sc->sc_cachelsz = csz << 2;     /* convert to bytes */
1323
1324         ah = ath9k_hw_attach(devid, sc, sc->mem, &status);
1325         if (ah == NULL) {
1326                 DPRINTF(sc, ATH_DBG_FATAL,
1327                         "%s: unable to attach hardware; HAL status %u\n",
1328                         __func__, status);
1329                 error = -ENXIO;
1330                 goto bad;
1331         }
1332         sc->sc_ah = ah;
1333
1334         /* Get the hardware key cache size. */
1335         sc->sc_keymax = ah->ah_caps.keycache_size;
1336         if (sc->sc_keymax > ATH_KEYMAX) {
1337                 DPRINTF(sc, ATH_DBG_KEYCACHE,
1338                         "%s: Warning, using only %u entries in %u key cache\n",
1339                         __func__, ATH_KEYMAX, sc->sc_keymax);
1340                 sc->sc_keymax = ATH_KEYMAX;
1341         }
1342
1343         /*
1344          * Reset the key cache since some parts do not
1345          * reset the contents on initial power up.
1346          */
1347         for (i = 0; i < sc->sc_keymax; i++)
1348                 ath9k_hw_keyreset(ah, (u16) i);
1349         /*
1350          * Mark key cache slots associated with global keys
1351          * as in use.  If we knew TKIP was not to be used we
1352          * could leave the +32, +64, and +32+64 slots free.
1353          * XXX only for splitmic.
1354          */
1355         for (i = 0; i < IEEE80211_WEP_NKID; i++) {
1356                 set_bit(i, sc->sc_keymap);
1357                 set_bit(i + 32, sc->sc_keymap);
1358                 set_bit(i + 64, sc->sc_keymap);
1359                 set_bit(i + 32 + 64, sc->sc_keymap);
1360         }
1361
1362         /* Collect the channel list using the default country code */
1363
1364         error = ath_setup_channels(sc);
1365         if (error)
1366                 goto bad;
1367
1368         /* default to MONITOR mode */
1369         sc->sc_ah->ah_opmode = ATH9K_M_MONITOR;
1370
1371         /* Setup rate tables */
1372
1373         ath_rate_attach(sc);
1374         ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1375         ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1376
1377         /*
1378          * Allocate hardware transmit queues: one queue for
1379          * beacon frames and one data queue for each QoS
1380          * priority.  Note that the hal handles reseting
1381          * these queues at the needed time.
1382          */
1383         sc->sc_bhalq = ath_beaconq_setup(ah);
1384         if (sc->sc_bhalq == -1) {
1385                 DPRINTF(sc, ATH_DBG_FATAL,
1386                         "%s: unable to setup a beacon xmit queue\n", __func__);
1387                 error = -EIO;
1388                 goto bad2;
1389         }
1390         sc->sc_cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1391         if (sc->sc_cabq == NULL) {
1392                 DPRINTF(sc, ATH_DBG_FATAL,
1393                         "%s: unable to setup CAB xmit queue\n", __func__);
1394                 error = -EIO;
1395                 goto bad2;
1396         }
1397
1398         sc->sc_config.cabqReadytime = ATH_CABQ_READY_TIME;
1399         ath_cabq_update(sc);
1400
1401         for (i = 0; i < ARRAY_SIZE(sc->sc_haltype2q); i++)
1402                 sc->sc_haltype2q[i] = -1;
1403
1404         /* Setup data queues */
1405         /* NB: ensure BK queue is the lowest priority h/w queue */
1406         if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1407                 DPRINTF(sc, ATH_DBG_FATAL,
1408                         "%s: unable to setup xmit queue for BK traffic\n",
1409                         __func__);
1410                 error = -EIO;
1411                 goto bad2;
1412         }
1413
1414         if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1415                 DPRINTF(sc, ATH_DBG_FATAL,
1416                         "%s: unable to setup xmit queue for BE traffic\n",
1417                         __func__);
1418                 error = -EIO;
1419                 goto bad2;
1420         }
1421         if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1422                 DPRINTF(sc, ATH_DBG_FATAL,
1423                         "%s: unable to setup xmit queue for VI traffic\n",
1424                         __func__);
1425                 error = -EIO;
1426                 goto bad2;
1427         }
1428         if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1429                 DPRINTF(sc, ATH_DBG_FATAL,
1430                         "%s: unable to setup xmit queue for VO traffic\n",
1431                         __func__);
1432                 error = -EIO;
1433                 goto bad2;
1434         }
1435
1436         /* Initializes the noise floor to a reasonable default value.
1437          * Later on this will be updated during ANI processing. */
1438
1439         sc->sc_ani.sc_noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1440         setup_timer(&sc->sc_ani.timer, ath_ani_calibrate, (unsigned long)sc);
1441
1442         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1443                                    ATH9K_CIPHER_TKIP, NULL)) {
1444                 /*
1445                  * Whether we should enable h/w TKIP MIC.
1446                  * XXX: if we don't support WME TKIP MIC, then we wouldn't
1447                  * report WMM capable, so it's always safe to turn on
1448                  * TKIP MIC in this case.
1449                  */
1450                 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1451                                        0, 1, NULL);
1452         }
1453
1454         /*
1455          * Check whether the separate key cache entries
1456          * are required to handle both tx+rx MIC keys.
1457          * With split mic keys the number of stations is limited
1458          * to 27 otherwise 59.
1459          */
1460         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1461                                    ATH9K_CIPHER_TKIP, NULL)
1462             && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1463                                       ATH9K_CIPHER_MIC, NULL)
1464             && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1465                                       0, NULL))
1466                 sc->sc_splitmic = 1;
1467
1468         /* turn on mcast key search if possible */
1469         if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1470                 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1471                                              1, NULL);
1472
1473         sc->sc_config.txpowlimit = ATH_TXPOWER_MAX;
1474         sc->sc_config.txpowlimit_override = 0;
1475
1476         /* 11n Capabilities */
1477         if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1478                 sc->sc_flags |= SC_OP_TXAGGR;
1479                 sc->sc_flags |= SC_OP_RXAGGR;
1480         }
1481
1482         sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask;
1483         sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask;
1484
1485         ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1486         sc->sc_defant = ath9k_hw_getdefantenna(ah);
1487
1488         ath9k_hw_getmac(ah, sc->sc_myaddr);
1489         if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
1490                 ath9k_hw_getbssidmask(ah, sc->sc_bssidmask);
1491                 ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask);
1492                 ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
1493         }
1494
1495         sc->sc_slottime = ATH9K_SLOT_TIME_9;    /* default to short slot time */
1496
1497         /* initialize beacon slots */
1498         for (i = 0; i < ARRAY_SIZE(sc->sc_bslot); i++)
1499                 sc->sc_bslot[i] = ATH_IF_ID_ANY;
1500
1501         /* save MISC configurations */
1502         sc->sc_config.swBeaconProcess = 1;
1503
1504 #ifdef CONFIG_SLOW_ANT_DIV
1505         /* range is 40 - 255, we use something in the middle */
1506         ath_slow_ant_div_init(&sc->sc_antdiv, sc, 0x127);
1507 #endif
1508
1509         /* setup channels and rates */
1510
1511         sc->sbands[IEEE80211_BAND_2GHZ].channels =
1512                 sc->channels[IEEE80211_BAND_2GHZ];
1513         sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1514                 sc->rates[IEEE80211_BAND_2GHZ];
1515         sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1516
1517         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes)) {
1518                 sc->sbands[IEEE80211_BAND_5GHZ].channels =
1519                         sc->channels[IEEE80211_BAND_5GHZ];
1520                 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1521                         sc->rates[IEEE80211_BAND_5GHZ];
1522                 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1523         }
1524
1525         return 0;
1526 bad2:
1527         /* cleanup tx queues */
1528         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1529                 if (ATH_TXQ_SETUP(sc, i))
1530                         ath_tx_cleanupq(sc, &sc->sc_txq[i]);
1531 bad:
1532         if (ah)
1533                 ath9k_hw_detach(ah);
1534
1535         return error;
1536 }
1537
1538 static int ath_attach(u16 devid, struct ath_softc *sc)
1539 {
1540         struct ieee80211_hw *hw = sc->hw;
1541         int error = 0;
1542
1543         DPRINTF(sc, ATH_DBG_CONFIG, "%s: Attach ATH hw\n", __func__);
1544
1545         error = ath_init(devid, sc);
1546         if (error != 0)
1547                 return error;
1548
1549         /* get mac address from hardware and set in mac80211 */
1550
1551         SET_IEEE80211_PERM_ADDR(hw, sc->sc_myaddr);
1552
1553         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1554                 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1555                 IEEE80211_HW_SIGNAL_DBM |
1556                 IEEE80211_HW_AMPDU_AGGREGATION;
1557
1558         hw->wiphy->interface_modes =
1559                 BIT(NL80211_IFTYPE_AP) |
1560                 BIT(NL80211_IFTYPE_STATION) |
1561                 BIT(NL80211_IFTYPE_ADHOC);
1562
1563         hw->queues = 4;
1564         hw->max_rates = 4;
1565         hw->max_rate_tries = ATH_11N_TXMAXTRY;
1566         hw->sta_data_size = sizeof(struct ath_node);
1567         hw->vif_data_size = sizeof(struct ath_vap);
1568
1569         /* Register rate control */
1570         hw->rate_control_algorithm = "ath9k_rate_control";
1571         error = ath_rate_control_register();
1572         if (error != 0) {
1573                 DPRINTF(sc, ATH_DBG_FATAL,
1574                         "%s: Unable to register rate control "
1575                         "algorithm:%d\n", __func__, error);
1576                 ath_rate_control_unregister();
1577                 goto bad;
1578         }
1579
1580         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1581                 setup_ht_cap(&sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1582                 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1583                         setup_ht_cap(&sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1584         }
1585
1586         hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ];
1587         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->ah_caps.wireless_modes))
1588                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1589                         &sc->sbands[IEEE80211_BAND_5GHZ];
1590
1591         /* initialize tx/rx engine */
1592         error = ath_tx_init(sc, ATH_TXBUF);
1593         if (error != 0)
1594                 goto detach;
1595
1596         error = ath_rx_init(sc, ATH_RXBUF);
1597         if (error != 0)
1598                 goto detach;
1599
1600 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1601         /* Initialze h/w Rfkill */
1602         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1603                 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1604
1605         /* Initialize s/w rfkill */
1606         if (ath_init_sw_rfkill(sc))
1607                 goto detach;
1608 #endif
1609
1610         error = ieee80211_register_hw(hw);
1611         if (error != 0) {
1612                 ath_rate_control_unregister();
1613                 goto bad;
1614         }
1615
1616         /* Initialize LED control */
1617         ath_init_leds(sc);
1618
1619         return 0;
1620 detach:
1621         ath_detach(sc);
1622 bad:
1623         return error;
1624 }
1625
1626 int ath_reset(struct ath_softc *sc, bool retry_tx)
1627 {
1628         struct ath_hal *ah = sc->sc_ah;
1629         int status;
1630         int error = 0;
1631
1632         ath9k_hw_set_interrupts(ah, 0);
1633         ath_draintxq(sc, retry_tx);
1634         ath_stoprecv(sc);
1635         ath_flushrecv(sc);
1636
1637         spin_lock_bh(&sc->sc_resetlock);
1638         if (!ath9k_hw_reset(ah, sc->sc_ah->ah_curchan,
1639                             sc->sc_ht_info.tx_chan_width,
1640                             sc->sc_tx_chainmask, sc->sc_rx_chainmask,
1641                             sc->sc_ht_extprotspacing, false, &status)) {
1642                 DPRINTF(sc, ATH_DBG_FATAL,
1643                         "%s: unable to reset hardware; hal status %u\n",
1644                         __func__, status);
1645                 error = -EIO;
1646         }
1647         spin_unlock_bh(&sc->sc_resetlock);
1648
1649         if (ath_startrecv(sc) != 0)
1650                 DPRINTF(sc, ATH_DBG_FATAL,
1651                         "%s: unable to start recv logic\n", __func__);
1652
1653         /*
1654          * We may be doing a reset in response to a request
1655          * that changes the channel so update any state that
1656          * might change as a result.
1657          */
1658         ath_setcurmode(sc, ath_chan2mode(sc->sc_ah->ah_curchan));
1659
1660         ath_update_txpow(sc);
1661
1662         if (sc->sc_flags & SC_OP_BEACONS)
1663                 ath_beacon_config(sc, ATH_IF_ID_ANY);   /* restart beacons */
1664
1665         ath9k_hw_set_interrupts(ah, sc->sc_imask);
1666
1667         if (retry_tx) {
1668                 int i;
1669                 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1670                         if (ATH_TXQ_SETUP(sc, i)) {
1671                                 spin_lock_bh(&sc->sc_txq[i].axq_lock);
1672                                 ath_txq_schedule(sc, &sc->sc_txq[i]);
1673                                 spin_unlock_bh(&sc->sc_txq[i].axq_lock);
1674                         }
1675                 }
1676         }
1677
1678         return error;
1679 }
1680
1681 /*
1682  *  This function will allocate both the DMA descriptor structure, and the
1683  *  buffers it contains.  These are used to contain the descriptors used
1684  *  by the system.
1685 */
1686 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1687                       struct list_head *head, const char *name,
1688                       int nbuf, int ndesc)
1689 {
1690 #define DS2PHYS(_dd, _ds)                                               \
1691         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1692 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1693 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1694
1695         struct ath_desc *ds;
1696         struct ath_buf *bf;
1697         int i, bsize, error;
1698
1699         DPRINTF(sc, ATH_DBG_CONFIG, "%s: %s DMA: %u buffers %u desc/buf\n",
1700                 __func__, name, nbuf, ndesc);
1701
1702         /* ath_desc must be a multiple of DWORDs */
1703         if ((sizeof(struct ath_desc) % 4) != 0) {
1704                 DPRINTF(sc, ATH_DBG_FATAL, "%s: ath_desc not DWORD aligned\n",
1705                         __func__);
1706                 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1707                 error = -ENOMEM;
1708                 goto fail;
1709         }
1710
1711         dd->dd_name = name;
1712         dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1713
1714         /*
1715          * Need additional DMA memory because we can't use
1716          * descriptors that cross the 4K page boundary. Assume
1717          * one skipped descriptor per 4K page.
1718          */
1719         if (!(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1720                 u32 ndesc_skipped =
1721                         ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1722                 u32 dma_len;
1723
1724                 while (ndesc_skipped) {
1725                         dma_len = ndesc_skipped * sizeof(struct ath_desc);
1726                         dd->dd_desc_len += dma_len;
1727
1728                         ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1729                 };
1730         }
1731
1732         /* allocate descriptors */
1733         dd->dd_desc = pci_alloc_consistent(sc->pdev,
1734                               dd->dd_desc_len,
1735                               &dd->dd_desc_paddr);
1736         if (dd->dd_desc == NULL) {
1737                 error = -ENOMEM;
1738                 goto fail;
1739         }
1740         ds = dd->dd_desc;
1741         DPRINTF(sc, ATH_DBG_CONFIG, "%s: %s DMA map: %p (%u) -> %llx (%u)\n",
1742                 __func__, dd->dd_name, ds, (u32) dd->dd_desc_len,
1743                 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1744
1745         /* allocate buffers */
1746         bsize = sizeof(struct ath_buf) * nbuf;
1747         bf = kmalloc(bsize, GFP_KERNEL);
1748         if (bf == NULL) {
1749                 error = -ENOMEM;
1750                 goto fail2;
1751         }
1752         memset(bf, 0, bsize);
1753         dd->dd_bufptr = bf;
1754
1755         INIT_LIST_HEAD(head);
1756         for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1757                 bf->bf_desc = ds;
1758                 bf->bf_daddr = DS2PHYS(dd, ds);
1759
1760                 if (!(sc->sc_ah->ah_caps.hw_caps &
1761                       ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1762                         /*
1763                          * Skip descriptor addresses which can cause 4KB
1764                          * boundary crossing (addr + length) with a 32 dword
1765                          * descriptor fetch.
1766                          */
1767                         while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1768                                 ASSERT((caddr_t) bf->bf_desc <
1769                                        ((caddr_t) dd->dd_desc +
1770                                         dd->dd_desc_len));
1771
1772                                 ds += ndesc;
1773                                 bf->bf_desc = ds;
1774                                 bf->bf_daddr = DS2PHYS(dd, ds);
1775                         }
1776                 }
1777                 list_add_tail(&bf->list, head);
1778         }
1779         return 0;
1780 fail2:
1781         pci_free_consistent(sc->pdev,
1782                 dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
1783 fail:
1784         memset(dd, 0, sizeof(*dd));
1785         return error;
1786 #undef ATH_DESC_4KB_BOUND_CHECK
1787 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1788 #undef DS2PHYS
1789 }
1790
1791 void ath_descdma_cleanup(struct ath_softc *sc,
1792                          struct ath_descdma *dd,
1793                          struct list_head *head)
1794 {
1795         pci_free_consistent(sc->pdev,
1796                 dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
1797
1798         INIT_LIST_HEAD(head);
1799         kfree(dd->dd_bufptr);
1800         memset(dd, 0, sizeof(*dd));
1801 }
1802
1803 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1804 {
1805         int qnum;
1806
1807         switch (queue) {
1808         case 0:
1809                 qnum = sc->sc_haltype2q[ATH9K_WME_AC_VO];
1810                 break;
1811         case 1:
1812                 qnum = sc->sc_haltype2q[ATH9K_WME_AC_VI];
1813                 break;
1814         case 2:
1815                 qnum = sc->sc_haltype2q[ATH9K_WME_AC_BE];
1816                 break;
1817         case 3:
1818                 qnum = sc->sc_haltype2q[ATH9K_WME_AC_BK];
1819                 break;
1820         default:
1821                 qnum = sc->sc_haltype2q[ATH9K_WME_AC_BE];
1822                 break;
1823         }
1824
1825         return qnum;
1826 }
1827
1828 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1829 {
1830         int qnum;
1831
1832         switch (queue) {
1833         case ATH9K_WME_AC_VO:
1834                 qnum = 0;
1835                 break;
1836         case ATH9K_WME_AC_VI:
1837                 qnum = 1;
1838                 break;
1839         case ATH9K_WME_AC_BE:
1840                 qnum = 2;
1841                 break;
1842         case ATH9K_WME_AC_BK:
1843                 qnum = 3;
1844                 break;
1845         default:
1846                 qnum = -1;
1847                 break;
1848         }
1849
1850         return qnum;
1851 }
1852
1853 /**********************/
1854 /* mac80211 callbacks */
1855 /**********************/
1856
1857 static int ath9k_start(struct ieee80211_hw *hw)
1858 {
1859         struct ath_softc *sc = hw->priv;
1860         struct ieee80211_channel *curchan = hw->conf.channel;
1861         struct ath9k_channel *init_channel;
1862         int error = 0, pos, status;
1863
1864         DPRINTF(sc, ATH_DBG_CONFIG, "%s: Starting driver with "
1865                 "initial channel: %d MHz\n", __func__, curchan->center_freq);
1866
1867         memset(&sc->sc_ht_info, 0, sizeof(struct ath_ht_info));
1868
1869         /* setup initial channel */
1870
1871         pos = ath_get_channel(sc, curchan);
1872         if (pos == -1) {
1873                 DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid channel\n", __func__);
1874                 error = -EINVAL;
1875                 goto error;
1876         }
1877
1878         sc->sc_ah->ah_channels[pos].chanmode =
1879                 (curchan->band == IEEE80211_BAND_2GHZ) ? CHANNEL_G : CHANNEL_A;
1880         init_channel = &sc->sc_ah->ah_channels[pos];
1881
1882         /* Reset SERDES registers */
1883         ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1884
1885         /*
1886          * The basic interface to setting the hardware in a good
1887          * state is ``reset''.  On return the hardware is known to
1888          * be powered up and with interrupts disabled.  This must
1889          * be followed by initialization of the appropriate bits
1890          * and then setup of the interrupt mask.
1891          */
1892         spin_lock_bh(&sc->sc_resetlock);
1893         if (!ath9k_hw_reset(sc->sc_ah, init_channel,
1894                             sc->sc_ht_info.tx_chan_width,
1895                             sc->sc_tx_chainmask, sc->sc_rx_chainmask,
1896                             sc->sc_ht_extprotspacing, false, &status)) {
1897                 DPRINTF(sc, ATH_DBG_FATAL,
1898                         "%s: unable to reset hardware; hal status %u "
1899                         "(freq %u flags 0x%x)\n", __func__, status,
1900                         init_channel->channel, init_channel->channelFlags);
1901                 error = -EIO;
1902                 spin_unlock_bh(&sc->sc_resetlock);
1903                 goto error;
1904         }
1905         spin_unlock_bh(&sc->sc_resetlock);
1906
1907         /*
1908          * This is needed only to setup initial state
1909          * but it's best done after a reset.
1910          */
1911         ath_update_txpow(sc);
1912
1913         /*
1914          * Setup the hardware after reset:
1915          * The receive engine is set going.
1916          * Frame transmit is handled entirely
1917          * in the frame output path; there's nothing to do
1918          * here except setup the interrupt mask.
1919          */
1920         if (ath_startrecv(sc) != 0) {
1921                 DPRINTF(sc, ATH_DBG_FATAL,
1922                         "%s: unable to start recv logic\n", __func__);
1923                 error = -EIO;
1924                 goto error;
1925         }
1926
1927         /* Setup our intr mask. */
1928         sc->sc_imask = ATH9K_INT_RX | ATH9K_INT_TX
1929                 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
1930                 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
1931
1932         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_GTT)
1933                 sc->sc_imask |= ATH9K_INT_GTT;
1934
1935         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
1936                 sc->sc_imask |= ATH9K_INT_CST;
1937
1938         /*
1939          * Enable MIB interrupts when there are hardware phy counters.
1940          * Note we only do this (at the moment) for station mode.
1941          */
1942         if (ath9k_hw_phycounters(sc->sc_ah) &&
1943             ((sc->sc_ah->ah_opmode == ATH9K_M_STA) ||
1944              (sc->sc_ah->ah_opmode == ATH9K_M_IBSS)))
1945                 sc->sc_imask |= ATH9K_INT_MIB;
1946         /*
1947          * Some hardware processes the TIM IE and fires an
1948          * interrupt when the TIM bit is set.  For hardware
1949          * that does, if not overridden by configuration,
1950          * enable the TIM interrupt when operating as station.
1951          */
1952         if ((sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
1953             (sc->sc_ah->ah_opmode == ATH9K_M_STA) &&
1954             !sc->sc_config.swBeaconProcess)
1955                 sc->sc_imask |= ATH9K_INT_TIM;
1956
1957         ath_setcurmode(sc, ath_chan2mode(init_channel));
1958
1959         sc->sc_flags &= ~SC_OP_INVALID;
1960
1961         /* Disable BMISS interrupt when we're not associated */
1962         sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
1963         ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
1964
1965         ieee80211_wake_queues(sc->hw);
1966
1967 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1968         error = ath_start_rfkill_poll(sc);
1969 #endif
1970
1971 error:
1972         return error;
1973 }
1974
1975 static int ath9k_tx(struct ieee80211_hw *hw,
1976                     struct sk_buff *skb)
1977 {
1978         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1979         struct ath_softc *sc = hw->priv;
1980         struct ath_tx_control txctl;
1981         int hdrlen, padsize;
1982
1983         memset(&txctl, 0, sizeof(struct ath_tx_control));
1984
1985         /*
1986          * As a temporary workaround, assign seq# here; this will likely need
1987          * to be cleaned up to work better with Beacon transmission and virtual
1988          * BSSes.
1989          */
1990         if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
1991                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
1992                 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
1993                         sc->seq_no += 0x10;
1994                 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
1995                 hdr->seq_ctrl |= cpu_to_le16(sc->seq_no);
1996         }
1997
1998         /* Add the padding after the header if this is not already done */
1999         hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2000         if (hdrlen & 3) {
2001                 padsize = hdrlen % 4;
2002                 if (skb_headroom(skb) < padsize)
2003                         return -1;
2004                 skb_push(skb, padsize);
2005                 memmove(skb->data, skb->data + padsize, hdrlen);
2006         }
2007
2008         /* Check if a tx queue is available */
2009
2010         txctl.txq = ath_test_get_txq(sc, skb);
2011         if (!txctl.txq)
2012                 goto exit;
2013
2014         DPRINTF(sc, ATH_DBG_XMIT, "%s: transmitting packet, skb: %p\n",
2015                 __func__,
2016                 skb);
2017
2018         if (ath_tx_start(sc, skb, &txctl) != 0) {
2019                 DPRINTF(sc, ATH_DBG_XMIT, "%s: TX failed\n", __func__);
2020                 goto exit;
2021         }
2022
2023         return 0;
2024 exit:
2025         dev_kfree_skb_any(skb);
2026         return 0;
2027 }
2028
2029 static void ath9k_stop(struct ieee80211_hw *hw)
2030 {
2031         struct ath_softc *sc = hw->priv;
2032
2033         if (sc->sc_flags & SC_OP_INVALID) {
2034                 DPRINTF(sc, ATH_DBG_ANY, "%s: Device not present\n", __func__);
2035                 return;
2036         }
2037
2038         DPRINTF(sc, ATH_DBG_CONFIG, "%s: Cleaning up\n", __func__);
2039
2040         ieee80211_stop_queues(sc->hw);
2041
2042         /* make sure h/w will not generate any interrupt
2043          * before setting the invalid flag. */
2044         ath9k_hw_set_interrupts(sc->sc_ah, 0);
2045
2046         if (!(sc->sc_flags & SC_OP_INVALID)) {
2047                 ath_draintxq(sc, false);
2048                 ath_stoprecv(sc);
2049                 ath9k_hw_phy_disable(sc->sc_ah);
2050         } else
2051                 sc->sc_rxlink = NULL;
2052
2053 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2054         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2055                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2056 #endif
2057         /* disable HAL and put h/w to sleep */
2058         ath9k_hw_disable(sc->sc_ah);
2059         ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2060
2061         sc->sc_flags |= SC_OP_INVALID;
2062
2063         DPRINTF(sc, ATH_DBG_CONFIG, "%s: Driver halt\n", __func__);
2064 }
2065
2066 static int ath9k_add_interface(struct ieee80211_hw *hw,
2067                                struct ieee80211_if_init_conf *conf)
2068 {
2069         struct ath_softc *sc = hw->priv;
2070         struct ath_vap *avp = (void *)conf->vif->drv_priv;
2071         int ic_opmode = 0;
2072
2073         /* Support only vap for now */
2074
2075         if (sc->sc_nvaps)
2076                 return -ENOBUFS;
2077
2078         switch (conf->type) {
2079         case NL80211_IFTYPE_STATION:
2080                 ic_opmode = ATH9K_M_STA;
2081                 break;
2082         case NL80211_IFTYPE_ADHOC:
2083                 ic_opmode = ATH9K_M_IBSS;
2084                 break;
2085         case NL80211_IFTYPE_AP:
2086                 ic_opmode = ATH9K_M_HOSTAP;
2087                 break;
2088         default:
2089                 DPRINTF(sc, ATH_DBG_FATAL,
2090                         "%s: Interface type %d not yet supported\n",
2091                         __func__, conf->type);
2092                 return -EOPNOTSUPP;
2093         }
2094
2095         DPRINTF(sc, ATH_DBG_CONFIG, "%s: Attach a VAP of type: %d\n",
2096                 __func__,
2097                 ic_opmode);
2098
2099         /* Set the VAP opmode */
2100         avp->av_opmode = ic_opmode;
2101         avp->av_bslot = -1;
2102
2103         if (ic_opmode == ATH9K_M_HOSTAP)
2104                 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2105
2106         sc->sc_vaps[0] = conf->vif;
2107         sc->sc_nvaps++;
2108
2109         /* Set the device opmode */
2110         sc->sc_ah->ah_opmode = ic_opmode;
2111
2112         if (conf->type == NL80211_IFTYPE_AP) {
2113                 /* TODO: is this a suitable place to start ANI for AP mode? */
2114                 /* Start ANI */
2115                 mod_timer(&sc->sc_ani.timer,
2116                           jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2117         }
2118
2119         return 0;
2120 }
2121
2122 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2123                                    struct ieee80211_if_init_conf *conf)
2124 {
2125         struct ath_softc *sc = hw->priv;
2126         struct ath_vap *avp = (void *)conf->vif->drv_priv;
2127
2128         DPRINTF(sc, ATH_DBG_CONFIG, "%s: Detach VAP\n", __func__);
2129
2130 #ifdef CONFIG_SLOW_ANT_DIV
2131         ath_slow_ant_div_stop(&sc->sc_antdiv);
2132 #endif
2133         /* Stop ANI */
2134         del_timer_sync(&sc->sc_ani.timer);
2135
2136         /* Reclaim beacon resources */
2137         if (sc->sc_ah->ah_opmode == ATH9K_M_HOSTAP ||
2138             sc->sc_ah->ah_opmode == ATH9K_M_IBSS) {
2139                 ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
2140                 ath_beacon_return(sc, avp);
2141         }
2142
2143         sc->sc_flags &= ~SC_OP_BEACONS;
2144
2145         sc->sc_vaps[0] = NULL;
2146         sc->sc_nvaps--;
2147 }
2148
2149 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2150 {
2151         struct ath_softc *sc = hw->priv;
2152         struct ieee80211_channel *curchan = hw->conf.channel;
2153         struct ieee80211_conf *conf = &hw->conf;
2154         int pos;
2155
2156         DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set channel: %d MHz\n",
2157                 __func__,
2158                 curchan->center_freq);
2159
2160         /* Update chainmask */
2161         ath_update_chainmask(sc, conf->ht.enabled);
2162
2163         pos = ath_get_channel(sc, curchan);
2164         if (pos == -1) {
2165                 DPRINTF(sc, ATH_DBG_FATAL, "%s: Invalid channel\n", __func__);
2166                 return -EINVAL;
2167         }
2168
2169         sc->sc_ah->ah_channels[pos].chanmode =
2170                 (curchan->band == IEEE80211_BAND_2GHZ) ?
2171                 CHANNEL_G : CHANNEL_A;
2172
2173         if (sc->sc_curaid && hw->conf.ht.enabled)
2174                 sc->sc_ah->ah_channels[pos].chanmode =
2175                         ath_get_extchanmode(sc, curchan);
2176
2177         if (changed & IEEE80211_CONF_CHANGE_POWER)
2178                 sc->sc_config.txpowlimit = 2 * conf->power_level;
2179
2180         /* set h/w channel */
2181         if (ath_set_channel(sc, &sc->sc_ah->ah_channels[pos]) < 0)
2182                 DPRINTF(sc, ATH_DBG_FATAL, "%s: Unable to set channel\n",
2183                         __func__);
2184
2185         return 0;
2186 }
2187
2188 static int ath9k_config_interface(struct ieee80211_hw *hw,
2189                                   struct ieee80211_vif *vif,
2190                                   struct ieee80211_if_conf *conf)
2191 {
2192         struct ath_softc *sc = hw->priv;
2193         struct ath_hal *ah = sc->sc_ah;
2194         struct ath_vap *avp = (void *)vif->drv_priv;
2195         u32 rfilt = 0;
2196         int error, i;
2197
2198         /* TODO: Need to decide which hw opmode to use for multi-interface
2199          * cases */
2200         if (vif->type == NL80211_IFTYPE_AP &&
2201             ah->ah_opmode != ATH9K_M_HOSTAP) {
2202                 ah->ah_opmode = ATH9K_M_HOSTAP;
2203                 ath9k_hw_setopmode(ah);
2204                 ath9k_hw_write_associd(ah, sc->sc_myaddr, 0);
2205                 /* Request full reset to get hw opmode changed properly */
2206                 sc->sc_flags |= SC_OP_FULL_RESET;
2207         }
2208
2209         if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2210             !is_zero_ether_addr(conf->bssid)) {
2211                 switch (vif->type) {
2212                 case NL80211_IFTYPE_STATION:
2213                 case NL80211_IFTYPE_ADHOC:
2214                         /* Set BSSID */
2215                         memcpy(sc->sc_curbssid, conf->bssid, ETH_ALEN);
2216                         sc->sc_curaid = 0;
2217                         ath9k_hw_write_associd(sc->sc_ah, sc->sc_curbssid,
2218                                                sc->sc_curaid);
2219
2220                         /* Set aggregation protection mode parameters */
2221                         sc->sc_config.ath_aggr_prot = 0;
2222
2223                         DPRINTF(sc, ATH_DBG_CONFIG,
2224                                 "%s: RX filter 0x%x bssid %pM aid 0x%x\n",
2225                                 __func__, rfilt,
2226                                 sc->sc_curbssid, sc->sc_curaid);
2227
2228                         /* need to reconfigure the beacon */
2229                         sc->sc_flags &= ~SC_OP_BEACONS ;
2230
2231                         break;
2232                 default:
2233                         break;
2234                 }
2235         }
2236
2237         if ((conf->changed & IEEE80211_IFCC_BEACON) &&
2238             ((vif->type == NL80211_IFTYPE_ADHOC) ||
2239              (vif->type == NL80211_IFTYPE_AP))) {
2240                 /*
2241                  * Allocate and setup the beacon frame.
2242                  *
2243                  * Stop any previous beacon DMA.  This may be
2244                  * necessary, for example, when an ibss merge
2245                  * causes reconfiguration; we may be called
2246                  * with beacon transmission active.
2247                  */
2248                 ath9k_hw_stoptxdma(sc->sc_ah, sc->sc_bhalq);
2249
2250                 error = ath_beacon_alloc(sc, 0);
2251                 if (error != 0)
2252                         return error;
2253
2254                 ath_beacon_sync(sc, 0);
2255         }
2256
2257         /* Check for WLAN_CAPABILITY_PRIVACY ? */
2258         if ((avp->av_opmode != ATH9K_M_STA)) {
2259                 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2260                         if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2261                                 ath9k_hw_keysetmac(sc->sc_ah,
2262                                                    (u16)i,
2263                                                    sc->sc_curbssid);
2264         }
2265
2266         /* Only legacy IBSS for now */
2267         if (vif->type == NL80211_IFTYPE_ADHOC)
2268                 ath_update_chainmask(sc, 0);
2269
2270         return 0;
2271 }
2272
2273 #define SUPPORTED_FILTERS                       \
2274         (FIF_PROMISC_IN_BSS |                   \
2275         FIF_ALLMULTI |                          \
2276         FIF_CONTROL |                           \
2277         FIF_OTHER_BSS |                         \
2278         FIF_BCN_PRBRESP_PROMISC |               \
2279         FIF_FCSFAIL)
2280
2281 /* FIXME: sc->sc_full_reset ? */
2282 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2283                                    unsigned int changed_flags,
2284                                    unsigned int *total_flags,
2285                                    int mc_count,
2286                                    struct dev_mc_list *mclist)
2287 {
2288         struct ath_softc *sc = hw->priv;
2289         u32 rfilt;
2290
2291         changed_flags &= SUPPORTED_FILTERS;
2292         *total_flags &= SUPPORTED_FILTERS;
2293
2294         sc->rx_filter = *total_flags;
2295         rfilt = ath_calcrxfilter(sc);
2296         ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2297
2298         if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
2299                 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
2300                         ath9k_hw_write_associd(sc->sc_ah, ath_bcast_mac, 0);
2301         }
2302
2303         DPRINTF(sc, ATH_DBG_CONFIG, "%s: Set HW RX filter: 0x%x\n",
2304                 __func__, sc->rx_filter);
2305 }
2306
2307 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2308                              struct ieee80211_vif *vif,
2309                              enum sta_notify_cmd cmd,
2310                              struct ieee80211_sta *sta)
2311 {
2312         struct ath_softc *sc = hw->priv;
2313
2314         switch (cmd) {
2315         case STA_NOTIFY_ADD:
2316                 ath_node_attach(sc, sta);
2317                 break;
2318         case STA_NOTIFY_REMOVE:
2319                 ath_node_detach(sc, sta);
2320                 break;
2321         default:
2322                 break;
2323         }
2324 }
2325
2326 static int ath9k_conf_tx(struct ieee80211_hw *hw,
2327                          u16 queue,
2328                          const struct ieee80211_tx_queue_params *params)
2329 {
2330         struct ath_softc *sc = hw->priv;
2331         struct ath9k_tx_queue_info qi;
2332         int ret = 0, qnum;
2333
2334         if (queue >= WME_NUM_AC)
2335                 return 0;
2336
2337         qi.tqi_aifs = params->aifs;
2338         qi.tqi_cwmin = params->cw_min;
2339         qi.tqi_cwmax = params->cw_max;
2340         qi.tqi_burstTime = params->txop;
2341         qnum = ath_get_hal_qnum(queue, sc);
2342
2343         DPRINTF(sc, ATH_DBG_CONFIG,
2344                 "%s: Configure tx [queue/halq] [%d/%d],  "
2345                 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2346                 __func__,
2347                 queue,
2348                 qnum,
2349                 params->aifs,
2350                 params->cw_min,
2351                 params->cw_max,
2352                 params->txop);
2353
2354         ret = ath_txq_update(sc, qnum, &qi);
2355         if (ret)
2356                 DPRINTF(sc, ATH_DBG_FATAL,
2357                         "%s: TXQ Update failed\n", __func__);
2358
2359         return ret;
2360 }
2361
2362 static int ath9k_set_key(struct ieee80211_hw *hw,
2363                          enum set_key_cmd cmd,
2364                          const u8 *local_addr,
2365                          const u8 *addr,
2366                          struct ieee80211_key_conf *key)
2367 {
2368         struct ath_softc *sc = hw->priv;
2369         int ret = 0;
2370
2371         DPRINTF(sc, ATH_DBG_KEYCACHE, " %s: Set HW Key\n", __func__);
2372
2373         switch (cmd) {
2374         case SET_KEY:
2375                 ret = ath_key_config(sc, addr, key);
2376                 if (!ret) {
2377                         set_bit(key->keyidx, sc->sc_keymap);
2378                         key->hw_key_idx = key->keyidx;
2379                         /* push IV and Michael MIC generation to stack */
2380                         key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2381                         if (key->alg == ALG_TKIP)
2382                                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2383                 }
2384                 break;
2385         case DISABLE_KEY:
2386                 ath_key_delete(sc, key);
2387                 clear_bit(key->keyidx, sc->sc_keymap);
2388                 break;
2389         default:
2390                 ret = -EINVAL;
2391         }
2392
2393         return ret;
2394 }
2395
2396 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2397                                    struct ieee80211_vif *vif,
2398                                    struct ieee80211_bss_conf *bss_conf,
2399                                    u32 changed)
2400 {
2401         struct ath_softc *sc = hw->priv;
2402
2403         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2404                 DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed PREAMBLE %d\n",
2405                         __func__,
2406                         bss_conf->use_short_preamble);
2407                 if (bss_conf->use_short_preamble)
2408                         sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2409                 else
2410                         sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2411         }
2412
2413         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2414                 DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed CTS PROT %d\n",
2415                         __func__,
2416                         bss_conf->use_cts_prot);
2417                 if (bss_conf->use_cts_prot &&
2418                     hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2419                         sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2420                 else
2421                         sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2422         }
2423
2424         if (changed & BSS_CHANGED_HT) {
2425                 DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed HT\n",
2426                         __func__);
2427                 ath9k_ht_conf(sc, bss_conf);
2428         }
2429
2430         if (changed & BSS_CHANGED_ASSOC) {
2431                 DPRINTF(sc, ATH_DBG_CONFIG, "%s: BSS Changed ASSOC %d\n",
2432                         __func__,
2433                         bss_conf->assoc);
2434                 ath9k_bss_assoc_info(sc, vif, bss_conf);
2435         }
2436 }
2437
2438 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2439 {
2440         u64 tsf;
2441         struct ath_softc *sc = hw->priv;
2442         struct ath_hal *ah = sc->sc_ah;
2443
2444         tsf = ath9k_hw_gettsf64(ah);
2445
2446         return tsf;
2447 }
2448
2449 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2450 {
2451         struct ath_softc *sc = hw->priv;
2452         struct ath_hal *ah = sc->sc_ah;
2453
2454         ath9k_hw_reset_tsf(ah);
2455 }
2456
2457 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2458                        enum ieee80211_ampdu_mlme_action action,
2459                        struct ieee80211_sta *sta,
2460                        u16 tid, u16 *ssn)
2461 {
2462         struct ath_softc *sc = hw->priv;
2463         int ret = 0;
2464
2465         switch (action) {
2466         case IEEE80211_AMPDU_RX_START:
2467                 if (!(sc->sc_flags & SC_OP_RXAGGR))
2468                         ret = -ENOTSUPP;
2469                 break;
2470         case IEEE80211_AMPDU_RX_STOP:
2471                 break;
2472         case IEEE80211_AMPDU_TX_START:
2473                 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2474                 if (ret < 0)
2475                         DPRINTF(sc, ATH_DBG_FATAL,
2476                                 "%s: Unable to start TX aggregation\n",
2477                                 __func__);
2478                 else
2479                         ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2480                 break;
2481         case IEEE80211_AMPDU_TX_STOP:
2482                 ret = ath_tx_aggr_stop(sc, sta, tid);
2483                 if (ret < 0)
2484                         DPRINTF(sc, ATH_DBG_FATAL,
2485                                 "%s: Unable to stop TX aggregation\n",
2486                                 __func__);
2487
2488                 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2489                 break;
2490         case IEEE80211_AMPDU_TX_RESUME:
2491                 ath_tx_aggr_resume(sc, sta, tid);
2492                 break;
2493         default:
2494                 DPRINTF(sc, ATH_DBG_FATAL,
2495                         "%s: Unknown AMPDU action\n", __func__);
2496         }
2497
2498         return ret;
2499 }
2500
2501 static int ath9k_no_fragmentation(struct ieee80211_hw *hw, u32 value)
2502 {
2503         return -EOPNOTSUPP;
2504 }
2505
2506 static struct ieee80211_ops ath9k_ops = {
2507         .tx                 = ath9k_tx,
2508         .start              = ath9k_start,
2509         .stop               = ath9k_stop,
2510         .add_interface      = ath9k_add_interface,
2511         .remove_interface   = ath9k_remove_interface,
2512         .config             = ath9k_config,
2513         .config_interface   = ath9k_config_interface,
2514         .configure_filter   = ath9k_configure_filter,
2515         .sta_notify         = ath9k_sta_notify,
2516         .conf_tx            = ath9k_conf_tx,
2517         .bss_info_changed   = ath9k_bss_info_changed,
2518         .set_key            = ath9k_set_key,
2519         .get_tsf            = ath9k_get_tsf,
2520         .reset_tsf          = ath9k_reset_tsf,
2521         .ampdu_action       = ath9k_ampdu_action,
2522         .set_frag_threshold = ath9k_no_fragmentation,
2523 };
2524
2525 static struct {
2526         u32 version;
2527         const char * name;
2528 } ath_mac_bb_names[] = {
2529         { AR_SREV_VERSION_5416_PCI,     "5416" },
2530         { AR_SREV_VERSION_5416_PCIE,    "5418" },
2531         { AR_SREV_VERSION_9100,         "9100" },
2532         { AR_SREV_VERSION_9160,         "9160" },
2533         { AR_SREV_VERSION_9280,         "9280" },
2534         { AR_SREV_VERSION_9285,         "9285" }
2535 };
2536
2537 static struct {
2538         u16 version;
2539         const char * name;
2540 } ath_rf_names[] = {
2541         { 0,                            "5133" },
2542         { AR_RAD5133_SREV_MAJOR,        "5133" },
2543         { AR_RAD5122_SREV_MAJOR,        "5122" },
2544         { AR_RAD2133_SREV_MAJOR,        "2133" },
2545         { AR_RAD2122_SREV_MAJOR,        "2122" }
2546 };
2547
2548 /*
2549  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2550  */
2551
2552 static const char *
2553 ath_mac_bb_name(u32 mac_bb_version)
2554 {
2555         int i;
2556
2557         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2558                 if (ath_mac_bb_names[i].version == mac_bb_version) {
2559                         return ath_mac_bb_names[i].name;
2560                 }
2561         }
2562
2563         return "????";
2564 }
2565
2566 /*
2567  * Return the RF name. "????" is returned if the RF is unknown.
2568  */
2569
2570 static const char *
2571 ath_rf_name(u16 rf_version)
2572 {
2573         int i;
2574
2575         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2576                 if (ath_rf_names[i].version == rf_version) {
2577                         return ath_rf_names[i].name;
2578                 }
2579         }
2580
2581         return "????";
2582 }
2583
2584 static int ath_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2585 {
2586         void __iomem *mem;
2587         struct ath_softc *sc;
2588         struct ieee80211_hw *hw;
2589         u8 csz;
2590         u32 val;
2591         int ret = 0;
2592         struct ath_hal *ah;
2593
2594         if (pci_enable_device(pdev))
2595                 return -EIO;
2596
2597         ret =  pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2598
2599         if (ret) {
2600                 printk(KERN_ERR "ath9k: 32-bit DMA not available\n");
2601                 goto bad;
2602         }
2603
2604         ret = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
2605
2606         if (ret) {
2607                 printk(KERN_ERR "ath9k: 32-bit DMA consistent "
2608                         "DMA enable faled\n");
2609                 goto bad;
2610         }
2611
2612         /*
2613          * Cache line size is used to size and align various
2614          * structures used to communicate with the hardware.
2615          */
2616         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
2617         if (csz == 0) {
2618                 /*
2619                  * Linux 2.4.18 (at least) writes the cache line size
2620                  * register as a 16-bit wide register which is wrong.
2621                  * We must have this setup properly for rx buffer
2622                  * DMA to work so force a reasonable value here if it
2623                  * comes up zero.
2624                  */
2625                 csz = L1_CACHE_BYTES / sizeof(u32);
2626                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
2627         }
2628         /*
2629          * The default setting of latency timer yields poor results,
2630          * set it to the value used by other systems. It may be worth
2631          * tweaking this setting more.
2632          */
2633         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
2634
2635         pci_set_master(pdev);
2636
2637         /*
2638          * Disable the RETRY_TIMEOUT register (0x41) to keep
2639          * PCI Tx retries from interfering with C3 CPU state.
2640          */
2641         pci_read_config_dword(pdev, 0x40, &val);
2642         if ((val & 0x0000ff00) != 0)
2643                 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2644
2645         ret = pci_request_region(pdev, 0, "ath9k");
2646         if (ret) {
2647                 dev_err(&pdev->dev, "PCI memory region reserve error\n");
2648                 ret = -ENODEV;
2649                 goto bad;
2650         }
2651
2652         mem = pci_iomap(pdev, 0, 0);
2653         if (!mem) {
2654                 printk(KERN_ERR "PCI memory map error\n") ;
2655                 ret = -EIO;
2656                 goto bad1;
2657         }
2658
2659         hw = ieee80211_alloc_hw(sizeof(struct ath_softc), &ath9k_ops);
2660         if (hw == NULL) {
2661                 printk(KERN_ERR "ath_pci: no memory for ieee80211_hw\n");
2662                 goto bad2;
2663         }
2664
2665         SET_IEEE80211_DEV(hw, &pdev->dev);
2666         pci_set_drvdata(pdev, hw);
2667
2668         sc = hw->priv;
2669         sc->hw = hw;
2670         sc->pdev = pdev;
2671         sc->mem = mem;
2672
2673         if (ath_attach(id->device, sc) != 0) {
2674                 ret = -ENODEV;
2675                 goto bad3;
2676         }
2677
2678         /* setup interrupt service routine */
2679
2680         if (request_irq(pdev->irq, ath_isr, IRQF_SHARED, "ath", sc)) {
2681                 printk(KERN_ERR "%s: request_irq failed\n",
2682                         wiphy_name(hw->wiphy));
2683                 ret = -EIO;
2684                 goto bad4;
2685         }
2686
2687         ah = sc->sc_ah;
2688         printk(KERN_INFO
2689                "%s: Atheros AR%s MAC/BB Rev:%x "
2690                "AR%s RF Rev:%x: mem=0x%lx, irq=%d\n",
2691                wiphy_name(hw->wiphy),
2692                ath_mac_bb_name(ah->ah_macVersion),
2693                ah->ah_macRev,
2694                ath_rf_name((ah->ah_analog5GhzRev & AR_RADIO_SREV_MAJOR)),
2695                ah->ah_phyRev,
2696                (unsigned long)mem, pdev->irq);
2697
2698         return 0;
2699 bad4:
2700         ath_detach(sc);
2701 bad3:
2702         ieee80211_free_hw(hw);
2703 bad2:
2704         pci_iounmap(pdev, mem);
2705 bad1:
2706         pci_release_region(pdev, 0);
2707 bad:
2708         pci_disable_device(pdev);
2709         return ret;
2710 }
2711
2712 static void ath_pci_remove(struct pci_dev *pdev)
2713 {
2714         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2715         struct ath_softc *sc = hw->priv;
2716
2717         ath_detach(sc);
2718         if (pdev->irq)
2719                 free_irq(pdev->irq, sc);
2720         pci_iounmap(pdev, sc->mem);
2721         pci_release_region(pdev, 0);
2722         pci_disable_device(pdev);
2723         ieee80211_free_hw(hw);
2724 }
2725
2726 #ifdef CONFIG_PM
2727
2728 static int ath_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2729 {
2730         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2731         struct ath_softc *sc = hw->priv;
2732
2733         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
2734
2735 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2736         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2737                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2738 #endif
2739
2740         pci_save_state(pdev);
2741         pci_disable_device(pdev);
2742         pci_set_power_state(pdev, 3);
2743
2744         return 0;
2745 }
2746
2747 static int ath_pci_resume(struct pci_dev *pdev)
2748 {
2749         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2750         struct ath_softc *sc = hw->priv;
2751         u32 val;
2752         int err;
2753
2754         err = pci_enable_device(pdev);
2755         if (err)
2756                 return err;
2757         pci_restore_state(pdev);
2758         /*
2759          * Suspend/Resume resets the PCI configuration space, so we have to
2760          * re-disable the RETRY_TIMEOUT register (0x41) to keep
2761          * PCI Tx retries from interfering with C3 CPU state
2762          */
2763         pci_read_config_dword(pdev, 0x40, &val);
2764         if ((val & 0x0000ff00) != 0)
2765                 pci_write_config_dword(pdev, 0x40, val & 0xffff00ff);
2766
2767         /* Enable LED */
2768         ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
2769                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
2770         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
2771
2772 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2773         /*
2774          * check the h/w rfkill state on resume
2775          * and start the rfkill poll timer
2776          */
2777         if (sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2778                 queue_delayed_work(sc->hw->workqueue,
2779                                    &sc->rf_kill.rfkill_poll, 0);
2780 #endif
2781
2782         return 0;
2783 }
2784
2785 #endif /* CONFIG_PM */
2786
2787 MODULE_DEVICE_TABLE(pci, ath_pci_id_table);
2788
2789 static struct pci_driver ath_pci_driver = {
2790         .name       = "ath9k",
2791         .id_table   = ath_pci_id_table,
2792         .probe      = ath_pci_probe,
2793         .remove     = ath_pci_remove,
2794 #ifdef CONFIG_PM
2795         .suspend    = ath_pci_suspend,
2796         .resume     = ath_pci_resume,
2797 #endif /* CONFIG_PM */
2798 };
2799
2800 static int __init init_ath_pci(void)
2801 {
2802         printk(KERN_INFO "%s: %s\n", dev_info, ATH_PCI_VERSION);
2803
2804         if (pci_register_driver(&ath_pci_driver) < 0) {
2805                 printk(KERN_ERR
2806                         "ath_pci: No devices found, driver not installed.\n");
2807                 pci_unregister_driver(&ath_pci_driver);
2808                 return -ENODEV;
2809         }
2810
2811         return 0;
2812 }
2813 module_init(init_ath_pci);
2814
2815 static void __exit exit_ath_pci(void)
2816 {
2817         pci_unregister_driver(&ath_pci_driver);
2818         printk(KERN_INFO "%s: driver unloaded\n", dev_info);
2819 }
2820 module_exit(exit_ath_pci);