SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/ath9k/main.c

   1 /*
   2  * Copyright (c) 2008 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/nl80211.h>
  18 #include "ath9k.h"
  19
  20 #define ATH_PCI_VERSION "0.1"
  21
  22 static char *dev_info = "ath9k";
  23
  24 MODULE_AUTHOR("Atheros Communications");
  25 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  26 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  27 MODULE_LICENSE("Dual BSD/GPL");
  28
  29 static int modparam_nohwcrypt;
  30 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
  31 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
  32
  33 /* We use the hw_value as an index into our private channel structure */
  34
  35 #define CHAN2G(_freq, _idx)  { \
  36         .center_freq = (_freq), \
  37         .hw_value = (_idx), \
  38         .max_power = 30, \
  39 }
  40
  41 #define CHAN5G(_freq, _idx) { \
  42         .band = IEEE80211_BAND_5GHZ, \
  43         .center_freq = (_freq), \
  44         .hw_value = (_idx), \
  45         .max_power = 30, \
  46 }
  47
  48 /* Some 2 GHz radios are actually tunable on 2312-2732
  49  * on 5 MHz steps, we support the channels which we know
  50  * we have calibration data for all cards though to make
  51  * this static */
  52 static struct ieee80211_channel ath9k_2ghz_chantable[] = {
  53         CHAN2G(2412, 0), /* Channel 1 */
  54         CHAN2G(2417, 1), /* Channel 2 */
  55         CHAN2G(2422, 2), /* Channel 3 */
  56         CHAN2G(2427, 3), /* Channel 4 */
  57         CHAN2G(2432, 4), /* Channel 5 */
  58         CHAN2G(2437, 5), /* Channel 6 */
  59         CHAN2G(2442, 6), /* Channel 7 */
  60         CHAN2G(2447, 7), /* Channel 8 */
  61         CHAN2G(2452, 8), /* Channel 9 */
  62         CHAN2G(2457, 9), /* Channel 10 */
  63         CHAN2G(2462, 10), /* Channel 11 */
  64         CHAN2G(2467, 11), /* Channel 12 */
  65         CHAN2G(2472, 12), /* Channel 13 */
  66         CHAN2G(2484, 13), /* Channel 14 */
  67 };
  68
  69 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
  70  * on 5 MHz steps, we support the channels which we know
  71  * we have calibration data for all cards though to make
  72  * this static */
  73 static struct ieee80211_channel ath9k_5ghz_chantable[] = {
  74         /* _We_ call this UNII 1 */
  75         CHAN5G(5180, 14), /* Channel 36 */
  76         CHAN5G(5200, 15), /* Channel 40 */
  77         CHAN5G(5220, 16), /* Channel 44 */
  78         CHAN5G(5240, 17), /* Channel 48 */
  79         /* _We_ call this UNII 2 */
  80         CHAN5G(5260, 18), /* Channel 52 */
  81         CHAN5G(5280, 19), /* Channel 56 */
  82         CHAN5G(5300, 20), /* Channel 60 */
  83         CHAN5G(5320, 21), /* Channel 64 */
  84         /* _We_ call this "Middle band" */
  85         CHAN5G(5500, 22), /* Channel 100 */
  86         CHAN5G(5520, 23), /* Channel 104 */
  87         CHAN5G(5540, 24), /* Channel 108 */
  88         CHAN5G(5560, 25), /* Channel 112 */
  89         CHAN5G(5580, 26), /* Channel 116 */
  90         CHAN5G(5600, 27), /* Channel 120 */
  91         CHAN5G(5620, 28), /* Channel 124 */
  92         CHAN5G(5640, 29), /* Channel 128 */
  93         CHAN5G(5660, 30), /* Channel 132 */
  94         CHAN5G(5680, 31), /* Channel 136 */
  95         CHAN5G(5700, 32), /* Channel 140 */
  96         /* _We_ call this UNII 3 */
  97         CHAN5G(5745, 33), /* Channel 149 */
  98         CHAN5G(5765, 34), /* Channel 153 */
  99         CHAN5G(5785, 35), /* Channel 157 */
 100         CHAN5G(5805, 36), /* Channel 161 */
 101         CHAN5G(5825, 37), /* Channel 165 */
 102 };
 103
 104 static void ath_cache_conf_rate(struct ath_softc *sc,
 105                                 struct ieee80211_conf *conf)
 106 {
 107         switch (conf->channel->band) {
 108         case IEEE80211_BAND_2GHZ:
 109                 if (conf_is_ht20(conf))
 110                         sc->cur_rate_table =
 111                           sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
 112                 else if (conf_is_ht40_minus(conf))
 113                         sc->cur_rate_table =
 114                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
 115                 else if (conf_is_ht40_plus(conf))
 116                         sc->cur_rate_table =
 117                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
 118                 else
 119                         sc->cur_rate_table =
 120                           sc->hw_rate_table[ATH9K_MODE_11G];
 121                 break;
 122         case IEEE80211_BAND_5GHZ:
 123                 if (conf_is_ht20(conf))
 124                         sc->cur_rate_table =
 125                           sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
 126                 else if (conf_is_ht40_minus(conf))
 127                         sc->cur_rate_table =
 128                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
 129                 else if (conf_is_ht40_plus(conf))
 130                         sc->cur_rate_table =
 131                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
 132                 else
 133                         sc->cur_rate_table =
 134                           sc->hw_rate_table[ATH9K_MODE_11A];
 135                 break;
 136         default:
 137                 BUG_ON(1);
 138                 break;
 139         }
 140 }
 141
 142 static void ath_update_txpow(struct ath_softc *sc)
 143 {
 144         struct ath_hw *ah = sc->sc_ah;
 145         u32 txpow;
 146
 147         if (sc->curtxpow != sc->config.txpowlimit) {
 148                 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
 149                 /* read back in case value is clamped */
 150                 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
 151                 sc->curtxpow = txpow;
 152         }
 153 }
 154
 155 static u8 parse_mpdudensity(u8 mpdudensity)
 156 {
 157         /*
 158          * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
 159          *   0 for no restriction
 160          *   1 for 1/4 us
 161          *   2 for 1/2 us
 162          *   3 for 1 us
 163          *   4 for 2 us
 164          *   5 for 4 us
 165          *   6 for 8 us
 166          *   7 for 16 us
 167          */
 168         switch (mpdudensity) {
 169         case 0:
 170                 return 0;
 171         case 1:
 172         case 2:
 173         case 3:
 174                 /* Our lower layer calculations limit our precision to
 175                    1 microsecond */
 176                 return 1;
 177         case 4:
 178                 return 2;
 179         case 5:
 180                 return 4;
 181         case 6:
 182                 return 8;
 183         case 7:
 184                 return 16;
 185         default:
 186                 return 0;
 187         }
 188 }
 189
 190 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
 191 {
 192         struct ath_rate_table *rate_table = NULL;
 193         struct ieee80211_supported_band *sband;
 194         struct ieee80211_rate *rate;
 195         int i, maxrates;
 196
 197         switch (band) {
 198         case IEEE80211_BAND_2GHZ:
 199                 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
 200                 break;
 201         case IEEE80211_BAND_5GHZ:
 202                 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
 203                 break;
 204         default:
 205                 break;
 206         }
 207
 208         if (rate_table == NULL)
 209                 return;
 210
 211         sband = &sc->sbands[band];
 212         rate = sc->rates[band];
 213
 214         if (rate_table->rate_cnt > ATH_RATE_MAX)
 215                 maxrates = ATH_RATE_MAX;
 216         else
 217                 maxrates = rate_table->rate_cnt;
 218
 219         for (i = 0; i < maxrates; i++) {
 220                 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
 221                 rate[i].hw_value = rate_table->info[i].ratecode;
 222                 if (rate_table->info[i].short_preamble) {
 223                         rate[i].hw_value_short = rate_table->info[i].ratecode |
 224                                 rate_table->info[i].short_preamble;
 225                         rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
 226                 }
 227                 sband->n_bitrates++;
 228
 229                 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
 230                         rate[i].bitrate / 10, rate[i].hw_value);
 231         }
 232 }
 233
 234 /*
 235  * Set/change channels.  If the channel is really being changed, it's done
 236  * by reseting the chip.  To accomplish this we must first cleanup any pending
 237  * DMA, then restart stuff.
 238 */
 239 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
 240                     struct ath9k_channel *hchan)
 241 {
 242         struct ath_hw *ah = sc->sc_ah;
 243         bool fastcc = true, stopped;
 244         struct ieee80211_channel *channel = hw->conf.channel;
 245         int r;
 246
 247         if (sc->sc_flags & SC_OP_INVALID)
 248                 return -EIO;
 249
 250         ath9k_ps_wakeup(sc);
 251
 252         /*
 253          * This is only performed if the channel settings have
 254          * actually changed.
 255          *
 256          * To switch channels clear any pending DMA operations;
 257          * wait long enough for the RX fifo to drain, reset the
 258          * hardware at the new frequency, and then re-enable
 259          * the relevant bits of the h/w.
 260          */
 261         ath9k_hw_set_interrupts(ah, 0);
 262         ath_drain_all_txq(sc, false);
 263         stopped = ath_stoprecv(sc);
 264
 265         /* XXX: do not flush receive queue here. We don't want
 266          * to flush data frames already in queue because of
 267          * changing channel. */
 268
 269         if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
 270                 fastcc = false;
 271
 272         DPRINTF(sc, ATH_DBG_CONFIG,
 273                 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
 274                 sc->sc_ah->curchan->channel,
 275                 channel->center_freq, sc->tx_chan_width);
 276
 277         spin_lock_bh(&sc->sc_resetlock);
 278
 279         r = ath9k_hw_reset(ah, hchan, fastcc);
 280         if (r) {
 281                 DPRINTF(sc, ATH_DBG_FATAL,
 282                         "Unable to reset channel (%u Mhz) "
 283                         "reset status %u\n",
 284                         channel->center_freq, r);
 285                 spin_unlock_bh(&sc->sc_resetlock);
 286                 return r;
 287         }
 288         spin_unlock_bh(&sc->sc_resetlock);
 289
 290         sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
 291         sc->sc_flags &= ~SC_OP_FULL_RESET;
 292
 293         if (ath_startrecv(sc) != 0) {
 294                 DPRINTF(sc, ATH_DBG_FATAL,
 295                         "Unable to restart recv logic\n");
 296                 return -EIO;
 297         }
 298
 299         ath_cache_conf_rate(sc, &hw->conf);
 300         ath_update_txpow(sc);
 301         ath9k_hw_set_interrupts(ah, sc->imask);
 302         ath9k_ps_restore(sc);
 303         return 0;
 304 }
 305
 306 /*
 307  *  This routine performs the periodic noise floor calibration function
 308  *  that is used to adjust and optimize the chip performance.  This
 309  *  takes environmental changes (location, temperature) into account.
 310  *  When the task is complete, it reschedules itself depending on the
 311  *  appropriate interval that was calculated.
 312  */
 313 static void ath_ani_calibrate(unsigned long data)
 314 {
 315         struct ath_softc *sc = (struct ath_softc *)data;
 316         struct ath_hw *ah = sc->sc_ah;
 317         bool longcal = false;
 318         bool shortcal = false;
 319         bool aniflag = false;
 320         unsigned int timestamp = jiffies_to_msecs(jiffies);
 321         u32 cal_interval, short_cal_interval;
 322
 323         short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
 324                 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
 325
 326         /*
 327         * don't calibrate when we're scanning.
 328         * we are most likely not on our home channel.
 329         */
 330         if (sc->sc_flags & SC_OP_SCANNING)
 331                 goto set_timer;
 332
 333         /* Long calibration runs independently of short calibration. */
 334         if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
 335                 longcal = true;
 336                 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
 337                 sc->ani.longcal_timer = timestamp;
 338         }
 339
 340         /* Short calibration applies only while caldone is false */
 341         if (!sc->ani.caldone) {
 342                 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
 343                         shortcal = true;
 344                         DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
 345                         sc->ani.shortcal_timer = timestamp;
 346                         sc->ani.resetcal_timer = timestamp;
 347                 }
 348         } else {
 349                 if ((timestamp - sc->ani.resetcal_timer) >=
 350                     ATH_RESTART_CALINTERVAL) {
 351                         sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
 352                         if (sc->ani.caldone)
 353                                 sc->ani.resetcal_timer = timestamp;
 354                 }
 355         }
 356
 357         /* Verify whether we must check ANI */
 358         if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
 359                 aniflag = true;
 360                 sc->ani.checkani_timer = timestamp;
 361         }
 362
 363         /* Skip all processing if there's nothing to do. */
 364         if (longcal || shortcal || aniflag) {
 365                 /* Call ANI routine if necessary */
 366                 if (aniflag)
 367                         ath9k_hw_ani_monitor(ah, &sc->nodestats, ah->curchan);
 368
 369                 /* Perform calibration if necessary */
 370                 if (longcal || shortcal) {
 371                         bool iscaldone = false;
 372
 373                         if (ath9k_hw_calibrate(ah, ah->curchan,
 374                                                sc->rx_chainmask, longcal,
 375                                                &iscaldone)) {
 376                                 if (longcal)
 377                                         sc->ani.noise_floor =
 378                                                 ath9k_hw_getchan_noise(ah,
 379                                                                ah->curchan);
 380
 381                                 DPRINTF(sc, ATH_DBG_ANI,
 382                                         "calibrate chan %u/%x nf: %d\n",
 383                                         ah->curchan->channel,
 384                                         ah->curchan->channelFlags,
 385                                         sc->ani.noise_floor);
 386                         } else {
 387                                 DPRINTF(sc, ATH_DBG_ANY,
 388                                         "calibrate chan %u/%x failed\n",
 389                                         ah->curchan->channel,
 390                                         ah->curchan->channelFlags);
 391                         }
 392                         sc->ani.caldone = iscaldone;
 393                 }
 394         }
 395
 396 set_timer:
 397         /*
 398         * Set timer interval based on previous results.
 399         * The interval must be the shortest necessary to satisfy ANI,
 400         * short calibration and long calibration.
 401         */
 402         cal_interval = ATH_LONG_CALINTERVAL;
 403         if (sc->sc_ah->config.enable_ani)
 404                 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
 405         if (!sc->ani.caldone)
 406                 cal_interval = min(cal_interval, (u32)short_cal_interval);
 407
 408         mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
 409 }
 410
 411 /*
 412  * Update tx/rx chainmask. For legacy association,
 413  * hard code chainmask to 1x1, for 11n association, use
 414  * the chainmask configuration, for bt coexistence, use
 415  * the chainmask configuration even in legacy mode.
 416  */
 417 void ath_update_chainmask(struct ath_softc *sc, int is_ht)
 418 {
 419         sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
 420         if (is_ht ||
 421             (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
 422                 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
 423                 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
 424         } else {
 425                 sc->tx_chainmask = 1;
 426                 sc->rx_chainmask = 1;
 427         }
 428
 429         DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
 430                 sc->tx_chainmask, sc->rx_chainmask);
 431 }
 432
 433 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
 434 {
 435         struct ath_node *an;
 436
 437         an = (struct ath_node *)sta->drv_priv;
 438
 439         if (sc->sc_flags & SC_OP_TXAGGR)
 440                 ath_tx_node_init(sc, an);
 441
 442         an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
 443                              sta->ht_cap.ampdu_factor);
 444         an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
 445 }
 446
 447 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
 448 {
 449         struct ath_node *an = (struct ath_node *)sta->drv_priv;
 450
 451         if (sc->sc_flags & SC_OP_TXAGGR)
 452                 ath_tx_node_cleanup(sc, an);
 453 }
 454
 455 static void ath9k_tasklet(unsigned long data)
 456 {
 457         struct ath_softc *sc = (struct ath_softc *)data;
 458         u32 status = sc->intrstatus;
 459
 460         if (status & ATH9K_INT_FATAL) {
 461                 /* need a chip reset */
 462                 ath_reset(sc, false);
 463                 return;
 464         } else {
 465
 466                 if (status &
 467                     (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
 468                         spin_lock_bh(&sc->rx.rxflushlock);
 469                         ath_rx_tasklet(sc, 0);
 470                         spin_unlock_bh(&sc->rx.rxflushlock);
 471                 }
 472                 /* XXX: optimize this */
 473                 if (status & ATH9K_INT_TX)
 474                         ath_tx_tasklet(sc);
 475         }
 476
 477         /* re-enable hardware interrupt */
 478         ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
 479 }
 480
 481 irqreturn_t ath_isr(int irq, void *dev)
 482 {
 483         struct ath_softc *sc = dev;
 484         struct ath_hw *ah = sc->sc_ah;
 485         enum ath9k_int status;
 486         bool sched = false;
 487
 488         do {
 489                 if (sc->sc_flags & SC_OP_INVALID) {
 490                         /*
 491                          * The hardware is not ready/present, don't
 492                          * touch anything. Note this can happen early
 493                          * on if the IRQ is shared.
 494                          */
 495                         return IRQ_NONE;
 496                 }
 497                 if (!ath9k_hw_intrpend(ah)) {   /* shared irq, not for us */
 498                         return IRQ_NONE;
 499                 }
 500
 501                 /*
 502                  * Figure out the reason(s) for the interrupt.  Note
 503                  * that the hal returns a pseudo-ISR that may include
 504                  * bits we haven't explicitly enabled so we mask the
 505                  * value to insure we only process bits we requested.
 506                  */
 507                 ath9k_hw_getisr(ah, &status);   /* NB: clears ISR too */
 508
 509                 status &= sc->imask;    /* discard unasked-for bits */
 510
 511                 /*
 512                  * If there are no status bits set, then this interrupt was not
 513                  * for me (should have been caught above).
 514                  */
 515                 if (!status)
 516                         return IRQ_NONE;
 517
 518                 sc->intrstatus = status;
 519                 ath9k_ps_wakeup(sc);
 520
 521                 if (status & ATH9K_INT_FATAL) {
 522                         /* need a chip reset */
 523                         sched = true;
 524                 } else if (status & ATH9K_INT_RXORN) {
 525                         /* need a chip reset */
 526                         sched = true;
 527                 } else {
 528                         if (status & ATH9K_INT_SWBA) {
 529                                 /* schedule a tasklet for beacon handling */
 530                                 tasklet_schedule(&sc->bcon_tasklet);
 531                         }
 532                         if (status & ATH9K_INT_RXEOL) {
 533                                 /*
 534                                  * NB: the hardware should re-read the link when
 535                                  *     RXE bit is written, but it doesn't work
 536                                  *     at least on older hardware revs.
 537                                  */
 538                                 sched = true;
 539                         }
 540
 541                         if (status & ATH9K_INT_TXURN)
 542                                 /* bump tx trigger level */
 543                                 ath9k_hw_updatetxtriglevel(ah, true);
 544                         /* XXX: optimize this */
 545                         if (status & ATH9K_INT_RX)
 546                                 sched = true;
 547                         if (status & ATH9K_INT_TX)
 548                                 sched = true;
 549                         if (status & ATH9K_INT_BMISS)
 550                                 sched = true;
 551                         /* carrier sense timeout */
 552                         if (status & ATH9K_INT_CST)
 553                                 sched = true;
 554                         if (status & ATH9K_INT_MIB) {
 555                                 /*
 556                                  * Disable interrupts until we service the MIB
 557                                  * interrupt; otherwise it will continue to
 558                                  * fire.
 559                                  */
 560                                 ath9k_hw_set_interrupts(ah, 0);
 561                                 /*
 562                                  * Let the hal handle the event. We assume
 563                                  * it will clear whatever condition caused
 564                                  * the interrupt.
 565                                  */
 566                                 ath9k_hw_procmibevent(ah, &sc->nodestats);
 567                                 ath9k_hw_set_interrupts(ah, sc->imask);
 568                         }
 569                         if (status & ATH9K_INT_TIM_TIMER) {
 570                                 if (!(ah->caps.hw_caps &
 571                                       ATH9K_HW_CAP_AUTOSLEEP)) {
 572                                         /* Clear RxAbort bit so that we can
 573                                          * receive frames */
 574                                         ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
 575                                         ath9k_hw_setrxabort(ah, 0);
 576                                         sched = true;
 577                                         sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
 578                                 }
 579                         }
 580                         if (status & ATH9K_INT_TSFOOR) {
 581                                 /* FIXME: Handle this interrupt for power save */
 582                                 sched = true;
 583                         }
 584                 }
 585                 ath9k_ps_restore(sc);
 586         } while (0);
 587
 588         ath_debug_stat_interrupt(sc, status);
 589
 590         if (sched) {
 591                 /* turn off every interrupt except SWBA */
 592                 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
 593                 tasklet_schedule(&sc->intr_tq);
 594         }
 595
 596         return IRQ_HANDLED;
 597 }
 598
 599 static u32 ath_get_extchanmode(struct ath_softc *sc,
 600                                struct ieee80211_channel *chan,
 601                                enum nl80211_channel_type channel_type)
 602 {
 603         u32 chanmode = 0;
 604
 605         switch (chan->band) {
 606         case IEEE80211_BAND_2GHZ:
 607                 switch(channel_type) {
 608                 case NL80211_CHAN_NO_HT:
 609                 case NL80211_CHAN_HT20:
 610                         chanmode = CHANNEL_G_HT20;
 611                         break;
 612                 case NL80211_CHAN_HT40PLUS:
 613                         chanmode = CHANNEL_G_HT40PLUS;
 614                         break;
 615                 case NL80211_CHAN_HT40MINUS:
 616                         chanmode = CHANNEL_G_HT40MINUS;
 617                         break;
 618                 }
 619                 break;
 620         case IEEE80211_BAND_5GHZ:
 621                 switch(channel_type) {
 622                 case NL80211_CHAN_NO_HT:
 623                 case NL80211_CHAN_HT20:
 624                         chanmode = CHANNEL_A_HT20;
 625                         break;
 626                 case NL80211_CHAN_HT40PLUS:
 627                         chanmode = CHANNEL_A_HT40PLUS;
 628                         break;
 629                 case NL80211_CHAN_HT40MINUS:
 630                         chanmode = CHANNEL_A_HT40MINUS;
 631                         break;
 632                 }
 633                 break;
 634         default:
 635                 break;
 636         }
 637
 638         return chanmode;
 639 }
 640
 641 static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
 642                            struct ath9k_keyval *hk, const u8 *addr,
 643                            bool authenticator)
 644 {
 645         const u8 *key_rxmic;
 646         const u8 *key_txmic;
 647
 648         key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
 649         key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
 650
 651         if (addr == NULL) {
 652                 /*
 653                  * Group key installation - only two key cache entries are used
 654                  * regardless of splitmic capability since group key is only
 655                  * used either for TX or RX.
 656                  */
 657                 if (authenticator) {
 658                         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
 659                         memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
 660                 } else {
 661                         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 662                         memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
 663                 }
 664                 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
 665         }
 666         if (!sc->splitmic) {
 667                 /* TX and RX keys share the same key cache entry. */
 668                 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 669                 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
 670                 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
 671         }
 672
 673         /* Separate key cache entries for TX and RX */
 674
 675         /* TX key goes at first index, RX key at +32. */
 676         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
 677         if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
 678                 /* TX MIC entry failed. No need to proceed further */
 679                 DPRINTF(sc, ATH_DBG_KEYCACHE,
 680                         "Setting TX MIC Key Failed\n");
 681                 return 0;
 682         }
 683
 684         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 685         /* XXX delete tx key on failure? */
 686         return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
 687 }
 688
 689 static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
 690 {
 691         int i;
 692
 693         for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
 694                 if (test_bit(i, sc->keymap) ||
 695                     test_bit(i + 64, sc->keymap))
 696                         continue; /* At least one part of TKIP key allocated */
 697                 if (sc->splitmic &&
 698                     (test_bit(i + 32, sc->keymap) ||
 699                      test_bit(i + 64 + 32, sc->keymap)))
 700                         continue; /* At least one part of TKIP key allocated */
 701
 702                 /* Found a free slot for a TKIP key */
 703                 return i;
 704         }
 705         return -1;
 706 }
 707
 708 static int ath_reserve_key_cache_slot(struct ath_softc *sc)
 709 {
 710         int i;
 711
 712         /* First, try to find slots that would not be available for TKIP. */
 713         if (sc->splitmic) {
 714                 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
 715                         if (!test_bit(i, sc->keymap) &&
 716                             (test_bit(i + 32, sc->keymap) ||
 717                              test_bit(i + 64, sc->keymap) ||
 718                              test_bit(i + 64 + 32, sc->keymap)))
 719                                 return i;
 720                         if (!test_bit(i + 32, sc->keymap) &&
 721                             (test_bit(i, sc->keymap) ||
 722                              test_bit(i + 64, sc->keymap) ||
 723                              test_bit(i + 64 + 32, sc->keymap)))
 724                                 return i + 32;
 725                         if (!test_bit(i + 64, sc->keymap) &&
 726                             (test_bit(i , sc->keymap) ||
 727                              test_bit(i + 32, sc->keymap) ||
 728                              test_bit(i + 64 + 32, sc->keymap)))
 729                                 return i + 64;
 730                         if (!test_bit(i + 64 + 32, sc->keymap) &&
 731                             (test_bit(i, sc->keymap) ||
 732                              test_bit(i + 32, sc->keymap) ||
 733                              test_bit(i + 64, sc->keymap)))
 734                                 return i + 64 + 32;
 735                 }
 736         } else {
 737                 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
 738                         if (!test_bit(i, sc->keymap) &&
 739                             test_bit(i + 64, sc->keymap))
 740                                 return i;
 741                         if (test_bit(i, sc->keymap) &&
 742                             !test_bit(i + 64, sc->keymap))
 743                                 return i + 64;
 744                 }
 745         }
 746
 747         /* No partially used TKIP slots, pick any available slot */
 748         for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
 749                 /* Do not allow slots that could be needed for TKIP group keys
 750                  * to be used. This limitation could be removed if we know that
 751                  * TKIP will not be used. */
 752                 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
 753                         continue;
 754                 if (sc->splitmic) {
 755                         if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
 756                                 continue;
 757                         if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
 758                                 continue;
 759                 }
 760
 761                 if (!test_bit(i, sc->keymap))
 762                         return i; /* Found a free slot for a key */
 763         }
 764
 765         /* No free slot found */
 766         return -1;
 767 }
 768
 769 static int ath_key_config(struct ath_softc *sc,
 770                           struct ieee80211_vif *vif,
 771                           struct ieee80211_sta *sta,
 772                           struct ieee80211_key_conf *key)
 773 {
 774         struct ath9k_keyval hk;
 775         const u8 *mac = NULL;
 776         int ret = 0;
 777         int idx;
 778
 779         memset(&hk, 0, sizeof(hk));
 780
 781         switch (key->alg) {
 782         case ALG_WEP:
 783                 hk.kv_type = ATH9K_CIPHER_WEP;
 784                 break;
 785         case ALG_TKIP:
 786                 hk.kv_type = ATH9K_CIPHER_TKIP;
 787                 break;
 788         case ALG_CCMP:
 789                 hk.kv_type = ATH9K_CIPHER_AES_CCM;
 790                 break;
 791         default:
 792                 return -EOPNOTSUPP;
 793         }
 794
 795         hk.kv_len = key->keylen;
 796         memcpy(hk.kv_val, key->key, key->keylen);
 797
 798         if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
 799                 /* For now, use the default keys for broadcast keys. This may
 800                  * need to change with virtual interfaces. */
 801                 idx = key->keyidx;
 802         } else if (key->keyidx) {
 803                 if (WARN_ON(!sta))
 804                         return -EOPNOTSUPP;
 805                 mac = sta->addr;
 806
 807                 if (vif->type != NL80211_IFTYPE_AP) {
 808                         /* Only keyidx 0 should be used with unicast key, but
 809                          * allow this for client mode for now. */
 810                         idx = key->keyidx;
 811                 } else
 812                         return -EIO;
 813         } else {
 814                 if (WARN_ON(!sta))
 815                         return -EOPNOTSUPP;
 816                 mac = sta->addr;
 817
 818                 if (key->alg == ALG_TKIP)
 819                         idx = ath_reserve_key_cache_slot_tkip(sc);
 820                 else
 821                         idx = ath_reserve_key_cache_slot(sc);
 822                 if (idx < 0)
 823                         return -ENOSPC; /* no free key cache entries */
 824         }
 825
 826         if (key->alg == ALG_TKIP)
 827                 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
 828                                       vif->type == NL80211_IFTYPE_AP);
 829         else
 830                 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
 831
 832         if (!ret)
 833                 return -EIO;
 834
 835         set_bit(idx, sc->keymap);
 836         if (key->alg == ALG_TKIP) {
 837                 set_bit(idx + 64, sc->keymap);
 838                 if (sc->splitmic) {
 839                         set_bit(idx + 32, sc->keymap);
 840                         set_bit(idx + 64 + 32, sc->keymap);
 841                 }
 842         }
 843
 844         return idx;
 845 }
 846
 847 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
 848 {
 849         ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
 850         if (key->hw_key_idx < IEEE80211_WEP_NKID)
 851                 return;
 852
 853         clear_bit(key->hw_key_idx, sc->keymap);
 854         if (key->alg != ALG_TKIP)
 855                 return;
 856
 857         clear_bit(key->hw_key_idx + 64, sc->keymap);
 858         if (sc->splitmic) {
 859                 clear_bit(key->hw_key_idx + 32, sc->keymap);
 860                 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
 861         }
 862 }
 863
 864 static void setup_ht_cap(struct ath_softc *sc,
 865                          struct ieee80211_sta_ht_cap *ht_info)
 866 {
 867 #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3       /* 2 ^ 16 */
 868 #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6          /* 8 usec */
 869
 870         ht_info->ht_supported = true;
 871         ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
 872                        IEEE80211_HT_CAP_SM_PS |
 873                        IEEE80211_HT_CAP_SGI_40 |
 874                        IEEE80211_HT_CAP_DSSSCCK40;
 875
 876         ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
 877         ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
 878
 879         /* set up supported mcs set */
 880         memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
 881
 882         switch(sc->rx_chainmask) {
 883         case 1:
 884                 ht_info->mcs.rx_mask[0] = 0xff;
 885                 break;
 886         case 3:
 887         case 5:
 888         case 7:
 889         default:
 890                 ht_info->mcs.rx_mask[0] = 0xff;
 891                 ht_info->mcs.rx_mask[1] = 0xff;
 892                 break;
 893         }
 894
 895         ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
 896 }
 897
 898 static void ath9k_bss_assoc_info(struct ath_softc *sc,
 899                                  struct ieee80211_vif *vif,
 900                                  struct ieee80211_bss_conf *bss_conf)
 901 {
 902         struct ath_vif *avp = (void *)vif->drv_priv;
 903
 904         if (bss_conf->assoc) {
 905                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
 906                         bss_conf->aid, sc->curbssid);
 907
 908                 /* New association, store aid */
 909                 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
 910                         sc->curaid = bss_conf->aid;
 911                         ath9k_hw_write_associd(sc);
 912                 }
 913
 914                 /* Configure the beacon */
 915                 ath_beacon_config(sc, vif);
 916
 917                 /* Reset rssi stats */
 918                 sc->nodestats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
 919                 sc->nodestats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
 920                 sc->nodestats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
 921                 sc->nodestats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
 922
 923                 /* Start ANI */
 924                 mod_timer(&sc->ani.timer,
 925                           jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
 926         } else {
 927                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n");
 928                 sc->curaid = 0;
 929         }
 930 }
 931
 932 /********************************/
 933 /*       LED functions          */
 934 /********************************/
 935
 936 static void ath_led_blink_work(struct work_struct *work)
 937 {
 938         struct ath_softc *sc = container_of(work, struct ath_softc,
 939                                             ath_led_blink_work.work);
 940
 941         if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
 942                 return;
 943         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
 944                           (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
 945
 946         queue_delayed_work(sc->hw->workqueue, &sc->ath_led_blink_work,
 947                            (sc->sc_flags & SC_OP_LED_ON) ?
 948                            msecs_to_jiffies(sc->led_off_duration) :
 949                            msecs_to_jiffies(sc->led_on_duration));
 950
 951         sc->led_on_duration =
 952                         max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25);
 953         sc->led_off_duration =
 954                         max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10);
 955         sc->led_on_cnt = sc->led_off_cnt = 0;
 956         if (sc->sc_flags & SC_OP_LED_ON)
 957                 sc->sc_flags &= ~SC_OP_LED_ON;
 958         else
 959                 sc->sc_flags |= SC_OP_LED_ON;
 960 }
 961
 962 static void ath_led_brightness(struct led_classdev *led_cdev,
 963                                enum led_brightness brightness)
 964 {
 965         struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
 966         struct ath_softc *sc = led->sc;
 967
 968         switch (brightness) {
 969         case LED_OFF:
 970                 if (led->led_type == ATH_LED_ASSOC ||
 971                     led->led_type == ATH_LED_RADIO) {
 972                         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
 973                                 (led->led_type == ATH_LED_RADIO));
 974                         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
 975                         if (led->led_type == ATH_LED_RADIO)
 976                                 sc->sc_flags &= ~SC_OP_LED_ON;
 977                 } else {
 978                         sc->led_off_cnt++;
 979                 }
 980                 break;
 981         case LED_FULL:
 982                 if (led->led_type == ATH_LED_ASSOC) {
 983                         sc->sc_flags |= SC_OP_LED_ASSOCIATED;
 984                         queue_delayed_work(sc->hw->workqueue,
 985                                            &sc->ath_led_blink_work, 0);
 986                 } else if (led->led_type == ATH_LED_RADIO) {
 987                         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
 988                         sc->sc_flags |= SC_OP_LED_ON;
 989                 } else {
 990                         sc->led_on_cnt++;
 991                 }
 992                 break;
 993         default:
 994                 break;
 995         }
 996 }
 997
 998 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
 999                             char *trigger)
1000 {
1001         int ret;
1002
1003         led->sc = sc;
1004         led->led_cdev.name = led->name;
1005         led->led_cdev.default_trigger = trigger;
1006         led->led_cdev.brightness_set = ath_led_brightness;
1007
1008         ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1009         if (ret)
1010                 DPRINTF(sc, ATH_DBG_FATAL,
1011                         "Failed to register led:%s", led->name);
1012         else
1013                 led->registered = 1;
1014         return ret;
1015 }
1016
1017 static void ath_unregister_led(struct ath_led *led)
1018 {
1019         if (led->registered) {
1020                 led_classdev_unregister(&led->led_cdev);
1021                 led->registered = 0;
1022         }
1023 }
1024
1025 static void ath_deinit_leds(struct ath_softc *sc)
1026 {
1027         cancel_delayed_work_sync(&sc->ath_led_blink_work);
1028         ath_unregister_led(&sc->assoc_led);
1029         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1030         ath_unregister_led(&sc->tx_led);
1031         ath_unregister_led(&sc->rx_led);
1032         ath_unregister_led(&sc->radio_led);
1033         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1034 }
1035
1036 static void ath_init_leds(struct ath_softc *sc)
1037 {
1038         char *trigger;
1039         int ret;
1040
1041         /* Configure gpio 1 for output */
1042         ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1043                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1044         /* LED off, active low */
1045         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1046
1047         INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1048
1049         trigger = ieee80211_get_radio_led_name(sc->hw);
1050         snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1051                 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
1052         ret = ath_register_led(sc, &sc->radio_led, trigger);
1053         sc->radio_led.led_type = ATH_LED_RADIO;
1054         if (ret)
1055                 goto fail;
1056
1057         trigger = ieee80211_get_assoc_led_name(sc->hw);
1058         snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1059                 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
1060         ret = ath_register_led(sc, &sc->assoc_led, trigger);
1061         sc->assoc_led.led_type = ATH_LED_ASSOC;
1062         if (ret)
1063                 goto fail;
1064
1065         trigger = ieee80211_get_tx_led_name(sc->hw);
1066         snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1067                 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
1068         ret = ath_register_led(sc, &sc->tx_led, trigger);
1069         sc->tx_led.led_type = ATH_LED_TX;
1070         if (ret)
1071                 goto fail;
1072
1073         trigger = ieee80211_get_rx_led_name(sc->hw);
1074         snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1075                 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
1076         ret = ath_register_led(sc, &sc->rx_led, trigger);
1077         sc->rx_led.led_type = ATH_LED_RX;
1078         if (ret)
1079                 goto fail;
1080
1081         return;
1082
1083 fail:
1084         ath_deinit_leds(sc);
1085 }
1086
1087 void ath_radio_enable(struct ath_softc *sc)
1088 {
1089         struct ath_hw *ah = sc->sc_ah;
1090         struct ieee80211_channel *channel = sc->hw->conf.channel;
1091         int r;
1092
1093         ath9k_ps_wakeup(sc);
1094         spin_lock_bh(&sc->sc_resetlock);
1095
1096         r = ath9k_hw_reset(ah, ah->curchan, false);
1097
1098         if (r) {
1099                 DPRINTF(sc, ATH_DBG_FATAL,
1100                         "Unable to reset channel %u (%uMhz) ",
1101                         "reset status %u\n",
1102                         channel->center_freq, r);
1103         }
1104         spin_unlock_bh(&sc->sc_resetlock);
1105
1106         ath_update_txpow(sc);
1107         if (ath_startrecv(sc) != 0) {
1108                 DPRINTF(sc, ATH_DBG_FATAL,
1109                         "Unable to restart recv logic\n");
1110                 return;
1111         }
1112
1113         if (sc->sc_flags & SC_OP_BEACONS)
1114                 ath_beacon_config(sc, NULL);    /* restart beacons */
1115
1116         /* Re-Enable  interrupts */
1117         ath9k_hw_set_interrupts(ah, sc->imask);
1118
1119         /* Enable LED */
1120         ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1121                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1122         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1123
1124         ieee80211_wake_queues(sc->hw);
1125         ath9k_ps_restore(sc);
1126 }
1127
1128 void ath_radio_disable(struct ath_softc *sc)
1129 {
1130         struct ath_hw *ah = sc->sc_ah;
1131         struct ieee80211_channel *channel = sc->hw->conf.channel;
1132         int r;
1133
1134         ath9k_ps_wakeup(sc);
1135         ieee80211_stop_queues(sc->hw);
1136
1137         /* Disable LED */
1138         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1139         ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1140
1141         /* Disable interrupts */
1142         ath9k_hw_set_interrupts(ah, 0);
1143
1144         ath_drain_all_txq(sc, false);   /* clear pending tx frames */
1145         ath_stoprecv(sc);               /* turn off frame recv */
1146         ath_flushrecv(sc);              /* flush recv queue */
1147
1148         spin_lock_bh(&sc->sc_resetlock);
1149         r = ath9k_hw_reset(ah, ah->curchan, false);
1150         if (r) {
1151                 DPRINTF(sc, ATH_DBG_FATAL,
1152                         "Unable to reset channel %u (%uMhz) "
1153                         "reset status %u\n",
1154                         channel->center_freq, r);
1155         }
1156         spin_unlock_bh(&sc->sc_resetlock);
1157
1158         ath9k_hw_phy_disable(ah);
1159         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1160         ath9k_ps_restore(sc);
1161 }
1162
1163 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1164
1165 /*******************/
1166 /*      Rfkill     */
1167 /*******************/
1168
1169 static bool ath_is_rfkill_set(struct ath_softc *sc)
1170 {
1171         struct ath_hw *ah = sc->sc_ah;
1172
1173         return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1174                                   ah->rfkill_polarity;
1175 }
1176
1177 /* h/w rfkill poll function */
1178 static void ath_rfkill_poll(struct work_struct *work)
1179 {
1180         struct ath_softc *sc = container_of(work, struct ath_softc,
1181                                             rf_kill.rfkill_poll.work);
1182         bool radio_on;
1183
1184         if (sc->sc_flags & SC_OP_INVALID)
1185                 return;
1186
1187         radio_on = !ath_is_rfkill_set(sc);
1188
1189         /*
1190          * enable/disable radio only when there is a
1191          * state change in RF switch
1192          */
1193         if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1194                 enum rfkill_state state;
1195
1196                 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1197                         state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1198                                 : RFKILL_STATE_HARD_BLOCKED;
1199                 } else if (radio_on) {
1200                         ath_radio_enable(sc);
1201                         state = RFKILL_STATE_UNBLOCKED;
1202                 } else {
1203                         ath_radio_disable(sc);
1204                         state = RFKILL_STATE_HARD_BLOCKED;
1205                 }
1206
1207                 if (state == RFKILL_STATE_HARD_BLOCKED)
1208                         sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1209                 else
1210                         sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1211
1212                 rfkill_force_state(sc->rf_kill.rfkill, state);
1213         }
1214
1215         queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1216                            msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1217 }
1218
1219 /* s/w rfkill handler */
1220 static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1221 {
1222         struct ath_softc *sc = data;
1223
1224         switch (state) {
1225         case RFKILL_STATE_SOFT_BLOCKED:
1226                 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1227                     SC_OP_RFKILL_SW_BLOCKED)))
1228                         ath_radio_disable(sc);
1229                 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1230                 return 0;
1231         case RFKILL_STATE_UNBLOCKED:
1232                 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1233                         sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1234                         if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1235                                 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
1236                                         "radio as it is disabled by h/w\n");
1237                                 return -EPERM;
1238                         }
1239                         ath_radio_enable(sc);
1240                 }
1241                 return 0;
1242         default:
1243                 return -EINVAL;
1244         }
1245 }
1246
1247 /* Init s/w rfkill */
1248 static int ath_init_sw_rfkill(struct ath_softc *sc)
1249 {
1250         sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1251                                              RFKILL_TYPE_WLAN);
1252         if (!sc->rf_kill.rfkill) {
1253                 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1254                 return -ENOMEM;
1255         }
1256
1257         snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1258                 "ath9k-%s::rfkill", wiphy_name(sc->hw->wiphy));
1259         sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1260         sc->rf_kill.rfkill->data = sc;
1261         sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1262         sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1263         sc->rf_kill.rfkill->user_claim_unsupported = 1;
1264
1265         return 0;
1266 }
1267
1268 /* Deinitialize rfkill */
1269 static void ath_deinit_rfkill(struct ath_softc *sc)
1270 {
1271         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1272                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1273
1274         if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1275                 rfkill_unregister(sc->rf_kill.rfkill);
1276                 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1277                 sc->rf_kill.rfkill = NULL;
1278         }
1279 }
1280
1281 static int ath_start_rfkill_poll(struct ath_softc *sc)
1282 {
1283         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1284                 queue_delayed_work(sc->hw->workqueue,
1285                                    &sc->rf_kill.rfkill_poll, 0);
1286
1287         if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1288                 if (rfkill_register(sc->rf_kill.rfkill)) {
1289                         DPRINTF(sc, ATH_DBG_FATAL,
1290                                 "Unable to register rfkill\n");
1291                         rfkill_free(sc->rf_kill.rfkill);
1292
1293                         /* Deinitialize the device */
1294                         ath_cleanup(sc);
1295                         return -EIO;
1296                 } else {
1297                         sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1298                 }
1299         }
1300
1301         return 0;
1302 }
1303 #endif /* CONFIG_RFKILL */
1304
1305 void ath_cleanup(struct ath_softc *sc)
1306 {
1307         ath_detach(sc);
1308         free_irq(sc->irq, sc);
1309         ath_bus_cleanup(sc);
1310         kfree(sc->sec_wiphy);
1311         ieee80211_free_hw(sc->hw);
1312 }
1313
1314 void ath_detach(struct ath_softc *sc)
1315 {
1316         struct ieee80211_hw *hw = sc->hw;
1317         int i = 0;
1318
1319         ath9k_ps_wakeup(sc);
1320
1321         DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
1322
1323 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1324         ath_deinit_rfkill(sc);
1325 #endif
1326         ath_deinit_leds(sc);
1327         cancel_work_sync(&sc->chan_work);
1328         cancel_delayed_work_sync(&sc->wiphy_work);
1329
1330         for (i = 0; i < sc->num_sec_wiphy; i++) {
1331                 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1332                 if (aphy == NULL)
1333                         continue;
1334                 sc->sec_wiphy[i] = NULL;
1335                 ieee80211_unregister_hw(aphy->hw);
1336                 ieee80211_free_hw(aphy->hw);
1337         }
1338         ieee80211_unregister_hw(hw);
1339         ath_rx_cleanup(sc);
1340         ath_tx_cleanup(sc);
1341
1342         tasklet_kill(&sc->intr_tq);
1343         tasklet_kill(&sc->bcon_tasklet);
1344
1345         if (!(sc->sc_flags & SC_OP_INVALID))
1346                 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1347
1348         /* cleanup tx queues */
1349         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1350                 if (ATH_TXQ_SETUP(sc, i))
1351                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1352
1353         ath9k_hw_detach(sc->sc_ah);
1354         ath9k_exit_debug(sc);
1355         ath9k_ps_restore(sc);
1356 }
1357
1358 static int ath_init(u16 devid, struct ath_softc *sc)
1359 {
1360         struct ath_hw *ah = NULL;
1361         int status;
1362         int error = 0, i;
1363         int csz = 0;
1364
1365         /* XXX: hardware will not be ready until ath_open() being called */
1366         sc->sc_flags |= SC_OP_INVALID;
1367
1368         if (ath9k_init_debug(sc) < 0)
1369                 printk(KERN_ERR "Unable to create debugfs files\n");
1370
1371         spin_lock_init(&sc->wiphy_lock);
1372         spin_lock_init(&sc->sc_resetlock);
1373         mutex_init(&sc->mutex);
1374         tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1375         tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
1376                      (unsigned long)sc);
1377
1378         /*
1379          * Cache line size is used to size and align various
1380          * structures used to communicate with the hardware.
1381          */
1382         ath_read_cachesize(sc, &csz);
1383         /* XXX assert csz is non-zero */
1384         sc->cachelsz = csz << 2;        /* convert to bytes */
1385
1386         ah = ath9k_hw_attach(devid, sc, &status);
1387         if (ah == NULL) {
1388                 DPRINTF(sc, ATH_DBG_FATAL,
1389                         "Unable to attach hardware; HAL status %d\n", status);
1390                 error = -ENXIO;
1391                 goto bad;
1392         }
1393         sc->sc_ah = ah;
1394
1395         /* Get the hardware key cache size. */
1396         sc->keymax = ah->caps.keycache_size;
1397         if (sc->keymax > ATH_KEYMAX) {
1398                 DPRINTF(sc, ATH_DBG_KEYCACHE,
1399                         "Warning, using only %u entries in %u key cache\n",
1400                         ATH_KEYMAX, sc->keymax);
1401                 sc->keymax = ATH_KEYMAX;
1402         }
1403
1404         /*
1405          * Reset the key cache since some parts do not
1406          * reset the contents on initial power up.
1407          */
1408         for (i = 0; i < sc->keymax; i++)
1409                 ath9k_hw_keyreset(ah, (u16) i);
1410
1411         if (ath9k_regd_init(sc->sc_ah))
1412                 goto bad;
1413
1414         /* default to MONITOR mode */
1415         sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1416
1417         /* Setup rate tables */
1418
1419         ath_rate_attach(sc);
1420         ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1421         ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1422
1423         /*
1424          * Allocate hardware transmit queues: one queue for
1425          * beacon frames and one data queue for each QoS
1426          * priority.  Note that the hal handles reseting
1427          * these queues at the needed time.
1428          */
1429         sc->beacon.beaconq = ath_beaconq_setup(ah);
1430         if (sc->beacon.beaconq == -1) {
1431                 DPRINTF(sc, ATH_DBG_FATAL,
1432                         "Unable to setup a beacon xmit queue\n");
1433                 error = -EIO;
1434                 goto bad2;
1435         }
1436         sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1437         if (sc->beacon.cabq == NULL) {
1438                 DPRINTF(sc, ATH_DBG_FATAL,
1439                         "Unable to setup CAB xmit queue\n");
1440                 error = -EIO;
1441                 goto bad2;
1442         }
1443
1444         sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
1445         ath_cabq_update(sc);
1446
1447         for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1448                 sc->tx.hwq_map[i] = -1;
1449
1450         /* Setup data queues */
1451         /* NB: ensure BK queue is the lowest priority h/w queue */
1452         if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1453                 DPRINTF(sc, ATH_DBG_FATAL,
1454                         "Unable to setup xmit queue for BK traffic\n");
1455                 error = -EIO;
1456                 goto bad2;
1457         }
1458
1459         if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1460                 DPRINTF(sc, ATH_DBG_FATAL,
1461                         "Unable to setup xmit queue for BE traffic\n");
1462                 error = -EIO;
1463                 goto bad2;
1464         }
1465         if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1466                 DPRINTF(sc, ATH_DBG_FATAL,
1467                         "Unable to setup xmit queue for VI traffic\n");
1468                 error = -EIO;
1469                 goto bad2;
1470         }
1471         if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1472                 DPRINTF(sc, ATH_DBG_FATAL,
1473                         "Unable to setup xmit queue for VO traffic\n");
1474                 error = -EIO;
1475                 goto bad2;
1476         }
1477
1478         /* Initializes the noise floor to a reasonable default value.
1479          * Later on this will be updated during ANI processing. */
1480
1481         sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1482         setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
1483
1484         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1485                                    ATH9K_CIPHER_TKIP, NULL)) {
1486                 /*
1487                  * Whether we should enable h/w TKIP MIC.
1488                  * XXX: if we don't support WME TKIP MIC, then we wouldn't
1489                  * report WMM capable, so it's always safe to turn on
1490                  * TKIP MIC in this case.
1491                  */
1492                 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1493                                        0, 1, NULL);
1494         }
1495
1496         /*
1497          * Check whether the separate key cache entries
1498          * are required to handle both tx+rx MIC keys.
1499          * With split mic keys the number of stations is limited
1500          * to 27 otherwise 59.
1501          */
1502         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1503                                    ATH9K_CIPHER_TKIP, NULL)
1504             && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1505                                       ATH9K_CIPHER_MIC, NULL)
1506             && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1507                                       0, NULL))
1508                 sc->splitmic = 1;
1509
1510         /* turn on mcast key search if possible */
1511         if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1512                 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1513                                              1, NULL);
1514
1515         sc->config.txpowlimit = ATH_TXPOWER_MAX;
1516
1517         /* 11n Capabilities */
1518         if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1519                 sc->sc_flags |= SC_OP_TXAGGR;
1520                 sc->sc_flags |= SC_OP_RXAGGR;
1521         }
1522
1523         sc->tx_chainmask = ah->caps.tx_chainmask;
1524         sc->rx_chainmask = ah->caps.rx_chainmask;
1525
1526         ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1527         sc->rx.defant = ath9k_hw_getdefantenna(ah);
1528
1529         if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
1530                 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
1531
1532         sc->beacon.slottime = ATH9K_SLOT_TIME_9;        /* default to short slot time */
1533
1534         /* initialize beacon slots */
1535         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
1536                 sc->beacon.bslot[i] = NULL;
1537                 sc->beacon.bslot_aphy[i] = NULL;
1538         }
1539
1540         /* save MISC configurations */
1541         sc->config.swBeaconProcess = 1;
1542
1543         /* setup channels and rates */
1544
1545         sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
1546         sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1547                 sc->rates[IEEE80211_BAND_2GHZ];
1548         sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1549         sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1550                 ARRAY_SIZE(ath9k_2ghz_chantable);
1551
1552         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
1553                 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
1554                 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1555                         sc->rates[IEEE80211_BAND_5GHZ];
1556                 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1557                 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1558                         ARRAY_SIZE(ath9k_5ghz_chantable);
1559         }
1560
1561         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
1562                 ath9k_hw_btcoex_enable(sc->sc_ah);
1563
1564         return 0;
1565 bad2:
1566         /* cleanup tx queues */
1567         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1568                 if (ATH_TXQ_SETUP(sc, i))
1569                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1570 bad:
1571         if (ah)
1572                 ath9k_hw_detach(ah);
1573         ath9k_exit_debug(sc);
1574
1575         return error;
1576 }
1577
1578 void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
1579 {
1580         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1581                 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1582                 IEEE80211_HW_SIGNAL_DBM |
1583                 IEEE80211_HW_AMPDU_AGGREGATION |
1584                 IEEE80211_HW_SUPPORTS_PS |
1585                 IEEE80211_HW_PS_NULLFUNC_STACK;
1586
1587         if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
1588                 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1589
1590         hw->wiphy->interface_modes =
1591                 BIT(NL80211_IFTYPE_AP) |
1592                 BIT(NL80211_IFTYPE_STATION) |
1593                 BIT(NL80211_IFTYPE_ADHOC);
1594
1595         hw->wiphy->reg_notifier = ath9k_reg_notifier;
1596         hw->wiphy->strict_regulatory = true;
1597
1598         hw->queues = 4;
1599         hw->max_rates = 4;
1600         hw->channel_change_time = 5000;
1601         hw->max_listen_interval = 10;
1602         hw->max_rate_tries = ATH_11N_TXMAXTRY;
1603         hw->sta_data_size = sizeof(struct ath_node);
1604         hw->vif_data_size = sizeof(struct ath_vif);
1605
1606         hw->rate_control_algorithm = "ath9k_rate_control";
1607
1608         hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1609                 &sc->sbands[IEEE80211_BAND_2GHZ];
1610         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1611                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1612                         &sc->sbands[IEEE80211_BAND_5GHZ];
1613 }
1614
1615 int ath_attach(u16 devid, struct ath_softc *sc)
1616 {
1617         struct ieee80211_hw *hw = sc->hw;
1618         const struct ieee80211_regdomain *regd;
1619         int error = 0, i;
1620
1621         DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1622
1623         error = ath_init(devid, sc);
1624         if (error != 0)
1625                 return error;
1626
1627         /* get mac address from hardware and set in mac80211 */
1628
1629         SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);
1630
1631         ath_set_hw_capab(sc, hw);
1632
1633         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1634                 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1635                 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1636                         setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1637         }
1638
1639         /* initialize tx/rx engine */
1640         error = ath_tx_init(sc, ATH_TXBUF);
1641         if (error != 0)
1642                 goto error_attach;
1643
1644         error = ath_rx_init(sc, ATH_RXBUF);
1645         if (error != 0)
1646                 goto error_attach;
1647
1648 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1649         /* Initialze h/w Rfkill */
1650         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1651                 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1652
1653         /* Initialize s/w rfkill */
1654         error = ath_init_sw_rfkill(sc);
1655         if (error)
1656                 goto error_attach;
1657 #endif
1658
1659         if (ath9k_is_world_regd(sc->sc_ah)) {
1660                 /* Anything applied here (prior to wiphy registration) gets
1661                  * saved on the wiphy orig_* parameters */
1662                 regd = ath9k_world_regdomain(sc->sc_ah);
1663                 hw->wiphy->custom_regulatory = true;
1664                 hw->wiphy->strict_regulatory = false;
1665         } else {
1666                 /* This gets applied in the case of the absense of CRDA,
1667                  * it's our own custom world regulatory domain, similar to
1668                  * cfg80211's but we enable passive scanning */
1669                 regd = ath9k_default_world_regdomain();
1670         }
1671         wiphy_apply_custom_regulatory(hw->wiphy, regd);
1672         ath9k_reg_apply_radar_flags(hw->wiphy);
1673         ath9k_reg_apply_world_flags(hw->wiphy, REGDOM_SET_BY_INIT);
1674
1675         INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
1676         INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1677         sc->wiphy_scheduler_int = msecs_to_jiffies(500);
1678
1679         error = ieee80211_register_hw(hw);
1680
1681         if (!ath9k_is_world_regd(sc->sc_ah)) {
1682                 error = regulatory_hint(hw->wiphy,
1683                         sc->sc_ah->regulatory.alpha2);
1684                 if (error)
1685                         goto error_attach;
1686         }
1687
1688         /* Initialize LED control */
1689         ath_init_leds(sc);
1690
1691
1692         return 0;
1693
1694 error_attach:
1695         /* cleanup tx queues */
1696         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1697                 if (ATH_TXQ_SETUP(sc, i))
1698                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1699
1700         ath9k_hw_detach(sc->sc_ah);
1701         ath9k_exit_debug(sc);
1702
1703         return error;
1704 }
1705
1706 int ath_reset(struct ath_softc *sc, bool retry_tx)
1707 {
1708         struct ath_hw *ah = sc->sc_ah;
1709         struct ieee80211_hw *hw = sc->hw;
1710         int r;
1711
1712         ath9k_hw_set_interrupts(ah, 0);
1713         ath_drain_all_txq(sc, retry_tx);
1714         ath_stoprecv(sc);
1715         ath_flushrecv(sc);
1716
1717         spin_lock_bh(&sc->sc_resetlock);
1718         r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1719         if (r)
1720                 DPRINTF(sc, ATH_DBG_FATAL,
1721                         "Unable to reset hardware; reset status %u\n", r);
1722         spin_unlock_bh(&sc->sc_resetlock);
1723
1724         if (ath_startrecv(sc) != 0)
1725                 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1726
1727         /*
1728          * We may be doing a reset in response to a request
1729          * that changes the channel so update any state that
1730          * might change as a result.
1731          */
1732         ath_cache_conf_rate(sc, &hw->conf);
1733
1734         ath_update_txpow(sc);
1735
1736         if (sc->sc_flags & SC_OP_BEACONS)
1737                 ath_beacon_config(sc, NULL);    /* restart beacons */
1738
1739         ath9k_hw_set_interrupts(ah, sc->imask);
1740
1741         if (retry_tx) {
1742                 int i;
1743                 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1744                         if (ATH_TXQ_SETUP(sc, i)) {
1745                                 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1746                                 ath_txq_schedule(sc, &sc->tx.txq[i]);
1747                                 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1748                         }
1749                 }
1750         }
1751
1752         return r;
1753 }
1754
1755 /*
1756  *  This function will allocate both the DMA descriptor structure, and the
1757  *  buffers it contains.  These are used to contain the descriptors used
1758  *  by the system.
1759 */
1760 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1761                       struct list_head *head, const char *name,
1762                       int nbuf, int ndesc)
1763 {
1764 #define DS2PHYS(_dd, _ds)                                               \
1765         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1766 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1767 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1768
1769         struct ath_desc *ds;
1770         struct ath_buf *bf;
1771         int i, bsize, error;
1772
1773         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1774                 name, nbuf, ndesc);
1775
1776         INIT_LIST_HEAD(head);
1777         /* ath_desc must be a multiple of DWORDs */
1778         if ((sizeof(struct ath_desc) % 4) != 0) {
1779                 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1780                 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1781                 error = -ENOMEM;
1782                 goto fail;
1783         }
1784
1785         dd->dd_name = name;
1786         dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1787
1788         /*
1789          * Need additional DMA memory because we can't use
1790          * descriptors that cross the 4K page boundary. Assume
1791          * one skipped descriptor per 4K page.
1792          */
1793         if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1794                 u32 ndesc_skipped =
1795                         ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1796                 u32 dma_len;
1797
1798                 while (ndesc_skipped) {
1799                         dma_len = ndesc_skipped * sizeof(struct ath_desc);
1800                         dd->dd_desc_len += dma_len;
1801
1802                         ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1803                 };
1804         }
1805
1806         /* allocate descriptors */
1807         dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
1808                                          &dd->dd_desc_paddr, GFP_KERNEL);
1809         if (dd->dd_desc == NULL) {
1810                 error = -ENOMEM;
1811                 goto fail;
1812         }
1813         ds = dd->dd_desc;
1814         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1815                 dd->dd_name, ds, (u32) dd->dd_desc_len,
1816                 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1817
1818         /* allocate buffers */
1819         bsize = sizeof(struct ath_buf) * nbuf;
1820         bf = kzalloc(bsize, GFP_KERNEL);
1821         if (bf == NULL) {
1822                 error = -ENOMEM;
1823                 goto fail2;
1824         }
1825         dd->dd_bufptr = bf;
1826
1827         for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1828                 bf->bf_desc = ds;
1829                 bf->bf_daddr = DS2PHYS(dd, ds);
1830
1831                 if (!(sc->sc_ah->caps.hw_caps &
1832                       ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1833                         /*
1834                          * Skip descriptor addresses which can cause 4KB
1835                          * boundary crossing (addr + length) with a 32 dword
1836                          * descriptor fetch.
1837                          */
1838                         while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1839                                 ASSERT((caddr_t) bf->bf_desc <
1840                                        ((caddr_t) dd->dd_desc +
1841                                         dd->dd_desc_len));
1842
1843                                 ds += ndesc;
1844                                 bf->bf_desc = ds;
1845                                 bf->bf_daddr = DS2PHYS(dd, ds);
1846                         }
1847                 }
1848                 list_add_tail(&bf->list, head);
1849         }
1850         return 0;
1851 fail2:
1852         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1853                           dd->dd_desc_paddr);
1854 fail:
1855         memset(dd, 0, sizeof(*dd));
1856         return error;
1857 #undef ATH_DESC_4KB_BOUND_CHECK
1858 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1859 #undef DS2PHYS
1860 }
1861
1862 void ath_descdma_cleanup(struct ath_softc *sc,
1863                          struct ath_descdma *dd,
1864                          struct list_head *head)
1865 {
1866         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1867                           dd->dd_desc_paddr);
1868
1869         INIT_LIST_HEAD(head);
1870         kfree(dd->dd_bufptr);
1871         memset(dd, 0, sizeof(*dd));
1872 }
1873
1874 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1875 {
1876         int qnum;
1877
1878         switch (queue) {
1879         case 0:
1880                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
1881                 break;
1882         case 1:
1883                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
1884                 break;
1885         case 2:
1886                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1887                 break;
1888         case 3:
1889                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
1890                 break;
1891         default:
1892                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1893                 break;
1894         }
1895
1896         return qnum;
1897 }
1898
1899 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1900 {
1901         int qnum;
1902
1903         switch (queue) {
1904         case ATH9K_WME_AC_VO:
1905                 qnum = 0;
1906                 break;
1907         case ATH9K_WME_AC_VI:
1908                 qnum = 1;
1909                 break;
1910         case ATH9K_WME_AC_BE:
1911                 qnum = 2;
1912                 break;
1913         case ATH9K_WME_AC_BK:
1914                 qnum = 3;
1915                 break;
1916         default:
1917                 qnum = -1;
1918                 break;
1919         }
1920
1921         return qnum;
1922 }
1923
1924 /* XXX: Remove me once we don't depend on ath9k_channel for all
1925  * this redundant data */
1926 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
1927                            struct ath9k_channel *ichan)
1928 {
1929         struct ieee80211_channel *chan = hw->conf.channel;
1930         struct ieee80211_conf *conf = &hw->conf;
1931
1932         ichan->channel = chan->center_freq;
1933         ichan->chan = chan;
1934
1935         if (chan->band == IEEE80211_BAND_2GHZ) {
1936                 ichan->chanmode = CHANNEL_G;
1937                 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1938         } else {
1939                 ichan->chanmode = CHANNEL_A;
1940                 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1941         }
1942
1943         sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1944
1945         if (conf_is_ht(conf)) {
1946                 if (conf_is_ht40(conf))
1947                         sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1948
1949                 ichan->chanmode = ath_get_extchanmode(sc, chan,
1950                                             conf->channel_type);
1951         }
1952 }
1953
1954 /**********************/
1955 /* mac80211 callbacks */
1956 /**********************/
1957
1958 static int ath9k_start(struct ieee80211_hw *hw)
1959 {
1960         struct ath_wiphy *aphy = hw->priv;
1961         struct ath_softc *sc = aphy->sc;
1962         struct ieee80211_channel *curchan = hw->conf.channel;
1963         struct ath9k_channel *init_channel;
1964         int r, pos;
1965
1966         DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1967                 "initial channel: %d MHz\n", curchan->center_freq);
1968
1969         mutex_lock(&sc->mutex);
1970
1971         if (ath9k_wiphy_started(sc)) {
1972                 if (sc->chan_idx == curchan->hw_value) {
1973                         /*
1974                          * Already on the operational channel, the new wiphy
1975                          * can be marked active.
1976                          */
1977                         aphy->state = ATH_WIPHY_ACTIVE;
1978                         ieee80211_wake_queues(hw);
1979                 } else {
1980                         /*
1981                          * Another wiphy is on another channel, start the new
1982                          * wiphy in paused state.
1983                          */
1984                         aphy->state = ATH_WIPHY_PAUSED;
1985                         ieee80211_stop_queues(hw);
1986                 }
1987                 mutex_unlock(&sc->mutex);
1988                 return 0;
1989         }
1990         aphy->state = ATH_WIPHY_ACTIVE;
1991
1992         /* setup initial channel */
1993
1994         pos = curchan->hw_value;
1995
1996         sc->chan_idx = pos;
1997         init_channel = &sc->sc_ah->channels[pos];
1998         ath9k_update_ichannel(sc, hw, init_channel);
1999
2000         /* Reset SERDES registers */
2001         ath9k_hw_configpcipowersave(sc->sc_ah, 0);
2002
2003         /*
2004          * The basic interface to setting the hardware in a good
2005          * state is ``reset''.  On return the hardware is known to
2006          * be powered up and with interrupts disabled.  This must
2007          * be followed by initialization of the appropriate bits
2008          * and then setup of the interrupt mask.
2009          */
2010         spin_lock_bh(&sc->sc_resetlock);
2011         r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
2012         if (r) {
2013                 DPRINTF(sc, ATH_DBG_FATAL,
2014                         "Unable to reset hardware; reset status %u "
2015                         "(freq %u MHz)\n", r,
2016                         curchan->center_freq);
2017                 spin_unlock_bh(&sc->sc_resetlock);
2018                 goto mutex_unlock;
2019         }
2020         spin_unlock_bh(&sc->sc_resetlock);
2021
2022         /*
2023          * This is needed only to setup initial state
2024          * but it's best done after a reset.
2025          */
2026         ath_update_txpow(sc);
2027
2028         /*
2029          * Setup the hardware after reset:
2030          * The receive engine is set going.
2031          * Frame transmit is handled entirely
2032          * in the frame output path; there's nothing to do
2033          * here except setup the interrupt mask.
2034          */
2035         if (ath_startrecv(sc) != 0) {
2036                 DPRINTF(sc, ATH_DBG_FATAL,
2037                         "Unable to start recv logic\n");
2038                 r = -EIO;
2039                 goto mutex_unlock;
2040         }
2041
2042         /* Setup our intr mask. */
2043         sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
2044                 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2045                 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2046
2047         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
2048                 sc->imask |= ATH9K_INT_GTT;
2049
2050         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
2051                 sc->imask |= ATH9K_INT_CST;
2052
2053         ath_cache_conf_rate(sc, &hw->conf);
2054
2055         sc->sc_flags &= ~SC_OP_INVALID;
2056
2057         /* Disable BMISS interrupt when we're not associated */
2058         sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2059         ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2060
2061         ieee80211_wake_queues(hw);
2062
2063 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2064         r = ath_start_rfkill_poll(sc);
2065 #endif
2066
2067 mutex_unlock:
2068         mutex_unlock(&sc->mutex);
2069
2070         return r;
2071 }
2072
2073 static int ath9k_tx(struct ieee80211_hw *hw,
2074                     struct sk_buff *skb)
2075 {
2076         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2077         struct ath_wiphy *aphy = hw->priv;
2078         struct ath_softc *sc = aphy->sc;
2079         struct ath_tx_control txctl;
2080         int hdrlen, padsize;
2081
2082         if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
2083                 printk(KERN_DEBUG "ath9k: %s: TX in unexpected wiphy state "
2084                        "%d\n", wiphy_name(hw->wiphy), aphy->state);
2085                 goto exit;
2086         }
2087
2088         memset(&txctl, 0, sizeof(struct ath_tx_control));
2089
2090         /*
2091          * As a temporary workaround, assign seq# here; this will likely need
2092          * to be cleaned up to work better with Beacon transmission and virtual
2093          * BSSes.
2094          */
2095         if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2096                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2097                 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2098                         sc->tx.seq_no += 0x10;
2099                 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2100                 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2101         }
2102
2103         /* Add the padding after the header if this is not already done */
2104         hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2105         if (hdrlen & 3) {
2106                 padsize = hdrlen % 4;
2107                 if (skb_headroom(skb) < padsize)
2108                         return -1;
2109                 skb_push(skb, padsize);
2110                 memmove(skb->data, skb->data + padsize, hdrlen);
2111         }
2112
2113         /* Check if a tx queue is available */
2114
2115         txctl.txq = ath_test_get_txq(sc, skb);
2116         if (!txctl.txq)
2117                 goto exit;
2118
2119         DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2120
2121         if (ath_tx_start(hw, skb, &txctl) != 0) {
2122                 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
2123                 goto exit;
2124         }
2125
2126         return 0;
2127 exit:
2128         dev_kfree_skb_any(skb);
2129         return 0;
2130 }
2131
2132 static void ath9k_stop(struct ieee80211_hw *hw)
2133 {
2134         struct ath_wiphy *aphy = hw->priv;
2135         struct ath_softc *sc = aphy->sc;
2136
2137         aphy->state = ATH_WIPHY_INACTIVE;
2138
2139         if (sc->sc_flags & SC_OP_INVALID) {
2140                 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
2141                 return;
2142         }
2143
2144         mutex_lock(&sc->mutex);
2145
2146         ieee80211_stop_queues(hw);
2147
2148         if (ath9k_wiphy_started(sc)) {
2149                 mutex_unlock(&sc->mutex);
2150                 return; /* another wiphy still in use */
2151         }
2152
2153         /* make sure h/w will not generate any interrupt
2154          * before setting the invalid flag. */
2155         ath9k_hw_set_interrupts(sc->sc_ah, 0);
2156
2157         if (!(sc->sc_flags & SC_OP_INVALID)) {
2158                 ath_drain_all_txq(sc, false);
2159                 ath_stoprecv(sc);
2160                 ath9k_hw_phy_disable(sc->sc_ah);
2161         } else
2162                 sc->rx.rxlink = NULL;
2163
2164 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2165         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2166                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2167 #endif
2168         /* disable HAL and put h/w to sleep */
2169         ath9k_hw_disable(sc->sc_ah);
2170         ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2171
2172         sc->sc_flags |= SC_OP_INVALID;
2173
2174         mutex_unlock(&sc->mutex);
2175
2176         DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
2177 }
2178
2179 static int ath9k_add_interface(struct ieee80211_hw *hw,
2180                                struct ieee80211_if_init_conf *conf)
2181 {
2182         struct ath_wiphy *aphy = hw->priv;
2183         struct ath_softc *sc = aphy->sc;
2184         struct ath_vif *avp = (void *)conf->vif->drv_priv;
2185         enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2186         int ret = 0;
2187
2188         mutex_lock(&sc->mutex);
2189
2190         if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2191             sc->nvifs > 0) {
2192                 ret = -ENOBUFS;
2193                 goto out;
2194         }
2195
2196         switch (conf->type) {
2197         case NL80211_IFTYPE_STATION:
2198                 ic_opmode = NL80211_IFTYPE_STATION;
2199                 break;
2200         case NL80211_IFTYPE_ADHOC:
2201                 if (sc->nbcnvifs >= ATH_BCBUF) {
2202                         ret = -ENOBUFS;
2203                         goto out;
2204                 }
2205                 ic_opmode = NL80211_IFTYPE_ADHOC;
2206                 break;
2207         case NL80211_IFTYPE_AP:
2208                 if (sc->nbcnvifs >= ATH_BCBUF) {
2209                         ret = -ENOBUFS;
2210                         goto out;
2211                 }
2212                 ic_opmode = NL80211_IFTYPE_AP;
2213                 break;
2214         default:
2215                 DPRINTF(sc, ATH_DBG_FATAL,
2216                         "Interface type %d not yet supported\n", conf->type);
2217                 ret = -EOPNOTSUPP;
2218                 goto out;
2219         }
2220
2221         DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
2222
2223         /* Set the VIF opmode */
2224         avp->av_opmode = ic_opmode;
2225         avp->av_bslot = -1;
2226
2227         sc->nvifs++;
2228
2229         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2230                 ath9k_set_bssid_mask(hw);
2231
2232         if (sc->nvifs > 1)
2233                 goto out; /* skip global settings for secondary vif */
2234
2235         if (ic_opmode == NL80211_IFTYPE_AP) {
2236                 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2237                 sc->sc_flags |= SC_OP_TSF_RESET;
2238         }
2239
2240         /* Set the device opmode */
2241         sc->sc_ah->opmode = ic_opmode;
2242
2243         /*
2244          * Enable MIB interrupts when there are hardware phy counters.
2245          * Note we only do this (at the moment) for station mode.
2246          */
2247         if ((conf->type == NL80211_IFTYPE_STATION) ||
2248             (conf->type == NL80211_IFTYPE_ADHOC)) {
2249                 if (ath9k_hw_phycounters(sc->sc_ah))
2250                         sc->imask |= ATH9K_INT_MIB;
2251                 sc->imask |= ATH9K_INT_TSFOOR;
2252         }
2253
2254         /*
2255          * Some hardware processes the TIM IE and fires an
2256          * interrupt when the TIM bit is set.  For hardware
2257          * that does, if not overridden by configuration,
2258          * enable the TIM interrupt when operating as station.
2259          */
2260         if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
2261             (conf->type == NL80211_IFTYPE_STATION) &&
2262             !sc->config.swBeaconProcess)
2263                 sc->imask |= ATH9K_INT_TIM;
2264
2265         ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2266
2267         if (conf->type == NL80211_IFTYPE_AP) {
2268                 /* TODO: is this a suitable place to start ANI for AP mode? */
2269                 /* Start ANI */
2270                 mod_timer(&sc->ani.timer,
2271                           jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2272         }
2273
2274 out:
2275         mutex_unlock(&sc->mutex);
2276         return ret;
2277 }
2278
2279 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2280                                    struct ieee80211_if_init_conf *conf)
2281 {
2282         struct ath_wiphy *aphy = hw->priv;
2283         struct ath_softc *sc = aphy->sc;
2284         struct ath_vif *avp = (void *)conf->vif->drv_priv;
2285         int i;
2286
2287         DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
2288
2289         mutex_lock(&sc->mutex);
2290
2291         /* Stop ANI */
2292         del_timer_sync(&sc->ani.timer);
2293
2294         /* Reclaim beacon resources */
2295         if (sc->sc_ah->opmode == NL80211_IFTYPE_AP ||
2296             sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) {
2297                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2298                 ath_beacon_return(sc, avp);
2299         }
2300
2301         sc->sc_flags &= ~SC_OP_BEACONS;
2302
2303         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2304                 if (sc->beacon.bslot[i] == conf->vif) {
2305                         printk(KERN_DEBUG "%s: vif had allocated beacon "
2306                                "slot\n", __func__);
2307                         sc->beacon.bslot[i] = NULL;
2308                         sc->beacon.bslot_aphy[i] = NULL;
2309                 }
2310         }
2311
2312         sc->nvifs--;
2313
2314         mutex_unlock(&sc->mutex);
2315 }
2316
2317 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2318 {
2319         struct ath_wiphy *aphy = hw->priv;
2320         struct ath_softc *sc = aphy->sc;
2321         struct ieee80211_conf *conf = &hw->conf;
2322
2323         mutex_lock(&sc->mutex);
2324
2325         if (changed & IEEE80211_CONF_CHANGE_PS) {
2326                 if (conf->flags & IEEE80211_CONF_PS) {
2327                         if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2328                                 sc->imask |= ATH9K_INT_TIM_TIMER;
2329                                 ath9k_hw_set_interrupts(sc->sc_ah,
2330                                                 sc->imask);
2331                         }
2332                         ath9k_hw_setrxabort(sc->sc_ah, 1);
2333                         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2334                 } else {
2335                         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
2336                         ath9k_hw_setrxabort(sc->sc_ah, 0);
2337                         sc->sc_flags &= ~SC_OP_WAIT_FOR_BEACON;
2338                         if (sc->imask & ATH9K_INT_TIM_TIMER) {
2339                                 sc->imask &= ~ATH9K_INT_TIM_TIMER;
2340                                 ath9k_hw_set_interrupts(sc->sc_ah,
2341                                                 sc->imask);
2342                         }
2343                 }
2344         }
2345
2346         if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2347                 struct ieee80211_channel *curchan = hw->conf.channel;
2348                 int pos = curchan->hw_value;
2349
2350                 aphy->chan_idx = pos;
2351                 aphy->chan_is_ht = conf_is_ht(conf);
2352
2353                 if (aphy->state == ATH_WIPHY_SCAN ||
2354                     aphy->state == ATH_WIPHY_ACTIVE)
2355                         ath9k_wiphy_pause_all_forced(sc, aphy);
2356                 else {
2357                         /*
2358                          * Do not change operational channel based on a paused
2359                          * wiphy changes.
2360                          */
2361                         goto skip_chan_change;
2362                 }
2363
2364                 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2365                         curchan->center_freq);
2366
2367                 /* XXX: remove me eventualy */
2368                 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
2369
2370                 ath_update_chainmask(sc, conf_is_ht(conf));
2371
2372                 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
2373                         DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
2374                         mutex_unlock(&sc->mutex);
2375                         return -EINVAL;
2376                 }
2377         }
2378
2379 skip_chan_change:
2380         if (changed & IEEE80211_CONF_CHANGE_POWER)
2381                 sc->config.txpowlimit = 2 * conf->power_level;
2382
2383         /*
2384          * The HW TSF has to be reset when the beacon interval changes.
2385          * We set the flag here, and ath_beacon_config_ap() would take this
2386          * into account when it gets called through the subsequent
2387          * config_interface() call - with IFCC_BEACON in the changed field.
2388          */
2389
2390         if (changed & IEEE80211_CONF_CHANGE_BEACON_INTERVAL)
2391                 sc->sc_flags |= SC_OP_TSF_RESET;
2392
2393         mutex_unlock(&sc->mutex);
2394
2395         return 0;
2396 }
2397
2398 static int ath9k_config_interface(struct ieee80211_hw *hw,
2399                                   struct ieee80211_vif *vif,
2400                                   struct ieee80211_if_conf *conf)
2401 {
2402         struct ath_wiphy *aphy = hw->priv;
2403         struct ath_softc *sc = aphy->sc;
2404         struct ath_hw *ah = sc->sc_ah;
2405         struct ath_vif *avp = (void *)vif->drv_priv;
2406         u32 rfilt = 0;
2407         int error, i;
2408
2409         mutex_lock(&sc->mutex);
2410
2411         /* TODO: Need to decide which hw opmode to use for multi-interface
2412          * cases */
2413         if (vif->type == NL80211_IFTYPE_AP &&
2414             ah->opmode != NL80211_IFTYPE_AP) {
2415                 ah->opmode = NL80211_IFTYPE_STATION;
2416                 ath9k_hw_setopmode(ah);
2417                 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2418                 sc->curaid = 0;
2419                 ath9k_hw_write_associd(sc);
2420                 /* Request full reset to get hw opmode changed properly */
2421                 sc->sc_flags |= SC_OP_FULL_RESET;
2422         }
2423
2424         if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2425             !is_zero_ether_addr(conf->bssid)) {
2426                 switch (vif->type) {
2427                 case NL80211_IFTYPE_STATION:
2428                 case NL80211_IFTYPE_ADHOC:
2429                         /* Set BSSID */
2430                         memcpy(sc->curbssid, conf->bssid, ETH_ALEN);
2431                         memcpy(avp->bssid, conf->bssid, ETH_ALEN);
2432                         sc->curaid = 0;
2433                         ath9k_hw_write_associd(sc);
2434
2435                         /* Set aggregation protection mode parameters */
2436                         sc->config.ath_aggr_prot = 0;
2437
2438                         DPRINTF(sc, ATH_DBG_CONFIG,
2439                                 "RX filter 0x%x bssid %pM aid 0x%x\n",
2440                                 rfilt, sc->curbssid, sc->curaid);
2441
2442                         /* need to reconfigure the beacon */
2443                         sc->sc_flags &= ~SC_OP_BEACONS ;
2444
2445                         break;
2446                 default:
2447                         break;
2448                 }
2449         }
2450
2451         if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2452             (vif->type == NL80211_IFTYPE_AP)) {
2453                 if ((conf->changed & IEEE80211_IFCC_BEACON) ||
2454                     (conf->changed & IEEE80211_IFCC_BEACON_ENABLED &&
2455                      conf->enable_beacon)) {
2456                         /*
2457                          * Allocate and setup the beacon frame.
2458                          *
2459                          * Stop any previous beacon DMA.  This may be
2460                          * necessary, for example, when an ibss merge
2461                          * causes reconfiguration; we may be called
2462                          * with beacon transmission active.
2463                          */
2464                         ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2465
2466                         error = ath_beacon_alloc(aphy, vif);
2467                         if (error != 0) {
2468                                 mutex_unlock(&sc->mutex);
2469                                 return error;
2470                         }
2471
2472                         ath_beacon_config(sc, vif);
2473                 }
2474         }
2475
2476         /* Check for WLAN_CAPABILITY_PRIVACY ? */
2477         if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2478                 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2479                         if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2480                                 ath9k_hw_keysetmac(sc->sc_ah,
2481                                                    (u16)i,
2482                                                    sc->curbssid);
2483         }
2484
2485         /* Only legacy IBSS for now */
2486         if (vif->type == NL80211_IFTYPE_ADHOC)
2487                 ath_update_chainmask(sc, 0);
2488
2489         mutex_unlock(&sc->mutex);
2490
2491         return 0;
2492 }
2493
2494 #define SUPPORTED_FILTERS                       \
2495         (FIF_PROMISC_IN_BSS |                   \
2496         FIF_ALLMULTI |                          \
2497         FIF_CONTROL |                           \
2498         FIF_OTHER_BSS |                         \
2499         FIF_BCN_PRBRESP_PROMISC |               \
2500         FIF_FCSFAIL)
2501
2502 /* FIXME: sc->sc_full_reset ? */
2503 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2504                                    unsigned int changed_flags,
2505                                    unsigned int *total_flags,
2506                                    int mc_count,
2507                                    struct dev_mc_list *mclist)
2508 {
2509         struct ath_wiphy *aphy = hw->priv;
2510         struct ath_softc *sc = aphy->sc;
2511         u32 rfilt;
2512
2513         changed_flags &= SUPPORTED_FILTERS;
2514         *total_flags &= SUPPORTED_FILTERS;
2515
2516         sc->rx.rxfilter = *total_flags;
2517         rfilt = ath_calcrxfilter(sc);
2518         ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2519
2520         DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
2521 }
2522
2523 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2524                              struct ieee80211_vif *vif,
2525                              enum sta_notify_cmd cmd,
2526                              struct ieee80211_sta *sta)
2527 {
2528         struct ath_wiphy *aphy = hw->priv;
2529         struct ath_softc *sc = aphy->sc;
2530
2531         switch (cmd) {
2532         case STA_NOTIFY_ADD:
2533                 ath_node_attach(sc, sta);
2534                 break;
2535         case STA_NOTIFY_REMOVE:
2536                 ath_node_detach(sc, sta);
2537                 break;
2538         default:
2539                 break;
2540         }
2541 }
2542
2543 static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2544                          const struct ieee80211_tx_queue_params *params)
2545 {
2546         struct ath_wiphy *aphy = hw->priv;
2547         struct ath_softc *sc = aphy->sc;
2548         struct ath9k_tx_queue_info qi;
2549         int ret = 0, qnum;
2550
2551         if (queue >= WME_NUM_AC)
2552                 return 0;
2553
2554         mutex_lock(&sc->mutex);
2555
2556         qi.tqi_aifs = params->aifs;
2557         qi.tqi_cwmin = params->cw_min;
2558         qi.tqi_cwmax = params->cw_max;
2559         qi.tqi_burstTime = params->txop;
2560         qnum = ath_get_hal_qnum(queue, sc);
2561
2562         DPRINTF(sc, ATH_DBG_CONFIG,
2563                 "Configure tx [queue/halq] [%d/%d],  "
2564                 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2565                 queue, qnum, params->aifs, params->cw_min,
2566                 params->cw_max, params->txop);
2567
2568         ret = ath_txq_update(sc, qnum, &qi);
2569         if (ret)
2570                 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
2571
2572         mutex_unlock(&sc->mutex);
2573
2574         return ret;
2575 }
2576
2577 static int ath9k_set_key(struct ieee80211_hw *hw,
2578                          enum set_key_cmd cmd,
2579                          struct ieee80211_vif *vif,
2580                          struct ieee80211_sta *sta,
2581                          struct ieee80211_key_conf *key)
2582 {
2583         struct ath_wiphy *aphy = hw->priv;
2584         struct ath_softc *sc = aphy->sc;
2585         int ret = 0;
2586
2587         if (modparam_nohwcrypt)
2588                 return -ENOSPC;
2589
2590         mutex_lock(&sc->mutex);
2591         ath9k_ps_wakeup(sc);
2592         DPRINTF(sc, ATH_DBG_KEYCACHE, "Set HW Key\n");
2593
2594         switch (cmd) {
2595         case SET_KEY:
2596                 ret = ath_key_config(sc, vif, sta, key);
2597                 if (ret >= 0) {
2598                         key->hw_key_idx = ret;
2599                         /* push IV and Michael MIC generation to stack */
2600                         key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2601                         if (key->alg == ALG_TKIP)
2602                                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2603                         if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2604                                 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2605                         ret = 0;
2606                 }
2607                 break;
2608         case DISABLE_KEY:
2609                 ath_key_delete(sc, key);
2610                 break;
2611         default:
2612                 ret = -EINVAL;
2613         }
2614
2615         ath9k_ps_restore(sc);
2616         mutex_unlock(&sc->mutex);
2617
2618         return ret;
2619 }
2620
2621 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2622                                    struct ieee80211_vif *vif,
2623                                    struct ieee80211_bss_conf *bss_conf,
2624                                    u32 changed)
2625 {
2626         struct ath_wiphy *aphy = hw->priv;
2627         struct ath_softc *sc = aphy->sc;
2628
2629         mutex_lock(&sc->mutex);
2630
2631         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2632                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2633                         bss_conf->use_short_preamble);
2634                 if (bss_conf->use_short_preamble)
2635                         sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2636                 else
2637                         sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2638         }
2639
2640         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2641                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2642                         bss_conf->use_cts_prot);
2643                 if (bss_conf->use_cts_prot &&
2644                     hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2645                         sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2646                 else
2647                         sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2648         }
2649
2650         if (changed & BSS_CHANGED_ASSOC) {
2651                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2652                         bss_conf->assoc);
2653                 ath9k_bss_assoc_info(sc, vif, bss_conf);
2654         }
2655
2656         mutex_unlock(&sc->mutex);
2657 }
2658
2659 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2660 {
2661         u64 tsf;
2662         struct ath_wiphy *aphy = hw->priv;
2663         struct ath_softc *sc = aphy->sc;
2664
2665         mutex_lock(&sc->mutex);
2666         tsf = ath9k_hw_gettsf64(sc->sc_ah);
2667         mutex_unlock(&sc->mutex);
2668
2669         return tsf;
2670 }
2671
2672 static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2673 {
2674         struct ath_wiphy *aphy = hw->priv;
2675         struct ath_softc *sc = aphy->sc;
2676
2677         mutex_lock(&sc->mutex);
2678         ath9k_hw_settsf64(sc->sc_ah, tsf);
2679         mutex_unlock(&sc->mutex);
2680 }
2681
2682 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2683 {
2684         struct ath_wiphy *aphy = hw->priv;
2685         struct ath_softc *sc = aphy->sc;
2686
2687         mutex_lock(&sc->mutex);
2688         ath9k_hw_reset_tsf(sc->sc_ah);
2689         mutex_unlock(&sc->mutex);
2690 }
2691
2692 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2693                               enum ieee80211_ampdu_mlme_action action,
2694                               struct ieee80211_sta *sta,
2695                               u16 tid, u16 *ssn)
2696 {
2697         struct ath_wiphy *aphy = hw->priv;
2698         struct ath_softc *sc = aphy->sc;
2699         int ret = 0;
2700
2701         switch (action) {
2702         case IEEE80211_AMPDU_RX_START:
2703                 if (!(sc->sc_flags & SC_OP_RXAGGR))
2704                         ret = -ENOTSUPP;
2705                 break;
2706         case IEEE80211_AMPDU_RX_STOP:
2707                 break;
2708         case IEEE80211_AMPDU_TX_START:
2709                 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2710                 if (ret < 0)
2711                         DPRINTF(sc, ATH_DBG_FATAL,
2712                                 "Unable to start TX aggregation\n");
2713                 else
2714                         ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2715                 break;
2716         case IEEE80211_AMPDU_TX_STOP:
2717                 ret = ath_tx_aggr_stop(sc, sta, tid);
2718                 if (ret < 0)
2719                         DPRINTF(sc, ATH_DBG_FATAL,
2720                                 "Unable to stop TX aggregation\n");
2721
2722                 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2723                 break;
2724         case IEEE80211_AMPDU_TX_RESUME:
2725                 ath_tx_aggr_resume(sc, sta, tid);
2726                 break;
2727         default:
2728                 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
2729         }
2730
2731         return ret;
2732 }
2733
2734 static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
2735 {
2736         struct ath_wiphy *aphy = hw->priv;
2737         struct ath_softc *sc = aphy->sc;
2738
2739         if (ath9k_wiphy_scanning(sc)) {
2740                 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
2741                        "same time\n");
2742                 /*
2743                  * Do not allow the concurrent scanning state for now. This
2744                  * could be improved with scanning control moved into ath9k.
2745                  */
2746                 return;
2747         }
2748
2749         aphy->state = ATH_WIPHY_SCAN;
2750         ath9k_wiphy_pause_all_forced(sc, aphy);
2751
2752         mutex_lock(&sc->mutex);
2753         sc->sc_flags |= SC_OP_SCANNING;
2754         mutex_unlock(&sc->mutex);
2755 }
2756
2757 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
2758 {
2759         struct ath_wiphy *aphy = hw->priv;
2760         struct ath_softc *sc = aphy->sc;
2761
2762         mutex_lock(&sc->mutex);
2763         aphy->state = ATH_WIPHY_ACTIVE;
2764         sc->sc_flags &= ~SC_OP_SCANNING;
2765         mutex_unlock(&sc->mutex);
2766 }
2767
2768 struct ieee80211_ops ath9k_ops = {
2769         .tx                 = ath9k_tx,
2770         .start              = ath9k_start,
2771         .stop               = ath9k_stop,
2772         .add_interface      = ath9k_add_interface,
2773         .remove_interface   = ath9k_remove_interface,
2774         .config             = ath9k_config,
2775         .config_interface   = ath9k_config_interface,
2776         .configure_filter   = ath9k_configure_filter,
2777         .sta_notify         = ath9k_sta_notify,
2778         .conf_tx            = ath9k_conf_tx,
2779         .bss_info_changed   = ath9k_bss_info_changed,
2780         .set_key            = ath9k_set_key,
2781         .get_tsf            = ath9k_get_tsf,
2782         .set_tsf            = ath9k_set_tsf,
2783         .reset_tsf          = ath9k_reset_tsf,
2784         .ampdu_action       = ath9k_ampdu_action,
2785         .sw_scan_start      = ath9k_sw_scan_start,
2786         .sw_scan_complete   = ath9k_sw_scan_complete,
2787 };
2788
2789 static struct {
2790         u32 version;
2791         const char * name;
2792 } ath_mac_bb_names[] = {
2793         { AR_SREV_VERSION_5416_PCI,     "5416" },
2794         { AR_SREV_VERSION_5416_PCIE,    "5418" },
2795         { AR_SREV_VERSION_9100,         "9100" },
2796         { AR_SREV_VERSION_9160,         "9160" },
2797         { AR_SREV_VERSION_9280,         "9280" },
2798         { AR_SREV_VERSION_9285,         "9285" }
2799 };
2800
2801 static struct {
2802         u16 version;
2803         const char * name;
2804 } ath_rf_names[] = {
2805         { 0,                            "5133" },
2806         { AR_RAD5133_SREV_MAJOR,        "5133" },
2807         { AR_RAD5122_SREV_MAJOR,        "5122" },
2808         { AR_RAD2133_SREV_MAJOR,        "2133" },
2809         { AR_RAD2122_SREV_MAJOR,        "2122" }
2810 };
2811
2812 /*
2813  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2814  */
2815 const char *
2816 ath_mac_bb_name(u32 mac_bb_version)
2817 {
2818         int i;
2819
2820         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2821                 if (ath_mac_bb_names[i].version == mac_bb_version) {
2822                         return ath_mac_bb_names[i].name;
2823                 }
2824         }
2825
2826         return "????";
2827 }
2828
2829 /*
2830  * Return the RF name. "????" is returned if the RF is unknown.
2831  */
2832 const char *
2833 ath_rf_name(u16 rf_version)
2834 {
2835         int i;
2836
2837         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2838                 if (ath_rf_names[i].version == rf_version) {
2839                         return ath_rf_names[i].name;
2840                 }
2841         }
2842
2843         return "????";
2844 }
2845
2846 static int __init ath9k_init(void)
2847 {
2848         int error;
2849
2850         /* Register rate control algorithm */
2851         error = ath_rate_control_register();
2852         if (error != 0) {
2853                 printk(KERN_ERR
2854                         "ath9k: Unable to register rate control "
2855                         "algorithm: %d\n",
2856                         error);
2857                 goto err_out;
2858         }
2859
2860         error = ath9k_debug_create_root();
2861         if (error) {
2862                 printk(KERN_ERR
2863                         "ath9k: Unable to create debugfs root: %d\n",
2864                         error);
2865                 goto err_rate_unregister;
2866         }
2867
2868         error = ath_pci_init();
2869         if (error < 0) {
2870                 printk(KERN_ERR
2871                         "ath9k: No PCI devices found, driver not installed.\n");
2872                 error = -ENODEV;
2873                 goto err_remove_root;
2874         }
2875
2876         error = ath_ahb_init();
2877         if (error < 0) {
2878                 error = -ENODEV;
2879                 goto err_pci_exit;
2880         }
2881
2882         return 0;
2883
2884  err_pci_exit:
2885         ath_pci_exit();
2886
2887  err_remove_root:
2888         ath9k_debug_remove_root();
2889  err_rate_unregister:
2890         ath_rate_control_unregister();
2891  err_out:
2892         return error;
2893 }
2894 module_init(ath9k_init);
2895
2896 static void __exit ath9k_exit(void)
2897 {
2898         ath_ahb_exit();
2899         ath_pci_exit();
2900         ath9k_debug_remove_root();
2901         ath_rate_control_unregister();
2902         printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
2903 }
2904 module_exit(ath9k_exit);