SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/ath9k/main.c

   1 /*
   2  * Copyright (c) 2008 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/nl80211.h>
  18 #include "ath9k.h"
  19
  20 #define ATH_PCI_VERSION "0.1"
  21
  22 static char *dev_info = "ath9k";
  23
  24 MODULE_AUTHOR("Atheros Communications");
  25 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  26 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  27 MODULE_LICENSE("Dual BSD/GPL");
  28
  29 /* We use the hw_value as an index into our private channel structure */
  30
  31 #define CHAN2G(_freq, _idx)  { \
  32         .center_freq = (_freq), \
  33         .hw_value = (_idx), \
  34         .max_power = 30, \
  35 }
  36
  37 #define CHAN5G(_freq, _idx) { \
  38         .band = IEEE80211_BAND_5GHZ, \
  39         .center_freq = (_freq), \
  40         .hw_value = (_idx), \
  41         .max_power = 30, \
  42 }
  43
  44 /* Some 2 GHz radios are actually tunable on 2312-2732
  45  * on 5 MHz steps, we support the channels which we know
  46  * we have calibration data for all cards though to make
  47  * this static */
  48 static struct ieee80211_channel ath9k_2ghz_chantable[] = {
  49         CHAN2G(2412, 0), /* Channel 1 */
  50         CHAN2G(2417, 1), /* Channel 2 */
  51         CHAN2G(2422, 2), /* Channel 3 */
  52         CHAN2G(2427, 3), /* Channel 4 */
  53         CHAN2G(2432, 4), /* Channel 5 */
  54         CHAN2G(2437, 5), /* Channel 6 */
  55         CHAN2G(2442, 6), /* Channel 7 */
  56         CHAN2G(2447, 7), /* Channel 8 */
  57         CHAN2G(2452, 8), /* Channel 9 */
  58         CHAN2G(2457, 9), /* Channel 10 */
  59         CHAN2G(2462, 10), /* Channel 11 */
  60         CHAN2G(2467, 11), /* Channel 12 */
  61         CHAN2G(2472, 12), /* Channel 13 */
  62         CHAN2G(2484, 13), /* Channel 14 */
  63 };
  64
  65 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
  66  * on 5 MHz steps, we support the channels which we know
  67  * we have calibration data for all cards though to make
  68  * this static */
  69 static struct ieee80211_channel ath9k_5ghz_chantable[] = {
  70         /* _We_ call this UNII 1 */
  71         CHAN5G(5180, 14), /* Channel 36 */
  72         CHAN5G(5200, 15), /* Channel 40 */
  73         CHAN5G(5220, 16), /* Channel 44 */
  74         CHAN5G(5240, 17), /* Channel 48 */
  75         /* _We_ call this UNII 2 */
  76         CHAN5G(5260, 18), /* Channel 52 */
  77         CHAN5G(5280, 19), /* Channel 56 */
  78         CHAN5G(5300, 20), /* Channel 60 */
  79         CHAN5G(5320, 21), /* Channel 64 */
  80         /* _We_ call this "Middle band" */
  81         CHAN5G(5500, 22), /* Channel 100 */
  82         CHAN5G(5520, 23), /* Channel 104 */
  83         CHAN5G(5540, 24), /* Channel 108 */
  84         CHAN5G(5560, 25), /* Channel 112 */
  85         CHAN5G(5580, 26), /* Channel 116 */
  86         CHAN5G(5600, 27), /* Channel 120 */
  87         CHAN5G(5620, 28), /* Channel 124 */
  88         CHAN5G(5640, 29), /* Channel 128 */
  89         CHAN5G(5660, 30), /* Channel 132 */
  90         CHAN5G(5680, 31), /* Channel 136 */
  91         CHAN5G(5700, 32), /* Channel 140 */
  92         /* _We_ call this UNII 3 */
  93         CHAN5G(5745, 33), /* Channel 149 */
  94         CHAN5G(5765, 34), /* Channel 153 */
  95         CHAN5G(5785, 35), /* Channel 157 */
  96         CHAN5G(5805, 36), /* Channel 161 */
  97         CHAN5G(5825, 37), /* Channel 165 */
  98 };
  99
 100 static void ath_cache_conf_rate(struct ath_softc *sc,
 101                                 struct ieee80211_conf *conf)
 102 {
 103         switch (conf->channel->band) {
 104         case IEEE80211_BAND_2GHZ:
 105                 if (conf_is_ht20(conf))
 106                         sc->cur_rate_table =
 107                           sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
 108                 else if (conf_is_ht40_minus(conf))
 109                         sc->cur_rate_table =
 110                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
 111                 else if (conf_is_ht40_plus(conf))
 112                         sc->cur_rate_table =
 113                           sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
 114                 else
 115                         sc->cur_rate_table =
 116                           sc->hw_rate_table[ATH9K_MODE_11G];
 117                 break;
 118         case IEEE80211_BAND_5GHZ:
 119                 if (conf_is_ht20(conf))
 120                         sc->cur_rate_table =
 121                           sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
 122                 else if (conf_is_ht40_minus(conf))
 123                         sc->cur_rate_table =
 124                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
 125                 else if (conf_is_ht40_plus(conf))
 126                         sc->cur_rate_table =
 127                           sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
 128                 else
 129                         sc->cur_rate_table =
 130                           sc->hw_rate_table[ATH9K_MODE_11A];
 131                 break;
 132         default:
 133                 BUG_ON(1);
 134                 break;
 135         }
 136 }
 137
 138 static void ath_update_txpow(struct ath_softc *sc)
 139 {
 140         struct ath_hw *ah = sc->sc_ah;
 141         u32 txpow;
 142
 143         if (sc->curtxpow != sc->config.txpowlimit) {
 144                 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
 145                 /* read back in case value is clamped */
 146                 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
 147                 sc->curtxpow = txpow;
 148         }
 149 }
 150
 151 static u8 parse_mpdudensity(u8 mpdudensity)
 152 {
 153         /*
 154          * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
 155          *   0 for no restriction
 156          *   1 for 1/4 us
 157          *   2 for 1/2 us
 158          *   3 for 1 us
 159          *   4 for 2 us
 160          *   5 for 4 us
 161          *   6 for 8 us
 162          *   7 for 16 us
 163          */
 164         switch (mpdudensity) {
 165         case 0:
 166                 return 0;
 167         case 1:
 168         case 2:
 169         case 3:
 170                 /* Our lower layer calculations limit our precision to
 171                    1 microsecond */
 172                 return 1;
 173         case 4:
 174                 return 2;
 175         case 5:
 176                 return 4;
 177         case 6:
 178                 return 8;
 179         case 7:
 180                 return 16;
 181         default:
 182                 return 0;
 183         }
 184 }
 185
 186 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
 187 {
 188         struct ath_rate_table *rate_table = NULL;
 189         struct ieee80211_supported_band *sband;
 190         struct ieee80211_rate *rate;
 191         int i, maxrates;
 192
 193         switch (band) {
 194         case IEEE80211_BAND_2GHZ:
 195                 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
 196                 break;
 197         case IEEE80211_BAND_5GHZ:
 198                 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
 199                 break;
 200         default:
 201                 break;
 202         }
 203
 204         if (rate_table == NULL)
 205                 return;
 206
 207         sband = &sc->sbands[band];
 208         rate = sc->rates[band];
 209
 210         if (rate_table->rate_cnt > ATH_RATE_MAX)
 211                 maxrates = ATH_RATE_MAX;
 212         else
 213                 maxrates = rate_table->rate_cnt;
 214
 215         for (i = 0; i < maxrates; i++) {
 216                 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
 217                 rate[i].hw_value = rate_table->info[i].ratecode;
 218                 if (rate_table->info[i].short_preamble) {
 219                         rate[i].hw_value_short = rate_table->info[i].ratecode |
 220                                 rate_table->info[i].short_preamble;
 221                         rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
 222                 }
 223                 sband->n_bitrates++;
 224
 225                 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
 226                         rate[i].bitrate / 10, rate[i].hw_value);
 227         }
 228 }
 229
 230 /*
 231  * Set/change channels.  If the channel is really being changed, it's done
 232  * by reseting the chip.  To accomplish this we must first cleanup any pending
 233  * DMA, then restart stuff.
 234 */
 235 static int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
 236 {
 237         struct ath_hw *ah = sc->sc_ah;
 238         bool fastcc = true, stopped;
 239         struct ieee80211_hw *hw = sc->hw;
 240         struct ieee80211_channel *channel = hw->conf.channel;
 241         int r;
 242
 243         if (sc->sc_flags & SC_OP_INVALID)
 244                 return -EIO;
 245
 246         ath9k_ps_wakeup(sc);
 247
 248         /*
 249          * This is only performed if the channel settings have
 250          * actually changed.
 251          *
 252          * To switch channels clear any pending DMA operations;
 253          * wait long enough for the RX fifo to drain, reset the
 254          * hardware at the new frequency, and then re-enable
 255          * the relevant bits of the h/w.
 256          */
 257         ath9k_hw_set_interrupts(ah, 0);
 258         ath_drain_all_txq(sc, false);
 259         stopped = ath_stoprecv(sc);
 260
 261         /* XXX: do not flush receive queue here. We don't want
 262          * to flush data frames already in queue because of
 263          * changing channel. */
 264
 265         if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
 266                 fastcc = false;
 267
 268         DPRINTF(sc, ATH_DBG_CONFIG,
 269                 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
 270                 sc->sc_ah->curchan->channel,
 271                 channel->center_freq, sc->tx_chan_width);
 272
 273         spin_lock_bh(&sc->sc_resetlock);
 274
 275         r = ath9k_hw_reset(ah, hchan, fastcc);
 276         if (r) {
 277                 DPRINTF(sc, ATH_DBG_FATAL,
 278                         "Unable to reset channel (%u Mhz) "
 279                         "reset status %u\n",
 280                         channel->center_freq, r);
 281                 spin_unlock_bh(&sc->sc_resetlock);
 282                 return r;
 283         }
 284         spin_unlock_bh(&sc->sc_resetlock);
 285
 286         sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
 287         sc->sc_flags &= ~SC_OP_FULL_RESET;
 288
 289         if (ath_startrecv(sc) != 0) {
 290                 DPRINTF(sc, ATH_DBG_FATAL,
 291                         "Unable to restart recv logic\n");
 292                 return -EIO;
 293         }
 294
 295         ath_cache_conf_rate(sc, &hw->conf);
 296         ath_update_txpow(sc);
 297         ath9k_hw_set_interrupts(ah, sc->imask);
 298         ath9k_ps_restore(sc);
 299         return 0;
 300 }
 301
 302 /*
 303  *  This routine performs the periodic noise floor calibration function
 304  *  that is used to adjust and optimize the chip performance.  This
 305  *  takes environmental changes (location, temperature) into account.
 306  *  When the task is complete, it reschedules itself depending on the
 307  *  appropriate interval that was calculated.
 308  */
 309 static void ath_ani_calibrate(unsigned long data)
 310 {
 311         struct ath_softc *sc = (struct ath_softc *)data;
 312         struct ath_hw *ah = sc->sc_ah;
 313         bool longcal = false;
 314         bool shortcal = false;
 315         bool aniflag = false;
 316         unsigned int timestamp = jiffies_to_msecs(jiffies);
 317         u32 cal_interval, short_cal_interval;
 318
 319         short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
 320                 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
 321
 322         /*
 323         * don't calibrate when we're scanning.
 324         * we are most likely not on our home channel.
 325         */
 326         if (sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC)
 327                 goto set_timer;
 328
 329         /* Long calibration runs independently of short calibration. */
 330         if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
 331                 longcal = true;
 332                 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
 333                 sc->ani.longcal_timer = timestamp;
 334         }
 335
 336         /* Short calibration applies only while caldone is false */
 337         if (!sc->ani.caldone) {
 338                 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
 339                         shortcal = true;
 340                         DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
 341                         sc->ani.shortcal_timer = timestamp;
 342                         sc->ani.resetcal_timer = timestamp;
 343                 }
 344         } else {
 345                 if ((timestamp - sc->ani.resetcal_timer) >=
 346                     ATH_RESTART_CALINTERVAL) {
 347                         sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
 348                         if (sc->ani.caldone)
 349                                 sc->ani.resetcal_timer = timestamp;
 350                 }
 351         }
 352
 353         /* Verify whether we must check ANI */
 354         if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
 355                 aniflag = true;
 356                 sc->ani.checkani_timer = timestamp;
 357         }
 358
 359         /* Skip all processing if there's nothing to do. */
 360         if (longcal || shortcal || aniflag) {
 361                 /* Call ANI routine if necessary */
 362                 if (aniflag)
 363                         ath9k_hw_ani_monitor(ah, &sc->nodestats, ah->curchan);
 364
 365                 /* Perform calibration if necessary */
 366                 if (longcal || shortcal) {
 367                         bool iscaldone = false;
 368
 369                         if (ath9k_hw_calibrate(ah, ah->curchan,
 370                                                sc->rx_chainmask, longcal,
 371                                                &iscaldone)) {
 372                                 if (longcal)
 373                                         sc->ani.noise_floor =
 374                                                 ath9k_hw_getchan_noise(ah,
 375                                                                ah->curchan);
 376
 377                                 DPRINTF(sc, ATH_DBG_ANI,
 378                                         "calibrate chan %u/%x nf: %d\n",
 379                                         ah->curchan->channel,
 380                                         ah->curchan->channelFlags,
 381                                         sc->ani.noise_floor);
 382                         } else {
 383                                 DPRINTF(sc, ATH_DBG_ANY,
 384                                         "calibrate chan %u/%x failed\n",
 385                                         ah->curchan->channel,
 386                                         ah->curchan->channelFlags);
 387                         }
 388                         sc->ani.caldone = iscaldone;
 389                 }
 390         }
 391
 392 set_timer:
 393         /*
 394         * Set timer interval based on previous results.
 395         * The interval must be the shortest necessary to satisfy ANI,
 396         * short calibration and long calibration.
 397         */
 398         cal_interval = ATH_LONG_CALINTERVAL;
 399         if (sc->sc_ah->config.enable_ani)
 400                 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
 401         if (!sc->ani.caldone)
 402                 cal_interval = min(cal_interval, (u32)short_cal_interval);
 403
 404         mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
 405 }
 406
 407 /*
 408  * Update tx/rx chainmask. For legacy association,
 409  * hard code chainmask to 1x1, for 11n association, use
 410  * the chainmask configuration, for bt coexistence, use
 411  * the chainmask configuration even in legacy mode.
 412  */
 413 static void ath_update_chainmask(struct ath_softc *sc, int is_ht)
 414 {
 415         sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
 416         if (is_ht ||
 417             (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)) {
 418                 sc->tx_chainmask = sc->sc_ah->caps.tx_chainmask;
 419                 sc->rx_chainmask = sc->sc_ah->caps.rx_chainmask;
 420         } else {
 421                 sc->tx_chainmask = 1;
 422                 sc->rx_chainmask = 1;
 423         }
 424
 425         DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
 426                 sc->tx_chainmask, sc->rx_chainmask);
 427 }
 428
 429 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
 430 {
 431         struct ath_node *an;
 432
 433         an = (struct ath_node *)sta->drv_priv;
 434
 435         if (sc->sc_flags & SC_OP_TXAGGR)
 436                 ath_tx_node_init(sc, an);
 437
 438         an->maxampdu = 1 << (IEEE80211_HTCAP_MAXRXAMPDU_FACTOR +
 439                              sta->ht_cap.ampdu_factor);
 440         an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
 441 }
 442
 443 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
 444 {
 445         struct ath_node *an = (struct ath_node *)sta->drv_priv;
 446
 447         if (sc->sc_flags & SC_OP_TXAGGR)
 448                 ath_tx_node_cleanup(sc, an);
 449 }
 450
 451 static void ath9k_tasklet(unsigned long data)
 452 {
 453         struct ath_softc *sc = (struct ath_softc *)data;
 454         u32 status = sc->intrstatus;
 455
 456         if (status & ATH9K_INT_FATAL) {
 457                 /* need a chip reset */
 458                 ath_reset(sc, false);
 459                 return;
 460         } else {
 461
 462                 if (status &
 463                     (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
 464                         spin_lock_bh(&sc->rx.rxflushlock);
 465                         ath_rx_tasklet(sc, 0);
 466                         spin_unlock_bh(&sc->rx.rxflushlock);
 467                 }
 468                 /* XXX: optimize this */
 469                 if (status & ATH9K_INT_TX)
 470                         ath_tx_tasklet(sc);
 471         }
 472
 473         /* re-enable hardware interrupt */
 474         ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
 475 }
 476
 477 irqreturn_t ath_isr(int irq, void *dev)
 478 {
 479         struct ath_softc *sc = dev;
 480         struct ath_hw *ah = sc->sc_ah;
 481         enum ath9k_int status;
 482         bool sched = false;
 483
 484         do {
 485                 if (sc->sc_flags & SC_OP_INVALID) {
 486                         /*
 487                          * The hardware is not ready/present, don't
 488                          * touch anything. Note this can happen early
 489                          * on if the IRQ is shared.
 490                          */
 491                         return IRQ_NONE;
 492                 }
 493                 if (!ath9k_hw_intrpend(ah)) {   /* shared irq, not for us */
 494                         return IRQ_NONE;
 495                 }
 496
 497                 /*
 498                  * Figure out the reason(s) for the interrupt.  Note
 499                  * that the hal returns a pseudo-ISR that may include
 500                  * bits we haven't explicitly enabled so we mask the
 501                  * value to insure we only process bits we requested.
 502                  */
 503                 ath9k_hw_getisr(ah, &status);   /* NB: clears ISR too */
 504
 505                 status &= sc->imask;    /* discard unasked-for bits */
 506
 507                 /*
 508                  * If there are no status bits set, then this interrupt was not
 509                  * for me (should have been caught above).
 510                  */
 511                 if (!status)
 512                         return IRQ_NONE;
 513
 514                 sc->intrstatus = status;
 515
 516                 if (status & ATH9K_INT_FATAL) {
 517                         /* need a chip reset */
 518                         sched = true;
 519                 } else if (status & ATH9K_INT_RXORN) {
 520                         /* need a chip reset */
 521                         sched = true;
 522                 } else {
 523                         if (status & ATH9K_INT_SWBA) {
 524                                 /* schedule a tasklet for beacon handling */
 525                                 tasklet_schedule(&sc->bcon_tasklet);
 526                         }
 527                         if (status & ATH9K_INT_RXEOL) {
 528                                 /*
 529                                  * NB: the hardware should re-read the link when
 530                                  *     RXE bit is written, but it doesn't work
 531                                  *     at least on older hardware revs.
 532                                  */
 533                                 sched = true;
 534                         }
 535
 536                         if (status & ATH9K_INT_TXURN)
 537                                 /* bump tx trigger level */
 538                                 ath9k_hw_updatetxtriglevel(ah, true);
 539                         /* XXX: optimize this */
 540                         if (status & ATH9K_INT_RX)
 541                                 sched = true;
 542                         if (status & ATH9K_INT_TX)
 543                                 sched = true;
 544                         if (status & ATH9K_INT_BMISS)
 545                                 sched = true;
 546                         /* carrier sense timeout */
 547                         if (status & ATH9K_INT_CST)
 548                                 sched = true;
 549                         if (status & ATH9K_INT_MIB) {
 550                                 /*
 551                                  * Disable interrupts until we service the MIB
 552                                  * interrupt; otherwise it will continue to
 553                                  * fire.
 554                                  */
 555                                 ath9k_hw_set_interrupts(ah, 0);
 556                                 /*
 557                                  * Let the hal handle the event. We assume
 558                                  * it will clear whatever condition caused
 559                                  * the interrupt.
 560                                  */
 561                                 ath9k_hw_procmibevent(ah, &sc->nodestats);
 562                                 ath9k_hw_set_interrupts(ah, sc->imask);
 563                         }
 564                         if (status & ATH9K_INT_TIM_TIMER) {
 565                                 if (!(ah->caps.hw_caps &
 566                                       ATH9K_HW_CAP_AUTOSLEEP)) {
 567                                         /* Clear RxAbort bit so that we can
 568                                          * receive frames */
 569                                         ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
 570                                         ath9k_hw_setrxabort(ah, 0);
 571                                         sched = true;
 572                                         sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
 573                                 }
 574                         }
 575                         if (status & ATH9K_INT_TSFOOR) {
 576                                 /* FIXME: Handle this interrupt for power save */
 577                                 sched = true;
 578                         }
 579                 }
 580         } while (0);
 581
 582         ath_debug_stat_interrupt(sc, status);
 583
 584         if (sched) {
 585                 /* turn off every interrupt except SWBA */
 586                 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
 587                 tasklet_schedule(&sc->intr_tq);
 588         }
 589
 590         return IRQ_HANDLED;
 591 }
 592
 593 static u32 ath_get_extchanmode(struct ath_softc *sc,
 594                                struct ieee80211_channel *chan,
 595                                enum nl80211_channel_type channel_type)
 596 {
 597         u32 chanmode = 0;
 598
 599         switch (chan->band) {
 600         case IEEE80211_BAND_2GHZ:
 601                 switch(channel_type) {
 602                 case NL80211_CHAN_NO_HT:
 603                 case NL80211_CHAN_HT20:
 604                         chanmode = CHANNEL_G_HT20;
 605                         break;
 606                 case NL80211_CHAN_HT40PLUS:
 607                         chanmode = CHANNEL_G_HT40PLUS;
 608                         break;
 609                 case NL80211_CHAN_HT40MINUS:
 610                         chanmode = CHANNEL_G_HT40MINUS;
 611                         break;
 612                 }
 613                 break;
 614         case IEEE80211_BAND_5GHZ:
 615                 switch(channel_type) {
 616                 case NL80211_CHAN_NO_HT:
 617                 case NL80211_CHAN_HT20:
 618                         chanmode = CHANNEL_A_HT20;
 619                         break;
 620                 case NL80211_CHAN_HT40PLUS:
 621                         chanmode = CHANNEL_A_HT40PLUS;
 622                         break;
 623                 case NL80211_CHAN_HT40MINUS:
 624                         chanmode = CHANNEL_A_HT40MINUS;
 625                         break;
 626                 }
 627                 break;
 628         default:
 629                 break;
 630         }
 631
 632         return chanmode;
 633 }
 634
 635 static int ath_keyset(struct ath_softc *sc, u16 keyix,
 636                struct ath9k_keyval *hk, const u8 mac[ETH_ALEN])
 637 {
 638         bool status;
 639
 640         status = ath9k_hw_set_keycache_entry(sc->sc_ah,
 641                 keyix, hk, mac, false);
 642
 643         return status != false;
 644 }
 645
 646 static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
 647                            struct ath9k_keyval *hk,
 648                            const u8 *addr)
 649 {
 650         const u8 *key_rxmic;
 651         const u8 *key_txmic;
 652
 653         key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
 654         key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
 655
 656         if (addr == NULL) {
 657                 /* Group key installation */
 658                 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 659                 return ath_keyset(sc, keyix, hk, addr);
 660         }
 661         if (!sc->splitmic) {
 662                 /*
 663                  * data key goes at first index,
 664                  * the hal handles the MIC keys at index+64.
 665                  */
 666                 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 667                 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
 668                 return ath_keyset(sc, keyix, hk, addr);
 669         }
 670         /*
 671          * TX key goes at first index, RX key at +32.
 672          * The hal handles the MIC keys at index+64.
 673          */
 674         memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
 675         if (!ath_keyset(sc, keyix, hk, NULL)) {
 676                 /* Txmic entry failed. No need to proceed further */
 677                 DPRINTF(sc, ATH_DBG_KEYCACHE,
 678                         "Setting TX MIC Key Failed\n");
 679                 return 0;
 680         }
 681
 682         memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
 683         /* XXX delete tx key on failure? */
 684         return ath_keyset(sc, keyix + 32, hk, addr);
 685 }
 686
 687 static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
 688 {
 689         int i;
 690
 691         for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
 692                 if (test_bit(i, sc->keymap) ||
 693                     test_bit(i + 64, sc->keymap))
 694                         continue; /* At least one part of TKIP key allocated */
 695                 if (sc->splitmic &&
 696                     (test_bit(i + 32, sc->keymap) ||
 697                      test_bit(i + 64 + 32, sc->keymap)))
 698                         continue; /* At least one part of TKIP key allocated */
 699
 700                 /* Found a free slot for a TKIP key */
 701                 return i;
 702         }
 703         return -1;
 704 }
 705
 706 static int ath_reserve_key_cache_slot(struct ath_softc *sc)
 707 {
 708         int i;
 709
 710         /* First, try to find slots that would not be available for TKIP. */
 711         if (sc->splitmic) {
 712                 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
 713                         if (!test_bit(i, sc->keymap) &&
 714                             (test_bit(i + 32, sc->keymap) ||
 715                              test_bit(i + 64, sc->keymap) ||
 716                              test_bit(i + 64 + 32, sc->keymap)))
 717                                 return i;
 718                         if (!test_bit(i + 32, sc->keymap) &&
 719                             (test_bit(i, sc->keymap) ||
 720                              test_bit(i + 64, sc->keymap) ||
 721                              test_bit(i + 64 + 32, sc->keymap)))
 722                                 return i + 32;
 723                         if (!test_bit(i + 64, sc->keymap) &&
 724                             (test_bit(i , sc->keymap) ||
 725                              test_bit(i + 32, sc->keymap) ||
 726                              test_bit(i + 64 + 32, sc->keymap)))
 727                                 return i + 64;
 728                         if (!test_bit(i + 64 + 32, sc->keymap) &&
 729                             (test_bit(i, sc->keymap) ||
 730                              test_bit(i + 32, sc->keymap) ||
 731                              test_bit(i + 64, sc->keymap)))
 732                                 return i + 64 + 32;
 733                 }
 734         } else {
 735                 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
 736                         if (!test_bit(i, sc->keymap) &&
 737                             test_bit(i + 64, sc->keymap))
 738                                 return i;
 739                         if (test_bit(i, sc->keymap) &&
 740                             !test_bit(i + 64, sc->keymap))
 741                                 return i + 64;
 742                 }
 743         }
 744
 745         /* No partially used TKIP slots, pick any available slot */
 746         for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
 747                 /* Do not allow slots that could be needed for TKIP group keys
 748                  * to be used. This limitation could be removed if we know that
 749                  * TKIP will not be used. */
 750                 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
 751                         continue;
 752                 if (sc->splitmic) {
 753                         if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
 754                                 continue;
 755                         if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
 756                                 continue;
 757                 }
 758
 759                 if (!test_bit(i, sc->keymap))
 760                         return i; /* Found a free slot for a key */
 761         }
 762
 763         /* No free slot found */
 764         return -1;
 765 }
 766
 767 static int ath_key_config(struct ath_softc *sc,
 768                           struct ieee80211_sta *sta,
 769                           struct ieee80211_key_conf *key)
 770 {
 771         struct ath9k_keyval hk;
 772         const u8 *mac = NULL;
 773         int ret = 0;
 774         int idx;
 775
 776         memset(&hk, 0, sizeof(hk));
 777
 778         switch (key->alg) {
 779         case ALG_WEP:
 780                 hk.kv_type = ATH9K_CIPHER_WEP;
 781                 break;
 782         case ALG_TKIP:
 783                 hk.kv_type = ATH9K_CIPHER_TKIP;
 784                 break;
 785         case ALG_CCMP:
 786                 hk.kv_type = ATH9K_CIPHER_AES_CCM;
 787                 break;
 788         default:
 789                 return -EOPNOTSUPP;
 790         }
 791
 792         hk.kv_len = key->keylen;
 793         memcpy(hk.kv_val, key->key, key->keylen);
 794
 795         if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
 796                 /* For now, use the default keys for broadcast keys. This may
 797                  * need to change with virtual interfaces. */
 798                 idx = key->keyidx;
 799         } else if (key->keyidx) {
 800                 struct ieee80211_vif *vif;
 801
 802                 if (WARN_ON(!sta))
 803                         return -EOPNOTSUPP;
 804                 mac = sta->addr;
 805
 806                 vif = sc->vifs[0];
 807                 if (vif->type != NL80211_IFTYPE_AP) {
 808                         /* Only keyidx 0 should be used with unicast key, but
 809                          * allow this for client mode for now. */
 810                         idx = key->keyidx;
 811                 } else
 812                         return -EIO;
 813         } else {
 814                 if (WARN_ON(!sta))
 815                         return -EOPNOTSUPP;
 816                 mac = sta->addr;
 817
 818                 if (key->alg == ALG_TKIP)
 819                         idx = ath_reserve_key_cache_slot_tkip(sc);
 820                 else
 821                         idx = ath_reserve_key_cache_slot(sc);
 822                 if (idx < 0)
 823                         return -ENOSPC; /* no free key cache entries */
 824         }
 825
 826         if (key->alg == ALG_TKIP)
 827                 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac);
 828         else
 829                 ret = ath_keyset(sc, idx, &hk, mac);
 830
 831         if (!ret)
 832                 return -EIO;
 833
 834         set_bit(idx, sc->keymap);
 835         if (key->alg == ALG_TKIP) {
 836                 set_bit(idx + 64, sc->keymap);
 837                 if (sc->splitmic) {
 838                         set_bit(idx + 32, sc->keymap);
 839                         set_bit(idx + 64 + 32, sc->keymap);
 840                 }
 841         }
 842
 843         return idx;
 844 }
 845
 846 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
 847 {
 848         ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
 849         if (key->hw_key_idx < IEEE80211_WEP_NKID)
 850                 return;
 851
 852         clear_bit(key->hw_key_idx, sc->keymap);
 853         if (key->alg != ALG_TKIP)
 854                 return;
 855
 856         clear_bit(key->hw_key_idx + 64, sc->keymap);
 857         if (sc->splitmic) {
 858                 clear_bit(key->hw_key_idx + 32, sc->keymap);
 859                 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
 860         }
 861 }
 862
 863 static void setup_ht_cap(struct ath_softc *sc,
 864                          struct ieee80211_sta_ht_cap *ht_info)
 865 {
 866 #define ATH9K_HT_CAP_MAXRXAMPDU_65536 0x3       /* 2 ^ 16 */
 867 #define ATH9K_HT_CAP_MPDUDENSITY_8 0x6          /* 8 usec */
 868
 869         ht_info->ht_supported = true;
 870         ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
 871                        IEEE80211_HT_CAP_SM_PS |
 872                        IEEE80211_HT_CAP_SGI_40 |
 873                        IEEE80211_HT_CAP_DSSSCCK40;
 874
 875         ht_info->ampdu_factor = ATH9K_HT_CAP_MAXRXAMPDU_65536;
 876         ht_info->ampdu_density = ATH9K_HT_CAP_MPDUDENSITY_8;
 877
 878         /* set up supported mcs set */
 879         memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
 880
 881         switch(sc->rx_chainmask) {
 882         case 1:
 883                 ht_info->mcs.rx_mask[0] = 0xff;
 884                 break;
 885         case 3:
 886         case 5:
 887         case 7:
 888         default:
 889                 ht_info->mcs.rx_mask[0] = 0xff;
 890                 ht_info->mcs.rx_mask[1] = 0xff;
 891                 break;
 892         }
 893
 894         ht_info->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
 895 }
 896
 897 static void ath9k_bss_assoc_info(struct ath_softc *sc,
 898                                  struct ieee80211_vif *vif,
 899                                  struct ieee80211_bss_conf *bss_conf)
 900 {
 901         struct ath_vif *avp = (void *)vif->drv_priv;
 902
 903         if (bss_conf->assoc) {
 904                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
 905                         bss_conf->aid, sc->curbssid);
 906
 907                 /* New association, store aid */
 908                 if (avp->av_opmode == NL80211_IFTYPE_STATION) {
 909                         sc->curaid = bss_conf->aid;
 910                         ath9k_hw_write_associd(sc);
 911                 }
 912
 913                 /* Configure the beacon */
 914                 ath_beacon_config(sc, 0);
 915                 sc->sc_flags |= SC_OP_BEACONS;
 916
 917                 /* Reset rssi stats */
 918                 sc->nodestats.ns_avgbrssi = ATH_RSSI_DUMMY_MARKER;
 919                 sc->nodestats.ns_avgrssi = ATH_RSSI_DUMMY_MARKER;
 920                 sc->nodestats.ns_avgtxrssi = ATH_RSSI_DUMMY_MARKER;
 921                 sc->nodestats.ns_avgtxrate = ATH_RATE_DUMMY_MARKER;
 922
 923                 /* Start ANI */
 924                 mod_timer(&sc->ani.timer,
 925                           jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
 926         } else {
 927                 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISSOC\n");
 928                 sc->curaid = 0;
 929         }
 930 }
 931
 932 /********************************/
 933 /*       LED functions          */
 934 /********************************/
 935
 936 static void ath_led_blink_work(struct work_struct *work)
 937 {
 938         struct ath_softc *sc = container_of(work, struct ath_softc,
 939                                             ath_led_blink_work.work);
 940
 941         if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
 942                 return;
 943         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
 944                           (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
 945
 946         queue_delayed_work(sc->hw->workqueue, &sc->ath_led_blink_work,
 947                            (sc->sc_flags & SC_OP_LED_ON) ?
 948                            msecs_to_jiffies(sc->led_off_duration) :
 949                            msecs_to_jiffies(sc->led_on_duration));
 950
 951         sc->led_on_duration =
 952                         max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25);
 953         sc->led_off_duration =
 954                         max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10);
 955         sc->led_on_cnt = sc->led_off_cnt = 0;
 956         if (sc->sc_flags & SC_OP_LED_ON)
 957                 sc->sc_flags &= ~SC_OP_LED_ON;
 958         else
 959                 sc->sc_flags |= SC_OP_LED_ON;
 960 }
 961
 962 static void ath_led_brightness(struct led_classdev *led_cdev,
 963                                enum led_brightness brightness)
 964 {
 965         struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
 966         struct ath_softc *sc = led->sc;
 967
 968         switch (brightness) {
 969         case LED_OFF:
 970                 if (led->led_type == ATH_LED_ASSOC ||
 971                     led->led_type == ATH_LED_RADIO) {
 972                         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN,
 973                                 (led->led_type == ATH_LED_RADIO));
 974                         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
 975                         if (led->led_type == ATH_LED_RADIO)
 976                                 sc->sc_flags &= ~SC_OP_LED_ON;
 977                 } else {
 978                         sc->led_off_cnt++;
 979                 }
 980                 break;
 981         case LED_FULL:
 982                 if (led->led_type == ATH_LED_ASSOC) {
 983                         sc->sc_flags |= SC_OP_LED_ASSOCIATED;
 984                         queue_delayed_work(sc->hw->workqueue,
 985                                            &sc->ath_led_blink_work, 0);
 986                 } else if (led->led_type == ATH_LED_RADIO) {
 987                         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 0);
 988                         sc->sc_flags |= SC_OP_LED_ON;
 989                 } else {
 990                         sc->led_on_cnt++;
 991                 }
 992                 break;
 993         default:
 994                 break;
 995         }
 996 }
 997
 998 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
 999                             char *trigger)
1000 {
1001         int ret;
1002
1003         led->sc = sc;
1004         led->led_cdev.name = led->name;
1005         led->led_cdev.default_trigger = trigger;
1006         led->led_cdev.brightness_set = ath_led_brightness;
1007
1008         ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1009         if (ret)
1010                 DPRINTF(sc, ATH_DBG_FATAL,
1011                         "Failed to register led:%s", led->name);
1012         else
1013                 led->registered = 1;
1014         return ret;
1015 }
1016
1017 static void ath_unregister_led(struct ath_led *led)
1018 {
1019         if (led->registered) {
1020                 led_classdev_unregister(&led->led_cdev);
1021                 led->registered = 0;
1022         }
1023 }
1024
1025 static void ath_deinit_leds(struct ath_softc *sc)
1026 {
1027         cancel_delayed_work_sync(&sc->ath_led_blink_work);
1028         ath_unregister_led(&sc->assoc_led);
1029         sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1030         ath_unregister_led(&sc->tx_led);
1031         ath_unregister_led(&sc->rx_led);
1032         ath_unregister_led(&sc->radio_led);
1033         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1034 }
1035
1036 static void ath_init_leds(struct ath_softc *sc)
1037 {
1038         char *trigger;
1039         int ret;
1040
1041         /* Configure gpio 1 for output */
1042         ath9k_hw_cfg_output(sc->sc_ah, ATH_LED_PIN,
1043                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1044         /* LED off, active low */
1045         ath9k_hw_set_gpio(sc->sc_ah, ATH_LED_PIN, 1);
1046
1047         INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1048
1049         trigger = ieee80211_get_radio_led_name(sc->hw);
1050         snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1051                 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
1052         ret = ath_register_led(sc, &sc->radio_led, trigger);
1053         sc->radio_led.led_type = ATH_LED_RADIO;
1054         if (ret)
1055                 goto fail;
1056
1057         trigger = ieee80211_get_assoc_led_name(sc->hw);
1058         snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1059                 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
1060         ret = ath_register_led(sc, &sc->assoc_led, trigger);
1061         sc->assoc_led.led_type = ATH_LED_ASSOC;
1062         if (ret)
1063                 goto fail;
1064
1065         trigger = ieee80211_get_tx_led_name(sc->hw);
1066         snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1067                 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
1068         ret = ath_register_led(sc, &sc->tx_led, trigger);
1069         sc->tx_led.led_type = ATH_LED_TX;
1070         if (ret)
1071                 goto fail;
1072
1073         trigger = ieee80211_get_rx_led_name(sc->hw);
1074         snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1075                 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
1076         ret = ath_register_led(sc, &sc->rx_led, trigger);
1077         sc->rx_led.led_type = ATH_LED_RX;
1078         if (ret)
1079                 goto fail;
1080
1081         return;
1082
1083 fail:
1084         ath_deinit_leds(sc);
1085 }
1086
1087 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1088
1089 /*******************/
1090 /*      Rfkill     */
1091 /*******************/
1092
1093 static void ath_radio_enable(struct ath_softc *sc)
1094 {
1095         struct ath_hw *ah = sc->sc_ah;
1096         struct ieee80211_channel *channel = sc->hw->conf.channel;
1097         int r;
1098
1099         ath9k_ps_wakeup(sc);
1100         spin_lock_bh(&sc->sc_resetlock);
1101
1102         r = ath9k_hw_reset(ah, ah->curchan, false);
1103
1104         if (r) {
1105                 DPRINTF(sc, ATH_DBG_FATAL,
1106                         "Unable to reset channel %u (%uMhz) ",
1107                         "reset status %u\n",
1108                         channel->center_freq, r);
1109         }
1110         spin_unlock_bh(&sc->sc_resetlock);
1111
1112         ath_update_txpow(sc);
1113         if (ath_startrecv(sc) != 0) {
1114                 DPRINTF(sc, ATH_DBG_FATAL,
1115                         "Unable to restart recv logic\n");
1116                 return;
1117         }
1118
1119         if (sc->sc_flags & SC_OP_BEACONS)
1120                 ath_beacon_config(sc, ATH_IF_ID_ANY);   /* restart beacons */
1121
1122         /* Re-Enable  interrupts */
1123         ath9k_hw_set_interrupts(ah, sc->imask);
1124
1125         /* Enable LED */
1126         ath9k_hw_cfg_output(ah, ATH_LED_PIN,
1127                             AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1128         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 0);
1129
1130         ieee80211_wake_queues(sc->hw);
1131         ath9k_ps_restore(sc);
1132 }
1133
1134 static void ath_radio_disable(struct ath_softc *sc)
1135 {
1136         struct ath_hw *ah = sc->sc_ah;
1137         struct ieee80211_channel *channel = sc->hw->conf.channel;
1138         int r;
1139
1140         ath9k_ps_wakeup(sc);
1141         ieee80211_stop_queues(sc->hw);
1142
1143         /* Disable LED */
1144         ath9k_hw_set_gpio(ah, ATH_LED_PIN, 1);
1145         ath9k_hw_cfg_gpio_input(ah, ATH_LED_PIN);
1146
1147         /* Disable interrupts */
1148         ath9k_hw_set_interrupts(ah, 0);
1149
1150         ath_drain_all_txq(sc, false);   /* clear pending tx frames */
1151         ath_stoprecv(sc);               /* turn off frame recv */
1152         ath_flushrecv(sc);              /* flush recv queue */
1153
1154         spin_lock_bh(&sc->sc_resetlock);
1155         r = ath9k_hw_reset(ah, ah->curchan, false);
1156         if (r) {
1157                 DPRINTF(sc, ATH_DBG_FATAL,
1158                         "Unable to reset channel %u (%uMhz) "
1159                         "reset status %u\n",
1160                         channel->center_freq, r);
1161         }
1162         spin_unlock_bh(&sc->sc_resetlock);
1163
1164         ath9k_hw_phy_disable(ah);
1165         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1166         ath9k_ps_restore(sc);
1167 }
1168
1169 static bool ath_is_rfkill_set(struct ath_softc *sc)
1170 {
1171         struct ath_hw *ah = sc->sc_ah;
1172
1173         return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1174                                   ah->rfkill_polarity;
1175 }
1176
1177 /* h/w rfkill poll function */
1178 static void ath_rfkill_poll(struct work_struct *work)
1179 {
1180         struct ath_softc *sc = container_of(work, struct ath_softc,
1181                                             rf_kill.rfkill_poll.work);
1182         bool radio_on;
1183
1184         if (sc->sc_flags & SC_OP_INVALID)
1185                 return;
1186
1187         radio_on = !ath_is_rfkill_set(sc);
1188
1189         /*
1190          * enable/disable radio only when there is a
1191          * state change in RF switch
1192          */
1193         if (radio_on == !!(sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED)) {
1194                 enum rfkill_state state;
1195
1196                 if (sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED) {
1197                         state = radio_on ? RFKILL_STATE_SOFT_BLOCKED
1198                                 : RFKILL_STATE_HARD_BLOCKED;
1199                 } else if (radio_on) {
1200                         ath_radio_enable(sc);
1201                         state = RFKILL_STATE_UNBLOCKED;
1202                 } else {
1203                         ath_radio_disable(sc);
1204                         state = RFKILL_STATE_HARD_BLOCKED;
1205                 }
1206
1207                 if (state == RFKILL_STATE_HARD_BLOCKED)
1208                         sc->sc_flags |= SC_OP_RFKILL_HW_BLOCKED;
1209                 else
1210                         sc->sc_flags &= ~SC_OP_RFKILL_HW_BLOCKED;
1211
1212                 rfkill_force_state(sc->rf_kill.rfkill, state);
1213         }
1214
1215         queue_delayed_work(sc->hw->workqueue, &sc->rf_kill.rfkill_poll,
1216                            msecs_to_jiffies(ATH_RFKILL_POLL_INTERVAL));
1217 }
1218
1219 /* s/w rfkill handler */
1220 static int ath_sw_toggle_radio(void *data, enum rfkill_state state)
1221 {
1222         struct ath_softc *sc = data;
1223
1224         switch (state) {
1225         case RFKILL_STATE_SOFT_BLOCKED:
1226                 if (!(sc->sc_flags & (SC_OP_RFKILL_HW_BLOCKED |
1227                     SC_OP_RFKILL_SW_BLOCKED)))
1228                         ath_radio_disable(sc);
1229                 sc->sc_flags |= SC_OP_RFKILL_SW_BLOCKED;
1230                 return 0;
1231         case RFKILL_STATE_UNBLOCKED:
1232                 if ((sc->sc_flags & SC_OP_RFKILL_SW_BLOCKED)) {
1233                         sc->sc_flags &= ~SC_OP_RFKILL_SW_BLOCKED;
1234                         if (sc->sc_flags & SC_OP_RFKILL_HW_BLOCKED) {
1235                                 DPRINTF(sc, ATH_DBG_FATAL, "Can't turn on the"
1236                                         "radio as it is disabled by h/w\n");
1237                                 return -EPERM;
1238                         }
1239                         ath_radio_enable(sc);
1240                 }
1241                 return 0;
1242         default:
1243                 return -EINVAL;
1244         }
1245 }
1246
1247 /* Init s/w rfkill */
1248 static int ath_init_sw_rfkill(struct ath_softc *sc)
1249 {
1250         sc->rf_kill.rfkill = rfkill_allocate(wiphy_dev(sc->hw->wiphy),
1251                                              RFKILL_TYPE_WLAN);
1252         if (!sc->rf_kill.rfkill) {
1253                 DPRINTF(sc, ATH_DBG_FATAL, "Failed to allocate rfkill\n");
1254                 return -ENOMEM;
1255         }
1256
1257         snprintf(sc->rf_kill.rfkill_name, sizeof(sc->rf_kill.rfkill_name),
1258                 "ath9k-%s::rfkill", wiphy_name(sc->hw->wiphy));
1259         sc->rf_kill.rfkill->name = sc->rf_kill.rfkill_name;
1260         sc->rf_kill.rfkill->data = sc;
1261         sc->rf_kill.rfkill->toggle_radio = ath_sw_toggle_radio;
1262         sc->rf_kill.rfkill->state = RFKILL_STATE_UNBLOCKED;
1263         sc->rf_kill.rfkill->user_claim_unsupported = 1;
1264
1265         return 0;
1266 }
1267
1268 /* Deinitialize rfkill */
1269 static void ath_deinit_rfkill(struct ath_softc *sc)
1270 {
1271         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1272                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
1273
1274         if (sc->sc_flags & SC_OP_RFKILL_REGISTERED) {
1275                 rfkill_unregister(sc->rf_kill.rfkill);
1276                 sc->sc_flags &= ~SC_OP_RFKILL_REGISTERED;
1277                 sc->rf_kill.rfkill = NULL;
1278         }
1279 }
1280
1281 static int ath_start_rfkill_poll(struct ath_softc *sc)
1282 {
1283         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1284                 queue_delayed_work(sc->hw->workqueue,
1285                                    &sc->rf_kill.rfkill_poll, 0);
1286
1287         if (!(sc->sc_flags & SC_OP_RFKILL_REGISTERED)) {
1288                 if (rfkill_register(sc->rf_kill.rfkill)) {
1289                         DPRINTF(sc, ATH_DBG_FATAL,
1290                                 "Unable to register rfkill\n");
1291                         rfkill_free(sc->rf_kill.rfkill);
1292
1293                         /* Deinitialize the device */
1294                         ath_cleanup(sc);
1295                         return -EIO;
1296                 } else {
1297                         sc->sc_flags |= SC_OP_RFKILL_REGISTERED;
1298                 }
1299         }
1300
1301         return 0;
1302 }
1303 #endif /* CONFIG_RFKILL */
1304
1305 void ath_cleanup(struct ath_softc *sc)
1306 {
1307         ath_detach(sc);
1308         free_irq(sc->irq, sc);
1309         ath_bus_cleanup(sc);
1310         ieee80211_free_hw(sc->hw);
1311 }
1312
1313 void ath_detach(struct ath_softc *sc)
1314 {
1315         struct ieee80211_hw *hw = sc->hw;
1316         int i = 0;
1317
1318         ath9k_ps_wakeup(sc);
1319
1320         DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n");
1321
1322 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1323         ath_deinit_rfkill(sc);
1324 #endif
1325         ath_deinit_leds(sc);
1326
1327         ieee80211_unregister_hw(hw);
1328         ath_rx_cleanup(sc);
1329         ath_tx_cleanup(sc);
1330
1331         tasklet_kill(&sc->intr_tq);
1332         tasklet_kill(&sc->bcon_tasklet);
1333
1334         if (!(sc->sc_flags & SC_OP_INVALID))
1335                 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1336
1337         /* cleanup tx queues */
1338         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1339                 if (ATH_TXQ_SETUP(sc, i))
1340                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1341
1342         ath9k_hw_detach(sc->sc_ah);
1343         ath9k_exit_debug(sc);
1344         ath9k_ps_restore(sc);
1345 }
1346
1347 static int ath_init(u16 devid, struct ath_softc *sc)
1348 {
1349         struct ath_hw *ah = NULL;
1350         int status;
1351         int error = 0, i;
1352         int csz = 0;
1353
1354         /* XXX: hardware will not be ready until ath_open() being called */
1355         sc->sc_flags |= SC_OP_INVALID;
1356
1357         if (ath9k_init_debug(sc) < 0)
1358                 printk(KERN_ERR "Unable to create debugfs files\n");
1359
1360         spin_lock_init(&sc->sc_resetlock);
1361         mutex_init(&sc->mutex);
1362         tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1363         tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
1364                      (unsigned long)sc);
1365
1366         /*
1367          * Cache line size is used to size and align various
1368          * structures used to communicate with the hardware.
1369          */
1370         ath_read_cachesize(sc, &csz);
1371         /* XXX assert csz is non-zero */
1372         sc->cachelsz = csz << 2;        /* convert to bytes */
1373
1374         ah = ath9k_hw_attach(devid, sc, &status);
1375         if (ah == NULL) {
1376                 DPRINTF(sc, ATH_DBG_FATAL,
1377                         "Unable to attach hardware; HAL status %d\n", status);
1378                 error = -ENXIO;
1379                 goto bad;
1380         }
1381         sc->sc_ah = ah;
1382
1383         /* Get the hardware key cache size. */
1384         sc->keymax = ah->caps.keycache_size;
1385         if (sc->keymax > ATH_KEYMAX) {
1386                 DPRINTF(sc, ATH_DBG_KEYCACHE,
1387                         "Warning, using only %u entries in %u key cache\n",
1388                         ATH_KEYMAX, sc->keymax);
1389                 sc->keymax = ATH_KEYMAX;
1390         }
1391
1392         /*
1393          * Reset the key cache since some parts do not
1394          * reset the contents on initial power up.
1395          */
1396         for (i = 0; i < sc->keymax; i++)
1397                 ath9k_hw_keyreset(ah, (u16) i);
1398
1399         if (ath9k_regd_init(sc->sc_ah))
1400                 goto bad;
1401
1402         /* default to MONITOR mode */
1403         sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1404
1405         /* Setup rate tables */
1406
1407         ath_rate_attach(sc);
1408         ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1409         ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1410
1411         /*
1412          * Allocate hardware transmit queues: one queue for
1413          * beacon frames and one data queue for each QoS
1414          * priority.  Note that the hal handles reseting
1415          * these queues at the needed time.
1416          */
1417         sc->beacon.beaconq = ath_beaconq_setup(ah);
1418         if (sc->beacon.beaconq == -1) {
1419                 DPRINTF(sc, ATH_DBG_FATAL,
1420                         "Unable to setup a beacon xmit queue\n");
1421                 error = -EIO;
1422                 goto bad2;
1423         }
1424         sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1425         if (sc->beacon.cabq == NULL) {
1426                 DPRINTF(sc, ATH_DBG_FATAL,
1427                         "Unable to setup CAB xmit queue\n");
1428                 error = -EIO;
1429                 goto bad2;
1430         }
1431
1432         sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
1433         ath_cabq_update(sc);
1434
1435         for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1436                 sc->tx.hwq_map[i] = -1;
1437
1438         /* Setup data queues */
1439         /* NB: ensure BK queue is the lowest priority h/w queue */
1440         if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1441                 DPRINTF(sc, ATH_DBG_FATAL,
1442                         "Unable to setup xmit queue for BK traffic\n");
1443                 error = -EIO;
1444                 goto bad2;
1445         }
1446
1447         if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1448                 DPRINTF(sc, ATH_DBG_FATAL,
1449                         "Unable to setup xmit queue for BE traffic\n");
1450                 error = -EIO;
1451                 goto bad2;
1452         }
1453         if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1454                 DPRINTF(sc, ATH_DBG_FATAL,
1455                         "Unable to setup xmit queue for VI traffic\n");
1456                 error = -EIO;
1457                 goto bad2;
1458         }
1459         if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1460                 DPRINTF(sc, ATH_DBG_FATAL,
1461                         "Unable to setup xmit queue for VO traffic\n");
1462                 error = -EIO;
1463                 goto bad2;
1464         }
1465
1466         /* Initializes the noise floor to a reasonable default value.
1467          * Later on this will be updated during ANI processing. */
1468
1469         sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1470         setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
1471
1472         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1473                                    ATH9K_CIPHER_TKIP, NULL)) {
1474                 /*
1475                  * Whether we should enable h/w TKIP MIC.
1476                  * XXX: if we don't support WME TKIP MIC, then we wouldn't
1477                  * report WMM capable, so it's always safe to turn on
1478                  * TKIP MIC in this case.
1479                  */
1480                 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1481                                        0, 1, NULL);
1482         }
1483
1484         /*
1485          * Check whether the separate key cache entries
1486          * are required to handle both tx+rx MIC keys.
1487          * With split mic keys the number of stations is limited
1488          * to 27 otherwise 59.
1489          */
1490         if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1491                                    ATH9K_CIPHER_TKIP, NULL)
1492             && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1493                                       ATH9K_CIPHER_MIC, NULL)
1494             && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1495                                       0, NULL))
1496                 sc->splitmic = 1;
1497
1498         /* turn on mcast key search if possible */
1499         if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1500                 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1501                                              1, NULL);
1502
1503         sc->config.txpowlimit = ATH_TXPOWER_MAX;
1504
1505         /* 11n Capabilities */
1506         if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1507                 sc->sc_flags |= SC_OP_TXAGGR;
1508                 sc->sc_flags |= SC_OP_RXAGGR;
1509         }
1510
1511         sc->tx_chainmask = ah->caps.tx_chainmask;
1512         sc->rx_chainmask = ah->caps.rx_chainmask;
1513
1514         ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1515         sc->rx.defant = ath9k_hw_getdefantenna(ah);
1516
1517         if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
1518                 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
1519                 ATH_SET_VIF_BSSID_MASK(sc->bssidmask);
1520                 ath9k_hw_setbssidmask(sc);
1521         }
1522
1523         sc->beacon.slottime = ATH9K_SLOT_TIME_9;        /* default to short slot time */
1524
1525         /* initialize beacon slots */
1526         for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
1527                 sc->beacon.bslot[i] = ATH_IF_ID_ANY;
1528
1529         /* save MISC configurations */
1530         sc->config.swBeaconProcess = 1;
1531
1532         /* setup channels and rates */
1533
1534         sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
1535         sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1536                 sc->rates[IEEE80211_BAND_2GHZ];
1537         sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1538         sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1539                 ARRAY_SIZE(ath9k_2ghz_chantable);
1540
1541         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
1542                 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
1543                 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1544                         sc->rates[IEEE80211_BAND_5GHZ];
1545                 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1546                 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1547                         ARRAY_SIZE(ath9k_5ghz_chantable);
1548         }
1549
1550         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BT_COEX)
1551                 ath9k_hw_btcoex_enable(sc->sc_ah);
1552
1553         return 0;
1554 bad2:
1555         /* cleanup tx queues */
1556         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1557                 if (ATH_TXQ_SETUP(sc, i))
1558                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1559 bad:
1560         if (ah)
1561                 ath9k_hw_detach(ah);
1562         ath9k_exit_debug(sc);
1563
1564         return error;
1565 }
1566
1567 int ath_attach(u16 devid, struct ath_softc *sc)
1568 {
1569         struct ieee80211_hw *hw = sc->hw;
1570         const struct ieee80211_regdomain *regd;
1571         int error = 0, i;
1572
1573         DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n");
1574
1575         error = ath_init(devid, sc);
1576         if (error != 0)
1577                 return error;
1578
1579         /* get mac address from hardware and set in mac80211 */
1580
1581         SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr);
1582
1583         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1584                 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1585                 IEEE80211_HW_SIGNAL_DBM |
1586                 IEEE80211_HW_AMPDU_AGGREGATION |
1587                 IEEE80211_HW_SUPPORTS_PS |
1588                 IEEE80211_HW_PS_NULLFUNC_STACK;
1589
1590         if (AR_SREV_9160_10_OR_LATER(sc->sc_ah))
1591                 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1592
1593         hw->wiphy->interface_modes =
1594                 BIT(NL80211_IFTYPE_AP) |
1595                 BIT(NL80211_IFTYPE_STATION) |
1596                 BIT(NL80211_IFTYPE_ADHOC);
1597
1598         hw->wiphy->reg_notifier = ath9k_reg_notifier;
1599         hw->wiphy->strict_regulatory = true;
1600
1601         hw->queues = 4;
1602         hw->max_rates = 4;
1603         hw->channel_change_time = 5000;
1604         hw->max_rate_tries = ATH_11N_TXMAXTRY;
1605         hw->sta_data_size = sizeof(struct ath_node);
1606         hw->vif_data_size = sizeof(struct ath_vif);
1607
1608         hw->rate_control_algorithm = "ath9k_rate_control";
1609
1610         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1611                 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1612                 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1613                         setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1614         }
1615
1616         hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &sc->sbands[IEEE80211_BAND_2GHZ];
1617         if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1618                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1619                         &sc->sbands[IEEE80211_BAND_5GHZ];
1620
1621         /* initialize tx/rx engine */
1622         error = ath_tx_init(sc, ATH_TXBUF);
1623         if (error != 0)
1624                 goto error_attach;
1625
1626         error = ath_rx_init(sc, ATH_RXBUF);
1627         if (error != 0)
1628                 goto error_attach;
1629
1630 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
1631         /* Initialze h/w Rfkill */
1632         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1633                 INIT_DELAYED_WORK(&sc->rf_kill.rfkill_poll, ath_rfkill_poll);
1634
1635         /* Initialize s/w rfkill */
1636         error = ath_init_sw_rfkill(sc);
1637         if (error)
1638                 goto error_attach;
1639 #endif
1640
1641         if (ath9k_is_world_regd(sc->sc_ah)) {
1642                 /* Anything applied here (prior to wiphy registration) gets
1643                  * saved on the wiphy orig_* parameters */
1644                 regd = ath9k_world_regdomain(sc->sc_ah);
1645                 hw->wiphy->custom_regulatory = true;
1646                 hw->wiphy->strict_regulatory = false;
1647         } else {
1648                 /* This gets applied in the case of the absense of CRDA,
1649                  * it's our own custom world regulatory domain, similar to
1650                  * cfg80211's but we enable passive scanning */
1651                 regd = ath9k_default_world_regdomain();
1652         }
1653         wiphy_apply_custom_regulatory(hw->wiphy, regd);
1654         ath9k_reg_apply_radar_flags(hw->wiphy);
1655         ath9k_reg_apply_world_flags(hw->wiphy, REGDOM_SET_BY_INIT);
1656
1657         error = ieee80211_register_hw(hw);
1658
1659         if (!ath9k_is_world_regd(sc->sc_ah)) {
1660                 error = regulatory_hint(hw->wiphy,
1661                         sc->sc_ah->regulatory.alpha2);
1662                 if (error)
1663                         goto error_attach;
1664         }
1665
1666         /* Initialize LED control */
1667         ath_init_leds(sc);
1668
1669
1670         return 0;
1671
1672 error_attach:
1673         /* cleanup tx queues */
1674         for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1675                 if (ATH_TXQ_SETUP(sc, i))
1676                         ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1677
1678         ath9k_hw_detach(sc->sc_ah);
1679         ath9k_exit_debug(sc);
1680
1681         return error;
1682 }
1683
1684 int ath_reset(struct ath_softc *sc, bool retry_tx)
1685 {
1686         struct ath_hw *ah = sc->sc_ah;
1687         struct ieee80211_hw *hw = sc->hw;
1688         int r;
1689
1690         ath9k_hw_set_interrupts(ah, 0);
1691         ath_drain_all_txq(sc, retry_tx);
1692         ath_stoprecv(sc);
1693         ath_flushrecv(sc);
1694
1695         spin_lock_bh(&sc->sc_resetlock);
1696         r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1697         if (r)
1698                 DPRINTF(sc, ATH_DBG_FATAL,
1699                         "Unable to reset hardware; reset status %u\n", r);
1700         spin_unlock_bh(&sc->sc_resetlock);
1701
1702         if (ath_startrecv(sc) != 0)
1703                 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n");
1704
1705         /*
1706          * We may be doing a reset in response to a request
1707          * that changes the channel so update any state that
1708          * might change as a result.
1709          */
1710         ath_cache_conf_rate(sc, &hw->conf);
1711
1712         ath_update_txpow(sc);
1713
1714         if (sc->sc_flags & SC_OP_BEACONS)
1715                 ath_beacon_config(sc, ATH_IF_ID_ANY);   /* restart beacons */
1716
1717         ath9k_hw_set_interrupts(ah, sc->imask);
1718
1719         if (retry_tx) {
1720                 int i;
1721                 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1722                         if (ATH_TXQ_SETUP(sc, i)) {
1723                                 spin_lock_bh(&sc->tx.txq[i].axq_lock);
1724                                 ath_txq_schedule(sc, &sc->tx.txq[i]);
1725                                 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
1726                         }
1727                 }
1728         }
1729
1730         return r;
1731 }
1732
1733 /*
1734  *  This function will allocate both the DMA descriptor structure, and the
1735  *  buffers it contains.  These are used to contain the descriptors used
1736  *  by the system.
1737 */
1738 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1739                       struct list_head *head, const char *name,
1740                       int nbuf, int ndesc)
1741 {
1742 #define DS2PHYS(_dd, _ds)                                               \
1743         ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1744 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1745 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1746
1747         struct ath_desc *ds;
1748         struct ath_buf *bf;
1749         int i, bsize, error;
1750
1751         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1752                 name, nbuf, ndesc);
1753
1754         /* ath_desc must be a multiple of DWORDs */
1755         if ((sizeof(struct ath_desc) % 4) != 0) {
1756                 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1757                 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1758                 error = -ENOMEM;
1759                 goto fail;
1760         }
1761
1762         dd->dd_name = name;
1763         dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1764
1765         /*
1766          * Need additional DMA memory because we can't use
1767          * descriptors that cross the 4K page boundary. Assume
1768          * one skipped descriptor per 4K page.
1769          */
1770         if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1771                 u32 ndesc_skipped =
1772                         ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1773                 u32 dma_len;
1774
1775                 while (ndesc_skipped) {
1776                         dma_len = ndesc_skipped * sizeof(struct ath_desc);
1777                         dd->dd_desc_len += dma_len;
1778
1779                         ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1780                 };
1781         }
1782
1783         /* allocate descriptors */
1784         dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
1785                                          &dd->dd_desc_paddr, GFP_ATOMIC);
1786         if (dd->dd_desc == NULL) {
1787                 error = -ENOMEM;
1788                 goto fail;
1789         }
1790         ds = dd->dd_desc;
1791         DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1792                 dd->dd_name, ds, (u32) dd->dd_desc_len,
1793                 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1794
1795         /* allocate buffers */
1796         bsize = sizeof(struct ath_buf) * nbuf;
1797         bf = kmalloc(bsize, GFP_KERNEL);
1798         if (bf == NULL) {
1799                 error = -ENOMEM;
1800                 goto fail2;
1801         }
1802         memset(bf, 0, bsize);
1803         dd->dd_bufptr = bf;
1804
1805         INIT_LIST_HEAD(head);
1806         for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1807                 bf->bf_desc = ds;
1808                 bf->bf_daddr = DS2PHYS(dd, ds);
1809
1810                 if (!(sc->sc_ah->caps.hw_caps &
1811                       ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1812                         /*
1813                          * Skip descriptor addresses which can cause 4KB
1814                          * boundary crossing (addr + length) with a 32 dword
1815                          * descriptor fetch.
1816                          */
1817                         while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1818                                 ASSERT((caddr_t) bf->bf_desc <
1819                                        ((caddr_t) dd->dd_desc +
1820                                         dd->dd_desc_len));
1821
1822                                 ds += ndesc;
1823                                 bf->bf_desc = ds;
1824                                 bf->bf_daddr = DS2PHYS(dd, ds);
1825                         }
1826                 }
1827                 list_add_tail(&bf->list, head);
1828         }
1829         return 0;
1830 fail2:
1831         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1832                           dd->dd_desc_paddr);
1833 fail:
1834         memset(dd, 0, sizeof(*dd));
1835         return error;
1836 #undef ATH_DESC_4KB_BOUND_CHECK
1837 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1838 #undef DS2PHYS
1839 }
1840
1841 void ath_descdma_cleanup(struct ath_softc *sc,
1842                          struct ath_descdma *dd,
1843                          struct list_head *head)
1844 {
1845         dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
1846                           dd->dd_desc_paddr);
1847
1848         INIT_LIST_HEAD(head);
1849         kfree(dd->dd_bufptr);
1850         memset(dd, 0, sizeof(*dd));
1851 }
1852
1853 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1854 {
1855         int qnum;
1856
1857         switch (queue) {
1858         case 0:
1859                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
1860                 break;
1861         case 1:
1862                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
1863                 break;
1864         case 2:
1865                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1866                 break;
1867         case 3:
1868                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
1869                 break;
1870         default:
1871                 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
1872                 break;
1873         }
1874
1875         return qnum;
1876 }
1877
1878 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1879 {
1880         int qnum;
1881
1882         switch (queue) {
1883         case ATH9K_WME_AC_VO:
1884                 qnum = 0;
1885                 break;
1886         case ATH9K_WME_AC_VI:
1887                 qnum = 1;
1888                 break;
1889         case ATH9K_WME_AC_BE:
1890                 qnum = 2;
1891                 break;
1892         case ATH9K_WME_AC_BK:
1893                 qnum = 3;
1894                 break;
1895         default:
1896                 qnum = -1;
1897                 break;
1898         }
1899
1900         return qnum;
1901 }
1902
1903 /* XXX: Remove me once we don't depend on ath9k_channel for all
1904  * this redundant data */
1905 static void ath9k_update_ichannel(struct ath_softc *sc,
1906                           struct ath9k_channel *ichan)
1907 {
1908         struct ieee80211_hw *hw = sc->hw;
1909         struct ieee80211_channel *chan = hw->conf.channel;
1910         struct ieee80211_conf *conf = &hw->conf;
1911
1912         ichan->channel = chan->center_freq;
1913         ichan->chan = chan;
1914
1915         if (chan->band == IEEE80211_BAND_2GHZ) {
1916                 ichan->chanmode = CHANNEL_G;
1917                 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM;
1918         } else {
1919                 ichan->chanmode = CHANNEL_A;
1920                 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
1921         }
1922
1923         sc->tx_chan_width = ATH9K_HT_MACMODE_20;
1924
1925         if (conf_is_ht(conf)) {
1926                 if (conf_is_ht40(conf))
1927                         sc->tx_chan_width = ATH9K_HT_MACMODE_2040;
1928
1929                 ichan->chanmode = ath_get_extchanmode(sc, chan,
1930                                             conf->channel_type);
1931         }
1932 }
1933
1934 /**********************/
1935 /* mac80211 callbacks */
1936 /**********************/
1937
1938 static int ath9k_start(struct ieee80211_hw *hw)
1939 {
1940         struct ath_softc *sc = hw->priv;
1941         struct ieee80211_channel *curchan = hw->conf.channel;
1942         struct ath9k_channel *init_channel;
1943         int r, pos;
1944
1945         DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with "
1946                 "initial channel: %d MHz\n", curchan->center_freq);
1947
1948         mutex_lock(&sc->mutex);
1949
1950         /* setup initial channel */
1951
1952         pos = curchan->hw_value;
1953
1954         init_channel = &sc->sc_ah->channels[pos];
1955         ath9k_update_ichannel(sc, init_channel);
1956
1957         /* Reset SERDES registers */
1958         ath9k_hw_configpcipowersave(sc->sc_ah, 0);
1959
1960         /*
1961          * The basic interface to setting the hardware in a good
1962          * state is ``reset''.  On return the hardware is known to
1963          * be powered up and with interrupts disabled.  This must
1964          * be followed by initialization of the appropriate bits
1965          * and then setup of the interrupt mask.
1966          */
1967         spin_lock_bh(&sc->sc_resetlock);
1968         r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1969         if (r) {
1970                 DPRINTF(sc, ATH_DBG_FATAL,
1971                         "Unable to reset hardware; reset status %u "
1972                         "(freq %u MHz)\n", r,
1973                         curchan->center_freq);
1974                 spin_unlock_bh(&sc->sc_resetlock);
1975                 goto mutex_unlock;
1976         }
1977         spin_unlock_bh(&sc->sc_resetlock);
1978
1979         /*
1980          * This is needed only to setup initial state
1981          * but it's best done after a reset.
1982          */
1983         ath_update_txpow(sc);
1984
1985         /*
1986          * Setup the hardware after reset:
1987          * The receive engine is set going.
1988          * Frame transmit is handled entirely
1989          * in the frame output path; there's nothing to do
1990          * here except setup the interrupt mask.
1991          */
1992         if (ath_startrecv(sc) != 0) {
1993                 DPRINTF(sc, ATH_DBG_FATAL,
1994                         "Unable to start recv logic\n");
1995                 r = -EIO;
1996                 goto mutex_unlock;
1997         }
1998
1999         /* Setup our intr mask. */
2000         sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
2001                 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2002                 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2003
2004         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
2005                 sc->imask |= ATH9K_INT_GTT;
2006
2007         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT)
2008                 sc->imask |= ATH9K_INT_CST;
2009
2010         ath_cache_conf_rate(sc, &hw->conf);
2011
2012         sc->sc_flags &= ~SC_OP_INVALID;
2013
2014         /* Disable BMISS interrupt when we're not associated */
2015         sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2016         ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2017
2018         ieee80211_wake_queues(sc->hw);
2019
2020 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2021         r = ath_start_rfkill_poll(sc);
2022 #endif
2023
2024 mutex_unlock:
2025         mutex_unlock(&sc->mutex);
2026
2027         return r;
2028 }
2029
2030 static int ath9k_tx(struct ieee80211_hw *hw,
2031                     struct sk_buff *skb)
2032 {
2033         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2034         struct ath_softc *sc = hw->priv;
2035         struct ath_tx_control txctl;
2036         int hdrlen, padsize;
2037
2038         memset(&txctl, 0, sizeof(struct ath_tx_control));
2039
2040         /*
2041          * As a temporary workaround, assign seq# here; this will likely need
2042          * to be cleaned up to work better with Beacon transmission and virtual
2043          * BSSes.
2044          */
2045         if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2046                 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2047                 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2048                         sc->tx.seq_no += 0x10;
2049                 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2050                 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2051         }
2052
2053         /* Add the padding after the header if this is not already done */
2054         hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2055         if (hdrlen & 3) {
2056                 padsize = hdrlen % 4;
2057                 if (skb_headroom(skb) < padsize)
2058                         return -1;
2059                 skb_push(skb, padsize);
2060                 memmove(skb->data, skb->data + padsize, hdrlen);
2061         }
2062
2063         /* Check if a tx queue is available */
2064
2065         txctl.txq = ath_test_get_txq(sc, skb);
2066         if (!txctl.txq)
2067                 goto exit;
2068
2069         DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2070
2071         if (ath_tx_start(sc, skb, &txctl) != 0) {
2072                 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n");
2073                 goto exit;
2074         }
2075
2076         return 0;
2077 exit:
2078         dev_kfree_skb_any(skb);
2079         return 0;
2080 }
2081
2082 static void ath9k_stop(struct ieee80211_hw *hw)
2083 {
2084         struct ath_softc *sc = hw->priv;
2085
2086         if (sc->sc_flags & SC_OP_INVALID) {
2087                 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n");
2088                 return;
2089         }
2090
2091         mutex_lock(&sc->mutex);
2092
2093         ieee80211_stop_queues(sc->hw);
2094
2095         /* make sure h/w will not generate any interrupt
2096          * before setting the invalid flag. */
2097         ath9k_hw_set_interrupts(sc->sc_ah, 0);
2098
2099         if (!(sc->sc_flags & SC_OP_INVALID)) {
2100                 ath_drain_all_txq(sc, false);
2101                 ath_stoprecv(sc);
2102                 ath9k_hw_phy_disable(sc->sc_ah);
2103         } else
2104                 sc->rx.rxlink = NULL;
2105
2106 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2107         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2108                 cancel_delayed_work_sync(&sc->rf_kill.rfkill_poll);
2109 #endif
2110         /* disable HAL and put h/w to sleep */
2111         ath9k_hw_disable(sc->sc_ah);
2112         ath9k_hw_configpcipowersave(sc->sc_ah, 1);
2113
2114         sc->sc_flags |= SC_OP_INVALID;
2115
2116         mutex_unlock(&sc->mutex);
2117
2118         DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n");
2119 }
2120
2121 static int ath9k_add_interface(struct ieee80211_hw *hw,
2122                                struct ieee80211_if_init_conf *conf)
2123 {
2124         struct ath_softc *sc = hw->priv;
2125         struct ath_vif *avp = (void *)conf->vif->drv_priv;
2126         enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2127
2128         /* Support only vif for now */
2129
2130         if (sc->nvifs)
2131                 return -ENOBUFS;
2132
2133         mutex_lock(&sc->mutex);
2134
2135         switch (conf->type) {
2136         case NL80211_IFTYPE_STATION:
2137                 ic_opmode = NL80211_IFTYPE_STATION;
2138                 break;
2139         case NL80211_IFTYPE_ADHOC:
2140                 ic_opmode = NL80211_IFTYPE_ADHOC;
2141                 break;
2142         case NL80211_IFTYPE_AP:
2143                 ic_opmode = NL80211_IFTYPE_AP;
2144                 break;
2145         default:
2146                 DPRINTF(sc, ATH_DBG_FATAL,
2147                         "Interface type %d not yet supported\n", conf->type);
2148                 return -EOPNOTSUPP;
2149         }
2150
2151         DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
2152
2153         /* Set the VIF opmode */
2154         avp->av_opmode = ic_opmode;
2155         avp->av_bslot = -1;
2156
2157         if (ic_opmode == NL80211_IFTYPE_AP)
2158                 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2159
2160         sc->vifs[0] = conf->vif;
2161         sc->nvifs++;
2162
2163         /* Set the device opmode */
2164         sc->sc_ah->opmode = ic_opmode;
2165
2166         /*
2167          * Enable MIB interrupts when there are hardware phy counters.
2168          * Note we only do this (at the moment) for station mode.
2169          */
2170         if ((conf->type == NL80211_IFTYPE_STATION) ||
2171             (conf->type == NL80211_IFTYPE_ADHOC)) {
2172                 if (ath9k_hw_phycounters(sc->sc_ah))
2173                         sc->imask |= ATH9K_INT_MIB;
2174                 sc->imask |= ATH9K_INT_TSFOOR;
2175         }
2176
2177         /*
2178          * Some hardware processes the TIM IE and fires an
2179          * interrupt when the TIM bit is set.  For hardware
2180          * that does, if not overridden by configuration,
2181          * enable the TIM interrupt when operating as station.
2182          */
2183         if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
2184             (conf->type == NL80211_IFTYPE_STATION) &&
2185             !sc->config.swBeaconProcess)
2186                 sc->imask |= ATH9K_INT_TIM;
2187
2188         ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2189
2190         if (conf->type == NL80211_IFTYPE_AP) {
2191                 /* TODO: is this a suitable place to start ANI for AP mode? */
2192                 /* Start ANI */
2193                 mod_timer(&sc->ani.timer,
2194                           jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
2195         }
2196
2197         mutex_unlock(&sc->mutex);
2198
2199         return 0;
2200 }
2201
2202 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2203                                    struct ieee80211_if_init_conf *conf)
2204 {
2205         struct ath_softc *sc = hw->priv;
2206         struct ath_vif *avp = (void *)conf->vif->drv_priv;
2207
2208         DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n");
2209
2210         mutex_lock(&sc->mutex);
2211
2212         /* Stop ANI */
2213         del_timer_sync(&sc->ani.timer);
2214
2215         /* Reclaim beacon resources */
2216         if (sc->sc_ah->opmode == NL80211_IFTYPE_AP ||
2217             sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) {
2218                 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2219                 ath_beacon_return(sc, avp);
2220         }
2221
2222         sc->sc_flags &= ~SC_OP_BEACONS;
2223
2224         sc->vifs[0] = NULL;
2225         sc->nvifs--;
2226
2227         mutex_unlock(&sc->mutex);
2228 }
2229
2230 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2231 {
2232         struct ath_softc *sc = hw->priv;
2233         struct ieee80211_conf *conf = &hw->conf;
2234
2235         mutex_lock(&sc->mutex);
2236
2237         if (changed & IEEE80211_CONF_CHANGE_PS) {
2238                 if (conf->flags & IEEE80211_CONF_PS) {
2239                         if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2240                                 sc->imask |= ATH9K_INT_TIM_TIMER;
2241                                 ath9k_hw_set_interrupts(sc->sc_ah,
2242                                                 sc->imask);
2243                         }
2244                         ath9k_hw_setrxabort(sc->sc_ah, 1);
2245                         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2246                 } else {
2247                         ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
2248                         ath9k_hw_setrxabort(sc->sc_ah, 0);
2249                         sc->sc_flags &= ~SC_OP_WAIT_FOR_BEACON;
2250                         if (sc->imask & ATH9K_INT_TIM_TIMER) {
2251                                 sc->imask &= ~ATH9K_INT_TIM_TIMER;
2252                                 ath9k_hw_set_interrupts(sc->sc_ah,
2253                                                 sc->imask);
2254                         }
2255                 }
2256         }
2257
2258         if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2259                 struct ieee80211_channel *curchan = hw->conf.channel;
2260                 int pos = curchan->hw_value;
2261
2262                 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2263                         curchan->center_freq);
2264
2265                 /* XXX: remove me eventualy */
2266                 ath9k_update_ichannel(sc, &sc->sc_ah->channels[pos]);
2267
2268                 ath_update_chainmask(sc, conf_is_ht(conf));
2269
2270                 if (ath_set_channel(sc, &sc->sc_ah->channels[pos]) < 0) {
2271                         DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n");
2272                         mutex_unlock(&sc->mutex);
2273                         return -EINVAL;
2274                 }
2275         }
2276
2277         if (changed & IEEE80211_CONF_CHANGE_POWER)
2278                 sc->config.txpowlimit = 2 * conf->power_level;
2279
2280         mutex_unlock(&sc->mutex);
2281
2282         return 0;
2283 }
2284
2285 static int ath9k_config_interface(struct ieee80211_hw *hw,
2286                                   struct ieee80211_vif *vif,
2287                                   struct ieee80211_if_conf *conf)
2288 {
2289         struct ath_softc *sc = hw->priv;
2290         struct ath_hw *ah = sc->sc_ah;
2291         struct ath_vif *avp = (void *)vif->drv_priv;
2292         u32 rfilt = 0;
2293         int error, i;
2294
2295         /* TODO: Need to decide which hw opmode to use for multi-interface
2296          * cases */
2297         if (vif->type == NL80211_IFTYPE_AP &&
2298             ah->opmode != NL80211_IFTYPE_AP) {
2299                 ah->opmode = NL80211_IFTYPE_STATION;
2300                 ath9k_hw_setopmode(ah);
2301                 memcpy(sc->curbssid, sc->sc_ah->macaddr, ETH_ALEN);
2302                 sc->curaid = 0;
2303                 ath9k_hw_write_associd(sc);
2304                 /* Request full reset to get hw opmode changed properly */
2305                 sc->sc_flags |= SC_OP_FULL_RESET;
2306         }
2307
2308         if ((conf->changed & IEEE80211_IFCC_BSSID) &&
2309             !is_zero_ether_addr(conf->bssid)) {
2310                 switch (vif->type) {
2311                 case NL80211_IFTYPE_STATION:
2312                 case NL80211_IFTYPE_ADHOC:
2313                         /* Set BSSID */
2314                         memcpy(sc->curbssid, conf->bssid, ETH_ALEN);
2315                         sc->curaid = 0;
2316                         ath9k_hw_write_associd(sc);
2317
2318                         /* Set aggregation protection mode parameters */
2319                         sc->config.ath_aggr_prot = 0;
2320
2321                         DPRINTF(sc, ATH_DBG_CONFIG,
2322                                 "RX filter 0x%x bssid %pM aid 0x%x\n",
2323                                 rfilt, sc->curbssid, sc->curaid);
2324
2325                         /* need to reconfigure the beacon */
2326                         sc->sc_flags &= ~SC_OP_BEACONS ;
2327
2328                         break;
2329                 default:
2330                         break;
2331                 }
2332         }
2333
2334         if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2335             (vif->type == NL80211_IFTYPE_AP)) {
2336                 if ((conf->changed & IEEE80211_IFCC_BEACON) ||
2337                     (conf->changed & IEEE80211_IFCC_BEACON_ENABLED &&
2338                      conf->enable_beacon)) {
2339                         /*
2340                          * Allocate and setup the beacon frame.
2341                          *
2342                          * Stop any previous beacon DMA.  This may be
2343                          * necessary, for example, when an ibss merge
2344                          * causes reconfiguration; we may be called
2345                          * with beacon transmission active.
2346                          */
2347                         ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2348
2349                         error = ath_beacon_alloc(sc, 0);
2350                         if (error != 0)
2351                                 return error;
2352
2353                         ath_beacon_sync(sc, 0);
2354                 }
2355         }
2356
2357         /* Check for WLAN_CAPABILITY_PRIVACY ? */
2358         if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2359                 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2360                         if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2361                                 ath9k_hw_keysetmac(sc->sc_ah,
2362                                                    (u16)i,
2363                                                    sc->curbssid);
2364         }
2365
2366         /* Only legacy IBSS for now */
2367         if (vif->type == NL80211_IFTYPE_ADHOC)
2368                 ath_update_chainmask(sc, 0);
2369
2370         return 0;
2371 }
2372
2373 #define SUPPORTED_FILTERS                       \
2374         (FIF_PROMISC_IN_BSS |                   \
2375         FIF_ALLMULTI |                          \
2376         FIF_CONTROL |                           \
2377         FIF_OTHER_BSS |                         \
2378         FIF_BCN_PRBRESP_PROMISC |               \
2379         FIF_FCSFAIL)
2380
2381 /* FIXME: sc->sc_full_reset ? */
2382 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2383                                    unsigned int changed_flags,
2384                                    unsigned int *total_flags,
2385                                    int mc_count,
2386                                    struct dev_mc_list *mclist)
2387 {
2388         struct ath_softc *sc = hw->priv;
2389         u32 rfilt;
2390
2391         changed_flags &= SUPPORTED_FILTERS;
2392         *total_flags &= SUPPORTED_FILTERS;
2393
2394         sc->rx.rxfilter = *total_flags;
2395         rfilt = ath_calcrxfilter(sc);
2396         ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2397
2398         if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
2399                 if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
2400                         memcpy(sc->curbssid, ath_bcast_mac, ETH_ALEN);
2401                         sc->curaid = 0;
2402                         ath9k_hw_write_associd(sc);
2403                 }
2404         }
2405
2406         DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", sc->rx.rxfilter);
2407 }
2408
2409 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2410                              struct ieee80211_vif *vif,
2411                              enum sta_notify_cmd cmd,
2412                              struct ieee80211_sta *sta)
2413 {
2414         struct ath_softc *sc = hw->priv;
2415
2416         switch (cmd) {
2417         case STA_NOTIFY_ADD:
2418                 ath_node_attach(sc, sta);
2419                 break;
2420         case STA_NOTIFY_REMOVE:
2421                 ath_node_detach(sc, sta);
2422                 break;
2423         default:
2424                 break;
2425         }
2426 }
2427
2428 static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2429                          const struct ieee80211_tx_queue_params *params)
2430 {
2431         struct ath_softc *sc = hw->priv;
2432         struct ath9k_tx_queue_info qi;
2433         int ret = 0, qnum;
2434
2435         if (queue >= WME_NUM_AC)
2436                 return 0;
2437
2438         mutex_lock(&sc->mutex);
2439
2440         qi.tqi_aifs = params->aifs;
2441         qi.tqi_cwmin = params->cw_min;
2442         qi.tqi_cwmax = params->cw_max;
2443         qi.tqi_burstTime = params->txop;
2444         qnum = ath_get_hal_qnum(queue, sc);
2445
2446         DPRINTF(sc, ATH_DBG_CONFIG,
2447                 "Configure tx [queue/halq] [%d/%d],  "
2448                 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2449                 queue, qnum, params->aifs, params->cw_min,
2450                 params->cw_max, params->txop);
2451
2452         ret = ath_txq_update(sc, qnum, &qi);
2453         if (ret)
2454                 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n");
2455
2456         mutex_unlock(&sc->mutex);
2457
2458         return ret;
2459 }
2460
2461 static int ath9k_set_key(struct ieee80211_hw *hw,
2462                          enum set_key_cmd cmd,
2463                          struct ieee80211_vif *vif,
2464                          struct ieee80211_sta *sta,
2465                          struct ieee80211_key_conf *key)
2466 {
2467         struct ath_softc *sc = hw->priv;
2468         int ret = 0;
2469
2470         mutex_lock(&sc->mutex);
2471         ath9k_ps_wakeup(sc);
2472         DPRINTF(sc, ATH_DBG_KEYCACHE, "Set HW Key\n");
2473
2474         switch (cmd) {
2475         case SET_KEY:
2476                 ret = ath_key_config(sc, sta, key);
2477                 if (ret >= 0) {
2478                         key->hw_key_idx = ret;
2479                         /* push IV and Michael MIC generation to stack */
2480                         key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2481                         if (key->alg == ALG_TKIP)
2482                                 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2483                         if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2484                                 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2485                         ret = 0;
2486                 }
2487                 break;
2488         case DISABLE_KEY:
2489                 ath_key_delete(sc, key);
2490                 break;
2491         default:
2492                 ret = -EINVAL;
2493         }
2494
2495         ath9k_ps_restore(sc);
2496         mutex_unlock(&sc->mutex);
2497
2498         return ret;
2499 }
2500
2501 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2502                                    struct ieee80211_vif *vif,
2503                                    struct ieee80211_bss_conf *bss_conf,
2504                                    u32 changed)
2505 {
2506         struct ath_softc *sc = hw->priv;
2507
2508         mutex_lock(&sc->mutex);
2509
2510         if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2511                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2512                         bss_conf->use_short_preamble);
2513                 if (bss_conf->use_short_preamble)
2514                         sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
2515                 else
2516                         sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
2517         }
2518
2519         if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2520                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2521                         bss_conf->use_cts_prot);
2522                 if (bss_conf->use_cts_prot &&
2523                     hw->conf.channel->band != IEEE80211_BAND_5GHZ)
2524                         sc->sc_flags |= SC_OP_PROTECT_ENABLE;
2525                 else
2526                         sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
2527         }
2528
2529         if (changed & BSS_CHANGED_ASSOC) {
2530                 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2531                         bss_conf->assoc);
2532                 ath9k_bss_assoc_info(sc, vif, bss_conf);
2533         }
2534
2535         mutex_unlock(&sc->mutex);
2536 }
2537
2538 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
2539 {
2540         u64 tsf;
2541         struct ath_softc *sc = hw->priv;
2542
2543         mutex_lock(&sc->mutex);
2544         tsf = ath9k_hw_gettsf64(sc->sc_ah);
2545         mutex_unlock(&sc->mutex);
2546
2547         return tsf;
2548 }
2549
2550 static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
2551 {
2552         struct ath_softc *sc = hw->priv;
2553
2554         mutex_lock(&sc->mutex);
2555         ath9k_hw_settsf64(sc->sc_ah, tsf);
2556         mutex_unlock(&sc->mutex);
2557 }
2558
2559 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
2560 {
2561         struct ath_softc *sc = hw->priv;
2562
2563         mutex_lock(&sc->mutex);
2564         ath9k_hw_reset_tsf(sc->sc_ah);
2565         mutex_unlock(&sc->mutex);
2566 }
2567
2568 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2569                               enum ieee80211_ampdu_mlme_action action,
2570                               struct ieee80211_sta *sta,
2571                               u16 tid, u16 *ssn)
2572 {
2573         struct ath_softc *sc = hw->priv;
2574         int ret = 0;
2575
2576         switch (action) {
2577         case IEEE80211_AMPDU_RX_START:
2578                 if (!(sc->sc_flags & SC_OP_RXAGGR))
2579                         ret = -ENOTSUPP;
2580                 break;
2581         case IEEE80211_AMPDU_RX_STOP:
2582                 break;
2583         case IEEE80211_AMPDU_TX_START:
2584                 ret = ath_tx_aggr_start(sc, sta, tid, ssn);
2585                 if (ret < 0)
2586                         DPRINTF(sc, ATH_DBG_FATAL,
2587                                 "Unable to start TX aggregation\n");
2588                 else
2589                         ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2590                 break;
2591         case IEEE80211_AMPDU_TX_STOP:
2592                 ret = ath_tx_aggr_stop(sc, sta, tid);
2593                 if (ret < 0)
2594                         DPRINTF(sc, ATH_DBG_FATAL,
2595                                 "Unable to stop TX aggregation\n");
2596
2597                 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
2598                 break;
2599         case IEEE80211_AMPDU_TX_RESUME:
2600                 ath_tx_aggr_resume(sc, sta, tid);
2601                 break;
2602         default:
2603                 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n");
2604         }
2605
2606         return ret;
2607 }
2608
2609 struct ieee80211_ops ath9k_ops = {
2610         .tx                 = ath9k_tx,
2611         .start              = ath9k_start,
2612         .stop               = ath9k_stop,
2613         .add_interface      = ath9k_add_interface,
2614         .remove_interface   = ath9k_remove_interface,
2615         .config             = ath9k_config,
2616         .config_interface   = ath9k_config_interface,
2617         .configure_filter   = ath9k_configure_filter,
2618         .sta_notify         = ath9k_sta_notify,
2619         .conf_tx            = ath9k_conf_tx,
2620         .bss_info_changed   = ath9k_bss_info_changed,
2621         .set_key            = ath9k_set_key,
2622         .get_tsf            = ath9k_get_tsf,
2623         .set_tsf            = ath9k_set_tsf,
2624         .reset_tsf          = ath9k_reset_tsf,
2625         .ampdu_action       = ath9k_ampdu_action,
2626 };
2627
2628 static struct {
2629         u32 version;
2630         const char * name;
2631 } ath_mac_bb_names[] = {
2632         { AR_SREV_VERSION_5416_PCI,     "5416" },
2633         { AR_SREV_VERSION_5416_PCIE,    "5418" },
2634         { AR_SREV_VERSION_9100,         "9100" },
2635         { AR_SREV_VERSION_9160,         "9160" },
2636         { AR_SREV_VERSION_9280,         "9280" },
2637         { AR_SREV_VERSION_9285,         "9285" }
2638 };
2639
2640 static struct {
2641         u16 version;
2642         const char * name;
2643 } ath_rf_names[] = {
2644         { 0,                            "5133" },
2645         { AR_RAD5133_SREV_MAJOR,        "5133" },
2646         { AR_RAD5122_SREV_MAJOR,        "5122" },
2647         { AR_RAD2133_SREV_MAJOR,        "2133" },
2648         { AR_RAD2122_SREV_MAJOR,        "2122" }
2649 };
2650
2651 /*
2652  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2653  */
2654 const char *
2655 ath_mac_bb_name(u32 mac_bb_version)
2656 {
2657         int i;
2658
2659         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2660                 if (ath_mac_bb_names[i].version == mac_bb_version) {
2661                         return ath_mac_bb_names[i].name;
2662                 }
2663         }
2664
2665         return "????";
2666 }
2667
2668 /*
2669  * Return the RF name. "????" is returned if the RF is unknown.
2670  */
2671 const char *
2672 ath_rf_name(u16 rf_version)
2673 {
2674         int i;
2675
2676         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2677                 if (ath_rf_names[i].version == rf_version) {
2678                         return ath_rf_names[i].name;
2679                 }
2680         }
2681
2682         return "????";
2683 }
2684
2685 static int __init ath9k_init(void)
2686 {
2687         int error;
2688
2689         /* Register rate control algorithm */
2690         error = ath_rate_control_register();
2691         if (error != 0) {
2692                 printk(KERN_ERR
2693                         "ath9k: Unable to register rate control "
2694                         "algorithm: %d\n",
2695                         error);
2696                 goto err_out;
2697         }
2698
2699         error = ath_pci_init();
2700         if (error < 0) {
2701                 printk(KERN_ERR
2702                         "ath9k: No PCI devices found, driver not installed.\n");
2703                 error = -ENODEV;
2704                 goto err_rate_unregister;
2705         }
2706
2707         error = ath_ahb_init();
2708         if (error < 0) {
2709                 error = -ENODEV;
2710                 goto err_pci_exit;
2711         }
2712
2713         return 0;
2714
2715  err_pci_exit:
2716         ath_pci_exit();
2717
2718  err_rate_unregister:
2719         ath_rate_control_unregister();
2720  err_out:
2721         return error;
2722 }
2723 module_init(ath9k_init);
2724
2725 static void __exit ath9k_exit(void)
2726 {
2727         ath_ahb_exit();
2728         ath_pci_exit();
2729         ath_rate_control_unregister();
2730         printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
2731 }
2732 module_exit(ath9k_exit);