SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/ath9k/hw.c

   1 /*
   2  * Copyright (c) 2008 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <asm/unaligned.h>
  19
  20 #include "ath9k.h"
  21 #include "initvals.h"
  22
  23 static int btcoex_enable;
  24 module_param(btcoex_enable, bool, 0);
  25 MODULE_PARM_DESC(btcoex_enable, "Enable Bluetooth coexistence support");
  26
  27 #define ATH9K_CLOCK_RATE_CCK            22
  28 #define ATH9K_CLOCK_RATE_5GHZ_OFDM      40
  29 #define ATH9K_CLOCK_RATE_2GHZ_OFDM      44
  30
  31 static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type);
  32 static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
  33                               enum ath9k_ht_macmode macmode);
  34 static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
  35                               struct ar5416_eeprom_def *pEepData,
  36                               u32 reg, u32 value);
  37 static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan);
  38 static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan);
  39
  40 /********************/
  41 /* Helper Functions */
  42 /********************/
  43
  44 static u32 ath9k_hw_mac_usec(struct ath_hal *ah, u32 clks)
  45 {
  46         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  47         if (!ah->ah_curchan) /* should really check for CCK instead */
  48                 return clks / ATH9K_CLOCK_RATE_CCK;
  49         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  50                 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
  51         return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
  52 }
  53
  54 static u32 ath9k_hw_mac_to_usec(struct ath_hal *ah, u32 clks)
  55 {
  56         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  57         if (conf_is_ht40(conf))
  58                 return ath9k_hw_mac_usec(ah, clks) / 2;
  59         else
  60                 return ath9k_hw_mac_usec(ah, clks);
  61 }
  62
  63 static u32 ath9k_hw_mac_clks(struct ath_hal *ah, u32 usecs)
  64 {
  65         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  66         if (!ah->ah_curchan) /* should really check for CCK instead */
  67                 return usecs *ATH9K_CLOCK_RATE_CCK;
  68         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  69                 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
  70         return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
  71 }
  72
  73 static u32 ath9k_hw_mac_to_clks(struct ath_hal *ah, u32 usecs)
  74 {
  75         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  76         if (conf_is_ht40(conf))
  77                 return ath9k_hw_mac_clks(ah, usecs) * 2;
  78         else
  79                 return ath9k_hw_mac_clks(ah, usecs);
  80 }
  81
  82 bool ath9k_hw_wait(struct ath_hal *ah, u32 reg, u32 mask, u32 val)
  83 {
  84         int i;
  85
  86         for (i = 0; i < (AH_TIMEOUT / AH_TIME_QUANTUM); i++) {
  87                 if ((REG_READ(ah, reg) & mask) == val)
  88                         return true;
  89
  90                 udelay(AH_TIME_QUANTUM);
  91         }
  92
  93         DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
  94                 "timeout on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
  95                 reg, REG_READ(ah, reg), mask, val);
  96
  97         return false;
  98 }
  99
 100 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
 101 {
 102         u32 retval;
 103         int i;
 104
 105         for (i = 0, retval = 0; i < n; i++) {
 106                 retval = (retval << 1) | (val & 1);
 107                 val >>= 1;
 108         }
 109         return retval;
 110 }
 111
 112 bool ath9k_get_channel_edges(struct ath_hal *ah,
 113                              u16 flags, u16 *low,
 114                              u16 *high)
 115 {
 116         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
 117
 118         if (flags & CHANNEL_5GHZ) {
 119                 *low = pCap->low_5ghz_chan;
 120                 *high = pCap->high_5ghz_chan;
 121                 return true;
 122         }
 123         if ((flags & CHANNEL_2GHZ)) {
 124                 *low = pCap->low_2ghz_chan;
 125                 *high = pCap->high_2ghz_chan;
 126                 return true;
 127         }
 128         return false;
 129 }
 130
 131 u16 ath9k_hw_computetxtime(struct ath_hal *ah,
 132                            struct ath_rate_table *rates,
 133                            u32 frameLen, u16 rateix,
 134                            bool shortPreamble)
 135 {
 136         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
 137         u32 kbps;
 138
 139         kbps = rates->info[rateix].ratekbps;
 140
 141         if (kbps == 0)
 142                 return 0;
 143
 144         switch (rates->info[rateix].phy) {
 145         case WLAN_RC_PHY_CCK:
 146                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
 147                 if (shortPreamble && rates->info[rateix].short_preamble)
 148                         phyTime >>= 1;
 149                 numBits = frameLen << 3;
 150                 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
 151                 break;
 152         case WLAN_RC_PHY_OFDM:
 153                 if (ah->ah_curchan && IS_CHAN_QUARTER_RATE(ah->ah_curchan)) {
 154                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
 155                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 156                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 157                         txTime = OFDM_SIFS_TIME_QUARTER
 158                                 + OFDM_PREAMBLE_TIME_QUARTER
 159                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
 160                 } else if (ah->ah_curchan &&
 161                            IS_CHAN_HALF_RATE(ah->ah_curchan)) {
 162                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
 163                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 164                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 165                         txTime = OFDM_SIFS_TIME_HALF +
 166                                 OFDM_PREAMBLE_TIME_HALF
 167                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
 168                 } else {
 169                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
 170                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 171                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 172                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
 173                                 + (numSymbols * OFDM_SYMBOL_TIME);
 174                 }
 175                 break;
 176         default:
 177                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 178                         "Unknown phy %u (rate ix %u)\n",
 179                         rates->info[rateix].phy, rateix);
 180                 txTime = 0;
 181                 break;
 182         }
 183
 184         return txTime;
 185 }
 186
 187 void ath9k_hw_get_channel_centers(struct ath_hal *ah,
 188                                   struct ath9k_channel *chan,
 189                                   struct chan_centers *centers)
 190 {
 191         int8_t extoff;
 192         struct ath_hal_5416 *ahp = AH5416(ah);
 193
 194         if (!IS_CHAN_HT40(chan)) {
 195                 centers->ctl_center = centers->ext_center =
 196                         centers->synth_center = chan->channel;
 197                 return;
 198         }
 199
 200         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 201             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
 202                 centers->synth_center =
 203                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
 204                 extoff = 1;
 205         } else {
 206                 centers->synth_center =
 207                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
 208                 extoff = -1;
 209         }
 210
 211         centers->ctl_center =
 212                 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
 213         centers->ext_center =
 214                 centers->synth_center + (extoff *
 215                          ((ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
 216                           HT40_CHANNEL_CENTER_SHIFT : 15));
 217
 218 }
 219
 220 /******************/
 221 /* Chip Revisions */
 222 /******************/
 223
 224 static void ath9k_hw_read_revisions(struct ath_hal *ah)
 225 {
 226         u32 val;
 227
 228         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
 229
 230         if (val == 0xFF) {
 231                 val = REG_READ(ah, AR_SREV);
 232                 ah->hw_version.macVersion =
 233                         (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
 234                 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
 235                 ah->ah_isPciExpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
 236         } else {
 237                 if (!AR_SREV_9100(ah))
 238                         ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
 239
 240                 ah->hw_version.macRev = val & AR_SREV_REVISION;
 241
 242                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
 243                         ah->ah_isPciExpress = true;
 244         }
 245 }
 246
 247 static int ath9k_hw_get_radiorev(struct ath_hal *ah)
 248 {
 249         u32 val;
 250         int i;
 251
 252         REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
 253
 254         for (i = 0; i < 8; i++)
 255                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
 256         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
 257         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
 258
 259         return ath9k_hw_reverse_bits(val, 8);
 260 }
 261
 262 /************************************/
 263 /* HW Attach, Detach, Init Routines */
 264 /************************************/
 265
 266 static void ath9k_hw_disablepcie(struct ath_hal *ah)
 267 {
 268         if (AR_SREV_9100(ah))
 269                 return;
 270
 271         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 272         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 273         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
 274         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
 275         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
 276         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
 277         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 278         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 279         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
 280
 281         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 282 }
 283
 284 static bool ath9k_hw_chip_test(struct ath_hal *ah)
 285 {
 286         u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
 287         u32 regHold[2];
 288         u32 patternData[4] = { 0x55555555,
 289                                0xaaaaaaaa,
 290                                0x66666666,
 291                                0x99999999 };
 292         int i, j;
 293
 294         for (i = 0; i < 2; i++) {
 295                 u32 addr = regAddr[i];
 296                 u32 wrData, rdData;
 297
 298                 regHold[i] = REG_READ(ah, addr);
 299                 for (j = 0; j < 0x100; j++) {
 300                         wrData = (j << 16) | j;
 301                         REG_WRITE(ah, addr, wrData);
 302                         rdData = REG_READ(ah, addr);
 303                         if (rdData != wrData) {
 304                                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 305                                         "address test failed "
 306                                         "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 307                                         addr, wrData, rdData);
 308                                 return false;
 309                         }
 310                 }
 311                 for (j = 0; j < 4; j++) {
 312                         wrData = patternData[j];
 313                         REG_WRITE(ah, addr, wrData);
 314                         rdData = REG_READ(ah, addr);
 315                         if (wrData != rdData) {
 316                                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 317                                         "address test failed "
 318                                         "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 319                                         addr, wrData, rdData);
 320                                 return false;
 321                         }
 322                 }
 323                 REG_WRITE(ah, regAddr[i], regHold[i]);
 324         }
 325         udelay(100);
 326         return true;
 327 }
 328
 329 static const char *ath9k_hw_devname(u16 devid)
 330 {
 331         switch (devid) {
 332         case AR5416_DEVID_PCI:
 333                 return "Atheros 5416";
 334         case AR5416_DEVID_PCIE:
 335                 return "Atheros 5418";
 336         case AR9160_DEVID_PCI:
 337                 return "Atheros 9160";
 338         case AR5416_AR9100_DEVID:
 339                 return "Atheros 9100";
 340         case AR9280_DEVID_PCI:
 341         case AR9280_DEVID_PCIE:
 342                 return "Atheros 9280";
 343         case AR9285_DEVID_PCIE:
 344                 return "Atheros 9285";
 345         }
 346
 347         return NULL;
 348 }
 349
 350 static void ath9k_hw_set_defaults(struct ath_hal *ah)
 351 {
 352         int i;
 353
 354         ah->ah_config.dma_beacon_response_time = 2;
 355         ah->ah_config.sw_beacon_response_time = 10;
 356         ah->ah_config.additional_swba_backoff = 0;
 357         ah->ah_config.ack_6mb = 0x0;
 358         ah->ah_config.cwm_ignore_extcca = 0;
 359         ah->ah_config.pcie_powersave_enable = 0;
 360         ah->ah_config.pcie_l1skp_enable = 0;
 361         ah->ah_config.pcie_clock_req = 0;
 362         ah->ah_config.pcie_power_reset = 0x100;
 363         ah->ah_config.pcie_restore = 0;
 364         ah->ah_config.pcie_waen = 0;
 365         ah->ah_config.analog_shiftreg = 1;
 366         ah->ah_config.ht_enable = 1;
 367         ah->ah_config.ofdm_trig_low = 200;
 368         ah->ah_config.ofdm_trig_high = 500;
 369         ah->ah_config.cck_trig_high = 200;
 370         ah->ah_config.cck_trig_low = 100;
 371         ah->ah_config.enable_ani = 1;
 372         ah->ah_config.noise_immunity_level = 4;
 373         ah->ah_config.ofdm_weaksignal_det = 1;
 374         ah->ah_config.cck_weaksignal_thr = 0;
 375         ah->ah_config.spur_immunity_level = 2;
 376         ah->ah_config.firstep_level = 0;
 377         ah->ah_config.rssi_thr_high = 40;
 378         ah->ah_config.rssi_thr_low = 7;
 379         ah->ah_config.diversity_control = 0;
 380         ah->ah_config.antenna_switch_swap = 0;
 381
 382         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 383                 ah->ah_config.spurchans[i][0] = AR_NO_SPUR;
 384                 ah->ah_config.spurchans[i][1] = AR_NO_SPUR;
 385         }
 386
 387         ah->ah_config.intr_mitigation = 1;
 388 }
 389
 390 static struct ath_hal_5416 *ath9k_hw_newstate(u16 devid,
 391                                               struct ath_softc *sc,
 392                                               void __iomem *mem,
 393                                               int *status)
 394 {
 395         struct ath_hal_5416 *ahp;
 396         struct ath_hal *ah;
 397
 398         ahp = kzalloc(sizeof(struct ath_hal_5416), GFP_KERNEL);
 399         if (ahp == NULL) {
 400                 DPRINTF(sc, ATH_DBG_FATAL,
 401                         "Cannot allocate memory for state block\n");
 402                 *status = -ENOMEM;
 403                 return NULL;
 404         }
 405
 406         ah = &ahp->ah;
 407         ah->ah_sc = sc;
 408         ah->ah_sh = mem;
 409         ah->hw_version.magic = AR5416_MAGIC;
 410         ah->regulatory.country_code = CTRY_DEFAULT;
 411         ah->hw_version.devid = devid;
 412         ah->hw_version.subvendorid = 0;
 413
 414         ah->ah_flags = 0;
 415         if ((devid == AR5416_AR9100_DEVID))
 416                 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
 417         if (!AR_SREV_9100(ah))
 418                 ah->ah_flags = AH_USE_EEPROM;
 419
 420         ah->regulatory.power_limit = MAX_RATE_POWER;
 421         ah->regulatory.tp_scale = ATH9K_TP_SCALE_MAX;
 422         ahp->ah_atimWindow = 0;
 423         ahp->ah_diversityControl = ah->ah_config.diversity_control;
 424         ahp->ah_antennaSwitchSwap =
 425                 ah->ah_config.antenna_switch_swap;
 426         ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
 427         ahp->ah_beaconInterval = 100;
 428         ahp->ah_enable32kHzClock = DONT_USE_32KHZ;
 429         ahp->ah_slottime = (u32) -1;
 430         ahp->ah_acktimeout = (u32) -1;
 431         ahp->ah_ctstimeout = (u32) -1;
 432         ahp->ah_globaltxtimeout = (u32) -1;
 433
 434         ahp->ah_gBeaconRate = 0;
 435
 436         return ahp;
 437 }
 438
 439 static int ath9k_hw_rfattach(struct ath_hal *ah)
 440 {
 441         bool rfStatus = false;
 442         int ecode = 0;
 443
 444         rfStatus = ath9k_hw_init_rf(ah, &ecode);
 445         if (!rfStatus) {
 446                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 447                         "RF setup failed, status %u\n", ecode);
 448                 return ecode;
 449         }
 450
 451         return 0;
 452 }
 453
 454 static int ath9k_hw_rf_claim(struct ath_hal *ah)
 455 {
 456         u32 val;
 457
 458         REG_WRITE(ah, AR_PHY(0), 0x00000007);
 459
 460         val = ath9k_hw_get_radiorev(ah);
 461         switch (val & AR_RADIO_SREV_MAJOR) {
 462         case 0:
 463                 val = AR_RAD5133_SREV_MAJOR;
 464                 break;
 465         case AR_RAD5133_SREV_MAJOR:
 466         case AR_RAD5122_SREV_MAJOR:
 467         case AR_RAD2133_SREV_MAJOR:
 468         case AR_RAD2122_SREV_MAJOR:
 469                 break;
 470         default:
 471                 DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
 472                         "5G Radio Chip Rev 0x%02X is not "
 473                         "supported by this driver\n",
 474                         ah->hw_version.analog5GhzRev);
 475                 return -EOPNOTSUPP;
 476         }
 477
 478         ah->hw_version.analog5GhzRev = val;
 479
 480         return 0;
 481 }
 482
 483 static int ath9k_hw_init_macaddr(struct ath_hal *ah)
 484 {
 485         u32 sum;
 486         int i;
 487         u16 eeval;
 488
 489         sum = 0;
 490         for (i = 0; i < 3; i++) {
 491                 eeval = ath9k_hw_get_eeprom(ah, AR_EEPROM_MAC(i));
 492                 sum += eeval;
 493                 ah->macaddr[2 * i] = eeval >> 8;
 494                 ah->macaddr[2 * i + 1] = eeval & 0xff;
 495         }
 496         if (sum == 0 || sum == 0xffff * 3) {
 497                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 498                         "mac address read failed: %pM\n",
 499                         ah->macaddr);
 500                 return -EADDRNOTAVAIL;
 501         }
 502
 503         return 0;
 504 }
 505
 506 static void ath9k_hw_init_rxgain_ini(struct ath_hal *ah)
 507 {
 508         u32 rxgain_type;
 509         struct ath_hal_5416 *ahp = AH5416(ah);
 510
 511         if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
 512                 rxgain_type = ath9k_hw_get_eeprom(ah, EEP_RXGAIN_TYPE);
 513
 514                 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
 515                         INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
 516                         ar9280Modes_backoff_13db_rxgain_9280_2,
 517                         ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
 518                 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
 519                         INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
 520                         ar9280Modes_backoff_23db_rxgain_9280_2,
 521                         ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
 522                 else
 523                         INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
 524                         ar9280Modes_original_rxgain_9280_2,
 525                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 526         } else
 527                 INIT_INI_ARRAY(&ahp->ah_iniModesRxGain,
 528                         ar9280Modes_original_rxgain_9280_2,
 529                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 530 }
 531
 532 static void ath9k_hw_init_txgain_ini(struct ath_hal *ah)
 533 {
 534         u32 txgain_type;
 535         struct ath_hal_5416 *ahp = AH5416(ah);
 536
 537         if (ath9k_hw_get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
 538                 txgain_type = ath9k_hw_get_eeprom(ah, EEP_TXGAIN_TYPE);
 539
 540                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
 541                         INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
 542                         ar9280Modes_high_power_tx_gain_9280_2,
 543                         ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
 544                 else
 545                         INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
 546                         ar9280Modes_original_tx_gain_9280_2,
 547                         ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 548         } else
 549                 INIT_INI_ARRAY(&ahp->ah_iniModesTxGain,
 550                 ar9280Modes_original_tx_gain_9280_2,
 551                 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 552 }
 553
 554 static int ath9k_hw_post_attach(struct ath_hal *ah)
 555 {
 556         int ecode;
 557
 558         if (!ath9k_hw_chip_test(ah)) {
 559                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 560                         "hardware self-test failed\n");
 561                 return -ENODEV;
 562         }
 563
 564         ecode = ath9k_hw_rf_claim(ah);
 565         if (ecode != 0)
 566                 return ecode;
 567
 568         ecode = ath9k_hw_eeprom_attach(ah);
 569         if (ecode != 0)
 570                 return ecode;
 571         ecode = ath9k_hw_rfattach(ah);
 572         if (ecode != 0)
 573                 return ecode;
 574
 575         if (!AR_SREV_9100(ah)) {
 576                 ath9k_hw_ani_setup(ah);
 577                 ath9k_hw_ani_attach(ah);
 578         }
 579
 580         return 0;
 581 }
 582
 583 static struct ath_hal *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
 584                                           void __iomem *mem, int *status)
 585 {
 586         struct ath_hal_5416 *ahp;
 587         struct ath_hal *ah;
 588         int ecode;
 589         u32 i, j;
 590
 591         ahp = ath9k_hw_newstate(devid, sc, mem, status);
 592         if (ahp == NULL)
 593                 return NULL;
 594
 595         ah = &ahp->ah;
 596
 597         ath9k_hw_set_defaults(ah);
 598
 599         if (ah->ah_config.intr_mitigation != 0)
 600                 ahp->ah_intrMitigation = true;
 601
 602         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
 603                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "Couldn't reset chip\n");
 604                 ecode = -EIO;
 605                 goto bad;
 606         }
 607
 608         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
 609                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "Couldn't wakeup chip\n");
 610                 ecode = -EIO;
 611                 goto bad;
 612         }
 613
 614         if (ah->ah_config.serialize_regmode == SER_REG_MODE_AUTO) {
 615                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) {
 616                         ah->ah_config.serialize_regmode =
 617                                 SER_REG_MODE_ON;
 618                 } else {
 619                         ah->ah_config.serialize_regmode =
 620                                 SER_REG_MODE_OFF;
 621                 }
 622         }
 623
 624         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 625                 "serialize_regmode is %d\n",
 626                 ah->ah_config.serialize_regmode);
 627
 628         if ((ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCI) &&
 629             (ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCIE) &&
 630             (ah->hw_version.macVersion != AR_SREV_VERSION_9160) &&
 631             (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) && (!AR_SREV_9285(ah))) {
 632                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 633                         "Mac Chip Rev 0x%02x.%x is not supported by "
 634                         "this driver\n", ah->hw_version.macVersion,
 635                         ah->hw_version.macRev);
 636                 ecode = -EOPNOTSUPP;
 637                 goto bad;
 638         }
 639
 640         if (AR_SREV_9100(ah)) {
 641                 ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
 642                 ahp->ah_suppCals = IQ_MISMATCH_CAL;
 643                 ah->ah_isPciExpress = false;
 644         }
 645         ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
 646
 647         if (AR_SREV_9160_10_OR_LATER(ah)) {
 648                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 649                         ahp->ah_iqCalData.calData = &iq_cal_single_sample;
 650                         ahp->ah_adcGainCalData.calData =
 651                                 &adc_gain_cal_single_sample;
 652                         ahp->ah_adcDcCalData.calData =
 653                                 &adc_dc_cal_single_sample;
 654                         ahp->ah_adcDcCalInitData.calData =
 655                                 &adc_init_dc_cal;
 656                 } else {
 657                         ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
 658                         ahp->ah_adcGainCalData.calData =
 659                                 &adc_gain_cal_multi_sample;
 660                         ahp->ah_adcDcCalData.calData =
 661                                 &adc_dc_cal_multi_sample;
 662                         ahp->ah_adcDcCalInitData.calData =
 663                                 &adc_init_dc_cal;
 664                 }
 665                 ahp->ah_suppCals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
 666         }
 667
 668         if (AR_SREV_9160(ah)) {
 669                 ah->ah_config.enable_ani = 1;
 670                 ahp->ah_ani_function = (ATH9K_ANI_SPUR_IMMUNITY_LEVEL |
 671                                         ATH9K_ANI_FIRSTEP_LEVEL);
 672         } else {
 673                 ahp->ah_ani_function = ATH9K_ANI_ALL;
 674                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 675                         ahp->ah_ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
 676                 }
 677         }
 678
 679         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 680                 "This Mac Chip Rev 0x%02x.%x is \n",
 681                 ah->hw_version.macVersion, ah->hw_version.macRev);
 682
 683         if (AR_SREV_9285_12_OR_LATER(ah)) {
 684                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9285Modes_9285_1_2,
 685                                ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
 686                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9285Common_9285_1_2,
 687                                ARRAY_SIZE(ar9285Common_9285_1_2), 2);
 688
 689                 if (ah->ah_config.pcie_clock_req) {
 690                         INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
 691                         ar9285PciePhy_clkreq_off_L1_9285_1_2,
 692                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
 693                 } else {
 694                         INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
 695                         ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
 696                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
 697                                   2);
 698                 }
 699         } else if (AR_SREV_9285_10_OR_LATER(ah)) {
 700                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9285Modes_9285,
 701                                ARRAY_SIZE(ar9285Modes_9285), 6);
 702                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9285Common_9285,
 703                                ARRAY_SIZE(ar9285Common_9285), 2);
 704
 705                 if (ah->ah_config.pcie_clock_req) {
 706                         INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
 707                         ar9285PciePhy_clkreq_off_L1_9285,
 708                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
 709                 } else {
 710                         INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
 711                         ar9285PciePhy_clkreq_always_on_L1_9285,
 712                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
 713                 }
 714         } else if (AR_SREV_9280_20_OR_LATER(ah)) {
 715                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280_2,
 716                                ARRAY_SIZE(ar9280Modes_9280_2), 6);
 717                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280_2,
 718                                ARRAY_SIZE(ar9280Common_9280_2), 2);
 719
 720                 if (ah->ah_config.pcie_clock_req) {
 721                         INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
 722                                ar9280PciePhy_clkreq_off_L1_9280,
 723                                ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
 724                 } else {
 725                         INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
 726                                ar9280PciePhy_clkreq_always_on_L1_9280,
 727                                ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
 728                 }
 729                 INIT_INI_ARRAY(&ahp->ah_iniModesAdditional,
 730                                ar9280Modes_fast_clock_9280_2,
 731                                ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
 732         } else if (AR_SREV_9280_10_OR_LATER(ah)) {
 733                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280,
 734                                ARRAY_SIZE(ar9280Modes_9280), 6);
 735                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280,
 736                                ARRAY_SIZE(ar9280Common_9280), 2);
 737         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 738                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9160,
 739                                ARRAY_SIZE(ar5416Modes_9160), 6);
 740                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9160,
 741                                ARRAY_SIZE(ar5416Common_9160), 2);
 742                 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9160,
 743                                ARRAY_SIZE(ar5416Bank0_9160), 2);
 744                 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9160,
 745                                ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
 746                 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9160,
 747                                ARRAY_SIZE(ar5416Bank1_9160), 2);
 748                 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9160,
 749                                ARRAY_SIZE(ar5416Bank2_9160), 2);
 750                 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9160,
 751                                ARRAY_SIZE(ar5416Bank3_9160), 3);
 752                 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9160,
 753                                ARRAY_SIZE(ar5416Bank6_9160), 3);
 754                 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9160,
 755                                ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
 756                 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9160,
 757                                ARRAY_SIZE(ar5416Bank7_9160), 2);
 758                 if (AR_SREV_9160_11(ah)) {
 759                         INIT_INI_ARRAY(&ahp->ah_iniAddac,
 760                                        ar5416Addac_91601_1,
 761                                        ARRAY_SIZE(ar5416Addac_91601_1), 2);
 762                 } else {
 763                         INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9160,
 764                                        ARRAY_SIZE(ar5416Addac_9160), 2);
 765                 }
 766         } else if (AR_SREV_9100_OR_LATER(ah)) {
 767                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9100,
 768                                ARRAY_SIZE(ar5416Modes_9100), 6);
 769                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9100,
 770                                ARRAY_SIZE(ar5416Common_9100), 2);
 771                 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9100,
 772                                ARRAY_SIZE(ar5416Bank0_9100), 2);
 773                 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9100,
 774                                ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
 775                 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9100,
 776                                ARRAY_SIZE(ar5416Bank1_9100), 2);
 777                 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9100,
 778                                ARRAY_SIZE(ar5416Bank2_9100), 2);
 779                 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9100,
 780                                ARRAY_SIZE(ar5416Bank3_9100), 3);
 781                 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9100,
 782                                ARRAY_SIZE(ar5416Bank6_9100), 3);
 783                 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9100,
 784                                ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
 785                 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9100,
 786                                ARRAY_SIZE(ar5416Bank7_9100), 2);
 787                 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9100,
 788                                ARRAY_SIZE(ar5416Addac_9100), 2);
 789         } else {
 790                 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes,
 791                                ARRAY_SIZE(ar5416Modes), 6);
 792                 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common,
 793                                ARRAY_SIZE(ar5416Common), 2);
 794                 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0,
 795                                ARRAY_SIZE(ar5416Bank0), 2);
 796                 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain,
 797                                ARRAY_SIZE(ar5416BB_RfGain), 3);
 798                 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1,
 799                                ARRAY_SIZE(ar5416Bank1), 2);
 800                 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2,
 801                                ARRAY_SIZE(ar5416Bank2), 2);
 802                 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3,
 803                                ARRAY_SIZE(ar5416Bank3), 3);
 804                 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6,
 805                                ARRAY_SIZE(ar5416Bank6), 3);
 806                 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC,
 807                                ARRAY_SIZE(ar5416Bank6TPC), 3);
 808                 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7,
 809                                ARRAY_SIZE(ar5416Bank7), 2);
 810                 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac,
 811                                ARRAY_SIZE(ar5416Addac), 2);
 812         }
 813
 814         if (ah->ah_isPciExpress)
 815                 ath9k_hw_configpcipowersave(ah, 0);
 816         else
 817                 ath9k_hw_disablepcie(ah);
 818
 819         ecode = ath9k_hw_post_attach(ah);
 820         if (ecode != 0)
 821                 goto bad;
 822
 823         /* rxgain table */
 824         if (AR_SREV_9280_20(ah))
 825                 ath9k_hw_init_rxgain_ini(ah);
 826
 827         /* txgain table */
 828         if (AR_SREV_9280_20(ah))
 829                 ath9k_hw_init_txgain_ini(ah);
 830
 831         if (ah->hw_version.devid == AR9280_DEVID_PCI) {
 832                 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
 833                         u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
 834
 835                         for (j = 1; j < ahp->ah_iniModes.ia_columns; j++) {
 836                                 u32 val = INI_RA(&ahp->ah_iniModes, i, j);
 837
 838                                 INI_RA(&ahp->ah_iniModes, i, j) =
 839                                         ath9k_hw_ini_fixup(ah,
 840                                                            &ahp->ah_eeprom.def,
 841                                                            reg, val);
 842                         }
 843                 }
 844         }
 845
 846         if (!ath9k_hw_fill_cap_info(ah)) {
 847                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 848                         "failed ath9k_hw_fill_cap_info\n");
 849                 ecode = -EINVAL;
 850                 goto bad;
 851         }
 852
 853         ecode = ath9k_hw_init_macaddr(ah);
 854         if (ecode != 0) {
 855                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
 856                         "failed initializing mac address\n");
 857                 goto bad;
 858         }
 859
 860         if (AR_SREV_9285(ah))
 861                 ah->ah_txTrigLevel = (AR_FTRIG_256B >> AR_FTRIG_S);
 862         else
 863                 ah->ah_txTrigLevel = (AR_FTRIG_512B >> AR_FTRIG_S);
 864
 865         ath9k_init_nfcal_hist_buffer(ah);
 866
 867         return ah;
 868 bad:
 869         if (ahp)
 870                 ath9k_hw_detach((struct ath_hal *) ahp);
 871         if (status)
 872                 *status = ecode;
 873
 874         return NULL;
 875 }
 876
 877 static void ath9k_hw_init_bb(struct ath_hal *ah,
 878                              struct ath9k_channel *chan)
 879 {
 880         u32 synthDelay;
 881
 882         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 883         if (IS_CHAN_B(chan))
 884                 synthDelay = (4 * synthDelay) / 22;
 885         else
 886                 synthDelay /= 10;
 887
 888         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
 889
 890         udelay(synthDelay + BASE_ACTIVATE_DELAY);
 891 }
 892
 893 static void ath9k_hw_init_qos(struct ath_hal *ah)
 894 {
 895         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
 896         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
 897
 898         REG_WRITE(ah, AR_QOS_NO_ACK,
 899                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
 900                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
 901                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
 902
 903         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
 904         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
 905         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
 906         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
 907         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
 908 }
 909
 910 static void ath9k_hw_init_pll(struct ath_hal *ah,
 911                               struct ath9k_channel *chan)
 912 {
 913         u32 pll;
 914
 915         if (AR_SREV_9100(ah)) {
 916                 if (chan && IS_CHAN_5GHZ(chan))
 917                         pll = 0x1450;
 918                 else
 919                         pll = 0x1458;
 920         } else {
 921                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 922                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
 923
 924                         if (chan && IS_CHAN_HALF_RATE(chan))
 925                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
 926                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 927                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
 928
 929                         if (chan && IS_CHAN_5GHZ(chan)) {
 930                                 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
 931
 932
 933                                 if (AR_SREV_9280_20(ah)) {
 934                                         if (((chan->channel % 20) == 0)
 935                                             || ((chan->channel % 10) == 0))
 936                                                 pll = 0x2850;
 937                                         else
 938                                                 pll = 0x142c;
 939                                 }
 940                         } else {
 941                                 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
 942                         }
 943
 944                 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 945
 946                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
 947
 948                         if (chan && IS_CHAN_HALF_RATE(chan))
 949                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
 950                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 951                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
 952
 953                         if (chan && IS_CHAN_5GHZ(chan))
 954                                 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
 955                         else
 956                                 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
 957                 } else {
 958                         pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
 959
 960                         if (chan && IS_CHAN_HALF_RATE(chan))
 961                                 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
 962                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 963                                 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
 964
 965                         if (chan && IS_CHAN_5GHZ(chan))
 966                                 pll |= SM(0xa, AR_RTC_PLL_DIV);
 967                         else
 968                                 pll |= SM(0xb, AR_RTC_PLL_DIV);
 969                 }
 970         }
 971         REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
 972
 973         udelay(RTC_PLL_SETTLE_DELAY);
 974
 975         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
 976 }
 977
 978 static void ath9k_hw_init_chain_masks(struct ath_hal *ah)
 979 {
 980         struct ath_hal_5416 *ahp = AH5416(ah);
 981         int rx_chainmask, tx_chainmask;
 982
 983         rx_chainmask = ahp->ah_rxchainmask;
 984         tx_chainmask = ahp->ah_txchainmask;
 985
 986         switch (rx_chainmask) {
 987         case 0x5:
 988                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
 989                             AR_PHY_SWAP_ALT_CHAIN);
 990         case 0x3:
 991                 if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) {
 992                         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
 993                         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
 994                         break;
 995                 }
 996         case 0x1:
 997         case 0x2:
 998         case 0x7:
 999                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1000                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1001                 break;
1002         default:
1003                 break;
1004         }
1005
1006         REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1007         if (tx_chainmask == 0x5) {
1008                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1009                             AR_PHY_SWAP_ALT_CHAIN);
1010         }
1011         if (AR_SREV_9100(ah))
1012                 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1013                           REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1014 }
1015
1016 static void ath9k_hw_init_interrupt_masks(struct ath_hal *ah,
1017                                           enum nl80211_iftype opmode)
1018 {
1019         struct ath_hal_5416 *ahp = AH5416(ah);
1020
1021         ahp->ah_maskReg = AR_IMR_TXERR |
1022                 AR_IMR_TXURN |
1023                 AR_IMR_RXERR |
1024                 AR_IMR_RXORN |
1025                 AR_IMR_BCNMISC;
1026
1027         if (ahp->ah_intrMitigation)
1028                 ahp->ah_maskReg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1029         else
1030                 ahp->ah_maskReg |= AR_IMR_RXOK;
1031
1032         ahp->ah_maskReg |= AR_IMR_TXOK;
1033
1034         if (opmode == NL80211_IFTYPE_AP)
1035                 ahp->ah_maskReg |= AR_IMR_MIB;
1036
1037         REG_WRITE(ah, AR_IMR, ahp->ah_maskReg);
1038         REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1039
1040         if (!AR_SREV_9100(ah)) {
1041                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1042                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1043                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1044         }
1045 }
1046
1047 static bool ath9k_hw_set_ack_timeout(struct ath_hal *ah, u32 us)
1048 {
1049         struct ath_hal_5416 *ahp = AH5416(ah);
1050
1051         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1052                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
1053                 ahp->ah_acktimeout = (u32) -1;
1054                 return false;
1055         } else {
1056                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1057                               AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1058                 ahp->ah_acktimeout = us;
1059                 return true;
1060         }
1061 }
1062
1063 static bool ath9k_hw_set_cts_timeout(struct ath_hal *ah, u32 us)
1064 {
1065         struct ath_hal_5416 *ahp = AH5416(ah);
1066
1067         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1068                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
1069                 ahp->ah_ctstimeout = (u32) -1;
1070                 return false;
1071         } else {
1072                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1073                               AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1074                 ahp->ah_ctstimeout = us;
1075                 return true;
1076         }
1077 }
1078
1079 static bool ath9k_hw_set_global_txtimeout(struct ath_hal *ah, u32 tu)
1080 {
1081         struct ath_hal_5416 *ahp = AH5416(ah);
1082
1083         if (tu > 0xFFFF) {
1084                 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1085                         "bad global tx timeout %u\n", tu);
1086                 ahp->ah_globaltxtimeout = (u32) -1;
1087                 return false;
1088         } else {
1089                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1090                 ahp->ah_globaltxtimeout = tu;
1091                 return true;
1092         }
1093 }
1094
1095 static void ath9k_hw_init_user_settings(struct ath_hal *ah)
1096 {
1097         struct ath_hal_5416 *ahp = AH5416(ah);
1098
1099         DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ahp->ah_miscMode 0x%x\n",
1100                 ahp->ah_miscMode);
1101
1102         if (ahp->ah_miscMode != 0)
1103                 REG_WRITE(ah, AR_PCU_MISC,
1104                           REG_READ(ah, AR_PCU_MISC) | ahp->ah_miscMode);
1105         if (ahp->ah_slottime != (u32) -1)
1106                 ath9k_hw_setslottime(ah, ahp->ah_slottime);
1107         if (ahp->ah_acktimeout != (u32) -1)
1108                 ath9k_hw_set_ack_timeout(ah, ahp->ah_acktimeout);
1109         if (ahp->ah_ctstimeout != (u32) -1)
1110                 ath9k_hw_set_cts_timeout(ah, ahp->ah_ctstimeout);
1111         if (ahp->ah_globaltxtimeout != (u32) -1)
1112                 ath9k_hw_set_global_txtimeout(ah, ahp->ah_globaltxtimeout);
1113 }
1114
1115 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1116 {
1117         return vendorid == ATHEROS_VENDOR_ID ?
1118                 ath9k_hw_devname(devid) : NULL;
1119 }
1120
1121 void ath9k_hw_detach(struct ath_hal *ah)
1122 {
1123         if (!AR_SREV_9100(ah))
1124                 ath9k_hw_ani_detach(ah);
1125
1126         ath9k_hw_rfdetach(ah);
1127         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1128         kfree(ah);
1129 }
1130
1131 struct ath_hal *ath9k_hw_attach(u16 devid, struct ath_softc *sc,
1132                                 void __iomem *mem, int *error)
1133 {
1134         struct ath_hal *ah = NULL;
1135
1136         switch (devid) {
1137         case AR5416_DEVID_PCI:
1138         case AR5416_DEVID_PCIE:
1139         case AR5416_AR9100_DEVID:
1140         case AR9160_DEVID_PCI:
1141         case AR9280_DEVID_PCI:
1142         case AR9280_DEVID_PCIE:
1143         case AR9285_DEVID_PCIE:
1144                 ah = ath9k_hw_do_attach(devid, sc, mem, error);
1145                 break;
1146         default:
1147                 *error = -ENXIO;
1148                 break;
1149         }
1150
1151         return ah;
1152 }
1153
1154 /*******/
1155 /* INI */
1156 /*******/
1157
1158 static void ath9k_hw_override_ini(struct ath_hal *ah,
1159                                   struct ath9k_channel *chan)
1160 {
1161         /*
1162          * Set the RX_ABORT and RX_DIS and clear if off only after
1163          * RXE is set for MAC. This prevents frames with corrupted
1164          * descriptor status.
1165          */
1166         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1167
1168
1169         if (!AR_SREV_5416_V20_OR_LATER(ah) ||
1170             AR_SREV_9280_10_OR_LATER(ah))
1171                 return;
1172
1173         REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1174 }
1175
1176 static u32 ath9k_hw_def_ini_fixup(struct ath_hal *ah,
1177                               struct ar5416_eeprom_def *pEepData,
1178                               u32 reg, u32 value)
1179 {
1180         struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1181
1182         switch (ah->hw_version.devid) {
1183         case AR9280_DEVID_PCI:
1184                 if (reg == 0x7894) {
1185                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1186                                 "ini VAL: %x  EEPROM: %x\n", value,
1187                                 (pBase->version & 0xff));
1188
1189                         if ((pBase->version & 0xff) > 0x0a) {
1190                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1191                                         "PWDCLKIND: %d\n",
1192                                         pBase->pwdclkind);
1193                                 value &= ~AR_AN_TOP2_PWDCLKIND;
1194                                 value |= AR_AN_TOP2_PWDCLKIND &
1195                                         (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1196                         } else {
1197                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1198                                         "PWDCLKIND Earlier Rev\n");
1199                         }
1200
1201                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
1202                                 "final ini VAL: %x\n", value);
1203                 }
1204                 break;
1205         }
1206
1207         return value;
1208 }
1209
1210 static u32 ath9k_hw_ini_fixup(struct ath_hal *ah,
1211                               struct ar5416_eeprom_def *pEepData,
1212                               u32 reg, u32 value)
1213 {
1214         struct ath_hal_5416 *ahp = AH5416(ah);
1215
1216         if (ahp->ah_eep_map == EEP_MAP_4KBITS)
1217                 return value;
1218         else
1219                 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1220 }
1221
1222 static int ath9k_hw_process_ini(struct ath_hal *ah,
1223                                 struct ath9k_channel *chan,
1224                                 enum ath9k_ht_macmode macmode)
1225 {
1226         int i, regWrites = 0;
1227         struct ath_hal_5416 *ahp = AH5416(ah);
1228         struct ieee80211_channel *channel = chan->chan;
1229         u32 modesIndex, freqIndex;
1230         int status;
1231
1232         switch (chan->chanmode) {
1233         case CHANNEL_A:
1234         case CHANNEL_A_HT20:
1235                 modesIndex = 1;
1236                 freqIndex = 1;
1237                 break;
1238         case CHANNEL_A_HT40PLUS:
1239         case CHANNEL_A_HT40MINUS:
1240                 modesIndex = 2;
1241                 freqIndex = 1;
1242                 break;
1243         case CHANNEL_G:
1244         case CHANNEL_G_HT20:
1245         case CHANNEL_B:
1246                 modesIndex = 4;
1247                 freqIndex = 2;
1248                 break;
1249         case CHANNEL_G_HT40PLUS:
1250         case CHANNEL_G_HT40MINUS:
1251                 modesIndex = 3;
1252                 freqIndex = 2;
1253                 break;
1254
1255         default:
1256                 return -EINVAL;
1257         }
1258
1259         REG_WRITE(ah, AR_PHY(0), 0x00000007);
1260
1261         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1262
1263         ath9k_hw_set_addac(ah, chan);
1264
1265         if (AR_SREV_5416_V22_OR_LATER(ah)) {
1266                 REG_WRITE_ARRAY(&ahp->ah_iniAddac, 1, regWrites);
1267         } else {
1268                 struct ar5416IniArray temp;
1269                 u32 addacSize =
1270                         sizeof(u32) * ahp->ah_iniAddac.ia_rows *
1271                         ahp->ah_iniAddac.ia_columns;
1272
1273                 memcpy(ahp->ah_addac5416_21,
1274                        ahp->ah_iniAddac.ia_array, addacSize);
1275
1276                 (ahp->ah_addac5416_21)[31 * ahp->ah_iniAddac.ia_columns + 1] = 0;
1277
1278                 temp.ia_array = ahp->ah_addac5416_21;
1279                 temp.ia_columns = ahp->ah_iniAddac.ia_columns;
1280                 temp.ia_rows = ahp->ah_iniAddac.ia_rows;
1281                 REG_WRITE_ARRAY(&temp, 1, regWrites);
1282         }
1283
1284         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1285
1286         for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
1287                 u32 reg = INI_RA(&ahp->ah_iniModes, i, 0);
1288                 u32 val = INI_RA(&ahp->ah_iniModes, i, modesIndex);
1289
1290                 REG_WRITE(ah, reg, val);
1291
1292                 if (reg >= 0x7800 && reg < 0x78a0
1293                     && ah->ah_config.analog_shiftreg) {
1294                         udelay(100);
1295                 }
1296
1297                 DO_DELAY(regWrites);
1298         }
1299
1300         if (AR_SREV_9280(ah))
1301                 REG_WRITE_ARRAY(&ahp->ah_iniModesRxGain, modesIndex, regWrites);
1302
1303         if (AR_SREV_9280(ah))
1304                 REG_WRITE_ARRAY(&ahp->ah_iniModesTxGain, modesIndex, regWrites);
1305
1306         for (i = 0; i < ahp->ah_iniCommon.ia_rows; i++) {
1307                 u32 reg = INI_RA(&ahp->ah_iniCommon, i, 0);
1308                 u32 val = INI_RA(&ahp->ah_iniCommon, i, 1);
1309
1310                 REG_WRITE(ah, reg, val);
1311
1312                 if (reg >= 0x7800 && reg < 0x78a0
1313                     && ah->ah_config.analog_shiftreg) {
1314                         udelay(100);
1315                 }
1316
1317                 DO_DELAY(regWrites);
1318         }
1319
1320         ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1321
1322         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1323                 REG_WRITE_ARRAY(&ahp->ah_iniModesAdditional, modesIndex,
1324                                 regWrites);
1325         }
1326
1327         ath9k_hw_override_ini(ah, chan);
1328         ath9k_hw_set_regs(ah, chan, macmode);
1329         ath9k_hw_init_chain_masks(ah);
1330
1331         status = ath9k_hw_set_txpower(ah, chan,
1332                                       ath9k_regd_get_ctl(ah, chan),
1333                                       channel->max_antenna_gain * 2,
1334                                       channel->max_power * 2,
1335                                       min((u32) MAX_RATE_POWER,
1336                                           (u32) ah->regulatory.power_limit));
1337         if (status != 0) {
1338                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
1339                         "error init'ing transmit power\n");
1340                 return -EIO;
1341         }
1342
1343         if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1344                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1345                         "ar5416SetRfRegs failed\n");
1346                 return -EIO;
1347         }
1348
1349         return 0;
1350 }
1351
1352 /****************************************/
1353 /* Reset and Channel Switching Routines */
1354 /****************************************/
1355
1356 static void ath9k_hw_set_rfmode(struct ath_hal *ah, struct ath9k_channel *chan)
1357 {
1358         u32 rfMode = 0;
1359
1360         if (chan == NULL)
1361                 return;
1362
1363         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1364                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1365
1366         if (!AR_SREV_9280_10_OR_LATER(ah))
1367                 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1368                         AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1369
1370         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1371                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1372
1373         REG_WRITE(ah, AR_PHY_MODE, rfMode);
1374 }
1375
1376 static void ath9k_hw_mark_phy_inactive(struct ath_hal *ah)
1377 {
1378         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1379 }
1380
1381 static inline void ath9k_hw_set_dma(struct ath_hal *ah)
1382 {
1383         u32 regval;
1384
1385         regval = REG_READ(ah, AR_AHB_MODE);
1386         REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1387
1388         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1389         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1390
1391         REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->ah_txTrigLevel);
1392
1393         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1394         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1395
1396         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1397
1398         if (AR_SREV_9285(ah)) {
1399                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1400                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1401         } else {
1402                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1403                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1404         }
1405 }
1406
1407 static void ath9k_hw_set_operating_mode(struct ath_hal *ah, int opmode)
1408 {
1409         u32 val;
1410
1411         val = REG_READ(ah, AR_STA_ID1);
1412         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1413         switch (opmode) {
1414         case NL80211_IFTYPE_AP:
1415                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1416                           | AR_STA_ID1_KSRCH_MODE);
1417                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1418                 break;
1419         case NL80211_IFTYPE_ADHOC:
1420                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1421                           | AR_STA_ID1_KSRCH_MODE);
1422                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1423                 break;
1424         case NL80211_IFTYPE_STATION:
1425         case NL80211_IFTYPE_MONITOR:
1426                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1427                 break;
1428         }
1429 }
1430
1431 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hal *ah,
1432                                                  u32 coef_scaled,
1433                                                  u32 *coef_mantissa,
1434                                                  u32 *coef_exponent)
1435 {
1436         u32 coef_exp, coef_man;
1437
1438         for (coef_exp = 31; coef_exp > 0; coef_exp--)
1439                 if ((coef_scaled >> coef_exp) & 0x1)
1440                         break;
1441
1442         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1443
1444         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1445
1446         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1447         *coef_exponent = coef_exp - 16;
1448 }
1449
1450 static void ath9k_hw_set_delta_slope(struct ath_hal *ah,
1451                                      struct ath9k_channel *chan)
1452 {
1453         u32 coef_scaled, ds_coef_exp, ds_coef_man;
1454         u32 clockMhzScaled = 0x64000000;
1455         struct chan_centers centers;
1456
1457         if (IS_CHAN_HALF_RATE(chan))
1458                 clockMhzScaled = clockMhzScaled >> 1;
1459         else if (IS_CHAN_QUARTER_RATE(chan))
1460                 clockMhzScaled = clockMhzScaled >> 2;
1461
1462         ath9k_hw_get_channel_centers(ah, chan, &centers);
1463         coef_scaled = clockMhzScaled / centers.synth_center;
1464
1465         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1466                                       &ds_coef_exp);
1467
1468         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1469                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1470         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1471                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1472
1473         coef_scaled = (9 * coef_scaled) / 10;
1474
1475         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1476                                       &ds_coef_exp);
1477
1478         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1479                       AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1480         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1481                       AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1482 }
1483
1484 static bool ath9k_hw_set_reset(struct ath_hal *ah, int type)
1485 {
1486         u32 rst_flags;
1487         u32 tmpReg;
1488
1489         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1490                   AR_RTC_FORCE_WAKE_ON_INT);
1491
1492         if (AR_SREV_9100(ah)) {
1493                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1494                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1495         } else {
1496                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1497                 if (tmpReg &
1498                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
1499                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1500                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1501                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1502                 } else {
1503                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1504                 }
1505
1506                 rst_flags = AR_RTC_RC_MAC_WARM;
1507                 if (type == ATH9K_RESET_COLD)
1508                         rst_flags |= AR_RTC_RC_MAC_COLD;
1509         }
1510
1511         REG_WRITE(ah, AR_RTC_RC, rst_flags);
1512         udelay(50);
1513
1514         REG_WRITE(ah, AR_RTC_RC, 0);
1515         if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0)) {
1516                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1517                         "RTC stuck in MAC reset\n");
1518                 return false;
1519         }
1520
1521         if (!AR_SREV_9100(ah))
1522                 REG_WRITE(ah, AR_RC, 0);
1523
1524         ath9k_hw_init_pll(ah, NULL);
1525
1526         if (AR_SREV_9100(ah))
1527                 udelay(50);
1528
1529         return true;
1530 }
1531
1532 static bool ath9k_hw_set_reset_power_on(struct ath_hal *ah)
1533 {
1534         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1535                   AR_RTC_FORCE_WAKE_ON_INT);
1536
1537         REG_WRITE(ah, AR_RTC_RESET, 0);
1538         REG_WRITE(ah, AR_RTC_RESET, 1);
1539
1540         if (!ath9k_hw_wait(ah,
1541                            AR_RTC_STATUS,
1542                            AR_RTC_STATUS_M,
1543                            AR_RTC_STATUS_ON)) {
1544                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
1545                 return false;
1546         }
1547
1548         ath9k_hw_read_revisions(ah);
1549
1550         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1551 }
1552
1553 static bool ath9k_hw_set_reset_reg(struct ath_hal *ah, u32 type)
1554 {
1555         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1556                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1557
1558         switch (type) {
1559         case ATH9K_RESET_POWER_ON:
1560                 return ath9k_hw_set_reset_power_on(ah);
1561                 break;
1562         case ATH9K_RESET_WARM:
1563         case ATH9K_RESET_COLD:
1564                 return ath9k_hw_set_reset(ah, type);
1565                 break;
1566         default:
1567                 return false;
1568         }
1569 }
1570
1571 static void ath9k_hw_set_regs(struct ath_hal *ah, struct ath9k_channel *chan,
1572                               enum ath9k_ht_macmode macmode)
1573 {
1574         u32 phymode;
1575         u32 enableDacFifo = 0;
1576         struct ath_hal_5416 *ahp = AH5416(ah);
1577
1578         if (AR_SREV_9285_10_OR_LATER(ah))
1579                 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1580                                          AR_PHY_FC_ENABLE_DAC_FIFO);
1581
1582         phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1583                 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1584
1585         if (IS_CHAN_HT40(chan)) {
1586                 phymode |= AR_PHY_FC_DYN2040_EN;
1587
1588                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1589                     (chan->chanmode == CHANNEL_G_HT40PLUS))
1590                         phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1591
1592                 if (ahp->ah_extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1593                         phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1594         }
1595         REG_WRITE(ah, AR_PHY_TURBO, phymode);
1596
1597         ath9k_hw_set11nmac2040(ah, macmode);
1598
1599         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1600         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1601 }
1602
1603 static bool ath9k_hw_chip_reset(struct ath_hal *ah,
1604                                 struct ath9k_channel *chan)
1605 {
1606         struct ath_hal_5416 *ahp = AH5416(ah);
1607
1608         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1609                 return false;
1610
1611         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1612                 return false;
1613
1614         ahp->ah_chipFullSleep = false;
1615
1616         ath9k_hw_init_pll(ah, chan);
1617
1618         ath9k_hw_set_rfmode(ah, chan);
1619
1620         return true;
1621 }
1622
1623 static bool ath9k_hw_channel_change(struct ath_hal *ah,
1624                                     struct ath9k_channel *chan,
1625                                     enum ath9k_ht_macmode macmode)
1626 {
1627         struct ieee80211_channel *channel = chan->chan;
1628         u32 synthDelay, qnum;
1629
1630         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1631                 if (ath9k_hw_numtxpending(ah, qnum)) {
1632                         DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1633                                 "Transmit frames pending on queue %d\n", qnum);
1634                         return false;
1635                 }
1636         }
1637
1638         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1639         if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1640                            AR_PHY_RFBUS_GRANT_EN)) {
1641                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
1642                         "Could not kill baseband RX\n");
1643                 return false;
1644         }
1645
1646         ath9k_hw_set_regs(ah, chan, macmode);
1647
1648         if (AR_SREV_9280_10_OR_LATER(ah)) {
1649                 if (!(ath9k_hw_ar9280_set_channel(ah, chan))) {
1650                         DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1651                                 "failed to set channel\n");
1652                         return false;
1653                 }
1654         } else {
1655                 if (!(ath9k_hw_set_channel(ah, chan))) {
1656                         DPRINTF(ah->ah_sc, ATH_DBG_CHANNEL,
1657                                 "failed to set channel\n");
1658                         return false;
1659                 }
1660         }
1661
1662         if (ath9k_hw_set_txpower(ah, chan,
1663                                  ath9k_regd_get_ctl(ah, chan),
1664                                  channel->max_antenna_gain * 2,
1665                                  channel->max_power * 2,
1666                                  min((u32) MAX_RATE_POWER,
1667                                      (u32) ah->regulatory.power_limit)) != 0) {
1668                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1669                         "error init'ing transmit power\n");
1670                 return false;
1671         }
1672
1673         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1674         if (IS_CHAN_B(chan))
1675                 synthDelay = (4 * synthDelay) / 22;
1676         else
1677                 synthDelay /= 10;
1678
1679         udelay(synthDelay + BASE_ACTIVATE_DELAY);
1680
1681         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1682
1683         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1684                 ath9k_hw_set_delta_slope(ah, chan);
1685
1686         if (AR_SREV_9280_10_OR_LATER(ah))
1687                 ath9k_hw_9280_spur_mitigate(ah, chan);
1688         else
1689                 ath9k_hw_spur_mitigate(ah, chan);
1690
1691         if (!chan->oneTimeCalsDone)
1692                 chan->oneTimeCalsDone = true;
1693
1694         return true;
1695 }
1696
1697 static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan)
1698 {
1699         int bb_spur = AR_NO_SPUR;
1700         int freq;
1701         int bin, cur_bin;
1702         int bb_spur_off, spur_subchannel_sd;
1703         int spur_freq_sd;
1704         int spur_delta_phase;
1705         int denominator;
1706         int upper, lower, cur_vit_mask;
1707         int tmp, newVal;
1708         int i;
1709         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1710                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1711         };
1712         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1713                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1714         };
1715         int inc[4] = { 0, 100, 0, 0 };
1716         struct chan_centers centers;
1717
1718         int8_t mask_m[123];
1719         int8_t mask_p[123];
1720         int8_t mask_amt;
1721         int tmp_mask;
1722         int cur_bb_spur;
1723         bool is2GHz = IS_CHAN_2GHZ(chan);
1724
1725         memset(&mask_m, 0, sizeof(int8_t) * 123);
1726         memset(&mask_p, 0, sizeof(int8_t) * 123);
1727
1728         ath9k_hw_get_channel_centers(ah, chan, &centers);
1729         freq = centers.synth_center;
1730
1731         ah->ah_config.spurmode = SPUR_ENABLE_EEPROM;
1732         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1733                 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
1734
1735                 if (is2GHz)
1736                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1737                 else
1738                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1739
1740                 if (AR_NO_SPUR == cur_bb_spur)
1741                         break;
1742                 cur_bb_spur = cur_bb_spur - freq;
1743
1744                 if (IS_CHAN_HT40(chan)) {
1745                         if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1746                             (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1747                                 bb_spur = cur_bb_spur;
1748                                 break;
1749                         }
1750                 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1751                            (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1752                         bb_spur = cur_bb_spur;
1753                         break;
1754                 }
1755         }
1756
1757         if (AR_NO_SPUR == bb_spur) {
1758                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1759                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1760                 return;
1761         } else {
1762                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1763                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1764         }
1765
1766         bin = bb_spur * 320;
1767
1768         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1769
1770         newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1771                         AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1772                         AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1773                         AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1774         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1775
1776         newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1777                   AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1778                   AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1779                   AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1780                   SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1781         REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1782
1783         if (IS_CHAN_HT40(chan)) {
1784                 if (bb_spur < 0) {
1785                         spur_subchannel_sd = 1;
1786                         bb_spur_off = bb_spur + 10;
1787                 } else {
1788                         spur_subchannel_sd = 0;
1789                         bb_spur_off = bb_spur - 10;
1790                 }
1791         } else {
1792                 spur_subchannel_sd = 0;
1793                 bb_spur_off = bb_spur;
1794         }
1795
1796         if (IS_CHAN_HT40(chan))
1797                 spur_delta_phase =
1798                         ((bb_spur * 262144) /
1799                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1800         else
1801                 spur_delta_phase =
1802                         ((bb_spur * 524288) /
1803                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1804
1805         denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1806         spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1807
1808         newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1809                   SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1810                   SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1811         REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1812
1813         newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1814         REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1815
1816         cur_bin = -6000;
1817         upper = bin + 100;
1818         lower = bin - 100;
1819
1820         for (i = 0; i < 4; i++) {
1821                 int pilot_mask = 0;
1822                 int chan_mask = 0;
1823                 int bp = 0;
1824                 for (bp = 0; bp < 30; bp++) {
1825                         if ((cur_bin > lower) && (cur_bin < upper)) {
1826                                 pilot_mask = pilot_mask | 0x1 << bp;
1827                                 chan_mask = chan_mask | 0x1 << bp;
1828                         }
1829                         cur_bin += 100;
1830                 }
1831                 cur_bin += inc[i];
1832                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1833                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1834         }
1835
1836         cur_vit_mask = 6100;
1837         upper = bin + 120;
1838         lower = bin - 120;
1839
1840         for (i = 0; i < 123; i++) {
1841                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1842
1843                         /* workaround for gcc bug #37014 */
1844                         volatile int tmp_v = abs(cur_vit_mask - bin);
1845
1846                         if (tmp_v < 75)
1847                                 mask_amt = 1;
1848                         else
1849                                 mask_amt = 0;
1850                         if (cur_vit_mask < 0)
1851                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1852                         else
1853                                 mask_p[cur_vit_mask / 100] = mask_amt;
1854                 }
1855                 cur_vit_mask -= 100;
1856         }
1857
1858         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1859                 | (mask_m[48] << 26) | (mask_m[49] << 24)
1860                 | (mask_m[50] << 22) | (mask_m[51] << 20)
1861                 | (mask_m[52] << 18) | (mask_m[53] << 16)
1862                 | (mask_m[54] << 14) | (mask_m[55] << 12)
1863                 | (mask_m[56] << 10) | (mask_m[57] << 8)
1864                 | (mask_m[58] << 6) | (mask_m[59] << 4)
1865                 | (mask_m[60] << 2) | (mask_m[61] << 0);
1866         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1867         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1868
1869         tmp_mask = (mask_m[31] << 28)
1870                 | (mask_m[32] << 26) | (mask_m[33] << 24)
1871                 | (mask_m[34] << 22) | (mask_m[35] << 20)
1872                 | (mask_m[36] << 18) | (mask_m[37] << 16)
1873                 | (mask_m[48] << 14) | (mask_m[39] << 12)
1874                 | (mask_m[40] << 10) | (mask_m[41] << 8)
1875                 | (mask_m[42] << 6) | (mask_m[43] << 4)
1876                 | (mask_m[44] << 2) | (mask_m[45] << 0);
1877         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1878         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1879
1880         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1881                 | (mask_m[18] << 26) | (mask_m[18] << 24)
1882                 | (mask_m[20] << 22) | (mask_m[20] << 20)
1883                 | (mask_m[22] << 18) | (mask_m[22] << 16)
1884                 | (mask_m[24] << 14) | (mask_m[24] << 12)
1885                 | (mask_m[25] << 10) | (mask_m[26] << 8)
1886                 | (mask_m[27] << 6) | (mask_m[28] << 4)
1887                 | (mask_m[29] << 2) | (mask_m[30] << 0);
1888         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1889         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1890
1891         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1892                 | (mask_m[2] << 26) | (mask_m[3] << 24)
1893                 | (mask_m[4] << 22) | (mask_m[5] << 20)
1894                 | (mask_m[6] << 18) | (mask_m[7] << 16)
1895                 | (mask_m[8] << 14) | (mask_m[9] << 12)
1896                 | (mask_m[10] << 10) | (mask_m[11] << 8)
1897                 | (mask_m[12] << 6) | (mask_m[13] << 4)
1898                 | (mask_m[14] << 2) | (mask_m[15] << 0);
1899         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
1900         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
1901
1902         tmp_mask = (mask_p[15] << 28)
1903                 | (mask_p[14] << 26) | (mask_p[13] << 24)
1904                 | (mask_p[12] << 22) | (mask_p[11] << 20)
1905                 | (mask_p[10] << 18) | (mask_p[9] << 16)
1906                 | (mask_p[8] << 14) | (mask_p[7] << 12)
1907                 | (mask_p[6] << 10) | (mask_p[5] << 8)
1908                 | (mask_p[4] << 6) | (mask_p[3] << 4)
1909                 | (mask_p[2] << 2) | (mask_p[1] << 0);
1910         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
1911         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
1912
1913         tmp_mask = (mask_p[30] << 28)
1914                 | (mask_p[29] << 26) | (mask_p[28] << 24)
1915                 | (mask_p[27] << 22) | (mask_p[26] << 20)
1916                 | (mask_p[25] << 18) | (mask_p[24] << 16)
1917                 | (mask_p[23] << 14) | (mask_p[22] << 12)
1918                 | (mask_p[21] << 10) | (mask_p[20] << 8)
1919                 | (mask_p[19] << 6) | (mask_p[18] << 4)
1920                 | (mask_p[17] << 2) | (mask_p[16] << 0);
1921         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
1922         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
1923
1924         tmp_mask = (mask_p[45] << 28)
1925                 | (mask_p[44] << 26) | (mask_p[43] << 24)
1926                 | (mask_p[42] << 22) | (mask_p[41] << 20)
1927                 | (mask_p[40] << 18) | (mask_p[39] << 16)
1928                 | (mask_p[38] << 14) | (mask_p[37] << 12)
1929                 | (mask_p[36] << 10) | (mask_p[35] << 8)
1930                 | (mask_p[34] << 6) | (mask_p[33] << 4)
1931                 | (mask_p[32] << 2) | (mask_p[31] << 0);
1932         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
1933         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
1934
1935         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
1936                 | (mask_p[59] << 26) | (mask_p[58] << 24)
1937                 | (mask_p[57] << 22) | (mask_p[56] << 20)
1938                 | (mask_p[55] << 18) | (mask_p[54] << 16)
1939                 | (mask_p[53] << 14) | (mask_p[52] << 12)
1940                 | (mask_p[51] << 10) | (mask_p[50] << 8)
1941                 | (mask_p[49] << 6) | (mask_p[48] << 4)
1942                 | (mask_p[47] << 2) | (mask_p[46] << 0);
1943         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
1944         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
1945 }
1946
1947 static void ath9k_hw_spur_mitigate(struct ath_hal *ah, struct ath9k_channel *chan)
1948 {
1949         int bb_spur = AR_NO_SPUR;
1950         int bin, cur_bin;
1951         int spur_freq_sd;
1952         int spur_delta_phase;
1953         int denominator;
1954         int upper, lower, cur_vit_mask;
1955         int tmp, new;
1956         int i;
1957         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1958                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1959         };
1960         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1961                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1962         };
1963         int inc[4] = { 0, 100, 0, 0 };
1964
1965         int8_t mask_m[123];
1966         int8_t mask_p[123];
1967         int8_t mask_amt;
1968         int tmp_mask;
1969         int cur_bb_spur;
1970         bool is2GHz = IS_CHAN_2GHZ(chan);
1971
1972         memset(&mask_m, 0, sizeof(int8_t) * 123);
1973         memset(&mask_p, 0, sizeof(int8_t) * 123);
1974
1975         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1976                 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
1977                 if (AR_NO_SPUR == cur_bb_spur)
1978                         break;
1979                 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
1980                 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
1981                         bb_spur = cur_bb_spur;
1982                         break;
1983                 }
1984         }
1985
1986         if (AR_NO_SPUR == bb_spur)
1987                 return;
1988
1989         bin = bb_spur * 32;
1990
1991         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1992         new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1993                      AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1994                      AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1995                      AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1996
1997         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
1998
1999         new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2000                AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2001                AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2002                AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2003                SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2004         REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2005
2006         spur_delta_phase = ((bb_spur * 524288) / 100) &
2007                 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2008
2009         denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2010         spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2011
2012         new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2013                SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2014                SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2015         REG_WRITE(ah, AR_PHY_TIMING11, new);
2016
2017         cur_bin = -6000;
2018         upper = bin + 100;
2019         lower = bin - 100;
2020
2021         for (i = 0; i < 4; i++) {
2022                 int pilot_mask = 0;
2023                 int chan_mask = 0;
2024                 int bp = 0;
2025                 for (bp = 0; bp < 30; bp++) {
2026                         if ((cur_bin > lower) && (cur_bin < upper)) {
2027                                 pilot_mask = pilot_mask | 0x1 << bp;
2028                                 chan_mask = chan_mask | 0x1 << bp;
2029                         }
2030                         cur_bin += 100;
2031                 }
2032                 cur_bin += inc[i];
2033                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2034                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2035         }
2036
2037         cur_vit_mask = 6100;
2038         upper = bin + 120;
2039         lower = bin - 120;
2040
2041         for (i = 0; i < 123; i++) {
2042                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2043
2044                         /* workaround for gcc bug #37014 */
2045                         volatile int tmp_v = abs(cur_vit_mask - bin);
2046
2047                         if (tmp_v < 75)
2048                                 mask_amt = 1;
2049                         else
2050                                 mask_amt = 0;
2051                         if (cur_vit_mask < 0)
2052                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2053                         else
2054                                 mask_p[cur_vit_mask / 100] = mask_amt;
2055                 }
2056                 cur_vit_mask -= 100;
2057         }
2058
2059         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2060                 | (mask_m[48] << 26) | (mask_m[49] << 24)
2061                 | (mask_m[50] << 22) | (mask_m[51] << 20)
2062                 | (mask_m[52] << 18) | (mask_m[53] << 16)
2063                 | (mask_m[54] << 14) | (mask_m[55] << 12)
2064                 | (mask_m[56] << 10) | (mask_m[57] << 8)
2065                 | (mask_m[58] << 6) | (mask_m[59] << 4)
2066                 | (mask_m[60] << 2) | (mask_m[61] << 0);
2067         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2068         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2069
2070         tmp_mask = (mask_m[31] << 28)
2071                 | (mask_m[32] << 26) | (mask_m[33] << 24)
2072                 | (mask_m[34] << 22) | (mask_m[35] << 20)
2073                 | (mask_m[36] << 18) | (mask_m[37] << 16)
2074                 | (mask_m[48] << 14) | (mask_m[39] << 12)
2075                 | (mask_m[40] << 10) | (mask_m[41] << 8)
2076                 | (mask_m[42] << 6) | (mask_m[43] << 4)
2077                 | (mask_m[44] << 2) | (mask_m[45] << 0);
2078         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2079         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2080
2081         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2082                 | (mask_m[18] << 26) | (mask_m[18] << 24)
2083                 | (mask_m[20] << 22) | (mask_m[20] << 20)
2084                 | (mask_m[22] << 18) | (mask_m[22] << 16)
2085                 | (mask_m[24] << 14) | (mask_m[24] << 12)
2086                 | (mask_m[25] << 10) | (mask_m[26] << 8)
2087                 | (mask_m[27] << 6) | (mask_m[28] << 4)
2088                 | (mask_m[29] << 2) | (mask_m[30] << 0);
2089         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2090         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2091
2092         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2093                 | (mask_m[2] << 26) | (mask_m[3] << 24)
2094                 | (mask_m[4] << 22) | (mask_m[5] << 20)
2095                 | (mask_m[6] << 18) | (mask_m[7] << 16)
2096                 | (mask_m[8] << 14) | (mask_m[9] << 12)
2097                 | (mask_m[10] << 10) | (mask_m[11] << 8)
2098                 | (mask_m[12] << 6) | (mask_m[13] << 4)
2099                 | (mask_m[14] << 2) | (mask_m[15] << 0);
2100         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2101         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2102
2103         tmp_mask = (mask_p[15] << 28)
2104                 | (mask_p[14] << 26) | (mask_p[13] << 24)
2105                 | (mask_p[12] << 22) | (mask_p[11] << 20)
2106                 | (mask_p[10] << 18) | (mask_p[9] << 16)
2107                 | (mask_p[8] << 14) | (mask_p[7] << 12)
2108                 | (mask_p[6] << 10) | (mask_p[5] << 8)
2109                 | (mask_p[4] << 6) | (mask_p[3] << 4)
2110                 | (mask_p[2] << 2) | (mask_p[1] << 0);
2111         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2112         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2113
2114         tmp_mask = (mask_p[30] << 28)
2115                 | (mask_p[29] << 26) | (mask_p[28] << 24)
2116                 | (mask_p[27] << 22) | (mask_p[26] << 20)
2117                 | (mask_p[25] << 18) | (mask_p[24] << 16)
2118                 | (mask_p[23] << 14) | (mask_p[22] << 12)
2119                 | (mask_p[21] << 10) | (mask_p[20] << 8)
2120                 | (mask_p[19] << 6) | (mask_p[18] << 4)
2121                 | (mask_p[17] << 2) | (mask_p[16] << 0);
2122         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2123         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2124
2125         tmp_mask = (mask_p[45] << 28)
2126                 | (mask_p[44] << 26) | (mask_p[43] << 24)
2127                 | (mask_p[42] << 22) | (mask_p[41] << 20)
2128                 | (mask_p[40] << 18) | (mask_p[39] << 16)
2129                 | (mask_p[38] << 14) | (mask_p[37] << 12)
2130                 | (mask_p[36] << 10) | (mask_p[35] << 8)
2131                 | (mask_p[34] << 6) | (mask_p[33] << 4)
2132                 | (mask_p[32] << 2) | (mask_p[31] << 0);
2133         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2134         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2135
2136         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2137                 | (mask_p[59] << 26) | (mask_p[58] << 24)
2138                 | (mask_p[57] << 22) | (mask_p[56] << 20)
2139                 | (mask_p[55] << 18) | (mask_p[54] << 16)
2140                 | (mask_p[53] << 14) | (mask_p[52] << 12)
2141                 | (mask_p[51] << 10) | (mask_p[50] << 8)
2142                 | (mask_p[49] << 6) | (mask_p[48] << 4)
2143                 | (mask_p[47] << 2) | (mask_p[46] << 0);
2144         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2145         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2146 }
2147
2148 int ath9k_hw_reset(struct ath_hal *ah, struct ath9k_channel *chan,
2149                     bool bChannelChange)
2150 {
2151         u32 saveLedState;
2152         struct ath_softc *sc = ah->ah_sc;
2153         struct ath_hal_5416 *ahp = AH5416(ah);
2154         struct ath9k_channel *curchan = ah->ah_curchan;
2155         u32 saveDefAntenna;
2156         u32 macStaId1;
2157         int i, rx_chainmask, r;
2158
2159         ahp->ah_extprotspacing = sc->ht_extprotspacing;
2160         ahp->ah_txchainmask = sc->tx_chainmask;
2161         ahp->ah_rxchainmask = sc->rx_chainmask;
2162
2163         if (AR_SREV_9285(ah)) {
2164                 ahp->ah_txchainmask &= 0x1;
2165                 ahp->ah_rxchainmask &= 0x1;
2166         } else if (AR_SREV_9280(ah)) {
2167                 ahp->ah_txchainmask &= 0x3;
2168                 ahp->ah_rxchainmask &= 0x3;
2169         }
2170
2171         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2172                 return -EIO;
2173
2174         if (curchan)
2175                 ath9k_hw_getnf(ah, curchan);
2176
2177         if (bChannelChange &&
2178             (ahp->ah_chipFullSleep != true) &&
2179             (ah->ah_curchan != NULL) &&
2180             (chan->channel != ah->ah_curchan->channel) &&
2181             ((chan->channelFlags & CHANNEL_ALL) ==
2182              (ah->ah_curchan->channelFlags & CHANNEL_ALL)) &&
2183             (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2184                                    !IS_CHAN_A_5MHZ_SPACED(ah->ah_curchan)))) {
2185
2186                 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
2187                         ath9k_hw_loadnf(ah, ah->ah_curchan);
2188                         ath9k_hw_start_nfcal(ah);
2189                         return 0;
2190                 }
2191         }
2192
2193         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2194         if (saveDefAntenna == 0)
2195                 saveDefAntenna = 1;
2196
2197         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2198
2199         saveLedState = REG_READ(ah, AR_CFG_LED) &
2200                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2201                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2202
2203         ath9k_hw_mark_phy_inactive(ah);
2204
2205         if (!ath9k_hw_chip_reset(ah, chan)) {
2206                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "chip reset failed\n");
2207                 return -EINVAL;
2208         }
2209
2210         if (AR_SREV_9280_10_OR_LATER(ah))
2211                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
2212
2213         r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
2214         if (r)
2215                 return r;
2216
2217         /* Setup MFP options for CCMP */
2218         if (AR_SREV_9280_20_OR_LATER(ah)) {
2219                 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2220                  * frames when constructing CCMP AAD. */
2221                 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2222                               0xc7ff);
2223                 ah->sw_mgmt_crypto = false;
2224         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2225                 /* Disable hardware crypto for management frames */
2226                 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2227                             AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2228                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2229                             AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2230                 ah->sw_mgmt_crypto = true;
2231         } else
2232                 ah->sw_mgmt_crypto = true;
2233
2234         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2235                 ath9k_hw_set_delta_slope(ah, chan);
2236
2237         if (AR_SREV_9280_10_OR_LATER(ah))
2238                 ath9k_hw_9280_spur_mitigate(ah, chan);
2239         else
2240                 ath9k_hw_spur_mitigate(ah, chan);
2241
2242         if (!ath9k_hw_eeprom_set_board_values(ah, chan)) {
2243                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2244                         "error setting board options\n");
2245                 return -EIO;
2246         }
2247
2248         ath9k_hw_decrease_chain_power(ah, chan);
2249
2250         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ah->macaddr));
2251         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ah->macaddr + 4)
2252                   | macStaId1
2253                   | AR_STA_ID1_RTS_USE_DEF
2254                   | (ah->ah_config.
2255                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2256                   | ahp->ah_staId1Defaults);
2257         ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
2258
2259         REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
2260         REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
2261
2262         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2263
2264         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
2265         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
2266                   ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2267
2268         REG_WRITE(ah, AR_ISR, ~0);
2269
2270         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2271
2272         if (AR_SREV_9280_10_OR_LATER(ah)) {
2273                 if (!(ath9k_hw_ar9280_set_channel(ah, chan)))
2274                         return -EIO;
2275         } else {
2276                 if (!(ath9k_hw_set_channel(ah, chan)))
2277                         return -EIO;
2278         }
2279
2280         for (i = 0; i < AR_NUM_DCU; i++)
2281                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2282
2283         ahp->ah_intrTxqs = 0;
2284         for (i = 0; i < ah->ah_caps.total_queues; i++)
2285                 ath9k_hw_resettxqueue(ah, i);
2286
2287         ath9k_hw_init_interrupt_masks(ah, ah->ah_opmode);
2288         ath9k_hw_init_qos(ah);
2289
2290 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2291         if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2292                 ath9k_enable_rfkill(ah);
2293 #endif
2294         ath9k_hw_init_user_settings(ah);
2295
2296         REG_WRITE(ah, AR_STA_ID1,
2297                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2298
2299         ath9k_hw_set_dma(ah);
2300
2301         REG_WRITE(ah, AR_OBS, 8);
2302
2303         if (ahp->ah_intrMitigation) {
2304
2305                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2306                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2307         }
2308
2309         ath9k_hw_init_bb(ah, chan);
2310
2311         if (!ath9k_hw_init_cal(ah, chan))
2312                 return -EIO;;
2313
2314         rx_chainmask = ahp->ah_rxchainmask;
2315         if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2316                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2317                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2318         }
2319
2320         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2321
2322         if (AR_SREV_9100(ah)) {
2323                 u32 mask;
2324                 mask = REG_READ(ah, AR_CFG);
2325                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2326                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2327                                 "CFG Byte Swap Set 0x%x\n", mask);
2328                 } else {
2329                         mask =
2330                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2331                         REG_WRITE(ah, AR_CFG, mask);
2332                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2333                                 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2334                 }
2335         } else {
2336 #ifdef __BIG_ENDIAN
2337                 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2338 #endif
2339         }
2340
2341         return 0;
2342 }
2343
2344 /************************/
2345 /* Key Cache Management */
2346 /************************/
2347
2348 bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry)
2349 {
2350         u32 keyType;
2351
2352         if (entry >= ah->ah_caps.keycache_size) {
2353                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2354                         "entry %u out of range\n", entry);
2355                 return false;
2356         }
2357
2358         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2359
2360         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2361         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2362         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2363         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2364         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2365         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2366         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2367         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2368
2369         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2370                 u16 micentry = entry + 64;
2371
2372                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2373                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2374                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2375                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2376
2377         }
2378
2379         if (ah->ah_curchan == NULL)
2380                 return true;
2381
2382         return true;
2383 }
2384
2385 bool ath9k_hw_keysetmac(struct ath_hal *ah, u16 entry, const u8 *mac)
2386 {
2387         u32 macHi, macLo;
2388
2389         if (entry >= ah->ah_caps.keycache_size) {
2390                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2391                         "entry %u out of range\n", entry);
2392                 return false;
2393         }
2394
2395         if (mac != NULL) {
2396                 macHi = (mac[5] << 8) | mac[4];
2397                 macLo = (mac[3] << 24) |
2398                         (mac[2] << 16) |
2399                         (mac[1] << 8) |
2400                         mac[0];
2401                 macLo >>= 1;
2402                 macLo |= (macHi & 1) << 31;
2403                 macHi >>= 1;
2404         } else {
2405                 macLo = macHi = 0;
2406         }
2407         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2408         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2409
2410         return true;
2411 }
2412
2413 bool ath9k_hw_set_keycache_entry(struct ath_hal *ah, u16 entry,
2414                                  const struct ath9k_keyval *k,
2415                                  const u8 *mac, int xorKey)
2416 {
2417         const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2418         u32 key0, key1, key2, key3, key4;
2419         u32 keyType;
2420         u32 xorMask = xorKey ?
2421                 (ATH9K_KEY_XOR << 24 | ATH9K_KEY_XOR << 16 | ATH9K_KEY_XOR << 8
2422                  | ATH9K_KEY_XOR) : 0;
2423         struct ath_hal_5416 *ahp = AH5416(ah);
2424
2425         if (entry >= pCap->keycache_size) {
2426                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2427                         "entry %u out of range\n", entry);
2428                 return false;
2429         }
2430
2431         switch (k->kv_type) {
2432         case ATH9K_CIPHER_AES_OCB:
2433                 keyType = AR_KEYTABLE_TYPE_AES;
2434                 break;
2435         case ATH9K_CIPHER_AES_CCM:
2436                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2437                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2438                                 "AES-CCM not supported by mac rev 0x%x\n",
2439                                 ah->hw_version.macRev);
2440                         return false;
2441                 }
2442                 keyType = AR_KEYTABLE_TYPE_CCM;
2443                 break;
2444         case ATH9K_CIPHER_TKIP:
2445                 keyType = AR_KEYTABLE_TYPE_TKIP;
2446                 if (ATH9K_IS_MIC_ENABLED(ah)
2447                     && entry + 64 >= pCap->keycache_size) {
2448                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2449                                 "entry %u inappropriate for TKIP\n", entry);
2450                         return false;
2451                 }
2452                 break;
2453         case ATH9K_CIPHER_WEP:
2454                 if (k->kv_len < LEN_WEP40) {
2455                         DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2456                                 "WEP key length %u too small\n", k->kv_len);
2457                         return false;
2458                 }
2459                 if (k->kv_len <= LEN_WEP40)
2460                         keyType = AR_KEYTABLE_TYPE_40;
2461                 else if (k->kv_len <= LEN_WEP104)
2462                         keyType = AR_KEYTABLE_TYPE_104;
2463                 else
2464                         keyType = AR_KEYTABLE_TYPE_128;
2465                 break;
2466         case ATH9K_CIPHER_CLR:
2467                 keyType = AR_KEYTABLE_TYPE_CLR;
2468                 break;
2469         default:
2470                 DPRINTF(ah->ah_sc, ATH_DBG_KEYCACHE,
2471                         "cipher %u not supported\n", k->kv_type);
2472                 return false;
2473         }
2474
2475         key0 = get_unaligned_le32(k->kv_val + 0) ^ xorMask;
2476         key1 = (get_unaligned_le16(k->kv_val + 4) ^ xorMask) & 0xffff;
2477         key2 = get_unaligned_le32(k->kv_val + 6) ^ xorMask;
2478         key3 = (get_unaligned_le16(k->kv_val + 10) ^ xorMask) & 0xffff;
2479         key4 = get_unaligned_le32(k->kv_val + 12) ^ xorMask;
2480         if (k->kv_len <= LEN_WEP104)
2481                 key4 &= 0xff;
2482
2483         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2484                 u16 micentry = entry + 64;
2485
2486                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2487                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2488                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2489                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2490                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2491                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2492                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2493
2494                 if (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) {
2495                         u32 mic0, mic1, mic2, mic3, mic4;
2496
2497                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2498                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2499                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2500                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2501                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
2502                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2503                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2504                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2505                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2506                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2507                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2508                                   AR_KEYTABLE_TYPE_CLR);
2509
2510                 } else {
2511                         u32 mic0, mic2;
2512
2513                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2514                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2515                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2516                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2517                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2518                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2519                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2520                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2521                                   AR_KEYTABLE_TYPE_CLR);
2522                 }
2523                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2524                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2525                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2526                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2527         } else {
2528                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2529                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2530                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2531                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2532                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2533                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2534
2535                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2536         }
2537
2538         if (ah->ah_curchan == NULL)
2539                 return true;
2540
2541         return true;
2542 }
2543
2544 bool ath9k_hw_keyisvalid(struct ath_hal *ah, u16 entry)
2545 {
2546         if (entry < ah->ah_caps.keycache_size) {
2547                 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2548                 if (val & AR_KEYTABLE_VALID)
2549                         return true;
2550         }
2551         return false;
2552 }
2553
2554 /******************************/
2555 /* Power Management (Chipset) */
2556 /******************************/
2557
2558 static void ath9k_set_power_sleep(struct ath_hal *ah, int setChip)
2559 {
2560         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2561         if (setChip) {
2562                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2563                             AR_RTC_FORCE_WAKE_EN);
2564                 if (!AR_SREV_9100(ah))
2565                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2566
2567                 REG_CLR_BIT(ah, (AR_RTC_RESET),
2568                             AR_RTC_RESET_EN);
2569         }
2570 }
2571
2572 static void ath9k_set_power_network_sleep(struct ath_hal *ah, int setChip)
2573 {
2574         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2575         if (setChip) {
2576                 struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2577
2578                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2579                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2580                                   AR_RTC_FORCE_WAKE_ON_INT);
2581                 } else {
2582                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2583                                     AR_RTC_FORCE_WAKE_EN);
2584                 }
2585         }
2586 }
2587
2588 static bool ath9k_hw_set_power_awake(struct ath_hal *ah,
2589                                      int setChip)
2590 {
2591         u32 val;
2592         int i;
2593
2594         if (setChip) {
2595                 if ((REG_READ(ah, AR_RTC_STATUS) &
2596                      AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2597                         if (ath9k_hw_set_reset_reg(ah,
2598                                            ATH9K_RESET_POWER_ON) != true) {
2599                                 return false;
2600                         }
2601                 }
2602                 if (AR_SREV_9100(ah))
2603                         REG_SET_BIT(ah, AR_RTC_RESET,
2604                                     AR_RTC_RESET_EN);
2605
2606                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2607                             AR_RTC_FORCE_WAKE_EN);
2608                 udelay(50);
2609
2610                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2611                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2612                         if (val == AR_RTC_STATUS_ON)
2613                                 break;
2614                         udelay(50);
2615                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2616                                     AR_RTC_FORCE_WAKE_EN);
2617                 }
2618                 if (i == 0) {
2619                         DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2620                                 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
2621                         return false;
2622                 }
2623         }
2624
2625         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2626
2627         return true;
2628 }
2629
2630 bool ath9k_hw_setpower(struct ath_hal *ah,
2631                        enum ath9k_power_mode mode)
2632 {
2633         struct ath_hal_5416 *ahp = AH5416(ah);
2634         static const char *modes[] = {
2635                 "AWAKE",
2636                 "FULL-SLEEP",
2637                 "NETWORK SLEEP",
2638                 "UNDEFINED"
2639         };
2640         int status = true, setChip = true;
2641
2642         DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT, "%s -> %s (%s)\n",
2643                 modes[ah->ah_power_mode], modes[mode],
2644                 setChip ? "set chip " : "");
2645
2646         switch (mode) {
2647         case ATH9K_PM_AWAKE:
2648                 status = ath9k_hw_set_power_awake(ah, setChip);
2649                 break;
2650         case ATH9K_PM_FULL_SLEEP:
2651                 ath9k_set_power_sleep(ah, setChip);
2652                 ahp->ah_chipFullSleep = true;
2653                 break;
2654         case ATH9K_PM_NETWORK_SLEEP:
2655                 ath9k_set_power_network_sleep(ah, setChip);
2656                 break;
2657         default:
2658                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2659                         "Unknown power mode %u\n", mode);
2660                 return false;
2661         }
2662         ah->ah_power_mode = mode;
2663
2664         return status;
2665 }
2666
2667 void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore)
2668 {
2669         struct ath_hal_5416 *ahp = AH5416(ah);
2670         u8 i;
2671
2672         if (ah->ah_isPciExpress != true)
2673                 return;
2674
2675         if (ah->ah_config.pcie_powersave_enable == 2)
2676                 return;
2677
2678         if (restore)
2679                 return;
2680
2681         if (AR_SREV_9280_20_OR_LATER(ah)) {
2682                 for (i = 0; i < ahp->ah_iniPcieSerdes.ia_rows; i++) {
2683                         REG_WRITE(ah, INI_RA(&ahp->ah_iniPcieSerdes, i, 0),
2684                                   INI_RA(&ahp->ah_iniPcieSerdes, i, 1));
2685                 }
2686                 udelay(1000);
2687         } else if (AR_SREV_9280(ah) &&
2688                    (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2689                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2690                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2691
2692                 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2693                 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2694                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2695
2696                 if (ah->ah_config.pcie_clock_req)
2697                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2698                 else
2699                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2700
2701                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2702                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2703                 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2704
2705                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2706
2707                 udelay(1000);
2708         } else {
2709                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2710                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2711                 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2712                 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2713                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2714                 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2715                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2716                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2717                 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2718                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2719         }
2720
2721         REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2722
2723         if (ah->ah_config.pcie_waen) {
2724                 REG_WRITE(ah, AR_WA, ah->ah_config.pcie_waen);
2725         } else {
2726                 if (AR_SREV_9285(ah))
2727                         REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
2728                 else if (AR_SREV_9280(ah))
2729                         REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
2730                 else
2731                         REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
2732         }
2733
2734 }
2735
2736 /**********************/
2737 /* Interrupt Handling */
2738 /**********************/
2739
2740 bool ath9k_hw_intrpend(struct ath_hal *ah)
2741 {
2742         u32 host_isr;
2743
2744         if (AR_SREV_9100(ah))
2745                 return true;
2746
2747         host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2748         if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2749                 return true;
2750
2751         host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2752         if ((host_isr & AR_INTR_SYNC_DEFAULT)
2753             && (host_isr != AR_INTR_SPURIOUS))
2754                 return true;
2755
2756         return false;
2757 }
2758
2759 bool ath9k_hw_getisr(struct ath_hal *ah, enum ath9k_int *masked)
2760 {
2761         u32 isr = 0;
2762         u32 mask2 = 0;
2763         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2764         u32 sync_cause = 0;
2765         bool fatal_int = false;
2766         struct ath_hal_5416 *ahp = AH5416(ah);
2767
2768         if (!AR_SREV_9100(ah)) {
2769                 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2770                         if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2771                             == AR_RTC_STATUS_ON) {
2772                                 isr = REG_READ(ah, AR_ISR);
2773                         }
2774                 }
2775
2776                 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2777                         AR_INTR_SYNC_DEFAULT;
2778
2779                 *masked = 0;
2780
2781                 if (!isr && !sync_cause)
2782                         return false;
2783         } else {
2784                 *masked = 0;
2785                 isr = REG_READ(ah, AR_ISR);
2786         }
2787
2788         if (isr) {
2789                 if (isr & AR_ISR_BCNMISC) {
2790                         u32 isr2;
2791                         isr2 = REG_READ(ah, AR_ISR_S2);
2792                         if (isr2 & AR_ISR_S2_TIM)
2793                                 mask2 |= ATH9K_INT_TIM;
2794                         if (isr2 & AR_ISR_S2_DTIM)
2795                                 mask2 |= ATH9K_INT_DTIM;
2796                         if (isr2 & AR_ISR_S2_DTIMSYNC)
2797                                 mask2 |= ATH9K_INT_DTIMSYNC;
2798                         if (isr2 & (AR_ISR_S2_CABEND))
2799                                 mask2 |= ATH9K_INT_CABEND;
2800                         if (isr2 & AR_ISR_S2_GTT)
2801                                 mask2 |= ATH9K_INT_GTT;
2802                         if (isr2 & AR_ISR_S2_CST)
2803                                 mask2 |= ATH9K_INT_CST;
2804                 }
2805
2806                 isr = REG_READ(ah, AR_ISR_RAC);
2807                 if (isr == 0xffffffff) {
2808                         *masked = 0;
2809                         return false;
2810                 }
2811
2812                 *masked = isr & ATH9K_INT_COMMON;
2813
2814                 if (ahp->ah_intrMitigation) {
2815                         if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2816                                 *masked |= ATH9K_INT_RX;
2817                 }
2818
2819                 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2820                         *masked |= ATH9K_INT_RX;
2821                 if (isr &
2822                     (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2823                      AR_ISR_TXEOL)) {
2824                         u32 s0_s, s1_s;
2825
2826                         *masked |= ATH9K_INT_TX;
2827
2828                         s0_s = REG_READ(ah, AR_ISR_S0_S);
2829                         ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2830                         ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2831
2832                         s1_s = REG_READ(ah, AR_ISR_S1_S);
2833                         ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2834                         ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2835                 }
2836
2837                 if (isr & AR_ISR_RXORN) {
2838                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2839                                 "receive FIFO overrun interrupt\n");
2840                 }
2841
2842                 if (!AR_SREV_9100(ah)) {
2843                         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2844                                 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2845                                 if (isr5 & AR_ISR_S5_TIM_TIMER)
2846                                         *masked |= ATH9K_INT_TIM_TIMER;
2847                         }
2848                 }
2849
2850                 *masked |= mask2;
2851         }
2852
2853         if (AR_SREV_9100(ah))
2854                 return true;
2855
2856         if (sync_cause) {
2857                 fatal_int =
2858                         (sync_cause &
2859                          (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2860                         ? true : false;
2861
2862                 if (fatal_int) {
2863                         if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2864                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2865                                         "received PCI FATAL interrupt\n");
2866                         }
2867                         if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2868                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2869                                         "received PCI PERR interrupt\n");
2870                         }
2871                 }
2872                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2873                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2874                                 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2875                         REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2876                         REG_WRITE(ah, AR_RC, 0);
2877                         *masked |= ATH9K_INT_FATAL;
2878                 }
2879                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2880                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2881                                 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
2882                 }
2883
2884                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2885                 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2886         }
2887
2888         return true;
2889 }
2890
2891 enum ath9k_int ath9k_hw_intrget(struct ath_hal *ah)
2892 {
2893         return AH5416(ah)->ah_maskReg;
2894 }
2895
2896 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum ath9k_int ints)
2897 {
2898         struct ath_hal_5416 *ahp = AH5416(ah);
2899         u32 omask = ahp->ah_maskReg;
2900         u32 mask, mask2;
2901         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
2902
2903         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
2904
2905         if (omask & ATH9K_INT_GLOBAL) {
2906                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
2907                 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
2908                 (void) REG_READ(ah, AR_IER);
2909                 if (!AR_SREV_9100(ah)) {
2910                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
2911                         (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
2912
2913                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
2914                         (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
2915                 }
2916         }
2917
2918         mask = ints & ATH9K_INT_COMMON;
2919         mask2 = 0;
2920
2921         if (ints & ATH9K_INT_TX) {
2922                 if (ahp->ah_txOkInterruptMask)
2923                         mask |= AR_IMR_TXOK;
2924                 if (ahp->ah_txDescInterruptMask)
2925                         mask |= AR_IMR_TXDESC;
2926                 if (ahp->ah_txErrInterruptMask)
2927                         mask |= AR_IMR_TXERR;
2928                 if (ahp->ah_txEolInterruptMask)
2929                         mask |= AR_IMR_TXEOL;
2930         }
2931         if (ints & ATH9K_INT_RX) {
2932                 mask |= AR_IMR_RXERR;
2933                 if (ahp->ah_intrMitigation)
2934                         mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
2935                 else
2936                         mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
2937                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
2938                         mask |= AR_IMR_GENTMR;
2939         }
2940
2941         if (ints & (ATH9K_INT_BMISC)) {
2942                 mask |= AR_IMR_BCNMISC;
2943                 if (ints & ATH9K_INT_TIM)
2944                         mask2 |= AR_IMR_S2_TIM;
2945                 if (ints & ATH9K_INT_DTIM)
2946                         mask2 |= AR_IMR_S2_DTIM;
2947                 if (ints & ATH9K_INT_DTIMSYNC)
2948                         mask2 |= AR_IMR_S2_DTIMSYNC;
2949                 if (ints & ATH9K_INT_CABEND)
2950                         mask2 |= (AR_IMR_S2_CABEND);
2951         }
2952
2953         if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
2954                 mask |= AR_IMR_BCNMISC;
2955                 if (ints & ATH9K_INT_GTT)
2956                         mask2 |= AR_IMR_S2_GTT;
2957                 if (ints & ATH9K_INT_CST)
2958                         mask2 |= AR_IMR_S2_CST;
2959         }
2960
2961         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
2962         REG_WRITE(ah, AR_IMR, mask);
2963         mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
2964                                            AR_IMR_S2_DTIM |
2965                                            AR_IMR_S2_DTIMSYNC |
2966                                            AR_IMR_S2_CABEND |
2967                                            AR_IMR_S2_CABTO |
2968                                            AR_IMR_S2_TSFOOR |
2969                                            AR_IMR_S2_GTT | AR_IMR_S2_CST);
2970         REG_WRITE(ah, AR_IMR_S2, mask | mask2);
2971         ahp->ah_maskReg = ints;
2972
2973         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2974                 if (ints & ATH9K_INT_TIM_TIMER)
2975                         REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2976                 else
2977                         REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2978         }
2979
2980         if (ints & ATH9K_INT_GLOBAL) {
2981                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
2982                 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
2983                 if (!AR_SREV_9100(ah)) {
2984                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
2985                                   AR_INTR_MAC_IRQ);
2986                         REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
2987
2988
2989                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
2990                                   AR_INTR_SYNC_DEFAULT);
2991                         REG_WRITE(ah, AR_INTR_SYNC_MASK,
2992                                   AR_INTR_SYNC_DEFAULT);
2993                 }
2994                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
2995                          REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
2996         }
2997
2998         return omask;
2999 }
3000
3001 /*******************/
3002 /* Beacon Handling */
3003 /*******************/
3004
3005 void ath9k_hw_beaconinit(struct ath_hal *ah, u32 next_beacon, u32 beacon_period)
3006 {
3007         struct ath_hal_5416 *ahp = AH5416(ah);
3008         int flags = 0;
3009
3010         ahp->ah_beaconInterval = beacon_period;
3011
3012         switch (ah->ah_opmode) {
3013         case NL80211_IFTYPE_STATION:
3014         case NL80211_IFTYPE_MONITOR:
3015                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3016                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3017                 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3018                 flags |= AR_TBTT_TIMER_EN;
3019                 break;
3020         case NL80211_IFTYPE_ADHOC:
3021                 REG_SET_BIT(ah, AR_TXCFG,
3022                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3023                 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3024                           TU_TO_USEC(next_beacon +
3025                                      (ahp->ah_atimWindow ? ahp->
3026                                       ah_atimWindow : 1)));
3027                 flags |= AR_NDP_TIMER_EN;
3028         case NL80211_IFTYPE_AP:
3029                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3030                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3031                           TU_TO_USEC(next_beacon -
3032                                      ah->ah_config.
3033                                      dma_beacon_response_time));
3034                 REG_WRITE(ah, AR_NEXT_SWBA,
3035                           TU_TO_USEC(next_beacon -
3036                                      ah->ah_config.
3037                                      sw_beacon_response_time));
3038                 flags |=
3039                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3040                 break;
3041         default:
3042                 DPRINTF(ah->ah_sc, ATH_DBG_BEACON,
3043                         "%s: unsupported opmode: %d\n",
3044                         __func__, ah->ah_opmode);
3045                 return;
3046                 break;
3047         }
3048
3049         REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3050         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3051         REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3052         REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3053
3054         beacon_period &= ~ATH9K_BEACON_ENA;
3055         if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3056                 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3057                 ath9k_hw_reset_tsf(ah);
3058         }
3059
3060         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3061 }
3062
3063 void ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
3064                                     const struct ath9k_beacon_state *bs)
3065 {
3066         u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3067         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3068
3069         REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3070
3071         REG_WRITE(ah, AR_BEACON_PERIOD,
3072                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3073         REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3074                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3075
3076         REG_RMW_FIELD(ah, AR_RSSI_THR,
3077                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3078
3079         beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3080
3081         if (bs->bs_sleepduration > beaconintval)
3082                 beaconintval = bs->bs_sleepduration;
3083
3084         dtimperiod = bs->bs_dtimperiod;
3085         if (bs->bs_sleepduration > dtimperiod)
3086                 dtimperiod = bs->bs_sleepduration;
3087
3088         if (beaconintval == dtimperiod)
3089                 nextTbtt = bs->bs_nextdtim;
3090         else
3091                 nextTbtt = bs->bs_nexttbtt;
3092
3093         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3094         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3095         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3096         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3097
3098         REG_WRITE(ah, AR_NEXT_DTIM,
3099                   TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3100         REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3101
3102         REG_WRITE(ah, AR_SLEEP1,
3103                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3104                   | AR_SLEEP1_ASSUME_DTIM);
3105
3106         if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3107                 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3108         else
3109                 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3110
3111         REG_WRITE(ah, AR_SLEEP2,
3112                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3113
3114         REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3115         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3116
3117         REG_SET_BIT(ah, AR_TIMER_MODE,
3118                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3119                     AR_DTIM_TIMER_EN);
3120
3121 }
3122
3123 /*******************/
3124 /* HW Capabilities */
3125 /*******************/
3126
3127 bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
3128 {
3129         struct ath_hal_5416 *ahp = AH5416(ah);
3130         struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3131         u16 capField = 0, eeval;
3132
3133         eeval = ath9k_hw_get_eeprom(ah, EEP_REG_0);
3134
3135         ah->regulatory.current_rd = eeval;
3136
3137         eeval = ath9k_hw_get_eeprom(ah, EEP_REG_1);
3138         ah->regulatory.current_rd_ext = eeval;
3139
3140         capField = ath9k_hw_get_eeprom(ah, EEP_OP_CAP);
3141
3142         if (ah->ah_opmode != NL80211_IFTYPE_AP &&
3143             ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3144                 if (ah->regulatory.current_rd == 0x64 ||
3145                     ah->regulatory.current_rd == 0x65)
3146                         ah->regulatory.current_rd += 5;
3147                 else if (ah->regulatory.current_rd == 0x41)
3148                         ah->regulatory.current_rd = 0x43;
3149                 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
3150                         "regdomain mapped to 0x%x\n", ah->regulatory.current_rd);
3151         }
3152
3153         eeval = ath9k_hw_get_eeprom(ah, EEP_OP_MODE);
3154         bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3155
3156         if (eeval & AR5416_OPFLAGS_11A) {
3157                 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3158                 if (ah->ah_config.ht_enable) {
3159                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3160                                 set_bit(ATH9K_MODE_11NA_HT20,
3161                                         pCap->wireless_modes);
3162                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3163                                 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3164                                         pCap->wireless_modes);
3165                                 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3166                                         pCap->wireless_modes);
3167                         }
3168                 }
3169         }
3170
3171         if (eeval & AR5416_OPFLAGS_11G) {
3172                 set_bit(ATH9K_MODE_11B, pCap->wireless_modes);
3173                 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3174                 if (ah->ah_config.ht_enable) {
3175                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3176                                 set_bit(ATH9K_MODE_11NG_HT20,
3177                                         pCap->wireless_modes);
3178                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3179                                 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3180                                         pCap->wireless_modes);
3181                                 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3182                                         pCap->wireless_modes);
3183                         }
3184                 }
3185         }
3186
3187         pCap->tx_chainmask = ath9k_hw_get_eeprom(ah, EEP_TX_MASK);
3188         if ((ah->ah_isPciExpress)
3189             || (eeval & AR5416_OPFLAGS_11A)) {
3190                 pCap->rx_chainmask =
3191                         ath9k_hw_get_eeprom(ah, EEP_RX_MASK);
3192         } else {
3193                 pCap->rx_chainmask =
3194                         (ath9k_hw_gpio_get(ah, 0)) ? 0x5 : 0x7;
3195         }
3196
3197         if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3198                 ahp->ah_miscMode |= AR_PCU_MIC_NEW_LOC_ENA;
3199
3200         pCap->low_2ghz_chan = 2312;
3201         pCap->high_2ghz_chan = 2732;
3202
3203         pCap->low_5ghz_chan = 4920;
3204         pCap->high_5ghz_chan = 6100;
3205
3206         pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3207         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3208         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3209
3210         pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3211         pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3212         pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3213
3214         pCap->hw_caps |= ATH9K_HW_CAP_CHAN_SPREAD;
3215
3216         if (ah->ah_config.ht_enable)
3217                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3218         else
3219                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3220
3221         pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3222         pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3223         pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3224         pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3225
3226         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3227                 pCap->total_queues =
3228                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3229         else
3230                 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3231
3232         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3233                 pCap->keycache_size =
3234                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3235         else
3236                 pCap->keycache_size = AR_KEYTABLE_SIZE;
3237
3238         pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3239         pCap->num_mr_retries = 4;
3240         pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3241
3242         if (AR_SREV_9285_10_OR_LATER(ah))
3243                 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3244         else if (AR_SREV_9280_10_OR_LATER(ah))
3245                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3246         else
3247                 pCap->num_gpio_pins = AR_NUM_GPIO;
3248
3249         if (AR_SREV_9280_10_OR_LATER(ah)) {
3250                 pCap->hw_caps |= ATH9K_HW_CAP_WOW;
3251                 pCap->hw_caps |= ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3252         } else {
3253                 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW;
3254                 pCap->hw_caps &= ~ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT;
3255         }
3256
3257         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3258                 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3259                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3260         } else {
3261                 pCap->rts_aggr_limit = (8 * 1024);
3262         }
3263
3264         pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3265
3266 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3267         ah->ah_rfsilent = ath9k_hw_get_eeprom(ah, EEP_RF_SILENT);
3268         if (ah->ah_rfsilent & EEP_RFSILENT_ENABLED) {
3269                 ah->ah_rfkill_gpio =
3270                         MS(ah->ah_rfsilent, EEP_RFSILENT_GPIO_SEL);
3271                 ah->ah_rfkill_polarity =
3272                         MS(ah->ah_rfsilent, EEP_RFSILENT_POLARITY);
3273
3274                 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3275         }
3276 #endif
3277
3278         if ((ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) ||
3279             (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) ||
3280             (ah->hw_version.macVersion == AR_SREV_VERSION_9160) ||
3281             (ah->hw_version.macVersion == AR_SREV_VERSION_9100) ||
3282             (ah->hw_version.macVersion == AR_SREV_VERSION_9280))
3283                 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3284         else
3285                 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3286
3287         if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3288                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3289         else
3290                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3291
3292         if (ah->regulatory.current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3293                 pCap->reg_cap =
3294                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3295                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3296                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
3297                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3298         } else {
3299                 pCap->reg_cap =
3300                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3301                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3302         }
3303
3304         pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3305
3306         pCap->num_antcfg_5ghz =
3307                 ath9k_hw_get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3308         pCap->num_antcfg_2ghz =
3309                 ath9k_hw_get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3310
3311         if (AR_SREV_9280_10_OR_LATER(ah) && btcoex_enable) {
3312                 pCap->hw_caps |= ATH9K_HW_CAP_BT_COEX;
3313                 ah->ah_btactive_gpio = 6;
3314                 ah->ah_wlanactive_gpio = 5;
3315         }
3316
3317         return true;
3318 }
3319
3320 bool ath9k_hw_getcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3321                             u32 capability, u32 *result)
3322 {
3323         struct ath_hal_5416 *ahp = AH5416(ah);
3324         const struct ath9k_hw_capabilities *pCap = &ah->ah_caps;
3325
3326         switch (type) {
3327         case ATH9K_CAP_CIPHER:
3328                 switch (capability) {
3329                 case ATH9K_CIPHER_AES_CCM:
3330                 case ATH9K_CIPHER_AES_OCB:
3331                 case ATH9K_CIPHER_TKIP:
3332                 case ATH9K_CIPHER_WEP:
3333                 case ATH9K_CIPHER_MIC:
3334                 case ATH9K_CIPHER_CLR:
3335                         return true;
3336                 default:
3337                         return false;
3338                 }
3339         case ATH9K_CAP_TKIP_MIC:
3340                 switch (capability) {
3341                 case 0:
3342                         return true;
3343                 case 1:
3344                         return (ahp->ah_staId1Defaults &
3345                                 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3346                         false;
3347                 }
3348         case ATH9K_CAP_TKIP_SPLIT:
3349                 return (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) ?
3350                         false : true;
3351         case ATH9K_CAP_WME_TKIPMIC:
3352                 return 0;
3353         case ATH9K_CAP_PHYCOUNTERS:
3354                 return ahp->ah_hasHwPhyCounters ? 0 : -ENXIO;
3355         case ATH9K_CAP_DIVERSITY:
3356                 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3357                         AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3358                         true : false;
3359         case ATH9K_CAP_PHYDIAG:
3360                 return true;
3361         case ATH9K_CAP_MCAST_KEYSRCH:
3362                 switch (capability) {
3363                 case 0:
3364                         return true;
3365                 case 1:
3366                         if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3367                                 return false;
3368                         } else {
3369                                 return (ahp->ah_staId1Defaults &
3370                                         AR_STA_ID1_MCAST_KSRCH) ? true :
3371                                         false;
3372                         }
3373                 }
3374                 return false;
3375         case ATH9K_CAP_TSF_ADJUST:
3376                 return (ahp->ah_miscMode & AR_PCU_TX_ADD_TSF) ?
3377                         true : false;
3378         case ATH9K_CAP_RFSILENT:
3379                 if (capability == 3)
3380                         return false;
3381         case ATH9K_CAP_ANT_CFG_2GHZ:
3382                 *result = pCap->num_antcfg_2ghz;
3383                 return true;
3384         case ATH9K_CAP_ANT_CFG_5GHZ:
3385                 *result = pCap->num_antcfg_5ghz;
3386                 return true;
3387         case ATH9K_CAP_TXPOW:
3388                 switch (capability) {
3389                 case 0:
3390                         return 0;
3391                 case 1:
3392                         *result = ah->regulatory.power_limit;
3393                         return 0;
3394                 case 2:
3395                         *result = ah->regulatory.max_power_level;
3396                         return 0;
3397                 case 3:
3398                         *result = ah->regulatory.tp_scale;
3399                         return 0;
3400                 }
3401                 return false;
3402         default:
3403                 return false;
3404         }
3405 }
3406
3407 bool ath9k_hw_setcapability(struct ath_hal *ah, enum ath9k_capability_type type,
3408                             u32 capability, u32 setting, int *status)
3409 {
3410         struct ath_hal_5416 *ahp = AH5416(ah);
3411         u32 v;
3412
3413         switch (type) {
3414         case ATH9K_CAP_TKIP_MIC:
3415                 if (setting)
3416                         ahp->ah_staId1Defaults |=
3417                                 AR_STA_ID1_CRPT_MIC_ENABLE;
3418                 else
3419                         ahp->ah_staId1Defaults &=
3420                                 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3421                 return true;
3422         case ATH9K_CAP_DIVERSITY:
3423                 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3424                 if (setting)
3425                         v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3426                 else
3427                         v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3428                 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3429                 return true;
3430         case ATH9K_CAP_MCAST_KEYSRCH:
3431                 if (setting)
3432                         ahp->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH;
3433                 else
3434                         ahp->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3435                 return true;
3436         case ATH9K_CAP_TSF_ADJUST:
3437                 if (setting)
3438                         ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
3439                 else
3440                         ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
3441                 return true;
3442         default:
3443                 return false;
3444         }
3445 }
3446
3447 /****************************/
3448 /* GPIO / RFKILL / Antennae */
3449 /****************************/
3450
3451 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah,
3452                                          u32 gpio, u32 type)
3453 {
3454         int addr;
3455         u32 gpio_shift, tmp;
3456
3457         if (gpio > 11)
3458                 addr = AR_GPIO_OUTPUT_MUX3;
3459         else if (gpio > 5)
3460                 addr = AR_GPIO_OUTPUT_MUX2;
3461         else
3462                 addr = AR_GPIO_OUTPUT_MUX1;
3463
3464         gpio_shift = (gpio % 6) * 5;
3465
3466         if (AR_SREV_9280_20_OR_LATER(ah)
3467             || (addr != AR_GPIO_OUTPUT_MUX1)) {
3468                 REG_RMW(ah, addr, (type << gpio_shift),
3469                         (0x1f << gpio_shift));
3470         } else {
3471                 tmp = REG_READ(ah, addr);
3472                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3473                 tmp &= ~(0x1f << gpio_shift);
3474                 tmp |= (type << gpio_shift);
3475                 REG_WRITE(ah, addr, tmp);
3476         }
3477 }
3478
3479 void ath9k_hw_cfg_gpio_input(struct ath_hal *ah, u32 gpio)
3480 {
3481         u32 gpio_shift;
3482
3483         ASSERT(gpio < ah->ah_caps.num_gpio_pins);
3484
3485         gpio_shift = gpio << 1;
3486
3487         REG_RMW(ah,
3488                 AR_GPIO_OE_OUT,
3489                 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3490                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3491 }
3492
3493 u32 ath9k_hw_gpio_get(struct ath_hal *ah, u32 gpio)
3494 {
3495 #define MS_REG_READ(x, y) \
3496         (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3497
3498         if (gpio >= ah->ah_caps.num_gpio_pins)
3499                 return 0xffffffff;
3500
3501         if (AR_SREV_9285_10_OR_LATER(ah))
3502                 return MS_REG_READ(AR9285, gpio) != 0;
3503         else if (AR_SREV_9280_10_OR_LATER(ah))
3504                 return MS_REG_READ(AR928X, gpio) != 0;
3505         else
3506                 return MS_REG_READ(AR, gpio) != 0;
3507 }
3508
3509 void ath9k_hw_cfg_output(struct ath_hal *ah, u32 gpio,
3510                          u32 ah_signal_type)
3511 {
3512         u32 gpio_shift;
3513
3514         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3515
3516         gpio_shift = 2 * gpio;
3517
3518         REG_RMW(ah,
3519                 AR_GPIO_OE_OUT,
3520                 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3521                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3522 }
3523
3524 void ath9k_hw_set_gpio(struct ath_hal *ah, u32 gpio, u32 val)
3525 {
3526         REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3527                 AR_GPIO_BIT(gpio));
3528 }
3529
3530 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3531 void ath9k_enable_rfkill(struct ath_hal *ah)
3532 {
3533         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3534                     AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
3535
3536         REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
3537                     AR_GPIO_INPUT_MUX2_RFSILENT);
3538
3539         ath9k_hw_cfg_gpio_input(ah, ah->ah_rfkill_gpio);
3540         REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
3541 }
3542 #endif
3543
3544 u32 ath9k_hw_getdefantenna(struct ath_hal *ah)
3545 {
3546         return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3547 }
3548
3549 void ath9k_hw_setantenna(struct ath_hal *ah, u32 antenna)
3550 {
3551         REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3552 }
3553
3554 bool ath9k_hw_setantennaswitch(struct ath_hal *ah,
3555                                enum ath9k_ant_setting settings,
3556                                struct ath9k_channel *chan,
3557                                u8 *tx_chainmask,
3558                                u8 *rx_chainmask,
3559                                u8 *antenna_cfgd)
3560 {
3561         struct ath_hal_5416 *ahp = AH5416(ah);
3562         static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3563
3564         if (AR_SREV_9280(ah)) {
3565                 if (!tx_chainmask_cfg) {
3566
3567                         tx_chainmask_cfg = *tx_chainmask;
3568                         rx_chainmask_cfg = *rx_chainmask;
3569                 }
3570
3571                 switch (settings) {
3572                 case ATH9K_ANT_FIXED_A:
3573                         *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3574                         *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3575                         *antenna_cfgd = true;
3576                         break;
3577                 case ATH9K_ANT_FIXED_B:
3578                         if (ah->ah_caps.tx_chainmask >
3579                             ATH9K_ANTENNA1_CHAINMASK) {
3580                                 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3581                         }
3582                         *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3583                         *antenna_cfgd = true;
3584                         break;
3585                 case ATH9K_ANT_VARIABLE:
3586                         *tx_chainmask = tx_chainmask_cfg;
3587                         *rx_chainmask = rx_chainmask_cfg;
3588                         *antenna_cfgd = true;
3589                         break;
3590                 default:
3591                         break;
3592                 }
3593         } else {
3594                 ahp->ah_diversityControl = settings;
3595         }
3596
3597         return true;
3598 }
3599
3600 /*********************/
3601 /* General Operation */
3602 /*********************/
3603
3604 u32 ath9k_hw_getrxfilter(struct ath_hal *ah)
3605 {
3606         u32 bits = REG_READ(ah, AR_RX_FILTER);
3607         u32 phybits = REG_READ(ah, AR_PHY_ERR);
3608
3609         if (phybits & AR_PHY_ERR_RADAR)
3610                 bits |= ATH9K_RX_FILTER_PHYRADAR;
3611         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3612                 bits |= ATH9K_RX_FILTER_PHYERR;
3613
3614         return bits;
3615 }
3616
3617 void ath9k_hw_setrxfilter(struct ath_hal *ah, u32 bits)
3618 {
3619         u32 phybits;
3620
3621         REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
3622         phybits = 0;
3623         if (bits & ATH9K_RX_FILTER_PHYRADAR)
3624                 phybits |= AR_PHY_ERR_RADAR;
3625         if (bits & ATH9K_RX_FILTER_PHYERR)
3626                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3627         REG_WRITE(ah, AR_PHY_ERR, phybits);
3628
3629         if (phybits)
3630                 REG_WRITE(ah, AR_RXCFG,
3631                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3632         else
3633                 REG_WRITE(ah, AR_RXCFG,
3634                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3635 }
3636
3637 bool ath9k_hw_phy_disable(struct ath_hal *ah)
3638 {
3639         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3640 }
3641
3642 bool ath9k_hw_disable(struct ath_hal *ah)
3643 {
3644         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3645                 return false;
3646
3647         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3648 }
3649
3650 bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit)
3651 {
3652         struct ath9k_channel *chan = ah->ah_curchan;
3653         struct ieee80211_channel *channel = chan->chan;
3654
3655         ah->regulatory.power_limit = min(limit, (u32) MAX_RATE_POWER);
3656
3657         if (ath9k_hw_set_txpower(ah, chan,
3658                                  ath9k_regd_get_ctl(ah, chan),
3659                                  channel->max_antenna_gain * 2,
3660                                  channel->max_power * 2,
3661                                  min((u32) MAX_RATE_POWER,
3662                                      (u32) ah->regulatory.power_limit)) != 0)
3663                 return false;
3664
3665         return true;
3666 }
3667
3668 void ath9k_hw_setmac(struct ath_hal *ah, const u8 *mac)
3669 {
3670         memcpy(ah->macaddr, mac, ETH_ALEN);
3671 }
3672
3673 void ath9k_hw_setopmode(struct ath_hal *ah)
3674 {
3675         ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
3676 }
3677
3678 void ath9k_hw_setmcastfilter(struct ath_hal *ah, u32 filter0, u32 filter1)
3679 {
3680         REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3681         REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3682 }
3683
3684 void ath9k_hw_setbssidmask(struct ath_softc *sc)
3685 {
3686         REG_WRITE(sc->sc_ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
3687         REG_WRITE(sc->sc_ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
3688 }
3689
3690 void ath9k_hw_write_associd(struct ath_softc *sc)
3691 {
3692         REG_WRITE(sc->sc_ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
3693         REG_WRITE(sc->sc_ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
3694                   ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3695 }
3696
3697 u64 ath9k_hw_gettsf64(struct ath_hal *ah)
3698 {
3699         u64 tsf;
3700
3701         tsf = REG_READ(ah, AR_TSF_U32);
3702         tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3703
3704         return tsf;
3705 }
3706
3707 void ath9k_hw_settsf64(struct ath_hal *ah, u64 tsf64)
3708 {
3709         REG_WRITE(ah, AR_TSF_L32, 0x00000000);
3710         REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3711         REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3712 }
3713
3714 void ath9k_hw_reset_tsf(struct ath_hal *ah)
3715 {
3716         int count;
3717
3718         count = 0;
3719         while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
3720                 count++;
3721                 if (count > 10) {
3722                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3723                                 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3724                         break;
3725                 }
3726                 udelay(10);
3727         }
3728         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3729 }
3730
3731 bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u32 setting)
3732 {
3733         struct ath_hal_5416 *ahp = AH5416(ah);
3734
3735         if (setting)
3736                 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
3737         else
3738                 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
3739
3740         return true;
3741 }
3742
3743 bool ath9k_hw_setslottime(struct ath_hal *ah, u32 us)
3744 {
3745         struct ath_hal_5416 *ahp = AH5416(ah);
3746
3747         if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
3748                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
3749                 ahp->ah_slottime = (u32) -1;
3750                 return false;
3751         } else {
3752                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
3753                 ahp->ah_slottime = us;
3754                 return true;
3755         }
3756 }
3757
3758 void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum ath9k_ht_macmode mode)
3759 {
3760         u32 macmode;
3761
3762         if (mode == ATH9K_HT_MACMODE_2040 &&
3763             !ah->ah_config.cwm_ignore_extcca)
3764                 macmode = AR_2040_JOINED_RX_CLEAR;
3765         else
3766                 macmode = 0;
3767
3768         REG_WRITE(ah, AR_2040_MODE, macmode);
3769 }
3770
3771 /***************************/
3772 /*  Bluetooth Coexistence  */
3773 /***************************/
3774
3775 void ath9k_hw_btcoex_enable(struct ath_hal *ah)
3776 {
3777         /* connect bt_active to baseband */
3778         REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3779                         (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
3780                          AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
3781
3782         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3783                         AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
3784
3785         /* Set input mux for bt_active to gpio pin */
3786         REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
3787                         AR_GPIO_INPUT_MUX1_BT_ACTIVE,
3788                         ah->ah_btactive_gpio);
3789
3790         /* Configure the desired gpio port for input */
3791         ath9k_hw_cfg_gpio_input(ah, ah->ah_btactive_gpio);
3792
3793         /* Configure the desired GPIO port for TX_FRAME output */
3794         ath9k_hw_cfg_output(ah, ah->ah_wlanactive_gpio,
3795                             AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
3796 }