SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/ath9k/eeprom.c

   1 /*
   2  * Copyright (c) 2008 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include "ath9k.h"
  18
  19 static void ath9k_hw_analog_shift_rmw(struct ath_hw *ah,
  20                                       u32 reg, u32 mask,
  21                                       u32 shift, u32 val)
  22 {
  23         u32 regVal;
  24
  25         regVal = REG_READ(ah, reg) & ~mask;
  26         regVal |= (val << shift) & mask;
  27
  28         REG_WRITE(ah, reg, regVal);
  29
  30         if (ah->config.analog_shiftreg)
  31                 udelay(100);
  32
  33         return;
  34 }
  35
  36 static inline u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz)
  37 {
  38
  39         if (fbin == AR5416_BCHAN_UNUSED)
  40                 return fbin;
  41
  42         return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
  43 }
  44
  45 static inline int16_t ath9k_hw_interpolate(u16 target,
  46                                            u16 srcLeft, u16 srcRight,
  47                                            int16_t targetLeft,
  48                                            int16_t targetRight)
  49 {
  50         int16_t rv;
  51
  52         if (srcRight == srcLeft) {
  53                 rv = targetLeft;
  54         } else {
  55                 rv = (int16_t) (((target - srcLeft) * targetRight +
  56                                  (srcRight - target) * targetLeft) /
  57                                 (srcRight - srcLeft));
  58         }
  59         return rv;
  60 }
  61
  62 static inline bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList,
  63                                                   u16 listSize, u16 *indexL,
  64                                                   u16 *indexR)
  65 {
  66         u16 i;
  67
  68         if (target <= pList[0]) {
  69                 *indexL = *indexR = 0;
  70                 return true;
  71         }
  72         if (target >= pList[listSize - 1]) {
  73                 *indexL = *indexR = (u16) (listSize - 1);
  74                 return true;
  75         }
  76
  77         for (i = 0; i < listSize - 1; i++) {
  78                 if (pList[i] == target) {
  79                         *indexL = *indexR = i;
  80                         return true;
  81                 }
  82                 if (target < pList[i + 1]) {
  83                         *indexL = i;
  84                         *indexR = (u16) (i + 1);
  85                         return false;
  86                 }
  87         }
  88         return false;
  89 }
  90
  91 static inline bool ath9k_hw_nvram_read(struct ath_hw *ah, u32 off, u16 *data)
  92 {
  93         struct ath_softc *sc = ah->ah_sc;
  94
  95         return sc->bus_ops->eeprom_read(ah, off, data);
  96 }
  97
  98 static inline bool ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList,
  99                                            u8 *pVpdList, u16 numIntercepts,
 100                                            u8 *pRetVpdList)
 101 {
 102         u16 i, k;
 103         u8 currPwr = pwrMin;
 104         u16 idxL = 0, idxR = 0;
 105
 106         for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) {
 107                 ath9k_hw_get_lower_upper_index(currPwr, pPwrList,
 108                                                numIntercepts, &(idxL),
 109                                                &(idxR));
 110                 if (idxR < 1)
 111                         idxR = 1;
 112                 if (idxL == numIntercepts - 1)
 113                         idxL = (u16) (numIntercepts - 2);
 114                 if (pPwrList[idxL] == pPwrList[idxR])
 115                         k = pVpdList[idxL];
 116                 else
 117                         k = (u16)(((currPwr - pPwrList[idxL]) * pVpdList[idxR] +
 118                                    (pPwrList[idxR] - currPwr) * pVpdList[idxL]) /
 119                                   (pPwrList[idxR] - pPwrList[idxL]));
 120                 pRetVpdList[i] = (u8) k;
 121                 currPwr += 2;
 122         }
 123
 124         return true;
 125 }
 126
 127 static void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah,
 128                                       struct ath9k_channel *chan,
 129                                       struct cal_target_power_leg *powInfo,
 130                                       u16 numChannels,
 131                                       struct cal_target_power_leg *pNewPower,
 132                                       u16 numRates, bool isExtTarget)
 133 {
 134         struct chan_centers centers;
 135         u16 clo, chi;
 136         int i;
 137         int matchIndex = -1, lowIndex = -1;
 138         u16 freq;
 139
 140         ath9k_hw_get_channel_centers(ah, chan, &centers);
 141         freq = (isExtTarget) ? centers.ext_center : centers.ctl_center;
 142
 143         if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel,
 144                                        IS_CHAN_2GHZ(chan))) {
 145                 matchIndex = 0;
 146         } else {
 147                 for (i = 0; (i < numChannels) &&
 148                              (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
 149                         if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel,
 150                                                        IS_CHAN_2GHZ(chan))) {
 151                                 matchIndex = i;
 152                                 break;
 153                         } else if ((freq < ath9k_hw_fbin2freq(powInfo[i].bChannel,
 154                                                       IS_CHAN_2GHZ(chan))) &&
 155                                    (freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel,
 156                                                       IS_CHAN_2GHZ(chan)))) {
 157                                 lowIndex = i - 1;
 158                                 break;
 159                         }
 160                 }
 161                 if ((matchIndex == -1) && (lowIndex == -1))
 162                         matchIndex = i - 1;
 163         }
 164
 165         if (matchIndex != -1) {
 166                 *pNewPower = powInfo[matchIndex];
 167         } else {
 168                 clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
 169                                          IS_CHAN_2GHZ(chan));
 170                 chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
 171                                          IS_CHAN_2GHZ(chan));
 172
 173                 for (i = 0; i < numRates; i++) {
 174                         pNewPower->tPow2x[i] =
 175                                 (u8)ath9k_hw_interpolate(freq, clo, chi,
 176                                                 powInfo[lowIndex].tPow2x[i],
 177                                                 powInfo[lowIndex + 1].tPow2x[i]);
 178                 }
 179         }
 180 }
 181
 182 static void ath9k_get_txgain_index(struct ath_hw *ah,
 183                 struct ath9k_channel *chan,
 184                 struct calDataPerFreqOpLoop *rawDatasetOpLoop,
 185                 u8 *calChans,  u16 availPiers, u8 *pwr, u8 *pcdacIdx)
 186 {
 187         u8 pcdac, i = 0;
 188         u16 idxL = 0, idxR = 0, numPiers;
 189         bool match;
 190         struct chan_centers centers;
 191
 192         ath9k_hw_get_channel_centers(ah, chan, &centers);
 193
 194         for (numPiers = 0; numPiers < availPiers; numPiers++)
 195                 if (calChans[numPiers] == AR5416_BCHAN_UNUSED)
 196                         break;
 197
 198         match = ath9k_hw_get_lower_upper_index(
 199                         (u8)FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan)),
 200                         calChans, numPiers, &idxL, &idxR);
 201         if (match) {
 202                 pcdac = rawDatasetOpLoop[idxL].pcdac[0][0];
 203                 *pwr = rawDatasetOpLoop[idxL].pwrPdg[0][0];
 204         } else {
 205                 pcdac = rawDatasetOpLoop[idxR].pcdac[0][0];
 206                 *pwr = (rawDatasetOpLoop[idxL].pwrPdg[0][0] +
 207                                 rawDatasetOpLoop[idxR].pwrPdg[0][0])/2;
 208         }
 209
 210         while (pcdac > ah->originalGain[i] &&
 211                         i < (AR9280_TX_GAIN_TABLE_SIZE - 1))
 212                 i++;
 213
 214         *pcdacIdx = i;
 215         return;
 216 }
 217
 218 static void ath9k_olc_get_pdadcs(struct ath_hw *ah,
 219                                 u32 initTxGain,
 220                                 int txPower,
 221                                 u8 *pPDADCValues)
 222 {
 223         u32 i;
 224         u32 offset;
 225
 226         REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_0,
 227                         AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
 228         REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL6_1,
 229                         AR_PHY_TX_PWRCTRL_ERR_EST_MODE, 3);
 230
 231         REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL7,
 232                         AR_PHY_TX_PWRCTRL_INIT_TX_GAIN, initTxGain);
 233
 234         offset = txPower;
 235         for (i = 0; i < AR5416_NUM_PDADC_VALUES; i++)
 236                 if (i < offset)
 237                         pPDADCValues[i] = 0x0;
 238                 else
 239                         pPDADCValues[i] = 0xFF;
 240 }
 241
 242
 243
 244
 245 static void ath9k_hw_get_target_powers(struct ath_hw *ah,
 246                                        struct ath9k_channel *chan,
 247                                        struct cal_target_power_ht *powInfo,
 248                                        u16 numChannels,
 249                                        struct cal_target_power_ht *pNewPower,
 250                                        u16 numRates, bool isHt40Target)
 251 {
 252         struct chan_centers centers;
 253         u16 clo, chi;
 254         int i;
 255         int matchIndex = -1, lowIndex = -1;
 256         u16 freq;
 257
 258         ath9k_hw_get_channel_centers(ah, chan, &centers);
 259         freq = isHt40Target ? centers.synth_center : centers.ctl_center;
 260
 261         if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel, IS_CHAN_2GHZ(chan))) {
 262                 matchIndex = 0;
 263         } else {
 264                 for (i = 0; (i < numChannels) &&
 265                              (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
 266                         if (freq == ath9k_hw_fbin2freq(powInfo[i].bChannel,
 267                                                        IS_CHAN_2GHZ(chan))) {
 268                                 matchIndex = i;
 269                                 break;
 270                         } else
 271                                 if ((freq < ath9k_hw_fbin2freq(powInfo[i].bChannel,
 272                                                        IS_CHAN_2GHZ(chan))) &&
 273                                     (freq > ath9k_hw_fbin2freq(powInfo[i - 1].bChannel,
 274                                                        IS_CHAN_2GHZ(chan)))) {
 275                                         lowIndex = i - 1;
 276                                         break;
 277                                 }
 278                 }
 279                 if ((matchIndex == -1) && (lowIndex == -1))
 280                         matchIndex = i - 1;
 281         }
 282
 283         if (matchIndex != -1) {
 284                 *pNewPower = powInfo[matchIndex];
 285         } else {
 286                 clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
 287                                          IS_CHAN_2GHZ(chan));
 288                 chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
 289                                          IS_CHAN_2GHZ(chan));
 290
 291                 for (i = 0; i < numRates; i++) {
 292                         pNewPower->tPow2x[i] = (u8)ath9k_hw_interpolate(freq,
 293                                                 clo, chi,
 294                                                 powInfo[lowIndex].tPow2x[i],
 295                                                 powInfo[lowIndex + 1].tPow2x[i]);
 296                 }
 297         }
 298 }
 299
 300 static u16 ath9k_hw_get_max_edge_power(u16 freq,
 301                                        struct cal_ctl_edges *pRdEdgesPower,
 302                                        bool is2GHz, int num_band_edges)
 303 {
 304         u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
 305         int i;
 306
 307         for (i = 0; (i < num_band_edges) &&
 308                      (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
 309                 if (freq == ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel, is2GHz)) {
 310                         twiceMaxEdgePower = pRdEdgesPower[i].tPower;
 311                         break;
 312                 } else if ((i > 0) &&
 313                            (freq < ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel,
 314                                                       is2GHz))) {
 315                         if (ath9k_hw_fbin2freq(pRdEdgesPower[i - 1].bChannel,
 316                                                is2GHz) < freq &&
 317                             pRdEdgesPower[i - 1].flag) {
 318                                 twiceMaxEdgePower =
 319                                         pRdEdgesPower[i - 1].tPower;
 320                         }
 321                         break;
 322                 }
 323         }
 324
 325         return twiceMaxEdgePower;
 326 }
 327
 328 /****************************************/
 329 /* EEPROM Operations for 4K sized cards */
 330 /****************************************/
 331
 332 static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah)
 333 {
 334         return ((ah->eeprom.map4k.baseEepHeader.version >> 12) & 0xF);
 335 }
 336
 337 static int ath9k_hw_4k_get_eeprom_rev(struct ath_hw *ah)
 338 {
 339         return ((ah->eeprom.map4k.baseEepHeader.version) & 0xFFF);
 340 }
 341
 342 static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
 343 {
 344 #define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
 345         struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
 346         u16 *eep_data;
 347         int addr, eep_start_loc = 0;
 348
 349         eep_start_loc = 64;
 350
 351         if (!ath9k_hw_use_flash(ah)) {
 352                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 353                         "Reading from EEPROM, not flash\n");
 354         }
 355
 356         eep_data = (u16 *)eep;
 357
 358         for (addr = 0; addr < SIZE_EEPROM_4K; addr++) {
 359                 if (!ath9k_hw_nvram_read(ah, addr + eep_start_loc, eep_data)) {
 360                         DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 361                                "Unable to read eeprom region \n");
 362                         return false;
 363                 }
 364                 eep_data++;
 365         }
 366         return true;
 367 #undef SIZE_EEPROM_4K
 368 }
 369
 370 static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
 371 {
 372 #define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
 373         struct ar5416_eeprom_4k *eep =
 374                 (struct ar5416_eeprom_4k *) &ah->eeprom.map4k;
 375         u16 *eepdata, temp, magic, magic2;
 376         u32 sum = 0, el;
 377         bool need_swap = false;
 378         int i, addr;
 379
 380
 381         if (!ath9k_hw_use_flash(ah)) {
 382
 383                 if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
 384                                          &magic)) {
 385                         DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 386                                 "Reading Magic # failed\n");
 387                         return false;
 388                 }
 389
 390                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 391                                 "Read Magic = 0x%04X\n", magic);
 392
 393                 if (magic != AR5416_EEPROM_MAGIC) {
 394                         magic2 = swab16(magic);
 395
 396                         if (magic2 == AR5416_EEPROM_MAGIC) {
 397                                 need_swap = true;
 398                                 eepdata = (u16 *) (&ah->eeprom);
 399
 400                                 for (addr = 0; addr < EEPROM_4K_SIZE; addr++) {
 401                                         temp = swab16(*eepdata);
 402                                         *eepdata = temp;
 403                                         eepdata++;
 404
 405                                         DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 406                                                 "0x%04X  ", *eepdata);
 407
 408                                         if (((addr + 1) % 6) == 0)
 409                                                 DPRINTF(ah->ah_sc,
 410                                                         ATH_DBG_EEPROM, "\n");
 411                                 }
 412                         } else {
 413                                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 414                                         "Invalid EEPROM Magic. "
 415                                         "endianness mismatch.\n");
 416                                 return -EINVAL;
 417                         }
 418                 }
 419         }
 420
 421         DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n",
 422                 need_swap ? "True" : "False");
 423
 424         if (need_swap)
 425                 el = swab16(ah->eeprom.map4k.baseEepHeader.length);
 426         else
 427                 el = ah->eeprom.map4k.baseEepHeader.length;
 428
 429         if (el > sizeof(struct ar5416_eeprom_def))
 430                 el = sizeof(struct ar5416_eeprom_4k) / sizeof(u16);
 431         else
 432                 el = el / sizeof(u16);
 433
 434         eepdata = (u16 *)(&ah->eeprom);
 435
 436         for (i = 0; i < el; i++)
 437                 sum ^= *eepdata++;
 438
 439         if (need_swap) {
 440                 u32 integer;
 441                 u16 word;
 442
 443                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 444                         "EEPROM Endianness is not native.. Changing \n");
 445
 446                 word = swab16(eep->baseEepHeader.length);
 447                 eep->baseEepHeader.length = word;
 448
 449                 word = swab16(eep->baseEepHeader.checksum);
 450                 eep->baseEepHeader.checksum = word;
 451
 452                 word = swab16(eep->baseEepHeader.version);
 453                 eep->baseEepHeader.version = word;
 454
 455                 word = swab16(eep->baseEepHeader.regDmn[0]);
 456                 eep->baseEepHeader.regDmn[0] = word;
 457
 458                 word = swab16(eep->baseEepHeader.regDmn[1]);
 459                 eep->baseEepHeader.regDmn[1] = word;
 460
 461                 word = swab16(eep->baseEepHeader.rfSilent);
 462                 eep->baseEepHeader.rfSilent = word;
 463
 464                 word = swab16(eep->baseEepHeader.blueToothOptions);
 465                 eep->baseEepHeader.blueToothOptions = word;
 466
 467                 word = swab16(eep->baseEepHeader.deviceCap);
 468                 eep->baseEepHeader.deviceCap = word;
 469
 470                 integer = swab32(eep->modalHeader.antCtrlCommon);
 471                 eep->modalHeader.antCtrlCommon = integer;
 472
 473                 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
 474                         integer = swab32(eep->modalHeader.antCtrlChain[i]);
 475                         eep->modalHeader.antCtrlChain[i] = integer;
 476                 }
 477
 478                 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
 479                         word = swab16(eep->modalHeader.spurChans[i].spurChan);
 480                         eep->modalHeader.spurChans[i].spurChan = word;
 481                 }
 482         }
 483
 484         if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
 485             ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
 486                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
 487                         "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
 488                         sum, ah->eep_ops->get_eeprom_ver(ah));
 489                 return -EINVAL;
 490         }
 491
 492         return 0;
 493 #undef EEPROM_4K_SIZE
 494 }
 495
 496 static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah,
 497                                   enum eeprom_param param)
 498 {
 499         struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
 500         struct modal_eep_4k_header *pModal = &eep->modalHeader;
 501         struct base_eep_header_4k *pBase = &eep->baseEepHeader;
 502
 503         switch (param) {
 504         case EEP_NFTHRESH_2:
 505                 return pModal->noiseFloorThreshCh[0];
 506         case AR_EEPROM_MAC(0):
 507                 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
 508         case AR_EEPROM_MAC(1):
 509                 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
 510         case AR_EEPROM_MAC(2):
 511                 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
 512         case EEP_REG_0:
 513                 return pBase->regDmn[0];
 514         case EEP_REG_1:
 515                 return pBase->regDmn[1];
 516         case EEP_OP_CAP:
 517                 return pBase->deviceCap;
 518         case EEP_OP_MODE:
 519                 return pBase->opCapFlags;
 520         case EEP_RF_SILENT:
 521                 return pBase->rfSilent;
 522         case EEP_OB_2:
 523                 return pModal->ob_01;
 524         case EEP_DB_2:
 525                 return pModal->db1_01;
 526         case EEP_MINOR_REV:
 527                 return pBase->version & AR5416_EEP_VER_MINOR_MASK;
 528         case EEP_TX_MASK:
 529                 return pBase->txMask;
 530         case EEP_RX_MASK:
 531                 return pBase->rxMask;
 532         case EEP_FRAC_N_5G:
 533                 return 0;
 534         default:
 535                 return 0;
 536         }
 537 }
 538
 539 static void ath9k_hw_get_4k_gain_boundaries_pdadcs(struct ath_hw *ah,
 540                                 struct ath9k_channel *chan,
 541                                 struct cal_data_per_freq_4k *pRawDataSet,
 542                                 u8 *bChans, u16 availPiers,
 543                                 u16 tPdGainOverlap, int16_t *pMinCalPower,
 544                                 u16 *pPdGainBoundaries, u8 *pPDADCValues,
 545                                 u16 numXpdGains)
 546 {
 547 #define TMP_VAL_VPD_TABLE \
 548         ((vpdTableI[i][sizeCurrVpdTable - 1] + (ss - maxIndex + 1) * vpdStep));
 549         int i, j, k;
 550         int16_t ss;
 551         u16 idxL = 0, idxR = 0, numPiers;
 552         static u8 vpdTableL[AR5416_EEP4K_NUM_PD_GAINS]
 553                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
 554         static u8 vpdTableR[AR5416_EEP4K_NUM_PD_GAINS]
 555                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
 556         static u8 vpdTableI[AR5416_EEP4K_NUM_PD_GAINS]
 557                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
 558
 559         u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
 560         u8 minPwrT4[AR5416_EEP4K_NUM_PD_GAINS];
 561         u8 maxPwrT4[AR5416_EEP4K_NUM_PD_GAINS];
 562         int16_t vpdStep;
 563         int16_t tmpVal;
 564         u16 sizeCurrVpdTable, maxIndex, tgtIndex;
 565         bool match;
 566         int16_t minDelta = 0;
 567         struct chan_centers centers;
 568 #define PD_GAIN_BOUNDARY_DEFAULT 58;
 569
 570         ath9k_hw_get_channel_centers(ah, chan, &centers);
 571
 572         for (numPiers = 0; numPiers < availPiers; numPiers++) {
 573                 if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
 574                         break;
 575         }
 576
 577         match = ath9k_hw_get_lower_upper_index(
 578                                         (u8)FREQ2FBIN(centers.synth_center,
 579                                         IS_CHAN_2GHZ(chan)), bChans, numPiers,
 580                                         &idxL, &idxR);
 581
 582         if (match) {
 583                 for (i = 0; i < numXpdGains; i++) {
 584                         minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
 585                         maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
 586                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
 587                                         pRawDataSet[idxL].pwrPdg[i],
 588                                         pRawDataSet[idxL].vpdPdg[i],
 589                                         AR5416_EEP4K_PD_GAIN_ICEPTS,
 590                                         vpdTableI[i]);
 591                 }
 592         } else {
 593                 for (i = 0; i < numXpdGains; i++) {
 594                         pVpdL = pRawDataSet[idxL].vpdPdg[i];
 595                         pPwrL = pRawDataSet[idxL].pwrPdg[i];
 596                         pVpdR = pRawDataSet[idxR].vpdPdg[i];
 597                         pPwrR = pRawDataSet[idxR].pwrPdg[i];
 598
 599                         minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
 600
 601                         maxPwrT4[i] =
 602                                 min(pPwrL[AR5416_EEP4K_PD_GAIN_ICEPTS - 1],
 603                                     pPwrR[AR5416_EEP4K_PD_GAIN_ICEPTS - 1]);
 604
 605
 606                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
 607                                                 pPwrL, pVpdL,
 608                                                 AR5416_EEP4K_PD_GAIN_ICEPTS,
 609                                                 vpdTableL[i]);
 610                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
 611                                                 pPwrR, pVpdR,
 612                                                 AR5416_EEP4K_PD_GAIN_ICEPTS,
 613                                                 vpdTableR[i]);
 614
 615                         for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
 616                                 vpdTableI[i][j] =
 617                                         (u8)(ath9k_hw_interpolate((u16)
 618                                              FREQ2FBIN(centers.
 619                                                        synth_center,
 620                                                        IS_CHAN_2GHZ
 621                                                        (chan)),
 622                                              bChans[idxL], bChans[idxR],
 623                                              vpdTableL[i][j], vpdTableR[i][j]));
 624                         }
 625                 }
 626         }
 627
 628         *pMinCalPower = (int16_t)(minPwrT4[0] / 2);
 629
 630         k = 0;
 631
 632         for (i = 0; i < numXpdGains; i++) {
 633                 if (i == (numXpdGains - 1))
 634                         pPdGainBoundaries[i] =
 635                                 (u16)(maxPwrT4[i] / 2);
 636                 else
 637                         pPdGainBoundaries[i] =
 638                                 (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
 639
 640                 pPdGainBoundaries[i] =
 641                         min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
 642
 643                 if ((i == 0) && !AR_SREV_5416_V20_OR_LATER(ah)) {
 644                         minDelta = pPdGainBoundaries[0] - 23;
 645                         pPdGainBoundaries[0] = 23;
 646                 } else {
 647                         minDelta = 0;
 648                 }
 649
 650                 if (i == 0) {
 651                         if (AR_SREV_9280_10_OR_LATER(ah))
 652                                 ss = (int16_t)(0 - (minPwrT4[i] / 2));
 653                         else
 654                                 ss = 0;
 655                 } else {
 656                         ss = (int16_t)((pPdGainBoundaries[i - 1] -
 657                                         (minPwrT4[i] / 2)) -
 658                                        tPdGainOverlap + 1 + minDelta);
 659                 }
 660                 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
 661                 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
 662
 663                 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
 664                         tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
 665                         pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
 666                         ss++;
 667                 }
 668
 669                 sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
 670                 tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
 671                                 (minPwrT4[i] / 2));
 672                 maxIndex = (tgtIndex < sizeCurrVpdTable) ?
 673                         tgtIndex : sizeCurrVpdTable;
 674
 675                 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1)))
 676                         pPDADCValues[k++] = vpdTableI[i][ss++];
 677
 678                 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
 679                                     vpdTableI[i][sizeCurrVpdTable - 2]);
 680                 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
 681
 682                 if (tgtIndex > maxIndex) {
 683                         while ((ss <= tgtIndex) &&
 684                                (k < (AR5416_NUM_PDADC_VALUES - 1))) {
 685                                 tmpVal = (int16_t) TMP_VAL_VPD_TABLE;
 686                                 pPDADCValues[k++] = (u8)((tmpVal > 255) ?
 687                                                          255 : tmpVal);
 688                                 ss++;
 689                         }
 690                 }
 691         }
 692
 693         while (i < AR5416_EEP4K_PD_GAINS_IN_MASK) {
 694                 pPdGainBoundaries[i] = PD_GAIN_BOUNDARY_DEFAULT;
 695                 i++;
 696         }
 697
 698         while (k < AR5416_NUM_PDADC_VALUES) {
 699                 pPDADCValues[k] = pPDADCValues[k - 1];
 700                 k++;
 701         }
 702
 703         return;
 704 #undef TMP_VAL_VPD_TABLE
 705 }
 706
 707 static bool ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
 708                                   struct ath9k_channel *chan,
 709                                   int16_t *pTxPowerIndexOffset)
 710 {
 711         struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
 712         struct cal_data_per_freq_4k *pRawDataset;
 713         u8 *pCalBChans = NULL;
 714         u16 pdGainOverlap_t2;
 715         static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
 716         u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
 717         u16 numPiers, i, j;
 718         int16_t tMinCalPower;
 719         u16 numXpdGain, xpdMask;
 720         u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 };
 721         u32 reg32, regOffset, regChainOffset;
 722
 723         xpdMask = pEepData->modalHeader.xpdGain;
 724
 725         if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
 726             AR5416_EEP_MINOR_VER_2) {
 727                 pdGainOverlap_t2 =
 728                         pEepData->modalHeader.pdGainOverlap;
 729         } else {
 730                 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
 731                                             AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
 732         }
 733
 734         pCalBChans = pEepData->calFreqPier2G;
 735         numPiers = AR5416_NUM_2G_CAL_PIERS;
 736
 737         numXpdGain = 0;
 738
 739         for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
 740                 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
 741                         if (numXpdGain >= AR5416_NUM_PD_GAINS)
 742                                 break;
 743                         xpdGainValues[numXpdGain] =
 744                                 (u16)(AR5416_PD_GAINS_IN_MASK - i);
 745                         numXpdGain++;
 746                 }
 747         }
 748
 749         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
 750                       (numXpdGain - 1) & 0x3);
 751         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
 752                       xpdGainValues[0]);
 753         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
 754                       xpdGainValues[1]);
 755         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
 756                       xpdGainValues[2]);
 757
 758         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
 759                 if (AR_SREV_5416_V20_OR_LATER(ah) &&
 760                     (ah->rxchainmask == 5 || ah->txchainmask == 5) &&
 761                     (i != 0)) {
 762                         regChainOffset = (i == 1) ? 0x2000 : 0x1000;
 763                 } else
 764                         regChainOffset = i * 0x1000;
 765
 766                 if (pEepData->baseEepHeader.txMask & (1 << i)) {
 767                         pRawDataset = pEepData->calPierData2G[i];
 768
 769                         ath9k_hw_get_4k_gain_boundaries_pdadcs(ah, chan,
 770                                             pRawDataset, pCalBChans,
 771                                             numPiers, pdGainOverlap_t2,
 772                                             &tMinCalPower, gainBoundaries,
 773                                             pdadcValues, numXpdGain);
 774
 775                         if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) {
 776                                 REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset,
 777                                           SM(pdGainOverlap_t2,
 778                                              AR_PHY_TPCRG5_PD_GAIN_OVERLAP)
 779                                           | SM(gainBoundaries[0],
 780                                                AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
 781                                           | SM(gainBoundaries[1],
 782                                                AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
 783                                           | SM(gainBoundaries[2],
 784                                                AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
 785                                           | SM(gainBoundaries[3],
 786                                        AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
 787                         }
 788
 789                         regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
 790                         for (j = 0; j < 32; j++) {
 791                                 reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) |
 792                                         ((pdadcValues[4 * j + 1] & 0xFF) << 8) |
 793                                         ((pdadcValues[4 * j + 2] & 0xFF) << 16)|
 794                                         ((pdadcValues[4 * j + 3] & 0xFF) << 24);
 795                                 REG_WRITE(ah, regOffset, reg32);
 796
 797                                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 798                                         "PDADC (%d,%4x): %4.4x %8.8x\n",
 799                                         i, regChainOffset, regOffset,
 800                                         reg32);
 801                                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
 802                                         "PDADC: Chain %d | "
 803                                         "PDADC %3d Value %3d | "
 804                                         "PDADC %3d Value %3d | "
 805                                         "PDADC %3d Value %3d | "
 806                                         "PDADC %3d Value %3d |\n",
 807                                         i, 4 * j, pdadcValues[4 * j],
 808                                         4 * j + 1, pdadcValues[4 * j + 1],
 809                                         4 * j + 2, pdadcValues[4 * j + 2],
 810                                         4 * j + 3,
 811                                         pdadcValues[4 * j + 3]);
 812
 813                                 regOffset += 4;
 814                         }
 815                 }
 816         }
 817
 818         *pTxPowerIndexOffset = 0;
 819
 820         return true;
 821 }
 822
 823 static bool ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
 824                                                  struct ath9k_channel *chan,
 825                                                  int16_t *ratesArray,
 826                                                  u16 cfgCtl,
 827                                                  u16 AntennaReduction,
 828                                                  u16 twiceMaxRegulatoryPower,
 829                                                  u16 powerLimit)
 830 {
 831         struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
 832         u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
 833         static const u16 tpScaleReductionTable[5] =
 834                 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
 835
 836         int i;
 837         int16_t twiceLargestAntenna;
 838         struct cal_ctl_data_4k *rep;
 839         struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
 840                 0, { 0, 0, 0, 0}
 841         };
 842         struct cal_target_power_leg targetPowerOfdmExt = {
 843                 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
 844                 0, { 0, 0, 0, 0 }
 845         };
 846         struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
 847                 0, {0, 0, 0, 0}
 848         };
 849         u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
 850         u16 ctlModesFor11g[] =
 851                 { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT,
 852                   CTL_2GHT40
 853                 };
 854         u16 numCtlModes, *pCtlMode, ctlMode, freq;
 855         struct chan_centers centers;
 856         int tx_chainmask;
 857         u16 twiceMinEdgePower;
 858
 859         tx_chainmask = ah->txchainmask;
 860
 861         ath9k_hw_get_channel_centers(ah, chan, &centers);
 862
 863         twiceLargestAntenna = pEepData->modalHeader.antennaGainCh[0];
 864
 865         twiceLargestAntenna = (int16_t)min(AntennaReduction -
 866                                            twiceLargestAntenna, 0);
 867
 868         maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
 869
 870         if (ah->regulatory.tp_scale != ATH9K_TP_SCALE_MAX) {
 871                 maxRegAllowedPower -=
 872                         (tpScaleReductionTable[(ah->regulatory.tp_scale)] * 2);
 873         }
 874
 875         scaledPower = min(powerLimit, maxRegAllowedPower);
 876         scaledPower = max((u16)0, scaledPower);
 877
 878         numCtlModes = ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40;
 879         pCtlMode = ctlModesFor11g;
 880
 881         ath9k_hw_get_legacy_target_powers(ah, chan,
 882                         pEepData->calTargetPowerCck,
 883                         AR5416_NUM_2G_CCK_TARGET_POWERS,
 884                         &targetPowerCck, 4, false);
 885         ath9k_hw_get_legacy_target_powers(ah, chan,
 886                         pEepData->calTargetPower2G,
 887                         AR5416_NUM_2G_20_TARGET_POWERS,
 888                         &targetPowerOfdm, 4, false);
 889         ath9k_hw_get_target_powers(ah, chan,
 890                         pEepData->calTargetPower2GHT20,
 891                         AR5416_NUM_2G_20_TARGET_POWERS,
 892                         &targetPowerHt20, 8, false);
 893
 894         if (IS_CHAN_HT40(chan)) {
 895                 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
 896                 ath9k_hw_get_target_powers(ah, chan,
 897                                 pEepData->calTargetPower2GHT40,
 898                                 AR5416_NUM_2G_40_TARGET_POWERS,
 899                                 &targetPowerHt40, 8, true);
 900                 ath9k_hw_get_legacy_target_powers(ah, chan,
 901                                 pEepData->calTargetPowerCck,
 902                                 AR5416_NUM_2G_CCK_TARGET_POWERS,
 903                                 &targetPowerCckExt, 4, true);
 904                 ath9k_hw_get_legacy_target_powers(ah, chan,
 905                                 pEepData->calTargetPower2G,
 906                                 AR5416_NUM_2G_20_TARGET_POWERS,
 907                                 &targetPowerOfdmExt, 4, true);
 908         }
 909
 910         for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
 911                 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
 912                         (pCtlMode[ctlMode] == CTL_2GHT40);
 913                 if (isHt40CtlMode)
 914                         freq = centers.synth_center;
 915                 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
 916                         freq = centers.ext_center;
 917                 else
 918                         freq = centers.ctl_center;
 919
 920                 if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
 921                     ah->eep_ops->get_eeprom_rev(ah) <= 2)
 922                         twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
 923
 924                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
 925                         "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, "
 926                         "EXT_ADDITIVE %d\n",
 927                         ctlMode, numCtlModes, isHt40CtlMode,
 928                         (pCtlMode[ctlMode] & EXT_ADDITIVE));
 929
 930                 for (i = 0; (i < AR5416_NUM_CTLS) &&
 931                                 pEepData->ctlIndex[i]; i++) {
 932                         DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
 933                                 "  LOOP-Ctlidx %d: cfgCtl 0x%2.2x "
 934                                 "pCtlMode 0x%2.2x ctlIndex 0x%2.2x "
 935                                 "chan %d\n",
 936                                 i, cfgCtl, pCtlMode[ctlMode],
 937                                 pEepData->ctlIndex[i], chan->channel);
 938
 939                         if ((((cfgCtl & ~CTL_MODE_M) |
 940                               (pCtlMode[ctlMode] & CTL_MODE_M)) ==
 941                              pEepData->ctlIndex[i]) ||
 942                             (((cfgCtl & ~CTL_MODE_M) |
 943                               (pCtlMode[ctlMode] & CTL_MODE_M)) ==
 944                              ((pEepData->ctlIndex[i] & CTL_MODE_M) |
 945                               SD_NO_CTL))) {
 946                                 rep = &(pEepData->ctlData[i]);
 947
 948                                 twiceMinEdgePower =
 949                                         ath9k_hw_get_max_edge_power(freq,
 950                                 rep->ctlEdges[ar5416_get_ntxchains
 951                                                 (tx_chainmask) - 1],
 952                                 IS_CHAN_2GHZ(chan),
 953                                 AR5416_EEP4K_NUM_BAND_EDGES);
 954
 955                                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
 956                                         "    MATCH-EE_IDX %d: ch %d is2 %d "
 957                                         "2xMinEdge %d chainmask %d chains %d\n",
 958                                         i, freq, IS_CHAN_2GHZ(chan),
 959                                         twiceMinEdgePower, tx_chainmask,
 960                                         ar5416_get_ntxchains
 961                                         (tx_chainmask));
 962                                 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
 963                                         twiceMaxEdgePower =
 964                                                 min(twiceMaxEdgePower,
 965                                                     twiceMinEdgePower);
 966                                 } else {
 967                                         twiceMaxEdgePower = twiceMinEdgePower;
 968                                         break;
 969                                 }
 970                         }
 971                 }
 972
 973                 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
 974
 975                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
 976                         "    SEL-Min ctlMode %d pCtlMode %d "
 977                         "2xMaxEdge %d sP %d minCtlPwr %d\n",
 978                         ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
 979                         scaledPower, minCtlPower);
 980
 981                 switch (pCtlMode[ctlMode]) {
 982                 case CTL_11B:
 983                         for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x);
 984                                         i++) {
 985                                 targetPowerCck.tPow2x[i] =
 986                                         min((u16)targetPowerCck.tPow2x[i],
 987                                             minCtlPower);
 988                         }
 989                         break;
 990                 case CTL_11G:
 991                         for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x);
 992                                         i++) {
 993                                 targetPowerOfdm.tPow2x[i] =
 994                                         min((u16)targetPowerOfdm.tPow2x[i],
 995                                             minCtlPower);
 996                         }
 997                         break;
 998                 case CTL_2GHT20:
 999                         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x);
1000                                         i++) {
1001                                 targetPowerHt20.tPow2x[i] =
1002                                         min((u16)targetPowerHt20.tPow2x[i],
1003                                             minCtlPower);
1004                         }
1005                         break;
1006                 case CTL_11B_EXT:
1007                         targetPowerCckExt.tPow2x[0] = min((u16)
1008                                         targetPowerCckExt.tPow2x[0],
1009                                         minCtlPower);
1010                         break;
1011                 case CTL_11G_EXT:
1012                         targetPowerOfdmExt.tPow2x[0] = min((u16)
1013                                         targetPowerOfdmExt.tPow2x[0],
1014                                         minCtlPower);
1015                         break;
1016                 case CTL_2GHT40:
1017                         for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x);
1018                                         i++) {
1019                                 targetPowerHt40.tPow2x[i] =
1020                                         min((u16)targetPowerHt40.tPow2x[i],
1021                                             minCtlPower);
1022                         }
1023                         break;
1024                 default:
1025                         break;
1026                 }
1027         }
1028
1029         ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] =
1030                 ratesArray[rate18mb] = ratesArray[rate24mb] =
1031                 targetPowerOfdm.tPow2x[0];
1032         ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
1033         ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
1034         ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
1035         ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
1036
1037         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
1038                 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
1039
1040         ratesArray[rate1l] = targetPowerCck.tPow2x[0];
1041         ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck.tPow2x[1];
1042         ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck.tPow2x[2];
1043         ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck.tPow2x[3];
1044
1045         if (IS_CHAN_HT40(chan)) {
1046                 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
1047                         ratesArray[rateHt40_0 + i] =
1048                                 targetPowerHt40.tPow2x[i];
1049                 }
1050                 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
1051                 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
1052                 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
1053                 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
1054         }
1055         return true;
1056 }
1057
1058 static int ath9k_hw_4k_set_txpower(struct ath_hw *ah,
1059                                    struct ath9k_channel *chan,
1060                                    u16 cfgCtl,
1061                                    u8 twiceAntennaReduction,
1062                                    u8 twiceMaxRegulatoryPower,
1063                                    u8 powerLimit)
1064 {
1065         struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
1066         struct modal_eep_4k_header *pModal = &pEepData->modalHeader;
1067         int16_t ratesArray[Ar5416RateSize];
1068         int16_t txPowerIndexOffset = 0;
1069         u8 ht40PowerIncForPdadc = 2;
1070         int i;
1071
1072         memset(ratesArray, 0, sizeof(ratesArray));
1073
1074         if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1075             AR5416_EEP_MINOR_VER_2) {
1076                 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
1077         }
1078
1079         if (!ath9k_hw_set_4k_power_per_rate_table(ah, chan,
1080                                                &ratesArray[0], cfgCtl,
1081                                                twiceAntennaReduction,
1082                                                twiceMaxRegulatoryPower,
1083                                                powerLimit)) {
1084                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1085                         "ath9k_hw_set_txpower: unable to set "
1086                         "tx power per rate table\n");
1087                 return -EIO;
1088         }
1089
1090         if (!ath9k_hw_set_4k_power_cal_table(ah, chan, &txPowerIndexOffset)) {
1091                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1092                          "ath9k_hw_set_txpower: unable to set power table\n");
1093                 return -EIO;
1094         }
1095
1096         for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
1097                 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
1098                 if (ratesArray[i] > AR5416_MAX_RATE_POWER)
1099                         ratesArray[i] = AR5416_MAX_RATE_POWER;
1100         }
1101
1102         if (AR_SREV_9280_10_OR_LATER(ah)) {
1103                 for (i = 0; i < Ar5416RateSize; i++)
1104                         ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2;
1105         }
1106
1107         REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
1108                   ATH9K_POW_SM(ratesArray[rate18mb], 24)
1109                   | ATH9K_POW_SM(ratesArray[rate12mb], 16)
1110                   | ATH9K_POW_SM(ratesArray[rate9mb], 8)
1111                   | ATH9K_POW_SM(ratesArray[rate6mb], 0));
1112         REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
1113                   ATH9K_POW_SM(ratesArray[rate54mb], 24)
1114                   | ATH9K_POW_SM(ratesArray[rate48mb], 16)
1115                   | ATH9K_POW_SM(ratesArray[rate36mb], 8)
1116                   | ATH9K_POW_SM(ratesArray[rate24mb], 0));
1117
1118         if (IS_CHAN_2GHZ(chan)) {
1119                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
1120                           ATH9K_POW_SM(ratesArray[rate2s], 24)
1121                           | ATH9K_POW_SM(ratesArray[rate2l], 16)
1122                           | ATH9K_POW_SM(ratesArray[rateXr], 8)
1123                           | ATH9K_POW_SM(ratesArray[rate1l], 0));
1124                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
1125                           ATH9K_POW_SM(ratesArray[rate11s], 24)
1126                           | ATH9K_POW_SM(ratesArray[rate11l], 16)
1127                           | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
1128                           | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
1129         }
1130
1131         REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
1132                   ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
1133                   | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
1134                   | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
1135                   | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
1136         REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
1137                   ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
1138                   | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
1139                   | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
1140                   | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
1141
1142         if (IS_CHAN_HT40(chan)) {
1143                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
1144                           ATH9K_POW_SM(ratesArray[rateHt40_3] +
1145                                        ht40PowerIncForPdadc, 24)
1146                           | ATH9K_POW_SM(ratesArray[rateHt40_2] +
1147                                          ht40PowerIncForPdadc, 16)
1148                           | ATH9K_POW_SM(ratesArray[rateHt40_1] +
1149                                          ht40PowerIncForPdadc, 8)
1150                           | ATH9K_POW_SM(ratesArray[rateHt40_0] +
1151                                          ht40PowerIncForPdadc, 0));
1152                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
1153                           ATH9K_POW_SM(ratesArray[rateHt40_7] +
1154                                        ht40PowerIncForPdadc, 24)
1155                           | ATH9K_POW_SM(ratesArray[rateHt40_6] +
1156                                          ht40PowerIncForPdadc, 16)
1157                           | ATH9K_POW_SM(ratesArray[rateHt40_5] +
1158                                          ht40PowerIncForPdadc, 8)
1159                           | ATH9K_POW_SM(ratesArray[rateHt40_4] +
1160                                          ht40PowerIncForPdadc, 0));
1161
1162                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
1163                           ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
1164                           | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
1165                           | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
1166                           | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
1167         }
1168
1169         i = rate6mb;
1170
1171         if (IS_CHAN_HT40(chan))
1172                 i = rateHt40_0;
1173         else if (IS_CHAN_HT20(chan))
1174                 i = rateHt20_0;
1175
1176         if (AR_SREV_9280_10_OR_LATER(ah))
1177                 ah->regulatory.max_power_level =
1178                         ratesArray[i] + AR5416_PWR_TABLE_OFFSET * 2;
1179         else
1180                 ah->regulatory.max_power_level = ratesArray[i];
1181
1182         return 0;
1183 }
1184
1185 static void ath9k_hw_4k_set_addac(struct ath_hw *ah,
1186                                   struct ath9k_channel *chan)
1187 {
1188         struct modal_eep_4k_header *pModal;
1189         struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
1190         u8 biaslevel;
1191
1192         if (ah->hw_version.macVersion != AR_SREV_VERSION_9160)
1193                 return;
1194
1195         if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7)
1196                 return;
1197
1198         pModal = &eep->modalHeader;
1199
1200         if (pModal->xpaBiasLvl != 0xff) {
1201                 biaslevel = pModal->xpaBiasLvl;
1202                 INI_RA(&ah->iniAddac, 7, 1) =
1203                   (INI_RA(&ah->iniAddac, 7, 1) & (~0x18)) | biaslevel << 3;
1204         }
1205 }
1206
1207 static bool ath9k_hw_4k_set_board_values(struct ath_hw *ah,
1208                                          struct ath9k_channel *chan)
1209 {
1210         struct modal_eep_4k_header *pModal;
1211         struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
1212         int regChainOffset;
1213         u8 txRxAttenLocal;
1214         u8 ob[5], db1[5], db2[5];
1215         u8 ant_div_control1, ant_div_control2;
1216         u32 regVal;
1217
1218
1219         pModal = &eep->modalHeader;
1220
1221         txRxAttenLocal = 23;
1222
1223         REG_WRITE(ah, AR_PHY_SWITCH_COM,
1224                   ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
1225
1226         regChainOffset = 0;
1227         REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
1228                   pModal->antCtrlChain[0]);
1229
1230         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
1231                  (REG_READ(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset) &
1232                  ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
1233                  AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
1234                  SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
1235                  SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
1236
1237         if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1238                         AR5416_EEP_MINOR_VER_3) {
1239                 txRxAttenLocal = pModal->txRxAttenCh[0];
1240                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1241                         AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]);
1242                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1243                         AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
1244                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1245                         AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
1246                         pModal->xatten2Margin[0]);
1247                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset,
1248                         AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]);
1249         }
1250
1251         REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
1252                         AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
1253         REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset,
1254                         AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
1255
1256         if (AR_SREV_9285_11(ah))
1257                 REG_WRITE(ah, AR9285_AN_TOP4, (AR9285_AN_TOP4_DEFAULT | 0x14));
1258
1259         /* Initialize Ant Diversity settings from EEPROM */
1260         if (pModal->version == 3) {
1261                 ant_div_control1 = ((pModal->ob_234 >> 12) & 0xf);
1262                 ant_div_control2 = ((pModal->db1_234 >> 12) & 0xf);
1263                 regVal = REG_READ(ah, 0x99ac);
1264                 regVal &= (~(0x7f000000));
1265                 regVal |= ((ant_div_control1 & 0x1) << 24);
1266                 regVal |= (((ant_div_control1 >> 1) & 0x1) << 29);
1267                 regVal |= (((ant_div_control1 >> 2) & 0x1) << 30);
1268                 regVal |= ((ant_div_control2 & 0x3) << 25);
1269                 regVal |= (((ant_div_control2 >> 2) & 0x3) << 27);
1270                 REG_WRITE(ah, 0x99ac, regVal);
1271                 regVal = REG_READ(ah, 0x99ac);
1272                 regVal = REG_READ(ah, 0xa208);
1273                 regVal &= (~(0x1 << 13));
1274                 regVal |= (((ant_div_control1 >> 3) & 0x1) << 13);
1275                 REG_WRITE(ah, 0xa208, regVal);
1276                 regVal = REG_READ(ah, 0xa208);
1277         }
1278
1279         if (pModal->version >= 2) {
1280                 ob[0] = (pModal->ob_01 & 0xf);
1281                 ob[1] = (pModal->ob_01 >> 4) & 0xf;
1282                 ob[2] = (pModal->ob_234 & 0xf);
1283                 ob[3] = ((pModal->ob_234 >> 4) & 0xf);
1284                 ob[4] = ((pModal->ob_234 >> 8) & 0xf);
1285
1286                 db1[0] = (pModal->db1_01 & 0xf);
1287                 db1[1] = ((pModal->db1_01 >> 4) & 0xf);
1288                 db1[2] = (pModal->db1_234 & 0xf);
1289                 db1[3] = ((pModal->db1_234 >> 4) & 0xf);
1290                 db1[4] = ((pModal->db1_234 >> 8) & 0xf);
1291
1292                 db2[0] = (pModal->db2_01 & 0xf);
1293                 db2[1] = ((pModal->db2_01 >> 4) & 0xf);
1294                 db2[2] = (pModal->db2_234 & 0xf);
1295                 db2[3] = ((pModal->db2_234 >> 4) & 0xf);
1296                 db2[4] = ((pModal->db2_234 >> 8) & 0xf);
1297
1298         } else if (pModal->version == 1) {
1299
1300                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1301                         "EEPROM Model version is set to 1 \n");
1302                 ob[0] = (pModal->ob_01 & 0xf);
1303                 ob[1] = ob[2] = ob[3] = ob[4] = (pModal->ob_01 >> 4) & 0xf;
1304                 db1[0] = (pModal->db1_01 & 0xf);
1305                 db1[1] = db1[2] = db1[3] =
1306                         db1[4] = ((pModal->db1_01 >> 4) & 0xf);
1307                 db2[0] = (pModal->db2_01 & 0xf);
1308                 db2[1] = db2[2] = db2[3] =
1309                         db2[4] = ((pModal->db2_01 >> 4) & 0xf);
1310         } else {
1311                 int i;
1312                 for (i = 0; i < 5; i++) {
1313                         ob[i] = pModal->ob_01;
1314                         db1[i] = pModal->db1_01;
1315                         db2[i] = pModal->db1_01;
1316                 }
1317         }
1318
1319         ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
1320                         AR9285_AN_RF2G3_OB_0, AR9285_AN_RF2G3_OB_0_S, ob[0]);
1321         ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
1322                         AR9285_AN_RF2G3_OB_1, AR9285_AN_RF2G3_OB_1_S, ob[1]);
1323         ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
1324                         AR9285_AN_RF2G3_OB_2, AR9285_AN_RF2G3_OB_2_S, ob[2]);
1325         ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
1326                         AR9285_AN_RF2G3_OB_3, AR9285_AN_RF2G3_OB_3_S, ob[3]);
1327         ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
1328                         AR9285_AN_RF2G3_OB_4, AR9285_AN_RF2G3_OB_4_S, ob[4]);
1329
1330         ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
1331                         AR9285_AN_RF2G3_DB1_0, AR9285_AN_RF2G3_DB1_0_S, db1[0]);
1332         ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
1333                         AR9285_AN_RF2G3_DB1_1, AR9285_AN_RF2G3_DB1_1_S, db1[1]);
1334         ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G3,
1335                         AR9285_AN_RF2G3_DB1_2, AR9285_AN_RF2G3_DB1_2_S, db1[2]);
1336         ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4,
1337                         AR9285_AN_RF2G4_DB1_3, AR9285_AN_RF2G4_DB1_3_S, db1[3]);
1338         ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4,
1339                         AR9285_AN_RF2G4_DB1_4, AR9285_AN_RF2G4_DB1_4_S, db1[4]);
1340
1341         ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4,
1342                         AR9285_AN_RF2G4_DB2_0, AR9285_AN_RF2G4_DB2_0_S, db2[0]);
1343         ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4,
1344                         AR9285_AN_RF2G4_DB2_1, AR9285_AN_RF2G4_DB2_1_S, db2[1]);
1345         ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4,
1346                         AR9285_AN_RF2G4_DB2_2, AR9285_AN_RF2G4_DB2_2_S, db2[2]);
1347         ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4,
1348                         AR9285_AN_RF2G4_DB2_3, AR9285_AN_RF2G4_DB2_3_S, db2[3]);
1349         ath9k_hw_analog_shift_rmw(ah, AR9285_AN_RF2G4,
1350                         AR9285_AN_RF2G4_DB2_4, AR9285_AN_RF2G4_DB2_4_S, db2[4]);
1351
1352
1353         if (AR_SREV_9285_11(ah))
1354                 REG_WRITE(ah, AR9285_AN_TOP4, AR9285_AN_TOP4_DEFAULT);
1355
1356         REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
1357                       pModal->switchSettling);
1358         REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
1359                       pModal->adcDesiredSize);
1360
1361         REG_WRITE(ah, AR_PHY_RF_CTL4,
1362                   SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) |
1363                   SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) |
1364                   SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON)  |
1365                   SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON));
1366
1367         REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
1368                       pModal->txEndToRxOn);
1369         REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
1370                       pModal->thresh62);
1371         REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62,
1372                       pModal->thresh62);
1373
1374         if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1375                                                 AR5416_EEP_MINOR_VER_2) {
1376                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_DATA_START,
1377                               pModal->txFrameToDataStart);
1378                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
1379                               pModal->txFrameToPaOn);
1380         }
1381
1382         if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
1383                                                 AR5416_EEP_MINOR_VER_3) {
1384                 if (IS_CHAN_HT40(chan))
1385                         REG_RMW_FIELD(ah, AR_PHY_SETTLING,
1386                                       AR_PHY_SETTLING_SWITCH,
1387                                       pModal->swSettleHt40);
1388         }
1389
1390         return true;
1391 }
1392
1393 static u16 ath9k_hw_4k_get_eeprom_antenna_cfg(struct ath_hw *ah,
1394                                               struct ath9k_channel *chan)
1395 {
1396         struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
1397         struct modal_eep_4k_header *pModal = &eep->modalHeader;
1398
1399         return pModal->antCtrlCommon & 0xFFFF;
1400 }
1401
1402 static u8 ath9k_hw_4k_get_num_ant_config(struct ath_hw *ah,
1403                                          enum ieee80211_band freq_band)
1404 {
1405         return 1;
1406 }
1407
1408 static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1409 {
1410 #define EEP_MAP4K_SPURCHAN \
1411         (ah->eeprom.map4k.modalHeader.spurChans[i].spurChan)
1412
1413         u16 spur_val = AR_NO_SPUR;
1414
1415         DPRINTF(ah->ah_sc, ATH_DBG_ANI,
1416                 "Getting spur idx %d is2Ghz. %d val %x\n",
1417                 i, is2GHz, ah->config.spurchans[i][is2GHz]);
1418
1419         switch (ah->config.spurmode) {
1420         case SPUR_DISABLE:
1421                 break;
1422         case SPUR_ENABLE_IOCTL:
1423                 spur_val = ah->config.spurchans[i][is2GHz];
1424                 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
1425                         "Getting spur val from new loc. %d\n", spur_val);
1426                 break;
1427         case SPUR_ENABLE_EEPROM:
1428                 spur_val = EEP_MAP4K_SPURCHAN;
1429                 break;
1430         }
1431
1432         return spur_val;
1433
1434 #undef EEP_MAP4K_SPURCHAN
1435 }
1436
1437 static struct eeprom_ops eep_4k_ops = {
1438         .check_eeprom           = ath9k_hw_4k_check_eeprom,
1439         .get_eeprom             = ath9k_hw_4k_get_eeprom,
1440         .fill_eeprom            = ath9k_hw_4k_fill_eeprom,
1441         .get_eeprom_ver         = ath9k_hw_4k_get_eeprom_ver,
1442         .get_eeprom_rev         = ath9k_hw_4k_get_eeprom_rev,
1443         .get_num_ant_config     = ath9k_hw_4k_get_num_ant_config,
1444         .get_eeprom_antenna_cfg = ath9k_hw_4k_get_eeprom_antenna_cfg,
1445         .set_board_values       = ath9k_hw_4k_set_board_values,
1446         .set_addac              = ath9k_hw_4k_set_addac,
1447         .set_txpower            = ath9k_hw_4k_set_txpower,
1448         .get_spur_channel       = ath9k_hw_4k_get_spur_channel
1449 };
1450
1451 /************************************************/
1452 /* EEPROM Operations for non-4K (Default) cards */
1453 /************************************************/
1454
1455 static int ath9k_hw_def_get_eeprom_ver(struct ath_hw *ah)
1456 {
1457         return ((ah->eeprom.def.baseEepHeader.version >> 12) & 0xF);
1458 }
1459
1460 static int ath9k_hw_def_get_eeprom_rev(struct ath_hw *ah)
1461 {
1462         return ((ah->eeprom.def.baseEepHeader.version) & 0xFFF);
1463 }
1464
1465 static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
1466 {
1467 #define SIZE_EEPROM_DEF (sizeof(struct ar5416_eeprom_def) / sizeof(u16))
1468         struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1469         u16 *eep_data;
1470         int addr, ar5416_eep_start_loc = 0x100;
1471
1472         eep_data = (u16 *)eep;
1473
1474         for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) {
1475                 if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc,
1476                                          eep_data)) {
1477                         DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1478                                 "Unable to read eeprom region\n");
1479                         return false;
1480                 }
1481                 eep_data++;
1482         }
1483         return true;
1484 #undef SIZE_EEPROM_DEF
1485 }
1486
1487 static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
1488 {
1489         struct ar5416_eeprom_def *eep =
1490                 (struct ar5416_eeprom_def *) &ah->eeprom.def;
1491         u16 *eepdata, temp, magic, magic2;
1492         u32 sum = 0, el;
1493         bool need_swap = false;
1494         int i, addr, size;
1495
1496         if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
1497                                  &magic)) {
1498                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1499                         "Reading Magic # failed\n");
1500                 return false;
1501         }
1502
1503         if (!ath9k_hw_use_flash(ah)) {
1504
1505                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1506                                 "Read Magic = 0x%04X\n", magic);
1507
1508                 if (magic != AR5416_EEPROM_MAGIC) {
1509                         magic2 = swab16(magic);
1510
1511                         if (magic2 == AR5416_EEPROM_MAGIC) {
1512                                 size = sizeof(struct ar5416_eeprom_def);
1513                                 need_swap = true;
1514                                 eepdata = (u16 *) (&ah->eeprom);
1515
1516                                 for (addr = 0; addr < size / sizeof(u16); addr++) {
1517                                         temp = swab16(*eepdata);
1518                                         *eepdata = temp;
1519                                         eepdata++;
1520
1521                                         DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1522                                                 "0x%04X  ", *eepdata);
1523
1524                                         if (((addr + 1) % 6) == 0)
1525                                                 DPRINTF(ah->ah_sc,
1526                                                         ATH_DBG_EEPROM, "\n");
1527                                 }
1528                         } else {
1529                                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1530                                         "Invalid EEPROM Magic. "
1531                                         "endianness mismatch.\n");
1532                                 return -EINVAL;
1533                         }
1534                 }
1535         }
1536
1537         DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n",
1538                 need_swap ? "True" : "False");
1539
1540         if (need_swap)
1541                 el = swab16(ah->eeprom.def.baseEepHeader.length);
1542         else
1543                 el = ah->eeprom.def.baseEepHeader.length;
1544
1545         if (el > sizeof(struct ar5416_eeprom_def))
1546                 el = sizeof(struct ar5416_eeprom_def) / sizeof(u16);
1547         else
1548                 el = el / sizeof(u16);
1549
1550         eepdata = (u16 *)(&ah->eeprom);
1551
1552         for (i = 0; i < el; i++)
1553                 sum ^= *eepdata++;
1554
1555         if (need_swap) {
1556                 u32 integer, j;
1557                 u16 word;
1558
1559                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1560                         "EEPROM Endianness is not native.. Changing \n");
1561
1562                 word = swab16(eep->baseEepHeader.length);
1563                 eep->baseEepHeader.length = word;
1564
1565                 word = swab16(eep->baseEepHeader.checksum);
1566                 eep->baseEepHeader.checksum = word;
1567
1568                 word = swab16(eep->baseEepHeader.version);
1569                 eep->baseEepHeader.version = word;
1570
1571                 word = swab16(eep->baseEepHeader.regDmn[0]);
1572                 eep->baseEepHeader.regDmn[0] = word;
1573
1574                 word = swab16(eep->baseEepHeader.regDmn[1]);
1575                 eep->baseEepHeader.regDmn[1] = word;
1576
1577                 word = swab16(eep->baseEepHeader.rfSilent);
1578                 eep->baseEepHeader.rfSilent = word;
1579
1580                 word = swab16(eep->baseEepHeader.blueToothOptions);
1581                 eep->baseEepHeader.blueToothOptions = word;
1582
1583                 word = swab16(eep->baseEepHeader.deviceCap);
1584                 eep->baseEepHeader.deviceCap = word;
1585
1586                 for (j = 0; j < ARRAY_SIZE(eep->modalHeader); j++) {
1587                         struct modal_eep_header *pModal =
1588                                 &eep->modalHeader[j];
1589                         integer = swab32(pModal->antCtrlCommon);
1590                         pModal->antCtrlCommon = integer;
1591
1592                         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
1593                                 integer = swab32(pModal->antCtrlChain[i]);
1594                                 pModal->antCtrlChain[i] = integer;
1595                         }
1596
1597                         for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
1598                                 word = swab16(pModal->spurChans[i].spurChan);
1599                                 pModal->spurChans[i].spurChan = word;
1600                         }
1601                 }
1602         }
1603
1604         if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
1605             ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
1606                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1607                         "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
1608                         sum, ah->eep_ops->get_eeprom_ver(ah));
1609                 return -EINVAL;
1610         }
1611
1612         return 0;
1613 }
1614
1615 static u32 ath9k_hw_def_get_eeprom(struct ath_hw *ah,
1616                                    enum eeprom_param param)
1617 {
1618 #define AR5416_VER_MASK (pBase->version & AR5416_EEP_VER_MINOR_MASK)
1619         struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1620         struct modal_eep_header *pModal = eep->modalHeader;
1621         struct base_eep_header *pBase = &eep->baseEepHeader;
1622
1623         switch (param) {
1624         case EEP_NFTHRESH_5:
1625                 return pModal[0].noiseFloorThreshCh[0];
1626         case EEP_NFTHRESH_2:
1627                 return pModal[1].noiseFloorThreshCh[0];
1628         case AR_EEPROM_MAC(0):
1629                 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
1630         case AR_EEPROM_MAC(1):
1631                 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
1632         case AR_EEPROM_MAC(2):
1633                 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
1634         case EEP_REG_0:
1635                 return pBase->regDmn[0];
1636         case EEP_REG_1:
1637                 return pBase->regDmn[1];
1638         case EEP_OP_CAP:
1639                 return pBase->deviceCap;
1640         case EEP_OP_MODE:
1641                 return pBase->opCapFlags;
1642         case EEP_RF_SILENT:
1643                 return pBase->rfSilent;
1644         case EEP_OB_5:
1645                 return pModal[0].ob;
1646         case EEP_DB_5:
1647                 return pModal[0].db;
1648         case EEP_OB_2:
1649                 return pModal[1].ob;
1650         case EEP_DB_2:
1651                 return pModal[1].db;
1652         case EEP_MINOR_REV:
1653                 return AR5416_VER_MASK;
1654         case EEP_TX_MASK:
1655                 return pBase->txMask;
1656         case EEP_RX_MASK:
1657                 return pBase->rxMask;
1658         case EEP_RXGAIN_TYPE:
1659                 return pBase->rxGainType;
1660         case EEP_TXGAIN_TYPE:
1661                 return pBase->txGainType;
1662         case EEP_OL_PWRCTRL:
1663                 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
1664                         return pBase->openLoopPwrCntl ? true : false;
1665                 else
1666                         return false;
1667         case EEP_RC_CHAIN_MASK:
1668                 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
1669                         return pBase->rcChainMask;
1670                 else
1671                         return 0;
1672         case EEP_DAC_HPWR_5G:
1673                 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20)
1674                         return pBase->dacHiPwrMode_5G;
1675                 else
1676                         return 0;
1677         case EEP_FRAC_N_5G:
1678                 if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_22)
1679                         return pBase->frac_n_5g;
1680                 else
1681                         return 0;
1682         default:
1683                 return 0;
1684         }
1685 #undef AR5416_VER_MASK
1686 }
1687
1688 /* XXX: Clean me up, make me more legible */
1689 static bool ath9k_hw_def_set_board_values(struct ath_hw *ah,
1690                                           struct ath9k_channel *chan)
1691 {
1692 #define AR5416_VER_MASK (eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK)
1693         struct modal_eep_header *pModal;
1694         struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1695         int i, regChainOffset;
1696         u8 txRxAttenLocal;
1697
1698         pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
1699
1700         txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44;
1701
1702         REG_WRITE(ah, AR_PHY_SWITCH_COM,
1703                   ah->eep_ops->get_eeprom_antenna_cfg(ah, chan));
1704
1705         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
1706                 if (AR_SREV_9280(ah)) {
1707                         if (i >= 2)
1708                                 break;
1709                 }
1710
1711                 if (AR_SREV_5416_V20_OR_LATER(ah) &&
1712                     (ah->rxchainmask == 5 || ah->txchainmask == 5)
1713                     && (i != 0))
1714                         regChainOffset = (i == 1) ? 0x2000 : 0x1000;
1715                 else
1716                         regChainOffset = i * 0x1000;
1717
1718                 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
1719                           pModal->antCtrlChain[i]);
1720
1721                 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
1722                           (REG_READ(ah,
1723                                     AR_PHY_TIMING_CTRL4(0) +
1724                                     regChainOffset) &
1725                            ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
1726                              AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
1727                           SM(pModal->iqCalICh[i],
1728                              AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
1729                           SM(pModal->iqCalQCh[i],
1730                              AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
1731
1732                 if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) {
1733                         if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
1734                                 txRxAttenLocal = pModal->txRxAttenCh[i];
1735                                 if (AR_SREV_9280_10_OR_LATER(ah)) {
1736                                         REG_RMW_FIELD(ah,
1737                                                 AR_PHY_GAIN_2GHZ +
1738                                                 regChainOffset,
1739                                                 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
1740                                                 pModal->
1741                                                 bswMargin[i]);
1742                                         REG_RMW_FIELD(ah,
1743                                                 AR_PHY_GAIN_2GHZ +
1744                                                 regChainOffset,
1745                                                 AR_PHY_GAIN_2GHZ_XATTEN1_DB,
1746                                                 pModal->
1747                                                 bswAtten[i]);
1748                                         REG_RMW_FIELD(ah,
1749                                                 AR_PHY_GAIN_2GHZ +
1750                                                 regChainOffset,
1751                                                 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
1752                                                 pModal->
1753                                                 xatten2Margin[i]);
1754                                         REG_RMW_FIELD(ah,
1755                                                 AR_PHY_GAIN_2GHZ +
1756                                                 regChainOffset,
1757                                                 AR_PHY_GAIN_2GHZ_XATTEN2_DB,
1758                                                 pModal->
1759                                                 xatten2Db[i]);
1760                                 } else {
1761                                         REG_WRITE(ah,
1762                                                   AR_PHY_GAIN_2GHZ +
1763                                                   regChainOffset,
1764                                                   (REG_READ(ah,
1765                                                             AR_PHY_GAIN_2GHZ +
1766                                                             regChainOffset) &
1767                                                    ~AR_PHY_GAIN_2GHZ_BSW_MARGIN)
1768                                                   | SM(pModal->
1769                                                   bswMargin[i],
1770                                                   AR_PHY_GAIN_2GHZ_BSW_MARGIN));
1771                                         REG_WRITE(ah,
1772                                                   AR_PHY_GAIN_2GHZ +
1773                                                   regChainOffset,
1774                                                   (REG_READ(ah,
1775                                                             AR_PHY_GAIN_2GHZ +
1776                                                             regChainOffset) &
1777                                                    ~AR_PHY_GAIN_2GHZ_BSW_ATTEN)
1778                                                   | SM(pModal->bswAtten[i],
1779                                                   AR_PHY_GAIN_2GHZ_BSW_ATTEN));
1780                                 }
1781                         }
1782                         if (AR_SREV_9280_10_OR_LATER(ah)) {
1783                                 REG_RMW_FIELD(ah,
1784                                               AR_PHY_RXGAIN +
1785                                               regChainOffset,
1786                                               AR9280_PHY_RXGAIN_TXRX_ATTEN,
1787                                               txRxAttenLocal);
1788                                 REG_RMW_FIELD(ah,
1789                                               AR_PHY_RXGAIN +
1790                                               regChainOffset,
1791                                               AR9280_PHY_RXGAIN_TXRX_MARGIN,
1792                                               pModal->rxTxMarginCh[i]);
1793                         } else {
1794                                 REG_WRITE(ah,
1795                                           AR_PHY_RXGAIN + regChainOffset,
1796                                           (REG_READ(ah,
1797                                                     AR_PHY_RXGAIN +
1798                                                     regChainOffset) &
1799                                            ~AR_PHY_RXGAIN_TXRX_ATTEN) |
1800                                           SM(txRxAttenLocal,
1801                                              AR_PHY_RXGAIN_TXRX_ATTEN));
1802                                 REG_WRITE(ah,
1803                                           AR_PHY_GAIN_2GHZ +
1804                                           regChainOffset,
1805                                           (REG_READ(ah,
1806                                                     AR_PHY_GAIN_2GHZ +
1807                                                     regChainOffset) &
1808                                            ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
1809                                           SM(pModal->rxTxMarginCh[i],
1810                                              AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
1811                         }
1812                 }
1813         }
1814
1815         if (AR_SREV_9280_10_OR_LATER(ah)) {
1816                 if (IS_CHAN_2GHZ(chan)) {
1817                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
1818                                                   AR_AN_RF2G1_CH0_OB,
1819                                                   AR_AN_RF2G1_CH0_OB_S,
1820                                                   pModal->ob);
1821                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
1822                                                   AR_AN_RF2G1_CH0_DB,
1823                                                   AR_AN_RF2G1_CH0_DB_S,
1824                                                   pModal->db);
1825                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
1826                                                   AR_AN_RF2G1_CH1_OB,
1827                                                   AR_AN_RF2G1_CH1_OB_S,
1828                                                   pModal->ob_ch1);
1829                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
1830                                                   AR_AN_RF2G1_CH1_DB,
1831                                                   AR_AN_RF2G1_CH1_DB_S,
1832                                                   pModal->db_ch1);
1833                 } else {
1834                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
1835                                                   AR_AN_RF5G1_CH0_OB5,
1836                                                   AR_AN_RF5G1_CH0_OB5_S,
1837                                                   pModal->ob);
1838                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
1839                                                   AR_AN_RF5G1_CH0_DB5,
1840                                                   AR_AN_RF5G1_CH0_DB5_S,
1841                                                   pModal->db);
1842                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
1843                                                   AR_AN_RF5G1_CH1_OB5,
1844                                                   AR_AN_RF5G1_CH1_OB5_S,
1845                                                   pModal->ob_ch1);
1846                         ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
1847                                                   AR_AN_RF5G1_CH1_DB5,
1848                                                   AR_AN_RF5G1_CH1_DB5_S,
1849                                                   pModal->db_ch1);
1850                 }
1851                 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
1852                                           AR_AN_TOP2_XPABIAS_LVL,
1853                                           AR_AN_TOP2_XPABIAS_LVL_S,
1854                                           pModal->xpaBiasLvl);
1855                 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
1856                                           AR_AN_TOP2_LOCALBIAS,
1857                                           AR_AN_TOP2_LOCALBIAS_S,
1858                                           pModal->local_bias);
1859                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "ForceXPAon: %d\n",
1860                         pModal->force_xpaon);
1861                 REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG,
1862                               pModal->force_xpaon);
1863         }
1864
1865         REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
1866                       pModal->switchSettling);
1867         REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
1868                       pModal->adcDesiredSize);
1869
1870         if (!AR_SREV_9280_10_OR_LATER(ah))
1871                 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
1872                               AR_PHY_DESIRED_SZ_PGA,
1873                               pModal->pgaDesiredSize);
1874
1875         REG_WRITE(ah, AR_PHY_RF_CTL4,
1876                   SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
1877                   | SM(pModal->txEndToXpaOff,
1878                        AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
1879                   | SM(pModal->txFrameToXpaOn,
1880                        AR_PHY_RF_CTL4_FRAME_XPAA_ON)
1881                   | SM(pModal->txFrameToXpaOn,
1882                        AR_PHY_RF_CTL4_FRAME_XPAB_ON));
1883
1884         REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
1885                       pModal->txEndToRxOn);
1886         if (AR_SREV_9280_10_OR_LATER(ah)) {
1887                 REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
1888                               pModal->thresh62);
1889                 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
1890                               AR_PHY_EXT_CCA0_THRESH62,
1891                               pModal->thresh62);
1892         } else {
1893                 REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62,
1894                               pModal->thresh62);
1895                 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
1896                               AR_PHY_EXT_CCA_THRESH62,
1897                               pModal->thresh62);
1898         }
1899
1900         if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_2) {
1901                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
1902                               AR_PHY_TX_END_DATA_START,
1903                               pModal->txFrameToDataStart);
1904                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
1905                               pModal->txFrameToPaOn);
1906         }
1907
1908         if (AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_3) {
1909                 if (IS_CHAN_HT40(chan))
1910                         REG_RMW_FIELD(ah, AR_PHY_SETTLING,
1911                                       AR_PHY_SETTLING_SWITCH,
1912                                       pModal->swSettleHt40);
1913         }
1914
1915         if (AR_SREV_9280_20_OR_LATER(ah) &&
1916                         AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_19)
1917                 REG_RMW_FIELD(ah, AR_PHY_CCK_TX_CTRL,
1918                                 AR_PHY_CCK_TX_CTRL_TX_DAC_SCALE_CCK,
1919                                 pModal->miscBits);
1920
1921
1922         if (AR_SREV_9280_20(ah) && AR5416_VER_MASK >= AR5416_EEP_MINOR_VER_20) {
1923                 if (IS_CHAN_2GHZ(chan))
1924                         REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
1925                                         eep->baseEepHeader.dacLpMode);
1926                 else if (eep->baseEepHeader.dacHiPwrMode_5G)
1927                         REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE, 0);
1928                 else
1929                         REG_RMW_FIELD(ah, AR_AN_TOP1, AR_AN_TOP1_DACIPMODE,
1930                                         eep->baseEepHeader.dacLpMode);
1931
1932                 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL, AR_PHY_FRAME_CTL_TX_CLIP,
1933                                 pModal->miscBits >> 2);
1934
1935                 REG_RMW_FIELD(ah, AR_PHY_TX_PWRCTRL9,
1936                                 AR_PHY_TX_DESIRED_SCALE_CCK,
1937                                 eep->baseEepHeader.desiredScaleCCK);
1938         }
1939
1940         return true;
1941 #undef AR5416_VER_MASK
1942 }
1943
1944 static void ath9k_hw_def_set_addac(struct ath_hw *ah,
1945                                    struct ath9k_channel *chan)
1946 {
1947 #define XPA_LVL_FREQ(cnt) (pModal->xpaBiasLvlFreq[cnt])
1948         struct modal_eep_header *pModal;
1949         struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1950         u8 biaslevel;
1951
1952         if (ah->hw_version.macVersion != AR_SREV_VERSION_9160)
1953                 return;
1954
1955         if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7)
1956                 return;
1957
1958         pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
1959
1960         if (pModal->xpaBiasLvl != 0xff) {
1961                 biaslevel = pModal->xpaBiasLvl;
1962         } else {
1963                 u16 resetFreqBin, freqBin, freqCount = 0;
1964                 struct chan_centers centers;
1965
1966                 ath9k_hw_get_channel_centers(ah, chan, &centers);
1967
1968                 resetFreqBin = FREQ2FBIN(centers.synth_center,
1969                                          IS_CHAN_2GHZ(chan));
1970                 freqBin = XPA_LVL_FREQ(0) & 0xff;
1971                 biaslevel = (u8) (XPA_LVL_FREQ(0) >> 14);
1972
1973                 freqCount++;
1974
1975                 while (freqCount < 3) {
1976                         if (XPA_LVL_FREQ(freqCount) == 0x0)
1977                                 break;
1978
1979                         freqBin = XPA_LVL_FREQ(freqCount) & 0xff;
1980                         if (resetFreqBin >= freqBin)
1981                                 biaslevel = (u8)(XPA_LVL_FREQ(freqCount) >> 14);
1982                         else
1983                                 break;
1984                         freqCount++;
1985                 }
1986         }
1987
1988         if (IS_CHAN_2GHZ(chan)) {
1989                 INI_RA(&ah->iniAddac, 7, 1) = (INI_RA(&ah->iniAddac,
1990                                         7, 1) & (~0x18)) | biaslevel << 3;
1991         } else {
1992                 INI_RA(&ah->iniAddac, 6, 1) = (INI_RA(&ah->iniAddac,
1993                                         6, 1) & (~0xc0)) | biaslevel << 6;
1994         }
1995 #undef XPA_LVL_FREQ
1996 }
1997
1998 static void ath9k_hw_get_def_gain_boundaries_pdadcs(struct ath_hw *ah,
1999                                 struct ath9k_channel *chan,
2000                                 struct cal_data_per_freq *pRawDataSet,
2001                                 u8 *bChans, u16 availPiers,
2002                                 u16 tPdGainOverlap, int16_t *pMinCalPower,
2003                                 u16 *pPdGainBoundaries, u8 *pPDADCValues,
2004                                 u16 numXpdGains)
2005 {
2006         int i, j, k;
2007         int16_t ss;
2008         u16 idxL = 0, idxR = 0, numPiers;
2009         static u8 vpdTableL[AR5416_NUM_PD_GAINS]
2010                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
2011         static u8 vpdTableR[AR5416_NUM_PD_GAINS]
2012                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
2013         static u8 vpdTableI[AR5416_NUM_PD_GAINS]
2014                 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
2015
2016         u8 *pVpdL, *pVpdR, *pPwrL, *pPwrR;
2017         u8 minPwrT4[AR5416_NUM_PD_GAINS];
2018         u8 maxPwrT4[AR5416_NUM_PD_GAINS];
2019         int16_t vpdStep;
2020         int16_t tmpVal;
2021         u16 sizeCurrVpdTable, maxIndex, tgtIndex;
2022         bool match;
2023         int16_t minDelta = 0;
2024         struct chan_centers centers;
2025
2026         ath9k_hw_get_channel_centers(ah, chan, &centers);
2027
2028         for (numPiers = 0; numPiers < availPiers; numPiers++) {
2029                 if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
2030                         break;
2031         }
2032
2033         match = ath9k_hw_get_lower_upper_index((u8)FREQ2FBIN(centers.synth_center,
2034                                                              IS_CHAN_2GHZ(chan)),
2035                                                bChans, numPiers, &idxL, &idxR);
2036
2037         if (match) {
2038                 for (i = 0; i < numXpdGains; i++) {
2039                         minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
2040                         maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
2041                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
2042                                         pRawDataSet[idxL].pwrPdg[i],
2043                                         pRawDataSet[idxL].vpdPdg[i],
2044                                         AR5416_PD_GAIN_ICEPTS,
2045                                         vpdTableI[i]);
2046                 }
2047         } else {
2048                 for (i = 0; i < numXpdGains; i++) {
2049                         pVpdL = pRawDataSet[idxL].vpdPdg[i];
2050                         pPwrL = pRawDataSet[idxL].pwrPdg[i];
2051                         pVpdR = pRawDataSet[idxR].vpdPdg[i];
2052                         pPwrR = pRawDataSet[idxR].pwrPdg[i];
2053
2054                         minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
2055
2056                         maxPwrT4[i] =
2057                                 min(pPwrL[AR5416_PD_GAIN_ICEPTS - 1],
2058                                     pPwrR[AR5416_PD_GAIN_ICEPTS - 1]);
2059
2060
2061                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
2062                                                 pPwrL, pVpdL,
2063                                                 AR5416_PD_GAIN_ICEPTS,
2064                                                 vpdTableL[i]);
2065                         ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
2066                                                 pPwrR, pVpdR,
2067                                                 AR5416_PD_GAIN_ICEPTS,
2068                                                 vpdTableR[i]);
2069
2070                         for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
2071                                 vpdTableI[i][j] =
2072                                         (u8)(ath9k_hw_interpolate((u16)
2073                                              FREQ2FBIN(centers.
2074                                                        synth_center,
2075                                                        IS_CHAN_2GHZ
2076                                                        (chan)),
2077                                              bChans[idxL], bChans[idxR],
2078                                              vpdTableL[i][j], vpdTableR[i][j]));
2079                         }
2080                 }
2081         }
2082
2083         *pMinCalPower = (int16_t)(minPwrT4[0] / 2);
2084
2085         k = 0;
2086
2087         for (i = 0; i < numXpdGains; i++) {
2088                 if (i == (numXpdGains - 1))
2089                         pPdGainBoundaries[i] =
2090                                 (u16)(maxPwrT4[i] / 2);
2091                 else
2092                         pPdGainBoundaries[i] =
2093                                 (u16)((maxPwrT4[i] + minPwrT4[i + 1]) / 4);
2094
2095                 pPdGainBoundaries[i] =
2096                         min((u16)AR5416_MAX_RATE_POWER, pPdGainBoundaries[i]);
2097
2098                 if ((i == 0) && !AR_SREV_5416_V20_OR_LATER(ah)) {
2099                         minDelta = pPdGainBoundaries[0] - 23;
2100                         pPdGainBoundaries[0] = 23;
2101                 } else {
2102                         minDelta = 0;
2103                 }
2104
2105                 if (i == 0) {
2106                         if (AR_SREV_9280_10_OR_LATER(ah))
2107                                 ss = (int16_t)(0 - (minPwrT4[i] / 2));
2108                         else
2109                                 ss = 0;
2110                 } else {
2111                         ss = (int16_t)((pPdGainBoundaries[i - 1] -
2112                                         (minPwrT4[i] / 2)) -
2113                                        tPdGainOverlap + 1 + minDelta);
2114                 }
2115                 vpdStep = (int16_t)(vpdTableI[i][1] - vpdTableI[i][0]);
2116                 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
2117
2118                 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
2119                         tmpVal = (int16_t)(vpdTableI[i][0] + ss * vpdStep);
2120                         pPDADCValues[k++] = (u8)((tmpVal < 0) ? 0 : tmpVal);
2121                         ss++;
2122                 }
2123
2124                 sizeCurrVpdTable = (u8) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
2125                 tgtIndex = (u8)(pPdGainBoundaries[i] + tPdGainOverlap -
2126                                 (minPwrT4[i] / 2));
2127                 maxIndex = (tgtIndex < sizeCurrVpdTable) ?
2128                         tgtIndex : sizeCurrVpdTable;
2129
2130                 while ((ss < maxIndex) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
2131                         pPDADCValues[k++] = vpdTableI[i][ss++];
2132                 }
2133
2134                 vpdStep = (int16_t)(vpdTableI[i][sizeCurrVpdTable - 1] -
2135                                     vpdTableI[i][sizeCurrVpdTable - 2]);
2136                 vpdStep = (int16_t)((vpdStep < 1) ? 1 : vpdStep);
2137
2138                 if (tgtIndex > maxIndex) {
2139                         while ((ss <= tgtIndex) &&
2140                                (k < (AR5416_NUM_PDADC_VALUES - 1))) {
2141                                 tmpVal = (int16_t)((vpdTableI[i][sizeCurrVpdTable - 1] +
2142                                                     (ss - maxIndex + 1) * vpdStep));
2143                                 pPDADCValues[k++] = (u8)((tmpVal > 255) ?
2144                                                          255 : tmpVal);
2145                                 ss++;
2146                         }
2147                 }
2148         }
2149
2150         while (i < AR5416_PD_GAINS_IN_MASK) {
2151                 pPdGainBoundaries[i] = pPdGainBoundaries[i - 1];
2152                 i++;
2153         }
2154
2155         while (k < AR5416_NUM_PDADC_VALUES) {
2156                 pPDADCValues[k] = pPDADCValues[k - 1];
2157                 k++;
2158         }
2159
2160         return;
2161 }
2162
2163 static bool ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
2164                                   struct ath9k_channel *chan,
2165                                   int16_t *pTxPowerIndexOffset)
2166 {
2167 #define OLC_FOR_AR9280_20_LATER (AR_SREV_9280_20_OR_LATER(ah) && \
2168                                 ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
2169 #define SM_PD_GAIN(x) SM(0x38, AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##x)
2170 #define SM_PDGAIN_B(x, y) \
2171                 SM((gainBoundaries[x]), AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_##y)
2172
2173         struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
2174         struct cal_data_per_freq *pRawDataset;
2175         u8 *pCalBChans = NULL;
2176         u16 pdGainOverlap_t2;
2177         static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
2178         u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
2179         u16 numPiers, i, j;
2180         int16_t tMinCalPower;
2181         u16 numXpdGain, xpdMask;
2182         u16 xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 };
2183         u32 reg32, regOffset, regChainOffset;
2184         int16_t modalIdx;
2185
2186         modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0;
2187         xpdMask = pEepData->modalHeader[modalIdx].xpdGain;
2188
2189         if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
2190             AR5416_EEP_MINOR_VER_2) {
2191                 pdGainOverlap_t2 =
2192                         pEepData->modalHeader[modalIdx].pdGainOverlap;
2193         } else {
2194                 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
2195                                             AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
2196         }
2197
2198         if (IS_CHAN_2GHZ(chan)) {
2199                 pCalBChans = pEepData->calFreqPier2G;
2200                 numPiers = AR5416_NUM_2G_CAL_PIERS;
2201         } else {
2202                 pCalBChans = pEepData->calFreqPier5G;
2203                 numPiers = AR5416_NUM_5G_CAL_PIERS;
2204         }
2205
2206         if (OLC_FOR_AR9280_20_LATER && IS_CHAN_2GHZ(chan)) {
2207                 pRawDataset = pEepData->calPierData2G[0];
2208                 ah->initPDADC = ((struct calDataPerFreqOpLoop *)
2209                                  pRawDataset)->vpdPdg[0][0];
2210         }
2211
2212         numXpdGain = 0;
2213
2214         for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
2215                 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
2216                         if (numXpdGain >= AR5416_NUM_PD_GAINS)
2217                                 break;
2218                         xpdGainValues[numXpdGain] =
2219                                 (u16)(AR5416_PD_GAINS_IN_MASK - i);
2220                         numXpdGain++;
2221                 }
2222         }
2223
2224         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
2225                       (numXpdGain - 1) & 0x3);
2226         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
2227                       xpdGainValues[0]);
2228         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
2229                       xpdGainValues[1]);
2230         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
2231                       xpdGainValues[2]);
2232
2233         for (i = 0; i < AR5416_MAX_CHAINS; i++) {
2234                 if (AR_SREV_5416_V20_OR_LATER(ah) &&
2235                     (ah->rxchainmask == 5 || ah->txchainmask == 5) &&
2236                     (i != 0)) {
2237                         regChainOffset = (i == 1) ? 0x2000 : 0x1000;
2238                 } else
2239                         regChainOffset = i * 0x1000;
2240
2241                 if (pEepData->baseEepHeader.txMask & (1 << i)) {
2242                         if (IS_CHAN_2GHZ(chan))
2243                                 pRawDataset = pEepData->calPierData2G[i];
2244                         else
2245                                 pRawDataset = pEepData->calPierData5G[i];
2246
2247
2248                         if (OLC_FOR_AR9280_20_LATER) {
2249                                 u8 pcdacIdx;
2250                                 u8 txPower;
2251
2252                                 ath9k_get_txgain_index(ah, chan,
2253                                 (struct calDataPerFreqOpLoop *)pRawDataset,
2254                                 pCalBChans, numPiers, &txPower, &pcdacIdx);
2255                                 ath9k_olc_get_pdadcs(ah, pcdacIdx,
2256                                                      txPower/2, pdadcValues);
2257                         } else {
2258                                 ath9k_hw_get_def_gain_boundaries_pdadcs(ah,
2259                                                         chan, pRawDataset,
2260                                                         pCalBChans, numPiers,
2261                                                         pdGainOverlap_t2,
2262                                                         &tMinCalPower,
2263                                                         gainBoundaries,
2264                                                         pdadcValues,
2265                                                         numXpdGain);
2266                         }
2267
2268                         if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) {
2269                                 if (OLC_FOR_AR9280_20_LATER) {
2270                                         REG_WRITE(ah,
2271                                                 AR_PHY_TPCRG5 + regChainOffset,
2272                                                 SM(0x6,
2273                                                 AR_PHY_TPCRG5_PD_GAIN_OVERLAP) |
2274                                                 SM_PD_GAIN(1) | SM_PD_GAIN(2) |
2275                                                 SM_PD_GAIN(3) | SM_PD_GAIN(4));
2276                                 } else {
2277                                         REG_WRITE(ah,
2278                                                 AR_PHY_TPCRG5 + regChainOffset,
2279                                                 SM(pdGainOverlap_t2,
2280                                                 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)|
2281                                                 SM_PDGAIN_B(0, 1) |
2282                                                 SM_PDGAIN_B(1, 2) |
2283                                                 SM_PDGAIN_B(2, 3) |
2284                                                 SM_PDGAIN_B(3, 4));
2285                                 }
2286                         }
2287
2288                         regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
2289                         for (j = 0; j < 32; j++) {
2290                                 reg32 = ((pdadcValues[4 * j + 0] & 0xFF) << 0) |
2291                                         ((pdadcValues[4 * j + 1] & 0xFF) << 8) |
2292                                         ((pdadcValues[4 * j + 2] & 0xFF) << 16)|
2293                                         ((pdadcValues[4 * j + 3] & 0xFF) << 24);
2294                                 REG_WRITE(ah, regOffset, reg32);
2295
2296                                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
2297                                         "PDADC (%d,%4x): %4.4x %8.8x\n",
2298                                         i, regChainOffset, regOffset,
2299                                         reg32);
2300                                 DPRINTF(ah->ah_sc, ATH_DBG_REG_IO,
2301                                         "PDADC: Chain %d | PDADC %3d "
2302                                         "Value %3d | PDADC %3d Value %3d | "
2303                                         "PDADC %3d Value %3d | PDADC %3d "
2304                                         "Value %3d |\n",
2305                                         i, 4 * j, pdadcValues[4 * j],
2306                                         4 * j + 1, pdadcValues[4 * j + 1],
2307                                         4 * j + 2, pdadcValues[4 * j + 2],
2308                                         4 * j + 3,
2309                                         pdadcValues[4 * j + 3]);
2310
2311                                 regOffset += 4;
2312                         }
2313                 }
2314         }
2315
2316         *pTxPowerIndexOffset = 0;
2317
2318         return true;
2319 #undef SM_PD_GAIN
2320 #undef SM_PDGAIN_B
2321 }
2322
2323 static bool ath9k_hw_set_def_power_per_rate_table(struct ath_hw *ah,
2324                                                   struct ath9k_channel *chan,
2325                                                   int16_t *ratesArray,
2326                                                   u16 cfgCtl,
2327                                                   u16 AntennaReduction,
2328                                                   u16 twiceMaxRegulatoryPower,
2329                                                   u16 powerLimit)
2330 {
2331 #define REDUCE_SCALED_POWER_BY_TWO_CHAIN     6  /* 10*log10(2)*2 */
2332 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN   10 /* 10*log10(3)*2 */
2333
2334         struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
2335         u16 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
2336         static const u16 tpScaleReductionTable[5] =
2337                 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
2338
2339         int i;
2340         int16_t twiceLargestAntenna;
2341         struct cal_ctl_data *rep;
2342         struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
2343                 0, { 0, 0, 0, 0}
2344         };
2345         struct cal_target_power_leg targetPowerOfdmExt = {
2346                 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
2347                 0, { 0, 0, 0, 0 }
2348         };
2349         struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
2350                 0, {0, 0, 0, 0}
2351         };
2352         u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
2353         u16 ctlModesFor11a[] =
2354                 { CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 };
2355         u16 ctlModesFor11g[] =
2356                 { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT,
2357                   CTL_2GHT40
2358                 };
2359         u16 numCtlModes, *pCtlMode, ctlMode, freq;
2360         struct chan_centers centers;
2361         int tx_chainmask;
2362         u16 twiceMinEdgePower;
2363
2364         tx_chainmask = ah->txchainmask;
2365
2366         ath9k_hw_get_channel_centers(ah, chan, &centers);
2367
2368         twiceLargestAntenna = max(
2369                 pEepData->modalHeader
2370                         [IS_CHAN_2GHZ(chan)].antennaGainCh[0],
2371                 pEepData->modalHeader
2372                         [IS_CHAN_2GHZ(chan)].antennaGainCh[1]);
2373
2374         twiceLargestAntenna = max((u8)twiceLargestAntenna,
2375                                   pEepData->modalHeader
2376                                   [IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
2377
2378         twiceLargestAntenna = (int16_t)min(AntennaReduction -
2379                                            twiceLargestAntenna, 0);
2380
2381         maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
2382
2383         if (ah->regulatory.tp_scale != ATH9K_TP_SCALE_MAX) {
2384                 maxRegAllowedPower -=
2385                         (tpScaleReductionTable[(ah->regulatory.tp_scale)] * 2);
2386         }
2387
2388         scaledPower = min(powerLimit, maxRegAllowedPower);
2389
2390         switch (ar5416_get_ntxchains(tx_chainmask)) {
2391         case 1:
2392                 break;
2393         case 2:
2394                 scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
2395                 break;
2396         case 3:
2397                 scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
2398                 break;
2399         }
2400
2401         scaledPower = max((u16)0, scaledPower);
2402
2403         if (IS_CHAN_2GHZ(chan)) {
2404                 numCtlModes = ARRAY_SIZE(ctlModesFor11g) -
2405                         SUB_NUM_CTL_MODES_AT_2G_40;
2406                 pCtlMode = ctlModesFor11g;
2407
2408                 ath9k_hw_get_legacy_target_powers(ah, chan,
2409                         pEepData->calTargetPowerCck,
2410                         AR5416_NUM_2G_CCK_TARGET_POWERS,
2411                         &targetPowerCck, 4, false);
2412                 ath9k_hw_get_legacy_target_powers(ah, chan,
2413                         pEepData->calTargetPower2G,
2414                         AR5416_NUM_2G_20_TARGET_POWERS,
2415                         &targetPowerOfdm, 4, false);
2416                 ath9k_hw_get_target_powers(ah, chan,
2417                         pEepData->calTargetPower2GHT20,
2418                         AR5416_NUM_2G_20_TARGET_POWERS,
2419                         &targetPowerHt20, 8, false);
2420
2421                 if (IS_CHAN_HT40(chan)) {
2422                         numCtlModes = ARRAY_SIZE(ctlModesFor11g);
2423                         ath9k_hw_get_target_powers(ah, chan,
2424                                 pEepData->calTargetPower2GHT40,
2425                                 AR5416_NUM_2G_40_TARGET_POWERS,
2426                                 &targetPowerHt40, 8, true);
2427                         ath9k_hw_get_legacy_target_powers(ah, chan,
2428                                 pEepData->calTargetPowerCck,
2429                                 AR5416_NUM_2G_CCK_TARGET_POWERS,
2430                                 &targetPowerCckExt, 4, true);
2431                         ath9k_hw_get_legacy_target_powers(ah, chan,
2432                                 pEepData->calTargetPower2G,
2433                                 AR5416_NUM_2G_20_TARGET_POWERS,
2434                                 &targetPowerOfdmExt, 4, true);
2435                 }
2436         } else {
2437                 numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
2438                         SUB_NUM_CTL_MODES_AT_5G_40;
2439                 pCtlMode = ctlModesFor11a;
2440
2441                 ath9k_hw_get_legacy_target_powers(ah, chan,
2442                         pEepData->calTargetPower5G,
2443                         AR5416_NUM_5G_20_TARGET_POWERS,
2444                         &targetPowerOfdm, 4, false);
2445                 ath9k_hw_get_target_powers(ah, chan,
2446                         pEepData->calTargetPower5GHT20,
2447                         AR5416_NUM_5G_20_TARGET_POWERS,
2448                         &targetPowerHt20, 8, false);
2449
2450                 if (IS_CHAN_HT40(chan)) {
2451                         numCtlModes = ARRAY_SIZE(ctlModesFor11a);
2452                         ath9k_hw_get_target_powers(ah, chan,
2453                                 pEepData->calTargetPower5GHT40,
2454                                 AR5416_NUM_5G_40_TARGET_POWERS,
2455                                 &targetPowerHt40, 8, true);
2456                         ath9k_hw_get_legacy_target_powers(ah, chan,
2457                                 pEepData->calTargetPower5G,
2458                                 AR5416_NUM_5G_20_TARGET_POWERS,
2459                                 &targetPowerOfdmExt, 4, true);
2460                 }
2461         }
2462
2463         for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
2464                 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
2465                         (pCtlMode[ctlMode] == CTL_2GHT40);
2466                 if (isHt40CtlMode)
2467                         freq = centers.synth_center;
2468                 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
2469                         freq = centers.ext_center;
2470                 else
2471                         freq = centers.ctl_center;
2472
2473                 if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
2474                     ah->eep_ops->get_eeprom_rev(ah) <= 2)
2475                         twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
2476
2477                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2478                         "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, "
2479                         "EXT_ADDITIVE %d\n",
2480                         ctlMode, numCtlModes, isHt40CtlMode,
2481                         (pCtlMode[ctlMode] & EXT_ADDITIVE));
2482
2483                 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i]; i++) {
2484                         DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2485                                 "  LOOP-Ctlidx %d: cfgCtl 0x%2.2x "
2486                                 "pCtlMode 0x%2.2x ctlIndex 0x%2.2x "
2487                                 "chan %d\n",
2488                                 i, cfgCtl, pCtlMode[ctlMode],
2489                                 pEepData->ctlIndex[i], chan->channel);
2490
2491                         if ((((cfgCtl & ~CTL_MODE_M) |
2492                               (pCtlMode[ctlMode] & CTL_MODE_M)) ==
2493                              pEepData->ctlIndex[i]) ||
2494                             (((cfgCtl & ~CTL_MODE_M) |
2495                               (pCtlMode[ctlMode] & CTL_MODE_M)) ==
2496                              ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) {
2497                                 rep = &(pEepData->ctlData[i]);
2498
2499                                 twiceMinEdgePower = ath9k_hw_get_max_edge_power(freq,
2500                                 rep->ctlEdges[ar5416_get_ntxchains(tx_chainmask) - 1],
2501                                 IS_CHAN_2GHZ(chan), AR5416_NUM_BAND_EDGES);
2502
2503                                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2504                                         "    MATCH-EE_IDX %d: ch %d is2 %d "
2505                                         "2xMinEdge %d chainmask %d chains %d\n",
2506                                         i, freq, IS_CHAN_2GHZ(chan),
2507                                         twiceMinEdgePower, tx_chainmask,
2508                                         ar5416_get_ntxchains
2509                                         (tx_chainmask));
2510                                 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
2511                                         twiceMaxEdgePower = min(twiceMaxEdgePower,
2512                                                                 twiceMinEdgePower);
2513                                 } else {
2514                                         twiceMaxEdgePower = twiceMinEdgePower;
2515                                         break;
2516                                 }
2517                         }
2518                 }
2519
2520                 minCtlPower = min(twiceMaxEdgePower, scaledPower);
2521
2522                 DPRINTF(ah->ah_sc, ATH_DBG_POWER_MGMT,
2523                         "    SEL-Min ctlMode %d pCtlMode %d "
2524                         "2xMaxEdge %d sP %d minCtlPwr %d\n",
2525                         ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
2526                         scaledPower, minCtlPower);
2527
2528                 switch (pCtlMode[ctlMode]) {
2529                 case CTL_11B:
2530                         for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
2531                                 targetPowerCck.tPow2x[i] =
2532                                         min((u16)targetPowerCck.tPow2x[i],
2533                                             minCtlPower);
2534                         }
2535                         break;
2536                 case CTL_11A:
2537                 case CTL_11G:
2538                         for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
2539                                 targetPowerOfdm.tPow2x[i] =
2540                                         min((u16)targetPowerOfdm.tPow2x[i],
2541                                             minCtlPower);
2542                         }
2543                         break;
2544                 case CTL_5GHT20:
2545                 case CTL_2GHT20:
2546                         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
2547                                 targetPowerHt20.tPow2x[i] =
2548                                         min((u16)targetPowerHt20.tPow2x[i],
2549                                             minCtlPower);
2550                         }
2551                         break;
2552                 case CTL_11B_EXT:
2553                         targetPowerCckExt.tPow2x[0] = min((u16)
2554                                         targetPowerCckExt.tPow2x[0],
2555                                         minCtlPower);
2556                         break;
2557                 case CTL_11A_EXT:
2558                 case CTL_11G_EXT:
2559                         targetPowerOfdmExt.tPow2x[0] = min((u16)
2560                                         targetPowerOfdmExt.tPow2x[0],
2561                                         minCtlPower);
2562                         break;
2563                 case CTL_5GHT40:
2564                 case CTL_2GHT40:
2565                         for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
2566                                 targetPowerHt40.tPow2x[i] =
2567                                         min((u16)targetPowerHt40.tPow2x[i],
2568                                             minCtlPower);
2569                         }
2570                         break;
2571                 default:
2572                         break;
2573                 }
2574         }
2575
2576         ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] =
2577                 ratesArray[rate18mb] = ratesArray[rate24mb] =
2578                 targetPowerOfdm.tPow2x[0];
2579         ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
2580         ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
2581         ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
2582         ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
2583
2584         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
2585                 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
2586
2587         if (IS_CHAN_2GHZ(chan)) {
2588                 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
2589                 ratesArray[rate2s] = ratesArray[rate2l] =
2590                         targetPowerCck.tPow2x[1];
2591                 ratesArray[rate5_5s] = ratesArray[rate5_5l] =
2592                         targetPowerCck.tPow2x[2];
2593                 ;
2594                 ratesArray[rate11s] = ratesArray[rate11l] =
2595                         targetPowerCck.tPow2x[3];
2596                 ;
2597         }
2598         if (IS_CHAN_HT40(chan)) {
2599                 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
2600                         ratesArray[rateHt40_0 + i] =
2601                                 targetPowerHt40.tPow2x[i];
2602                 }
2603                 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
2604                 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
2605                 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
2606                 if (IS_CHAN_2GHZ(chan)) {
2607                         ratesArray[rateExtCck] =
2608                                 targetPowerCckExt.tPow2x[0];
2609                 }
2610         }
2611         return true;
2612 }
2613
2614 static int ath9k_hw_def_set_txpower(struct ath_hw *ah,
2615                                     struct ath9k_channel *chan,
2616                                     u16 cfgCtl,
2617                                     u8 twiceAntennaReduction,
2618                                     u8 twiceMaxRegulatoryPower,
2619                                     u8 powerLimit)
2620 {
2621 #define RT_AR_DELTA(x) (ratesArray[x] - cck_ofdm_delta)
2622         struct ar5416_eeprom_def *pEepData = &ah->eeprom.def;
2623         struct modal_eep_header *pModal =
2624                 &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]);
2625         int16_t ratesArray[Ar5416RateSize];
2626         int16_t txPowerIndexOffset = 0;
2627         u8 ht40PowerIncForPdadc = 2;
2628         int i, cck_ofdm_delta = 0;
2629
2630         memset(ratesArray, 0, sizeof(ratesArray));
2631
2632         if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
2633             AR5416_EEP_MINOR_VER_2) {
2634                 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
2635         }
2636
2637         if (!ath9k_hw_set_def_power_per_rate_table(ah, chan,
2638                                                &ratesArray[0], cfgCtl,
2639                                                twiceAntennaReduction,
2640                                                twiceMaxRegulatoryPower,
2641                                                powerLimit)) {
2642                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2643                         "ath9k_hw_set_txpower: unable to set "
2644                         "tx power per rate table\n");
2645                 return -EIO;
2646         }
2647
2648         if (!ath9k_hw_set_def_power_cal_table(ah, chan, &txPowerIndexOffset)) {
2649                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2650                          "ath9k_hw_set_txpower: unable to set power table\n");
2651                 return -EIO;
2652         }
2653
2654         for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
2655                 ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]);
2656                 if (ratesArray[i] > AR5416_MAX_RATE_POWER)
2657                         ratesArray[i] = AR5416_MAX_RATE_POWER;
2658         }
2659
2660         if (AR_SREV_9280_10_OR_LATER(ah)) {
2661                 for (i = 0; i < Ar5416RateSize; i++)
2662                         ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2;
2663         }
2664
2665         REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
2666                   ATH9K_POW_SM(ratesArray[rate18mb], 24)
2667                   | ATH9K_POW_SM(ratesArray[rate12mb], 16)
2668                   | ATH9K_POW_SM(ratesArray[rate9mb], 8)
2669                   | ATH9K_POW_SM(ratesArray[rate6mb], 0));
2670         REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
2671                   ATH9K_POW_SM(ratesArray[rate54mb], 24)
2672                   | ATH9K_POW_SM(ratesArray[rate48mb], 16)
2673                   | ATH9K_POW_SM(ratesArray[rate36mb], 8)
2674                   | ATH9K_POW_SM(ratesArray[rate24mb], 0));
2675
2676         if (IS_CHAN_2GHZ(chan)) {
2677                 if (OLC_FOR_AR9280_20_LATER) {
2678                         cck_ofdm_delta = 2;
2679                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
2680                                 ATH9K_POW_SM(RT_AR_DELTA(rate2s), 24)
2681                                 | ATH9K_POW_SM(RT_AR_DELTA(rate2l), 16)
2682                                 | ATH9K_POW_SM(ratesArray[rateXr], 8)
2683                                 | ATH9K_POW_SM(RT_AR_DELTA(rate1l), 0));
2684                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
2685                                 ATH9K_POW_SM(RT_AR_DELTA(rate11s), 24)
2686                                 | ATH9K_POW_SM(RT_AR_DELTA(rate11l), 16)
2687                                 | ATH9K_POW_SM(RT_AR_DELTA(rate5_5s), 8)
2688                                 | ATH9K_POW_SM(RT_AR_DELTA(rate5_5l), 0));
2689                 } else {
2690                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
2691                                 ATH9K_POW_SM(ratesArray[rate2s], 24)
2692                                 | ATH9K_POW_SM(ratesArray[rate2l], 16)
2693                                 | ATH9K_POW_SM(ratesArray[rateXr], 8)
2694                                 | ATH9K_POW_SM(ratesArray[rate1l], 0));
2695                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
2696                                 ATH9K_POW_SM(ratesArray[rate11s], 24)
2697                                 | ATH9K_POW_SM(ratesArray[rate11l], 16)
2698                                 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
2699                                 | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
2700                 }
2701         }
2702
2703         REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
2704                   ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
2705                   | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
2706                   | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
2707                   | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
2708         REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
2709                   ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
2710                   | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
2711                   | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
2712                   | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
2713
2714         if (IS_CHAN_HT40(chan)) {
2715                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
2716                           ATH9K_POW_SM(ratesArray[rateHt40_3] +
2717                                        ht40PowerIncForPdadc, 24)
2718                           | ATH9K_POW_SM(ratesArray[rateHt40_2] +
2719                                          ht40PowerIncForPdadc, 16)
2720                           | ATH9K_POW_SM(ratesArray[rateHt40_1] +
2721                                          ht40PowerIncForPdadc, 8)
2722                           | ATH9K_POW_SM(ratesArray[rateHt40_0] +
2723                                          ht40PowerIncForPdadc, 0));
2724                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
2725                           ATH9K_POW_SM(ratesArray[rateHt40_7] +
2726                                        ht40PowerIncForPdadc, 24)
2727                           | ATH9K_POW_SM(ratesArray[rateHt40_6] +
2728                                          ht40PowerIncForPdadc, 16)
2729                           | ATH9K_POW_SM(ratesArray[rateHt40_5] +
2730                                          ht40PowerIncForPdadc, 8)
2731                           | ATH9K_POW_SM(ratesArray[rateHt40_4] +
2732                                          ht40PowerIncForPdadc, 0));
2733                 if (OLC_FOR_AR9280_20_LATER) {
2734                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
2735                                 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
2736                                 | ATH9K_POW_SM(RT_AR_DELTA(rateExtCck), 16)
2737                                 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
2738                                 | ATH9K_POW_SM(RT_AR_DELTA(rateDupCck), 0));
2739                 } else {
2740                         REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
2741                                 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
2742                                 | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
2743                                 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
2744                                 | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
2745                 }
2746         }
2747
2748         REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
2749                   ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6)
2750                   | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0));
2751
2752         i = rate6mb;
2753
2754         if (IS_CHAN_HT40(chan))
2755                 i = rateHt40_0;
2756         else if (IS_CHAN_HT20(chan))
2757                 i = rateHt20_0;
2758
2759         if (AR_SREV_9280_10_OR_LATER(ah))
2760                 ah->regulatory.max_power_level =
2761                         ratesArray[i] + AR5416_PWR_TABLE_OFFSET * 2;
2762         else
2763                 ah->regulatory.max_power_level = ratesArray[i];
2764
2765         switch(ar5416_get_ntxchains(ah->txchainmask)) {
2766         case 1:
2767                 break;
2768         case 2:
2769                 ah->regulatory.max_power_level += INCREASE_MAXPOW_BY_TWO_CHAIN;
2770                 break;
2771         case 3:
2772                 ah->regulatory.max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
2773                 break;
2774         default:
2775                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
2776                         "Invalid chainmask configuration\n");
2777                 break;
2778         }
2779
2780         return 0;
2781 }
2782
2783 static u8 ath9k_hw_def_get_num_ant_config(struct ath_hw *ah,
2784                                           enum ieee80211_band freq_band)
2785 {
2786         struct ar5416_eeprom_def *eep = &ah->eeprom.def;
2787         struct modal_eep_header *pModal =
2788                 &(eep->modalHeader[ATH9K_HAL_FREQ_BAND_2GHZ == freq_band]);
2789         struct base_eep_header *pBase = &eep->baseEepHeader;
2790         u8 num_ant_config;
2791
2792         num_ant_config = 1;
2793
2794         if (pBase->version >= 0x0E0D)
2795                 if (pModal->useAnt1)
2796                         num_ant_config += 1;
2797
2798         return num_ant_config;
2799 }
2800
2801 static u16 ath9k_hw_def_get_eeprom_antenna_cfg(struct ath_hw *ah,
2802                                                struct ath9k_channel *chan)
2803 {
2804         struct ar5416_eeprom_def *eep = &ah->eeprom.def;
2805         struct modal_eep_header *pModal =
2806                 &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
2807
2808         return pModal->antCtrlCommon & 0xFFFF;
2809 }
2810
2811 static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
2812 {
2813 #define EEP_DEF_SPURCHAN \
2814         (ah->eeprom.def.modalHeader[is2GHz].spurChans[i].spurChan)
2815
2816         u16 spur_val = AR_NO_SPUR;
2817
2818         DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2819                 "Getting spur idx %d is2Ghz. %d val %x\n",
2820                 i, is2GHz, ah->config.spurchans[i][is2GHz]);
2821
2822         switch (ah->config.spurmode) {
2823         case SPUR_DISABLE:
2824                 break;
2825         case SPUR_ENABLE_IOCTL:
2826                 spur_val = ah->config.spurchans[i][is2GHz];
2827                 DPRINTF(ah->ah_sc, ATH_DBG_ANI,
2828                         "Getting spur val from new loc. %d\n", spur_val);
2829                 break;
2830         case SPUR_ENABLE_EEPROM:
2831                 spur_val = EEP_DEF_SPURCHAN;
2832                 break;
2833         }
2834
2835         return spur_val;
2836
2837 #undef EEP_DEF_SPURCHAN
2838 }
2839
2840 static struct eeprom_ops eep_def_ops = {
2841         .check_eeprom           = ath9k_hw_def_check_eeprom,
2842         .get_eeprom             = ath9k_hw_def_get_eeprom,
2843         .fill_eeprom            = ath9k_hw_def_fill_eeprom,
2844         .get_eeprom_ver         = ath9k_hw_def_get_eeprom_ver,
2845         .get_eeprom_rev         = ath9k_hw_def_get_eeprom_rev,
2846         .get_num_ant_config     = ath9k_hw_def_get_num_ant_config,
2847         .get_eeprom_antenna_cfg = ath9k_hw_def_get_eeprom_antenna_cfg,
2848         .set_board_values       = ath9k_hw_def_set_board_values,
2849         .set_addac              = ath9k_hw_def_set_addac,
2850         .set_txpower            = ath9k_hw_def_set_txpower,
2851         .get_spur_channel       = ath9k_hw_def_get_spur_channel
2852 };
2853
2854 int ath9k_hw_eeprom_attach(struct ath_hw *ah)
2855 {
2856         int status;
2857
2858         if (AR_SREV_9285(ah)) {
2859                 ah->eep_map = EEP_MAP_4KBITS;
2860                 ah->eep_ops = &eep_4k_ops;
2861         } else {
2862                 ah->eep_map = EEP_MAP_DEFAULT;
2863                 ah->eep_ops = &eep_def_ops;
2864         }
2865
2866         if (!ah->eep_ops->fill_eeprom(ah))
2867                 return -EIO;
2868
2869         status = ah->eep_ops->check_eeprom(ah);
2870
2871         return status;
2872 }