2 * Copyright (c) 2008, Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 /* Implementation of the main "ATH" layer. */
22 static int ath_outdoor; /* enable outdoor use */
24 static u32 ath_chainmask_sel_up_rssi_thres =
25 ATH_CHAINMASK_SEL_UP_RSSI_THRES;
26 static u32 ath_chainmask_sel_down_rssi_thres =
27 ATH_CHAINMASK_SEL_DOWN_RSSI_THRES;
28 static u32 ath_chainmask_sel_period =
29 ATH_CHAINMASK_SEL_TIMEOUT;
31 /* return bus cachesize in 4B word units */
33 static void bus_read_cachesize(struct ath_softc *sc, int *csz)
37 pci_read_config_byte(sc->pdev, PCI_CACHE_LINE_SIZE, (u8 *)&u8tmp);
41 * This check was put in to avoid "unplesant" consequences if
42 * the bootrom has not fully initialized all PCI devices.
43 * Sometimes the cache line size register is not set
47 *csz = DEFAULT_CACHELINE >> 2; /* Use the default size */
51 * Set current operating mode
53 * This function initializes and fills the rate table in the ATH object based
54 * on the operating mode. The blink rates are also set up here, although
55 * they have been superceeded by the ath_led module.
58 static void ath_setcurmode(struct ath_softc *sc, enum wireless_mode mode)
60 const struct ath9k_rate_table *rt;
63 memset(sc->sc_rixmap, 0xff, sizeof(sc->sc_rixmap));
64 rt = ath9k_hw_getratetable(sc->sc_ah, mode);
67 for (i = 0; i < rt->rateCount; i++)
68 sc->sc_rixmap[rt->info[i].rateCode] = (u8) i;
70 memzero(sc->sc_hwmap, sizeof(sc->sc_hwmap));
71 for (i = 0; i < 256; i++) {
72 u8 ix = rt->rateCodeToIndex[i];
77 sc->sc_hwmap[i].ieeerate =
78 rt->info[ix].dot11Rate & IEEE80211_RATE_VAL;
79 sc->sc_hwmap[i].rateKbps = rt->info[ix].rateKbps;
81 if (rt->info[ix].shortPreamble ||
82 rt->info[ix].phy == PHY_OFDM) {
83 /* XXX: Handle this */
86 /* NB: this uses the last entry if the rate isn't found */
87 /* XXX beware of overlow */
90 sc->sc_curmode = mode;
92 * All protection frames are transmited at 2Mb/s for
93 * 11g, otherwise at 1Mb/s.
94 * XXX select protection rate index from rate table.
96 sc->sc_protrix = (mode == ATH9K_MODE_11G ? 1 : 0);
100 * Set up rate table (legacy rates)
102 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
104 struct ath_hal *ah = sc->sc_ah;
105 const struct ath9k_rate_table *rt = NULL;
106 struct ieee80211_supported_band *sband;
107 struct ieee80211_rate *rate;
111 case IEEE80211_BAND_2GHZ:
112 rt = ath9k_hw_getratetable(ah, ATH9K_MODE_11G);
114 case IEEE80211_BAND_5GHZ:
115 rt = ath9k_hw_getratetable(ah, ATH9K_MODE_11A);
124 sband = &sc->sbands[band];
125 rate = sc->rates[band];
127 if (rt->rateCount > ATH_RATE_MAX)
128 maxrates = ATH_RATE_MAX;
130 maxrates = rt->rateCount;
132 for (i = 0; i < maxrates; i++) {
133 rate[i].bitrate = rt->info[i].rateKbps / 100;
134 rate[i].hw_value = rt->info[i].rateCode;
136 DPRINTF(sc, ATH_DBG_CONFIG,
137 "%s: Rate: %2dMbps, ratecode: %2d\n",
139 rate[i].bitrate / 10,
145 * Set up channel list
147 static int ath_setup_channels(struct ath_softc *sc)
149 struct ath_hal *ah = sc->sc_ah;
150 int nchan, i, a = 0, b = 0;
151 u8 regclassids[ATH_REGCLASSIDS_MAX];
153 struct ieee80211_supported_band *band_2ghz;
154 struct ieee80211_supported_band *band_5ghz;
155 struct ieee80211_channel *chan_2ghz;
156 struct ieee80211_channel *chan_5ghz;
157 struct ath9k_channel *c;
159 /* Fill in ah->ah_channels */
160 if (!ath9k_regd_init_channels(ah,
169 u32 rd = ah->ah_currentRD;
171 DPRINTF(sc, ATH_DBG_FATAL,
172 "%s: unable to collect channel list; "
173 "regdomain likely %u country code %u\n",
174 __func__, rd, CTRY_DEFAULT);
178 band_2ghz = &sc->sbands[IEEE80211_BAND_2GHZ];
179 band_5ghz = &sc->sbands[IEEE80211_BAND_5GHZ];
180 chan_2ghz = sc->channels[IEEE80211_BAND_2GHZ];
181 chan_5ghz = sc->channels[IEEE80211_BAND_5GHZ];
183 for (i = 0; i < nchan; i++) {
184 c = &ah->ah_channels[i];
185 if (IS_CHAN_2GHZ(c)) {
186 chan_2ghz[a].band = IEEE80211_BAND_2GHZ;
187 chan_2ghz[a].center_freq = c->channel;
188 chan_2ghz[a].max_power = c->maxTxPower;
190 if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
191 chan_2ghz[a].flags |=
192 IEEE80211_CHAN_NO_IBSS;
193 if (c->channelFlags & CHANNEL_PASSIVE)
194 chan_2ghz[a].flags |=
195 IEEE80211_CHAN_PASSIVE_SCAN;
197 band_2ghz->n_channels = ++a;
199 DPRINTF(sc, ATH_DBG_CONFIG,
200 "%s: 2MHz channel: %d, "
201 "channelFlags: 0x%x\n",
205 } else if (IS_CHAN_5GHZ(c)) {
206 chan_5ghz[b].band = IEEE80211_BAND_5GHZ;
207 chan_5ghz[b].center_freq = c->channel;
208 chan_5ghz[b].max_power = c->maxTxPower;
210 if (c->privFlags & CHANNEL_DISALLOW_ADHOC)
211 chan_5ghz[b].flags |=
212 IEEE80211_CHAN_NO_IBSS;
213 if (c->channelFlags & CHANNEL_PASSIVE)
214 chan_5ghz[b].flags |=
215 IEEE80211_CHAN_PASSIVE_SCAN;
217 band_5ghz->n_channels = ++b;
219 DPRINTF(sc, ATH_DBG_CONFIG,
220 "%s: 5MHz channel: %d, "
221 "channelFlags: 0x%x\n",
232 * Determine mode from channel flags
234 * This routine will provide the enumerated WIRELESSS_MODE value based
235 * on the settings of the channel flags. If ho valid set of flags
236 * exist, the lowest mode (11b) is selected.
239 static enum wireless_mode ath_chan2mode(struct ath9k_channel *chan)
241 if (chan->chanmode == CHANNEL_A)
242 return ATH9K_MODE_11A;
243 else if (chan->chanmode == CHANNEL_G)
244 return ATH9K_MODE_11G;
245 else if (chan->chanmode == CHANNEL_B)
246 return ATH9K_MODE_11B;
247 else if (chan->chanmode == CHANNEL_A_HT20)
248 return ATH9K_MODE_11NA_HT20;
249 else if (chan->chanmode == CHANNEL_G_HT20)
250 return ATH9K_MODE_11NG_HT20;
251 else if (chan->chanmode == CHANNEL_A_HT40PLUS)
252 return ATH9K_MODE_11NA_HT40PLUS;
253 else if (chan->chanmode == CHANNEL_A_HT40MINUS)
254 return ATH9K_MODE_11NA_HT40MINUS;
255 else if (chan->chanmode == CHANNEL_G_HT40PLUS)
256 return ATH9K_MODE_11NG_HT40PLUS;
257 else if (chan->chanmode == CHANNEL_G_HT40MINUS)
258 return ATH9K_MODE_11NG_HT40MINUS;
260 /* NB: should not get here */
261 return ATH9K_MODE_11B;
265 * Stop the device, grabbing the top-level lock to protect
266 * against concurrent entry through ath_init (which can happen
267 * if another thread does a system call and the thread doing the
268 * stop is preempted).
271 static int ath_stop(struct ath_softc *sc)
273 struct ath_hal *ah = sc->sc_ah;
275 DPRINTF(sc, ATH_DBG_CONFIG, "%s: invalid %ld\n",
276 __func__, sc->sc_flags & SC_OP_INVALID);
279 * Shutdown the hardware and driver:
280 * stop output from above
281 * reset 802.11 state machine
282 * (sends station deassoc/deauth frames)
285 * clear transmit machinery
286 * clear receive machinery
288 * reclaim beacon resources
290 * Note that some of this work is not possible if the
291 * hardware is gone (invalid).
294 if (!(sc->sc_flags & SC_OP_INVALID))
295 ath9k_hw_set_interrupts(ah, 0);
296 ath_draintxq(sc, false);
297 if (!(sc->sc_flags & SC_OP_INVALID)) {
299 ath9k_hw_phy_disable(ah);
301 sc->sc_rxlink = NULL;
307 * Set the current channel
309 * Set/change channels. If the channel is really being changed, it's done
310 * by reseting the chip. To accomplish this we must first cleanup any pending
311 * DMA, then restart stuff after a la ath_init.
313 int ath_set_channel(struct ath_softc *sc, struct ath9k_channel *hchan)
315 struct ath_hal *ah = sc->sc_ah;
316 bool fastcc = true, stopped;
318 if (sc->sc_flags & SC_OP_INVALID) /* the device is invalid or removed */
321 DPRINTF(sc, ATH_DBG_CONFIG,
322 "%s: %u (%u MHz) -> %u (%u MHz), cflags:%x\n",
324 ath9k_hw_mhz2ieee(ah, sc->sc_ah->ah_curchan->channel,
325 sc->sc_ah->ah_curchan->channelFlags),
326 sc->sc_ah->ah_curchan->channel,
327 ath9k_hw_mhz2ieee(ah, hchan->channel, hchan->channelFlags),
328 hchan->channel, hchan->channelFlags);
330 if (hchan->channel != sc->sc_ah->ah_curchan->channel ||
331 hchan->channelFlags != sc->sc_ah->ah_curchan->channelFlags ||
332 (sc->sc_flags & SC_OP_CHAINMASK_UPDATE) ||
333 (sc->sc_flags & SC_OP_FULL_RESET)) {
336 * This is only performed if the channel settings have
339 * To switch channels clear any pending DMA operations;
340 * wait long enough for the RX fifo to drain, reset the
341 * hardware at the new frequency, and then re-enable
342 * the relevant bits of the h/w.
344 ath9k_hw_set_interrupts(ah, 0); /* disable interrupts */
345 ath_draintxq(sc, false); /* clear pending tx frames */
346 stopped = ath_stoprecv(sc); /* turn off frame recv */
348 /* XXX: do not flush receive queue here. We don't want
349 * to flush data frames already in queue because of
350 * changing channel. */
352 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
355 spin_lock_bh(&sc->sc_resetlock);
356 if (!ath9k_hw_reset(ah, hchan,
357 sc->sc_ht_info.tx_chan_width,
360 sc->sc_ht_extprotspacing,
362 DPRINTF(sc, ATH_DBG_FATAL,
363 "%s: unable to reset channel %u (%uMhz) "
364 "flags 0x%x hal status %u\n", __func__,
365 ath9k_hw_mhz2ieee(ah, hchan->channel,
366 hchan->channelFlags),
367 hchan->channel, hchan->channelFlags, status);
368 spin_unlock_bh(&sc->sc_resetlock);
371 spin_unlock_bh(&sc->sc_resetlock);
373 sc->sc_flags &= ~SC_OP_CHAINMASK_UPDATE;
374 sc->sc_flags &= ~SC_OP_FULL_RESET;
376 /* Re-enable rx framework */
377 if (ath_startrecv(sc) != 0) {
378 DPRINTF(sc, ATH_DBG_FATAL,
379 "%s: unable to restart recv logic\n", __func__);
383 * Change channels and update the h/w rate map
384 * if we're switching; e.g. 11a to 11b/g.
386 ath_setcurmode(sc, ath_chan2mode(hchan));
388 ath_update_txpow(sc); /* update tx power state */
390 * Re-enable interrupts.
392 ath9k_hw_set_interrupts(ah, sc->sc_imask);
397 /**********************/
398 /* Chainmask Handling */
399 /**********************/
401 static void ath_chainmask_sel_timertimeout(unsigned long data)
403 struct ath_chainmask_sel *cm = (struct ath_chainmask_sel *)data;
404 cm->switch_allowed = 1;
407 /* Start chainmask select timer */
408 static void ath_chainmask_sel_timerstart(struct ath_chainmask_sel *cm)
410 cm->switch_allowed = 0;
411 mod_timer(&cm->timer, ath_chainmask_sel_period);
414 /* Stop chainmask select timer */
415 static void ath_chainmask_sel_timerstop(struct ath_chainmask_sel *cm)
417 cm->switch_allowed = 0;
418 del_timer_sync(&cm->timer);
421 static void ath_chainmask_sel_init(struct ath_softc *sc, struct ath_node *an)
423 struct ath_chainmask_sel *cm = &an->an_chainmask_sel;
425 memzero(cm, sizeof(struct ath_chainmask_sel));
427 cm->cur_tx_mask = sc->sc_tx_chainmask;
428 cm->cur_rx_mask = sc->sc_rx_chainmask;
429 cm->tx_avgrssi = ATH_RSSI_DUMMY_MARKER;
430 setup_timer(&cm->timer,
431 ath_chainmask_sel_timertimeout, (unsigned long) cm);
434 int ath_chainmask_sel_logic(struct ath_softc *sc, struct ath_node *an)
436 struct ath_chainmask_sel *cm = &an->an_chainmask_sel;
439 * Disable auto-swtiching in one of the following if conditions.
440 * sc_chainmask_auto_sel is used for internal global auto-switching
441 * enabled/disabled setting
443 if (sc->sc_ah->ah_caps.tx_chainmask != ATH_CHAINMASK_SEL_3X3) {
444 cm->cur_tx_mask = sc->sc_tx_chainmask;
445 return cm->cur_tx_mask;
448 if (cm->tx_avgrssi == ATH_RSSI_DUMMY_MARKER)
449 return cm->cur_tx_mask;
451 if (cm->switch_allowed) {
452 /* Switch down from tx 3 to tx 2. */
453 if (cm->cur_tx_mask == ATH_CHAINMASK_SEL_3X3 &&
454 ATH_RSSI_OUT(cm->tx_avgrssi) >=
455 ath_chainmask_sel_down_rssi_thres) {
456 cm->cur_tx_mask = sc->sc_tx_chainmask;
458 /* Don't let another switch happen until
459 * this timer expires */
460 ath_chainmask_sel_timerstart(cm);
462 /* Switch up from tx 2 to 3. */
463 else if (cm->cur_tx_mask == sc->sc_tx_chainmask &&
464 ATH_RSSI_OUT(cm->tx_avgrssi) <=
465 ath_chainmask_sel_up_rssi_thres) {
466 cm->cur_tx_mask = ATH_CHAINMASK_SEL_3X3;
468 /* Don't let another switch happen
469 * until this timer expires */
470 ath_chainmask_sel_timerstart(cm);
474 return cm->cur_tx_mask;
478 * Update tx/rx chainmask. For legacy association,
479 * hard code chainmask to 1x1, for 11n association, use
480 * the chainmask configuration.
483 void ath_update_chainmask(struct ath_softc *sc, int is_ht)
485 sc->sc_flags |= SC_OP_CHAINMASK_UPDATE;
487 sc->sc_tx_chainmask = sc->sc_ah->ah_caps.tx_chainmask;
488 sc->sc_rx_chainmask = sc->sc_ah->ah_caps.rx_chainmask;
490 sc->sc_tx_chainmask = 1;
491 sc->sc_rx_chainmask = 1;
494 DPRINTF(sc, ATH_DBG_CONFIG, "%s: tx chmask: %d, rx chmask: %d\n",
495 __func__, sc->sc_tx_chainmask, sc->sc_rx_chainmask);
505 * This routine brings the VAP out of the down state into a "listen" state
506 * where it waits for association requests. This is used in AP and AdHoc
510 int ath_vap_listen(struct ath_softc *sc, int if_id)
512 struct ath_hal *ah = sc->sc_ah;
515 DECLARE_MAC_BUF(mac);
517 avp = sc->sc_vaps[if_id];
519 DPRINTF(sc, ATH_DBG_FATAL, "%s: invalid interface id %u\n",
524 #ifdef CONFIG_SLOW_ANT_DIV
525 ath_slow_ant_div_stop(&sc->sc_antdiv);
528 /* update ratectrl about the new state */
529 ath_rate_newstate(sc, avp);
531 rfilt = ath_calcrxfilter(sc);
532 ath9k_hw_setrxfilter(ah, rfilt);
534 if (sc->sc_ah->ah_opmode == ATH9K_M_STA ||
535 sc->sc_ah->ah_opmode == ATH9K_M_IBSS) {
536 memcpy(sc->sc_curbssid, ath_bcast_mac, ETH_ALEN);
537 ath9k_hw_write_associd(ah, sc->sc_curbssid, sc->sc_curaid);
541 DPRINTF(sc, ATH_DBG_CONFIG,
542 "%s: RX filter 0x%x bssid %s aid 0x%x\n",
543 __func__, rfilt, print_mac(mac,
544 sc->sc_curbssid), sc->sc_curaid);
548 * Disable BMISS interrupt when we're not associated
550 if (sc->sc_ah->ah_opmode == ATH9K_M_HOSTAP) {
551 ath9k_hw_set_interrupts(ah, sc->sc_imask & ~ATH9K_INT_BMISS);
552 sc->sc_imask &= ~ATH9K_INT_BMISS;
554 ath9k_hw_set_interrupts(
556 sc->sc_imask & ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS));
557 sc->sc_imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
559 /* need to reconfigure the beacons when it moves to RUN */
560 sc->sc_flags &= ~SC_OP_BEACONS;
565 int ath_vap_attach(struct ath_softc *sc,
567 struct ieee80211_vif *if_data,
568 enum ath9k_opmode opmode)
572 if (if_id >= ATH_BCBUF || sc->sc_vaps[if_id] != NULL) {
573 DPRINTF(sc, ATH_DBG_FATAL,
574 "%s: Invalid interface id = %u\n", __func__, if_id);
581 case ATH9K_M_MONITOR:
584 /* XXX not right, beacon buffer is allocated on RUN trans */
585 if (list_empty(&sc->sc_bbuf))
593 avp = kmalloc(sizeof(struct ath_vap), GFP_KERNEL);
597 memzero(avp, sizeof(struct ath_vap));
598 avp->av_if_data = if_data;
599 /* Set the VAP opmode */
600 avp->av_opmode = opmode;
602 INIT_LIST_HEAD(&avp->av_mcastq.axq_q);
603 INIT_LIST_HEAD(&avp->av_mcastq.axq_acq);
604 spin_lock_init(&avp->av_mcastq.axq_lock);
606 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
608 sc->sc_vaps[if_id] = avp;
610 /* Set the device opmode */
611 sc->sc_ah->ah_opmode = opmode;
613 /* default VAP configuration */
614 avp->av_config.av_fixed_rateset = IEEE80211_FIXED_RATE_NONE;
615 avp->av_config.av_fixed_retryset = 0x03030303;
620 int ath_vap_detach(struct ath_softc *sc, int if_id)
622 struct ath_hal *ah = sc->sc_ah;
625 avp = sc->sc_vaps[if_id];
627 DPRINTF(sc, ATH_DBG_FATAL, "%s: invalid interface id %u\n",
633 * Quiesce the hardware while we remove the vap. In
634 * particular we need to reclaim all references to the
635 * vap state by any frames pending on the tx queues.
637 * XXX can we do this w/o affecting other vap's?
639 ath9k_hw_set_interrupts(ah, 0); /* disable interrupts */
640 ath_draintxq(sc, false); /* stop xmit side */
641 ath_stoprecv(sc); /* stop recv side */
642 ath_flushrecv(sc); /* flush recv queue */
644 /* Reclaim any pending mcast bufs on the vap. */
645 ath_tx_draintxq(sc, &avp->av_mcastq, false);
648 sc->sc_vaps[if_id] = NULL;
654 int ath_vap_config(struct ath_softc *sc,
655 int if_id, struct ath_vap_config *if_config)
659 if (if_id >= ATH_BCBUF) {
660 DPRINTF(sc, ATH_DBG_FATAL,
661 "%s: Invalid interface id = %u\n", __func__, if_id);
665 avp = sc->sc_vaps[if_id];
669 memcpy(&avp->av_config, if_config, sizeof(avp->av_config));
678 int ath_open(struct ath_softc *sc, struct ath9k_channel *initial_chan)
680 struct ath_hal *ah = sc->sc_ah;
684 DPRINTF(sc, ATH_DBG_CONFIG, "%s: mode %d\n",
685 __func__, sc->sc_ah->ah_opmode);
688 * Stop anything previously setup. This is safe
689 * whether this is the first time through or not.
693 /* Initialize chanmask selection */
694 sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask;
695 sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask;
697 /* Reset SERDES registers */
698 ath9k_hw_configpcipowersave(ah, 0);
701 * The basic interface to setting the hardware in a good
702 * state is ``reset''. On return the hardware is known to
703 * be powered up and with interrupts disabled. This must
704 * be followed by initialization of the appropriate bits
705 * and then setup of the interrupt mask.
708 spin_lock_bh(&sc->sc_resetlock);
709 if (!ath9k_hw_reset(ah, initial_chan,
710 sc->sc_ht_info.tx_chan_width,
711 sc->sc_tx_chainmask, sc->sc_rx_chainmask,
712 sc->sc_ht_extprotspacing, false, &status)) {
713 DPRINTF(sc, ATH_DBG_FATAL,
714 "%s: unable to reset hardware; hal status %u "
715 "(freq %u flags 0x%x)\n", __func__, status,
716 initial_chan->channel, initial_chan->channelFlags);
718 spin_unlock_bh(&sc->sc_resetlock);
721 spin_unlock_bh(&sc->sc_resetlock);
723 * This is needed only to setup initial state
724 * but it's best done after a reset.
726 ath_update_txpow(sc);
729 * Setup the hardware after reset:
730 * The receive engine is set going.
731 * Frame transmit is handled entirely
732 * in the frame output path; there's nothing to do
733 * here except setup the interrupt mask.
735 if (ath_startrecv(sc) != 0) {
736 DPRINTF(sc, ATH_DBG_FATAL,
737 "%s: unable to start recv logic\n", __func__);
741 /* Setup our intr mask. */
742 sc->sc_imask = ATH9K_INT_RX | ATH9K_INT_TX
743 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
744 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
746 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_GTT)
747 sc->sc_imask |= ATH9K_INT_GTT;
749 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT)
750 sc->sc_imask |= ATH9K_INT_CST;
753 * Enable MIB interrupts when there are hardware phy counters.
754 * Note we only do this (at the moment) for station mode.
756 if (ath9k_hw_phycounters(ah) &&
757 ((sc->sc_ah->ah_opmode == ATH9K_M_STA) ||
758 (sc->sc_ah->ah_opmode == ATH9K_M_IBSS)))
759 sc->sc_imask |= ATH9K_INT_MIB;
761 * Some hardware processes the TIM IE and fires an
762 * interrupt when the TIM bit is set. For hardware
763 * that does, if not overridden by configuration,
764 * enable the TIM interrupt when operating as station.
766 if ((ah->ah_caps.hw_caps & ATH9K_HW_CAP_ENHANCEDPM) &&
767 (sc->sc_ah->ah_opmode == ATH9K_M_STA) &&
768 !sc->sc_config.swBeaconProcess)
769 sc->sc_imask |= ATH9K_INT_TIM;
771 * Don't enable interrupts here as we've not yet built our
772 * vap and node data structures, which will be needed as soon
773 * as we start receiving.
775 ath_setcurmode(sc, ath_chan2mode(initial_chan));
777 /* XXX: we must make sure h/w is ready and clear invalid flag
778 * before turning on interrupt. */
779 sc->sc_flags &= ~SC_OP_INVALID;
784 int ath_reset(struct ath_softc *sc, bool retry_tx)
786 struct ath_hal *ah = sc->sc_ah;
790 ath9k_hw_set_interrupts(ah, 0); /* disable interrupts */
791 ath_draintxq(sc, retry_tx); /* stop xmit */
792 ath_stoprecv(sc); /* stop recv */
793 ath_flushrecv(sc); /* flush recv queue */
796 spin_lock_bh(&sc->sc_resetlock);
797 if (!ath9k_hw_reset(ah, sc->sc_ah->ah_curchan,
798 sc->sc_ht_info.tx_chan_width,
799 sc->sc_tx_chainmask, sc->sc_rx_chainmask,
800 sc->sc_ht_extprotspacing, false, &status)) {
801 DPRINTF(sc, ATH_DBG_FATAL,
802 "%s: unable to reset hardware; hal status %u\n",
806 spin_unlock_bh(&sc->sc_resetlock);
808 if (ath_startrecv(sc) != 0) /* restart recv */
809 DPRINTF(sc, ATH_DBG_FATAL,
810 "%s: unable to start recv logic\n", __func__);
813 * We may be doing a reset in response to a request
814 * that changes the channel so update any state that
815 * might change as a result.
817 ath_setcurmode(sc, ath_chan2mode(sc->sc_ah->ah_curchan));
819 ath_update_txpow(sc);
821 if (sc->sc_flags & SC_OP_BEACONS)
822 ath_beacon_config(sc, ATH_IF_ID_ANY); /* restart beacons */
824 ath9k_hw_set_interrupts(ah, sc->sc_imask);
826 /* Restart the txq */
829 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
830 if (ATH_TXQ_SETUP(sc, i)) {
831 spin_lock_bh(&sc->sc_txq[i].axq_lock);
832 ath_txq_schedule(sc, &sc->sc_txq[i]);
833 spin_unlock_bh(&sc->sc_txq[i].axq_lock);
841 int ath_suspend(struct ath_softc *sc)
843 struct ath_hal *ah = sc->sc_ah;
845 /* No I/O if device has been surprise removed */
846 if (sc->sc_flags & SC_OP_INVALID)
849 /* Shut off the interrupt before setting sc->sc_invalid to '1' */
850 ath9k_hw_set_interrupts(ah, 0);
852 /* XXX: we must make sure h/w will not generate any interrupt
853 * before setting the invalid flag. */
854 sc->sc_flags |= SC_OP_INVALID;
856 /* disable HAL and put h/w to sleep */
857 ath9k_hw_disable(sc->sc_ah);
859 ath9k_hw_configpcipowersave(sc->sc_ah, 1);
864 /* Interrupt handler. Most of the actual processing is deferred.
865 * It's the caller's responsibility to ensure the chip is awake. */
867 irqreturn_t ath_isr(int irq, void *dev)
869 struct ath_softc *sc = dev;
870 struct ath_hal *ah = sc->sc_ah;
871 enum ath9k_int status;
875 if (sc->sc_flags & SC_OP_INVALID) {
877 * The hardware is not ready/present, don't
878 * touch anything. Note this can happen early
879 * on if the IRQ is shared.
883 if (!ath9k_hw_intrpend(ah)) { /* shared irq, not for us */
888 * Figure out the reason(s) for the interrupt. Note
889 * that the hal returns a pseudo-ISR that may include
890 * bits we haven't explicitly enabled so we mask the
891 * value to insure we only process bits we requested.
893 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
895 status &= sc->sc_imask; /* discard unasked-for bits */
898 * If there are no status bits set, then this interrupt was not
899 * for me (should have been caught above).
905 sc->sc_intrstatus = status;
907 if (status & ATH9K_INT_FATAL) {
908 /* need a chip reset */
910 } else if (status & ATH9K_INT_RXORN) {
911 /* need a chip reset */
914 if (status & ATH9K_INT_SWBA) {
915 /* schedule a tasklet for beacon handling */
916 tasklet_schedule(&sc->bcon_tasklet);
918 if (status & ATH9K_INT_RXEOL) {
920 * NB: the hardware should re-read the link when
921 * RXE bit is written, but it doesn't work
922 * at least on older hardware revs.
927 if (status & ATH9K_INT_TXURN)
928 /* bump tx trigger level */
929 ath9k_hw_updatetxtriglevel(ah, true);
930 /* XXX: optimize this */
931 if (status & ATH9K_INT_RX)
933 if (status & ATH9K_INT_TX)
935 if (status & ATH9K_INT_BMISS)
937 /* carrier sense timeout */
938 if (status & ATH9K_INT_CST)
940 if (status & ATH9K_INT_MIB) {
942 * Disable interrupts until we service the MIB
943 * interrupt; otherwise it will continue to
946 ath9k_hw_set_interrupts(ah, 0);
948 * Let the hal handle the event. We assume
949 * it will clear whatever condition caused
952 ath9k_hw_procmibevent(ah, &sc->sc_halstats);
953 ath9k_hw_set_interrupts(ah, sc->sc_imask);
955 if (status & ATH9K_INT_TIM_TIMER) {
956 if (!(ah->ah_caps.hw_caps &
957 ATH9K_HW_CAP_AUTOSLEEP)) {
958 /* Clear RxAbort bit so that we can
960 ath9k_hw_setrxabort(ah, 0);
968 /* turn off every interrupt except SWBA */
969 ath9k_hw_set_interrupts(ah, (sc->sc_imask & ATH9K_INT_SWBA));
970 tasklet_schedule(&sc->intr_tq);
976 /* Deferred interrupt processing */
978 static void ath9k_tasklet(unsigned long data)
980 struct ath_softc *sc = (struct ath_softc *)data;
981 u32 status = sc->sc_intrstatus;
983 if (status & ATH9K_INT_FATAL) {
984 /* need a chip reset */
985 ath_reset(sc, false);
990 (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
991 /* XXX: fill me in */
993 if (status & ATH9K_INT_RXORN) {
995 if (status & ATH9K_INT_RXEOL) {
998 spin_lock_bh(&sc->sc_rxflushlock);
999 ath_rx_tasklet(sc, 0);
1000 spin_unlock_bh(&sc->sc_rxflushlock);
1002 /* XXX: optimize this */
1003 if (status & ATH9K_INT_TX)
1005 /* XXX: fill me in */
1007 if (status & ATH9K_INT_BMISS) {
1009 if (status & (ATH9K_INT_TIM | ATH9K_INT_DTIMSYNC)) {
1010 if (status & ATH9K_INT_TIM) {
1012 if (status & ATH9K_INT_DTIMSYNC) {
1018 /* re-enable hardware interrupt */
1019 ath9k_hw_set_interrupts(sc->sc_ah, sc->sc_imask);
1022 int ath_init(u16 devid, struct ath_softc *sc)
1024 struct ath_hal *ah = NULL;
1030 /* XXX: hardware will not be ready until ath_open() being called */
1031 sc->sc_flags |= SC_OP_INVALID;
1033 sc->sc_debug = DBG_DEFAULT;
1034 DPRINTF(sc, ATH_DBG_CONFIG, "%s: devid 0x%x\n", __func__, devid);
1036 /* Initialize tasklet */
1037 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1038 tasklet_init(&sc->bcon_tasklet, ath9k_beacon_tasklet,
1042 * Cache line size is used to size and align various
1043 * structures used to communicate with the hardware.
1045 bus_read_cachesize(sc, &csz);
1046 /* XXX assert csz is non-zero */
1047 sc->sc_cachelsz = csz << 2; /* convert to bytes */
1049 spin_lock_init(&sc->sc_resetlock);
1051 ah = ath9k_hw_attach(devid, sc, sc->mem, &status);
1053 DPRINTF(sc, ATH_DBG_FATAL,
1054 "%s: unable to attach hardware; HAL status %u\n",
1061 /* Get the hardware key cache size. */
1062 sc->sc_keymax = ah->ah_caps.keycache_size;
1063 if (sc->sc_keymax > ATH_KEYMAX) {
1064 DPRINTF(sc, ATH_DBG_KEYCACHE,
1065 "%s: Warning, using only %u entries in %u key cache\n",
1066 __func__, ATH_KEYMAX, sc->sc_keymax);
1067 sc->sc_keymax = ATH_KEYMAX;
1071 * Reset the key cache since some parts do not
1072 * reset the contents on initial power up.
1074 for (i = 0; i < sc->sc_keymax; i++)
1075 ath9k_hw_keyreset(ah, (u16) i);
1077 * Mark key cache slots associated with global keys
1078 * as in use. If we knew TKIP was not to be used we
1079 * could leave the +32, +64, and +32+64 slots free.
1080 * XXX only for splitmic.
1082 for (i = 0; i < IEEE80211_WEP_NKID; i++) {
1083 set_bit(i, sc->sc_keymap);
1084 set_bit(i + 32, sc->sc_keymap);
1085 set_bit(i + 64, sc->sc_keymap);
1086 set_bit(i + 32 + 64, sc->sc_keymap);
1089 * Collect the channel list using the default country
1090 * code and including outdoor channels. The 802.11 layer
1091 * is resposible for filtering this list based on settings
1092 * like the phy mode.
1094 rd = ah->ah_currentRD;
1096 error = ath_setup_channels(sc);
1100 /* default to STA mode */
1101 sc->sc_ah->ah_opmode = ATH9K_M_MONITOR;
1103 /* Setup rate tables */
1105 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1106 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1108 /* NB: setup here so ath_rate_update is happy */
1109 ath_setcurmode(sc, ATH9K_MODE_11A);
1112 * Allocate hardware transmit queues: one queue for
1113 * beacon frames and one data queue for each QoS
1114 * priority. Note that the hal handles reseting
1115 * these queues at the needed time.
1117 sc->sc_bhalq = ath_beaconq_setup(ah);
1118 if (sc->sc_bhalq == -1) {
1119 DPRINTF(sc, ATH_DBG_FATAL,
1120 "%s: unable to setup a beacon xmit queue\n", __func__);
1124 sc->sc_cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1125 if (sc->sc_cabq == NULL) {
1126 DPRINTF(sc, ATH_DBG_FATAL,
1127 "%s: unable to setup CAB xmit queue\n", __func__);
1132 sc->sc_config.cabqReadytime = ATH_CABQ_READY_TIME;
1133 ath_cabq_update(sc);
1135 for (i = 0; i < ARRAY_SIZE(sc->sc_haltype2q); i++)
1136 sc->sc_haltype2q[i] = -1;
1138 /* Setup data queues */
1139 /* NB: ensure BK queue is the lowest priority h/w queue */
1140 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1141 DPRINTF(sc, ATH_DBG_FATAL,
1142 "%s: unable to setup xmit queue for BK traffic\n",
1148 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1149 DPRINTF(sc, ATH_DBG_FATAL,
1150 "%s: unable to setup xmit queue for BE traffic\n",
1155 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1156 DPRINTF(sc, ATH_DBG_FATAL,
1157 "%s: unable to setup xmit queue for VI traffic\n",
1162 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1163 DPRINTF(sc, ATH_DBG_FATAL,
1164 "%s: unable to setup xmit queue for VO traffic\n",
1170 sc->sc_rc = ath_rate_attach(ah);
1171 if (sc->sc_rc == NULL) {
1176 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1177 ATH9K_CIPHER_TKIP, NULL)) {
1179 * Whether we should enable h/w TKIP MIC.
1180 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1181 * report WMM capable, so it's always safe to turn on
1182 * TKIP MIC in this case.
1184 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1189 * Check whether the separate key cache entries
1190 * are required to handle both tx+rx MIC keys.
1191 * With split mic keys the number of stations is limited
1192 * to 27 otherwise 59.
1194 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1195 ATH9K_CIPHER_TKIP, NULL)
1196 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1197 ATH9K_CIPHER_MIC, NULL)
1198 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1200 sc->sc_splitmic = 1;
1202 /* turn on mcast key search if possible */
1203 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1204 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1207 sc->sc_config.txpowlimit = ATH_TXPOWER_MAX;
1208 sc->sc_config.txpowlimit_override = 0;
1210 /* 11n Capabilities */
1211 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_HT) {
1212 sc->sc_flags |= SC_OP_TXAGGR;
1213 sc->sc_flags |= SC_OP_RXAGGR;
1216 sc->sc_tx_chainmask = ah->ah_caps.tx_chainmask;
1217 sc->sc_rx_chainmask = ah->ah_caps.rx_chainmask;
1219 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1220 sc->sc_defant = ath9k_hw_getdefantenna(ah);
1222 ath9k_hw_getmac(ah, sc->sc_myaddr);
1223 if (ah->ah_caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) {
1224 ath9k_hw_getbssidmask(ah, sc->sc_bssidmask);
1225 ATH_SET_VAP_BSSID_MASK(sc->sc_bssidmask);
1226 ath9k_hw_setbssidmask(ah, sc->sc_bssidmask);
1228 sc->sc_slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
1230 /* initialize beacon slots */
1231 for (i = 0; i < ARRAY_SIZE(sc->sc_bslot); i++)
1232 sc->sc_bslot[i] = ATH_IF_ID_ANY;
1234 /* save MISC configurations */
1235 sc->sc_config.swBeaconProcess = 1;
1237 #ifdef CONFIG_SLOW_ANT_DIV
1238 /* range is 40 - 255, we use something in the middle */
1239 ath_slow_ant_div_init(&sc->sc_antdiv, sc, 0x127);
1244 /* cleanup tx queues */
1245 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1246 if (ATH_TXQ_SETUP(sc, i))
1247 ath_tx_cleanupq(sc, &sc->sc_txq[i]);
1250 ath9k_hw_detach(ah);
1254 void ath_deinit(struct ath_softc *sc)
1256 struct ath_hal *ah = sc->sc_ah;
1259 DPRINTF(sc, ATH_DBG_CONFIG, "%s\n", __func__);
1262 if (!(sc->sc_flags & SC_OP_INVALID))
1263 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
1264 ath_rate_detach(sc->sc_rc);
1265 /* cleanup tx queues */
1266 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1267 if (ATH_TXQ_SETUP(sc, i))
1268 ath_tx_cleanupq(sc, &sc->sc_txq[i]);
1269 ath9k_hw_detach(ah);
1272 /*******************/
1273 /* Node Management */
1274 /*******************/
1276 struct ath_node *ath_node_attach(struct ath_softc *sc, u8 *addr, int if_id)
1278 struct ath_vap *avp;
1279 struct ath_node *an;
1280 DECLARE_MAC_BUF(mac);
1282 avp = sc->sc_vaps[if_id];
1283 ASSERT(avp != NULL);
1285 /* mac80211 sta_notify callback is from an IRQ context, so no sleep */
1286 an = kmalloc(sizeof(struct ath_node), GFP_ATOMIC);
1289 memzero(an, sizeof(*an));
1292 memcpy(an->an_addr, addr, ETH_ALEN);
1293 atomic_set(&an->an_refcnt, 1);
1295 /* set up per-node tx/rx state */
1296 ath_tx_node_init(sc, an);
1297 ath_rx_node_init(sc, an);
1299 ath_chainmask_sel_init(sc, an);
1300 ath_chainmask_sel_timerstart(&an->an_chainmask_sel);
1301 list_add(&an->list, &sc->node_list);
1306 void ath_node_detach(struct ath_softc *sc, struct ath_node *an, bool bh_flag)
1308 unsigned long flags;
1310 DECLARE_MAC_BUF(mac);
1312 ath_chainmask_sel_timerstop(&an->an_chainmask_sel);
1313 an->an_flags |= ATH_NODE_CLEAN;
1314 ath_tx_node_cleanup(sc, an, bh_flag);
1315 ath_rx_node_cleanup(sc, an);
1317 ath_tx_node_free(sc, an);
1318 ath_rx_node_free(sc, an);
1320 spin_lock_irqsave(&sc->node_lock, flags);
1322 list_del(&an->list);
1324 spin_unlock_irqrestore(&sc->node_lock, flags);
1329 /* Finds a node and increases the refcnt if found */
1331 struct ath_node *ath_node_get(struct ath_softc *sc, u8 *addr)
1333 struct ath_node *an = NULL, *an_found = NULL;
1335 if (list_empty(&sc->node_list)) /* FIXME */
1337 list_for_each_entry(an, &sc->node_list, list) {
1338 if (!compare_ether_addr(an->an_addr, addr)) {
1339 atomic_inc(&an->an_refcnt);
1348 /* Decrements the refcnt and if it drops to zero, detach the node */
1350 void ath_node_put(struct ath_softc *sc, struct ath_node *an, bool bh_flag)
1352 if (atomic_dec_and_test(&an->an_refcnt))
1353 ath_node_detach(sc, an, bh_flag);
1356 /* Finds a node, doesn't increment refcnt. Caller must hold sc->node_lock */
1357 struct ath_node *ath_node_find(struct ath_softc *sc, u8 *addr)
1359 struct ath_node *an = NULL, *an_found = NULL;
1361 if (list_empty(&sc->node_list))
1364 list_for_each_entry(an, &sc->node_list, list)
1365 if (!compare_ether_addr(an->an_addr, addr)) {
1376 * Setup driver-specific state for a newly associated node. This routine
1377 * really only applies if compression or XR are enabled, there is no code
1378 * covering any other cases.
1381 void ath_newassoc(struct ath_softc *sc,
1382 struct ath_node *an, int isnew, int isuapsd)
1386 /* if station reassociates, tear down the aggregation state. */
1388 for (tidno = 0; tidno < WME_NUM_TID; tidno++) {
1389 if (sc->sc_flags & SC_OP_TXAGGR)
1390 ath_tx_aggr_teardown(sc, an, tidno);
1391 if (sc->sc_flags & SC_OP_RXAGGR)
1392 ath_rx_aggr_teardown(sc, an, tidno);
1402 void ath_key_reset(struct ath_softc *sc, u16 keyix, int freeslot)
1404 ath9k_hw_keyreset(sc->sc_ah, keyix);
1406 clear_bit(keyix, sc->sc_keymap);
1409 int ath_keyset(struct ath_softc *sc,
1411 struct ath9k_keyval *hk,
1412 const u8 mac[ETH_ALEN])
1416 status = ath9k_hw_set_keycache_entry(sc->sc_ah,
1417 keyix, hk, mac, false);
1419 return status != false;
1422 /***********************/
1423 /* TX Power/Regulatory */
1424 /***********************/
1427 * Set Transmit power in HAL
1429 * This routine makes the actual HAL calls to set the new transmit power
1433 void ath_update_txpow(struct ath_softc *sc)
1435 struct ath_hal *ah = sc->sc_ah;
1438 if (sc->sc_curtxpow != sc->sc_config.txpowlimit) {
1439 ath9k_hw_set_txpowerlimit(ah, sc->sc_config.txpowlimit);
1440 /* read back in case value is clamped */
1441 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
1442 sc->sc_curtxpow = txpow;
1446 /* Return the current country and domain information */
1447 void ath_get_currentCountry(struct ath_softc *sc,
1448 struct ath9k_country_entry *ctry)
1450 ath9k_regd_get_current_country(sc->sc_ah, ctry);
1452 /* If HAL not specific yet, since it is band dependent,
1453 * use the one we passed in. */
1454 if (ctry->countryCode == CTRY_DEFAULT) {
1457 } else if (ctry->iso[0] && ctry->iso[1]) {
1458 if (!ctry->iso[2]) {
1467 /**************************/
1468 /* Slow Antenna Diversity */
1469 /**************************/
1471 void ath_slow_ant_div_init(struct ath_antdiv *antdiv,
1472 struct ath_softc *sc,
1477 /* antdivf_rssitrig can range from 40 - 0xff */
1478 trig = (rssitrig > 0xff) ? 0xff : rssitrig;
1479 trig = (rssitrig < 40) ? 40 : rssitrig;
1481 antdiv->antdiv_sc = sc;
1482 antdiv->antdivf_rssitrig = trig;
1485 void ath_slow_ant_div_start(struct ath_antdiv *antdiv,
1489 antdiv->antdiv_num_antcfg =
1490 num_antcfg < ATH_ANT_DIV_MAX_CFG ?
1491 num_antcfg : ATH_ANT_DIV_MAX_CFG;
1492 antdiv->antdiv_state = ATH_ANT_DIV_IDLE;
1493 antdiv->antdiv_curcfg = 0;
1494 antdiv->antdiv_bestcfg = 0;
1495 antdiv->antdiv_laststatetsf = 0;
1497 memcpy(antdiv->antdiv_bssid, bssid, sizeof(antdiv->antdiv_bssid));
1499 antdiv->antdiv_start = 1;
1502 void ath_slow_ant_div_stop(struct ath_antdiv *antdiv)
1504 antdiv->antdiv_start = 0;
1507 static int32_t ath_find_max_val(int32_t *val,
1508 u8 num_val, u8 *max_index)
1510 u32 MaxVal = *val++;
1514 while (++cur_index < num_val) {
1515 if (*val > MaxVal) {
1517 *max_index = cur_index;
1526 void ath_slow_ant_div(struct ath_antdiv *antdiv,
1527 struct ieee80211_hdr *hdr,
1528 struct ath_rx_status *rx_stats)
1530 struct ath_softc *sc = antdiv->antdiv_sc;
1531 struct ath_hal *ah = sc->sc_ah;
1533 u8 bestcfg, curcfg = antdiv->antdiv_curcfg;
1534 __le16 fc = hdr->frame_control;
1536 if (antdiv->antdiv_start && ieee80211_is_beacon(fc)
1537 && !compare_ether_addr(hdr->addr3, antdiv->antdiv_bssid)) {
1538 antdiv->antdiv_lastbrssi[curcfg] = rx_stats->rs_rssi;
1539 antdiv->antdiv_lastbtsf[curcfg] = ath9k_hw_gettsf64(sc->sc_ah);
1540 curtsf = antdiv->antdiv_lastbtsf[curcfg];
1545 switch (antdiv->antdiv_state) {
1546 case ATH_ANT_DIV_IDLE:
1547 if ((antdiv->antdiv_lastbrssi[curcfg] <
1548 antdiv->antdivf_rssitrig)
1549 && ((curtsf - antdiv->antdiv_laststatetsf) >
1550 ATH_ANT_DIV_MIN_IDLE_US)) {
1553 if (curcfg == antdiv->antdiv_num_antcfg)
1556 if (!ath9k_hw_select_antconfig(ah, curcfg)) {
1557 antdiv->antdiv_bestcfg = antdiv->antdiv_curcfg;
1558 antdiv->antdiv_curcfg = curcfg;
1559 antdiv->antdiv_laststatetsf = curtsf;
1560 antdiv->antdiv_state = ATH_ANT_DIV_SCAN;
1565 case ATH_ANT_DIV_SCAN:
1566 if ((curtsf - antdiv->antdiv_laststatetsf) <
1567 ATH_ANT_DIV_MIN_SCAN_US)
1571 if (curcfg == antdiv->antdiv_num_antcfg)
1574 if (curcfg == antdiv->antdiv_bestcfg) {
1575 ath_find_max_val(antdiv->antdiv_lastbrssi,
1576 antdiv->antdiv_num_antcfg, &bestcfg);
1577 if (!ath9k_hw_select_antconfig(ah, bestcfg)) {
1578 antdiv->antdiv_bestcfg = bestcfg;
1579 antdiv->antdiv_curcfg = bestcfg;
1580 antdiv->antdiv_laststatetsf = curtsf;
1581 antdiv->antdiv_state = ATH_ANT_DIV_IDLE;
1584 if (!ath9k_hw_select_antconfig(ah, curcfg)) {
1585 antdiv->antdiv_curcfg = curcfg;
1586 antdiv->antdiv_laststatetsf = curtsf;
1587 antdiv->antdiv_state = ATH_ANT_DIV_SCAN;
1595 /***********************/
1596 /* Descriptor Handling */
1597 /***********************/
1600 * Set up DMA descriptors
1602 * This function will allocate both the DMA descriptor structure, and the
1603 * buffers it contains. These are used to contain the descriptors used
1607 int ath_descdma_setup(struct ath_softc *sc,
1608 struct ath_descdma *dd,
1609 struct list_head *head,
1614 #define DS2PHYS(_dd, _ds) \
1615 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
1616 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
1617 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
1619 struct ath_desc *ds;
1621 int i, bsize, error;
1623 DPRINTF(sc, ATH_DBG_CONFIG, "%s: %s DMA: %u buffers %u desc/buf\n",
1624 __func__, name, nbuf, ndesc);
1626 /* ath_desc must be a multiple of DWORDs */
1627 if ((sizeof(struct ath_desc) % 4) != 0) {
1628 DPRINTF(sc, ATH_DBG_FATAL, "%s: ath_desc not DWORD aligned\n",
1630 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1636 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
1639 * Need additional DMA memory because we can't use
1640 * descriptors that cross the 4K page boundary. Assume
1641 * one skipped descriptor per 4K page.
1643 if (!(sc->sc_ah->ah_caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1645 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
1648 while (ndesc_skipped) {
1649 dma_len = ndesc_skipped * sizeof(struct ath_desc);
1650 dd->dd_desc_len += dma_len;
1652 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
1656 /* allocate descriptors */
1657 dd->dd_desc = pci_alloc_consistent(sc->pdev,
1659 &dd->dd_desc_paddr);
1660 if (dd->dd_desc == NULL) {
1665 DPRINTF(sc, ATH_DBG_CONFIG, "%s: %s DMA map: %p (%u) -> %llx (%u)\n",
1666 __func__, dd->dd_name, ds, (u32) dd->dd_desc_len,
1667 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1669 /* allocate buffers */
1670 bsize = sizeof(struct ath_buf) * nbuf;
1671 bf = kmalloc(bsize, GFP_KERNEL);
1679 INIT_LIST_HEAD(head);
1680 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
1682 bf->bf_daddr = DS2PHYS(dd, ds);
1684 if (!(sc->sc_ah->ah_caps.hw_caps &
1685 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
1687 * Skip descriptor addresses which can cause 4KB
1688 * boundary crossing (addr + length) with a 32 dword
1691 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
1692 ASSERT((caddr_t) bf->bf_desc <
1693 ((caddr_t) dd->dd_desc +
1698 bf->bf_daddr = DS2PHYS(dd, ds);
1701 list_add_tail(&bf->list, head);
1705 pci_free_consistent(sc->pdev,
1706 dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
1708 memzero(dd, sizeof(*dd));
1710 #undef ATH_DESC_4KB_BOUND_CHECK
1711 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
1716 * Cleanup DMA descriptors
1718 * This function will free the DMA block that was allocated for the descriptor
1719 * pool. Since this was allocated as one "chunk", it is freed in the same
1723 void ath_descdma_cleanup(struct ath_softc *sc,
1724 struct ath_descdma *dd,
1725 struct list_head *head)
1727 /* Free memory associated with descriptors */
1728 pci_free_consistent(sc->pdev,
1729 dd->dd_desc_len, dd->dd_desc, dd->dd_desc_paddr);
1731 INIT_LIST_HEAD(head);
1732 kfree(dd->dd_bufptr);
1733 memzero(dd, sizeof(*dd));
1740 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
1746 qnum = sc->sc_haltype2q[ATH9K_WME_AC_VO];
1749 qnum = sc->sc_haltype2q[ATH9K_WME_AC_VI];
1752 qnum = sc->sc_haltype2q[ATH9K_WME_AC_BE];
1755 qnum = sc->sc_haltype2q[ATH9K_WME_AC_BK];
1758 qnum = sc->sc_haltype2q[ATH9K_WME_AC_BE];
1765 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
1770 case ATH9K_WME_AC_VO:
1773 case ATH9K_WME_AC_VI:
1776 case ATH9K_WME_AC_BE:
1779 case ATH9K_WME_AC_BK:
1792 * Expand time stamp to TSF
1794 * Extend 15-bit time stamp from rx descriptor to
1795 * a full 64-bit TSF using the current h/w TSF.
1798 u64 ath_extend_tsf(struct ath_softc *sc, u32 rstamp)
1802 tsf = ath9k_hw_gettsf64(sc->sc_ah);
1803 if ((tsf & 0x7fff) < rstamp)
1805 return (tsf & ~0x7fff) | rstamp;
1809 * Set Default Antenna
1811 * Call into the HAL to set the default antenna to use. Not really valid for
1815 void ath_setdefantenna(void *context, u32 antenna)
1817 struct ath_softc *sc = (struct ath_softc *)context;
1818 struct ath_hal *ah = sc->sc_ah;
1820 /* XXX block beacon interrupts */
1821 ath9k_hw_setantenna(ah, antenna);
1822 sc->sc_defant = antenna;
1823 sc->sc_rxotherant = 0;
1829 * This will wake up the chip if required, and set the slot time for the
1830 * frame (maximum transmit time). Slot time is assumed to be already set
1831 * in the ATH object member sc_slottime
1834 void ath_setslottime(struct ath_softc *sc)
1836 ath9k_hw_setslottime(sc->sc_ah, sc->sc_slottime);
1837 sc->sc_updateslot = OK;