2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/hardirq.h>
48 #include <linux/netdevice.h>
49 #include <linux/cache.h>
50 #include <linux/pci.h>
51 #include <linux/ethtool.h>
52 #include <linux/uaccess.h>
54 #include <net/ieee80211_radiotap.h>
56 #include <asm/unaligned.h>
62 static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
63 static int modparam_nohwcrypt;
64 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
65 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
73 MODULE_AUTHOR("Jiri Slaby");
74 MODULE_AUTHOR("Nick Kossifidis");
75 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
76 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
77 MODULE_LICENSE("Dual BSD/GPL");
78 MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
82 static struct pci_device_id ath5k_pci_id_table[] __devinitdata = {
83 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
84 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
85 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
86 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
87 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
88 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
89 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
90 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
91 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
92 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
93 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
94 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
95 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
96 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
98 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
99 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* PCI-E cards */
100 { PCI_VDEVICE(ATHEROS, 0x001d), .driver_data = AR5K_AR5212 }, /* 2417 Nala */
103 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
106 static struct ath5k_srev_name srev_names[] = {
107 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
108 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
109 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
110 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
111 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
112 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
113 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
114 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
115 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
116 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
117 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
118 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
119 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
120 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
121 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
122 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
123 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
124 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
125 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
126 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
127 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
128 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
129 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
130 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
131 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
132 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
133 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
134 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
135 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
136 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
137 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
138 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
139 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
140 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
141 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
142 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
145 static struct ieee80211_rate ath5k_rates[] = {
147 .hw_value = ATH5K_RATE_CODE_1M, },
149 .hw_value = ATH5K_RATE_CODE_2M,
150 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
151 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
153 .hw_value = ATH5K_RATE_CODE_5_5M,
154 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
155 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
157 .hw_value = ATH5K_RATE_CODE_11M,
158 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
159 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
161 .hw_value = ATH5K_RATE_CODE_6M,
164 .hw_value = ATH5K_RATE_CODE_9M,
167 .hw_value = ATH5K_RATE_CODE_12M,
170 .hw_value = ATH5K_RATE_CODE_18M,
173 .hw_value = ATH5K_RATE_CODE_24M,
176 .hw_value = ATH5K_RATE_CODE_36M,
179 .hw_value = ATH5K_RATE_CODE_48M,
182 .hw_value = ATH5K_RATE_CODE_54M,
188 * Prototypes - PCI stack related functions
190 static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
191 const struct pci_device_id *id);
192 static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
194 static int ath5k_pci_suspend(struct pci_dev *pdev,
196 static int ath5k_pci_resume(struct pci_dev *pdev);
198 #define ath5k_pci_suspend NULL
199 #define ath5k_pci_resume NULL
200 #endif /* CONFIG_PM */
202 static struct pci_driver ath5k_pci_driver = {
203 .name = KBUILD_MODNAME,
204 .id_table = ath5k_pci_id_table,
205 .probe = ath5k_pci_probe,
206 .remove = __devexit_p(ath5k_pci_remove),
207 .suspend = ath5k_pci_suspend,
208 .resume = ath5k_pci_resume,
214 * Prototypes - MAC 802.11 stack related functions
216 static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
217 static int ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel);
218 static int ath5k_reset_wake(struct ath5k_softc *sc);
219 static int ath5k_start(struct ieee80211_hw *hw);
220 static void ath5k_stop(struct ieee80211_hw *hw);
221 static int ath5k_add_interface(struct ieee80211_hw *hw,
222 struct ieee80211_if_init_conf *conf);
223 static void ath5k_remove_interface(struct ieee80211_hw *hw,
224 struct ieee80211_if_init_conf *conf);
225 static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
226 static int ath5k_config_interface(struct ieee80211_hw *hw,
227 struct ieee80211_vif *vif,
228 struct ieee80211_if_conf *conf);
229 static void ath5k_configure_filter(struct ieee80211_hw *hw,
230 unsigned int changed_flags,
231 unsigned int *new_flags,
232 int mc_count, struct dev_mc_list *mclist);
233 static int ath5k_set_key(struct ieee80211_hw *hw,
234 enum set_key_cmd cmd,
235 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
236 struct ieee80211_key_conf *key);
237 static int ath5k_get_stats(struct ieee80211_hw *hw,
238 struct ieee80211_low_level_stats *stats);
239 static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
240 struct ieee80211_tx_queue_stats *stats);
241 static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
242 static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf);
243 static void ath5k_reset_tsf(struct ieee80211_hw *hw);
244 static int ath5k_beacon_update(struct ath5k_softc *sc,
245 struct sk_buff *skb);
246 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
247 struct ieee80211_vif *vif,
248 struct ieee80211_bss_conf *bss_conf,
251 static struct ieee80211_ops ath5k_hw_ops = {
253 .start = ath5k_start,
255 .add_interface = ath5k_add_interface,
256 .remove_interface = ath5k_remove_interface,
257 .config = ath5k_config,
258 .config_interface = ath5k_config_interface,
259 .configure_filter = ath5k_configure_filter,
260 .set_key = ath5k_set_key,
261 .get_stats = ath5k_get_stats,
263 .get_tx_stats = ath5k_get_tx_stats,
264 .get_tsf = ath5k_get_tsf,
265 .set_tsf = ath5k_set_tsf,
266 .reset_tsf = ath5k_reset_tsf,
267 .bss_info_changed = ath5k_bss_info_changed,
271 * Prototypes - Internal functions
274 static int ath5k_attach(struct pci_dev *pdev,
275 struct ieee80211_hw *hw);
276 static void ath5k_detach(struct pci_dev *pdev,
277 struct ieee80211_hw *hw);
278 /* Channel/mode setup */
279 static inline short ath5k_ieee2mhz(short chan);
280 static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
281 struct ieee80211_channel *channels,
284 static int ath5k_setup_bands(struct ieee80211_hw *hw);
285 static int ath5k_chan_set(struct ath5k_softc *sc,
286 struct ieee80211_channel *chan);
287 static void ath5k_setcurmode(struct ath5k_softc *sc,
289 static void ath5k_mode_setup(struct ath5k_softc *sc);
291 /* Descriptor setup */
292 static int ath5k_desc_alloc(struct ath5k_softc *sc,
293 struct pci_dev *pdev);
294 static void ath5k_desc_free(struct ath5k_softc *sc,
295 struct pci_dev *pdev);
297 static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
298 struct ath5k_buf *bf);
299 static int ath5k_txbuf_setup(struct ath5k_softc *sc,
300 struct ath5k_buf *bf);
301 static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
302 struct ath5k_buf *bf)
307 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
309 dev_kfree_skb_any(bf->skb);
314 static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
315 int qtype, int subtype);
316 static int ath5k_beaconq_setup(struct ath5k_hw *ah);
317 static int ath5k_beaconq_config(struct ath5k_softc *sc);
318 static void ath5k_txq_drainq(struct ath5k_softc *sc,
319 struct ath5k_txq *txq);
320 static void ath5k_txq_cleanup(struct ath5k_softc *sc);
321 static void ath5k_txq_release(struct ath5k_softc *sc);
323 static int ath5k_rx_start(struct ath5k_softc *sc);
324 static void ath5k_rx_stop(struct ath5k_softc *sc);
325 static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
326 struct ath5k_desc *ds,
328 struct ath5k_rx_status *rs);
329 static void ath5k_tasklet_rx(unsigned long data);
331 static void ath5k_tx_processq(struct ath5k_softc *sc,
332 struct ath5k_txq *txq);
333 static void ath5k_tasklet_tx(unsigned long data);
334 /* Beacon handling */
335 static int ath5k_beacon_setup(struct ath5k_softc *sc,
336 struct ath5k_buf *bf);
337 static void ath5k_beacon_send(struct ath5k_softc *sc);
338 static void ath5k_beacon_config(struct ath5k_softc *sc);
339 static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
341 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
343 u64 tsf = ath5k_hw_get_tsf64(ah);
345 if ((tsf & 0x7fff) < rstamp)
348 return (tsf & ~0x7fff) | rstamp;
351 /* Interrupt handling */
352 static int ath5k_init(struct ath5k_softc *sc);
353 static int ath5k_stop_locked(struct ath5k_softc *sc);
354 static int ath5k_stop_hw(struct ath5k_softc *sc);
355 static irqreturn_t ath5k_intr(int irq, void *dev_id);
356 static void ath5k_tasklet_reset(unsigned long data);
358 static void ath5k_calibrate(unsigned long data);
360 static int ath5k_init_leds(struct ath5k_softc *sc);
361 static void ath5k_led_enable(struct ath5k_softc *sc);
362 static void ath5k_led_off(struct ath5k_softc *sc);
363 static void ath5k_unregister_leds(struct ath5k_softc *sc);
366 * Module init/exit functions
375 ret = pci_register_driver(&ath5k_pci_driver);
377 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
387 pci_unregister_driver(&ath5k_pci_driver);
389 ath5k_debug_finish();
392 module_init(init_ath5k_pci);
393 module_exit(exit_ath5k_pci);
396 /********************\
397 * PCI Initialization *
398 \********************/
401 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
403 const char *name = "xxxxx";
406 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
407 if (srev_names[i].sr_type != type)
410 if ((val & 0xf0) == srev_names[i].sr_val)
411 name = srev_names[i].sr_name;
413 if ((val & 0xff) == srev_names[i].sr_val) {
414 name = srev_names[i].sr_name;
423 ath5k_pci_probe(struct pci_dev *pdev,
424 const struct pci_device_id *id)
427 struct ath5k_softc *sc;
428 struct ieee80211_hw *hw;
432 ret = pci_enable_device(pdev);
434 dev_err(&pdev->dev, "can't enable device\n");
438 /* XXX 32-bit addressing only */
439 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
441 dev_err(&pdev->dev, "32-bit DMA not available\n");
446 * Cache line size is used to size and align various
447 * structures used to communicate with the hardware.
449 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
452 * Linux 2.4.18 (at least) writes the cache line size
453 * register as a 16-bit wide register which is wrong.
454 * We must have this setup properly for rx buffer
455 * DMA to work so force a reasonable value here if it
458 csz = L1_CACHE_BYTES / sizeof(u32);
459 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
462 * The default setting of latency timer yields poor results,
463 * set it to the value used by other systems. It may be worth
464 * tweaking this setting more.
466 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
468 /* Enable bus mastering */
469 pci_set_master(pdev);
472 * Disable the RETRY_TIMEOUT register (0x41) to keep
473 * PCI Tx retries from interfering with C3 CPU state.
475 pci_write_config_byte(pdev, 0x41, 0);
477 ret = pci_request_region(pdev, 0, "ath5k");
479 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
483 mem = pci_iomap(pdev, 0, 0);
485 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
491 * Allocate hw (mac80211 main struct)
492 * and hw->priv (driver private data)
494 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
496 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
501 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
503 /* Initialize driver private data */
504 SET_IEEE80211_DEV(hw, &pdev->dev);
505 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
506 IEEE80211_HW_SIGNAL_DBM |
507 IEEE80211_HW_NOISE_DBM;
509 hw->wiphy->interface_modes =
510 BIT(NL80211_IFTYPE_STATION) |
511 BIT(NL80211_IFTYPE_ADHOC) |
512 BIT(NL80211_IFTYPE_MESH_POINT);
514 hw->extra_tx_headroom = 2;
515 hw->channel_change_time = 5000;
520 ath5k_debug_init_device(sc);
523 * Mark the device as detached to avoid processing
524 * interrupts until setup is complete.
526 __set_bit(ATH_STAT_INVALID, sc->status);
528 sc->iobase = mem; /* So we can unmap it on detach */
529 sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
530 sc->opmode = NL80211_IFTYPE_STATION;
531 mutex_init(&sc->lock);
532 spin_lock_init(&sc->rxbuflock);
533 spin_lock_init(&sc->txbuflock);
534 spin_lock_init(&sc->block);
536 /* Set private data */
537 pci_set_drvdata(pdev, hw);
539 /* Setup interrupt handler */
540 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
542 ATH5K_ERR(sc, "request_irq failed\n");
546 /* Initialize device */
547 sc->ah = ath5k_hw_attach(sc, id->driver_data);
548 if (IS_ERR(sc->ah)) {
549 ret = PTR_ERR(sc->ah);
553 /* set up multi-rate retry capabilities */
554 if (sc->ah->ah_version == AR5K_AR5212) {
556 hw->max_rate_tries = 11;
559 /* Finish private driver data initialization */
560 ret = ath5k_attach(pdev, hw);
564 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
565 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
567 sc->ah->ah_phy_revision);
569 if (!sc->ah->ah_single_chip) {
570 /* Single chip radio (!RF5111) */
571 if (sc->ah->ah_radio_5ghz_revision &&
572 !sc->ah->ah_radio_2ghz_revision) {
573 /* No 5GHz support -> report 2GHz radio */
574 if (!test_bit(AR5K_MODE_11A,
575 sc->ah->ah_capabilities.cap_mode)) {
576 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
577 ath5k_chip_name(AR5K_VERSION_RAD,
578 sc->ah->ah_radio_5ghz_revision),
579 sc->ah->ah_radio_5ghz_revision);
580 /* No 2GHz support (5110 and some
581 * 5Ghz only cards) -> report 5Ghz radio */
582 } else if (!test_bit(AR5K_MODE_11B,
583 sc->ah->ah_capabilities.cap_mode)) {
584 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
585 ath5k_chip_name(AR5K_VERSION_RAD,
586 sc->ah->ah_radio_5ghz_revision),
587 sc->ah->ah_radio_5ghz_revision);
588 /* Multiband radio */
590 ATH5K_INFO(sc, "RF%s multiband radio found"
592 ath5k_chip_name(AR5K_VERSION_RAD,
593 sc->ah->ah_radio_5ghz_revision),
594 sc->ah->ah_radio_5ghz_revision);
597 /* Multi chip radio (RF5111 - RF2111) ->
598 * report both 2GHz/5GHz radios */
599 else if (sc->ah->ah_radio_5ghz_revision &&
600 sc->ah->ah_radio_2ghz_revision){
601 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
602 ath5k_chip_name(AR5K_VERSION_RAD,
603 sc->ah->ah_radio_5ghz_revision),
604 sc->ah->ah_radio_5ghz_revision);
605 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
606 ath5k_chip_name(AR5K_VERSION_RAD,
607 sc->ah->ah_radio_2ghz_revision),
608 sc->ah->ah_radio_2ghz_revision);
613 /* ready to process interrupts */
614 __clear_bit(ATH_STAT_INVALID, sc->status);
618 ath5k_hw_detach(sc->ah);
620 free_irq(pdev->irq, sc);
622 ieee80211_free_hw(hw);
624 pci_iounmap(pdev, mem);
626 pci_release_region(pdev, 0);
628 pci_disable_device(pdev);
633 static void __devexit
634 ath5k_pci_remove(struct pci_dev *pdev)
636 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
637 struct ath5k_softc *sc = hw->priv;
639 ath5k_debug_finish_device(sc);
640 ath5k_detach(pdev, hw);
641 ath5k_hw_detach(sc->ah);
642 free_irq(pdev->irq, sc);
643 pci_iounmap(pdev, sc->iobase);
644 pci_release_region(pdev, 0);
645 pci_disable_device(pdev);
646 ieee80211_free_hw(hw);
651 ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
653 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
654 struct ath5k_softc *sc = hw->priv;
658 free_irq(pdev->irq, sc);
659 pci_save_state(pdev);
660 pci_disable_device(pdev);
661 pci_set_power_state(pdev, PCI_D3hot);
667 ath5k_pci_resume(struct pci_dev *pdev)
669 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
670 struct ath5k_softc *sc = hw->priv;
673 pci_restore_state(pdev);
675 err = pci_enable_device(pdev);
680 * Suspend/Resume resets the PCI configuration space, so we have to
681 * re-disable the RETRY_TIMEOUT register (0x41) to keep
682 * PCI Tx retries from interfering with C3 CPU state
684 pci_write_config_byte(pdev, 0x41, 0);
686 err = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
688 ATH5K_ERR(sc, "request_irq failed\n");
692 ath5k_led_enable(sc);
696 pci_disable_device(pdev);
699 #endif /* CONFIG_PM */
702 /***********************\
703 * Driver Initialization *
704 \***********************/
707 ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
709 struct ath5k_softc *sc = hw->priv;
710 struct ath5k_hw *ah = sc->ah;
711 u8 mac[ETH_ALEN] = {};
714 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
717 * Check if the MAC has multi-rate retry support.
718 * We do this by trying to setup a fake extended
719 * descriptor. MAC's that don't have support will
720 * return false w/o doing anything. MAC's that do
721 * support it will return true w/o doing anything.
723 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
727 __set_bit(ATH_STAT_MRRETRY, sc->status);
730 * Collect the channel list. The 802.11 layer
731 * is resposible for filtering this list based
732 * on settings like the phy mode and regulatory
733 * domain restrictions.
735 ret = ath5k_setup_bands(hw);
737 ATH5K_ERR(sc, "can't get channels\n");
741 /* NB: setup here so ath5k_rate_update is happy */
742 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
743 ath5k_setcurmode(sc, AR5K_MODE_11A);
745 ath5k_setcurmode(sc, AR5K_MODE_11B);
748 * Allocate tx+rx descriptors and populate the lists.
750 ret = ath5k_desc_alloc(sc, pdev);
752 ATH5K_ERR(sc, "can't allocate descriptors\n");
757 * Allocate hardware transmit queues: one queue for
758 * beacon frames and one data queue for each QoS
759 * priority. Note that hw functions handle reseting
760 * these queues at the needed time.
762 ret = ath5k_beaconq_setup(ah);
764 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
769 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
770 if (IS_ERR(sc->txq)) {
771 ATH5K_ERR(sc, "can't setup xmit queue\n");
772 ret = PTR_ERR(sc->txq);
776 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
777 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
778 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
779 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
781 ret = ath5k_eeprom_read_mac(ah, mac);
783 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
788 SET_IEEE80211_PERM_ADDR(hw, mac);
789 /* All MAC address bits matter for ACKs */
790 memset(sc->bssidmask, 0xff, ETH_ALEN);
791 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
793 ret = ieee80211_register_hw(hw);
795 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
803 ath5k_txq_release(sc);
805 ath5k_hw_release_tx_queue(ah, sc->bhalq);
807 ath5k_desc_free(sc, pdev);
813 ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
815 struct ath5k_softc *sc = hw->priv;
818 * NB: the order of these is important:
819 * o call the 802.11 layer before detaching ath5k_hw to
820 * insure callbacks into the driver to delete global
821 * key cache entries can be handled
822 * o reclaim the tx queue data structures after calling
823 * the 802.11 layer as we'll get called back to reclaim
824 * node state and potentially want to use them
825 * o to cleanup the tx queues the hal is called, so detach
827 * XXX: ??? detach ath5k_hw ???
828 * Other than that, it's straightforward...
830 ieee80211_unregister_hw(hw);
831 ath5k_desc_free(sc, pdev);
832 ath5k_txq_release(sc);
833 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
834 ath5k_unregister_leds(sc);
837 * NB: can't reclaim these until after ieee80211_ifdetach
838 * returns because we'll get called back to reclaim node
839 * state and potentially want to use them.
846 /********************\
847 * Channel/mode setup *
848 \********************/
851 * Convert IEEE channel number to MHz frequency.
854 ath5k_ieee2mhz(short chan)
856 if (chan <= 14 || chan >= 27)
857 return ieee80211chan2mhz(chan);
859 return 2212 + chan * 20;
863 ath5k_copy_channels(struct ath5k_hw *ah,
864 struct ieee80211_channel *channels,
868 unsigned int i, count, size, chfreq, freq, ch;
870 if (!test_bit(mode, ah->ah_modes))
875 case AR5K_MODE_11A_TURBO:
876 /* 1..220, but 2GHz frequencies are filtered by check_channel */
878 chfreq = CHANNEL_5GHZ;
882 case AR5K_MODE_11G_TURBO:
884 chfreq = CHANNEL_2GHZ;
887 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
891 for (i = 0, count = 0; i < size && max > 0; i++) {
893 freq = ath5k_ieee2mhz(ch);
895 /* Check if channel is supported by the chipset */
896 if (!ath5k_channel_ok(ah, freq, chfreq))
899 /* Write channel info and increment counter */
900 channels[count].center_freq = freq;
901 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
902 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
906 channels[count].hw_value = chfreq | CHANNEL_OFDM;
908 case AR5K_MODE_11A_TURBO:
909 case AR5K_MODE_11G_TURBO:
910 channels[count].hw_value = chfreq |
911 CHANNEL_OFDM | CHANNEL_TURBO;
914 channels[count].hw_value = CHANNEL_B;
925 ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
929 for (i = 0; i < AR5K_MAX_RATES; i++)
930 sc->rate_idx[b->band][i] = -1;
932 for (i = 0; i < b->n_bitrates; i++) {
933 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
934 if (b->bitrates[i].hw_value_short)
935 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
940 ath5k_setup_bands(struct ieee80211_hw *hw)
942 struct ath5k_softc *sc = hw->priv;
943 struct ath5k_hw *ah = sc->ah;
944 struct ieee80211_supported_band *sband;
945 int max_c, count_c = 0;
948 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
949 max_c = ARRAY_SIZE(sc->channels);
952 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
953 sband->band = IEEE80211_BAND_2GHZ;
954 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
956 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
958 memcpy(sband->bitrates, &ath5k_rates[0],
959 sizeof(struct ieee80211_rate) * 12);
960 sband->n_bitrates = 12;
962 sband->channels = sc->channels;
963 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
964 AR5K_MODE_11G, max_c);
966 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
967 count_c = sband->n_channels;
969 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
971 memcpy(sband->bitrates, &ath5k_rates[0],
972 sizeof(struct ieee80211_rate) * 4);
973 sband->n_bitrates = 4;
975 /* 5211 only supports B rates and uses 4bit rate codes
976 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
979 if (ah->ah_version == AR5K_AR5211) {
980 for (i = 0; i < 4; i++) {
981 sband->bitrates[i].hw_value =
982 sband->bitrates[i].hw_value & 0xF;
983 sband->bitrates[i].hw_value_short =
984 sband->bitrates[i].hw_value_short & 0xF;
988 sband->channels = sc->channels;
989 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
990 AR5K_MODE_11B, max_c);
992 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
993 count_c = sband->n_channels;
996 ath5k_setup_rate_idx(sc, sband);
998 /* 5GHz band, A mode */
999 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
1000 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1001 sband->band = IEEE80211_BAND_5GHZ;
1002 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
1004 memcpy(sband->bitrates, &ath5k_rates[4],
1005 sizeof(struct ieee80211_rate) * 8);
1006 sband->n_bitrates = 8;
1008 sband->channels = &sc->channels[count_c];
1009 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1010 AR5K_MODE_11A, max_c);
1012 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1014 ath5k_setup_rate_idx(sc, sband);
1016 ath5k_debug_dump_bands(sc);
1022 * Set/change channels. If the channel is really being changed,
1023 * it's done by reseting the chip. To accomplish this we must
1024 * first cleanup any pending DMA, then restart stuff after a la
1028 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1030 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1031 sc->curchan->center_freq, chan->center_freq);
1033 if (chan->center_freq != sc->curchan->center_freq ||
1034 chan->hw_value != sc->curchan->hw_value) {
1037 sc->curband = &sc->sbands[chan->band];
1040 * To switch channels clear any pending DMA operations;
1041 * wait long enough for the RX fifo to drain, reset the
1042 * hardware at the new frequency, and then re-enable
1043 * the relevant bits of the h/w.
1045 return ath5k_reset(sc, true, true);
1052 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1056 if (mode == AR5K_MODE_11A) {
1057 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1059 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1064 ath5k_mode_setup(struct ath5k_softc *sc)
1066 struct ath5k_hw *ah = sc->ah;
1069 /* configure rx filter */
1070 rfilt = sc->filter_flags;
1071 ath5k_hw_set_rx_filter(ah, rfilt);
1073 if (ath5k_hw_hasbssidmask(ah))
1074 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1076 /* configure operational mode */
1077 ath5k_hw_set_opmode(ah);
1079 ath5k_hw_set_mcast_filter(ah, 0, 0);
1080 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1084 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1086 WARN_ON(hw_rix < 0 || hw_rix > AR5K_MAX_RATES);
1087 return sc->rate_idx[sc->curband->band][hw_rix];
1095 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
1097 struct sk_buff *skb;
1101 * Allocate buffer with headroom_needed space for the
1102 * fake physical layer header at the start.
1104 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1107 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1108 sc->rxbufsize + sc->cachelsz - 1);
1112 * Cache-line-align. This is important (for the
1113 * 5210 at least) as not doing so causes bogus data
1116 off = ((unsigned long)skb->data) % sc->cachelsz;
1118 skb_reserve(skb, sc->cachelsz - off);
1120 *skb_addr = pci_map_single(sc->pdev,
1121 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1122 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
1123 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1131 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1133 struct ath5k_hw *ah = sc->ah;
1134 struct sk_buff *skb = bf->skb;
1135 struct ath5k_desc *ds;
1138 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
1145 * Setup descriptors. For receive we always terminate
1146 * the descriptor list with a self-linked entry so we'll
1147 * not get overrun under high load (as can happen with a
1148 * 5212 when ANI processing enables PHY error frames).
1150 * To insure the last descriptor is self-linked we create
1151 * each descriptor as self-linked and add it to the end. As
1152 * each additional descriptor is added the previous self-linked
1153 * entry is ``fixed'' naturally. This should be safe even
1154 * if DMA is happening. When processing RX interrupts we
1155 * never remove/process the last, self-linked, entry on the
1156 * descriptor list. This insures the hardware always has
1157 * someplace to write a new frame.
1160 ds->ds_link = bf->daddr; /* link to self */
1161 ds->ds_data = bf->skbaddr;
1162 ah->ah_setup_rx_desc(ah, ds,
1163 skb_tailroom(skb), /* buffer size */
1166 if (sc->rxlink != NULL)
1167 *sc->rxlink = bf->daddr;
1168 sc->rxlink = &ds->ds_link;
1173 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1175 struct ath5k_hw *ah = sc->ah;
1176 struct ath5k_txq *txq = sc->txq;
1177 struct ath5k_desc *ds = bf->desc;
1178 struct sk_buff *skb = bf->skb;
1179 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1180 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1181 struct ieee80211_rate *rate;
1182 unsigned int mrr_rate[3], mrr_tries[3];
1189 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
1191 /* XXX endianness */
1192 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1195 rate = ieee80211_get_tx_rate(sc->hw, info);
1197 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
1198 flags |= AR5K_TXDESC_NOACK;
1200 rc_flags = info->control.rates[0].flags;
1201 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
1202 rate->hw_value_short : rate->hw_value;
1206 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1207 flags |= AR5K_TXDESC_RTSENA;
1208 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1209 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
1210 sc->vif, pktlen, info));
1212 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1213 flags |= AR5K_TXDESC_CTSENA;
1214 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1215 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
1216 sc->vif, pktlen, info));
1219 if (info->control.hw_key) {
1220 keyidx = info->control.hw_key->hw_key_idx;
1221 pktlen += info->control.hw_key->icv_len;
1223 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1224 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
1225 (sc->power_level * 2),
1227 info->control.rates[0].count, keyidx, 0, flags,
1228 cts_rate, duration);
1232 memset(mrr_rate, 0, sizeof(mrr_rate));
1233 memset(mrr_tries, 0, sizeof(mrr_tries));
1234 for (i = 0; i < 3; i++) {
1235 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1239 mrr_rate[i] = rate->hw_value;
1240 mrr_tries[i] = info->control.rates[i + 1].count;
1243 ah->ah_setup_mrr_tx_desc(ah, ds,
1244 mrr_rate[0], mrr_tries[0],
1245 mrr_rate[1], mrr_tries[1],
1246 mrr_rate[2], mrr_tries[2]);
1249 ds->ds_data = bf->skbaddr;
1251 spin_lock_bh(&txq->lock);
1252 list_add_tail(&bf->list, &txq->q);
1253 sc->tx_stats[txq->qnum].len++;
1254 if (txq->link == NULL) /* is this first packet? */
1255 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
1256 else /* no, so only link it */
1257 *txq->link = bf->daddr;
1259 txq->link = &ds->ds_link;
1260 ath5k_hw_start_tx_dma(ah, txq->qnum);
1262 spin_unlock_bh(&txq->lock);
1266 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1270 /*******************\
1271 * Descriptors setup *
1272 \*******************/
1275 ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1277 struct ath5k_desc *ds;
1278 struct ath5k_buf *bf;
1283 /* allocate descriptors */
1284 sc->desc_len = sizeof(struct ath5k_desc) *
1285 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1286 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1287 if (sc->desc == NULL) {
1288 ATH5K_ERR(sc, "can't allocate descriptors\n");
1293 da = sc->desc_daddr;
1294 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1295 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1297 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1298 sizeof(struct ath5k_buf), GFP_KERNEL);
1300 ATH5K_ERR(sc, "can't allocate bufptr\n");
1306 INIT_LIST_HEAD(&sc->rxbuf);
1307 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1310 list_add_tail(&bf->list, &sc->rxbuf);
1313 INIT_LIST_HEAD(&sc->txbuf);
1314 sc->txbuf_len = ATH_TXBUF;
1315 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1316 da += sizeof(*ds)) {
1319 list_add_tail(&bf->list, &sc->txbuf);
1329 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1336 ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1338 struct ath5k_buf *bf;
1340 ath5k_txbuf_free(sc, sc->bbuf);
1341 list_for_each_entry(bf, &sc->txbuf, list)
1342 ath5k_txbuf_free(sc, bf);
1343 list_for_each_entry(bf, &sc->rxbuf, list)
1344 ath5k_txbuf_free(sc, bf);
1346 /* Free memory associated with all descriptors */
1347 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1361 static struct ath5k_txq *
1362 ath5k_txq_setup(struct ath5k_softc *sc,
1363 int qtype, int subtype)
1365 struct ath5k_hw *ah = sc->ah;
1366 struct ath5k_txq *txq;
1367 struct ath5k_txq_info qi = {
1368 .tqi_subtype = subtype,
1369 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1370 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1371 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1376 * Enable interrupts only for EOL and DESC conditions.
1377 * We mark tx descriptors to receive a DESC interrupt
1378 * when a tx queue gets deep; otherwise waiting for the
1379 * EOL to reap descriptors. Note that this is done to
1380 * reduce interrupt load and this only defers reaping
1381 * descriptors, never transmitting frames. Aside from
1382 * reducing interrupts this also permits more concurrency.
1383 * The only potential downside is if the tx queue backs
1384 * up in which case the top half of the kernel may backup
1385 * due to a lack of tx descriptors.
1387 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1388 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1389 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1392 * NB: don't print a message, this happens
1393 * normally on parts with too few tx queues
1395 return ERR_PTR(qnum);
1397 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1398 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1399 qnum, ARRAY_SIZE(sc->txqs));
1400 ath5k_hw_release_tx_queue(ah, qnum);
1401 return ERR_PTR(-EINVAL);
1403 txq = &sc->txqs[qnum];
1407 INIT_LIST_HEAD(&txq->q);
1408 spin_lock_init(&txq->lock);
1411 return &sc->txqs[qnum];
1415 ath5k_beaconq_setup(struct ath5k_hw *ah)
1417 struct ath5k_txq_info qi = {
1418 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1419 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1420 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1421 /* NB: for dynamic turbo, don't enable any other interrupts */
1422 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1425 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1429 ath5k_beaconq_config(struct ath5k_softc *sc)
1431 struct ath5k_hw *ah = sc->ah;
1432 struct ath5k_txq_info qi;
1435 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1438 if (sc->opmode == NL80211_IFTYPE_AP ||
1439 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
1441 * Always burst out beacon and CAB traffic
1442 * (aifs = cwmin = cwmax = 0)
1447 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1449 * Adhoc mode; backoff between 0 and (2 * cw_min).
1453 qi.tqi_cw_max = 2 * ah->ah_cw_min;
1456 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1457 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1458 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1460 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
1462 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1463 "hardware queue!\n", __func__);
1467 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1471 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1473 struct ath5k_buf *bf, *bf0;
1476 * NB: this assumes output has been stopped and
1477 * we do not need to block ath5k_tx_tasklet
1479 spin_lock_bh(&txq->lock);
1480 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1481 ath5k_debug_printtxbuf(sc, bf);
1483 ath5k_txbuf_free(sc, bf);
1485 spin_lock_bh(&sc->txbuflock);
1486 sc->tx_stats[txq->qnum].len--;
1487 list_move_tail(&bf->list, &sc->txbuf);
1489 spin_unlock_bh(&sc->txbuflock);
1492 spin_unlock_bh(&txq->lock);
1496 * Drain the transmit queues and reclaim resources.
1499 ath5k_txq_cleanup(struct ath5k_softc *sc)
1501 struct ath5k_hw *ah = sc->ah;
1504 /* XXX return value */
1505 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1506 /* don't touch the hardware if marked invalid */
1507 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1508 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1509 ath5k_hw_get_txdp(ah, sc->bhalq));
1510 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1511 if (sc->txqs[i].setup) {
1512 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1513 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1516 ath5k_hw_get_txdp(ah,
1521 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
1523 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1524 if (sc->txqs[i].setup)
1525 ath5k_txq_drainq(sc, &sc->txqs[i]);
1529 ath5k_txq_release(struct ath5k_softc *sc)
1531 struct ath5k_txq *txq = sc->txqs;
1534 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1536 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1549 * Enable the receive h/w following a reset.
1552 ath5k_rx_start(struct ath5k_softc *sc)
1554 struct ath5k_hw *ah = sc->ah;
1555 struct ath5k_buf *bf;
1558 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1560 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1561 sc->cachelsz, sc->rxbufsize);
1565 spin_lock_bh(&sc->rxbuflock);
1566 list_for_each_entry(bf, &sc->rxbuf, list) {
1567 ret = ath5k_rxbuf_setup(sc, bf);
1569 spin_unlock_bh(&sc->rxbuflock);
1573 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1574 spin_unlock_bh(&sc->rxbuflock);
1576 ath5k_hw_set_rxdp(ah, bf->daddr);
1577 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
1578 ath5k_mode_setup(sc); /* set filters, etc. */
1579 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1587 * Disable the receive h/w in preparation for a reset.
1590 ath5k_rx_stop(struct ath5k_softc *sc)
1592 struct ath5k_hw *ah = sc->ah;
1594 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
1595 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1596 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
1598 ath5k_debug_printrxbuffs(sc, ah);
1600 sc->rxlink = NULL; /* just in case */
1604 ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
1605 struct sk_buff *skb, struct ath5k_rx_status *rs)
1607 struct ieee80211_hdr *hdr = (void *)skb->data;
1608 unsigned int keyix, hlen;
1610 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1611 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1612 return RX_FLAG_DECRYPTED;
1614 /* Apparently when a default key is used to decrypt the packet
1615 the hw does not set the index used to decrypt. In such cases
1616 get the index from the packet. */
1617 hlen = ieee80211_hdrlen(hdr->frame_control);
1618 if (ieee80211_has_protected(hdr->frame_control) &&
1619 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1620 skb->len >= hlen + 4) {
1621 keyix = skb->data[hlen + 3] >> 6;
1623 if (test_bit(keyix, sc->keymap))
1624 return RX_FLAG_DECRYPTED;
1632 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1633 struct ieee80211_rx_status *rxs)
1637 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1639 if (ieee80211_is_beacon(mgmt->frame_control) &&
1640 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1641 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1643 * Received an IBSS beacon with the same BSSID. Hardware *must*
1644 * have updated the local TSF. We have to work around various
1645 * hardware bugs, though...
1647 tsf = ath5k_hw_get_tsf64(sc->ah);
1648 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1649 hw_tu = TSF_TO_TU(tsf);
1651 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1652 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1653 (unsigned long long)bc_tstamp,
1654 (unsigned long long)rxs->mactime,
1655 (unsigned long long)(rxs->mactime - bc_tstamp),
1656 (unsigned long long)tsf);
1659 * Sometimes the HW will give us a wrong tstamp in the rx
1660 * status, causing the timestamp extension to go wrong.
1661 * (This seems to happen especially with beacon frames bigger
1662 * than 78 byte (incl. FCS))
1663 * But we know that the receive timestamp must be later than the
1664 * timestamp of the beacon since HW must have synced to that.
1666 * NOTE: here we assume mactime to be after the frame was
1667 * received, not like mac80211 which defines it at the start.
1669 if (bc_tstamp > rxs->mactime) {
1670 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1671 "fixing mactime from %llx to %llx\n",
1672 (unsigned long long)rxs->mactime,
1673 (unsigned long long)tsf);
1678 * Local TSF might have moved higher than our beacon timers,
1679 * in that case we have to update them to continue sending
1680 * beacons. This also takes care of synchronizing beacon sending
1681 * times with other stations.
1683 if (hw_tu >= sc->nexttbtt)
1684 ath5k_beacon_update_timers(sc, bc_tstamp);
1690 ath5k_tasklet_rx(unsigned long data)
1692 struct ieee80211_rx_status rxs = {};
1693 struct ath5k_rx_status rs = {};
1694 struct sk_buff *skb, *next_skb;
1695 dma_addr_t next_skb_addr;
1696 struct ath5k_softc *sc = (void *)data;
1697 struct ath5k_buf *bf, *bf_last;
1698 struct ath5k_desc *ds;
1703 spin_lock(&sc->rxbuflock);
1704 if (list_empty(&sc->rxbuf)) {
1705 ATH5K_WARN(sc, "empty rx buf pool\n");
1708 bf_last = list_entry(sc->rxbuf.prev, struct ath5k_buf, list);
1712 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1713 BUG_ON(bf->skb == NULL);
1718 * last buffer must not be freed to ensure proper hardware
1719 * function. When the hardware finishes also a packet next to
1720 * it, we are sure, it doesn't use it anymore and we can go on.
1725 struct ath5k_buf *bf_next = list_entry(bf->list.next,
1726 struct ath5k_buf, list);
1727 ret = sc->ah->ah_proc_rx_desc(sc->ah, bf_next->desc,
1732 /* skip the overwritten one (even status is martian) */
1736 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1737 if (unlikely(ret == -EINPROGRESS))
1739 else if (unlikely(ret)) {
1740 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1741 spin_unlock(&sc->rxbuflock);
1745 if (unlikely(rs.rs_more)) {
1746 ATH5K_WARN(sc, "unsupported jumbo\n");
1750 if (unlikely(rs.rs_status)) {
1751 if (rs.rs_status & AR5K_RXERR_PHY)
1753 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
1755 * Decrypt error. If the error occurred
1756 * because there was no hardware key, then
1757 * let the frame through so the upper layers
1758 * can process it. This is necessary for 5210
1759 * parts which have no way to setup a ``clear''
1762 * XXX do key cache faulting
1764 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1765 !(rs.rs_status & AR5K_RXERR_CRC))
1768 if (rs.rs_status & AR5K_RXERR_MIC) {
1769 rxs.flag |= RX_FLAG_MMIC_ERROR;
1773 /* let crypto-error packets fall through in MNTR */
1775 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
1776 sc->opmode != NL80211_IFTYPE_MONITOR)
1780 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
1783 * If we can't replace bf->skb with a new skb under memory
1784 * pressure, just skip this packet
1789 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1790 PCI_DMA_FROMDEVICE);
1791 skb_put(skb, rs.rs_datalen);
1793 /* The MAC header is padded to have 32-bit boundary if the
1794 * packet payload is non-zero. The general calculation for
1795 * padsize would take into account odd header lengths:
1796 * padsize = (4 - hdrlen % 4) % 4; However, since only
1797 * even-length headers are used, padding can only be 0 or 2
1798 * bytes and we can optimize this a bit. In addition, we must
1799 * not try to remove padding from short control frames that do
1800 * not have payload. */
1801 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1802 padsize = ath5k_pad_size(hdrlen);
1804 memmove(skb->data + padsize, skb->data, hdrlen);
1805 skb_pull(skb, padsize);
1809 * always extend the mac timestamp, since this information is
1810 * also needed for proper IBSS merging.
1812 * XXX: it might be too late to do it here, since rs_tstamp is
1813 * 15bit only. that means TSF extension has to be done within
1814 * 32768usec (about 32ms). it might be necessary to move this to
1815 * the interrupt handler, like it is done in madwifi.
1817 * Unfortunately we don't know when the hardware takes the rx
1818 * timestamp (beginning of phy frame, data frame, end of rx?).
1819 * The only thing we know is that it is hardware specific...
1820 * On AR5213 it seems the rx timestamp is at the end of the
1821 * frame, but i'm not sure.
1823 * NOTE: mac80211 defines mactime at the beginning of the first
1824 * data symbol. Since we don't have any time references it's
1825 * impossible to comply to that. This affects IBSS merge only
1826 * right now, so it's not too bad...
1828 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
1829 rxs.flag |= RX_FLAG_TSFT;
1831 rxs.freq = sc->curchan->center_freq;
1832 rxs.band = sc->curband->band;
1834 rxs.noise = sc->ah->ah_noise_floor;
1835 rxs.signal = rxs.noise + rs.rs_rssi;
1837 /* An rssi of 35 indicates you should be able use
1838 * 54 Mbps reliably. A more elaborate scheme can be used
1839 * here but it requires a map of SNR/throughput for each
1840 * possible mode used */
1841 rxs.qual = rs.rs_rssi * 100 / 35;
1843 /* rssi can be more than 35 though, anything above that
1844 * should be considered at 100% */
1848 rxs.antenna = rs.rs_antenna;
1849 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1850 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
1852 if (rxs.rate_idx >= 0 && rs.rs_rate ==
1853 sc->curband->bitrates[rxs.rate_idx].hw_value_short)
1854 rxs.flag |= RX_FLAG_SHORTPRE;
1856 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1858 /* check beacons in IBSS mode */
1859 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1860 ath5k_check_ibss_tsf(sc, skb, &rxs);
1862 __ieee80211_rx(sc->hw, skb, &rxs);
1865 bf->skbaddr = next_skb_addr;
1867 list_move_tail(&bf->list, &sc->rxbuf);
1868 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1870 spin_unlock(&sc->rxbuflock);
1881 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1883 struct ath5k_tx_status ts = {};
1884 struct ath5k_buf *bf, *bf0;
1885 struct ath5k_desc *ds;
1886 struct sk_buff *skb;
1887 struct ieee80211_tx_info *info;
1890 spin_lock(&txq->lock);
1891 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1894 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1895 if (unlikely(ret == -EINPROGRESS))
1897 else if (unlikely(ret)) {
1898 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1904 info = IEEE80211_SKB_CB(skb);
1907 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1910 ieee80211_tx_info_clear_status(info);
1911 for (i = 0; i < 4; i++) {
1912 struct ieee80211_tx_rate *r =
1913 &info->status.rates[i];
1915 if (ts.ts_rate[i]) {
1916 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
1917 r->count = ts.ts_retry[i];
1924 /* count the successful attempt as well */
1925 info->status.rates[ts.ts_final_idx].count++;
1927 if (unlikely(ts.ts_status)) {
1928 sc->ll_stats.dot11ACKFailureCount++;
1929 if (ts.ts_status & AR5K_TXERR_FILT)
1930 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1932 info->flags |= IEEE80211_TX_STAT_ACK;
1933 info->status.ack_signal = ts.ts_rssi;
1936 ieee80211_tx_status(sc->hw, skb);
1937 sc->tx_stats[txq->qnum].count++;
1939 spin_lock(&sc->txbuflock);
1940 sc->tx_stats[txq->qnum].len--;
1941 list_move_tail(&bf->list, &sc->txbuf);
1943 spin_unlock(&sc->txbuflock);
1945 if (likely(list_empty(&txq->q)))
1947 spin_unlock(&txq->lock);
1948 if (sc->txbuf_len > ATH_TXBUF / 5)
1949 ieee80211_wake_queues(sc->hw);
1953 ath5k_tasklet_tx(unsigned long data)
1955 struct ath5k_softc *sc = (void *)data;
1957 ath5k_tx_processq(sc, sc->txq);
1966 * Setup the beacon frame for transmit.
1969 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1971 struct sk_buff *skb = bf->skb;
1972 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1973 struct ath5k_hw *ah = sc->ah;
1974 struct ath5k_desc *ds;
1975 int ret, antenna = 0;
1978 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1980 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1981 "skbaddr %llx\n", skb, skb->data, skb->len,
1982 (unsigned long long)bf->skbaddr);
1983 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
1984 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1990 flags = AR5K_TXDESC_NOACK;
1991 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
1992 ds->ds_link = bf->daddr; /* self-linked */
1993 flags |= AR5K_TXDESC_VEOL;
1995 * Let hardware handle antenna switching if txantenna is not set
2000 * Switch antenna every 4 beacons if txantenna is not set
2001 * XXX assumes two antennas
2004 antenna = sc->bsent & 4 ? 2 : 1;
2007 ds->ds_data = bf->skbaddr;
2008 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
2009 ieee80211_get_hdrlen_from_skb(skb),
2010 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
2011 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2012 1, AR5K_TXKEYIX_INVALID,
2013 antenna, flags, 0, 0);
2019 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
2024 * Transmit a beacon frame at SWBA. Dynamic updates to the
2025 * frame contents are done as needed and the slot time is
2026 * also adjusted based on current state.
2028 * this is usually called from interrupt context (ath5k_intr())
2029 * but also from ath5k_beacon_config() in IBSS mode which in turn
2030 * can be called from a tasklet and user context
2033 ath5k_beacon_send(struct ath5k_softc *sc)
2035 struct ath5k_buf *bf = sc->bbuf;
2036 struct ath5k_hw *ah = sc->ah;
2038 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
2040 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
2041 sc->opmode == NL80211_IFTYPE_MONITOR)) {
2042 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2046 * Check if the previous beacon has gone out. If
2047 * not don't don't try to post another, skip this
2048 * period and wait for the next. Missed beacons
2049 * indicate a problem and should not occur. If we
2050 * miss too many consecutive beacons reset the device.
2052 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2054 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2055 "missed %u consecutive beacons\n", sc->bmisscount);
2056 if (sc->bmisscount > 3) { /* NB: 3 is a guess */
2057 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2058 "stuck beacon time (%u missed)\n",
2060 tasklet_schedule(&sc->restq);
2064 if (unlikely(sc->bmisscount != 0)) {
2065 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2066 "resume beacon xmit after %u misses\n",
2072 * Stop any current dma and put the new frame on the queue.
2073 * This should never fail since we check above that no frames
2074 * are still pending on the queue.
2076 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2077 ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
2078 /* NB: hw still stops DMA, so proceed */
2081 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2082 ath5k_hw_start_tx_dma(ah, sc->bhalq);
2083 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
2084 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2091 * ath5k_beacon_update_timers - update beacon timers
2093 * @sc: struct ath5k_softc pointer we are operating on
2094 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2095 * beacon timer update based on the current HW TSF.
2097 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2098 * of a received beacon or the current local hardware TSF and write it to the
2099 * beacon timer registers.
2101 * This is called in a variety of situations, e.g. when a beacon is received,
2102 * when a TSF update has been detected, but also when an new IBSS is created or
2103 * when we otherwise know we have to update the timers, but we keep it in this
2104 * function to have it all together in one place.
2107 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
2109 struct ath5k_hw *ah = sc->ah;
2110 u32 nexttbtt, intval, hw_tu, bc_tu;
2113 intval = sc->bintval & AR5K_BEACON_PERIOD;
2114 if (WARN_ON(!intval))
2117 /* beacon TSF converted to TU */
2118 bc_tu = TSF_TO_TU(bc_tsf);
2120 /* current TSF converted to TU */
2121 hw_tsf = ath5k_hw_get_tsf64(ah);
2122 hw_tu = TSF_TO_TU(hw_tsf);
2125 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2128 * no beacons received, called internally.
2129 * just need to refresh timers based on HW TSF.
2131 nexttbtt = roundup(hw_tu + FUDGE, intval);
2132 } else if (bc_tsf == 0) {
2134 * no beacon received, probably called by ath5k_reset_tsf().
2135 * reset TSF to start with 0.
2138 intval |= AR5K_BEACON_RESET_TSF;
2139 } else if (bc_tsf > hw_tsf) {
2141 * beacon received, SW merge happend but HW TSF not yet updated.
2142 * not possible to reconfigure timers yet, but next time we
2143 * receive a beacon with the same BSSID, the hardware will
2144 * automatically update the TSF and then we need to reconfigure
2147 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2148 "need to wait for HW TSF sync\n");
2152 * most important case for beacon synchronization between STA.
2154 * beacon received and HW TSF has been already updated by HW.
2155 * update next TBTT based on the TSF of the beacon, but make
2156 * sure it is ahead of our local TSF timer.
2158 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2162 sc->nexttbtt = nexttbtt;
2164 intval |= AR5K_BEACON_ENA;
2165 ath5k_hw_init_beacon(ah, nexttbtt, intval);
2168 * debugging output last in order to preserve the time critical aspect
2172 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2173 "reconfigured timers based on HW TSF\n");
2174 else if (bc_tsf == 0)
2175 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2176 "reset HW TSF and timers\n");
2178 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2179 "updated timers based on beacon TSF\n");
2181 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2182 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2183 (unsigned long long) bc_tsf,
2184 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2185 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2186 intval & AR5K_BEACON_PERIOD,
2187 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2188 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2193 * ath5k_beacon_config - Configure the beacon queues and interrupts
2195 * @sc: struct ath5k_softc pointer we are operating on
2197 * When operating in station mode we want to receive a BMISS interrupt when we
2198 * stop seeing beacons from the AP we've associated with so we can look for
2199 * another AP to associate with.
2201 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2202 * interrupts to detect TSF updates only.
2205 ath5k_beacon_config(struct ath5k_softc *sc)
2207 struct ath5k_hw *ah = sc->ah;
2209 ath5k_hw_set_imr(ah, 0);
2211 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2213 if (sc->opmode == NL80211_IFTYPE_STATION) {
2214 sc->imask |= AR5K_INT_BMISS;
2215 } else if (sc->opmode == NL80211_IFTYPE_ADHOC ||
2216 sc->opmode == NL80211_IFTYPE_MESH_POINT ||
2217 sc->opmode == NL80211_IFTYPE_AP) {
2219 * In IBSS mode we use a self-linked tx descriptor and let the
2220 * hardware send the beacons automatically. We have to load it
2222 * We use the SWBA interrupt only to keep track of the beacon
2223 * timers in order to detect automatic TSF updates.
2225 ath5k_beaconq_config(sc);
2227 sc->imask |= AR5K_INT_SWBA;
2229 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2230 if (ath5k_hw_hasveol(ah)) {
2231 spin_lock(&sc->block);
2232 ath5k_beacon_send(sc);
2233 spin_unlock(&sc->block);
2236 ath5k_beacon_update_timers(sc, -1);
2239 ath5k_hw_set_imr(ah, sc->imask);
2243 /********************\
2244 * Interrupt handling *
2245 \********************/
2248 ath5k_init(struct ath5k_softc *sc)
2250 struct ath5k_hw *ah = sc->ah;
2253 mutex_lock(&sc->lock);
2255 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2258 * Stop anything previously setup. This is safe
2259 * no matter this is the first time through or not.
2261 ath5k_stop_locked(sc);
2264 * The basic interface to setting the hardware in a good
2265 * state is ``reset''. On return the hardware is known to
2266 * be powered up and with interrupts disabled. This must
2267 * be followed by initialization of the appropriate bits
2268 * and then setup of the interrupt mask.
2270 sc->curchan = sc->hw->conf.channel;
2271 sc->curband = &sc->sbands[sc->curchan->band];
2272 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2273 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2274 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
2275 ret = ath5k_reset(sc, false, false);
2280 * Reset the key cache since some parts do not reset the
2281 * contents on initial power up or resume from suspend.
2283 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2284 ath5k_hw_reset_key(ah, i);
2286 /* Set ack to be sent at low bit-rates */
2287 ath5k_hw_set_ack_bitrate_high(ah, false);
2289 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2290 msecs_to_jiffies(ath5k_calinterval * 1000)));
2295 mutex_unlock(&sc->lock);
2300 ath5k_stop_locked(struct ath5k_softc *sc)
2302 struct ath5k_hw *ah = sc->ah;
2304 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2305 test_bit(ATH_STAT_INVALID, sc->status));
2308 * Shutdown the hardware and driver:
2309 * stop output from above
2310 * disable interrupts
2312 * turn off the radio
2313 * clear transmit machinery
2314 * clear receive machinery
2315 * drain and release tx queues
2316 * reclaim beacon resources
2317 * power down hardware
2319 * Note that some of this work is not possible if the
2320 * hardware is gone (invalid).
2322 ieee80211_stop_queues(sc->hw);
2324 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2326 ath5k_hw_set_imr(ah, 0);
2327 synchronize_irq(sc->pdev->irq);
2329 ath5k_txq_cleanup(sc);
2330 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2332 ath5k_hw_phy_disable(ah);
2340 * Stop the device, grabbing the top-level lock to protect
2341 * against concurrent entry through ath5k_init (which can happen
2342 * if another thread does a system call and the thread doing the
2343 * stop is preempted).
2346 ath5k_stop_hw(struct ath5k_softc *sc)
2350 mutex_lock(&sc->lock);
2351 ret = ath5k_stop_locked(sc);
2352 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2354 * Set the chip in full sleep mode. Note that we are
2355 * careful to do this only when bringing the interface
2356 * completely to a stop. When the chip is in this state
2357 * it must be carefully woken up or references to
2358 * registers in the PCI clock domain may freeze the bus
2359 * (and system). This varies by chip and is mostly an
2360 * issue with newer parts that go to sleep more quickly.
2362 if (sc->ah->ah_mac_srev >= 0x78) {
2365 * don't put newer MAC revisions > 7.8 to sleep because
2366 * of the above mentioned problems
2368 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2369 "not putting device to sleep\n");
2371 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2372 "putting device to full sleep\n");
2373 ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2376 ath5k_txbuf_free(sc, sc->bbuf);
2379 mutex_unlock(&sc->lock);
2381 del_timer_sync(&sc->calib_tim);
2382 tasklet_kill(&sc->rxtq);
2383 tasklet_kill(&sc->txtq);
2384 tasklet_kill(&sc->restq);
2390 ath5k_intr(int irq, void *dev_id)
2392 struct ath5k_softc *sc = dev_id;
2393 struct ath5k_hw *ah = sc->ah;
2394 enum ath5k_int status;
2395 unsigned int counter = 1000;
2397 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2398 !ath5k_hw_is_intr_pending(ah)))
2403 * Figure out the reason(s) for the interrupt. Note
2404 * that get_isr returns a pseudo-ISR that may include
2405 * bits we haven't explicitly enabled so we mask the
2406 * value to insure we only process bits we requested.
2408 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2409 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2411 status &= sc->imask; /* discard unasked for bits */
2412 if (unlikely(status & AR5K_INT_FATAL)) {
2414 * Fatal errors are unrecoverable.
2415 * Typically these are caused by DMA errors.
2417 tasklet_schedule(&sc->restq);
2418 } else if (unlikely(status & AR5K_INT_RXORN)) {
2419 tasklet_schedule(&sc->restq);
2421 if (status & AR5K_INT_SWBA) {
2423 * Software beacon alert--time to send a beacon.
2424 * Handle beacon transmission directly; deferring
2425 * this is too slow to meet timing constraints
2428 * In IBSS mode we use this interrupt just to
2429 * keep track of the next TBTT (target beacon
2430 * transmission time) in order to detect wether
2431 * automatic TSF updates happened.
2433 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2434 /* XXX: only if VEOL suppported */
2435 u64 tsf = ath5k_hw_get_tsf64(ah);
2436 sc->nexttbtt += sc->bintval;
2437 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2438 "SWBA nexttbtt: %x hw_tu: %x "
2442 (unsigned long long) tsf);
2444 spin_lock(&sc->block);
2445 ath5k_beacon_send(sc);
2446 spin_unlock(&sc->block);
2449 if (status & AR5K_INT_RXEOL) {
2451 * NB: the hardware should re-read the link when
2452 * RXE bit is written, but it doesn't work at
2453 * least on older hardware revs.
2457 if (status & AR5K_INT_TXURN) {
2458 /* bump tx trigger level */
2459 ath5k_hw_update_tx_triglevel(ah, true);
2461 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
2462 tasklet_schedule(&sc->rxtq);
2463 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2464 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
2465 tasklet_schedule(&sc->txtq);
2466 if (status & AR5K_INT_BMISS) {
2468 if (status & AR5K_INT_MIB) {
2470 * These stats are also used for ANI i think
2471 * so how about updating them more often ?
2473 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
2476 } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
2478 if (unlikely(!counter))
2479 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2485 ath5k_tasklet_reset(unsigned long data)
2487 struct ath5k_softc *sc = (void *)data;
2489 ath5k_reset_wake(sc);
2493 * Periodically recalibrate the PHY to account
2494 * for temperature/environment changes.
2497 ath5k_calibrate(unsigned long data)
2499 struct ath5k_softc *sc = (void *)data;
2500 struct ath5k_hw *ah = sc->ah;
2502 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2503 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2504 sc->curchan->hw_value);
2506 if (ath5k_hw_get_rf_gain(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2508 * Rfgain is out of bounds, reset the chip
2509 * to load new gain values.
2511 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2512 ath5k_reset_wake(sc);
2514 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2515 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2516 ieee80211_frequency_to_channel(
2517 sc->curchan->center_freq));
2519 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2520 msecs_to_jiffies(ath5k_calinterval * 1000)));
2530 ath5k_led_enable(struct ath5k_softc *sc)
2532 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
2533 ath5k_hw_set_gpio_output(sc->ah, sc->led_pin);
2539 ath5k_led_on(struct ath5k_softc *sc)
2541 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2543 ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on);
2547 ath5k_led_off(struct ath5k_softc *sc)
2549 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2551 ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on);
2555 ath5k_led_brightness_set(struct led_classdev *led_dev,
2556 enum led_brightness brightness)
2558 struct ath5k_led *led = container_of(led_dev, struct ath5k_led,
2561 if (brightness == LED_OFF)
2562 ath5k_led_off(led->sc);
2564 ath5k_led_on(led->sc);
2568 ath5k_register_led(struct ath5k_softc *sc, struct ath5k_led *led,
2569 const char *name, char *trigger)
2574 strncpy(led->name, name, sizeof(led->name));
2575 led->led_dev.name = led->name;
2576 led->led_dev.default_trigger = trigger;
2577 led->led_dev.brightness_set = ath5k_led_brightness_set;
2579 err = led_classdev_register(&sc->pdev->dev, &led->led_dev);
2581 ATH5K_WARN(sc, "could not register LED %s\n", name);
2588 ath5k_unregister_led(struct ath5k_led *led)
2592 led_classdev_unregister(&led->led_dev);
2593 ath5k_led_off(led->sc);
2598 ath5k_unregister_leds(struct ath5k_softc *sc)
2600 ath5k_unregister_led(&sc->rx_led);
2601 ath5k_unregister_led(&sc->tx_led);
2606 ath5k_init_leds(struct ath5k_softc *sc)
2609 struct ieee80211_hw *hw = sc->hw;
2610 struct pci_dev *pdev = sc->pdev;
2611 char name[ATH5K_LED_MAX_NAME_LEN + 1];
2614 * Auto-enable soft led processing for IBM cards and for
2615 * 5211 minipci cards.
2617 if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM ||
2618 pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) {
2619 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2621 sc->led_on = 0; /* active low */
2623 /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
2624 if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) {
2625 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2627 sc->led_on = 1; /* active high */
2630 * Pin 3 on Foxconn chips used in Acer Aspire One (0x105b:e008) and
2631 * in emachines notebooks with AMBIT subsystem.
2633 if (pdev->subsystem_vendor == PCI_VENDOR_ID_FOXCONN ||
2634 pdev->subsystem_vendor == PCI_VENDOR_ID_AMBIT) {
2635 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2637 sc->led_on = 0; /* active low */
2640 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2643 ath5k_led_enable(sc);
2645 snprintf(name, sizeof(name), "ath5k-%s::rx", wiphy_name(hw->wiphy));
2646 ret = ath5k_register_led(sc, &sc->rx_led, name,
2647 ieee80211_get_rx_led_name(hw));
2651 snprintf(name, sizeof(name), "ath5k-%s::tx", wiphy_name(hw->wiphy));
2652 ret = ath5k_register_led(sc, &sc->tx_led, name,
2653 ieee80211_get_tx_led_name(hw));
2659 /********************\
2660 * Mac80211 functions *
2661 \********************/
2664 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2666 struct ath5k_softc *sc = hw->priv;
2667 struct ath5k_buf *bf;
2668 unsigned long flags;
2672 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2674 if (sc->opmode == NL80211_IFTYPE_MONITOR)
2675 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2678 * the hardware expects the header padded to 4 byte boundaries
2679 * if this is not the case we add the padding after the header
2681 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2682 padsize = ath5k_pad_size(hdrlen);
2685 if (skb_headroom(skb) < padsize) {
2686 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2687 " headroom to pad %d\n", hdrlen, padsize);
2688 return NETDEV_TX_BUSY;
2690 skb_push(skb, padsize);
2691 memmove(skb->data, skb->data+padsize, hdrlen);
2694 spin_lock_irqsave(&sc->txbuflock, flags);
2695 if (list_empty(&sc->txbuf)) {
2696 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2697 spin_unlock_irqrestore(&sc->txbuflock, flags);
2698 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
2699 return NETDEV_TX_BUSY;
2701 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2702 list_del(&bf->list);
2704 if (list_empty(&sc->txbuf))
2705 ieee80211_stop_queues(hw);
2706 spin_unlock_irqrestore(&sc->txbuflock, flags);
2710 if (ath5k_txbuf_setup(sc, bf)) {
2712 spin_lock_irqsave(&sc->txbuflock, flags);
2713 list_add_tail(&bf->list, &sc->txbuf);
2715 spin_unlock_irqrestore(&sc->txbuflock, flags);
2716 dev_kfree_skb_any(skb);
2717 return NETDEV_TX_OK;
2720 return NETDEV_TX_OK;
2724 ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel)
2726 struct ath5k_hw *ah = sc->ah;
2729 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2732 ath5k_hw_set_imr(ah, 0);
2733 ath5k_txq_cleanup(sc);
2736 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
2738 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2743 * This is needed only to setup initial state
2744 * but it's best done after a reset.
2746 ath5k_hw_set_txpower_limit(sc->ah, 0);
2748 ret = ath5k_rx_start(sc);
2750 ATH5K_ERR(sc, "can't start recv logic\n");
2755 * Change channels and update the h/w rate map if we're switching;
2756 * e.g. 11a to 11b/g.
2758 * We may be doing a reset in response to an ioctl that changes the
2759 * channel so update any state that might change as a result.
2763 /* ath5k_chan_change(sc, c); */
2765 ath5k_beacon_config(sc);
2766 /* intrs are enabled by ath5k_beacon_config */
2774 ath5k_reset_wake(struct ath5k_softc *sc)
2778 ret = ath5k_reset(sc, true, true);
2780 ieee80211_wake_queues(sc->hw);
2785 static int ath5k_start(struct ieee80211_hw *hw)
2787 return ath5k_init(hw->priv);
2790 static void ath5k_stop(struct ieee80211_hw *hw)
2792 ath5k_stop_hw(hw->priv);
2795 static int ath5k_add_interface(struct ieee80211_hw *hw,
2796 struct ieee80211_if_init_conf *conf)
2798 struct ath5k_softc *sc = hw->priv;
2801 mutex_lock(&sc->lock);
2807 sc->vif = conf->vif;
2809 switch (conf->type) {
2810 case NL80211_IFTYPE_AP:
2811 case NL80211_IFTYPE_STATION:
2812 case NL80211_IFTYPE_ADHOC:
2813 case NL80211_IFTYPE_MESH_POINT:
2814 case NL80211_IFTYPE_MONITOR:
2815 sc->opmode = conf->type;
2822 /* Set to a reasonable value. Note that this will
2823 * be set to mac80211's value at ath5k_config(). */
2825 ath5k_hw_set_lladdr(sc->ah, conf->mac_addr);
2829 mutex_unlock(&sc->lock);
2834 ath5k_remove_interface(struct ieee80211_hw *hw,
2835 struct ieee80211_if_init_conf *conf)
2837 struct ath5k_softc *sc = hw->priv;
2838 u8 mac[ETH_ALEN] = {};
2840 mutex_lock(&sc->lock);
2841 if (sc->vif != conf->vif)
2844 ath5k_hw_set_lladdr(sc->ah, mac);
2847 mutex_unlock(&sc->lock);
2851 * TODO: Phy disable/diversity etc
2854 ath5k_config(struct ieee80211_hw *hw, u32 changed)
2856 struct ath5k_softc *sc = hw->priv;
2857 struct ieee80211_conf *conf = &hw->conf;
2859 sc->bintval = conf->beacon_int;
2860 sc->power_level = conf->power_level;
2862 return ath5k_chan_set(sc, conf->channel);
2866 ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2867 struct ieee80211_if_conf *conf)
2869 struct ath5k_softc *sc = hw->priv;
2870 struct ath5k_hw *ah = sc->ah;
2873 mutex_lock(&sc->lock);
2874 if (sc->vif != vif) {
2878 if (conf->changed & IEEE80211_IFCC_BSSID && conf->bssid) {
2879 /* Cache for later use during resets */
2880 memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
2881 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2882 * a clean way of letting us retrieve this yet. */
2883 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
2886 if (conf->changed & IEEE80211_IFCC_BEACON &&
2887 (vif->type == NL80211_IFTYPE_ADHOC ||
2888 vif->type == NL80211_IFTYPE_MESH_POINT ||
2889 vif->type == NL80211_IFTYPE_AP)) {
2890 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2895 ath5k_beacon_update(sc, beacon);
2897 mutex_unlock(&sc->lock);
2899 return ath5k_reset_wake(sc);
2901 mutex_unlock(&sc->lock);
2905 #define SUPPORTED_FIF_FLAGS \
2906 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2907 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2908 FIF_BCN_PRBRESP_PROMISC
2910 * o always accept unicast, broadcast, and multicast traffic
2911 * o multicast traffic for all BSSIDs will be enabled if mac80211
2913 * o maintain current state of phy ofdm or phy cck error reception.
2914 * If the hardware detects any of these type of errors then
2915 * ath5k_hw_get_rx_filter() will pass to us the respective
2916 * hardware filters to be able to receive these type of frames.
2917 * o probe request frames are accepted only when operating in
2918 * hostap, adhoc, or monitor modes
2919 * o enable promiscuous mode according to the interface state
2921 * - when operating in adhoc mode so the 802.11 layer creates
2922 * node table entries for peers,
2923 * - when operating in station mode for collecting rssi data when
2924 * the station is otherwise quiet, or
2927 static void ath5k_configure_filter(struct ieee80211_hw *hw,
2928 unsigned int changed_flags,
2929 unsigned int *new_flags,
2930 int mc_count, struct dev_mc_list *mclist)
2932 struct ath5k_softc *sc = hw->priv;
2933 struct ath5k_hw *ah = sc->ah;
2934 u32 mfilt[2], val, rfilt;
2941 /* Only deal with supported flags */
2942 changed_flags &= SUPPORTED_FIF_FLAGS;
2943 *new_flags &= SUPPORTED_FIF_FLAGS;
2945 /* If HW detects any phy or radar errors, leave those filters on.
2946 * Also, always enable Unicast, Broadcasts and Multicast
2947 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2948 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2949 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2950 AR5K_RX_FILTER_MCAST);
2952 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2953 if (*new_flags & FIF_PROMISC_IN_BSS) {
2954 rfilt |= AR5K_RX_FILTER_PROM;
2955 __set_bit(ATH_STAT_PROMISC, sc->status);
2957 __clear_bit(ATH_STAT_PROMISC, sc->status);
2961 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2962 if (*new_flags & FIF_ALLMULTI) {
2966 for (i = 0; i < mc_count; i++) {
2969 /* calculate XOR of eight 6-bit values */
2970 val = get_unaligned_le32(mclist->dmi_addr + 0);
2971 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2972 val = get_unaligned_le32(mclist->dmi_addr + 3);
2973 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2975 mfilt[pos / 32] |= (1 << (pos % 32));
2976 /* XXX: we might be able to just do this instead,
2977 * but not sure, needs testing, if we do use this we'd
2978 * neet to inform below to not reset the mcast */
2979 /* ath5k_hw_set_mcast_filterindex(ah,
2980 * mclist->dmi_addr[5]); */
2981 mclist = mclist->next;
2985 /* This is the best we can do */
2986 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2987 rfilt |= AR5K_RX_FILTER_PHYERR;
2989 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2990 * and probes for any BSSID, this needs testing */
2991 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2992 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2994 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2995 * set we should only pass on control frames for this
2996 * station. This needs testing. I believe right now this
2997 * enables *all* control frames, which is OK.. but
2998 * but we should see if we can improve on granularity */
2999 if (*new_flags & FIF_CONTROL)
3000 rfilt |= AR5K_RX_FILTER_CONTROL;
3002 /* Additional settings per mode -- this is per ath5k */
3004 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
3006 if (sc->opmode == NL80211_IFTYPE_MONITOR)
3007 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
3008 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
3009 if (sc->opmode != NL80211_IFTYPE_STATION)
3010 rfilt |= AR5K_RX_FILTER_PROBEREQ;
3011 if (sc->opmode != NL80211_IFTYPE_AP &&
3012 sc->opmode != NL80211_IFTYPE_MESH_POINT &&
3013 test_bit(ATH_STAT_PROMISC, sc->status))
3014 rfilt |= AR5K_RX_FILTER_PROM;
3015 if ((sc->opmode == NL80211_IFTYPE_STATION && sc->assoc) ||
3016 sc->opmode == NL80211_IFTYPE_ADHOC ||
3017 sc->opmode == NL80211_IFTYPE_AP)
3018 rfilt |= AR5K_RX_FILTER_BEACON;
3019 if (sc->opmode == NL80211_IFTYPE_MESH_POINT)
3020 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
3021 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
3024 ath5k_hw_set_rx_filter(ah, rfilt);
3026 /* Set multicast bits */
3027 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
3028 /* Set the cached hw filter flags, this will alter actually
3030 sc->filter_flags = rfilt;
3034 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3035 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3036 struct ieee80211_key_conf *key)
3038 struct ath5k_softc *sc = hw->priv;
3041 if (modparam_nohwcrypt)
3055 mutex_lock(&sc->lock);
3059 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key,
3060 sta ? sta->addr : NULL);
3062 ATH5K_ERR(sc, "can't set the key\n");
3065 __set_bit(key->keyidx, sc->keymap);
3066 key->hw_key_idx = key->keyidx;
3067 key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV |
3068 IEEE80211_KEY_FLAG_GENERATE_MMIC);
3071 ath5k_hw_reset_key(sc->ah, key->keyidx);
3072 __clear_bit(key->keyidx, sc->keymap);
3081 mutex_unlock(&sc->lock);
3086 ath5k_get_stats(struct ieee80211_hw *hw,
3087 struct ieee80211_low_level_stats *stats)
3089 struct ath5k_softc *sc = hw->priv;
3090 struct ath5k_hw *ah = sc->ah;
3093 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
3095 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
3101 ath5k_get_tx_stats(struct ieee80211_hw *hw,
3102 struct ieee80211_tx_queue_stats *stats)
3104 struct ath5k_softc *sc = hw->priv;
3106 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
3112 ath5k_get_tsf(struct ieee80211_hw *hw)
3114 struct ath5k_softc *sc = hw->priv;
3116 return ath5k_hw_get_tsf64(sc->ah);
3120 ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3122 struct ath5k_softc *sc = hw->priv;
3124 ath5k_hw_set_tsf64(sc->ah, tsf);
3128 ath5k_reset_tsf(struct ieee80211_hw *hw)
3130 struct ath5k_softc *sc = hw->priv;
3133 * in IBSS mode we need to update the beacon timers too.
3134 * this will also reset the TSF if we call it with 0
3136 if (sc->opmode == NL80211_IFTYPE_ADHOC)
3137 ath5k_beacon_update_timers(sc, 0);
3139 ath5k_hw_reset_tsf(sc->ah);
3143 ath5k_beacon_update(struct ath5k_softc *sc, struct sk_buff *skb)
3145 unsigned long flags;
3148 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3150 spin_lock_irqsave(&sc->block, flags);
3151 ath5k_txbuf_free(sc, sc->bbuf);
3152 sc->bbuf->skb = skb;
3153 ret = ath5k_beacon_setup(sc, sc->bbuf);
3155 sc->bbuf->skb = NULL;
3156 spin_unlock_irqrestore(&sc->block, flags);
3158 ath5k_beacon_config(sc);
3165 set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3167 struct ath5k_softc *sc = hw->priv;
3168 struct ath5k_hw *ah = sc->ah;
3170 rfilt = ath5k_hw_get_rx_filter(ah);
3172 rfilt |= AR5K_RX_FILTER_BEACON;
3174 rfilt &= ~AR5K_RX_FILTER_BEACON;
3175 ath5k_hw_set_rx_filter(ah, rfilt);
3176 sc->filter_flags = rfilt;
3179 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3180 struct ieee80211_vif *vif,
3181 struct ieee80211_bss_conf *bss_conf,
3184 struct ath5k_softc *sc = hw->priv;
3185 if (changes & BSS_CHANGED_ASSOC) {
3186 mutex_lock(&sc->lock);
3187 sc->assoc = bss_conf->assoc;
3188 if (sc->opmode == NL80211_IFTYPE_STATION)
3189 set_beacon_filter(hw, sc->assoc);
3190 mutex_unlock(&sc->lock);
git://ftp.safe.ca / safe / jmp / linux-2.6 / blob