SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/ath5k/base.c

   1 /*-
   2  * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
   3  * Copyright (c) 2004-2005 Atheros Communications, Inc.
   4  * Copyright (c) 2006 Devicescape Software, Inc.
   5  * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
   6  * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
   7  *
   8  * All rights reserved.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer,
  15  *    without modification.
  16  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  17  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
  18  *    redistribution must be conditioned upon including a substantially
  19  *    similar Disclaimer requirement for further binary redistribution.
  20  * 3. Neither the names of the above-listed copyright holders nor the names
  21  *    of any contributors may be used to endorse or promote products derived
  22  *    from this software without specific prior written permission.
  23  *
  24  * Alternatively, this software may be distributed under the terms of the
  25  * GNU General Public License ("GPL") version 2 as published by the Free
  26  * Software Foundation.
  27  *
  28  * NO WARRANTY
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
  32  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
  33  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
  34  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  35  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  36  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
  37  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  38  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  39  * THE POSSIBILITY OF SUCH DAMAGES.
  40  *
  41  */
  42
  43 #include <linux/module.h>
  44 #include <linux/delay.h>
  45 #include <linux/hardirq.h>
  46 #include <linux/if.h>
  47 #include <linux/io.h>
  48 #include <linux/netdevice.h>
  49 #include <linux/cache.h>
  50 #include <linux/pci.h>
  51 #include <linux/ethtool.h>
  52 #include <linux/uaccess.h>
  53
  54 #include <net/ieee80211_radiotap.h>
  55
  56 #include <asm/unaligned.h>
  57
  58 #include "base.h"
  59 #include "reg.h"
  60 #include "debug.h"
  61
  62 static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
  63
  64
  65 /******************\
  66 * Internal defines *
  67 \******************/
  68
  69 /* Module info */
  70 MODULE_AUTHOR("Jiri Slaby");
  71 MODULE_AUTHOR("Nick Kossifidis");
  72 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
  73 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
  74 MODULE_LICENSE("Dual BSD/GPL");
  75 MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
  76
  77
  78 /* Known PCI ids */
  79 static struct pci_device_id ath5k_pci_id_table[] __devinitdata = {
  80         { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
  81         { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
  82         { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
  83         { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
  84         { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
  85         { PCI_VDEVICE(3COM_2,  0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
  86         { PCI_VDEVICE(3COM,    0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
  87         { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
  88         { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
  89         { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
  90         { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
  91         { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
  92         { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
  93         { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
  94         { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
  95         { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
  96         { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* PCI-E cards */
  97         { PCI_VDEVICE(ATHEROS, 0x001d), .driver_data = AR5K_AR5212 }, /* 2417 Nala */
  98         { 0 }
  99 };
 100 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
 101
 102 /* Known SREVs */
 103 static struct ath5k_srev_name srev_names[] = {
 104         { "5210",       AR5K_VERSION_MAC,       AR5K_SREV_AR5210 },
 105         { "5311",       AR5K_VERSION_MAC,       AR5K_SREV_AR5311 },
 106         { "5311A",      AR5K_VERSION_MAC,       AR5K_SREV_AR5311A },
 107         { "5311B",      AR5K_VERSION_MAC,       AR5K_SREV_AR5311B },
 108         { "5211",       AR5K_VERSION_MAC,       AR5K_SREV_AR5211 },
 109         { "5212",       AR5K_VERSION_MAC,       AR5K_SREV_AR5212 },
 110         { "5213",       AR5K_VERSION_MAC,       AR5K_SREV_AR5213 },
 111         { "5213A",      AR5K_VERSION_MAC,       AR5K_SREV_AR5213A },
 112         { "2413",       AR5K_VERSION_MAC,       AR5K_SREV_AR2413 },
 113         { "2414",       AR5K_VERSION_MAC,       AR5K_SREV_AR2414 },
 114         { "5424",       AR5K_VERSION_MAC,       AR5K_SREV_AR5424 },
 115         { "5413",       AR5K_VERSION_MAC,       AR5K_SREV_AR5413 },
 116         { "5414",       AR5K_VERSION_MAC,       AR5K_SREV_AR5414 },
 117         { "2415",       AR5K_VERSION_MAC,       AR5K_SREV_AR2415 },
 118         { "5416",       AR5K_VERSION_MAC,       AR5K_SREV_AR5416 },
 119         { "5418",       AR5K_VERSION_MAC,       AR5K_SREV_AR5418 },
 120         { "2425",       AR5K_VERSION_MAC,       AR5K_SREV_AR2425 },
 121         { "2417",       AR5K_VERSION_MAC,       AR5K_SREV_AR2417 },
 122         { "xxxxx",      AR5K_VERSION_MAC,       AR5K_SREV_UNKNOWN },
 123         { "5110",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5110 },
 124         { "5111",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5111 },
 125         { "5111A",      AR5K_VERSION_RAD,       AR5K_SREV_RAD_5111A },
 126         { "2111",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2111 },
 127         { "5112",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5112 },
 128         { "5112A",      AR5K_VERSION_RAD,       AR5K_SREV_RAD_5112A },
 129         { "5112B",      AR5K_VERSION_RAD,       AR5K_SREV_RAD_5112B },
 130         { "2112",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2112 },
 131         { "2112A",      AR5K_VERSION_RAD,       AR5K_SREV_RAD_2112A },
 132         { "2112B",      AR5K_VERSION_RAD,       AR5K_SREV_RAD_2112B },
 133         { "2413",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2413 },
 134         { "5413",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5413 },
 135         { "2316",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2316 },
 136         { "2317",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_2317 },
 137         { "5424",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5424 },
 138         { "5133",       AR5K_VERSION_RAD,       AR5K_SREV_RAD_5133 },
 139         { "xxxxx",      AR5K_VERSION_RAD,       AR5K_SREV_UNKNOWN },
 140 };
 141
 142 static struct ieee80211_rate ath5k_rates[] = {
 143         { .bitrate = 10,
 144           .hw_value = ATH5K_RATE_CODE_1M, },
 145         { .bitrate = 20,
 146           .hw_value = ATH5K_RATE_CODE_2M,
 147           .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
 148           .flags = IEEE80211_RATE_SHORT_PREAMBLE },
 149         { .bitrate = 55,
 150           .hw_value = ATH5K_RATE_CODE_5_5M,
 151           .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
 152           .flags = IEEE80211_RATE_SHORT_PREAMBLE },
 153         { .bitrate = 110,
 154           .hw_value = ATH5K_RATE_CODE_11M,
 155           .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
 156           .flags = IEEE80211_RATE_SHORT_PREAMBLE },
 157         { .bitrate = 60,
 158           .hw_value = ATH5K_RATE_CODE_6M,
 159           .flags = 0 },
 160         { .bitrate = 90,
 161           .hw_value = ATH5K_RATE_CODE_9M,
 162           .flags = 0 },
 163         { .bitrate = 120,
 164           .hw_value = ATH5K_RATE_CODE_12M,
 165           .flags = 0 },
 166         { .bitrate = 180,
 167           .hw_value = ATH5K_RATE_CODE_18M,
 168           .flags = 0 },
 169         { .bitrate = 240,
 170           .hw_value = ATH5K_RATE_CODE_24M,
 171           .flags = 0 },
 172         { .bitrate = 360,
 173           .hw_value = ATH5K_RATE_CODE_36M,
 174           .flags = 0 },
 175         { .bitrate = 480,
 176           .hw_value = ATH5K_RATE_CODE_48M,
 177           .flags = 0 },
 178         { .bitrate = 540,
 179           .hw_value = ATH5K_RATE_CODE_54M,
 180           .flags = 0 },
 181         /* XR missing */
 182 };
 183
 184 /*
 185  * Prototypes - PCI stack related functions
 186  */
 187 static int __devinit    ath5k_pci_probe(struct pci_dev *pdev,
 188                                 const struct pci_device_id *id);
 189 static void __devexit   ath5k_pci_remove(struct pci_dev *pdev);
 190 #ifdef CONFIG_PM
 191 static int              ath5k_pci_suspend(struct pci_dev *pdev,
 192                                         pm_message_t state);
 193 static int              ath5k_pci_resume(struct pci_dev *pdev);
 194 #else
 195 #define ath5k_pci_suspend NULL
 196 #define ath5k_pci_resume NULL
 197 #endif /* CONFIG_PM */
 198
 199 static struct pci_driver ath5k_pci_driver = {
 200         .name           = "ath5k_pci",
 201         .id_table       = ath5k_pci_id_table,
 202         .probe          = ath5k_pci_probe,
 203         .remove         = __devexit_p(ath5k_pci_remove),
 204         .suspend        = ath5k_pci_suspend,
 205         .resume         = ath5k_pci_resume,
 206 };
 207
 208
 209
 210 /*
 211  * Prototypes - MAC 802.11 stack related functions
 212  */
 213 static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
 214 static int ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel);
 215 static int ath5k_reset_wake(struct ath5k_softc *sc);
 216 static int ath5k_start(struct ieee80211_hw *hw);
 217 static void ath5k_stop(struct ieee80211_hw *hw);
 218 static int ath5k_add_interface(struct ieee80211_hw *hw,
 219                 struct ieee80211_if_init_conf *conf);
 220 static void ath5k_remove_interface(struct ieee80211_hw *hw,
 221                 struct ieee80211_if_init_conf *conf);
 222 static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
 223 static int ath5k_config_interface(struct ieee80211_hw *hw,
 224                 struct ieee80211_vif *vif,
 225                 struct ieee80211_if_conf *conf);
 226 static void ath5k_configure_filter(struct ieee80211_hw *hw,
 227                 unsigned int changed_flags,
 228                 unsigned int *new_flags,
 229                 int mc_count, struct dev_mc_list *mclist);
 230 static int ath5k_set_key(struct ieee80211_hw *hw,
 231                 enum set_key_cmd cmd,
 232                 const u8 *local_addr, const u8 *addr,
 233                 struct ieee80211_key_conf *key);
 234 static int ath5k_get_stats(struct ieee80211_hw *hw,
 235                 struct ieee80211_low_level_stats *stats);
 236 static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
 237                 struct ieee80211_tx_queue_stats *stats);
 238 static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
 239 static void ath5k_reset_tsf(struct ieee80211_hw *hw);
 240 static int ath5k_beacon_update(struct ath5k_softc *sc, struct sk_buff *skb);
 241
 242 static struct ieee80211_ops ath5k_hw_ops = {
 243         .tx             = ath5k_tx,
 244         .start          = ath5k_start,
 245         .stop           = ath5k_stop,
 246         .add_interface  = ath5k_add_interface,
 247         .remove_interface = ath5k_remove_interface,
 248         .config         = ath5k_config,
 249         .config_interface = ath5k_config_interface,
 250         .configure_filter = ath5k_configure_filter,
 251         .set_key        = ath5k_set_key,
 252         .get_stats      = ath5k_get_stats,
 253         .conf_tx        = NULL,
 254         .get_tx_stats   = ath5k_get_tx_stats,
 255         .get_tsf        = ath5k_get_tsf,
 256         .reset_tsf      = ath5k_reset_tsf,
 257 };
 258
 259 /*
 260  * Prototypes - Internal functions
 261  */
 262 /* Attach detach */
 263 static int      ath5k_attach(struct pci_dev *pdev,
 264                         struct ieee80211_hw *hw);
 265 static void     ath5k_detach(struct pci_dev *pdev,
 266                         struct ieee80211_hw *hw);
 267 /* Channel/mode setup */
 268 static inline short ath5k_ieee2mhz(short chan);
 269 static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
 270                                 struct ieee80211_channel *channels,
 271                                 unsigned int mode,
 272                                 unsigned int max);
 273 static int      ath5k_setup_bands(struct ieee80211_hw *hw);
 274 static int      ath5k_chan_set(struct ath5k_softc *sc,
 275                                 struct ieee80211_channel *chan);
 276 static void     ath5k_setcurmode(struct ath5k_softc *sc,
 277                                 unsigned int mode);
 278 static void     ath5k_mode_setup(struct ath5k_softc *sc);
 279
 280 /* Descriptor setup */
 281 static int      ath5k_desc_alloc(struct ath5k_softc *sc,
 282                                 struct pci_dev *pdev);
 283 static void     ath5k_desc_free(struct ath5k_softc *sc,
 284                                 struct pci_dev *pdev);
 285 /* Buffers setup */
 286 static int      ath5k_rxbuf_setup(struct ath5k_softc *sc,
 287                                 struct ath5k_buf *bf);
 288 static int      ath5k_txbuf_setup(struct ath5k_softc *sc,
 289                                 struct ath5k_buf *bf);
 290 static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
 291                                 struct ath5k_buf *bf)
 292 {
 293         BUG_ON(!bf);
 294         if (!bf->skb)
 295                 return;
 296         pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
 297                         PCI_DMA_TODEVICE);
 298         dev_kfree_skb_any(bf->skb);
 299         bf->skb = NULL;
 300 }
 301
 302 /* Queues setup */
 303 static struct   ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
 304                                 int qtype, int subtype);
 305 static int      ath5k_beaconq_setup(struct ath5k_hw *ah);
 306 static int      ath5k_beaconq_config(struct ath5k_softc *sc);
 307 static void     ath5k_txq_drainq(struct ath5k_softc *sc,
 308                                 struct ath5k_txq *txq);
 309 static void     ath5k_txq_cleanup(struct ath5k_softc *sc);
 310 static void     ath5k_txq_release(struct ath5k_softc *sc);
 311 /* Rx handling */
 312 static int      ath5k_rx_start(struct ath5k_softc *sc);
 313 static void     ath5k_rx_stop(struct ath5k_softc *sc);
 314 static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
 315                                         struct ath5k_desc *ds,
 316                                         struct sk_buff *skb,
 317                                         struct ath5k_rx_status *rs);
 318 static void     ath5k_tasklet_rx(unsigned long data);
 319 /* Tx handling */
 320 static void     ath5k_tx_processq(struct ath5k_softc *sc,
 321                                 struct ath5k_txq *txq);
 322 static void     ath5k_tasklet_tx(unsigned long data);
 323 /* Beacon handling */
 324 static int      ath5k_beacon_setup(struct ath5k_softc *sc,
 325                                         struct ath5k_buf *bf);
 326 static void     ath5k_beacon_send(struct ath5k_softc *sc);
 327 static void     ath5k_beacon_config(struct ath5k_softc *sc);
 328 static void     ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
 329
 330 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
 331 {
 332         u64 tsf = ath5k_hw_get_tsf64(ah);
 333
 334         if ((tsf & 0x7fff) < rstamp)
 335                 tsf -= 0x8000;
 336
 337         return (tsf & ~0x7fff) | rstamp;
 338 }
 339
 340 /* Interrupt handling */
 341 static int      ath5k_init(struct ath5k_softc *sc, bool is_resume);
 342 static int      ath5k_stop_locked(struct ath5k_softc *sc);
 343 static int      ath5k_stop_hw(struct ath5k_softc *sc, bool is_suspend);
 344 static irqreturn_t ath5k_intr(int irq, void *dev_id);
 345 static void     ath5k_tasklet_reset(unsigned long data);
 346
 347 static void     ath5k_calibrate(unsigned long data);
 348 /* LED functions */
 349 static int      ath5k_init_leds(struct ath5k_softc *sc);
 350 static void     ath5k_led_enable(struct ath5k_softc *sc);
 351 static void     ath5k_led_off(struct ath5k_softc *sc);
 352 static void     ath5k_unregister_leds(struct ath5k_softc *sc);
 353
 354 /*
 355  * Module init/exit functions
 356  */
 357 static int __init
 358 init_ath5k_pci(void)
 359 {
 360         int ret;
 361
 362         ath5k_debug_init();
 363
 364         ret = pci_register_driver(&ath5k_pci_driver);
 365         if (ret) {
 366                 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
 367                 return ret;
 368         }
 369
 370         return 0;
 371 }
 372
 373 static void __exit
 374 exit_ath5k_pci(void)
 375 {
 376         pci_unregister_driver(&ath5k_pci_driver);
 377
 378         ath5k_debug_finish();
 379 }
 380
 381 module_init(init_ath5k_pci);
 382 module_exit(exit_ath5k_pci);
 383
 384
 385 /********************\
 386 * PCI Initialization *
 387 \********************/
 388
 389 static const char *
 390 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
 391 {
 392         const char *name = "xxxxx";
 393         unsigned int i;
 394
 395         for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
 396                 if (srev_names[i].sr_type != type)
 397                         continue;
 398
 399                 if ((val & 0xf0) == srev_names[i].sr_val)
 400                         name = srev_names[i].sr_name;
 401
 402                 if ((val & 0xff) == srev_names[i].sr_val) {
 403                         name = srev_names[i].sr_name;
 404                         break;
 405                 }
 406         }
 407
 408         return name;
 409 }
 410
 411 static int __devinit
 412 ath5k_pci_probe(struct pci_dev *pdev,
 413                 const struct pci_device_id *id)
 414 {
 415         void __iomem *mem;
 416         struct ath5k_softc *sc;
 417         struct ieee80211_hw *hw;
 418         int ret;
 419         u8 csz;
 420
 421         ret = pci_enable_device(pdev);
 422         if (ret) {
 423                 dev_err(&pdev->dev, "can't enable device\n");
 424                 goto err;
 425         }
 426
 427         /* XXX 32-bit addressing only */
 428         ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
 429         if (ret) {
 430                 dev_err(&pdev->dev, "32-bit DMA not available\n");
 431                 goto err_dis;
 432         }
 433
 434         /*
 435          * Cache line size is used to size and align various
 436          * structures used to communicate with the hardware.
 437          */
 438         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
 439         if (csz == 0) {
 440                 /*
 441                  * Linux 2.4.18 (at least) writes the cache line size
 442                  * register as a 16-bit wide register which is wrong.
 443                  * We must have this setup properly for rx buffer
 444                  * DMA to work so force a reasonable value here if it
 445                  * comes up zero.
 446                  */
 447                 csz = L1_CACHE_BYTES / sizeof(u32);
 448                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
 449         }
 450         /*
 451          * The default setting of latency timer yields poor results,
 452          * set it to the value used by other systems.  It may be worth
 453          * tweaking this setting more.
 454          */
 455         pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
 456
 457         /* Enable bus mastering */
 458         pci_set_master(pdev);
 459
 460         /*
 461          * Disable the RETRY_TIMEOUT register (0x41) to keep
 462          * PCI Tx retries from interfering with C3 CPU state.
 463          */
 464         pci_write_config_byte(pdev, 0x41, 0);
 465
 466         ret = pci_request_region(pdev, 0, "ath5k");
 467         if (ret) {
 468                 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
 469                 goto err_dis;
 470         }
 471
 472         mem = pci_iomap(pdev, 0, 0);
 473         if (!mem) {
 474                 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
 475                 ret = -EIO;
 476                 goto err_reg;
 477         }
 478
 479         /*
 480          * Allocate hw (mac80211 main struct)
 481          * and hw->priv (driver private data)
 482          */
 483         hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
 484         if (hw == NULL) {
 485                 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
 486                 ret = -ENOMEM;
 487                 goto err_map;
 488         }
 489
 490         dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
 491
 492         /* Initialize driver private data */
 493         SET_IEEE80211_DEV(hw, &pdev->dev);
 494         hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
 495                     IEEE80211_HW_SIGNAL_DBM |
 496                     IEEE80211_HW_NOISE_DBM;
 497
 498         hw->wiphy->interface_modes =
 499                 BIT(NL80211_IFTYPE_STATION) |
 500                 BIT(NL80211_IFTYPE_ADHOC) |
 501                 BIT(NL80211_IFTYPE_MESH_POINT);
 502
 503         hw->extra_tx_headroom = 2;
 504         hw->channel_change_time = 5000;
 505         sc = hw->priv;
 506         sc->hw = hw;
 507         sc->pdev = pdev;
 508
 509         ath5k_debug_init_device(sc);
 510
 511         /*
 512          * Mark the device as detached to avoid processing
 513          * interrupts until setup is complete.
 514          */
 515         __set_bit(ATH_STAT_INVALID, sc->status);
 516
 517         sc->iobase = mem; /* So we can unmap it on detach */
 518         sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
 519         sc->opmode = NL80211_IFTYPE_STATION;
 520         mutex_init(&sc->lock);
 521         spin_lock_init(&sc->rxbuflock);
 522         spin_lock_init(&sc->txbuflock);
 523         spin_lock_init(&sc->block);
 524
 525         /* Set private data */
 526         pci_set_drvdata(pdev, hw);
 527
 528         /* Setup interrupt handler */
 529         ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
 530         if (ret) {
 531                 ATH5K_ERR(sc, "request_irq failed\n");
 532                 goto err_free;
 533         }
 534
 535         /* Initialize device */
 536         sc->ah = ath5k_hw_attach(sc, id->driver_data);
 537         if (IS_ERR(sc->ah)) {
 538                 ret = PTR_ERR(sc->ah);
 539                 goto err_irq;
 540         }
 541
 542         /* set up multi-rate retry capabilities */
 543         if (sc->ah->ah_version == AR5K_AR5212) {
 544                 hw->max_altrates = 3;
 545                 hw->max_altrate_tries = 11;
 546         }
 547
 548         /* Finish private driver data initialization */
 549         ret = ath5k_attach(pdev, hw);
 550         if (ret)
 551                 goto err_ah;
 552
 553         ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
 554                         ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
 555                                         sc->ah->ah_mac_srev,
 556                                         sc->ah->ah_phy_revision);
 557
 558         if (!sc->ah->ah_single_chip) {
 559                 /* Single chip radio (!RF5111) */
 560                 if (sc->ah->ah_radio_5ghz_revision &&
 561                         !sc->ah->ah_radio_2ghz_revision) {
 562                         /* No 5GHz support -> report 2GHz radio */
 563                         if (!test_bit(AR5K_MODE_11A,
 564                                 sc->ah->ah_capabilities.cap_mode)) {
 565                                 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
 566                                         ath5k_chip_name(AR5K_VERSION_RAD,
 567                                                 sc->ah->ah_radio_5ghz_revision),
 568                                                 sc->ah->ah_radio_5ghz_revision);
 569                         /* No 2GHz support (5110 and some
 570                          * 5Ghz only cards) -> report 5Ghz radio */
 571                         } else if (!test_bit(AR5K_MODE_11B,
 572                                 sc->ah->ah_capabilities.cap_mode)) {
 573                                 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
 574                                         ath5k_chip_name(AR5K_VERSION_RAD,
 575                                                 sc->ah->ah_radio_5ghz_revision),
 576                                                 sc->ah->ah_radio_5ghz_revision);
 577                         /* Multiband radio */
 578                         } else {
 579                                 ATH5K_INFO(sc, "RF%s multiband radio found"
 580                                         " (0x%x)\n",
 581                                         ath5k_chip_name(AR5K_VERSION_RAD,
 582                                                 sc->ah->ah_radio_5ghz_revision),
 583                                                 sc->ah->ah_radio_5ghz_revision);
 584                         }
 585                 }
 586                 /* Multi chip radio (RF5111 - RF2111) ->
 587                  * report both 2GHz/5GHz radios */
 588                 else if (sc->ah->ah_radio_5ghz_revision &&
 589                                 sc->ah->ah_radio_2ghz_revision){
 590                         ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
 591                                 ath5k_chip_name(AR5K_VERSION_RAD,
 592                                         sc->ah->ah_radio_5ghz_revision),
 593                                         sc->ah->ah_radio_5ghz_revision);
 594                         ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
 595                                 ath5k_chip_name(AR5K_VERSION_RAD,
 596                                         sc->ah->ah_radio_2ghz_revision),
 597                                         sc->ah->ah_radio_2ghz_revision);
 598                 }
 599         }
 600
 601
 602         /* ready to process interrupts */
 603         __clear_bit(ATH_STAT_INVALID, sc->status);
 604
 605         return 0;
 606 err_ah:
 607         ath5k_hw_detach(sc->ah);
 608 err_irq:
 609         free_irq(pdev->irq, sc);
 610 err_free:
 611         ieee80211_free_hw(hw);
 612 err_map:
 613         pci_iounmap(pdev, mem);
 614 err_reg:
 615         pci_release_region(pdev, 0);
 616 err_dis:
 617         pci_disable_device(pdev);
 618 err:
 619         return ret;
 620 }
 621
 622 static void __devexit
 623 ath5k_pci_remove(struct pci_dev *pdev)
 624 {
 625         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
 626         struct ath5k_softc *sc = hw->priv;
 627
 628         ath5k_debug_finish_device(sc);
 629         ath5k_detach(pdev, hw);
 630         ath5k_hw_detach(sc->ah);
 631         free_irq(pdev->irq, sc);
 632         pci_iounmap(pdev, sc->iobase);
 633         pci_release_region(pdev, 0);
 634         pci_disable_device(pdev);
 635         ieee80211_free_hw(hw);
 636 }
 637
 638 #ifdef CONFIG_PM
 639 static int
 640 ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
 641 {
 642         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
 643         struct ath5k_softc *sc = hw->priv;
 644
 645         ath5k_led_off(sc);
 646
 647         ath5k_stop_hw(sc, true);
 648
 649         free_irq(pdev->irq, sc);
 650         pci_save_state(pdev);
 651         pci_disable_device(pdev);
 652         pci_set_power_state(pdev, PCI_D3hot);
 653
 654         return 0;
 655 }
 656
 657 static int
 658 ath5k_pci_resume(struct pci_dev *pdev)
 659 {
 660         struct ieee80211_hw *hw = pci_get_drvdata(pdev);
 661         struct ath5k_softc *sc = hw->priv;
 662         int err;
 663
 664         pci_restore_state(pdev);
 665
 666         err = pci_enable_device(pdev);
 667         if (err)
 668                 return err;
 669
 670         /*
 671          * Suspend/Resume resets the PCI configuration space, so we have to
 672          * re-disable the RETRY_TIMEOUT register (0x41) to keep
 673          * PCI Tx retries from interfering with C3 CPU state
 674          */
 675         pci_write_config_byte(pdev, 0x41, 0);
 676
 677         err = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
 678         if (err) {
 679                 ATH5K_ERR(sc, "request_irq failed\n");
 680                 goto err_no_irq;
 681         }
 682
 683         err = ath5k_init(sc, true);
 684         if (err)
 685                 goto err_irq;
 686         ath5k_led_enable(sc);
 687
 688         return 0;
 689 err_irq:
 690         free_irq(pdev->irq, sc);
 691 err_no_irq:
 692         pci_disable_device(pdev);
 693         return err;
 694 }
 695 #endif /* CONFIG_PM */
 696
 697
 698 /***********************\
 699 * Driver Initialization *
 700 \***********************/
 701
 702 static int
 703 ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
 704 {
 705         struct ath5k_softc *sc = hw->priv;
 706         struct ath5k_hw *ah = sc->ah;
 707         u8 mac[ETH_ALEN];
 708         int ret;
 709
 710         ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
 711
 712         /*
 713          * Check if the MAC has multi-rate retry support.
 714          * We do this by trying to setup a fake extended
 715          * descriptor.  MAC's that don't have support will
 716          * return false w/o doing anything.  MAC's that do
 717          * support it will return true w/o doing anything.
 718          */
 719         ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
 720         if (ret < 0)
 721                 goto err;
 722         if (ret > 0)
 723                 __set_bit(ATH_STAT_MRRETRY, sc->status);
 724
 725         /*
 726          * Collect the channel list.  The 802.11 layer
 727          * is resposible for filtering this list based
 728          * on settings like the phy mode and regulatory
 729          * domain restrictions.
 730          */
 731         ret = ath5k_setup_bands(hw);
 732         if (ret) {
 733                 ATH5K_ERR(sc, "can't get channels\n");
 734                 goto err;
 735         }
 736
 737         /* NB: setup here so ath5k_rate_update is happy */
 738         if (test_bit(AR5K_MODE_11A, ah->ah_modes))
 739                 ath5k_setcurmode(sc, AR5K_MODE_11A);
 740         else
 741                 ath5k_setcurmode(sc, AR5K_MODE_11B);
 742
 743         /*
 744          * Allocate tx+rx descriptors and populate the lists.
 745          */
 746         ret = ath5k_desc_alloc(sc, pdev);
 747         if (ret) {
 748                 ATH5K_ERR(sc, "can't allocate descriptors\n");
 749                 goto err;
 750         }
 751
 752         /*
 753          * Allocate hardware transmit queues: one queue for
 754          * beacon frames and one data queue for each QoS
 755          * priority.  Note that hw functions handle reseting
 756          * these queues at the needed time.
 757          */
 758         ret = ath5k_beaconq_setup(ah);
 759         if (ret < 0) {
 760                 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
 761                 goto err_desc;
 762         }
 763         sc->bhalq = ret;
 764
 765         sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
 766         if (IS_ERR(sc->txq)) {
 767                 ATH5K_ERR(sc, "can't setup xmit queue\n");
 768                 ret = PTR_ERR(sc->txq);
 769                 goto err_bhal;
 770         }
 771
 772         tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
 773         tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
 774         tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
 775         setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
 776
 777         ath5k_hw_get_lladdr(ah, mac);
 778         SET_IEEE80211_PERM_ADDR(hw, mac);
 779         /* All MAC address bits matter for ACKs */
 780         memset(sc->bssidmask, 0xff, ETH_ALEN);
 781         ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
 782
 783         ret = ieee80211_register_hw(hw);
 784         if (ret) {
 785                 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
 786                 goto err_queues;
 787         }
 788
 789         ath5k_init_leds(sc);
 790
 791         return 0;
 792 err_queues:
 793         ath5k_txq_release(sc);
 794 err_bhal:
 795         ath5k_hw_release_tx_queue(ah, sc->bhalq);
 796 err_desc:
 797         ath5k_desc_free(sc, pdev);
 798 err:
 799         return ret;
 800 }
 801
 802 static void
 803 ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
 804 {
 805         struct ath5k_softc *sc = hw->priv;
 806
 807         /*
 808          * NB: the order of these is important:
 809          * o call the 802.11 layer before detaching ath5k_hw to
 810          *   insure callbacks into the driver to delete global
 811          *   key cache entries can be handled
 812          * o reclaim the tx queue data structures after calling
 813          *   the 802.11 layer as we'll get called back to reclaim
 814          *   node state and potentially want to use them
 815          * o to cleanup the tx queues the hal is called, so detach
 816          *   it last
 817          * XXX: ??? detach ath5k_hw ???
 818          * Other than that, it's straightforward...
 819          */
 820         ieee80211_unregister_hw(hw);
 821         ath5k_desc_free(sc, pdev);
 822         ath5k_txq_release(sc);
 823         ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
 824         ath5k_unregister_leds(sc);
 825
 826         /*
 827          * NB: can't reclaim these until after ieee80211_ifdetach
 828          * returns because we'll get called back to reclaim node
 829          * state and potentially want to use them.
 830          */
 831 }
 832
 833
 834
 835
 836 /********************\
 837 * Channel/mode setup *
 838 \********************/
 839
 840 /*
 841  * Convert IEEE channel number to MHz frequency.
 842  */
 843 static inline short
 844 ath5k_ieee2mhz(short chan)
 845 {
 846         if (chan <= 14 || chan >= 27)
 847                 return ieee80211chan2mhz(chan);
 848         else
 849                 return 2212 + chan * 20;
 850 }
 851
 852 static unsigned int
 853 ath5k_copy_channels(struct ath5k_hw *ah,
 854                 struct ieee80211_channel *channels,
 855                 unsigned int mode,
 856                 unsigned int max)
 857 {
 858         unsigned int i, count, size, chfreq, freq, ch;
 859
 860         if (!test_bit(mode, ah->ah_modes))
 861                 return 0;
 862
 863         switch (mode) {
 864         case AR5K_MODE_11A:
 865         case AR5K_MODE_11A_TURBO:
 866                 /* 1..220, but 2GHz frequencies are filtered by check_channel */
 867                 size = 220 ;
 868                 chfreq = CHANNEL_5GHZ;
 869                 break;
 870         case AR5K_MODE_11B:
 871         case AR5K_MODE_11G:
 872         case AR5K_MODE_11G_TURBO:
 873                 size = 26;
 874                 chfreq = CHANNEL_2GHZ;
 875                 break;
 876         default:
 877                 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
 878                 return 0;
 879         }
 880
 881         for (i = 0, count = 0; i < size && max > 0; i++) {
 882                 ch = i + 1 ;
 883                 freq = ath5k_ieee2mhz(ch);
 884
 885                 /* Check if channel is supported by the chipset */
 886                 if (!ath5k_channel_ok(ah, freq, chfreq))
 887                         continue;
 888
 889                 /* Write channel info and increment counter */
 890                 channels[count].center_freq = freq;
 891                 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
 892                         IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
 893                 switch (mode) {
 894                 case AR5K_MODE_11A:
 895                 case AR5K_MODE_11G:
 896                         channels[count].hw_value = chfreq | CHANNEL_OFDM;
 897                         break;
 898                 case AR5K_MODE_11A_TURBO:
 899                 case AR5K_MODE_11G_TURBO:
 900                         channels[count].hw_value = chfreq |
 901                                 CHANNEL_OFDM | CHANNEL_TURBO;
 902                         break;
 903                 case AR5K_MODE_11B:
 904                         channels[count].hw_value = CHANNEL_B;
 905                 }
 906
 907                 count++;
 908                 max--;
 909         }
 910
 911         return count;
 912 }
 913
 914 static void
 915 ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
 916 {
 917         u8 i;
 918
 919         for (i = 0; i < AR5K_MAX_RATES; i++)
 920                 sc->rate_idx[b->band][i] = -1;
 921
 922         for (i = 0; i < b->n_bitrates; i++) {
 923                 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
 924                 if (b->bitrates[i].hw_value_short)
 925                         sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
 926         }
 927 }
 928
 929 static int
 930 ath5k_setup_bands(struct ieee80211_hw *hw)
 931 {
 932         struct ath5k_softc *sc = hw->priv;
 933         struct ath5k_hw *ah = sc->ah;
 934         struct ieee80211_supported_band *sband;
 935         int max_c, count_c = 0;
 936         int i;
 937
 938         BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
 939         max_c = ARRAY_SIZE(sc->channels);
 940
 941         /* 2GHz band */
 942         sband = &sc->sbands[IEEE80211_BAND_2GHZ];
 943         sband->band = IEEE80211_BAND_2GHZ;
 944         sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
 945
 946         if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
 947                 /* G mode */
 948                 memcpy(sband->bitrates, &ath5k_rates[0],
 949                        sizeof(struct ieee80211_rate) * 12);
 950                 sband->n_bitrates = 12;
 951
 952                 sband->channels = sc->channels;
 953                 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
 954                                         AR5K_MODE_11G, max_c);
 955
 956                 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
 957                 count_c = sband->n_channels;
 958                 max_c -= count_c;
 959         } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
 960                 /* B mode */
 961                 memcpy(sband->bitrates, &ath5k_rates[0],
 962                        sizeof(struct ieee80211_rate) * 4);
 963                 sband->n_bitrates = 4;
 964
 965                 /* 5211 only supports B rates and uses 4bit rate codes
 966                  * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
 967                  * fix them up here:
 968                  */
 969                 if (ah->ah_version == AR5K_AR5211) {
 970                         for (i = 0; i < 4; i++) {
 971                                 sband->bitrates[i].hw_value =
 972                                         sband->bitrates[i].hw_value & 0xF;
 973                                 sband->bitrates[i].hw_value_short =
 974                                         sband->bitrates[i].hw_value_short & 0xF;
 975                         }
 976                 }
 977
 978                 sband->channels = sc->channels;
 979                 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
 980                                         AR5K_MODE_11B, max_c);
 981
 982                 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
 983                 count_c = sband->n_channels;
 984                 max_c -= count_c;
 985         }
 986         ath5k_setup_rate_idx(sc, sband);
 987
 988         /* 5GHz band, A mode */
 989         if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
 990                 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
 991                 sband->band = IEEE80211_BAND_5GHZ;
 992                 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
 993
 994                 memcpy(sband->bitrates, &ath5k_rates[4],
 995                        sizeof(struct ieee80211_rate) * 8);
 996                 sband->n_bitrates = 8;
 997
 998                 sband->channels = &sc->channels[count_c];
 999                 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1000                                         AR5K_MODE_11A, max_c);
1001
1002                 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1003         }
1004         ath5k_setup_rate_idx(sc, sband);
1005
1006         ath5k_debug_dump_bands(sc);
1007
1008         return 0;
1009 }
1010
1011 /*
1012  * Set/change channels.  If the channel is really being changed,
1013  * it's done by reseting the chip.  To accomplish this we must
1014  * first cleanup any pending DMA, then restart stuff after a la
1015  * ath5k_init.
1016  */
1017 static int
1018 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1019 {
1020         ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1021                 sc->curchan->center_freq, chan->center_freq);
1022
1023         if (chan->center_freq != sc->curchan->center_freq ||
1024                 chan->hw_value != sc->curchan->hw_value) {
1025
1026                 sc->curchan = chan;
1027                 sc->curband = &sc->sbands[chan->band];
1028
1029                 /*
1030                  * To switch channels clear any pending DMA operations;
1031                  * wait long enough for the RX fifo to drain, reset the
1032                  * hardware at the new frequency, and then re-enable
1033                  * the relevant bits of the h/w.
1034                  */
1035                 return ath5k_reset(sc, true, true);
1036         }
1037
1038         return 0;
1039 }
1040
1041 static void
1042 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1043 {
1044         sc->curmode = mode;
1045
1046         if (mode == AR5K_MODE_11A) {
1047                 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1048         } else {
1049                 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1050         }
1051 }
1052
1053 static void
1054 ath5k_mode_setup(struct ath5k_softc *sc)
1055 {
1056         struct ath5k_hw *ah = sc->ah;
1057         u32 rfilt;
1058
1059         /* configure rx filter */
1060         rfilt = sc->filter_flags;
1061         ath5k_hw_set_rx_filter(ah, rfilt);
1062
1063         if (ath5k_hw_hasbssidmask(ah))
1064                 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1065
1066         /* configure operational mode */
1067         ath5k_hw_set_opmode(ah);
1068
1069         ath5k_hw_set_mcast_filter(ah, 0, 0);
1070         ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1071 }
1072
1073 static inline int
1074 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1075 {
1076         WARN_ON(hw_rix < 0 || hw_rix > AR5K_MAX_RATES);
1077         return sc->rate_idx[sc->curband->band][hw_rix];
1078 }
1079
1080 /***************\
1081 * Buffers setup *
1082 \***************/
1083
1084 static int
1085 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1086 {
1087         struct ath5k_hw *ah = sc->ah;
1088         struct sk_buff *skb = bf->skb;
1089         struct ath5k_desc *ds;
1090
1091         if (likely(skb == NULL)) {
1092                 unsigned int off;
1093
1094                 /*
1095                  * Allocate buffer with headroom_needed space for the
1096                  * fake physical layer header at the start.
1097                  */
1098                 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1099                 if (unlikely(skb == NULL)) {
1100                         ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1101                                         sc->rxbufsize + sc->cachelsz - 1);
1102                         return -ENOMEM;
1103                 }
1104                 /*
1105                  * Cache-line-align.  This is important (for the
1106                  * 5210 at least) as not doing so causes bogus data
1107                  * in rx'd frames.
1108                  */
1109                 off = ((unsigned long)skb->data) % sc->cachelsz;
1110                 if (off != 0)
1111                         skb_reserve(skb, sc->cachelsz - off);
1112
1113                 bf->skb = skb;
1114                 bf->skbaddr = pci_map_single(sc->pdev,
1115                         skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1116                 if (unlikely(pci_dma_mapping_error(sc->pdev, bf->skbaddr))) {
1117                         ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1118                         dev_kfree_skb(skb);
1119                         bf->skb = NULL;
1120                         return -ENOMEM;
1121                 }
1122         }
1123
1124         /*
1125          * Setup descriptors.  For receive we always terminate
1126          * the descriptor list with a self-linked entry so we'll
1127          * not get overrun under high load (as can happen with a
1128          * 5212 when ANI processing enables PHY error frames).
1129          *
1130          * To insure the last descriptor is self-linked we create
1131          * each descriptor as self-linked and add it to the end.  As
1132          * each additional descriptor is added the previous self-linked
1133          * entry is ``fixed'' naturally.  This should be safe even
1134          * if DMA is happening.  When processing RX interrupts we
1135          * never remove/process the last, self-linked, entry on the
1136          * descriptor list.  This insures the hardware always has
1137          * someplace to write a new frame.
1138          */
1139         ds = bf->desc;
1140         ds->ds_link = bf->daddr;        /* link to self */
1141         ds->ds_data = bf->skbaddr;
1142         ah->ah_setup_rx_desc(ah, ds,
1143                 skb_tailroom(skb),      /* buffer size */
1144                 0);
1145
1146         if (sc->rxlink != NULL)
1147                 *sc->rxlink = bf->daddr;
1148         sc->rxlink = &ds->ds_link;
1149         return 0;
1150 }
1151
1152 static int
1153 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1154 {
1155         struct ath5k_hw *ah = sc->ah;
1156         struct ath5k_txq *txq = sc->txq;
1157         struct ath5k_desc *ds = bf->desc;
1158         struct sk_buff *skb = bf->skb;
1159         struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1160         unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1161         struct ieee80211_rate *rate;
1162         unsigned int mrr_rate[3], mrr_tries[3];
1163         int i, ret;
1164
1165         flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
1166
1167         /* XXX endianness */
1168         bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1169                         PCI_DMA_TODEVICE);
1170
1171         if (info->flags & IEEE80211_TX_CTL_NO_ACK)
1172                 flags |= AR5K_TXDESC_NOACK;
1173
1174         pktlen = skb->len;
1175
1176         if (info->control.hw_key) {
1177                 keyidx = info->control.hw_key->hw_key_idx;
1178                 pktlen += info->control.hw_key->icv_len;
1179         }
1180         ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1181                 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
1182                 (sc->power_level * 2),
1183                 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
1184                 info->control.retry_limit, keyidx, 0, flags, 0, 0);
1185         if (ret)
1186                 goto err_unmap;
1187
1188         memset(mrr_rate, 0, sizeof(mrr_rate));
1189         memset(mrr_tries, 0, sizeof(mrr_tries));
1190         for (i = 0; i < 3; i++) {
1191                 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1192                 if (!rate)
1193                         break;
1194
1195                 mrr_rate[i] = rate->hw_value;
1196                 mrr_tries[i] = info->control.retries[i].limit;
1197         }
1198
1199         ah->ah_setup_mrr_tx_desc(ah, ds,
1200                 mrr_rate[0], mrr_tries[0],
1201                 mrr_rate[1], mrr_tries[1],
1202                 mrr_rate[2], mrr_tries[2]);
1203
1204         ds->ds_link = 0;
1205         ds->ds_data = bf->skbaddr;
1206
1207         spin_lock_bh(&txq->lock);
1208         list_add_tail(&bf->list, &txq->q);
1209         sc->tx_stats[txq->qnum].len++;
1210         if (txq->link == NULL) /* is this first packet? */
1211                 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
1212         else /* no, so only link it */
1213                 *txq->link = bf->daddr;
1214
1215         txq->link = &ds->ds_link;
1216         ath5k_hw_start_tx_dma(ah, txq->qnum);
1217         mmiowb();
1218         spin_unlock_bh(&txq->lock);
1219
1220         return 0;
1221 err_unmap:
1222         pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1223         return ret;
1224 }
1225
1226 /*******************\
1227 * Descriptors setup *
1228 \*******************/
1229
1230 static int
1231 ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1232 {
1233         struct ath5k_desc *ds;
1234         struct ath5k_buf *bf;
1235         dma_addr_t da;
1236         unsigned int i;
1237         int ret;
1238
1239         /* allocate descriptors */
1240         sc->desc_len = sizeof(struct ath5k_desc) *
1241                         (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1242         sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1243         if (sc->desc == NULL) {
1244                 ATH5K_ERR(sc, "can't allocate descriptors\n");
1245                 ret = -ENOMEM;
1246                 goto err;
1247         }
1248         ds = sc->desc;
1249         da = sc->desc_daddr;
1250         ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1251                 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1252
1253         bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1254                         sizeof(struct ath5k_buf), GFP_KERNEL);
1255         if (bf == NULL) {
1256                 ATH5K_ERR(sc, "can't allocate bufptr\n");
1257                 ret = -ENOMEM;
1258                 goto err_free;
1259         }
1260         sc->bufptr = bf;
1261
1262         INIT_LIST_HEAD(&sc->rxbuf);
1263         for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1264                 bf->desc = ds;
1265                 bf->daddr = da;
1266                 list_add_tail(&bf->list, &sc->rxbuf);
1267         }
1268
1269         INIT_LIST_HEAD(&sc->txbuf);
1270         sc->txbuf_len = ATH_TXBUF;
1271         for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1272                         da += sizeof(*ds)) {
1273                 bf->desc = ds;
1274                 bf->daddr = da;
1275                 list_add_tail(&bf->list, &sc->txbuf);
1276         }
1277
1278         /* beacon buffer */
1279         bf->desc = ds;
1280         bf->daddr = da;
1281         sc->bbuf = bf;
1282
1283         return 0;
1284 err_free:
1285         pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1286 err:
1287         sc->desc = NULL;
1288         return ret;
1289 }
1290
1291 static void
1292 ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1293 {
1294         struct ath5k_buf *bf;
1295
1296         ath5k_txbuf_free(sc, sc->bbuf);
1297         list_for_each_entry(bf, &sc->txbuf, list)
1298                 ath5k_txbuf_free(sc, bf);
1299         list_for_each_entry(bf, &sc->rxbuf, list)
1300                 ath5k_txbuf_free(sc, bf);
1301
1302         /* Free memory associated with all descriptors */
1303         pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1304
1305         kfree(sc->bufptr);
1306         sc->bufptr = NULL;
1307 }
1308
1309
1310
1311
1312
1313 /**************\
1314 * Queues setup *
1315 \**************/
1316
1317 static struct ath5k_txq *
1318 ath5k_txq_setup(struct ath5k_softc *sc,
1319                 int qtype, int subtype)
1320 {
1321         struct ath5k_hw *ah = sc->ah;
1322         struct ath5k_txq *txq;
1323         struct ath5k_txq_info qi = {
1324                 .tqi_subtype = subtype,
1325                 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1326                 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1327                 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1328         };
1329         int qnum;
1330
1331         /*
1332          * Enable interrupts only for EOL and DESC conditions.
1333          * We mark tx descriptors to receive a DESC interrupt
1334          * when a tx queue gets deep; otherwise waiting for the
1335          * EOL to reap descriptors.  Note that this is done to
1336          * reduce interrupt load and this only defers reaping
1337          * descriptors, never transmitting frames.  Aside from
1338          * reducing interrupts this also permits more concurrency.
1339          * The only potential downside is if the tx queue backs
1340          * up in which case the top half of the kernel may backup
1341          * due to a lack of tx descriptors.
1342          */
1343         qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1344                                 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1345         qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1346         if (qnum < 0) {
1347                 /*
1348                  * NB: don't print a message, this happens
1349                  * normally on parts with too few tx queues
1350                  */
1351                 return ERR_PTR(qnum);
1352         }
1353         if (qnum >= ARRAY_SIZE(sc->txqs)) {
1354                 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1355                         qnum, ARRAY_SIZE(sc->txqs));
1356                 ath5k_hw_release_tx_queue(ah, qnum);
1357                 return ERR_PTR(-EINVAL);
1358         }
1359         txq = &sc->txqs[qnum];
1360         if (!txq->setup) {
1361                 txq->qnum = qnum;
1362                 txq->link = NULL;
1363                 INIT_LIST_HEAD(&txq->q);
1364                 spin_lock_init(&txq->lock);
1365                 txq->setup = true;
1366         }
1367         return &sc->txqs[qnum];
1368 }
1369
1370 static int
1371 ath5k_beaconq_setup(struct ath5k_hw *ah)
1372 {
1373         struct ath5k_txq_info qi = {
1374                 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1375                 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1376                 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1377                 /* NB: for dynamic turbo, don't enable any other interrupts */
1378                 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1379         };
1380
1381         return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1382 }
1383
1384 static int
1385 ath5k_beaconq_config(struct ath5k_softc *sc)
1386 {
1387         struct ath5k_hw *ah = sc->ah;
1388         struct ath5k_txq_info qi;
1389         int ret;
1390
1391         ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1392         if (ret)
1393                 return ret;
1394         if (sc->opmode == NL80211_IFTYPE_AP ||
1395                 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
1396                 /*
1397                  * Always burst out beacon and CAB traffic
1398                  * (aifs = cwmin = cwmax = 0)
1399                  */
1400                 qi.tqi_aifs = 0;
1401                 qi.tqi_cw_min = 0;
1402                 qi.tqi_cw_max = 0;
1403         } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1404                 /*
1405                  * Adhoc mode; backoff between 0 and (2 * cw_min).
1406                  */
1407                 qi.tqi_aifs = 0;
1408                 qi.tqi_cw_min = 0;
1409                 qi.tqi_cw_max = 2 * ah->ah_cw_min;
1410         }
1411
1412         ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1413                 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1414                 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1415
1416         ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
1417         if (ret) {
1418                 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1419                         "hardware queue!\n", __func__);
1420                 return ret;
1421         }
1422
1423         return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1424 }
1425
1426 static void
1427 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1428 {
1429         struct ath5k_buf *bf, *bf0;
1430
1431         /*
1432          * NB: this assumes output has been stopped and
1433          *     we do not need to block ath5k_tx_tasklet
1434          */
1435         spin_lock_bh(&txq->lock);
1436         list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1437                 ath5k_debug_printtxbuf(sc, bf);
1438
1439                 ath5k_txbuf_free(sc, bf);
1440
1441                 spin_lock_bh(&sc->txbuflock);
1442                 sc->tx_stats[txq->qnum].len--;
1443                 list_move_tail(&bf->list, &sc->txbuf);
1444                 sc->txbuf_len++;
1445                 spin_unlock_bh(&sc->txbuflock);
1446         }
1447         txq->link = NULL;
1448         spin_unlock_bh(&txq->lock);
1449 }
1450
1451 /*
1452  * Drain the transmit queues and reclaim resources.
1453  */
1454 static void
1455 ath5k_txq_cleanup(struct ath5k_softc *sc)
1456 {
1457         struct ath5k_hw *ah = sc->ah;
1458         unsigned int i;
1459
1460         /* XXX return value */
1461         if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1462                 /* don't touch the hardware if marked invalid */
1463                 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1464                 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1465                         ath5k_hw_get_txdp(ah, sc->bhalq));
1466                 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1467                         if (sc->txqs[i].setup) {
1468                                 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1469                                 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1470                                         "link %p\n",
1471                                         sc->txqs[i].qnum,
1472                                         ath5k_hw_get_txdp(ah,
1473                                                         sc->txqs[i].qnum),
1474                                         sc->txqs[i].link);
1475                         }
1476         }
1477         ieee80211_wake_queues(sc->hw); /* XXX move to callers */
1478
1479         for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1480                 if (sc->txqs[i].setup)
1481                         ath5k_txq_drainq(sc, &sc->txqs[i]);
1482 }
1483
1484 static void
1485 ath5k_txq_release(struct ath5k_softc *sc)
1486 {
1487         struct ath5k_txq *txq = sc->txqs;
1488         unsigned int i;
1489
1490         for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1491                 if (txq->setup) {
1492                         ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1493                         txq->setup = false;
1494                 }
1495 }
1496
1497
1498
1499
1500 /*************\
1501 * RX Handling *
1502 \*************/
1503
1504 /*
1505  * Enable the receive h/w following a reset.
1506  */
1507 static int
1508 ath5k_rx_start(struct ath5k_softc *sc)
1509 {
1510         struct ath5k_hw *ah = sc->ah;
1511         struct ath5k_buf *bf;
1512         int ret;
1513
1514         sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1515
1516         ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1517                 sc->cachelsz, sc->rxbufsize);
1518
1519         sc->rxlink = NULL;
1520
1521         spin_lock_bh(&sc->rxbuflock);
1522         list_for_each_entry(bf, &sc->rxbuf, list) {
1523                 ret = ath5k_rxbuf_setup(sc, bf);
1524                 if (ret != 0) {
1525                         spin_unlock_bh(&sc->rxbuflock);
1526                         goto err;
1527                 }
1528         }
1529         bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1530         spin_unlock_bh(&sc->rxbuflock);
1531
1532         ath5k_hw_set_rxdp(ah, bf->daddr);
1533         ath5k_hw_start_rx_dma(ah);      /* enable recv descriptors */
1534         ath5k_mode_setup(sc);           /* set filters, etc. */
1535         ath5k_hw_start_rx_pcu(ah);      /* re-enable PCU/DMA engine */
1536
1537         return 0;
1538 err:
1539         return ret;
1540 }
1541
1542 /*
1543  * Disable the receive h/w in preparation for a reset.
1544  */
1545 static void
1546 ath5k_rx_stop(struct ath5k_softc *sc)
1547 {
1548         struct ath5k_hw *ah = sc->ah;
1549
1550         ath5k_hw_stop_rx_pcu(ah);       /* disable PCU */
1551         ath5k_hw_set_rx_filter(ah, 0);  /* clear recv filter */
1552         ath5k_hw_stop_rx_dma(ah);       /* disable DMA engine */
1553
1554         ath5k_debug_printrxbuffs(sc, ah);
1555
1556         sc->rxlink = NULL;              /* just in case */
1557 }
1558
1559 static unsigned int
1560 ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
1561                 struct sk_buff *skb, struct ath5k_rx_status *rs)
1562 {
1563         struct ieee80211_hdr *hdr = (void *)skb->data;
1564         unsigned int keyix, hlen;
1565
1566         if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1567                         rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1568                 return RX_FLAG_DECRYPTED;
1569
1570         /* Apparently when a default key is used to decrypt the packet
1571            the hw does not set the index used to decrypt.  In such cases
1572            get the index from the packet. */
1573         hlen = ieee80211_hdrlen(hdr->frame_control);
1574         if (ieee80211_has_protected(hdr->frame_control) &&
1575             !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1576             skb->len >= hlen + 4) {
1577                 keyix = skb->data[hlen + 3] >> 6;
1578
1579                 if (test_bit(keyix, sc->keymap))
1580                         return RX_FLAG_DECRYPTED;
1581         }
1582
1583         return 0;
1584 }
1585
1586
1587 static void
1588 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1589                      struct ieee80211_rx_status *rxs)
1590 {
1591         u64 tsf, bc_tstamp;
1592         u32 hw_tu;
1593         struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1594
1595         if (ieee80211_is_beacon(mgmt->frame_control) &&
1596             le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1597             memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1598                 /*
1599                  * Received an IBSS beacon with the same BSSID. Hardware *must*
1600                  * have updated the local TSF. We have to work around various
1601                  * hardware bugs, though...
1602                  */
1603                 tsf = ath5k_hw_get_tsf64(sc->ah);
1604                 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1605                 hw_tu = TSF_TO_TU(tsf);
1606
1607                 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1608                         "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1609                         (unsigned long long)bc_tstamp,
1610                         (unsigned long long)rxs->mactime,
1611                         (unsigned long long)(rxs->mactime - bc_tstamp),
1612                         (unsigned long long)tsf);
1613
1614                 /*
1615                  * Sometimes the HW will give us a wrong tstamp in the rx
1616                  * status, causing the timestamp extension to go wrong.
1617                  * (This seems to happen especially with beacon frames bigger
1618                  * than 78 byte (incl. FCS))
1619                  * But we know that the receive timestamp must be later than the
1620                  * timestamp of the beacon since HW must have synced to that.
1621                  *
1622                  * NOTE: here we assume mactime to be after the frame was
1623                  * received, not like mac80211 which defines it at the start.
1624                  */
1625                 if (bc_tstamp > rxs->mactime) {
1626                         ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1627                                 "fixing mactime from %llx to %llx\n",
1628                                 (unsigned long long)rxs->mactime,
1629                                 (unsigned long long)tsf);
1630                         rxs->mactime = tsf;
1631                 }
1632
1633                 /*
1634                  * Local TSF might have moved higher than our beacon timers,
1635                  * in that case we have to update them to continue sending
1636                  * beacons. This also takes care of synchronizing beacon sending
1637                  * times with other stations.
1638                  */
1639                 if (hw_tu >= sc->nexttbtt)
1640                         ath5k_beacon_update_timers(sc, bc_tstamp);
1641         }
1642 }
1643
1644
1645 static void
1646 ath5k_tasklet_rx(unsigned long data)
1647 {
1648         struct ieee80211_rx_status rxs = {};
1649         struct ath5k_rx_status rs = {};
1650         struct sk_buff *skb;
1651         struct ath5k_softc *sc = (void *)data;
1652         struct ath5k_buf *bf, *bf_last;
1653         struct ath5k_desc *ds;
1654         int ret;
1655         int hdrlen;
1656         int pad;
1657
1658         spin_lock(&sc->rxbuflock);
1659         if (list_empty(&sc->rxbuf)) {
1660                 ATH5K_WARN(sc, "empty rx buf pool\n");
1661                 goto unlock;
1662         }
1663         bf_last = list_entry(sc->rxbuf.prev, struct ath5k_buf, list);
1664         do {
1665                 rxs.flag = 0;
1666
1667                 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1668                 BUG_ON(bf->skb == NULL);
1669                 skb = bf->skb;
1670                 ds = bf->desc;
1671
1672                 /*
1673                  * last buffer must not be freed to ensure proper hardware
1674                  * function. When the hardware finishes also a packet next to
1675                  * it, we are sure, it doesn't use it anymore and we can go on.
1676                  */
1677                 if (bf_last == bf)
1678                         bf->flags |= 1;
1679                 if (bf->flags) {
1680                         struct ath5k_buf *bf_next = list_entry(bf->list.next,
1681                                         struct ath5k_buf, list);
1682                         ret = sc->ah->ah_proc_rx_desc(sc->ah, bf_next->desc,
1683                                         &rs);
1684                         if (ret)
1685                                 break;
1686                         bf->flags &= ~1;
1687                         /* skip the overwritten one (even status is martian) */
1688                         goto next;
1689                 }
1690
1691                 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1692                 if (unlikely(ret == -EINPROGRESS))
1693                         break;
1694                 else if (unlikely(ret)) {
1695                         ATH5K_ERR(sc, "error in processing rx descriptor\n");
1696                         spin_unlock(&sc->rxbuflock);
1697                         return;
1698                 }
1699
1700                 if (unlikely(rs.rs_more)) {
1701                         ATH5K_WARN(sc, "unsupported jumbo\n");
1702                         goto next;
1703                 }
1704
1705                 if (unlikely(rs.rs_status)) {
1706                         if (rs.rs_status & AR5K_RXERR_PHY)
1707                                 goto next;
1708                         if (rs.rs_status & AR5K_RXERR_DECRYPT) {
1709                                 /*
1710                                  * Decrypt error.  If the error occurred
1711                                  * because there was no hardware key, then
1712                                  * let the frame through so the upper layers
1713                                  * can process it.  This is necessary for 5210
1714                                  * parts which have no way to setup a ``clear''
1715                                  * key cache entry.
1716                                  *
1717                                  * XXX do key cache faulting
1718                                  */
1719                                 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1720                                     !(rs.rs_status & AR5K_RXERR_CRC))
1721                                         goto accept;
1722                         }
1723                         if (rs.rs_status & AR5K_RXERR_MIC) {
1724                                 rxs.flag |= RX_FLAG_MMIC_ERROR;
1725                                 goto accept;
1726                         }
1727
1728                         /* let crypto-error packets fall through in MNTR */
1729                         if ((rs.rs_status &
1730                                 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
1731                                         sc->opmode != NL80211_IFTYPE_MONITOR)
1732                                 goto next;
1733                 }
1734 accept:
1735                 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1736                                 PCI_DMA_FROMDEVICE);
1737                 bf->skb = NULL;
1738
1739                 skb_put(skb, rs.rs_datalen);
1740
1741                 /*
1742                  * the hardware adds a padding to 4 byte boundaries between
1743                  * the header and the payload data if the header length is
1744                  * not multiples of 4 - remove it
1745                  */
1746                 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1747                 if (hdrlen & 3) {
1748                         pad = hdrlen % 4;
1749                         memmove(skb->data + pad, skb->data, hdrlen);
1750                         skb_pull(skb, pad);
1751                 }
1752
1753                 /*
1754                  * always extend the mac timestamp, since this information is
1755                  * also needed for proper IBSS merging.
1756                  *
1757                  * XXX: it might be too late to do it here, since rs_tstamp is
1758                  * 15bit only. that means TSF extension has to be done within
1759                  * 32768usec (about 32ms). it might be necessary to move this to
1760                  * the interrupt handler, like it is done in madwifi.
1761                  *
1762                  * Unfortunately we don't know when the hardware takes the rx
1763                  * timestamp (beginning of phy frame, data frame, end of rx?).
1764                  * The only thing we know is that it is hardware specific...
1765                  * On AR5213 it seems the rx timestamp is at the end of the
1766                  * frame, but i'm not sure.
1767                  *
1768                  * NOTE: mac80211 defines mactime at the beginning of the first
1769                  * data symbol. Since we don't have any time references it's
1770                  * impossible to comply to that. This affects IBSS merge only
1771                  * right now, so it's not too bad...
1772                  */
1773                 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
1774                 rxs.flag |= RX_FLAG_TSFT;
1775
1776                 rxs.freq = sc->curchan->center_freq;
1777                 rxs.band = sc->curband->band;
1778
1779                 rxs.noise = sc->ah->ah_noise_floor;
1780                 rxs.signal = rxs.noise + rs.rs_rssi;
1781                 rxs.qual = rs.rs_rssi * 100 / 64;
1782
1783                 rxs.antenna = rs.rs_antenna;
1784                 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1785                 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
1786
1787                 if (rxs.rate_idx >= 0 && rs.rs_rate ==
1788                     sc->curband->bitrates[rxs.rate_idx].hw_value_short)
1789                         rxs.flag |= RX_FLAG_SHORTPRE;
1790
1791                 ath5k_debug_dump_skb(sc, skb, "RX  ", 0);
1792
1793                 /* check beacons in IBSS mode */
1794                 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1795                         ath5k_check_ibss_tsf(sc, skb, &rxs);
1796
1797                 __ieee80211_rx(sc->hw, skb, &rxs);
1798 next:
1799                 list_move_tail(&bf->list, &sc->rxbuf);
1800         } while (ath5k_rxbuf_setup(sc, bf) == 0);
1801 unlock:
1802         spin_unlock(&sc->rxbuflock);
1803 }
1804
1805
1806
1807
1808 /*************\
1809 * TX Handling *
1810 \*************/
1811
1812 static void
1813 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1814 {
1815         struct ath5k_tx_status ts = {};
1816         struct ath5k_buf *bf, *bf0;
1817         struct ath5k_desc *ds;
1818         struct sk_buff *skb;
1819         struct ieee80211_tx_info *info;
1820         int i, ret;
1821
1822         spin_lock(&txq->lock);
1823         list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1824                 ds = bf->desc;
1825
1826                 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1827                 if (unlikely(ret == -EINPROGRESS))
1828                         break;
1829                 else if (unlikely(ret)) {
1830                         ATH5K_ERR(sc, "error %d while processing queue %u\n",
1831                                 ret, txq->qnum);
1832                         break;
1833                 }
1834
1835                 skb = bf->skb;
1836                 info = IEEE80211_SKB_CB(skb);
1837                 bf->skb = NULL;
1838
1839                 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1840                                 PCI_DMA_TODEVICE);
1841
1842                 memset(&info->status, 0, sizeof(info->status));
1843                 info->tx_rate_idx = ath5k_hw_to_driver_rix(sc,
1844                                 ts.ts_rate[ts.ts_final_idx]);
1845                 info->status.retry_count = ts.ts_longretry;
1846
1847                 for (i = 0; i < 4; i++) {
1848                         struct ieee80211_tx_altrate *r =
1849                                 &info->status.retries[i];
1850
1851                         if (ts.ts_rate[i]) {
1852                                 r->rate_idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
1853                                 r->limit = ts.ts_retry[i];
1854                         } else {
1855                                 r->rate_idx = -1;
1856                                 r->limit = 0;
1857                         }
1858                 }
1859
1860                 info->status.excessive_retries = 0;
1861                 if (unlikely(ts.ts_status)) {
1862                         sc->ll_stats.dot11ACKFailureCount++;
1863                         if (ts.ts_status & AR5K_TXERR_XRETRY)
1864                                 info->status.excessive_retries = 1;
1865                         else if (ts.ts_status & AR5K_TXERR_FILT)
1866                                 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1867                 } else {
1868                         info->flags |= IEEE80211_TX_STAT_ACK;
1869                         info->status.ack_signal = ts.ts_rssi;
1870                 }
1871
1872                 ieee80211_tx_status(sc->hw, skb);
1873                 sc->tx_stats[txq->qnum].count++;
1874
1875                 spin_lock(&sc->txbuflock);
1876                 sc->tx_stats[txq->qnum].len--;
1877                 list_move_tail(&bf->list, &sc->txbuf);
1878                 sc->txbuf_len++;
1879                 spin_unlock(&sc->txbuflock);
1880         }
1881         if (likely(list_empty(&txq->q)))
1882                 txq->link = NULL;
1883         spin_unlock(&txq->lock);
1884         if (sc->txbuf_len > ATH_TXBUF / 5)
1885                 ieee80211_wake_queues(sc->hw);
1886 }
1887
1888 static void
1889 ath5k_tasklet_tx(unsigned long data)
1890 {
1891         struct ath5k_softc *sc = (void *)data;
1892
1893         ath5k_tx_processq(sc, sc->txq);
1894 }
1895
1896
1897 /*****************\
1898 * Beacon handling *
1899 \*****************/
1900
1901 /*
1902  * Setup the beacon frame for transmit.
1903  */
1904 static int
1905 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1906 {
1907         struct sk_buff *skb = bf->skb;
1908         struct  ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1909         struct ath5k_hw *ah = sc->ah;
1910         struct ath5k_desc *ds;
1911         int ret, antenna = 0;
1912         u32 flags;
1913
1914         bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1915                         PCI_DMA_TODEVICE);
1916         ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1917                         "skbaddr %llx\n", skb, skb->data, skb->len,
1918                         (unsigned long long)bf->skbaddr);
1919         if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
1920                 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1921                 return -EIO;
1922         }
1923
1924         ds = bf->desc;
1925
1926         flags = AR5K_TXDESC_NOACK;
1927         if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
1928                 ds->ds_link = bf->daddr;        /* self-linked */
1929                 flags |= AR5K_TXDESC_VEOL;
1930                 /*
1931                  * Let hardware handle antenna switching if txantenna is not set
1932                  */
1933         } else {
1934                 ds->ds_link = 0;
1935                 /*
1936                  * Switch antenna every 4 beacons if txantenna is not set
1937                  * XXX assumes two antennas
1938                  */
1939                 if (antenna == 0)
1940                         antenna = sc->bsent & 4 ? 2 : 1;
1941         }
1942
1943         ds->ds_data = bf->skbaddr;
1944         ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
1945                         ieee80211_get_hdrlen_from_skb(skb),
1946                         AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
1947                         ieee80211_get_tx_rate(sc->hw, info)->hw_value,
1948                         1, AR5K_TXKEYIX_INVALID,
1949                         antenna, flags, 0, 0);
1950         if (ret)
1951                 goto err_unmap;
1952
1953         return 0;
1954 err_unmap:
1955         pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1956         return ret;
1957 }
1958
1959 /*
1960  * Transmit a beacon frame at SWBA.  Dynamic updates to the
1961  * frame contents are done as needed and the slot time is
1962  * also adjusted based on current state.
1963  *
1964  * this is usually called from interrupt context (ath5k_intr())
1965  * but also from ath5k_beacon_config() in IBSS mode which in turn
1966  * can be called from a tasklet and user context
1967  */
1968 static void
1969 ath5k_beacon_send(struct ath5k_softc *sc)
1970 {
1971         struct ath5k_buf *bf = sc->bbuf;
1972         struct ath5k_hw *ah = sc->ah;
1973
1974         ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
1975
1976         if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
1977                         sc->opmode == NL80211_IFTYPE_MONITOR)) {
1978                 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
1979                 return;
1980         }
1981         /*
1982          * Check if the previous beacon has gone out.  If
1983          * not don't don't try to post another, skip this
1984          * period and wait for the next.  Missed beacons
1985          * indicate a problem and should not occur.  If we
1986          * miss too many consecutive beacons reset the device.
1987          */
1988         if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
1989                 sc->bmisscount++;
1990                 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1991                         "missed %u consecutive beacons\n", sc->bmisscount);
1992                 if (sc->bmisscount > 3) {               /* NB: 3 is a guess */
1993                         ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1994                                 "stuck beacon time (%u missed)\n",
1995                                 sc->bmisscount);
1996                         tasklet_schedule(&sc->restq);
1997                 }
1998                 return;
1999         }
2000         if (unlikely(sc->bmisscount != 0)) {
2001                 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2002                         "resume beacon xmit after %u misses\n",
2003                         sc->bmisscount);
2004                 sc->bmisscount = 0;
2005         }
2006
2007         /*
2008          * Stop any current dma and put the new frame on the queue.
2009          * This should never fail since we check above that no frames
2010          * are still pending on the queue.
2011          */
2012         if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2013                 ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
2014                 /* NB: hw still stops DMA, so proceed */
2015         }
2016
2017         ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2018         ath5k_hw_start_tx_dma(ah, sc->bhalq);
2019         ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
2020                 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2021
2022         sc->bsent++;
2023 }
2024
2025
2026 /**
2027  * ath5k_beacon_update_timers - update beacon timers
2028  *
2029  * @sc: struct ath5k_softc pointer we are operating on
2030  * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2031  *          beacon timer update based on the current HW TSF.
2032  *
2033  * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2034  * of a received beacon or the current local hardware TSF and write it to the
2035  * beacon timer registers.
2036  *
2037  * This is called in a variety of situations, e.g. when a beacon is received,
2038  * when a TSF update has been detected, but also when an new IBSS is created or
2039  * when we otherwise know we have to update the timers, but we keep it in this
2040  * function to have it all together in one place.
2041  */
2042 static void
2043 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
2044 {
2045         struct ath5k_hw *ah = sc->ah;
2046         u32 nexttbtt, intval, hw_tu, bc_tu;
2047         u64 hw_tsf;
2048
2049         intval = sc->bintval & AR5K_BEACON_PERIOD;
2050         if (WARN_ON(!intval))
2051                 return;
2052
2053         /* beacon TSF converted to TU */
2054         bc_tu = TSF_TO_TU(bc_tsf);
2055
2056         /* current TSF converted to TU */
2057         hw_tsf = ath5k_hw_get_tsf64(ah);
2058         hw_tu = TSF_TO_TU(hw_tsf);
2059
2060 #define FUDGE 3
2061         /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2062         if (bc_tsf == -1) {
2063                 /*
2064                  * no beacons received, called internally.
2065                  * just need to refresh timers based on HW TSF.
2066                  */
2067                 nexttbtt = roundup(hw_tu + FUDGE, intval);
2068         } else if (bc_tsf == 0) {
2069                 /*
2070                  * no beacon received, probably called by ath5k_reset_tsf().
2071                  * reset TSF to start with 0.
2072                  */
2073                 nexttbtt = intval;
2074                 intval |= AR5K_BEACON_RESET_TSF;
2075         } else if (bc_tsf > hw_tsf) {
2076                 /*
2077                  * beacon received, SW merge happend but HW TSF not yet updated.
2078                  * not possible to reconfigure timers yet, but next time we
2079                  * receive a beacon with the same BSSID, the hardware will
2080                  * automatically update the TSF and then we need to reconfigure
2081                  * the timers.
2082                  */
2083                 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2084                         "need to wait for HW TSF sync\n");
2085                 return;
2086         } else {
2087                 /*
2088                  * most important case for beacon synchronization between STA.
2089                  *
2090                  * beacon received and HW TSF has been already updated by HW.
2091                  * update next TBTT based on the TSF of the beacon, but make
2092                  * sure it is ahead of our local TSF timer.
2093                  */
2094                 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2095         }
2096 #undef FUDGE
2097
2098         sc->nexttbtt = nexttbtt;
2099
2100         intval |= AR5K_BEACON_ENA;
2101         ath5k_hw_init_beacon(ah, nexttbtt, intval);
2102
2103         /*
2104          * debugging output last in order to preserve the time critical aspect
2105          * of this function
2106          */
2107         if (bc_tsf == -1)
2108                 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2109                         "reconfigured timers based on HW TSF\n");
2110         else if (bc_tsf == 0)
2111                 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2112                         "reset HW TSF and timers\n");
2113         else
2114                 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2115                         "updated timers based on beacon TSF\n");
2116
2117         ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2118                           "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2119                           (unsigned long long) bc_tsf,
2120                           (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2121         ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2122                 intval & AR5K_BEACON_PERIOD,
2123                 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2124                 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2125 }
2126
2127
2128 /**
2129  * ath5k_beacon_config - Configure the beacon queues and interrupts
2130  *
2131  * @sc: struct ath5k_softc pointer we are operating on
2132  *
2133  * When operating in station mode we want to receive a BMISS interrupt when we
2134  * stop seeing beacons from the AP we've associated with so we can look for
2135  * another AP to associate with.
2136  *
2137  * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2138  * interrupts to detect TSF updates only.
2139  */
2140 static void
2141 ath5k_beacon_config(struct ath5k_softc *sc)
2142 {
2143         struct ath5k_hw *ah = sc->ah;
2144
2145         ath5k_hw_set_imr(ah, 0);
2146         sc->bmisscount = 0;
2147         sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2148
2149         if (sc->opmode == NL80211_IFTYPE_STATION) {
2150                 sc->imask |= AR5K_INT_BMISS;
2151         } else if (sc->opmode == NL80211_IFTYPE_ADHOC ||
2152                         sc->opmode == NL80211_IFTYPE_AP) {
2153                 /*
2154                  * In IBSS mode we use a self-linked tx descriptor and let the
2155                  * hardware send the beacons automatically. We have to load it
2156                  * only once here.
2157                  * We use the SWBA interrupt only to keep track of the beacon
2158                  * timers in order to detect automatic TSF updates.
2159                  */
2160                 ath5k_beaconq_config(sc);
2161
2162                 sc->imask |= AR5K_INT_SWBA;
2163
2164                 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2165                         if (ath5k_hw_hasveol(ah)) {
2166                                 spin_lock(&sc->block);
2167                                 ath5k_beacon_send(sc);
2168                                 spin_unlock(&sc->block);
2169                         }
2170                 } else
2171                         ath5k_beacon_update_timers(sc, -1);
2172         }
2173
2174         ath5k_hw_set_imr(ah, sc->imask);
2175 }
2176
2177
2178 /********************\
2179 * Interrupt handling *
2180 \********************/
2181
2182 static int
2183 ath5k_init(struct ath5k_softc *sc, bool is_resume)
2184 {
2185         struct ath5k_hw *ah = sc->ah;
2186         int ret, i;
2187
2188         mutex_lock(&sc->lock);
2189
2190         if (is_resume && !test_bit(ATH_STAT_STARTED, sc->status))
2191                 goto out_ok;
2192
2193         __clear_bit(ATH_STAT_STARTED, sc->status);
2194
2195         ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2196
2197         /*
2198          * Stop anything previously setup.  This is safe
2199          * no matter this is the first time through or not.
2200          */
2201         ath5k_stop_locked(sc);
2202
2203         /*
2204          * The basic interface to setting the hardware in a good
2205          * state is ``reset''.  On return the hardware is known to
2206          * be powered up and with interrupts disabled.  This must
2207          * be followed by initialization of the appropriate bits
2208          * and then setup of the interrupt mask.
2209          */
2210         sc->curchan = sc->hw->conf.channel;
2211         sc->curband = &sc->sbands[sc->curchan->band];
2212         sc->imask = AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_RXEOL |
2213                 AR5K_INT_RXORN | AR5K_INT_FATAL | AR5K_INT_GLOBAL |
2214                 AR5K_INT_MIB;
2215         ret = ath5k_reset(sc, false, false);
2216         if (ret)
2217                 goto done;
2218
2219         /*
2220          * Reset the key cache since some parts do not reset the
2221          * contents on initial power up or resume from suspend.
2222          */
2223         for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2224                 ath5k_hw_reset_key(ah, i);
2225
2226         __set_bit(ATH_STAT_STARTED, sc->status);
2227
2228         /* Set ack to be sent at low bit-rates */
2229         ath5k_hw_set_ack_bitrate_high(ah, false);
2230
2231         mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2232                         msecs_to_jiffies(ath5k_calinterval * 1000)));
2233
2234 out_ok:
2235         ret = 0;
2236 done:
2237         mmiowb();
2238         mutex_unlock(&sc->lock);
2239         return ret;
2240 }
2241
2242 static int
2243 ath5k_stop_locked(struct ath5k_softc *sc)
2244 {
2245         struct ath5k_hw *ah = sc->ah;
2246
2247         ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2248                         test_bit(ATH_STAT_INVALID, sc->status));
2249
2250         /*
2251          * Shutdown the hardware and driver:
2252          *    stop output from above
2253          *    disable interrupts
2254          *    turn off timers
2255          *    turn off the radio
2256          *    clear transmit machinery
2257          *    clear receive machinery
2258          *    drain and release tx queues
2259          *    reclaim beacon resources
2260          *    power down hardware
2261          *
2262          * Note that some of this work is not possible if the
2263          * hardware is gone (invalid).
2264          */
2265         ieee80211_stop_queues(sc->hw);
2266
2267         if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2268                 ath5k_led_off(sc);
2269                 ath5k_hw_set_imr(ah, 0);
2270                 synchronize_irq(sc->pdev->irq);
2271         }
2272         ath5k_txq_cleanup(sc);
2273         if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2274                 ath5k_rx_stop(sc);
2275                 ath5k_hw_phy_disable(ah);
2276         } else
2277                 sc->rxlink = NULL;
2278
2279         return 0;
2280 }
2281
2282 /*
2283  * Stop the device, grabbing the top-level lock to protect
2284  * against concurrent entry through ath5k_init (which can happen
2285  * if another thread does a system call and the thread doing the
2286  * stop is preempted).
2287  */
2288 static int
2289 ath5k_stop_hw(struct ath5k_softc *sc, bool is_suspend)
2290 {
2291         int ret;
2292
2293         mutex_lock(&sc->lock);
2294         ret = ath5k_stop_locked(sc);
2295         if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2296                 /*
2297                  * Set the chip in full sleep mode.  Note that we are
2298                  * careful to do this only when bringing the interface
2299                  * completely to a stop.  When the chip is in this state
2300                  * it must be carefully woken up or references to
2301                  * registers in the PCI clock domain may freeze the bus
2302                  * (and system).  This varies by chip and is mostly an
2303                  * issue with newer parts that go to sleep more quickly.
2304                  */
2305                 if (sc->ah->ah_mac_srev >= 0x78) {
2306                         /*
2307                          * XXX
2308                          * don't put newer MAC revisions > 7.8 to sleep because
2309                          * of the above mentioned problems
2310                          */
2311                         ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2312                                 "not putting device to sleep\n");
2313                 } else {
2314                         ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2315                                 "putting device to full sleep\n");
2316                         ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2317                 }
2318         }
2319         ath5k_txbuf_free(sc, sc->bbuf);
2320         if (!is_suspend)
2321                 __clear_bit(ATH_STAT_STARTED, sc->status);
2322
2323         mmiowb();
2324         mutex_unlock(&sc->lock);
2325
2326         del_timer_sync(&sc->calib_tim);
2327         tasklet_kill(&sc->rxtq);
2328         tasklet_kill(&sc->txtq);
2329         tasklet_kill(&sc->restq);
2330
2331         return ret;
2332 }
2333
2334 static irqreturn_t
2335 ath5k_intr(int irq, void *dev_id)
2336 {
2337         struct ath5k_softc *sc = dev_id;
2338         struct ath5k_hw *ah = sc->ah;
2339         enum ath5k_int status;
2340         unsigned int counter = 1000;
2341
2342         if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2343                                 !ath5k_hw_is_intr_pending(ah)))
2344                 return IRQ_NONE;
2345
2346         do {
2347                 /*
2348                  * Figure out the reason(s) for the interrupt.  Note
2349                  * that get_isr returns a pseudo-ISR that may include
2350                  * bits we haven't explicitly enabled so we mask the
2351                  * value to insure we only process bits we requested.
2352                  */
2353                 ath5k_hw_get_isr(ah, &status);          /* NB: clears IRQ too */
2354                 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2355                                 status, sc->imask);
2356                 status &= sc->imask; /* discard unasked for bits */
2357                 if (unlikely(status & AR5K_INT_FATAL)) {
2358                         /*
2359                          * Fatal errors are unrecoverable.
2360                          * Typically these are caused by DMA errors.
2361                          */
2362                         tasklet_schedule(&sc->restq);
2363                 } else if (unlikely(status & AR5K_INT_RXORN)) {
2364                         tasklet_schedule(&sc->restq);
2365                 } else {
2366                         if (status & AR5K_INT_SWBA) {
2367                                 /*
2368                                 * Software beacon alert--time to send a beacon.
2369                                 * Handle beacon transmission directly; deferring
2370                                 * this is too slow to meet timing constraints
2371                                 * under load.
2372                                 *
2373                                 * In IBSS mode we use this interrupt just to
2374                                 * keep track of the next TBTT (target beacon
2375                                 * transmission time) in order to detect wether
2376                                 * automatic TSF updates happened.
2377                                 */
2378                                 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2379                                          /* XXX: only if VEOL suppported */
2380                                         u64 tsf = ath5k_hw_get_tsf64(ah);
2381                                         sc->nexttbtt += sc->bintval;
2382                                         ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2383                                                   "SWBA nexttbtt: %x hw_tu: %x "
2384                                                   "TSF: %llx\n",
2385                                                   sc->nexttbtt,
2386                                                   TSF_TO_TU(tsf),
2387                                                   (unsigned long long) tsf);
2388                                 } else {
2389                                         spin_lock(&sc->block);
2390                                         ath5k_beacon_send(sc);
2391                                         spin_unlock(&sc->block);
2392                                 }
2393                         }
2394                         if (status & AR5K_INT_RXEOL) {
2395                                 /*
2396                                 * NB: the hardware should re-read the link when
2397                                 *     RXE bit is written, but it doesn't work at
2398                                 *     least on older hardware revs.
2399                                 */
2400                                 sc->rxlink = NULL;
2401                         }
2402                         if (status & AR5K_INT_TXURN) {
2403                                 /* bump tx trigger level */
2404                                 ath5k_hw_update_tx_triglevel(ah, true);
2405                         }
2406                         if (status & AR5K_INT_RX)
2407                                 tasklet_schedule(&sc->rxtq);
2408                         if (status & AR5K_INT_TX)
2409                                 tasklet_schedule(&sc->txtq);
2410                         if (status & AR5K_INT_BMISS) {
2411                         }
2412                         if (status & AR5K_INT_MIB) {
2413                                 /*
2414                                  * These stats are also used for ANI i think
2415                                  * so how about updating them more often ?
2416                                  */
2417                                 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
2418                         }
2419                 }
2420         } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
2421
2422         if (unlikely(!counter))
2423                 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2424
2425         return IRQ_HANDLED;
2426 }
2427
2428 static void
2429 ath5k_tasklet_reset(unsigned long data)
2430 {
2431         struct ath5k_softc *sc = (void *)data;
2432
2433         ath5k_reset_wake(sc);
2434 }
2435
2436 /*
2437  * Periodically recalibrate the PHY to account
2438  * for temperature/environment changes.
2439  */
2440 static void
2441 ath5k_calibrate(unsigned long data)
2442 {
2443         struct ath5k_softc *sc = (void *)data;
2444         struct ath5k_hw *ah = sc->ah;
2445
2446         ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2447                 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2448                 sc->curchan->hw_value);
2449
2450         if (ath5k_hw_get_rf_gain(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2451                 /*
2452                  * Rfgain is out of bounds, reset the chip
2453                  * to load new gain values.
2454                  */
2455                 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2456                 ath5k_reset_wake(sc);
2457         }
2458         if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2459                 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2460                         ieee80211_frequency_to_channel(
2461                                 sc->curchan->center_freq));
2462
2463         mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2464                         msecs_to_jiffies(ath5k_calinterval * 1000)));
2465 }
2466
2467
2468
2469 /***************\
2470 * LED functions *
2471 \***************/
2472
2473 static void
2474 ath5k_led_enable(struct ath5k_softc *sc)
2475 {
2476         if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
2477                 ath5k_hw_set_gpio_output(sc->ah, sc->led_pin);
2478                 ath5k_led_off(sc);
2479         }
2480 }
2481
2482 static void
2483 ath5k_led_on(struct ath5k_softc *sc)
2484 {
2485         if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2486                 return;
2487         ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on);
2488 }
2489
2490 static void
2491 ath5k_led_off(struct ath5k_softc *sc)
2492 {
2493         if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2494                 return;
2495         ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on);
2496 }
2497
2498 static void
2499 ath5k_led_brightness_set(struct led_classdev *led_dev,
2500         enum led_brightness brightness)
2501 {
2502         struct ath5k_led *led = container_of(led_dev, struct ath5k_led,
2503                 led_dev);
2504
2505         if (brightness == LED_OFF)
2506                 ath5k_led_off(led->sc);
2507         else
2508                 ath5k_led_on(led->sc);
2509 }
2510
2511 static int
2512 ath5k_register_led(struct ath5k_softc *sc, struct ath5k_led *led,
2513                    const char *name, char *trigger)
2514 {
2515         int err;
2516
2517         led->sc = sc;
2518         strncpy(led->name, name, sizeof(led->name));
2519         led->led_dev.name = led->name;
2520         led->led_dev.default_trigger = trigger;
2521         led->led_dev.brightness_set = ath5k_led_brightness_set;
2522
2523         err = led_classdev_register(&sc->pdev->dev, &led->led_dev);
2524         if (err)
2525         {
2526                 ATH5K_WARN(sc, "could not register LED %s\n", name);
2527                 led->sc = NULL;
2528         }
2529         return err;
2530 }
2531
2532 static void
2533 ath5k_unregister_led(struct ath5k_led *led)
2534 {
2535         if (!led->sc)
2536                 return;
2537         led_classdev_unregister(&led->led_dev);
2538         ath5k_led_off(led->sc);
2539         led->sc = NULL;
2540 }
2541
2542 static void
2543 ath5k_unregister_leds(struct ath5k_softc *sc)
2544 {
2545         ath5k_unregister_led(&sc->rx_led);
2546         ath5k_unregister_led(&sc->tx_led);
2547 }
2548
2549
2550 static int
2551 ath5k_init_leds(struct ath5k_softc *sc)
2552 {
2553         int ret = 0;
2554         struct ieee80211_hw *hw = sc->hw;
2555         struct pci_dev *pdev = sc->pdev;
2556         char name[ATH5K_LED_MAX_NAME_LEN + 1];
2557
2558         /*
2559          * Auto-enable soft led processing for IBM cards and for
2560          * 5211 minipci cards.
2561          */
2562         if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM ||
2563             pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) {
2564                 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2565                 sc->led_pin = 0;
2566                 sc->led_on = 0;  /* active low */
2567         }
2568         /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
2569         if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) {
2570                 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2571                 sc->led_pin = 1;
2572                 sc->led_on = 1;  /* active high */
2573         }
2574         if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2575                 goto out;
2576
2577         ath5k_led_enable(sc);
2578
2579         snprintf(name, sizeof(name), "ath5k-%s::rx", wiphy_name(hw->wiphy));
2580         ret = ath5k_register_led(sc, &sc->rx_led, name,
2581                 ieee80211_get_rx_led_name(hw));
2582         if (ret)
2583                 goto out;
2584
2585         snprintf(name, sizeof(name), "ath5k-%s::tx", wiphy_name(hw->wiphy));
2586         ret = ath5k_register_led(sc, &sc->tx_led, name,
2587                 ieee80211_get_tx_led_name(hw));
2588 out:
2589         return ret;
2590 }
2591
2592
2593 /********************\
2594 * Mac80211 functions *
2595 \********************/
2596
2597 static int
2598 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2599 {
2600         struct ath5k_softc *sc = hw->priv;
2601         struct ath5k_buf *bf;
2602         unsigned long flags;
2603         int hdrlen;
2604         int pad;
2605
2606         ath5k_debug_dump_skb(sc, skb, "TX  ", 1);
2607
2608         if (sc->opmode == NL80211_IFTYPE_MONITOR)
2609                 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2610
2611         /*
2612          * the hardware expects the header padded to 4 byte boundaries
2613          * if this is not the case we add the padding after the header
2614          */
2615         hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2616         if (hdrlen & 3) {
2617                 pad = hdrlen % 4;
2618                 if (skb_headroom(skb) < pad) {
2619                         ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2620                                 " headroom to pad %d\n", hdrlen, pad);
2621                         return -1;
2622                 }
2623                 skb_push(skb, pad);
2624                 memmove(skb->data, skb->data+pad, hdrlen);
2625         }
2626
2627         spin_lock_irqsave(&sc->txbuflock, flags);
2628         if (list_empty(&sc->txbuf)) {
2629                 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2630                 spin_unlock_irqrestore(&sc->txbuflock, flags);
2631                 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
2632                 return -1;
2633         }
2634         bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2635         list_del(&bf->list);
2636         sc->txbuf_len--;
2637         if (list_empty(&sc->txbuf))
2638                 ieee80211_stop_queues(hw);
2639         spin_unlock_irqrestore(&sc->txbuflock, flags);
2640
2641         bf->skb = skb;
2642
2643         if (ath5k_txbuf_setup(sc, bf)) {
2644                 bf->skb = NULL;
2645                 spin_lock_irqsave(&sc->txbuflock, flags);
2646                 list_add_tail(&bf->list, &sc->txbuf);
2647                 sc->txbuf_len++;
2648                 spin_unlock_irqrestore(&sc->txbuflock, flags);
2649                 dev_kfree_skb_any(skb);
2650                 return 0;
2651         }
2652
2653         return 0;
2654 }
2655
2656 static int
2657 ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel)
2658 {
2659         struct ath5k_hw *ah = sc->ah;
2660         int ret;
2661
2662         ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2663
2664         if (stop) {
2665                 ath5k_hw_set_imr(ah, 0);
2666                 ath5k_txq_cleanup(sc);
2667                 ath5k_rx_stop(sc);
2668         }
2669         ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
2670         if (ret) {
2671                 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2672                 goto err;
2673         }
2674
2675         /*
2676          * This is needed only to setup initial state
2677          * but it's best done after a reset.
2678          */
2679         ath5k_hw_set_txpower_limit(sc->ah, 0);
2680
2681         ret = ath5k_rx_start(sc);
2682         if (ret) {
2683                 ATH5K_ERR(sc, "can't start recv logic\n");
2684                 goto err;
2685         }
2686
2687         /*
2688          * Change channels and update the h/w rate map if we're switching;
2689          * e.g. 11a to 11b/g.
2690          *
2691          * We may be doing a reset in response to an ioctl that changes the
2692          * channel so update any state that might change as a result.
2693          *
2694          * XXX needed?
2695          */
2696 /*      ath5k_chan_change(sc, c); */
2697
2698         ath5k_beacon_config(sc);
2699         /* intrs are enabled by ath5k_beacon_config */
2700
2701         return 0;
2702 err:
2703         return ret;
2704 }
2705
2706 static int
2707 ath5k_reset_wake(struct ath5k_softc *sc)
2708 {
2709         int ret;
2710
2711         ret = ath5k_reset(sc, true, true);
2712         if (!ret)
2713                 ieee80211_wake_queues(sc->hw);
2714
2715         return ret;
2716 }
2717
2718 static int ath5k_start(struct ieee80211_hw *hw)
2719 {
2720         return ath5k_init(hw->priv, false);
2721 }
2722
2723 static void ath5k_stop(struct ieee80211_hw *hw)
2724 {
2725         ath5k_stop_hw(hw->priv, false);
2726 }
2727
2728 static int ath5k_add_interface(struct ieee80211_hw *hw,
2729                 struct ieee80211_if_init_conf *conf)
2730 {
2731         struct ath5k_softc *sc = hw->priv;
2732         int ret;
2733
2734         mutex_lock(&sc->lock);
2735         if (sc->vif) {
2736                 ret = 0;
2737                 goto end;
2738         }
2739
2740         sc->vif = conf->vif;
2741
2742         switch (conf->type) {
2743         case NL80211_IFTYPE_AP:
2744         case NL80211_IFTYPE_STATION:
2745         case NL80211_IFTYPE_ADHOC:
2746         case NL80211_IFTYPE_MONITOR:
2747                 sc->opmode = conf->type;
2748                 break;
2749         default:
2750                 ret = -EOPNOTSUPP;
2751                 goto end;
2752         }
2753
2754         /* Set to a reasonable value. Note that this will
2755          * be set to mac80211's value at ath5k_config(). */
2756         sc->bintval = 1000;
2757
2758         ret = 0;
2759 end:
2760         mutex_unlock(&sc->lock);
2761         return ret;
2762 }
2763
2764 static void
2765 ath5k_remove_interface(struct ieee80211_hw *hw,
2766                         struct ieee80211_if_init_conf *conf)
2767 {
2768         struct ath5k_softc *sc = hw->priv;
2769
2770         mutex_lock(&sc->lock);
2771         if (sc->vif != conf->vif)
2772                 goto end;
2773
2774         sc->vif = NULL;
2775 end:
2776         mutex_unlock(&sc->lock);
2777 }
2778
2779 /*
2780  * TODO: Phy disable/diversity etc
2781  */
2782 static int
2783 ath5k_config(struct ieee80211_hw *hw, u32 changed)
2784 {
2785         struct ath5k_softc *sc = hw->priv;
2786         struct ieee80211_conf *conf = &hw->conf;
2787
2788         sc->bintval = conf->beacon_int;
2789         sc->power_level = conf->power_level;
2790
2791         return ath5k_chan_set(sc, conf->channel);
2792 }
2793
2794 static int
2795 ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2796                         struct ieee80211_if_conf *conf)
2797 {
2798         struct ath5k_softc *sc = hw->priv;
2799         struct ath5k_hw *ah = sc->ah;
2800         int ret;
2801
2802         mutex_lock(&sc->lock);
2803         if (sc->vif != vif) {
2804                 ret = -EIO;
2805                 goto unlock;
2806         }
2807         if (conf->changed & IEEE80211_IFCC_BSSID && conf->bssid) {
2808                 /* Cache for later use during resets */
2809                 memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
2810                 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2811                  * a clean way of letting us retrieve this yet. */
2812                 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
2813                 mmiowb();
2814         }
2815         if (conf->changed & IEEE80211_IFCC_BEACON &&
2816                         (vif->type == NL80211_IFTYPE_ADHOC ||
2817                          vif->type == NL80211_IFTYPE_AP)) {
2818                 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2819                 if (!beacon) {
2820                         ret = -ENOMEM;
2821                         goto unlock;
2822                 }
2823                 ath5k_beacon_update(sc, beacon);
2824         }
2825         mutex_unlock(&sc->lock);
2826
2827         return ath5k_reset_wake(sc);
2828 unlock:
2829         mutex_unlock(&sc->lock);
2830         return ret;
2831 }
2832
2833 #define SUPPORTED_FIF_FLAGS \
2834         FIF_PROMISC_IN_BSS |  FIF_ALLMULTI | FIF_FCSFAIL | \
2835         FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2836         FIF_BCN_PRBRESP_PROMISC
2837 /*
2838  * o always accept unicast, broadcast, and multicast traffic
2839  * o multicast traffic for all BSSIDs will be enabled if mac80211
2840  *   says it should be
2841  * o maintain current state of phy ofdm or phy cck error reception.
2842  *   If the hardware detects any of these type of errors then
2843  *   ath5k_hw_get_rx_filter() will pass to us the respective
2844  *   hardware filters to be able to receive these type of frames.
2845  * o probe request frames are accepted only when operating in
2846  *   hostap, adhoc, or monitor modes
2847  * o enable promiscuous mode according to the interface state
2848  * o accept beacons:
2849  *   - when operating in adhoc mode so the 802.11 layer creates
2850  *     node table entries for peers,
2851  *   - when operating in station mode for collecting rssi data when
2852  *     the station is otherwise quiet, or
2853  *   - when scanning
2854  */
2855 static void ath5k_configure_filter(struct ieee80211_hw *hw,
2856                 unsigned int changed_flags,
2857                 unsigned int *new_flags,
2858                 int mc_count, struct dev_mc_list *mclist)
2859 {
2860         struct ath5k_softc *sc = hw->priv;
2861         struct ath5k_hw *ah = sc->ah;
2862         u32 mfilt[2], val, rfilt;
2863         u8 pos;
2864         int i;
2865
2866         mfilt[0] = 0;
2867         mfilt[1] = 0;
2868
2869         /* Only deal with supported flags */
2870         changed_flags &= SUPPORTED_FIF_FLAGS;
2871         *new_flags &= SUPPORTED_FIF_FLAGS;
2872
2873         /* If HW detects any phy or radar errors, leave those filters on.
2874          * Also, always enable Unicast, Broadcasts and Multicast
2875          * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2876         rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2877                 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2878                 AR5K_RX_FILTER_MCAST);
2879
2880         if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2881                 if (*new_flags & FIF_PROMISC_IN_BSS) {
2882                         rfilt |= AR5K_RX_FILTER_PROM;
2883                         __set_bit(ATH_STAT_PROMISC, sc->status);
2884                 }
2885                 else
2886                         __clear_bit(ATH_STAT_PROMISC, sc->status);
2887         }
2888
2889         /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2890         if (*new_flags & FIF_ALLMULTI) {
2891                 mfilt[0] =  ~0;
2892                 mfilt[1] =  ~0;
2893         } else {
2894                 for (i = 0; i < mc_count; i++) {
2895                         if (!mclist)
2896                                 break;
2897                         /* calculate XOR of eight 6-bit values */
2898                         val = get_unaligned_le32(mclist->dmi_addr + 0);
2899                         pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2900                         val = get_unaligned_le32(mclist->dmi_addr + 3);
2901                         pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2902                         pos &= 0x3f;
2903                         mfilt[pos / 32] |= (1 << (pos % 32));
2904                         /* XXX: we might be able to just do this instead,
2905                         * but not sure, needs testing, if we do use this we'd
2906                         * neet to inform below to not reset the mcast */
2907                         /* ath5k_hw_set_mcast_filterindex(ah,
2908                          *      mclist->dmi_addr[5]); */
2909                         mclist = mclist->next;
2910                 }
2911         }
2912
2913         /* This is the best we can do */
2914         if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2915                 rfilt |= AR5K_RX_FILTER_PHYERR;
2916
2917         /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2918         * and probes for any BSSID, this needs testing */
2919         if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2920                 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2921
2922         /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2923          * set we should only pass on control frames for this
2924          * station. This needs testing. I believe right now this
2925          * enables *all* control frames, which is OK.. but
2926          * but we should see if we can improve on granularity */
2927         if (*new_flags & FIF_CONTROL)
2928                 rfilt |= AR5K_RX_FILTER_CONTROL;
2929
2930         /* Additional settings per mode -- this is per ath5k */
2931
2932         /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2933
2934         if (sc->opmode == NL80211_IFTYPE_MONITOR)
2935                 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2936                         AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
2937         if (sc->opmode != NL80211_IFTYPE_STATION)
2938                 rfilt |= AR5K_RX_FILTER_PROBEREQ;
2939         if (sc->opmode != NL80211_IFTYPE_AP &&
2940                 sc->opmode != NL80211_IFTYPE_MESH_POINT &&
2941                 test_bit(ATH_STAT_PROMISC, sc->status))
2942                 rfilt |= AR5K_RX_FILTER_PROM;
2943         if (sc->opmode == NL80211_IFTYPE_ADHOC)
2944                 rfilt |= AR5K_RX_FILTER_BEACON;
2945
2946         /* Set filters */
2947         ath5k_hw_set_rx_filter(ah,rfilt);
2948
2949         /* Set multicast bits */
2950         ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2951         /* Set the cached hw filter flags, this will alter actually
2952          * be set in HW */
2953         sc->filter_flags = rfilt;
2954 }
2955
2956 static int
2957 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2958                 const u8 *local_addr, const u8 *addr,
2959                 struct ieee80211_key_conf *key)
2960 {
2961         struct ath5k_softc *sc = hw->priv;
2962         int ret = 0;
2963
2964         switch(key->alg) {
2965         case ALG_WEP:
2966         /* XXX: fix hardware encryption, its not working. For now
2967          * allow software encryption */
2968                 /* break; */
2969         case ALG_TKIP:
2970         case ALG_CCMP:
2971                 return -EOPNOTSUPP;
2972         default:
2973                 WARN_ON(1);
2974                 return -EINVAL;
2975         }
2976
2977         mutex_lock(&sc->lock);
2978
2979         switch (cmd) {
2980         case SET_KEY:
2981                 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key, addr);
2982                 if (ret) {
2983                         ATH5K_ERR(sc, "can't set the key\n");
2984                         goto unlock;
2985                 }
2986                 __set_bit(key->keyidx, sc->keymap);
2987                 key->hw_key_idx = key->keyidx;
2988                 break;
2989         case DISABLE_KEY:
2990                 ath5k_hw_reset_key(sc->ah, key->keyidx);
2991                 __clear_bit(key->keyidx, sc->keymap);
2992                 break;
2993         default:
2994                 ret = -EINVAL;
2995                 goto unlock;
2996         }
2997
2998 unlock:
2999         mmiowb();
3000         mutex_unlock(&sc->lock);
3001         return ret;
3002 }
3003
3004 static int
3005 ath5k_get_stats(struct ieee80211_hw *hw,
3006                 struct ieee80211_low_level_stats *stats)
3007 {
3008         struct ath5k_softc *sc = hw->priv;
3009         struct ath5k_hw *ah = sc->ah;
3010
3011         /* Force update */
3012         ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
3013
3014         memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
3015
3016         return 0;
3017 }
3018
3019 static int
3020 ath5k_get_tx_stats(struct ieee80211_hw *hw,
3021                 struct ieee80211_tx_queue_stats *stats)
3022 {
3023         struct ath5k_softc *sc = hw->priv;
3024
3025         memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
3026
3027         return 0;
3028 }
3029
3030 static u64
3031 ath5k_get_tsf(struct ieee80211_hw *hw)
3032 {
3033         struct ath5k_softc *sc = hw->priv;
3034
3035         return ath5k_hw_get_tsf64(sc->ah);
3036 }
3037
3038 static void
3039 ath5k_reset_tsf(struct ieee80211_hw *hw)
3040 {
3041         struct ath5k_softc *sc = hw->priv;
3042
3043         /*
3044          * in IBSS mode we need to update the beacon timers too.
3045          * this will also reset the TSF if we call it with 0
3046          */
3047         if (sc->opmode == NL80211_IFTYPE_ADHOC)
3048                 ath5k_beacon_update_timers(sc, 0);
3049         else
3050                 ath5k_hw_reset_tsf(sc->ah);
3051 }
3052
3053 static int
3054 ath5k_beacon_update(struct ath5k_softc *sc, struct sk_buff *skb)
3055 {
3056         unsigned long flags;
3057         int ret;
3058
3059         ath5k_debug_dump_skb(sc, skb, "BC  ", 1);
3060
3061         spin_lock_irqsave(&sc->block, flags);
3062         ath5k_txbuf_free(sc, sc->bbuf);
3063         sc->bbuf->skb = skb;
3064         ret = ath5k_beacon_setup(sc, sc->bbuf);
3065         if (ret)
3066                 sc->bbuf->skb = NULL;
3067         spin_unlock_irqrestore(&sc->block, flags);
3068         if (!ret) {
3069                 ath5k_beacon_config(sc);
3070                 mmiowb();
3071         }
3072
3073         return ret;
3074 }
3075