2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
43 #include <linux/version.h>
44 #include <linux/module.h>
45 #include <linux/delay.h>
47 #include <linux/netdevice.h>
48 #include <linux/cache.h>
49 #include <linux/pci.h>
50 #include <linux/ethtool.h>
51 #include <linux/uaccess.h>
53 #include <net/ieee80211_radiotap.h>
55 #include <asm/unaligned.h>
61 static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
69 MODULE_AUTHOR("Jiri Slaby");
70 MODULE_AUTHOR("Nick Kossifidis");
71 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
72 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
73 MODULE_LICENSE("Dual BSD/GPL");
74 MODULE_VERSION("0.5.0 (EXPERIMENTAL)");
78 static struct pci_device_id ath5k_pci_id_table[] __devinitdata = {
79 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
80 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
81 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
82 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
83 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
84 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
85 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
86 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
87 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
88 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
89 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
90 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
91 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
92 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
93 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
94 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
95 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* 5424 Condor (PCI-E)*/
96 { PCI_VDEVICE(ATHEROS, 0x0023), .driver_data = AR5K_AR5212 }, /* 5416 */
97 { PCI_VDEVICE(ATHEROS, 0x0024), .driver_data = AR5K_AR5212 }, /* 5418 */
100 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
103 static struct ath5k_srev_name srev_names[] = {
104 { "5210", AR5K_VERSION_VER, AR5K_SREV_VER_AR5210 },
105 { "5311", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311 },
106 { "5311A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311A },
107 { "5311B", AR5K_VERSION_VER, AR5K_SREV_VER_AR5311B },
108 { "5211", AR5K_VERSION_VER, AR5K_SREV_VER_AR5211 },
109 { "5212", AR5K_VERSION_VER, AR5K_SREV_VER_AR5212 },
110 { "5213", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213 },
111 { "5213A", AR5K_VERSION_VER, AR5K_SREV_VER_AR5213A },
112 { "2413", AR5K_VERSION_VER, AR5K_SREV_VER_AR2413 },
113 { "2414", AR5K_VERSION_VER, AR5K_SREV_VER_AR2414 },
114 { "2424", AR5K_VERSION_VER, AR5K_SREV_VER_AR2424 },
115 { "5424", AR5K_VERSION_VER, AR5K_SREV_VER_AR5424 },
116 { "5413", AR5K_VERSION_VER, AR5K_SREV_VER_AR5413 },
117 { "5414", AR5K_VERSION_VER, AR5K_SREV_VER_AR5414 },
118 { "5416", AR5K_VERSION_VER, AR5K_SREV_VER_AR5416 },
119 { "5418", AR5K_VERSION_VER, AR5K_SREV_VER_AR5418 },
120 { "2425", AR5K_VERSION_VER, AR5K_SREV_VER_AR2425 },
121 { "xxxxx", AR5K_VERSION_VER, AR5K_SREV_UNKNOWN },
122 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
123 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
124 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
125 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
126 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
127 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
128 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
129 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC0 },
130 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC1 },
131 { "SChip", AR5K_VERSION_RAD, AR5K_SREV_RAD_SC2 },
132 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
133 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
137 * Prototypes - PCI stack related functions
139 static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
140 const struct pci_device_id *id);
141 static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
143 static int ath5k_pci_suspend(struct pci_dev *pdev,
145 static int ath5k_pci_resume(struct pci_dev *pdev);
147 #define ath5k_pci_suspend NULL
148 #define ath5k_pci_resume NULL
149 #endif /* CONFIG_PM */
151 static struct pci_driver ath5k_pci_driver = {
153 .id_table = ath5k_pci_id_table,
154 .probe = ath5k_pci_probe,
155 .remove = __devexit_p(ath5k_pci_remove),
156 .suspend = ath5k_pci_suspend,
157 .resume = ath5k_pci_resume,
163 * Prototypes - MAC 802.11 stack related functions
165 static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
166 static int ath5k_reset(struct ieee80211_hw *hw);
167 static int ath5k_start(struct ieee80211_hw *hw);
168 static void ath5k_stop(struct ieee80211_hw *hw);
169 static int ath5k_add_interface(struct ieee80211_hw *hw,
170 struct ieee80211_if_init_conf *conf);
171 static void ath5k_remove_interface(struct ieee80211_hw *hw,
172 struct ieee80211_if_init_conf *conf);
173 static int ath5k_config(struct ieee80211_hw *hw,
174 struct ieee80211_conf *conf);
175 static int ath5k_config_interface(struct ieee80211_hw *hw,
176 struct ieee80211_vif *vif,
177 struct ieee80211_if_conf *conf);
178 static void ath5k_configure_filter(struct ieee80211_hw *hw,
179 unsigned int changed_flags,
180 unsigned int *new_flags,
181 int mc_count, struct dev_mc_list *mclist);
182 static int ath5k_set_key(struct ieee80211_hw *hw,
183 enum set_key_cmd cmd,
184 const u8 *local_addr, const u8 *addr,
185 struct ieee80211_key_conf *key);
186 static int ath5k_get_stats(struct ieee80211_hw *hw,
187 struct ieee80211_low_level_stats *stats);
188 static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
189 struct ieee80211_tx_queue_stats *stats);
190 static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
191 static void ath5k_reset_tsf(struct ieee80211_hw *hw);
192 static int ath5k_beacon_update(struct ieee80211_hw *hw,
193 struct sk_buff *skb);
195 static struct ieee80211_ops ath5k_hw_ops = {
197 .start = ath5k_start,
199 .add_interface = ath5k_add_interface,
200 .remove_interface = ath5k_remove_interface,
201 .config = ath5k_config,
202 .config_interface = ath5k_config_interface,
203 .configure_filter = ath5k_configure_filter,
204 .set_key = ath5k_set_key,
205 .get_stats = ath5k_get_stats,
207 .get_tx_stats = ath5k_get_tx_stats,
208 .get_tsf = ath5k_get_tsf,
209 .reset_tsf = ath5k_reset_tsf,
213 * Prototypes - Internal functions
216 static int ath5k_attach(struct pci_dev *pdev,
217 struct ieee80211_hw *hw);
218 static void ath5k_detach(struct pci_dev *pdev,
219 struct ieee80211_hw *hw);
220 /* Channel/mode setup */
221 static inline short ath5k_ieee2mhz(short chan);
222 static unsigned int ath5k_copy_rates(struct ieee80211_rate *rates,
223 const struct ath5k_rate_table *rt,
225 static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
226 struct ieee80211_channel *channels,
229 static int ath5k_getchannels(struct ieee80211_hw *hw);
230 static int ath5k_chan_set(struct ath5k_softc *sc,
231 struct ieee80211_channel *chan);
232 static void ath5k_setcurmode(struct ath5k_softc *sc,
234 static void ath5k_mode_setup(struct ath5k_softc *sc);
235 static void ath5k_set_total_hw_rates(struct ath5k_softc *sc);
237 /* Descriptor setup */
238 static int ath5k_desc_alloc(struct ath5k_softc *sc,
239 struct pci_dev *pdev);
240 static void ath5k_desc_free(struct ath5k_softc *sc,
241 struct pci_dev *pdev);
243 static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
244 struct ath5k_buf *bf);
245 static int ath5k_txbuf_setup(struct ath5k_softc *sc,
246 struct ath5k_buf *bf);
247 static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
248 struct ath5k_buf *bf)
253 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
255 dev_kfree_skb(bf->skb);
260 static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
261 int qtype, int subtype);
262 static int ath5k_beaconq_setup(struct ath5k_hw *ah);
263 static int ath5k_beaconq_config(struct ath5k_softc *sc);
264 static void ath5k_txq_drainq(struct ath5k_softc *sc,
265 struct ath5k_txq *txq);
266 static void ath5k_txq_cleanup(struct ath5k_softc *sc);
267 static void ath5k_txq_release(struct ath5k_softc *sc);
269 static int ath5k_rx_start(struct ath5k_softc *sc);
270 static void ath5k_rx_stop(struct ath5k_softc *sc);
271 static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
272 struct ath5k_desc *ds,
274 struct ath5k_rx_status *rs);
275 static void ath5k_tasklet_rx(unsigned long data);
277 static void ath5k_tx_processq(struct ath5k_softc *sc,
278 struct ath5k_txq *txq);
279 static void ath5k_tasklet_tx(unsigned long data);
280 /* Beacon handling */
281 static int ath5k_beacon_setup(struct ath5k_softc *sc,
282 struct ath5k_buf *bf);
283 static void ath5k_beacon_send(struct ath5k_softc *sc);
284 static void ath5k_beacon_config(struct ath5k_softc *sc);
285 static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
287 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
289 u64 tsf = ath5k_hw_get_tsf64(ah);
291 if ((tsf & 0x7fff) < rstamp)
294 return (tsf & ~0x7fff) | rstamp;
297 /* Interrupt handling */
298 static int ath5k_init(struct ath5k_softc *sc);
299 static int ath5k_stop_locked(struct ath5k_softc *sc);
300 static int ath5k_stop_hw(struct ath5k_softc *sc);
301 static irqreturn_t ath5k_intr(int irq, void *dev_id);
302 static void ath5k_tasklet_reset(unsigned long data);
304 static void ath5k_calibrate(unsigned long data);
306 static int ath5k_init_leds(struct ath5k_softc *sc);
307 static void ath5k_led_enable(struct ath5k_softc *sc);
308 static void ath5k_led_off(struct ath5k_softc *sc);
309 static void ath5k_unregister_leds(struct ath5k_softc *sc);
312 * Module init/exit functions
321 ret = pci_register_driver(&ath5k_pci_driver);
323 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
333 pci_unregister_driver(&ath5k_pci_driver);
335 ath5k_debug_finish();
338 module_init(init_ath5k_pci);
339 module_exit(exit_ath5k_pci);
342 /********************\
343 * PCI Initialization *
344 \********************/
347 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
349 const char *name = "xxxxx";
352 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
353 if (srev_names[i].sr_type != type)
355 if ((val & 0xff) < srev_names[i + 1].sr_val) {
356 name = srev_names[i].sr_name;
365 ath5k_pci_probe(struct pci_dev *pdev,
366 const struct pci_device_id *id)
369 struct ath5k_softc *sc;
370 struct ieee80211_hw *hw;
374 ret = pci_enable_device(pdev);
376 dev_err(&pdev->dev, "can't enable device\n");
380 /* XXX 32-bit addressing only */
381 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
383 dev_err(&pdev->dev, "32-bit DMA not available\n");
388 * Cache line size is used to size and align various
389 * structures used to communicate with the hardware.
391 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
394 * Linux 2.4.18 (at least) writes the cache line size
395 * register as a 16-bit wide register which is wrong.
396 * We must have this setup properly for rx buffer
397 * DMA to work so force a reasonable value here if it
400 csz = L1_CACHE_BYTES / sizeof(u32);
401 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
404 * The default setting of latency timer yields poor results,
405 * set it to the value used by other systems. It may be worth
406 * tweaking this setting more.
408 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
410 /* Enable bus mastering */
411 pci_set_master(pdev);
414 * Disable the RETRY_TIMEOUT register (0x41) to keep
415 * PCI Tx retries from interfering with C3 CPU state.
417 pci_write_config_byte(pdev, 0x41, 0);
419 ret = pci_request_region(pdev, 0, "ath5k");
421 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
425 mem = pci_iomap(pdev, 0, 0);
427 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
433 * Allocate hw (mac80211 main struct)
434 * and hw->priv (driver private data)
436 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
438 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
443 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
445 /* Initialize driver private data */
446 SET_IEEE80211_DEV(hw, &pdev->dev);
447 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
448 IEEE80211_HW_SIGNAL_DBM |
449 IEEE80211_HW_NOISE_DBM;
450 hw->extra_tx_headroom = 2;
451 hw->channel_change_time = 5000;
456 ath5k_debug_init_device(sc);
459 * Mark the device as detached to avoid processing
460 * interrupts until setup is complete.
462 __set_bit(ATH_STAT_INVALID, sc->status);
464 sc->iobase = mem; /* So we can unmap it on detach */
465 sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
466 sc->opmode = IEEE80211_IF_TYPE_STA;
467 mutex_init(&sc->lock);
468 spin_lock_init(&sc->rxbuflock);
469 spin_lock_init(&sc->txbuflock);
471 /* Set private data */
472 pci_set_drvdata(pdev, hw);
474 /* Enable msi for devices that support it */
475 pci_enable_msi(pdev);
477 /* Setup interrupt handler */
478 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
480 ATH5K_ERR(sc, "request_irq failed\n");
484 /* Initialize device */
485 sc->ah = ath5k_hw_attach(sc, id->driver_data);
486 if (IS_ERR(sc->ah)) {
487 ret = PTR_ERR(sc->ah);
491 /* Finish private driver data initialization */
492 ret = ath5k_attach(pdev, hw);
496 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
497 ath5k_chip_name(AR5K_VERSION_VER,sc->ah->ah_mac_srev),
499 sc->ah->ah_phy_revision);
501 if (!sc->ah->ah_single_chip) {
502 /* Single chip radio (!RF5111) */
503 if (sc->ah->ah_radio_5ghz_revision &&
504 !sc->ah->ah_radio_2ghz_revision) {
505 /* No 5GHz support -> report 2GHz radio */
506 if (!test_bit(AR5K_MODE_11A,
507 sc->ah->ah_capabilities.cap_mode)) {
508 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
509 ath5k_chip_name(AR5K_VERSION_RAD,
510 sc->ah->ah_radio_5ghz_revision),
511 sc->ah->ah_radio_5ghz_revision);
512 /* No 2GHz support (5110 and some
513 * 5Ghz only cards) -> report 5Ghz radio */
514 } else if (!test_bit(AR5K_MODE_11B,
515 sc->ah->ah_capabilities.cap_mode)) {
516 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
517 ath5k_chip_name(AR5K_VERSION_RAD,
518 sc->ah->ah_radio_5ghz_revision),
519 sc->ah->ah_radio_5ghz_revision);
520 /* Multiband radio */
522 ATH5K_INFO(sc, "RF%s multiband radio found"
524 ath5k_chip_name(AR5K_VERSION_RAD,
525 sc->ah->ah_radio_5ghz_revision),
526 sc->ah->ah_radio_5ghz_revision);
529 /* Multi chip radio (RF5111 - RF2111) ->
530 * report both 2GHz/5GHz radios */
531 else if (sc->ah->ah_radio_5ghz_revision &&
532 sc->ah->ah_radio_2ghz_revision){
533 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
534 ath5k_chip_name(AR5K_VERSION_RAD,
535 sc->ah->ah_radio_5ghz_revision),
536 sc->ah->ah_radio_5ghz_revision);
537 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
538 ath5k_chip_name(AR5K_VERSION_RAD,
539 sc->ah->ah_radio_2ghz_revision),
540 sc->ah->ah_radio_2ghz_revision);
545 /* ready to process interrupts */
546 __clear_bit(ATH_STAT_INVALID, sc->status);
550 ath5k_hw_detach(sc->ah);
552 free_irq(pdev->irq, sc);
554 pci_disable_msi(pdev);
555 ieee80211_free_hw(hw);
557 pci_iounmap(pdev, mem);
559 pci_release_region(pdev, 0);
561 pci_disable_device(pdev);
566 static void __devexit
567 ath5k_pci_remove(struct pci_dev *pdev)
569 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
570 struct ath5k_softc *sc = hw->priv;
572 ath5k_debug_finish_device(sc);
573 ath5k_detach(pdev, hw);
574 ath5k_hw_detach(sc->ah);
575 free_irq(pdev->irq, sc);
576 pci_disable_msi(pdev);
577 pci_iounmap(pdev, sc->iobase);
578 pci_release_region(pdev, 0);
579 pci_disable_device(pdev);
580 ieee80211_free_hw(hw);
585 ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
587 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
588 struct ath5k_softc *sc = hw->priv;
593 pci_save_state(pdev);
594 pci_disable_device(pdev);
595 pci_set_power_state(pdev, PCI_D3hot);
601 ath5k_pci_resume(struct pci_dev *pdev)
603 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
604 struct ath5k_softc *sc = hw->priv;
605 struct ath5k_hw *ah = sc->ah;
608 err = pci_set_power_state(pdev, PCI_D0);
612 err = pci_enable_device(pdev);
616 pci_restore_state(pdev);
618 * Suspend/Resume resets the PCI configuration space, so we have to
619 * re-disable the RETRY_TIMEOUT register (0x41) to keep
620 * PCI Tx retries from interfering with C3 CPU state
622 pci_write_config_byte(pdev, 0x41, 0);
625 ath5k_led_enable(sc);
628 * Reset the key cache since some parts do not
629 * reset the contents on initial power up or resume.
631 * FIXME: This may need to be revisited when mac80211 becomes
632 * aware of suspend/resume.
634 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
635 ath5k_hw_reset_key(ah, i);
639 #endif /* CONFIG_PM */
643 /***********************\
644 * Driver Initialization *
645 \***********************/
648 ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
650 struct ath5k_softc *sc = hw->priv;
651 struct ath5k_hw *ah = sc->ah;
656 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
659 * Check if the MAC has multi-rate retry support.
660 * We do this by trying to setup a fake extended
661 * descriptor. MAC's that don't have support will
662 * return false w/o doing anything. MAC's that do
663 * support it will return true w/o doing anything.
665 ret = ah->ah_setup_xtx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
669 __set_bit(ATH_STAT_MRRETRY, sc->status);
672 * Reset the key cache since some parts do not
673 * reset the contents on initial power up.
675 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
676 ath5k_hw_reset_key(ah, i);
679 * Collect the channel list. The 802.11 layer
680 * is resposible for filtering this list based
681 * on settings like the phy mode and regulatory
682 * domain restrictions.
684 ret = ath5k_getchannels(hw);
686 ATH5K_ERR(sc, "can't get channels\n");
690 /* Set *_rates so we can map hw rate index */
691 ath5k_set_total_hw_rates(sc);
693 /* NB: setup here so ath5k_rate_update is happy */
694 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
695 ath5k_setcurmode(sc, AR5K_MODE_11A);
697 ath5k_setcurmode(sc, AR5K_MODE_11B);
700 * Allocate tx+rx descriptors and populate the lists.
702 ret = ath5k_desc_alloc(sc, pdev);
704 ATH5K_ERR(sc, "can't allocate descriptors\n");
709 * Allocate hardware transmit queues: one queue for
710 * beacon frames and one data queue for each QoS
711 * priority. Note that hw functions handle reseting
712 * these queues at the needed time.
714 ret = ath5k_beaconq_setup(ah);
716 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
721 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
722 if (IS_ERR(sc->txq)) {
723 ATH5K_ERR(sc, "can't setup xmit queue\n");
724 ret = PTR_ERR(sc->txq);
728 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
729 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
730 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
731 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
733 ath5k_hw_get_lladdr(ah, mac);
734 SET_IEEE80211_PERM_ADDR(hw, mac);
735 /* All MAC address bits matter for ACKs */
736 memset(sc->bssidmask, 0xff, ETH_ALEN);
737 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
739 ret = ieee80211_register_hw(hw);
741 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
749 ath5k_txq_release(sc);
751 ath5k_hw_release_tx_queue(ah, sc->bhalq);
753 ath5k_desc_free(sc, pdev);
759 ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
761 struct ath5k_softc *sc = hw->priv;
764 * NB: the order of these is important:
765 * o call the 802.11 layer before detaching ath5k_hw to
766 * insure callbacks into the driver to delete global
767 * key cache entries can be handled
768 * o reclaim the tx queue data structures after calling
769 * the 802.11 layer as we'll get called back to reclaim
770 * node state and potentially want to use them
771 * o to cleanup the tx queues the hal is called, so detach
773 * XXX: ??? detach ath5k_hw ???
774 * Other than that, it's straightforward...
776 ieee80211_unregister_hw(hw);
777 ath5k_desc_free(sc, pdev);
778 ath5k_txq_release(sc);
779 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
780 ath5k_unregister_leds(sc);
783 * NB: can't reclaim these until after ieee80211_ifdetach
784 * returns because we'll get called back to reclaim node
785 * state and potentially want to use them.
792 /********************\
793 * Channel/mode setup *
794 \********************/
797 * Convert IEEE channel number to MHz frequency.
800 ath5k_ieee2mhz(short chan)
802 if (chan <= 14 || chan >= 27)
803 return ieee80211chan2mhz(chan);
805 return 2212 + chan * 20;
809 ath5k_copy_rates(struct ieee80211_rate *rates,
810 const struct ath5k_rate_table *rt,
813 unsigned int i, count;
818 for (i = 0, count = 0; i < rt->rate_count && max > 0; i++) {
819 rates[count].bitrate = rt->rates[i].rate_kbps / 100;
820 rates[count].hw_value = rt->rates[i].rate_code;
821 rates[count].flags = rt->rates[i].modulation;
830 ath5k_copy_channels(struct ath5k_hw *ah,
831 struct ieee80211_channel *channels,
835 unsigned int i, count, size, chfreq, freq, ch;
837 if (!test_bit(mode, ah->ah_modes))
842 case AR5K_MODE_11A_TURBO:
843 /* 1..220, but 2GHz frequencies are filtered by check_channel */
845 chfreq = CHANNEL_5GHZ;
849 case AR5K_MODE_11G_TURBO:
851 chfreq = CHANNEL_2GHZ;
854 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
858 for (i = 0, count = 0; i < size && max > 0; i++) {
860 freq = ath5k_ieee2mhz(ch);
862 /* Check if channel is supported by the chipset */
863 if (!ath5k_channel_ok(ah, freq, chfreq))
866 /* Write channel info and increment counter */
867 channels[count].center_freq = freq;
868 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
869 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
873 channels[count].hw_value = chfreq | CHANNEL_OFDM;
875 case AR5K_MODE_11A_TURBO:
876 case AR5K_MODE_11G_TURBO:
877 channels[count].hw_value = chfreq |
878 CHANNEL_OFDM | CHANNEL_TURBO;
881 channels[count].hw_value = CHANNEL_B;
892 ath5k_getchannels(struct ieee80211_hw *hw)
894 struct ath5k_softc *sc = hw->priv;
895 struct ath5k_hw *ah = sc->ah;
896 struct ieee80211_supported_band *sbands = sc->sbands;
897 const struct ath5k_rate_table *hw_rates;
898 unsigned int max_r, max_c, count_r, count_c;
899 int mode2g = AR5K_MODE_11G;
901 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
903 max_r = ARRAY_SIZE(sc->rates);
904 max_c = ARRAY_SIZE(sc->channels);
905 count_r = count_c = 0;
908 if (!test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
909 mode2g = AR5K_MODE_11B;
910 if (!test_bit(AR5K_MODE_11B,
911 sc->ah->ah_capabilities.cap_mode))
916 struct ieee80211_supported_band *sband =
917 &sbands[IEEE80211_BAND_2GHZ];
919 sband->bitrates = sc->rates;
920 sband->channels = sc->channels;
922 sband->band = IEEE80211_BAND_2GHZ;
923 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
926 hw_rates = ath5k_hw_get_rate_table(ah, mode2g);
927 sband->n_bitrates = ath5k_copy_rates(sband->bitrates,
930 count_c = sband->n_channels;
931 count_r = sband->n_bitrates;
933 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
942 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
943 struct ieee80211_supported_band *sband =
944 &sbands[IEEE80211_BAND_5GHZ];
946 sband->bitrates = &sc->rates[count_r];
947 sband->channels = &sc->channels[count_c];
949 sband->band = IEEE80211_BAND_5GHZ;
950 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
951 AR5K_MODE_11A, max_c);
953 hw_rates = ath5k_hw_get_rate_table(ah, AR5K_MODE_11A);
954 sband->n_bitrates = ath5k_copy_rates(sband->bitrates,
957 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
960 ath5k_debug_dump_bands(sc);
966 * Set/change channels. If the channel is really being changed,
967 * it's done by reseting the chip. To accomplish this we must
968 * first cleanup any pending DMA, then restart stuff after a la
972 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
974 struct ath5k_hw *ah = sc->ah;
977 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
978 sc->curchan->center_freq, chan->center_freq);
980 if (chan->center_freq != sc->curchan->center_freq ||
981 chan->hw_value != sc->curchan->hw_value) {
984 sc->curband = &sc->sbands[chan->band];
987 * To switch channels clear any pending DMA operations;
988 * wait long enough for the RX fifo to drain, reset the
989 * hardware at the new frequency, and then re-enable
990 * the relevant bits of the h/w.
992 ath5k_hw_set_intr(ah, 0); /* disable interrupts */
993 ath5k_txq_cleanup(sc); /* clear pending tx frames */
994 ath5k_rx_stop(sc); /* turn off frame recv */
995 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
997 ATH5K_ERR(sc, "%s: unable to reset channel "
998 "(%u Mhz)\n", __func__, chan->center_freq);
1002 ath5k_hw_set_txpower_limit(sc->ah, 0);
1005 * Re-enable rx framework.
1007 ret = ath5k_rx_start(sc);
1009 ATH5K_ERR(sc, "%s: unable to restart recv logic\n",
1015 * Change channels and update the h/w rate map
1016 * if we're switching; e.g. 11a to 11b/g.
1020 /* ath5k_chan_change(sc, chan); */
1022 ath5k_beacon_config(sc);
1024 * Re-enable interrupts.
1026 ath5k_hw_set_intr(ah, sc->imask);
1033 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1037 if (mode == AR5K_MODE_11A) {
1038 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1040 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1045 ath5k_mode_setup(struct ath5k_softc *sc)
1047 struct ath5k_hw *ah = sc->ah;
1050 /* configure rx filter */
1051 rfilt = sc->filter_flags;
1052 ath5k_hw_set_rx_filter(ah, rfilt);
1054 if (ath5k_hw_hasbssidmask(ah))
1055 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1057 /* configure operational mode */
1058 ath5k_hw_set_opmode(ah);
1060 ath5k_hw_set_mcast_filter(ah, 0, 0);
1061 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1065 * Match the hw provided rate index (through descriptors)
1066 * to an index for sc->curband->bitrates, so it can be used
1069 * This one is a little bit tricky but i think i'm right
1072 * We have 4 rate tables in the following order:
1076 * 802.11g (12 rates)
1077 * that make the hw rate table.
1079 * Lets take a 5211 for example that supports a and b modes only.
1080 * First comes the 802.11a table and then 802.11b (total 12 rates).
1081 * When hw returns eg. 11 it points to the last 802.11b rate (11Mbit),
1082 * if it returns 2 it points to the second 802.11a rate etc.
1084 * Same goes for 5212 who has xr/a/b/g support (total 28 rates).
1085 * First comes the XR table, then 802.11a, 802.11b and 802.11g.
1086 * When hw returns eg. 27 it points to the last 802.11g rate (54Mbits) etc
1089 ath5k_set_total_hw_rates(struct ath5k_softc *sc) {
1091 struct ath5k_hw *ah = sc->ah;
1093 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
1096 if (test_bit(AR5K_MODE_11B, ah->ah_modes))
1099 if (test_bit(AR5K_MODE_11G, ah->ah_modes))
1102 /* XXX: Need to see what what happens when
1103 xr disable bits in eeprom are set */
1104 if (ah->ah_version >= AR5K_AR5212)
1110 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix) {
1114 if(sc->curband->band == IEEE80211_BAND_2GHZ) {
1115 /* We setup a g ratetable for both b/g modes */
1117 hw_rix - sc->b_rates - sc->a_rates - sc->xr_rates;
1119 mac80211_rix = hw_rix - sc->xr_rates;
1122 /* Something went wrong, fallback to basic rate for this band */
1123 if ((mac80211_rix >= sc->curband->n_bitrates) ||
1124 (mac80211_rix <= 0 ))
1127 return mac80211_rix;
1138 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1140 struct ath5k_hw *ah = sc->ah;
1141 struct sk_buff *skb = bf->skb;
1142 struct ath5k_desc *ds;
1144 if (likely(skb == NULL)) {
1148 * Allocate buffer with headroom_needed space for the
1149 * fake physical layer header at the start.
1151 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1152 if (unlikely(skb == NULL)) {
1153 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1154 sc->rxbufsize + sc->cachelsz - 1);
1158 * Cache-line-align. This is important (for the
1159 * 5210 at least) as not doing so causes bogus data
1162 off = ((unsigned long)skb->data) % sc->cachelsz;
1164 skb_reserve(skb, sc->cachelsz - off);
1167 bf->skbaddr = pci_map_single(sc->pdev,
1168 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1169 if (unlikely(pci_dma_mapping_error(sc->pdev, bf->skbaddr))) {
1170 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1178 * Setup descriptors. For receive we always terminate
1179 * the descriptor list with a self-linked entry so we'll
1180 * not get overrun under high load (as can happen with a
1181 * 5212 when ANI processing enables PHY error frames).
1183 * To insure the last descriptor is self-linked we create
1184 * each descriptor as self-linked and add it to the end. As
1185 * each additional descriptor is added the previous self-linked
1186 * entry is ``fixed'' naturally. This should be safe even
1187 * if DMA is happening. When processing RX interrupts we
1188 * never remove/process the last, self-linked, entry on the
1189 * descriptor list. This insures the hardware always has
1190 * someplace to write a new frame.
1193 ds->ds_link = bf->daddr; /* link to self */
1194 ds->ds_data = bf->skbaddr;
1195 ath5k_hw_setup_rx_desc(ah, ds,
1196 skb_tailroom(skb), /* buffer size */
1199 if (sc->rxlink != NULL)
1200 *sc->rxlink = bf->daddr;
1201 sc->rxlink = &ds->ds_link;
1206 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1208 struct ath5k_hw *ah = sc->ah;
1209 struct ath5k_txq *txq = sc->txq;
1210 struct ath5k_desc *ds = bf->desc;
1211 struct sk_buff *skb = bf->skb;
1212 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1213 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1216 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
1218 /* XXX endianness */
1219 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1222 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
1223 flags |= AR5K_TXDESC_NOACK;
1227 if (!(info->flags & IEEE80211_TX_CTL_DO_NOT_ENCRYPT)) {
1228 keyidx = info->control.hw_key->hw_key_idx;
1229 pktlen += info->control.icv_len;
1231 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1232 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
1233 (sc->power_level * 2),
1234 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
1235 info->control.retry_limit, keyidx, 0, flags, 0, 0);
1240 ds->ds_data = bf->skbaddr;
1242 spin_lock_bh(&txq->lock);
1243 list_add_tail(&bf->list, &txq->q);
1244 sc->tx_stats[txq->qnum].len++;
1245 if (txq->link == NULL) /* is this first packet? */
1246 ath5k_hw_put_tx_buf(ah, txq->qnum, bf->daddr);
1247 else /* no, so only link it */
1248 *txq->link = bf->daddr;
1250 txq->link = &ds->ds_link;
1251 ath5k_hw_tx_start(ah, txq->qnum);
1252 spin_unlock_bh(&txq->lock);
1256 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1260 /*******************\
1261 * Descriptors setup *
1262 \*******************/
1265 ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1267 struct ath5k_desc *ds;
1268 struct ath5k_buf *bf;
1273 /* allocate descriptors */
1274 sc->desc_len = sizeof(struct ath5k_desc) *
1275 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1276 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1277 if (sc->desc == NULL) {
1278 ATH5K_ERR(sc, "can't allocate descriptors\n");
1283 da = sc->desc_daddr;
1284 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1285 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1287 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1288 sizeof(struct ath5k_buf), GFP_KERNEL);
1290 ATH5K_ERR(sc, "can't allocate bufptr\n");
1296 INIT_LIST_HEAD(&sc->rxbuf);
1297 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1300 list_add_tail(&bf->list, &sc->rxbuf);
1303 INIT_LIST_HEAD(&sc->txbuf);
1304 sc->txbuf_len = ATH_TXBUF;
1305 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1306 da += sizeof(*ds)) {
1309 list_add_tail(&bf->list, &sc->txbuf);
1319 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1326 ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1328 struct ath5k_buf *bf;
1330 ath5k_txbuf_free(sc, sc->bbuf);
1331 list_for_each_entry(bf, &sc->txbuf, list)
1332 ath5k_txbuf_free(sc, bf);
1333 list_for_each_entry(bf, &sc->rxbuf, list)
1334 ath5k_txbuf_free(sc, bf);
1336 /* Free memory associated with all descriptors */
1337 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1351 static struct ath5k_txq *
1352 ath5k_txq_setup(struct ath5k_softc *sc,
1353 int qtype, int subtype)
1355 struct ath5k_hw *ah = sc->ah;
1356 struct ath5k_txq *txq;
1357 struct ath5k_txq_info qi = {
1358 .tqi_subtype = subtype,
1359 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1360 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1361 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1366 * Enable interrupts only for EOL and DESC conditions.
1367 * We mark tx descriptors to receive a DESC interrupt
1368 * when a tx queue gets deep; otherwise waiting for the
1369 * EOL to reap descriptors. Note that this is done to
1370 * reduce interrupt load and this only defers reaping
1371 * descriptors, never transmitting frames. Aside from
1372 * reducing interrupts this also permits more concurrency.
1373 * The only potential downside is if the tx queue backs
1374 * up in which case the top half of the kernel may backup
1375 * due to a lack of tx descriptors.
1377 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1378 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1379 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1382 * NB: don't print a message, this happens
1383 * normally on parts with too few tx queues
1385 return ERR_PTR(qnum);
1387 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1388 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1389 qnum, ARRAY_SIZE(sc->txqs));
1390 ath5k_hw_release_tx_queue(ah, qnum);
1391 return ERR_PTR(-EINVAL);
1393 txq = &sc->txqs[qnum];
1397 INIT_LIST_HEAD(&txq->q);
1398 spin_lock_init(&txq->lock);
1401 return &sc->txqs[qnum];
1405 ath5k_beaconq_setup(struct ath5k_hw *ah)
1407 struct ath5k_txq_info qi = {
1408 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1409 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1410 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1411 /* NB: for dynamic turbo, don't enable any other interrupts */
1412 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1415 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1419 ath5k_beaconq_config(struct ath5k_softc *sc)
1421 struct ath5k_hw *ah = sc->ah;
1422 struct ath5k_txq_info qi;
1425 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1428 if (sc->opmode == IEEE80211_IF_TYPE_AP) {
1430 * Always burst out beacon and CAB traffic
1431 * (aifs = cwmin = cwmax = 0)
1436 } else if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
1438 * Adhoc mode; backoff between 0 and (2 * cw_min).
1442 qi.tqi_cw_max = 2 * ah->ah_cw_min;
1445 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1446 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1447 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1449 ret = ath5k_hw_setup_tx_queueprops(ah, sc->bhalq, &qi);
1451 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1452 "hardware queue!\n", __func__);
1456 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1460 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1462 struct ath5k_buf *bf, *bf0;
1465 * NB: this assumes output has been stopped and
1466 * we do not need to block ath5k_tx_tasklet
1468 spin_lock_bh(&txq->lock);
1469 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1470 ath5k_debug_printtxbuf(sc, bf);
1472 ath5k_txbuf_free(sc, bf);
1474 spin_lock_bh(&sc->txbuflock);
1475 sc->tx_stats[txq->qnum].len--;
1476 list_move_tail(&bf->list, &sc->txbuf);
1478 spin_unlock_bh(&sc->txbuflock);
1481 spin_unlock_bh(&txq->lock);
1485 * Drain the transmit queues and reclaim resources.
1488 ath5k_txq_cleanup(struct ath5k_softc *sc)
1490 struct ath5k_hw *ah = sc->ah;
1493 /* XXX return value */
1494 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1495 /* don't touch the hardware if marked invalid */
1496 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1497 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1498 ath5k_hw_get_tx_buf(ah, sc->bhalq));
1499 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1500 if (sc->txqs[i].setup) {
1501 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1502 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1505 ath5k_hw_get_tx_buf(ah,
1510 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
1512 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1513 if (sc->txqs[i].setup)
1514 ath5k_txq_drainq(sc, &sc->txqs[i]);
1518 ath5k_txq_release(struct ath5k_softc *sc)
1520 struct ath5k_txq *txq = sc->txqs;
1523 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1525 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1538 * Enable the receive h/w following a reset.
1541 ath5k_rx_start(struct ath5k_softc *sc)
1543 struct ath5k_hw *ah = sc->ah;
1544 struct ath5k_buf *bf;
1547 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1549 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1550 sc->cachelsz, sc->rxbufsize);
1554 spin_lock_bh(&sc->rxbuflock);
1555 list_for_each_entry(bf, &sc->rxbuf, list) {
1556 ret = ath5k_rxbuf_setup(sc, bf);
1558 spin_unlock_bh(&sc->rxbuflock);
1562 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1563 spin_unlock_bh(&sc->rxbuflock);
1565 ath5k_hw_put_rx_buf(ah, bf->daddr);
1566 ath5k_hw_start_rx(ah); /* enable recv descriptors */
1567 ath5k_mode_setup(sc); /* set filters, etc. */
1568 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1576 * Disable the receive h/w in preparation for a reset.
1579 ath5k_rx_stop(struct ath5k_softc *sc)
1581 struct ath5k_hw *ah = sc->ah;
1583 ath5k_hw_stop_pcu_recv(ah); /* disable PCU */
1584 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1585 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
1586 mdelay(3); /* 3ms is long enough for 1 frame */
1588 ath5k_debug_printrxbuffs(sc, ah);
1590 sc->rxlink = NULL; /* just in case */
1594 ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
1595 struct sk_buff *skb, struct ath5k_rx_status *rs)
1597 struct ieee80211_hdr *hdr = (void *)skb->data;
1598 unsigned int keyix, hlen = ieee80211_get_hdrlen_from_skb(skb);
1600 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1601 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1602 return RX_FLAG_DECRYPTED;
1604 /* Apparently when a default key is used to decrypt the packet
1605 the hw does not set the index used to decrypt. In such cases
1606 get the index from the packet. */
1607 if (ieee80211_has_protected(hdr->frame_control) &&
1608 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1609 skb->len >= hlen + 4) {
1610 keyix = skb->data[hlen + 3] >> 6;
1612 if (test_bit(keyix, sc->keymap))
1613 return RX_FLAG_DECRYPTED;
1621 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1622 struct ieee80211_rx_status *rxs)
1626 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1628 if (ieee80211_is_beacon(mgmt->frame_control) &&
1629 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1630 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1632 * Received an IBSS beacon with the same BSSID. Hardware *must*
1633 * have updated the local TSF. We have to work around various
1634 * hardware bugs, though...
1636 tsf = ath5k_hw_get_tsf64(sc->ah);
1637 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1638 hw_tu = TSF_TO_TU(tsf);
1640 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1641 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1642 (unsigned long long)bc_tstamp,
1643 (unsigned long long)rxs->mactime,
1644 (unsigned long long)(rxs->mactime - bc_tstamp),
1645 (unsigned long long)tsf);
1648 * Sometimes the HW will give us a wrong tstamp in the rx
1649 * status, causing the timestamp extension to go wrong.
1650 * (This seems to happen especially with beacon frames bigger
1651 * than 78 byte (incl. FCS))
1652 * But we know that the receive timestamp must be later than the
1653 * timestamp of the beacon since HW must have synced to that.
1655 * NOTE: here we assume mactime to be after the frame was
1656 * received, not like mac80211 which defines it at the start.
1658 if (bc_tstamp > rxs->mactime) {
1659 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1660 "fixing mactime from %llx to %llx\n",
1661 (unsigned long long)rxs->mactime,
1662 (unsigned long long)tsf);
1667 * Local TSF might have moved higher than our beacon timers,
1668 * in that case we have to update them to continue sending
1669 * beacons. This also takes care of synchronizing beacon sending
1670 * times with other stations.
1672 if (hw_tu >= sc->nexttbtt)
1673 ath5k_beacon_update_timers(sc, bc_tstamp);
1679 ath5k_tasklet_rx(unsigned long data)
1681 struct ieee80211_rx_status rxs = {};
1682 struct ath5k_rx_status rs = {};
1683 struct sk_buff *skb;
1684 struct ath5k_softc *sc = (void *)data;
1685 struct ath5k_buf *bf, *bf_last;
1686 struct ath5k_desc *ds;
1691 spin_lock(&sc->rxbuflock);
1692 if (list_empty(&sc->rxbuf)) {
1693 ATH5K_WARN(sc, "empty rx buf pool\n");
1696 bf_last = list_entry(sc->rxbuf.prev, struct ath5k_buf, list);
1700 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1701 BUG_ON(bf->skb == NULL);
1705 /* TODO only one segment */
1706 pci_dma_sync_single_for_cpu(sc->pdev, sc->desc_daddr,
1707 sc->desc_len, PCI_DMA_FROMDEVICE);
1710 * last buffer must not be freed to ensure proper hardware
1711 * function. When the hardware finishes also a packet next to
1712 * it, we are sure, it doesn't use it anymore and we can go on.
1717 struct ath5k_buf *bf_next = list_entry(bf->list.next,
1718 struct ath5k_buf, list);
1719 ret = sc->ah->ah_proc_rx_desc(sc->ah, bf_next->desc,
1724 /* skip the overwritten one (even status is martian) */
1728 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1729 if (unlikely(ret == -EINPROGRESS))
1731 else if (unlikely(ret)) {
1732 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1733 spin_unlock(&sc->rxbuflock);
1737 if (unlikely(rs.rs_more)) {
1738 ATH5K_WARN(sc, "unsupported jumbo\n");
1742 if (unlikely(rs.rs_status)) {
1743 if (rs.rs_status & AR5K_RXERR_PHY)
1745 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
1747 * Decrypt error. If the error occurred
1748 * because there was no hardware key, then
1749 * let the frame through so the upper layers
1750 * can process it. This is necessary for 5210
1751 * parts which have no way to setup a ``clear''
1754 * XXX do key cache faulting
1756 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1757 !(rs.rs_status & AR5K_RXERR_CRC))
1760 if (rs.rs_status & AR5K_RXERR_MIC) {
1761 rxs.flag |= RX_FLAG_MMIC_ERROR;
1765 /* let crypto-error packets fall through in MNTR */
1767 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
1768 sc->opmode != IEEE80211_IF_TYPE_MNTR)
1772 pci_dma_sync_single_for_cpu(sc->pdev, bf->skbaddr,
1773 rs.rs_datalen, PCI_DMA_FROMDEVICE);
1774 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1775 PCI_DMA_FROMDEVICE);
1778 skb_put(skb, rs.rs_datalen);
1781 * the hardware adds a padding to 4 byte boundaries between
1782 * the header and the payload data if the header length is
1783 * not multiples of 4 - remove it
1785 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1788 memmove(skb->data + pad, skb->data, hdrlen);
1793 * always extend the mac timestamp, since this information is
1794 * also needed for proper IBSS merging.
1796 * XXX: it might be too late to do it here, since rs_tstamp is
1797 * 15bit only. that means TSF extension has to be done within
1798 * 32768usec (about 32ms). it might be necessary to move this to
1799 * the interrupt handler, like it is done in madwifi.
1801 * Unfortunately we don't know when the hardware takes the rx
1802 * timestamp (beginning of phy frame, data frame, end of rx?).
1803 * The only thing we know is that it is hardware specific...
1804 * On AR5213 it seems the rx timestamp is at the end of the
1805 * frame, but i'm not sure.
1807 * NOTE: mac80211 defines mactime at the beginning of the first
1808 * data symbol. Since we don't have any time references it's
1809 * impossible to comply to that. This affects IBSS merge only
1810 * right now, so it's not too bad...
1812 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
1813 rxs.flag |= RX_FLAG_TSFT;
1815 rxs.freq = sc->curchan->center_freq;
1816 rxs.band = sc->curband->band;
1818 rxs.noise = sc->ah->ah_noise_floor;
1819 rxs.signal = rxs.noise + rs.rs_rssi;
1820 rxs.qual = rs.rs_rssi * 100 / 64;
1822 rxs.antenna = rs.rs_antenna;
1823 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1824 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
1826 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1828 /* check beacons in IBSS mode */
1829 if (sc->opmode == IEEE80211_IF_TYPE_IBSS)
1830 ath5k_check_ibss_tsf(sc, skb, &rxs);
1832 __ieee80211_rx(sc->hw, skb, &rxs);
1834 list_move_tail(&bf->list, &sc->rxbuf);
1835 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1837 spin_unlock(&sc->rxbuflock);
1848 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1850 struct ath5k_tx_status ts = {};
1851 struct ath5k_buf *bf, *bf0;
1852 struct ath5k_desc *ds;
1853 struct sk_buff *skb;
1854 struct ieee80211_tx_info *info;
1857 spin_lock(&txq->lock);
1858 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1861 /* TODO only one segment */
1862 pci_dma_sync_single_for_cpu(sc->pdev, sc->desc_daddr,
1863 sc->desc_len, PCI_DMA_FROMDEVICE);
1864 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1865 if (unlikely(ret == -EINPROGRESS))
1867 else if (unlikely(ret)) {
1868 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1874 info = IEEE80211_SKB_CB(skb);
1877 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1880 info->status.retry_count = ts.ts_shortretry + ts.ts_longretry / 6;
1881 if (unlikely(ts.ts_status)) {
1882 sc->ll_stats.dot11ACKFailureCount++;
1883 if (ts.ts_status & AR5K_TXERR_XRETRY)
1884 info->status.excessive_retries = 1;
1885 else if (ts.ts_status & AR5K_TXERR_FILT)
1886 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1888 info->flags |= IEEE80211_TX_STAT_ACK;
1889 info->status.ack_signal = ts.ts_rssi;
1892 ieee80211_tx_status(sc->hw, skb);
1893 sc->tx_stats[txq->qnum].count++;
1895 spin_lock(&sc->txbuflock);
1896 sc->tx_stats[txq->qnum].len--;
1897 list_move_tail(&bf->list, &sc->txbuf);
1899 spin_unlock(&sc->txbuflock);
1901 if (likely(list_empty(&txq->q)))
1903 spin_unlock(&txq->lock);
1904 if (sc->txbuf_len > ATH_TXBUF / 5)
1905 ieee80211_wake_queues(sc->hw);
1909 ath5k_tasklet_tx(unsigned long data)
1911 struct ath5k_softc *sc = (void *)data;
1913 ath5k_tx_processq(sc, sc->txq);
1922 * Setup the beacon frame for transmit.
1925 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1927 struct sk_buff *skb = bf->skb;
1928 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1929 struct ath5k_hw *ah = sc->ah;
1930 struct ath5k_desc *ds;
1931 int ret, antenna = 0;
1934 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1936 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
1937 "skbaddr %llx\n", skb, skb->data, skb->len,
1938 (unsigned long long)bf->skbaddr);
1939 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
1940 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
1946 flags = AR5K_TXDESC_NOACK;
1947 if (sc->opmode == IEEE80211_IF_TYPE_IBSS && ath5k_hw_hasveol(ah)) {
1948 ds->ds_link = bf->daddr; /* self-linked */
1949 flags |= AR5K_TXDESC_VEOL;
1951 * Let hardware handle antenna switching if txantenna is not set
1956 * Switch antenna every 4 beacons if txantenna is not set
1957 * XXX assumes two antennas
1960 antenna = sc->bsent & 4 ? 2 : 1;
1963 ds->ds_data = bf->skbaddr;
1964 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
1965 ieee80211_get_hdrlen_from_skb(skb),
1966 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
1967 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
1968 1, AR5K_TXKEYIX_INVALID,
1969 antenna, flags, 0, 0);
1975 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1980 * Transmit a beacon frame at SWBA. Dynamic updates to the
1981 * frame contents are done as needed and the slot time is
1982 * also adjusted based on current state.
1984 * this is usually called from interrupt context (ath5k_intr())
1985 * but also from ath5k_beacon_config() in IBSS mode which in turn
1986 * can be called from a tasklet and user context
1989 ath5k_beacon_send(struct ath5k_softc *sc)
1991 struct ath5k_buf *bf = sc->bbuf;
1992 struct ath5k_hw *ah = sc->ah;
1994 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
1996 if (unlikely(bf->skb == NULL || sc->opmode == IEEE80211_IF_TYPE_STA ||
1997 sc->opmode == IEEE80211_IF_TYPE_MNTR)) {
1998 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2002 * Check if the previous beacon has gone out. If
2003 * not don't don't try to post another, skip this
2004 * period and wait for the next. Missed beacons
2005 * indicate a problem and should not occur. If we
2006 * miss too many consecutive beacons reset the device.
2008 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2010 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2011 "missed %u consecutive beacons\n", sc->bmisscount);
2012 if (sc->bmisscount > 3) { /* NB: 3 is a guess */
2013 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2014 "stuck beacon time (%u missed)\n",
2016 tasklet_schedule(&sc->restq);
2020 if (unlikely(sc->bmisscount != 0)) {
2021 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2022 "resume beacon xmit after %u misses\n",
2028 * Stop any current dma and put the new frame on the queue.
2029 * This should never fail since we check above that no frames
2030 * are still pending on the queue.
2032 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2033 ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
2034 /* NB: hw still stops DMA, so proceed */
2036 pci_dma_sync_single_for_cpu(sc->pdev, bf->skbaddr, bf->skb->len,
2039 ath5k_hw_put_tx_buf(ah, sc->bhalq, bf->daddr);
2040 ath5k_hw_tx_start(ah, sc->bhalq);
2041 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
2042 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2049 * ath5k_beacon_update_timers - update beacon timers
2051 * @sc: struct ath5k_softc pointer we are operating on
2052 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2053 * beacon timer update based on the current HW TSF.
2055 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2056 * of a received beacon or the current local hardware TSF and write it to the
2057 * beacon timer registers.
2059 * This is called in a variety of situations, e.g. when a beacon is received,
2060 * when a TSF update has been detected, but also when an new IBSS is created or
2061 * when we otherwise know we have to update the timers, but we keep it in this
2062 * function to have it all together in one place.
2065 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
2067 struct ath5k_hw *ah = sc->ah;
2068 u32 nexttbtt, intval, hw_tu, bc_tu;
2071 intval = sc->bintval & AR5K_BEACON_PERIOD;
2072 if (WARN_ON(!intval))
2075 /* beacon TSF converted to TU */
2076 bc_tu = TSF_TO_TU(bc_tsf);
2078 /* current TSF converted to TU */
2079 hw_tsf = ath5k_hw_get_tsf64(ah);
2080 hw_tu = TSF_TO_TU(hw_tsf);
2083 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2086 * no beacons received, called internally.
2087 * just need to refresh timers based on HW TSF.
2089 nexttbtt = roundup(hw_tu + FUDGE, intval);
2090 } else if (bc_tsf == 0) {
2092 * no beacon received, probably called by ath5k_reset_tsf().
2093 * reset TSF to start with 0.
2096 intval |= AR5K_BEACON_RESET_TSF;
2097 } else if (bc_tsf > hw_tsf) {
2099 * beacon received, SW merge happend but HW TSF not yet updated.
2100 * not possible to reconfigure timers yet, but next time we
2101 * receive a beacon with the same BSSID, the hardware will
2102 * automatically update the TSF and then we need to reconfigure
2105 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2106 "need to wait for HW TSF sync\n");
2110 * most important case for beacon synchronization between STA.
2112 * beacon received and HW TSF has been already updated by HW.
2113 * update next TBTT based on the TSF of the beacon, but make
2114 * sure it is ahead of our local TSF timer.
2116 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2120 sc->nexttbtt = nexttbtt;
2122 intval |= AR5K_BEACON_ENA;
2123 ath5k_hw_init_beacon(ah, nexttbtt, intval);
2126 * debugging output last in order to preserve the time critical aspect
2130 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2131 "reconfigured timers based on HW TSF\n");
2132 else if (bc_tsf == 0)
2133 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2134 "reset HW TSF and timers\n");
2136 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2137 "updated timers based on beacon TSF\n");
2139 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2140 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2141 (unsigned long long) bc_tsf,
2142 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2143 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2144 intval & AR5K_BEACON_PERIOD,
2145 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2146 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2151 * ath5k_beacon_config - Configure the beacon queues and interrupts
2153 * @sc: struct ath5k_softc pointer we are operating on
2155 * When operating in station mode we want to receive a BMISS interrupt when we
2156 * stop seeing beacons from the AP we've associated with so we can look for
2157 * another AP to associate with.
2159 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2160 * interrupts to detect TSF updates only.
2162 * AP mode is missing.
2165 ath5k_beacon_config(struct ath5k_softc *sc)
2167 struct ath5k_hw *ah = sc->ah;
2169 ath5k_hw_set_intr(ah, 0);
2172 if (sc->opmode == IEEE80211_IF_TYPE_STA) {
2173 sc->imask |= AR5K_INT_BMISS;
2174 } else if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2176 * In IBSS mode we use a self-linked tx descriptor and let the
2177 * hardware send the beacons automatically. We have to load it
2179 * We use the SWBA interrupt only to keep track of the beacon
2180 * timers in order to detect automatic TSF updates.
2182 ath5k_beaconq_config(sc);
2184 sc->imask |= AR5K_INT_SWBA;
2186 if (ath5k_hw_hasveol(ah))
2187 ath5k_beacon_send(sc);
2191 ath5k_hw_set_intr(ah, sc->imask);
2195 /********************\
2196 * Interrupt handling *
2197 \********************/
2200 ath5k_init(struct ath5k_softc *sc)
2204 mutex_lock(&sc->lock);
2206 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2209 * Stop anything previously setup. This is safe
2210 * no matter this is the first time through or not.
2212 ath5k_stop_locked(sc);
2215 * The basic interface to setting the hardware in a good
2216 * state is ``reset''. On return the hardware is known to
2217 * be powered up and with interrupts disabled. This must
2218 * be followed by initialization of the appropriate bits
2219 * and then setup of the interrupt mask.
2221 sc->curchan = sc->hw->conf.channel;
2222 sc->curband = &sc->sbands[sc->curchan->band];
2223 ret = ath5k_hw_reset(sc->ah, sc->opmode, sc->curchan, false);
2225 ATH5K_ERR(sc, "unable to reset hardware: %d\n", ret);
2229 * This is needed only to setup initial state
2230 * but it's best done after a reset.
2232 ath5k_hw_set_txpower_limit(sc->ah, 0);
2235 * Setup the hardware after reset: the key cache
2236 * is filled as needed and the receive engine is
2237 * set going. Frame transmit is handled entirely
2238 * in the frame output path; there's nothing to do
2239 * here except setup the interrupt mask.
2241 ret = ath5k_rx_start(sc);
2246 * Enable interrupts.
2248 sc->imask = AR5K_INT_RX | AR5K_INT_TX | AR5K_INT_RXEOL |
2249 AR5K_INT_RXORN | AR5K_INT_FATAL | AR5K_INT_GLOBAL |
2252 ath5k_hw_set_intr(sc->ah, sc->imask);
2253 /* Set ack to be sent at low bit-rates */
2254 ath5k_hw_set_ack_bitrate_high(sc->ah, false);
2256 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2257 msecs_to_jiffies(ath5k_calinterval * 1000)));
2261 mutex_unlock(&sc->lock);
2266 ath5k_stop_locked(struct ath5k_softc *sc)
2268 struct ath5k_hw *ah = sc->ah;
2270 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2271 test_bit(ATH_STAT_INVALID, sc->status));
2274 * Shutdown the hardware and driver:
2275 * stop output from above
2276 * disable interrupts
2278 * turn off the radio
2279 * clear transmit machinery
2280 * clear receive machinery
2281 * drain and release tx queues
2282 * reclaim beacon resources
2283 * power down hardware
2285 * Note that some of this work is not possible if the
2286 * hardware is gone (invalid).
2288 ieee80211_stop_queues(sc->hw);
2290 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2292 ath5k_hw_set_intr(ah, 0);
2294 ath5k_txq_cleanup(sc);
2295 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2297 ath5k_hw_phy_disable(ah);
2305 * Stop the device, grabbing the top-level lock to protect
2306 * against concurrent entry through ath5k_init (which can happen
2307 * if another thread does a system call and the thread doing the
2308 * stop is preempted).
2311 ath5k_stop_hw(struct ath5k_softc *sc)
2315 mutex_lock(&sc->lock);
2316 ret = ath5k_stop_locked(sc);
2317 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2319 * Set the chip in full sleep mode. Note that we are
2320 * careful to do this only when bringing the interface
2321 * completely to a stop. When the chip is in this state
2322 * it must be carefully woken up or references to
2323 * registers in the PCI clock domain may freeze the bus
2324 * (and system). This varies by chip and is mostly an
2325 * issue with newer parts that go to sleep more quickly.
2327 if (sc->ah->ah_mac_srev >= 0x78) {
2330 * don't put newer MAC revisions > 7.8 to sleep because
2331 * of the above mentioned problems
2333 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2334 "not putting device to sleep\n");
2336 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2337 "putting device to full sleep\n");
2338 ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2341 ath5k_txbuf_free(sc, sc->bbuf);
2342 mutex_unlock(&sc->lock);
2344 del_timer_sync(&sc->calib_tim);
2345 tasklet_kill(&sc->rxtq);
2346 tasklet_kill(&sc->txtq);
2347 tasklet_kill(&sc->restq);
2353 ath5k_intr(int irq, void *dev_id)
2355 struct ath5k_softc *sc = dev_id;
2356 struct ath5k_hw *ah = sc->ah;
2357 enum ath5k_int status;
2358 unsigned int counter = 1000;
2360 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2361 !ath5k_hw_is_intr_pending(ah)))
2366 * Figure out the reason(s) for the interrupt. Note
2367 * that get_isr returns a pseudo-ISR that may include
2368 * bits we haven't explicitly enabled so we mask the
2369 * value to insure we only process bits we requested.
2371 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2372 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2374 status &= sc->imask; /* discard unasked for bits */
2375 if (unlikely(status & AR5K_INT_FATAL)) {
2377 * Fatal errors are unrecoverable.
2378 * Typically these are caused by DMA errors.
2380 tasklet_schedule(&sc->restq);
2381 } else if (unlikely(status & AR5K_INT_RXORN)) {
2382 tasklet_schedule(&sc->restq);
2384 if (status & AR5K_INT_SWBA) {
2386 * Software beacon alert--time to send a beacon.
2387 * Handle beacon transmission directly; deferring
2388 * this is too slow to meet timing constraints
2391 * In IBSS mode we use this interrupt just to
2392 * keep track of the next TBTT (target beacon
2393 * transmission time) in order to detect wether
2394 * automatic TSF updates happened.
2396 if (sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2397 /* XXX: only if VEOL suppported */
2398 u64 tsf = ath5k_hw_get_tsf64(ah);
2399 sc->nexttbtt += sc->bintval;
2400 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2401 "SWBA nexttbtt: %x hw_tu: %x "
2405 (unsigned long long) tsf);
2407 ath5k_beacon_send(sc);
2410 if (status & AR5K_INT_RXEOL) {
2412 * NB: the hardware should re-read the link when
2413 * RXE bit is written, but it doesn't work at
2414 * least on older hardware revs.
2418 if (status & AR5K_INT_TXURN) {
2419 /* bump tx trigger level */
2420 ath5k_hw_update_tx_triglevel(ah, true);
2422 if (status & AR5K_INT_RX)
2423 tasklet_schedule(&sc->rxtq);
2424 if (status & AR5K_INT_TX)
2425 tasklet_schedule(&sc->txtq);
2426 if (status & AR5K_INT_BMISS) {
2428 if (status & AR5K_INT_MIB) {
2430 * These stats are also used for ANI i think
2431 * so how about updating them more often ?
2433 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
2436 } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
2438 if (unlikely(!counter))
2439 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2445 ath5k_tasklet_reset(unsigned long data)
2447 struct ath5k_softc *sc = (void *)data;
2449 ath5k_reset(sc->hw);
2453 * Periodically recalibrate the PHY to account
2454 * for temperature/environment changes.
2457 ath5k_calibrate(unsigned long data)
2459 struct ath5k_softc *sc = (void *)data;
2460 struct ath5k_hw *ah = sc->ah;
2462 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2463 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2464 sc->curchan->hw_value);
2466 if (ath5k_hw_get_rf_gain(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2468 * Rfgain is out of bounds, reset the chip
2469 * to load new gain values.
2471 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2472 ath5k_reset(sc->hw);
2474 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2475 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2476 ieee80211_frequency_to_channel(
2477 sc->curchan->center_freq));
2479 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2480 msecs_to_jiffies(ath5k_calinterval * 1000)));
2490 ath5k_led_enable(struct ath5k_softc *sc)
2492 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
2493 ath5k_hw_set_gpio_output(sc->ah, sc->led_pin);
2499 ath5k_led_on(struct ath5k_softc *sc)
2501 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2503 ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on);
2507 ath5k_led_off(struct ath5k_softc *sc)
2509 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2511 ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on);
2515 ath5k_led_brightness_set(struct led_classdev *led_dev,
2516 enum led_brightness brightness)
2518 struct ath5k_led *led = container_of(led_dev, struct ath5k_led,
2521 if (brightness == LED_OFF)
2522 ath5k_led_off(led->sc);
2524 ath5k_led_on(led->sc);
2528 ath5k_register_led(struct ath5k_softc *sc, struct ath5k_led *led,
2529 const char *name, char *trigger)
2534 strncpy(led->name, name, sizeof(led->name));
2535 led->led_dev.name = led->name;
2536 led->led_dev.default_trigger = trigger;
2537 led->led_dev.brightness_set = ath5k_led_brightness_set;
2539 err = led_classdev_register(&sc->pdev->dev, &led->led_dev);
2542 ATH5K_WARN(sc, "could not register LED %s\n", name);
2549 ath5k_unregister_led(struct ath5k_led *led)
2553 led_classdev_unregister(&led->led_dev);
2554 ath5k_led_off(led->sc);
2559 ath5k_unregister_leds(struct ath5k_softc *sc)
2561 ath5k_unregister_led(&sc->rx_led);
2562 ath5k_unregister_led(&sc->tx_led);
2567 ath5k_init_leds(struct ath5k_softc *sc)
2570 struct ieee80211_hw *hw = sc->hw;
2571 struct pci_dev *pdev = sc->pdev;
2572 char name[ATH5K_LED_MAX_NAME_LEN + 1];
2574 sc->led_on = 0; /* active low */
2577 * Auto-enable soft led processing for IBM cards and for
2578 * 5211 minipci cards.
2580 if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM ||
2581 pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) {
2582 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2585 /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
2586 if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) {
2587 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2590 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2593 ath5k_led_enable(sc);
2595 snprintf(name, sizeof(name), "ath5k-%s::rx", wiphy_name(hw->wiphy));
2596 ret = ath5k_register_led(sc, &sc->rx_led, name,
2597 ieee80211_get_rx_led_name(hw));
2601 snprintf(name, sizeof(name), "ath5k-%s::tx", wiphy_name(hw->wiphy));
2602 ret = ath5k_register_led(sc, &sc->tx_led, name,
2603 ieee80211_get_tx_led_name(hw));
2609 /********************\
2610 * Mac80211 functions *
2611 \********************/
2614 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2616 struct ath5k_softc *sc = hw->priv;
2617 struct ath5k_buf *bf;
2618 unsigned long flags;
2622 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2624 if (sc->opmode == IEEE80211_IF_TYPE_MNTR)
2625 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2628 * the hardware expects the header padded to 4 byte boundaries
2629 * if this is not the case we add the padding after the header
2631 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2634 if (skb_headroom(skb) < pad) {
2635 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2636 " headroom to pad %d\n", hdrlen, pad);
2640 memmove(skb->data, skb->data+pad, hdrlen);
2643 spin_lock_irqsave(&sc->txbuflock, flags);
2644 if (list_empty(&sc->txbuf)) {
2645 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2646 spin_unlock_irqrestore(&sc->txbuflock, flags);
2647 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
2650 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2651 list_del(&bf->list);
2653 if (list_empty(&sc->txbuf))
2654 ieee80211_stop_queues(hw);
2655 spin_unlock_irqrestore(&sc->txbuflock, flags);
2659 if (ath5k_txbuf_setup(sc, bf)) {
2661 spin_lock_irqsave(&sc->txbuflock, flags);
2662 list_add_tail(&bf->list, &sc->txbuf);
2664 spin_unlock_irqrestore(&sc->txbuflock, flags);
2665 dev_kfree_skb_any(skb);
2673 ath5k_reset(struct ieee80211_hw *hw)
2675 struct ath5k_softc *sc = hw->priv;
2676 struct ath5k_hw *ah = sc->ah;
2679 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2681 ath5k_hw_set_intr(ah, 0);
2682 ath5k_txq_cleanup(sc);
2685 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
2686 if (unlikely(ret)) {
2687 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2690 ath5k_hw_set_txpower_limit(sc->ah, 0);
2692 ret = ath5k_rx_start(sc);
2693 if (unlikely(ret)) {
2694 ATH5K_ERR(sc, "can't start recv logic\n");
2698 * We may be doing a reset in response to an ioctl
2699 * that changes the channel so update any state that
2700 * might change as a result.
2704 /* ath5k_chan_change(sc, c); */
2705 ath5k_beacon_config(sc);
2706 /* intrs are started by ath5k_beacon_config */
2708 ieee80211_wake_queues(hw);
2715 static int ath5k_start(struct ieee80211_hw *hw)
2717 return ath5k_init(hw->priv);
2720 static void ath5k_stop(struct ieee80211_hw *hw)
2722 ath5k_stop_hw(hw->priv);
2725 static int ath5k_add_interface(struct ieee80211_hw *hw,
2726 struct ieee80211_if_init_conf *conf)
2728 struct ath5k_softc *sc = hw->priv;
2731 mutex_lock(&sc->lock);
2737 sc->vif = conf->vif;
2739 switch (conf->type) {
2740 case IEEE80211_IF_TYPE_STA:
2741 case IEEE80211_IF_TYPE_IBSS:
2742 case IEEE80211_IF_TYPE_MNTR:
2743 sc->opmode = conf->type;
2751 mutex_unlock(&sc->lock);
2756 ath5k_remove_interface(struct ieee80211_hw *hw,
2757 struct ieee80211_if_init_conf *conf)
2759 struct ath5k_softc *sc = hw->priv;
2761 mutex_lock(&sc->lock);
2762 if (sc->vif != conf->vif)
2767 mutex_unlock(&sc->lock);
2771 * TODO: Phy disable/diversity etc
2774 ath5k_config(struct ieee80211_hw *hw,
2775 struct ieee80211_conf *conf)
2777 struct ath5k_softc *sc = hw->priv;
2779 sc->bintval = conf->beacon_int;
2780 sc->power_level = conf->power_level;
2782 return ath5k_chan_set(sc, conf->channel);
2786 ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2787 struct ieee80211_if_conf *conf)
2789 struct ath5k_softc *sc = hw->priv;
2790 struct ath5k_hw *ah = sc->ah;
2793 /* Set to a reasonable value. Note that this will
2794 * be set to mac80211's value at ath5k_config(). */
2796 mutex_lock(&sc->lock);
2797 if (sc->vif != vif) {
2802 /* Cache for later use during resets */
2803 memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
2804 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2805 * a clean way of letting us retrieve this yet. */
2806 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
2809 if (conf->changed & IEEE80211_IFCC_BEACON &&
2810 vif->type == IEEE80211_IF_TYPE_IBSS) {
2811 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2816 /* call old handler for now */
2817 ath5k_beacon_update(hw, beacon);
2820 mutex_unlock(&sc->lock);
2822 return ath5k_reset(hw);
2824 mutex_unlock(&sc->lock);
2828 #define SUPPORTED_FIF_FLAGS \
2829 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2830 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2831 FIF_BCN_PRBRESP_PROMISC
2833 * o always accept unicast, broadcast, and multicast traffic
2834 * o multicast traffic for all BSSIDs will be enabled if mac80211
2836 * o maintain current state of phy ofdm or phy cck error reception.
2837 * If the hardware detects any of these type of errors then
2838 * ath5k_hw_get_rx_filter() will pass to us the respective
2839 * hardware filters to be able to receive these type of frames.
2840 * o probe request frames are accepted only when operating in
2841 * hostap, adhoc, or monitor modes
2842 * o enable promiscuous mode according to the interface state
2844 * - when operating in adhoc mode so the 802.11 layer creates
2845 * node table entries for peers,
2846 * - when operating in station mode for collecting rssi data when
2847 * the station is otherwise quiet, or
2850 static void ath5k_configure_filter(struct ieee80211_hw *hw,
2851 unsigned int changed_flags,
2852 unsigned int *new_flags,
2853 int mc_count, struct dev_mc_list *mclist)
2855 struct ath5k_softc *sc = hw->priv;
2856 struct ath5k_hw *ah = sc->ah;
2857 u32 mfilt[2], val, rfilt;
2864 /* Only deal with supported flags */
2865 changed_flags &= SUPPORTED_FIF_FLAGS;
2866 *new_flags &= SUPPORTED_FIF_FLAGS;
2868 /* If HW detects any phy or radar errors, leave those filters on.
2869 * Also, always enable Unicast, Broadcasts and Multicast
2870 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2871 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2872 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2873 AR5K_RX_FILTER_MCAST);
2875 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2876 if (*new_flags & FIF_PROMISC_IN_BSS) {
2877 rfilt |= AR5K_RX_FILTER_PROM;
2878 __set_bit(ATH_STAT_PROMISC, sc->status);
2881 __clear_bit(ATH_STAT_PROMISC, sc->status);
2884 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2885 if (*new_flags & FIF_ALLMULTI) {
2889 for (i = 0; i < mc_count; i++) {
2892 /* calculate XOR of eight 6-bit values */
2893 val = get_unaligned_le32(mclist->dmi_addr + 0);
2894 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2895 val = get_unaligned_le32(mclist->dmi_addr + 3);
2896 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2898 mfilt[pos / 32] |= (1 << (pos % 32));
2899 /* XXX: we might be able to just do this instead,
2900 * but not sure, needs testing, if we do use this we'd
2901 * neet to inform below to not reset the mcast */
2902 /* ath5k_hw_set_mcast_filterindex(ah,
2903 * mclist->dmi_addr[5]); */
2904 mclist = mclist->next;
2908 /* This is the best we can do */
2909 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2910 rfilt |= AR5K_RX_FILTER_PHYERR;
2912 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2913 * and probes for any BSSID, this needs testing */
2914 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2915 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2917 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2918 * set we should only pass on control frames for this
2919 * station. This needs testing. I believe right now this
2920 * enables *all* control frames, which is OK.. but
2921 * but we should see if we can improve on granularity */
2922 if (*new_flags & FIF_CONTROL)
2923 rfilt |= AR5K_RX_FILTER_CONTROL;
2925 /* Additional settings per mode -- this is per ath5k */
2927 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2929 if (sc->opmode == IEEE80211_IF_TYPE_MNTR)
2930 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
2931 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
2932 if (sc->opmode != IEEE80211_IF_TYPE_STA)
2933 rfilt |= AR5K_RX_FILTER_PROBEREQ;
2934 if (sc->opmode != IEEE80211_IF_TYPE_AP &&
2935 test_bit(ATH_STAT_PROMISC, sc->status))
2936 rfilt |= AR5K_RX_FILTER_PROM;
2937 if (sc->opmode == IEEE80211_IF_TYPE_STA ||
2938 sc->opmode == IEEE80211_IF_TYPE_IBSS) {
2939 rfilt |= AR5K_RX_FILTER_BEACON;
2943 ath5k_hw_set_rx_filter(ah,rfilt);
2945 /* Set multicast bits */
2946 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
2947 /* Set the cached hw filter flags, this will alter actually
2949 sc->filter_flags = rfilt;
2953 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2954 const u8 *local_addr, const u8 *addr,
2955 struct ieee80211_key_conf *key)
2957 struct ath5k_softc *sc = hw->priv;
2962 /* XXX: fix hardware encryption, its not working. For now
2963 * allow software encryption */
2973 mutex_lock(&sc->lock);
2977 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key, addr);
2979 ATH5K_ERR(sc, "can't set the key\n");
2982 __set_bit(key->keyidx, sc->keymap);
2983 key->hw_key_idx = key->keyidx;
2986 ath5k_hw_reset_key(sc->ah, key->keyidx);
2987 __clear_bit(key->keyidx, sc->keymap);
2995 mutex_unlock(&sc->lock);
3000 ath5k_get_stats(struct ieee80211_hw *hw,
3001 struct ieee80211_low_level_stats *stats)
3003 struct ath5k_softc *sc = hw->priv;
3004 struct ath5k_hw *ah = sc->ah;
3007 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
3009 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
3015 ath5k_get_tx_stats(struct ieee80211_hw *hw,
3016 struct ieee80211_tx_queue_stats *stats)
3018 struct ath5k_softc *sc = hw->priv;
3020 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
3026 ath5k_get_tsf(struct ieee80211_hw *hw)
3028 struct ath5k_softc *sc = hw->priv;
3030 return ath5k_hw_get_tsf64(sc->ah);
3034 ath5k_reset_tsf(struct ieee80211_hw *hw)
3036 struct ath5k_softc *sc = hw->priv;
3039 * in IBSS mode we need to update the beacon timers too.
3040 * this will also reset the TSF if we call it with 0
3042 if (sc->opmode == IEEE80211_IF_TYPE_IBSS)
3043 ath5k_beacon_update_timers(sc, 0);
3045 ath5k_hw_reset_tsf(sc->ah);
3049 ath5k_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb)
3051 struct ath5k_softc *sc = hw->priv;
3054 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3056 mutex_lock(&sc->lock);
3058 if (sc->opmode != IEEE80211_IF_TYPE_IBSS) {
3063 ath5k_txbuf_free(sc, sc->bbuf);
3064 sc->bbuf->skb = skb;
3065 ret = ath5k_beacon_setup(sc, sc->bbuf);
3067 sc->bbuf->skb = NULL;
3069 ath5k_beacon_config(sc);
3072 mutex_unlock(&sc->lock);