2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/hardirq.h>
48 #include <linux/netdevice.h>
49 #include <linux/cache.h>
50 #include <linux/pci.h>
51 #include <linux/ethtool.h>
52 #include <linux/uaccess.h>
54 #include <net/ieee80211_radiotap.h>
56 #include <asm/unaligned.h>
62 static int ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
63 static int modparam_nohwcrypt;
64 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
65 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
73 MODULE_AUTHOR("Jiri Slaby");
74 MODULE_AUTHOR("Nick Kossifidis");
75 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
76 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
77 MODULE_LICENSE("Dual BSD/GPL");
78 MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
82 static struct pci_device_id ath5k_pci_id_table[] __devinitdata = {
83 { PCI_VDEVICE(ATHEROS, 0x0207), .driver_data = AR5K_AR5210 }, /* 5210 early */
84 { PCI_VDEVICE(ATHEROS, 0x0007), .driver_data = AR5K_AR5210 }, /* 5210 */
85 { PCI_VDEVICE(ATHEROS, 0x0011), .driver_data = AR5K_AR5211 }, /* 5311 - this is on AHB bus !*/
86 { PCI_VDEVICE(ATHEROS, 0x0012), .driver_data = AR5K_AR5211 }, /* 5211 */
87 { PCI_VDEVICE(ATHEROS, 0x0013), .driver_data = AR5K_AR5212 }, /* 5212 */
88 { PCI_VDEVICE(3COM_2, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 5212 */
89 { PCI_VDEVICE(3COM, 0x0013), .driver_data = AR5K_AR5212 }, /* 3com 3CRDAG675 5212 */
90 { PCI_VDEVICE(ATHEROS, 0x1014), .driver_data = AR5K_AR5212 }, /* IBM minipci 5212 */
91 { PCI_VDEVICE(ATHEROS, 0x0014), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
92 { PCI_VDEVICE(ATHEROS, 0x0015), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
93 { PCI_VDEVICE(ATHEROS, 0x0016), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
94 { PCI_VDEVICE(ATHEROS, 0x0017), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
95 { PCI_VDEVICE(ATHEROS, 0x0018), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
96 { PCI_VDEVICE(ATHEROS, 0x0019), .driver_data = AR5K_AR5212 }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x001a), .driver_data = AR5K_AR5212 }, /* 2413 Griffin-lite */
98 { PCI_VDEVICE(ATHEROS, 0x001b), .driver_data = AR5K_AR5212 }, /* 5413 Eagle */
99 { PCI_VDEVICE(ATHEROS, 0x001c), .driver_data = AR5K_AR5212 }, /* PCI-E cards */
100 { PCI_VDEVICE(ATHEROS, 0x001d), .driver_data = AR5K_AR5212 }, /* 2417 Nala */
103 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
106 static struct ath5k_srev_name srev_names[] = {
107 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
108 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
109 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
110 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
111 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
112 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
113 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
114 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
115 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
116 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
117 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
118 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
119 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
120 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
121 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
122 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
123 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
124 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
125 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
126 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
127 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
128 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
129 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
130 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
131 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
132 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
133 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
134 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
135 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
136 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
137 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
138 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
139 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
140 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
141 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
142 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
145 static struct ieee80211_rate ath5k_rates[] = {
147 .hw_value = ATH5K_RATE_CODE_1M, },
149 .hw_value = ATH5K_RATE_CODE_2M,
150 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
151 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
153 .hw_value = ATH5K_RATE_CODE_5_5M,
154 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
155 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
157 .hw_value = ATH5K_RATE_CODE_11M,
158 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
159 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
161 .hw_value = ATH5K_RATE_CODE_6M,
164 .hw_value = ATH5K_RATE_CODE_9M,
167 .hw_value = ATH5K_RATE_CODE_12M,
170 .hw_value = ATH5K_RATE_CODE_18M,
173 .hw_value = ATH5K_RATE_CODE_24M,
176 .hw_value = ATH5K_RATE_CODE_36M,
179 .hw_value = ATH5K_RATE_CODE_48M,
182 .hw_value = ATH5K_RATE_CODE_54M,
188 * Prototypes - PCI stack related functions
190 static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
191 const struct pci_device_id *id);
192 static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
194 static int ath5k_pci_suspend(struct pci_dev *pdev,
196 static int ath5k_pci_resume(struct pci_dev *pdev);
198 #define ath5k_pci_suspend NULL
199 #define ath5k_pci_resume NULL
200 #endif /* CONFIG_PM */
202 static struct pci_driver ath5k_pci_driver = {
203 .name = KBUILD_MODNAME,
204 .id_table = ath5k_pci_id_table,
205 .probe = ath5k_pci_probe,
206 .remove = __devexit_p(ath5k_pci_remove),
207 .suspend = ath5k_pci_suspend,
208 .resume = ath5k_pci_resume,
214 * Prototypes - MAC 802.11 stack related functions
216 static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
217 static int ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel);
218 static int ath5k_reset_wake(struct ath5k_softc *sc);
219 static int ath5k_start(struct ieee80211_hw *hw);
220 static void ath5k_stop(struct ieee80211_hw *hw);
221 static int ath5k_add_interface(struct ieee80211_hw *hw,
222 struct ieee80211_if_init_conf *conf);
223 static void ath5k_remove_interface(struct ieee80211_hw *hw,
224 struct ieee80211_if_init_conf *conf);
225 static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
226 static int ath5k_config_interface(struct ieee80211_hw *hw,
227 struct ieee80211_vif *vif,
228 struct ieee80211_if_conf *conf);
229 static void ath5k_configure_filter(struct ieee80211_hw *hw,
230 unsigned int changed_flags,
231 unsigned int *new_flags,
232 int mc_count, struct dev_mc_list *mclist);
233 static int ath5k_set_key(struct ieee80211_hw *hw,
234 enum set_key_cmd cmd,
235 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
236 struct ieee80211_key_conf *key);
237 static int ath5k_get_stats(struct ieee80211_hw *hw,
238 struct ieee80211_low_level_stats *stats);
239 static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
240 struct ieee80211_tx_queue_stats *stats);
241 static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
242 static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf);
243 static void ath5k_reset_tsf(struct ieee80211_hw *hw);
244 static int ath5k_beacon_update(struct ath5k_softc *sc,
245 struct sk_buff *skb);
246 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
247 struct ieee80211_vif *vif,
248 struct ieee80211_bss_conf *bss_conf,
251 static struct ieee80211_ops ath5k_hw_ops = {
253 .start = ath5k_start,
255 .add_interface = ath5k_add_interface,
256 .remove_interface = ath5k_remove_interface,
257 .config = ath5k_config,
258 .config_interface = ath5k_config_interface,
259 .configure_filter = ath5k_configure_filter,
260 .set_key = ath5k_set_key,
261 .get_stats = ath5k_get_stats,
263 .get_tx_stats = ath5k_get_tx_stats,
264 .get_tsf = ath5k_get_tsf,
265 .set_tsf = ath5k_set_tsf,
266 .reset_tsf = ath5k_reset_tsf,
267 .bss_info_changed = ath5k_bss_info_changed,
271 * Prototypes - Internal functions
274 static int ath5k_attach(struct pci_dev *pdev,
275 struct ieee80211_hw *hw);
276 static void ath5k_detach(struct pci_dev *pdev,
277 struct ieee80211_hw *hw);
278 /* Channel/mode setup */
279 static inline short ath5k_ieee2mhz(short chan);
280 static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
281 struct ieee80211_channel *channels,
284 static int ath5k_setup_bands(struct ieee80211_hw *hw);
285 static int ath5k_chan_set(struct ath5k_softc *sc,
286 struct ieee80211_channel *chan);
287 static void ath5k_setcurmode(struct ath5k_softc *sc,
289 static void ath5k_mode_setup(struct ath5k_softc *sc);
291 /* Descriptor setup */
292 static int ath5k_desc_alloc(struct ath5k_softc *sc,
293 struct pci_dev *pdev);
294 static void ath5k_desc_free(struct ath5k_softc *sc,
295 struct pci_dev *pdev);
297 static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
298 struct ath5k_buf *bf);
299 static int ath5k_txbuf_setup(struct ath5k_softc *sc,
300 struct ath5k_buf *bf);
301 static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
302 struct ath5k_buf *bf)
307 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
309 dev_kfree_skb_any(bf->skb);
313 static inline void ath5k_rxbuf_free(struct ath5k_softc *sc,
314 struct ath5k_buf *bf)
319 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
321 dev_kfree_skb_any(bf->skb);
327 static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
328 int qtype, int subtype);
329 static int ath5k_beaconq_setup(struct ath5k_hw *ah);
330 static int ath5k_beaconq_config(struct ath5k_softc *sc);
331 static void ath5k_txq_drainq(struct ath5k_softc *sc,
332 struct ath5k_txq *txq);
333 static void ath5k_txq_cleanup(struct ath5k_softc *sc);
334 static void ath5k_txq_release(struct ath5k_softc *sc);
336 static int ath5k_rx_start(struct ath5k_softc *sc);
337 static void ath5k_rx_stop(struct ath5k_softc *sc);
338 static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
339 struct ath5k_desc *ds,
341 struct ath5k_rx_status *rs);
342 static void ath5k_tasklet_rx(unsigned long data);
344 static void ath5k_tx_processq(struct ath5k_softc *sc,
345 struct ath5k_txq *txq);
346 static void ath5k_tasklet_tx(unsigned long data);
347 /* Beacon handling */
348 static int ath5k_beacon_setup(struct ath5k_softc *sc,
349 struct ath5k_buf *bf);
350 static void ath5k_beacon_send(struct ath5k_softc *sc);
351 static void ath5k_beacon_config(struct ath5k_softc *sc);
352 static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
353 static void ath5k_tasklet_beacon(unsigned long data);
355 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
357 u64 tsf = ath5k_hw_get_tsf64(ah);
359 if ((tsf & 0x7fff) < rstamp)
362 return (tsf & ~0x7fff) | rstamp;
365 /* Interrupt handling */
366 static int ath5k_init(struct ath5k_softc *sc);
367 static int ath5k_stop_locked(struct ath5k_softc *sc);
368 static int ath5k_stop_hw(struct ath5k_softc *sc);
369 static irqreturn_t ath5k_intr(int irq, void *dev_id);
370 static void ath5k_tasklet_reset(unsigned long data);
372 static void ath5k_calibrate(unsigned long data);
374 static int ath5k_init_leds(struct ath5k_softc *sc);
375 static void ath5k_led_enable(struct ath5k_softc *sc);
376 static void ath5k_led_off(struct ath5k_softc *sc);
377 static void ath5k_unregister_leds(struct ath5k_softc *sc);
380 * Module init/exit functions
389 ret = pci_register_driver(&ath5k_pci_driver);
391 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
401 pci_unregister_driver(&ath5k_pci_driver);
403 ath5k_debug_finish();
406 module_init(init_ath5k_pci);
407 module_exit(exit_ath5k_pci);
410 /********************\
411 * PCI Initialization *
412 \********************/
415 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
417 const char *name = "xxxxx";
420 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
421 if (srev_names[i].sr_type != type)
424 if ((val & 0xf0) == srev_names[i].sr_val)
425 name = srev_names[i].sr_name;
427 if ((val & 0xff) == srev_names[i].sr_val) {
428 name = srev_names[i].sr_name;
437 ath5k_pci_probe(struct pci_dev *pdev,
438 const struct pci_device_id *id)
441 struct ath5k_softc *sc;
442 struct ieee80211_hw *hw;
446 ret = pci_enable_device(pdev);
448 dev_err(&pdev->dev, "can't enable device\n");
452 /* XXX 32-bit addressing only */
453 ret = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
455 dev_err(&pdev->dev, "32-bit DMA not available\n");
460 * Cache line size is used to size and align various
461 * structures used to communicate with the hardware.
463 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
466 * Linux 2.4.18 (at least) writes the cache line size
467 * register as a 16-bit wide register which is wrong.
468 * We must have this setup properly for rx buffer
469 * DMA to work so force a reasonable value here if it
472 csz = L1_CACHE_BYTES / sizeof(u32);
473 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
476 * The default setting of latency timer yields poor results,
477 * set it to the value used by other systems. It may be worth
478 * tweaking this setting more.
480 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
482 /* Enable bus mastering */
483 pci_set_master(pdev);
486 * Disable the RETRY_TIMEOUT register (0x41) to keep
487 * PCI Tx retries from interfering with C3 CPU state.
489 pci_write_config_byte(pdev, 0x41, 0);
491 ret = pci_request_region(pdev, 0, "ath5k");
493 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
497 mem = pci_iomap(pdev, 0, 0);
499 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
505 * Allocate hw (mac80211 main struct)
506 * and hw->priv (driver private data)
508 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
510 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
515 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
517 /* Initialize driver private data */
518 SET_IEEE80211_DEV(hw, &pdev->dev);
519 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
520 IEEE80211_HW_SIGNAL_DBM |
521 IEEE80211_HW_NOISE_DBM;
523 hw->wiphy->interface_modes =
524 BIT(NL80211_IFTYPE_STATION) |
525 BIT(NL80211_IFTYPE_ADHOC) |
526 BIT(NL80211_IFTYPE_MESH_POINT);
528 hw->extra_tx_headroom = 2;
529 hw->channel_change_time = 5000;
534 ath5k_debug_init_device(sc);
537 * Mark the device as detached to avoid processing
538 * interrupts until setup is complete.
540 __set_bit(ATH_STAT_INVALID, sc->status);
542 sc->iobase = mem; /* So we can unmap it on detach */
543 sc->cachelsz = csz * sizeof(u32); /* convert to bytes */
544 sc->opmode = NL80211_IFTYPE_STATION;
545 mutex_init(&sc->lock);
546 spin_lock_init(&sc->rxbuflock);
547 spin_lock_init(&sc->txbuflock);
548 spin_lock_init(&sc->block);
550 /* Set private data */
551 pci_set_drvdata(pdev, hw);
553 /* Setup interrupt handler */
554 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
556 ATH5K_ERR(sc, "request_irq failed\n");
560 /* Initialize device */
561 sc->ah = ath5k_hw_attach(sc, id->driver_data);
562 if (IS_ERR(sc->ah)) {
563 ret = PTR_ERR(sc->ah);
567 /* set up multi-rate retry capabilities */
568 if (sc->ah->ah_version == AR5K_AR5212) {
570 hw->max_rate_tries = 11;
573 /* Finish private driver data initialization */
574 ret = ath5k_attach(pdev, hw);
578 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
579 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
581 sc->ah->ah_phy_revision);
583 if (!sc->ah->ah_single_chip) {
584 /* Single chip radio (!RF5111) */
585 if (sc->ah->ah_radio_5ghz_revision &&
586 !sc->ah->ah_radio_2ghz_revision) {
587 /* No 5GHz support -> report 2GHz radio */
588 if (!test_bit(AR5K_MODE_11A,
589 sc->ah->ah_capabilities.cap_mode)) {
590 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
591 ath5k_chip_name(AR5K_VERSION_RAD,
592 sc->ah->ah_radio_5ghz_revision),
593 sc->ah->ah_radio_5ghz_revision);
594 /* No 2GHz support (5110 and some
595 * 5Ghz only cards) -> report 5Ghz radio */
596 } else if (!test_bit(AR5K_MODE_11B,
597 sc->ah->ah_capabilities.cap_mode)) {
598 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
599 ath5k_chip_name(AR5K_VERSION_RAD,
600 sc->ah->ah_radio_5ghz_revision),
601 sc->ah->ah_radio_5ghz_revision);
602 /* Multiband radio */
604 ATH5K_INFO(sc, "RF%s multiband radio found"
606 ath5k_chip_name(AR5K_VERSION_RAD,
607 sc->ah->ah_radio_5ghz_revision),
608 sc->ah->ah_radio_5ghz_revision);
611 /* Multi chip radio (RF5111 - RF2111) ->
612 * report both 2GHz/5GHz radios */
613 else if (sc->ah->ah_radio_5ghz_revision &&
614 sc->ah->ah_radio_2ghz_revision){
615 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
616 ath5k_chip_name(AR5K_VERSION_RAD,
617 sc->ah->ah_radio_5ghz_revision),
618 sc->ah->ah_radio_5ghz_revision);
619 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
620 ath5k_chip_name(AR5K_VERSION_RAD,
621 sc->ah->ah_radio_2ghz_revision),
622 sc->ah->ah_radio_2ghz_revision);
627 /* ready to process interrupts */
628 __clear_bit(ATH_STAT_INVALID, sc->status);
632 ath5k_hw_detach(sc->ah);
634 free_irq(pdev->irq, sc);
636 ieee80211_free_hw(hw);
638 pci_iounmap(pdev, mem);
640 pci_release_region(pdev, 0);
642 pci_disable_device(pdev);
647 static void __devexit
648 ath5k_pci_remove(struct pci_dev *pdev)
650 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
651 struct ath5k_softc *sc = hw->priv;
653 ath5k_debug_finish_device(sc);
654 ath5k_detach(pdev, hw);
655 ath5k_hw_detach(sc->ah);
656 free_irq(pdev->irq, sc);
657 pci_iounmap(pdev, sc->iobase);
658 pci_release_region(pdev, 0);
659 pci_disable_device(pdev);
660 ieee80211_free_hw(hw);
665 ath5k_pci_suspend(struct pci_dev *pdev, pm_message_t state)
667 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
668 struct ath5k_softc *sc = hw->priv;
672 free_irq(pdev->irq, sc);
673 pci_save_state(pdev);
674 pci_disable_device(pdev);
675 pci_set_power_state(pdev, PCI_D3hot);
681 ath5k_pci_resume(struct pci_dev *pdev)
683 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
684 struct ath5k_softc *sc = hw->priv;
687 pci_restore_state(pdev);
689 err = pci_enable_device(pdev);
694 * Suspend/Resume resets the PCI configuration space, so we have to
695 * re-disable the RETRY_TIMEOUT register (0x41) to keep
696 * PCI Tx retries from interfering with C3 CPU state
698 pci_write_config_byte(pdev, 0x41, 0);
700 err = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
702 ATH5K_ERR(sc, "request_irq failed\n");
706 ath5k_led_enable(sc);
710 pci_disable_device(pdev);
713 #endif /* CONFIG_PM */
716 /***********************\
717 * Driver Initialization *
718 \***********************/
721 ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
723 struct ath5k_softc *sc = hw->priv;
724 struct ath5k_hw *ah = sc->ah;
725 u8 mac[ETH_ALEN] = {};
728 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
731 * Check if the MAC has multi-rate retry support.
732 * We do this by trying to setup a fake extended
733 * descriptor. MAC's that don't have support will
734 * return false w/o doing anything. MAC's that do
735 * support it will return true w/o doing anything.
737 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
741 __set_bit(ATH_STAT_MRRETRY, sc->status);
744 * Collect the channel list. The 802.11 layer
745 * is resposible for filtering this list based
746 * on settings like the phy mode and regulatory
747 * domain restrictions.
749 ret = ath5k_setup_bands(hw);
751 ATH5K_ERR(sc, "can't get channels\n");
755 /* NB: setup here so ath5k_rate_update is happy */
756 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
757 ath5k_setcurmode(sc, AR5K_MODE_11A);
759 ath5k_setcurmode(sc, AR5K_MODE_11B);
762 * Allocate tx+rx descriptors and populate the lists.
764 ret = ath5k_desc_alloc(sc, pdev);
766 ATH5K_ERR(sc, "can't allocate descriptors\n");
771 * Allocate hardware transmit queues: one queue for
772 * beacon frames and one data queue for each QoS
773 * priority. Note that hw functions handle reseting
774 * these queues at the needed time.
776 ret = ath5k_beaconq_setup(ah);
778 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
783 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
784 if (IS_ERR(sc->txq)) {
785 ATH5K_ERR(sc, "can't setup xmit queue\n");
786 ret = PTR_ERR(sc->txq);
790 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
791 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
792 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
793 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
794 setup_timer(&sc->calib_tim, ath5k_calibrate, (unsigned long)sc);
796 ret = ath5k_eeprom_read_mac(ah, mac);
798 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
803 SET_IEEE80211_PERM_ADDR(hw, mac);
804 /* All MAC address bits matter for ACKs */
805 memset(sc->bssidmask, 0xff, ETH_ALEN);
806 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
808 ret = ieee80211_register_hw(hw);
810 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
818 ath5k_txq_release(sc);
820 ath5k_hw_release_tx_queue(ah, sc->bhalq);
822 ath5k_desc_free(sc, pdev);
828 ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
830 struct ath5k_softc *sc = hw->priv;
833 * NB: the order of these is important:
834 * o call the 802.11 layer before detaching ath5k_hw to
835 * insure callbacks into the driver to delete global
836 * key cache entries can be handled
837 * o reclaim the tx queue data structures after calling
838 * the 802.11 layer as we'll get called back to reclaim
839 * node state and potentially want to use them
840 * o to cleanup the tx queues the hal is called, so detach
842 * XXX: ??? detach ath5k_hw ???
843 * Other than that, it's straightforward...
845 ieee80211_unregister_hw(hw);
846 ath5k_desc_free(sc, pdev);
847 ath5k_txq_release(sc);
848 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
849 ath5k_unregister_leds(sc);
852 * NB: can't reclaim these until after ieee80211_ifdetach
853 * returns because we'll get called back to reclaim node
854 * state and potentially want to use them.
861 /********************\
862 * Channel/mode setup *
863 \********************/
866 * Convert IEEE channel number to MHz frequency.
869 ath5k_ieee2mhz(short chan)
871 if (chan <= 14 || chan >= 27)
872 return ieee80211chan2mhz(chan);
874 return 2212 + chan * 20;
878 ath5k_copy_channels(struct ath5k_hw *ah,
879 struct ieee80211_channel *channels,
883 unsigned int i, count, size, chfreq, freq, ch;
885 if (!test_bit(mode, ah->ah_modes))
890 case AR5K_MODE_11A_TURBO:
891 /* 1..220, but 2GHz frequencies are filtered by check_channel */
893 chfreq = CHANNEL_5GHZ;
897 case AR5K_MODE_11G_TURBO:
899 chfreq = CHANNEL_2GHZ;
902 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
906 for (i = 0, count = 0; i < size && max > 0; i++) {
908 freq = ath5k_ieee2mhz(ch);
910 /* Check if channel is supported by the chipset */
911 if (!ath5k_channel_ok(ah, freq, chfreq))
914 /* Write channel info and increment counter */
915 channels[count].center_freq = freq;
916 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
917 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
921 channels[count].hw_value = chfreq | CHANNEL_OFDM;
923 case AR5K_MODE_11A_TURBO:
924 case AR5K_MODE_11G_TURBO:
925 channels[count].hw_value = chfreq |
926 CHANNEL_OFDM | CHANNEL_TURBO;
929 channels[count].hw_value = CHANNEL_B;
940 ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
944 for (i = 0; i < AR5K_MAX_RATES; i++)
945 sc->rate_idx[b->band][i] = -1;
947 for (i = 0; i < b->n_bitrates; i++) {
948 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
949 if (b->bitrates[i].hw_value_short)
950 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
955 ath5k_setup_bands(struct ieee80211_hw *hw)
957 struct ath5k_softc *sc = hw->priv;
958 struct ath5k_hw *ah = sc->ah;
959 struct ieee80211_supported_band *sband;
960 int max_c, count_c = 0;
963 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
964 max_c = ARRAY_SIZE(sc->channels);
967 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
968 sband->band = IEEE80211_BAND_2GHZ;
969 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
971 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
973 memcpy(sband->bitrates, &ath5k_rates[0],
974 sizeof(struct ieee80211_rate) * 12);
975 sband->n_bitrates = 12;
977 sband->channels = sc->channels;
978 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
979 AR5K_MODE_11G, max_c);
981 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
982 count_c = sband->n_channels;
984 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
986 memcpy(sband->bitrates, &ath5k_rates[0],
987 sizeof(struct ieee80211_rate) * 4);
988 sband->n_bitrates = 4;
990 /* 5211 only supports B rates and uses 4bit rate codes
991 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
994 if (ah->ah_version == AR5K_AR5211) {
995 for (i = 0; i < 4; i++) {
996 sband->bitrates[i].hw_value =
997 sband->bitrates[i].hw_value & 0xF;
998 sband->bitrates[i].hw_value_short =
999 sband->bitrates[i].hw_value_short & 0xF;
1003 sband->channels = sc->channels;
1004 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1005 AR5K_MODE_11B, max_c);
1007 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1008 count_c = sband->n_channels;
1011 ath5k_setup_rate_idx(sc, sband);
1013 /* 5GHz band, A mode */
1014 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
1015 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1016 sband->band = IEEE80211_BAND_5GHZ;
1017 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
1019 memcpy(sband->bitrates, &ath5k_rates[4],
1020 sizeof(struct ieee80211_rate) * 8);
1021 sband->n_bitrates = 8;
1023 sband->channels = &sc->channels[count_c];
1024 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1025 AR5K_MODE_11A, max_c);
1027 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1029 ath5k_setup_rate_idx(sc, sband);
1031 ath5k_debug_dump_bands(sc);
1037 * Set/change channels. If the channel is really being changed,
1038 * it's done by reseting the chip. To accomplish this we must
1039 * first cleanup any pending DMA, then restart stuff after a la
1042 * Called with sc->lock.
1045 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1047 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1048 sc->curchan->center_freq, chan->center_freq);
1050 if (chan->center_freq != sc->curchan->center_freq ||
1051 chan->hw_value != sc->curchan->hw_value) {
1054 sc->curband = &sc->sbands[chan->band];
1057 * To switch channels clear any pending DMA operations;
1058 * wait long enough for the RX fifo to drain, reset the
1059 * hardware at the new frequency, and then re-enable
1060 * the relevant bits of the h/w.
1062 return ath5k_reset(sc, true, true);
1069 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1073 if (mode == AR5K_MODE_11A) {
1074 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1076 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1081 ath5k_mode_setup(struct ath5k_softc *sc)
1083 struct ath5k_hw *ah = sc->ah;
1086 /* configure rx filter */
1087 rfilt = sc->filter_flags;
1088 ath5k_hw_set_rx_filter(ah, rfilt);
1090 if (ath5k_hw_hasbssidmask(ah))
1091 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1093 /* configure operational mode */
1094 ath5k_hw_set_opmode(ah);
1096 ath5k_hw_set_mcast_filter(ah, 0, 0);
1097 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1101 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1103 WARN_ON(hw_rix < 0 || hw_rix > AR5K_MAX_RATES);
1104 return sc->rate_idx[sc->curband->band][hw_rix];
1112 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
1114 struct sk_buff *skb;
1118 * Allocate buffer with headroom_needed space for the
1119 * fake physical layer header at the start.
1121 skb = dev_alloc_skb(sc->rxbufsize + sc->cachelsz - 1);
1124 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1125 sc->rxbufsize + sc->cachelsz - 1);
1129 * Cache-line-align. This is important (for the
1130 * 5210 at least) as not doing so causes bogus data
1133 off = ((unsigned long)skb->data) % sc->cachelsz;
1135 skb_reserve(skb, sc->cachelsz - off);
1137 *skb_addr = pci_map_single(sc->pdev,
1138 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1139 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
1140 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1148 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1150 struct ath5k_hw *ah = sc->ah;
1151 struct sk_buff *skb = bf->skb;
1152 struct ath5k_desc *ds;
1155 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
1162 * Setup descriptors. For receive we always terminate
1163 * the descriptor list with a self-linked entry so we'll
1164 * not get overrun under high load (as can happen with a
1165 * 5212 when ANI processing enables PHY error frames).
1167 * To insure the last descriptor is self-linked we create
1168 * each descriptor as self-linked and add it to the end. As
1169 * each additional descriptor is added the previous self-linked
1170 * entry is ``fixed'' naturally. This should be safe even
1171 * if DMA is happening. When processing RX interrupts we
1172 * never remove/process the last, self-linked, entry on the
1173 * descriptor list. This insures the hardware always has
1174 * someplace to write a new frame.
1177 ds->ds_link = bf->daddr; /* link to self */
1178 ds->ds_data = bf->skbaddr;
1179 ah->ah_setup_rx_desc(ah, ds,
1180 skb_tailroom(skb), /* buffer size */
1183 if (sc->rxlink != NULL)
1184 *sc->rxlink = bf->daddr;
1185 sc->rxlink = &ds->ds_link;
1190 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1192 struct ath5k_hw *ah = sc->ah;
1193 struct ath5k_txq *txq = sc->txq;
1194 struct ath5k_desc *ds = bf->desc;
1195 struct sk_buff *skb = bf->skb;
1196 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1197 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1198 struct ieee80211_rate *rate;
1199 unsigned int mrr_rate[3], mrr_tries[3];
1206 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
1208 /* XXX endianness */
1209 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1212 rate = ieee80211_get_tx_rate(sc->hw, info);
1214 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
1215 flags |= AR5K_TXDESC_NOACK;
1217 rc_flags = info->control.rates[0].flags;
1218 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
1219 rate->hw_value_short : rate->hw_value;
1223 if (info->control.hw_key) {
1224 keyidx = info->control.hw_key->hw_key_idx;
1225 pktlen += info->control.hw_key->icv_len;
1227 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1228 flags |= AR5K_TXDESC_RTSENA;
1229 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1230 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
1231 sc->vif, pktlen, info));
1233 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1234 flags |= AR5K_TXDESC_CTSENA;
1235 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1236 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
1237 sc->vif, pktlen, info));
1239 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1240 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
1241 (sc->power_level * 2),
1243 info->control.rates[0].count, keyidx, 0, flags,
1244 cts_rate, duration);
1248 memset(mrr_rate, 0, sizeof(mrr_rate));
1249 memset(mrr_tries, 0, sizeof(mrr_tries));
1250 for (i = 0; i < 3; i++) {
1251 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1255 mrr_rate[i] = rate->hw_value;
1256 mrr_tries[i] = info->control.rates[i + 1].count;
1259 ah->ah_setup_mrr_tx_desc(ah, ds,
1260 mrr_rate[0], mrr_tries[0],
1261 mrr_rate[1], mrr_tries[1],
1262 mrr_rate[2], mrr_tries[2]);
1265 ds->ds_data = bf->skbaddr;
1267 spin_lock_bh(&txq->lock);
1268 list_add_tail(&bf->list, &txq->q);
1269 sc->tx_stats[txq->qnum].len++;
1270 if (txq->link == NULL) /* is this first packet? */
1271 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
1272 else /* no, so only link it */
1273 *txq->link = bf->daddr;
1275 txq->link = &ds->ds_link;
1276 ath5k_hw_start_tx_dma(ah, txq->qnum);
1278 spin_unlock_bh(&txq->lock);
1282 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1286 /*******************\
1287 * Descriptors setup *
1288 \*******************/
1291 ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1293 struct ath5k_desc *ds;
1294 struct ath5k_buf *bf;
1299 /* allocate descriptors */
1300 sc->desc_len = sizeof(struct ath5k_desc) *
1301 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1302 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1303 if (sc->desc == NULL) {
1304 ATH5K_ERR(sc, "can't allocate descriptors\n");
1309 da = sc->desc_daddr;
1310 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1311 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1313 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1314 sizeof(struct ath5k_buf), GFP_KERNEL);
1316 ATH5K_ERR(sc, "can't allocate bufptr\n");
1322 INIT_LIST_HEAD(&sc->rxbuf);
1323 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1326 list_add_tail(&bf->list, &sc->rxbuf);
1329 INIT_LIST_HEAD(&sc->txbuf);
1330 sc->txbuf_len = ATH_TXBUF;
1331 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1332 da += sizeof(*ds)) {
1335 list_add_tail(&bf->list, &sc->txbuf);
1345 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1352 ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1354 struct ath5k_buf *bf;
1356 ath5k_txbuf_free(sc, sc->bbuf);
1357 list_for_each_entry(bf, &sc->txbuf, list)
1358 ath5k_txbuf_free(sc, bf);
1359 list_for_each_entry(bf, &sc->rxbuf, list)
1360 ath5k_rxbuf_free(sc, bf);
1362 /* Free memory associated with all descriptors */
1363 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1377 static struct ath5k_txq *
1378 ath5k_txq_setup(struct ath5k_softc *sc,
1379 int qtype, int subtype)
1381 struct ath5k_hw *ah = sc->ah;
1382 struct ath5k_txq *txq;
1383 struct ath5k_txq_info qi = {
1384 .tqi_subtype = subtype,
1385 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1386 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1387 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1392 * Enable interrupts only for EOL and DESC conditions.
1393 * We mark tx descriptors to receive a DESC interrupt
1394 * when a tx queue gets deep; otherwise waiting for the
1395 * EOL to reap descriptors. Note that this is done to
1396 * reduce interrupt load and this only defers reaping
1397 * descriptors, never transmitting frames. Aside from
1398 * reducing interrupts this also permits more concurrency.
1399 * The only potential downside is if the tx queue backs
1400 * up in which case the top half of the kernel may backup
1401 * due to a lack of tx descriptors.
1403 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1404 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1405 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1408 * NB: don't print a message, this happens
1409 * normally on parts with too few tx queues
1411 return ERR_PTR(qnum);
1413 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1414 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1415 qnum, ARRAY_SIZE(sc->txqs));
1416 ath5k_hw_release_tx_queue(ah, qnum);
1417 return ERR_PTR(-EINVAL);
1419 txq = &sc->txqs[qnum];
1423 INIT_LIST_HEAD(&txq->q);
1424 spin_lock_init(&txq->lock);
1427 return &sc->txqs[qnum];
1431 ath5k_beaconq_setup(struct ath5k_hw *ah)
1433 struct ath5k_txq_info qi = {
1434 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1435 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1436 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1437 /* NB: for dynamic turbo, don't enable any other interrupts */
1438 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1441 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1445 ath5k_beaconq_config(struct ath5k_softc *sc)
1447 struct ath5k_hw *ah = sc->ah;
1448 struct ath5k_txq_info qi;
1451 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1454 if (sc->opmode == NL80211_IFTYPE_AP ||
1455 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
1457 * Always burst out beacon and CAB traffic
1458 * (aifs = cwmin = cwmax = 0)
1463 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1465 * Adhoc mode; backoff between 0 and (2 * cw_min).
1469 qi.tqi_cw_max = 2 * ah->ah_cw_min;
1472 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1473 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1474 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1476 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
1478 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1479 "hardware queue!\n", __func__);
1483 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1487 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1489 struct ath5k_buf *bf, *bf0;
1492 * NB: this assumes output has been stopped and
1493 * we do not need to block ath5k_tx_tasklet
1495 spin_lock_bh(&txq->lock);
1496 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1497 ath5k_debug_printtxbuf(sc, bf);
1499 ath5k_txbuf_free(sc, bf);
1501 spin_lock_bh(&sc->txbuflock);
1502 sc->tx_stats[txq->qnum].len--;
1503 list_move_tail(&bf->list, &sc->txbuf);
1505 spin_unlock_bh(&sc->txbuflock);
1508 spin_unlock_bh(&txq->lock);
1512 * Drain the transmit queues and reclaim resources.
1515 ath5k_txq_cleanup(struct ath5k_softc *sc)
1517 struct ath5k_hw *ah = sc->ah;
1520 /* XXX return value */
1521 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1522 /* don't touch the hardware if marked invalid */
1523 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1524 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1525 ath5k_hw_get_txdp(ah, sc->bhalq));
1526 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1527 if (sc->txqs[i].setup) {
1528 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1529 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1532 ath5k_hw_get_txdp(ah,
1537 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
1539 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1540 if (sc->txqs[i].setup)
1541 ath5k_txq_drainq(sc, &sc->txqs[i]);
1545 ath5k_txq_release(struct ath5k_softc *sc)
1547 struct ath5k_txq *txq = sc->txqs;
1550 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1552 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1565 * Enable the receive h/w following a reset.
1568 ath5k_rx_start(struct ath5k_softc *sc)
1570 struct ath5k_hw *ah = sc->ah;
1571 struct ath5k_buf *bf;
1574 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, sc->cachelsz);
1576 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1577 sc->cachelsz, sc->rxbufsize);
1581 spin_lock_bh(&sc->rxbuflock);
1582 list_for_each_entry(bf, &sc->rxbuf, list) {
1583 ret = ath5k_rxbuf_setup(sc, bf);
1585 spin_unlock_bh(&sc->rxbuflock);
1589 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1590 spin_unlock_bh(&sc->rxbuflock);
1592 ath5k_hw_set_rxdp(ah, bf->daddr);
1593 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
1594 ath5k_mode_setup(sc); /* set filters, etc. */
1595 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1603 * Disable the receive h/w in preparation for a reset.
1606 ath5k_rx_stop(struct ath5k_softc *sc)
1608 struct ath5k_hw *ah = sc->ah;
1610 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
1611 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1612 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
1614 ath5k_debug_printrxbuffs(sc, ah);
1616 sc->rxlink = NULL; /* just in case */
1620 ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
1621 struct sk_buff *skb, struct ath5k_rx_status *rs)
1623 struct ieee80211_hdr *hdr = (void *)skb->data;
1624 unsigned int keyix, hlen;
1626 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1627 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1628 return RX_FLAG_DECRYPTED;
1630 /* Apparently when a default key is used to decrypt the packet
1631 the hw does not set the index used to decrypt. In such cases
1632 get the index from the packet. */
1633 hlen = ieee80211_hdrlen(hdr->frame_control);
1634 if (ieee80211_has_protected(hdr->frame_control) &&
1635 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1636 skb->len >= hlen + 4) {
1637 keyix = skb->data[hlen + 3] >> 6;
1639 if (test_bit(keyix, sc->keymap))
1640 return RX_FLAG_DECRYPTED;
1648 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1649 struct ieee80211_rx_status *rxs)
1653 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1655 if (ieee80211_is_beacon(mgmt->frame_control) &&
1656 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1657 memcmp(mgmt->bssid, sc->ah->ah_bssid, ETH_ALEN) == 0) {
1659 * Received an IBSS beacon with the same BSSID. Hardware *must*
1660 * have updated the local TSF. We have to work around various
1661 * hardware bugs, though...
1663 tsf = ath5k_hw_get_tsf64(sc->ah);
1664 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1665 hw_tu = TSF_TO_TU(tsf);
1667 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1668 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1669 (unsigned long long)bc_tstamp,
1670 (unsigned long long)rxs->mactime,
1671 (unsigned long long)(rxs->mactime - bc_tstamp),
1672 (unsigned long long)tsf);
1675 * Sometimes the HW will give us a wrong tstamp in the rx
1676 * status, causing the timestamp extension to go wrong.
1677 * (This seems to happen especially with beacon frames bigger
1678 * than 78 byte (incl. FCS))
1679 * But we know that the receive timestamp must be later than the
1680 * timestamp of the beacon since HW must have synced to that.
1682 * NOTE: here we assume mactime to be after the frame was
1683 * received, not like mac80211 which defines it at the start.
1685 if (bc_tstamp > rxs->mactime) {
1686 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1687 "fixing mactime from %llx to %llx\n",
1688 (unsigned long long)rxs->mactime,
1689 (unsigned long long)tsf);
1694 * Local TSF might have moved higher than our beacon timers,
1695 * in that case we have to update them to continue sending
1696 * beacons. This also takes care of synchronizing beacon sending
1697 * times with other stations.
1699 if (hw_tu >= sc->nexttbtt)
1700 ath5k_beacon_update_timers(sc, bc_tstamp);
1704 static void ath5k_tasklet_beacon(unsigned long data)
1706 struct ath5k_softc *sc = (struct ath5k_softc *) data;
1709 * Software beacon alert--time to send a beacon.
1711 * In IBSS mode we use this interrupt just to
1712 * keep track of the next TBTT (target beacon
1713 * transmission time) in order to detect wether
1714 * automatic TSF updates happened.
1716 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1717 /* XXX: only if VEOL suppported */
1718 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
1719 sc->nexttbtt += sc->bintval;
1720 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1721 "SWBA nexttbtt: %x hw_tu: %x "
1725 (unsigned long long) tsf);
1727 spin_lock(&sc->block);
1728 ath5k_beacon_send(sc);
1729 spin_unlock(&sc->block);
1734 ath5k_tasklet_rx(unsigned long data)
1736 struct ieee80211_rx_status rxs = {};
1737 struct ath5k_rx_status rs = {};
1738 struct sk_buff *skb, *next_skb;
1739 dma_addr_t next_skb_addr;
1740 struct ath5k_softc *sc = (void *)data;
1741 struct ath5k_buf *bf, *bf_last;
1742 struct ath5k_desc *ds;
1747 spin_lock(&sc->rxbuflock);
1748 if (list_empty(&sc->rxbuf)) {
1749 ATH5K_WARN(sc, "empty rx buf pool\n");
1752 bf_last = list_entry(sc->rxbuf.prev, struct ath5k_buf, list);
1756 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1757 BUG_ON(bf->skb == NULL);
1762 * last buffer must not be freed to ensure proper hardware
1763 * function. When the hardware finishes also a packet next to
1764 * it, we are sure, it doesn't use it anymore and we can go on.
1769 struct ath5k_buf *bf_next = list_entry(bf->list.next,
1770 struct ath5k_buf, list);
1771 ret = sc->ah->ah_proc_rx_desc(sc->ah, bf_next->desc,
1776 /* skip the overwritten one (even status is martian) */
1780 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1781 if (unlikely(ret == -EINPROGRESS))
1783 else if (unlikely(ret)) {
1784 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1785 spin_unlock(&sc->rxbuflock);
1789 if (unlikely(rs.rs_more)) {
1790 ATH5K_WARN(sc, "unsupported jumbo\n");
1794 if (unlikely(rs.rs_status)) {
1795 if (rs.rs_status & AR5K_RXERR_PHY)
1797 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
1799 * Decrypt error. If the error occurred
1800 * because there was no hardware key, then
1801 * let the frame through so the upper layers
1802 * can process it. This is necessary for 5210
1803 * parts which have no way to setup a ``clear''
1806 * XXX do key cache faulting
1808 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1809 !(rs.rs_status & AR5K_RXERR_CRC))
1812 if (rs.rs_status & AR5K_RXERR_MIC) {
1813 rxs.flag |= RX_FLAG_MMIC_ERROR;
1817 /* let crypto-error packets fall through in MNTR */
1819 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
1820 sc->opmode != NL80211_IFTYPE_MONITOR)
1824 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
1827 * If we can't replace bf->skb with a new skb under memory
1828 * pressure, just skip this packet
1833 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1834 PCI_DMA_FROMDEVICE);
1835 skb_put(skb, rs.rs_datalen);
1837 /* The MAC header is padded to have 32-bit boundary if the
1838 * packet payload is non-zero. The general calculation for
1839 * padsize would take into account odd header lengths:
1840 * padsize = (4 - hdrlen % 4) % 4; However, since only
1841 * even-length headers are used, padding can only be 0 or 2
1842 * bytes and we can optimize this a bit. In addition, we must
1843 * not try to remove padding from short control frames that do
1844 * not have payload. */
1845 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1846 padsize = ath5k_pad_size(hdrlen);
1848 memmove(skb->data + padsize, skb->data, hdrlen);
1849 skb_pull(skb, padsize);
1853 * always extend the mac timestamp, since this information is
1854 * also needed for proper IBSS merging.
1856 * XXX: it might be too late to do it here, since rs_tstamp is
1857 * 15bit only. that means TSF extension has to be done within
1858 * 32768usec (about 32ms). it might be necessary to move this to
1859 * the interrupt handler, like it is done in madwifi.
1861 * Unfortunately we don't know when the hardware takes the rx
1862 * timestamp (beginning of phy frame, data frame, end of rx?).
1863 * The only thing we know is that it is hardware specific...
1864 * On AR5213 it seems the rx timestamp is at the end of the
1865 * frame, but i'm not sure.
1867 * NOTE: mac80211 defines mactime at the beginning of the first
1868 * data symbol. Since we don't have any time references it's
1869 * impossible to comply to that. This affects IBSS merge only
1870 * right now, so it's not too bad...
1872 rxs.mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
1873 rxs.flag |= RX_FLAG_TSFT;
1875 rxs.freq = sc->curchan->center_freq;
1876 rxs.band = sc->curband->band;
1878 rxs.noise = sc->ah->ah_noise_floor;
1879 rxs.signal = rxs.noise + rs.rs_rssi;
1881 /* An rssi of 35 indicates you should be able use
1882 * 54 Mbps reliably. A more elaborate scheme can be used
1883 * here but it requires a map of SNR/throughput for each
1884 * possible mode used */
1885 rxs.qual = rs.rs_rssi * 100 / 35;
1887 /* rssi can be more than 35 though, anything above that
1888 * should be considered at 100% */
1892 rxs.antenna = rs.rs_antenna;
1893 rxs.rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1894 rxs.flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
1896 if (rxs.rate_idx >= 0 && rs.rs_rate ==
1897 sc->curband->bitrates[rxs.rate_idx].hw_value_short)
1898 rxs.flag |= RX_FLAG_SHORTPRE;
1900 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1902 /* check beacons in IBSS mode */
1903 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1904 ath5k_check_ibss_tsf(sc, skb, &rxs);
1906 __ieee80211_rx(sc->hw, skb, &rxs);
1909 bf->skbaddr = next_skb_addr;
1911 list_move_tail(&bf->list, &sc->rxbuf);
1912 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1914 spin_unlock(&sc->rxbuflock);
1925 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1927 struct ath5k_tx_status ts = {};
1928 struct ath5k_buf *bf, *bf0;
1929 struct ath5k_desc *ds;
1930 struct sk_buff *skb;
1931 struct ieee80211_tx_info *info;
1934 spin_lock(&txq->lock);
1935 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1938 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1939 if (unlikely(ret == -EINPROGRESS))
1941 else if (unlikely(ret)) {
1942 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1948 info = IEEE80211_SKB_CB(skb);
1951 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1954 ieee80211_tx_info_clear_status(info);
1955 for (i = 0; i < 4; i++) {
1956 struct ieee80211_tx_rate *r =
1957 &info->status.rates[i];
1959 if (ts.ts_rate[i]) {
1960 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
1961 r->count = ts.ts_retry[i];
1968 /* count the successful attempt as well */
1969 info->status.rates[ts.ts_final_idx].count++;
1971 if (unlikely(ts.ts_status)) {
1972 sc->ll_stats.dot11ACKFailureCount++;
1973 if (ts.ts_status & AR5K_TXERR_FILT)
1974 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1976 info->flags |= IEEE80211_TX_STAT_ACK;
1977 info->status.ack_signal = ts.ts_rssi;
1980 ieee80211_tx_status(sc->hw, skb);
1981 sc->tx_stats[txq->qnum].count++;
1983 spin_lock(&sc->txbuflock);
1984 sc->tx_stats[txq->qnum].len--;
1985 list_move_tail(&bf->list, &sc->txbuf);
1987 spin_unlock(&sc->txbuflock);
1989 if (likely(list_empty(&txq->q)))
1991 spin_unlock(&txq->lock);
1992 if (sc->txbuf_len > ATH_TXBUF / 5)
1993 ieee80211_wake_queues(sc->hw);
1997 ath5k_tasklet_tx(unsigned long data)
1999 struct ath5k_softc *sc = (void *)data;
2001 ath5k_tx_processq(sc, sc->txq);
2010 * Setup the beacon frame for transmit.
2013 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
2015 struct sk_buff *skb = bf->skb;
2016 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2017 struct ath5k_hw *ah = sc->ah;
2018 struct ath5k_desc *ds;
2019 int ret, antenna = 0;
2022 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
2024 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
2025 "skbaddr %llx\n", skb, skb->data, skb->len,
2026 (unsigned long long)bf->skbaddr);
2027 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
2028 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
2034 flags = AR5K_TXDESC_NOACK;
2035 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
2036 ds->ds_link = bf->daddr; /* self-linked */
2037 flags |= AR5K_TXDESC_VEOL;
2039 * Let hardware handle antenna switching if txantenna is not set
2044 * Switch antenna every 4 beacons if txantenna is not set
2045 * XXX assumes two antennas
2048 antenna = sc->bsent & 4 ? 2 : 1;
2051 ds->ds_data = bf->skbaddr;
2052 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
2053 ieee80211_get_hdrlen_from_skb(skb),
2054 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
2055 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2056 1, AR5K_TXKEYIX_INVALID,
2057 antenna, flags, 0, 0);
2063 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
2068 * Transmit a beacon frame at SWBA. Dynamic updates to the
2069 * frame contents are done as needed and the slot time is
2070 * also adjusted based on current state.
2072 * This is called from software irq context (beacontq or restq
2073 * tasklets) or user context from ath5k_beacon_config.
2076 ath5k_beacon_send(struct ath5k_softc *sc)
2078 struct ath5k_buf *bf = sc->bbuf;
2079 struct ath5k_hw *ah = sc->ah;
2081 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
2083 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
2084 sc->opmode == NL80211_IFTYPE_MONITOR)) {
2085 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2089 * Check if the previous beacon has gone out. If
2090 * not don't don't try to post another, skip this
2091 * period and wait for the next. Missed beacons
2092 * indicate a problem and should not occur. If we
2093 * miss too many consecutive beacons reset the device.
2095 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2097 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2098 "missed %u consecutive beacons\n", sc->bmisscount);
2099 if (sc->bmisscount > 3) { /* NB: 3 is a guess */
2100 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2101 "stuck beacon time (%u missed)\n",
2103 tasklet_schedule(&sc->restq);
2107 if (unlikely(sc->bmisscount != 0)) {
2108 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2109 "resume beacon xmit after %u misses\n",
2115 * Stop any current dma and put the new frame on the queue.
2116 * This should never fail since we check above that no frames
2117 * are still pending on the queue.
2119 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2120 ATH5K_WARN(sc, "beacon queue %u didn't stop?\n", sc->bhalq);
2121 /* NB: hw still stops DMA, so proceed */
2124 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2125 ath5k_hw_start_tx_dma(ah, sc->bhalq);
2126 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
2127 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2134 * ath5k_beacon_update_timers - update beacon timers
2136 * @sc: struct ath5k_softc pointer we are operating on
2137 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2138 * beacon timer update based on the current HW TSF.
2140 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2141 * of a received beacon or the current local hardware TSF and write it to the
2142 * beacon timer registers.
2144 * This is called in a variety of situations, e.g. when a beacon is received,
2145 * when a TSF update has been detected, but also when an new IBSS is created or
2146 * when we otherwise know we have to update the timers, but we keep it in this
2147 * function to have it all together in one place.
2150 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
2152 struct ath5k_hw *ah = sc->ah;
2153 u32 nexttbtt, intval, hw_tu, bc_tu;
2156 intval = sc->bintval & AR5K_BEACON_PERIOD;
2157 if (WARN_ON(!intval))
2160 /* beacon TSF converted to TU */
2161 bc_tu = TSF_TO_TU(bc_tsf);
2163 /* current TSF converted to TU */
2164 hw_tsf = ath5k_hw_get_tsf64(ah);
2165 hw_tu = TSF_TO_TU(hw_tsf);
2168 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2171 * no beacons received, called internally.
2172 * just need to refresh timers based on HW TSF.
2174 nexttbtt = roundup(hw_tu + FUDGE, intval);
2175 } else if (bc_tsf == 0) {
2177 * no beacon received, probably called by ath5k_reset_tsf().
2178 * reset TSF to start with 0.
2181 intval |= AR5K_BEACON_RESET_TSF;
2182 } else if (bc_tsf > hw_tsf) {
2184 * beacon received, SW merge happend but HW TSF not yet updated.
2185 * not possible to reconfigure timers yet, but next time we
2186 * receive a beacon with the same BSSID, the hardware will
2187 * automatically update the TSF and then we need to reconfigure
2190 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2191 "need to wait for HW TSF sync\n");
2195 * most important case for beacon synchronization between STA.
2197 * beacon received and HW TSF has been already updated by HW.
2198 * update next TBTT based on the TSF of the beacon, but make
2199 * sure it is ahead of our local TSF timer.
2201 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2205 sc->nexttbtt = nexttbtt;
2207 intval |= AR5K_BEACON_ENA;
2208 ath5k_hw_init_beacon(ah, nexttbtt, intval);
2211 * debugging output last in order to preserve the time critical aspect
2215 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2216 "reconfigured timers based on HW TSF\n");
2217 else if (bc_tsf == 0)
2218 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2219 "reset HW TSF and timers\n");
2221 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2222 "updated timers based on beacon TSF\n");
2224 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2225 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2226 (unsigned long long) bc_tsf,
2227 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2228 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2229 intval & AR5K_BEACON_PERIOD,
2230 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2231 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2236 * ath5k_beacon_config - Configure the beacon queues and interrupts
2238 * @sc: struct ath5k_softc pointer we are operating on
2240 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2241 * interrupts to detect TSF updates only.
2244 ath5k_beacon_config(struct ath5k_softc *sc)
2246 struct ath5k_hw *ah = sc->ah;
2247 unsigned long flags;
2249 ath5k_hw_set_imr(ah, 0);
2251 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2253 if (sc->opmode == NL80211_IFTYPE_ADHOC ||
2254 sc->opmode == NL80211_IFTYPE_MESH_POINT ||
2255 sc->opmode == NL80211_IFTYPE_AP) {
2257 * In IBSS mode we use a self-linked tx descriptor and let the
2258 * hardware send the beacons automatically. We have to load it
2260 * We use the SWBA interrupt only to keep track of the beacon
2261 * timers in order to detect automatic TSF updates.
2263 ath5k_beaconq_config(sc);
2265 sc->imask |= AR5K_INT_SWBA;
2267 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2268 if (ath5k_hw_hasveol(ah)) {
2269 spin_lock_irqsave(&sc->block, flags);
2270 ath5k_beacon_send(sc);
2271 spin_unlock_irqrestore(&sc->block, flags);
2274 ath5k_beacon_update_timers(sc, -1);
2277 ath5k_hw_set_imr(ah, sc->imask);
2281 /********************\
2282 * Interrupt handling *
2283 \********************/
2286 ath5k_init(struct ath5k_softc *sc)
2288 struct ath5k_hw *ah = sc->ah;
2291 mutex_lock(&sc->lock);
2293 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2296 * Stop anything previously setup. This is safe
2297 * no matter this is the first time through or not.
2299 ath5k_stop_locked(sc);
2302 * The basic interface to setting the hardware in a good
2303 * state is ``reset''. On return the hardware is known to
2304 * be powered up and with interrupts disabled. This must
2305 * be followed by initialization of the appropriate bits
2306 * and then setup of the interrupt mask.
2308 sc->curchan = sc->hw->conf.channel;
2309 sc->curband = &sc->sbands[sc->curchan->band];
2310 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2311 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2312 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB;
2313 ret = ath5k_reset(sc, false, false);
2318 * Reset the key cache since some parts do not reset the
2319 * contents on initial power up or resume from suspend.
2321 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2322 ath5k_hw_reset_key(ah, i);
2324 /* Set ack to be sent at low bit-rates */
2325 ath5k_hw_set_ack_bitrate_high(ah, false);
2327 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2328 msecs_to_jiffies(ath5k_calinterval * 1000)));
2333 mutex_unlock(&sc->lock);
2338 ath5k_stop_locked(struct ath5k_softc *sc)
2340 struct ath5k_hw *ah = sc->ah;
2342 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2343 test_bit(ATH_STAT_INVALID, sc->status));
2346 * Shutdown the hardware and driver:
2347 * stop output from above
2348 * disable interrupts
2350 * turn off the radio
2351 * clear transmit machinery
2352 * clear receive machinery
2353 * drain and release tx queues
2354 * reclaim beacon resources
2355 * power down hardware
2357 * Note that some of this work is not possible if the
2358 * hardware is gone (invalid).
2360 ieee80211_stop_queues(sc->hw);
2362 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2364 ath5k_hw_set_imr(ah, 0);
2365 synchronize_irq(sc->pdev->irq);
2367 ath5k_txq_cleanup(sc);
2368 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2370 ath5k_hw_phy_disable(ah);
2378 * Stop the device, grabbing the top-level lock to protect
2379 * against concurrent entry through ath5k_init (which can happen
2380 * if another thread does a system call and the thread doing the
2381 * stop is preempted).
2384 ath5k_stop_hw(struct ath5k_softc *sc)
2388 mutex_lock(&sc->lock);
2389 ret = ath5k_stop_locked(sc);
2390 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2392 * Set the chip in full sleep mode. Note that we are
2393 * careful to do this only when bringing the interface
2394 * completely to a stop. When the chip is in this state
2395 * it must be carefully woken up or references to
2396 * registers in the PCI clock domain may freeze the bus
2397 * (and system). This varies by chip and is mostly an
2398 * issue with newer parts that go to sleep more quickly.
2400 if (sc->ah->ah_mac_srev >= 0x78) {
2403 * don't put newer MAC revisions > 7.8 to sleep because
2404 * of the above mentioned problems
2406 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mac version > 7.8, "
2407 "not putting device to sleep\n");
2409 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2410 "putting device to full sleep\n");
2411 ath5k_hw_set_power(sc->ah, AR5K_PM_FULL_SLEEP, true, 0);
2414 ath5k_txbuf_free(sc, sc->bbuf);
2417 mutex_unlock(&sc->lock);
2419 del_timer_sync(&sc->calib_tim);
2420 tasklet_kill(&sc->rxtq);
2421 tasklet_kill(&sc->txtq);
2422 tasklet_kill(&sc->restq);
2423 tasklet_kill(&sc->beacontq);
2429 ath5k_intr(int irq, void *dev_id)
2431 struct ath5k_softc *sc = dev_id;
2432 struct ath5k_hw *ah = sc->ah;
2433 enum ath5k_int status;
2434 unsigned int counter = 1000;
2436 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2437 !ath5k_hw_is_intr_pending(ah)))
2441 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2442 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2444 if (unlikely(status & AR5K_INT_FATAL)) {
2446 * Fatal errors are unrecoverable.
2447 * Typically these are caused by DMA errors.
2449 tasklet_schedule(&sc->restq);
2450 } else if (unlikely(status & AR5K_INT_RXORN)) {
2451 tasklet_schedule(&sc->restq);
2453 if (status & AR5K_INT_SWBA) {
2454 tasklet_schedule(&sc->beacontq);
2456 if (status & AR5K_INT_RXEOL) {
2458 * NB: the hardware should re-read the link when
2459 * RXE bit is written, but it doesn't work at
2460 * least on older hardware revs.
2464 if (status & AR5K_INT_TXURN) {
2465 /* bump tx trigger level */
2466 ath5k_hw_update_tx_triglevel(ah, true);
2468 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
2469 tasklet_schedule(&sc->rxtq);
2470 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2471 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
2472 tasklet_schedule(&sc->txtq);
2473 if (status & AR5K_INT_BMISS) {
2476 if (status & AR5K_INT_MIB) {
2478 * These stats are also used for ANI i think
2479 * so how about updating them more often ?
2481 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
2484 } while (ath5k_hw_is_intr_pending(ah) && counter-- > 0);
2486 if (unlikely(!counter))
2487 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2493 ath5k_tasklet_reset(unsigned long data)
2495 struct ath5k_softc *sc = (void *)data;
2497 ath5k_reset_wake(sc);
2501 * Periodically recalibrate the PHY to account
2502 * for temperature/environment changes.
2505 ath5k_calibrate(unsigned long data)
2507 struct ath5k_softc *sc = (void *)data;
2508 struct ath5k_hw *ah = sc->ah;
2510 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2511 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2512 sc->curchan->hw_value);
2514 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2516 * Rfgain is out of bounds, reset the chip
2517 * to load new gain values.
2519 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2520 ath5k_reset_wake(sc);
2522 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2523 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2524 ieee80211_frequency_to_channel(
2525 sc->curchan->center_freq));
2527 mod_timer(&sc->calib_tim, round_jiffies(jiffies +
2528 msecs_to_jiffies(ath5k_calinterval * 1000)));
2538 ath5k_led_enable(struct ath5k_softc *sc)
2540 if (test_bit(ATH_STAT_LEDSOFT, sc->status)) {
2541 ath5k_hw_set_gpio_output(sc->ah, sc->led_pin);
2547 ath5k_led_on(struct ath5k_softc *sc)
2549 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2551 ath5k_hw_set_gpio(sc->ah, sc->led_pin, sc->led_on);
2555 ath5k_led_off(struct ath5k_softc *sc)
2557 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2559 ath5k_hw_set_gpio(sc->ah, sc->led_pin, !sc->led_on);
2563 ath5k_led_brightness_set(struct led_classdev *led_dev,
2564 enum led_brightness brightness)
2566 struct ath5k_led *led = container_of(led_dev, struct ath5k_led,
2569 if (brightness == LED_OFF)
2570 ath5k_led_off(led->sc);
2572 ath5k_led_on(led->sc);
2576 ath5k_register_led(struct ath5k_softc *sc, struct ath5k_led *led,
2577 const char *name, char *trigger)
2582 strncpy(led->name, name, sizeof(led->name));
2583 led->led_dev.name = led->name;
2584 led->led_dev.default_trigger = trigger;
2585 led->led_dev.brightness_set = ath5k_led_brightness_set;
2587 err = led_classdev_register(&sc->pdev->dev, &led->led_dev);
2589 ATH5K_WARN(sc, "could not register LED %s\n", name);
2596 ath5k_unregister_led(struct ath5k_led *led)
2600 led_classdev_unregister(&led->led_dev);
2601 ath5k_led_off(led->sc);
2606 ath5k_unregister_leds(struct ath5k_softc *sc)
2608 ath5k_unregister_led(&sc->rx_led);
2609 ath5k_unregister_led(&sc->tx_led);
2614 ath5k_init_leds(struct ath5k_softc *sc)
2617 struct ieee80211_hw *hw = sc->hw;
2618 struct pci_dev *pdev = sc->pdev;
2619 char name[ATH5K_LED_MAX_NAME_LEN + 1];
2622 * Auto-enable soft led processing for IBM cards and for
2623 * 5211 minipci cards.
2625 if (pdev->device == PCI_DEVICE_ID_ATHEROS_AR5212_IBM ||
2626 pdev->device == PCI_DEVICE_ID_ATHEROS_AR5211) {
2627 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2629 sc->led_on = 0; /* active low */
2631 /* Enable softled on PIN1 on HP Compaq nc6xx, nc4000 & nx5000 laptops */
2632 if (pdev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ) {
2633 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2635 sc->led_on = 1; /* active high */
2638 * Pin 3 on Foxconn chips used in Acer Aspire One (0x105b:e008) and
2639 * in emachines notebooks with AMBIT subsystem.
2641 if (pdev->subsystem_vendor == PCI_VENDOR_ID_FOXCONN ||
2642 pdev->subsystem_vendor == PCI_VENDOR_ID_AMBIT) {
2643 __set_bit(ATH_STAT_LEDSOFT, sc->status);
2645 sc->led_on = 0; /* active low */
2648 if (!test_bit(ATH_STAT_LEDSOFT, sc->status))
2651 ath5k_led_enable(sc);
2653 snprintf(name, sizeof(name), "ath5k-%s::rx", wiphy_name(hw->wiphy));
2654 ret = ath5k_register_led(sc, &sc->rx_led, name,
2655 ieee80211_get_rx_led_name(hw));
2659 snprintf(name, sizeof(name), "ath5k-%s::tx", wiphy_name(hw->wiphy));
2660 ret = ath5k_register_led(sc, &sc->tx_led, name,
2661 ieee80211_get_tx_led_name(hw));
2667 /********************\
2668 * Mac80211 functions *
2669 \********************/
2672 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2674 struct ath5k_softc *sc = hw->priv;
2675 struct ath5k_buf *bf;
2676 unsigned long flags;
2680 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2682 if (sc->opmode == NL80211_IFTYPE_MONITOR)
2683 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2686 * the hardware expects the header padded to 4 byte boundaries
2687 * if this is not the case we add the padding after the header
2689 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2690 padsize = ath5k_pad_size(hdrlen);
2693 if (skb_headroom(skb) < padsize) {
2694 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2695 " headroom to pad %d\n", hdrlen, padsize);
2696 return NETDEV_TX_BUSY;
2698 skb_push(skb, padsize);
2699 memmove(skb->data, skb->data+padsize, hdrlen);
2702 spin_lock_irqsave(&sc->txbuflock, flags);
2703 if (list_empty(&sc->txbuf)) {
2704 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2705 spin_unlock_irqrestore(&sc->txbuflock, flags);
2706 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
2707 return NETDEV_TX_BUSY;
2709 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2710 list_del(&bf->list);
2712 if (list_empty(&sc->txbuf))
2713 ieee80211_stop_queues(hw);
2714 spin_unlock_irqrestore(&sc->txbuflock, flags);
2718 if (ath5k_txbuf_setup(sc, bf)) {
2720 spin_lock_irqsave(&sc->txbuflock, flags);
2721 list_add_tail(&bf->list, &sc->txbuf);
2723 spin_unlock_irqrestore(&sc->txbuflock, flags);
2724 dev_kfree_skb_any(skb);
2725 return NETDEV_TX_OK;
2728 return NETDEV_TX_OK;
2732 ath5k_reset(struct ath5k_softc *sc, bool stop, bool change_channel)
2734 struct ath5k_hw *ah = sc->ah;
2737 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2740 ath5k_hw_set_imr(ah, 0);
2741 ath5k_txq_cleanup(sc);
2744 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, true);
2746 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2751 * This is needed only to setup initial state
2752 * but it's best done after a reset.
2754 ath5k_hw_set_txpower_limit(sc->ah, 0);
2756 ret = ath5k_rx_start(sc);
2758 ATH5K_ERR(sc, "can't start recv logic\n");
2763 * Change channels and update the h/w rate map if we're switching;
2764 * e.g. 11a to 11b/g.
2766 * We may be doing a reset in response to an ioctl that changes the
2767 * channel so update any state that might change as a result.
2771 /* ath5k_chan_change(sc, c); */
2773 ath5k_beacon_config(sc);
2774 /* intrs are enabled by ath5k_beacon_config */
2782 ath5k_reset_wake(struct ath5k_softc *sc)
2786 ret = ath5k_reset(sc, true, true);
2788 ieee80211_wake_queues(sc->hw);
2793 static int ath5k_start(struct ieee80211_hw *hw)
2795 return ath5k_init(hw->priv);
2798 static void ath5k_stop(struct ieee80211_hw *hw)
2800 ath5k_stop_hw(hw->priv);
2803 static int ath5k_add_interface(struct ieee80211_hw *hw,
2804 struct ieee80211_if_init_conf *conf)
2806 struct ath5k_softc *sc = hw->priv;
2809 mutex_lock(&sc->lock);
2815 sc->vif = conf->vif;
2817 switch (conf->type) {
2818 case NL80211_IFTYPE_AP:
2819 case NL80211_IFTYPE_STATION:
2820 case NL80211_IFTYPE_ADHOC:
2821 case NL80211_IFTYPE_MESH_POINT:
2822 case NL80211_IFTYPE_MONITOR:
2823 sc->opmode = conf->type;
2830 /* Set to a reasonable value. Note that this will
2831 * be set to mac80211's value at ath5k_config(). */
2833 ath5k_hw_set_lladdr(sc->ah, conf->mac_addr);
2837 mutex_unlock(&sc->lock);
2842 ath5k_remove_interface(struct ieee80211_hw *hw,
2843 struct ieee80211_if_init_conf *conf)
2845 struct ath5k_softc *sc = hw->priv;
2846 u8 mac[ETH_ALEN] = {};
2848 mutex_lock(&sc->lock);
2849 if (sc->vif != conf->vif)
2852 ath5k_hw_set_lladdr(sc->ah, mac);
2855 mutex_unlock(&sc->lock);
2859 * TODO: Phy disable/diversity etc
2862 ath5k_config(struct ieee80211_hw *hw, u32 changed)
2864 struct ath5k_softc *sc = hw->priv;
2865 struct ieee80211_conf *conf = &hw->conf;
2868 mutex_lock(&sc->lock);
2870 sc->bintval = conf->beacon_int;
2871 sc->power_level = conf->power_level;
2873 ret = ath5k_chan_set(sc, conf->channel);
2875 mutex_unlock(&sc->lock);
2880 ath5k_config_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2881 struct ieee80211_if_conf *conf)
2883 struct ath5k_softc *sc = hw->priv;
2884 struct ath5k_hw *ah = sc->ah;
2887 mutex_lock(&sc->lock);
2888 if (sc->vif != vif) {
2892 if (conf->changed & IEEE80211_IFCC_BSSID && conf->bssid) {
2893 /* Cache for later use during resets */
2894 memcpy(ah->ah_bssid, conf->bssid, ETH_ALEN);
2895 /* XXX: assoc id is set to 0 for now, mac80211 doesn't have
2896 * a clean way of letting us retrieve this yet. */
2897 ath5k_hw_set_associd(ah, ah->ah_bssid, 0);
2900 if (conf->changed & IEEE80211_IFCC_BEACON &&
2901 (vif->type == NL80211_IFTYPE_ADHOC ||
2902 vif->type == NL80211_IFTYPE_MESH_POINT ||
2903 vif->type == NL80211_IFTYPE_AP)) {
2904 struct sk_buff *beacon = ieee80211_beacon_get(hw, vif);
2909 ath5k_beacon_update(sc, beacon);
2913 mutex_unlock(&sc->lock);
2917 #define SUPPORTED_FIF_FLAGS \
2918 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2919 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2920 FIF_BCN_PRBRESP_PROMISC
2922 * o always accept unicast, broadcast, and multicast traffic
2923 * o multicast traffic for all BSSIDs will be enabled if mac80211
2925 * o maintain current state of phy ofdm or phy cck error reception.
2926 * If the hardware detects any of these type of errors then
2927 * ath5k_hw_get_rx_filter() will pass to us the respective
2928 * hardware filters to be able to receive these type of frames.
2929 * o probe request frames are accepted only when operating in
2930 * hostap, adhoc, or monitor modes
2931 * o enable promiscuous mode according to the interface state
2933 * - when operating in adhoc mode so the 802.11 layer creates
2934 * node table entries for peers,
2935 * - when operating in station mode for collecting rssi data when
2936 * the station is otherwise quiet, or
2939 static void ath5k_configure_filter(struct ieee80211_hw *hw,
2940 unsigned int changed_flags,
2941 unsigned int *new_flags,
2942 int mc_count, struct dev_mc_list *mclist)
2944 struct ath5k_softc *sc = hw->priv;
2945 struct ath5k_hw *ah = sc->ah;
2946 u32 mfilt[2], val, rfilt;
2953 /* Only deal with supported flags */
2954 changed_flags &= SUPPORTED_FIF_FLAGS;
2955 *new_flags &= SUPPORTED_FIF_FLAGS;
2957 /* If HW detects any phy or radar errors, leave those filters on.
2958 * Also, always enable Unicast, Broadcasts and Multicast
2959 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2960 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2961 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2962 AR5K_RX_FILTER_MCAST);
2964 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2965 if (*new_flags & FIF_PROMISC_IN_BSS) {
2966 rfilt |= AR5K_RX_FILTER_PROM;
2967 __set_bit(ATH_STAT_PROMISC, sc->status);
2969 __clear_bit(ATH_STAT_PROMISC, sc->status);
2973 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2974 if (*new_flags & FIF_ALLMULTI) {
2978 for (i = 0; i < mc_count; i++) {
2981 /* calculate XOR of eight 6-bit values */
2982 val = get_unaligned_le32(mclist->dmi_addr + 0);
2983 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2984 val = get_unaligned_le32(mclist->dmi_addr + 3);
2985 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2987 mfilt[pos / 32] |= (1 << (pos % 32));
2988 /* XXX: we might be able to just do this instead,
2989 * but not sure, needs testing, if we do use this we'd
2990 * neet to inform below to not reset the mcast */
2991 /* ath5k_hw_set_mcast_filterindex(ah,
2992 * mclist->dmi_addr[5]); */
2993 mclist = mclist->next;
2997 /* This is the best we can do */
2998 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2999 rfilt |= AR5K_RX_FILTER_PHYERR;
3001 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
3002 * and probes for any BSSID, this needs testing */
3003 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
3004 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
3006 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
3007 * set we should only pass on control frames for this
3008 * station. This needs testing. I believe right now this
3009 * enables *all* control frames, which is OK.. but
3010 * but we should see if we can improve on granularity */
3011 if (*new_flags & FIF_CONTROL)
3012 rfilt |= AR5K_RX_FILTER_CONTROL;
3014 /* Additional settings per mode -- this is per ath5k */
3016 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
3018 if (sc->opmode == NL80211_IFTYPE_MONITOR)
3019 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
3020 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
3021 if (sc->opmode != NL80211_IFTYPE_STATION)
3022 rfilt |= AR5K_RX_FILTER_PROBEREQ;
3023 if (sc->opmode != NL80211_IFTYPE_AP &&
3024 sc->opmode != NL80211_IFTYPE_MESH_POINT &&
3025 test_bit(ATH_STAT_PROMISC, sc->status))
3026 rfilt |= AR5K_RX_FILTER_PROM;
3027 if ((sc->opmode == NL80211_IFTYPE_STATION && sc->assoc) ||
3028 sc->opmode == NL80211_IFTYPE_ADHOC ||
3029 sc->opmode == NL80211_IFTYPE_AP)
3030 rfilt |= AR5K_RX_FILTER_BEACON;
3031 if (sc->opmode == NL80211_IFTYPE_MESH_POINT)
3032 rfilt |= AR5K_RX_FILTER_CONTROL | AR5K_RX_FILTER_BEACON |
3033 AR5K_RX_FILTER_PROBEREQ | AR5K_RX_FILTER_PROM;
3036 ath5k_hw_set_rx_filter(ah, rfilt);
3038 /* Set multicast bits */
3039 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
3040 /* Set the cached hw filter flags, this will alter actually
3042 sc->filter_flags = rfilt;
3046 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3047 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3048 struct ieee80211_key_conf *key)
3050 struct ath5k_softc *sc = hw->priv;
3053 if (modparam_nohwcrypt)
3067 mutex_lock(&sc->lock);
3071 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key,
3072 sta ? sta->addr : NULL);
3074 ATH5K_ERR(sc, "can't set the key\n");
3077 __set_bit(key->keyidx, sc->keymap);
3078 key->hw_key_idx = key->keyidx;
3079 key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV |
3080 IEEE80211_KEY_FLAG_GENERATE_MMIC);
3083 ath5k_hw_reset_key(sc->ah, key->keyidx);
3084 __clear_bit(key->keyidx, sc->keymap);
3093 mutex_unlock(&sc->lock);
3098 ath5k_get_stats(struct ieee80211_hw *hw,
3099 struct ieee80211_low_level_stats *stats)
3101 struct ath5k_softc *sc = hw->priv;
3102 struct ath5k_hw *ah = sc->ah;
3105 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
3107 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
3113 ath5k_get_tx_stats(struct ieee80211_hw *hw,
3114 struct ieee80211_tx_queue_stats *stats)
3116 struct ath5k_softc *sc = hw->priv;
3118 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
3124 ath5k_get_tsf(struct ieee80211_hw *hw)
3126 struct ath5k_softc *sc = hw->priv;
3128 return ath5k_hw_get_tsf64(sc->ah);
3132 ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3134 struct ath5k_softc *sc = hw->priv;
3136 ath5k_hw_set_tsf64(sc->ah, tsf);
3140 ath5k_reset_tsf(struct ieee80211_hw *hw)
3142 struct ath5k_softc *sc = hw->priv;
3145 * in IBSS mode we need to update the beacon timers too.
3146 * this will also reset the TSF if we call it with 0
3148 if (sc->opmode == NL80211_IFTYPE_ADHOC)
3149 ath5k_beacon_update_timers(sc, 0);
3151 ath5k_hw_reset_tsf(sc->ah);
3155 ath5k_beacon_update(struct ath5k_softc *sc, struct sk_buff *skb)
3157 unsigned long flags;
3160 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3162 spin_lock_irqsave(&sc->block, flags);
3163 ath5k_txbuf_free(sc, sc->bbuf);
3164 sc->bbuf->skb = skb;
3165 ret = ath5k_beacon_setup(sc, sc->bbuf);
3167 sc->bbuf->skb = NULL;
3168 spin_unlock_irqrestore(&sc->block, flags);
3170 ath5k_beacon_config(sc);
3177 set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3179 struct ath5k_softc *sc = hw->priv;
3180 struct ath5k_hw *ah = sc->ah;
3182 rfilt = ath5k_hw_get_rx_filter(ah);
3184 rfilt |= AR5K_RX_FILTER_BEACON;
3186 rfilt &= ~AR5K_RX_FILTER_BEACON;
3187 ath5k_hw_set_rx_filter(ah, rfilt);
3188 sc->filter_flags = rfilt;
3191 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3192 struct ieee80211_vif *vif,
3193 struct ieee80211_bss_conf *bss_conf,
3196 struct ath5k_softc *sc = hw->priv;
3197 if (changes & BSS_CHANGED_ASSOC) {
3198 mutex_lock(&sc->lock);
3199 sc->assoc = bss_conf->assoc;
3200 if (sc->opmode == NL80211_IFTYPE_STATION)
3201 set_beacon_filter(hw, sc->assoc);
3202 mutex_unlock(&sc->lock);