2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/nl80211.h>
21 static char *dev_info = "ath9k";
23 MODULE_AUTHOR("Atheros Communications");
24 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
25 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
26 MODULE_LICENSE("Dual BSD/GPL");
28 static int modparam_nohwcrypt;
29 module_param_named(nohwcrypt, modparam_nohwcrypt, int, 0444);
30 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
32 /* We use the hw_value as an index into our private channel structure */
34 #define CHAN2G(_freq, _idx) { \
35 .center_freq = (_freq), \
40 #define CHAN5G(_freq, _idx) { \
41 .band = IEEE80211_BAND_5GHZ, \
42 .center_freq = (_freq), \
47 /* Some 2 GHz radios are actually tunable on 2312-2732
48 * on 5 MHz steps, we support the channels which we know
49 * we have calibration data for all cards though to make
51 static struct ieee80211_channel ath9k_2ghz_chantable[] = {
52 CHAN2G(2412, 0), /* Channel 1 */
53 CHAN2G(2417, 1), /* Channel 2 */
54 CHAN2G(2422, 2), /* Channel 3 */
55 CHAN2G(2427, 3), /* Channel 4 */
56 CHAN2G(2432, 4), /* Channel 5 */
57 CHAN2G(2437, 5), /* Channel 6 */
58 CHAN2G(2442, 6), /* Channel 7 */
59 CHAN2G(2447, 7), /* Channel 8 */
60 CHAN2G(2452, 8), /* Channel 9 */
61 CHAN2G(2457, 9), /* Channel 10 */
62 CHAN2G(2462, 10), /* Channel 11 */
63 CHAN2G(2467, 11), /* Channel 12 */
64 CHAN2G(2472, 12), /* Channel 13 */
65 CHAN2G(2484, 13), /* Channel 14 */
68 /* Some 5 GHz radios are actually tunable on XXXX-YYYY
69 * on 5 MHz steps, we support the channels which we know
70 * we have calibration data for all cards though to make
72 static struct ieee80211_channel ath9k_5ghz_chantable[] = {
73 /* _We_ call this UNII 1 */
74 CHAN5G(5180, 14), /* Channel 36 */
75 CHAN5G(5200, 15), /* Channel 40 */
76 CHAN5G(5220, 16), /* Channel 44 */
77 CHAN5G(5240, 17), /* Channel 48 */
78 /* _We_ call this UNII 2 */
79 CHAN5G(5260, 18), /* Channel 52 */
80 CHAN5G(5280, 19), /* Channel 56 */
81 CHAN5G(5300, 20), /* Channel 60 */
82 CHAN5G(5320, 21), /* Channel 64 */
83 /* _We_ call this "Middle band" */
84 CHAN5G(5500, 22), /* Channel 100 */
85 CHAN5G(5520, 23), /* Channel 104 */
86 CHAN5G(5540, 24), /* Channel 108 */
87 CHAN5G(5560, 25), /* Channel 112 */
88 CHAN5G(5580, 26), /* Channel 116 */
89 CHAN5G(5600, 27), /* Channel 120 */
90 CHAN5G(5620, 28), /* Channel 124 */
91 CHAN5G(5640, 29), /* Channel 128 */
92 CHAN5G(5660, 30), /* Channel 132 */
93 CHAN5G(5680, 31), /* Channel 136 */
94 CHAN5G(5700, 32), /* Channel 140 */
95 /* _We_ call this UNII 3 */
96 CHAN5G(5745, 33), /* Channel 149 */
97 CHAN5G(5765, 34), /* Channel 153 */
98 CHAN5G(5785, 35), /* Channel 157 */
99 CHAN5G(5805, 36), /* Channel 161 */
100 CHAN5G(5825, 37), /* Channel 165 */
103 static void ath_cache_conf_rate(struct ath_softc *sc,
104 struct ieee80211_conf *conf)
106 switch (conf->channel->band) {
107 case IEEE80211_BAND_2GHZ:
108 if (conf_is_ht20(conf))
110 sc->hw_rate_table[ATH9K_MODE_11NG_HT20];
111 else if (conf_is_ht40_minus(conf))
113 sc->hw_rate_table[ATH9K_MODE_11NG_HT40MINUS];
114 else if (conf_is_ht40_plus(conf))
116 sc->hw_rate_table[ATH9K_MODE_11NG_HT40PLUS];
119 sc->hw_rate_table[ATH9K_MODE_11G];
121 case IEEE80211_BAND_5GHZ:
122 if (conf_is_ht20(conf))
124 sc->hw_rate_table[ATH9K_MODE_11NA_HT20];
125 else if (conf_is_ht40_minus(conf))
127 sc->hw_rate_table[ATH9K_MODE_11NA_HT40MINUS];
128 else if (conf_is_ht40_plus(conf))
130 sc->hw_rate_table[ATH9K_MODE_11NA_HT40PLUS];
133 sc->hw_rate_table[ATH9K_MODE_11A];
141 static void ath_update_txpow(struct ath_softc *sc)
143 struct ath_hw *ah = sc->sc_ah;
146 if (sc->curtxpow != sc->config.txpowlimit) {
147 ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
148 /* read back in case value is clamped */
149 ath9k_hw_getcapability(ah, ATH9K_CAP_TXPOW, 1, &txpow);
150 sc->curtxpow = txpow;
154 static u8 parse_mpdudensity(u8 mpdudensity)
157 * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
158 * 0 for no restriction
167 switch (mpdudensity) {
173 /* Our lower layer calculations limit our precision to
189 static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
191 const struct ath_rate_table *rate_table = NULL;
192 struct ieee80211_supported_band *sband;
193 struct ieee80211_rate *rate;
197 case IEEE80211_BAND_2GHZ:
198 rate_table = sc->hw_rate_table[ATH9K_MODE_11G];
200 case IEEE80211_BAND_5GHZ:
201 rate_table = sc->hw_rate_table[ATH9K_MODE_11A];
207 if (rate_table == NULL)
210 sband = &sc->sbands[band];
211 rate = sc->rates[band];
213 if (rate_table->rate_cnt > ATH_RATE_MAX)
214 maxrates = ATH_RATE_MAX;
216 maxrates = rate_table->rate_cnt;
218 for (i = 0; i < maxrates; i++) {
219 rate[i].bitrate = rate_table->info[i].ratekbps / 100;
220 rate[i].hw_value = rate_table->info[i].ratecode;
221 if (rate_table->info[i].short_preamble) {
222 rate[i].hw_value_short = rate_table->info[i].ratecode |
223 rate_table->info[i].short_preamble;
224 rate[i].flags = IEEE80211_RATE_SHORT_PREAMBLE;
228 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
229 "Rate: %2dMbps, ratecode: %2d\n",
230 rate[i].bitrate / 10, rate[i].hw_value);
234 static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
235 struct ieee80211_hw *hw)
237 struct ieee80211_channel *curchan = hw->conf.channel;
238 struct ath9k_channel *channel;
241 chan_idx = curchan->hw_value;
242 channel = &sc->sc_ah->channels[chan_idx];
243 ath9k_update_ichannel(sc, hw, channel);
247 static bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
252 spin_lock_irqsave(&sc->sc_pm_lock, flags);
253 ret = ath9k_hw_setpower(sc->sc_ah, mode);
254 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
259 void ath9k_ps_wakeup(struct ath_softc *sc)
263 spin_lock_irqsave(&sc->sc_pm_lock, flags);
264 if (++sc->ps_usecount != 1)
267 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
270 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
273 void ath9k_ps_restore(struct ath_softc *sc)
277 spin_lock_irqsave(&sc->sc_pm_lock, flags);
278 if (--sc->ps_usecount != 0)
281 if (sc->ps_enabled &&
282 !(sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
284 SC_OP_WAIT_FOR_PSPOLL_DATA |
285 SC_OP_WAIT_FOR_TX_ACK)))
286 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
289 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
293 * Set/change channels. If the channel is really being changed, it's done
294 * by reseting the chip. To accomplish this we must first cleanup any pending
295 * DMA, then restart stuff.
297 int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
298 struct ath9k_channel *hchan)
300 struct ath_hw *ah = sc->sc_ah;
301 struct ath_common *common = ath9k_hw_common(ah);
302 struct ieee80211_conf *conf = &common->hw->conf;
303 bool fastcc = true, stopped;
304 struct ieee80211_channel *channel = hw->conf.channel;
307 if (sc->sc_flags & SC_OP_INVALID)
313 * This is only performed if the channel settings have
316 * To switch channels clear any pending DMA operations;
317 * wait long enough for the RX fifo to drain, reset the
318 * hardware at the new frequency, and then re-enable
319 * the relevant bits of the h/w.
321 ath9k_hw_set_interrupts(ah, 0);
322 ath_drain_all_txq(sc, false);
323 stopped = ath_stoprecv(sc);
325 /* XXX: do not flush receive queue here. We don't want
326 * to flush data frames already in queue because of
327 * changing channel. */
329 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
332 ath_print(common, ATH_DBG_CONFIG,
333 "(%u MHz) -> (%u MHz), conf_is_ht40: %d\n",
334 sc->sc_ah->curchan->channel,
335 channel->center_freq, conf_is_ht40(conf));
337 spin_lock_bh(&sc->sc_resetlock);
339 r = ath9k_hw_reset(ah, hchan, fastcc);
341 ath_print(common, ATH_DBG_FATAL,
342 "Unable to reset channel (%u Mhz) "
344 channel->center_freq, r);
345 spin_unlock_bh(&sc->sc_resetlock);
348 spin_unlock_bh(&sc->sc_resetlock);
350 sc->sc_flags &= ~SC_OP_FULL_RESET;
352 if (ath_startrecv(sc) != 0) {
353 ath_print(common, ATH_DBG_FATAL,
354 "Unable to restart recv logic\n");
359 ath_cache_conf_rate(sc, &hw->conf);
360 ath_update_txpow(sc);
361 ath9k_hw_set_interrupts(ah, sc->imask);
364 ath9k_ps_restore(sc);
369 * This routine performs the periodic noise floor calibration function
370 * that is used to adjust and optimize the chip performance. This
371 * takes environmental changes (location, temperature) into account.
372 * When the task is complete, it reschedules itself depending on the
373 * appropriate interval that was calculated.
375 static void ath_ani_calibrate(unsigned long data)
377 struct ath_softc *sc = (struct ath_softc *)data;
378 struct ath_hw *ah = sc->sc_ah;
379 struct ath_common *common = ath9k_hw_common(ah);
380 bool longcal = false;
381 bool shortcal = false;
382 bool aniflag = false;
383 unsigned int timestamp = jiffies_to_msecs(jiffies);
384 u32 cal_interval, short_cal_interval;
386 short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
387 ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
390 * don't calibrate when we're scanning.
391 * we are most likely not on our home channel.
393 spin_lock(&sc->ani_lock);
394 if (sc->sc_flags & SC_OP_SCANNING)
397 /* Only calibrate if awake */
398 if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
403 /* Long calibration runs independently of short calibration. */
404 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
406 ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
407 sc->ani.longcal_timer = timestamp;
410 /* Short calibration applies only while caldone is false */
411 if (!sc->ani.caldone) {
412 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
414 ath_print(common, ATH_DBG_ANI,
415 "shortcal @%lu\n", jiffies);
416 sc->ani.shortcal_timer = timestamp;
417 sc->ani.resetcal_timer = timestamp;
420 if ((timestamp - sc->ani.resetcal_timer) >=
421 ATH_RESTART_CALINTERVAL) {
422 sc->ani.caldone = ath9k_hw_reset_calvalid(ah);
424 sc->ani.resetcal_timer = timestamp;
428 /* Verify whether we must check ANI */
429 if ((timestamp - sc->ani.checkani_timer) >= ATH_ANI_POLLINTERVAL) {
431 sc->ani.checkani_timer = timestamp;
434 /* Skip all processing if there's nothing to do. */
435 if (longcal || shortcal || aniflag) {
436 /* Call ANI routine if necessary */
438 ath9k_hw_ani_monitor(ah, ah->curchan);
440 /* Perform calibration if necessary */
441 if (longcal || shortcal) {
443 ath9k_hw_calibrate(ah,
445 common->rx_chainmask,
449 sc->ani.noise_floor = ath9k_hw_getchan_noise(ah,
452 ath_print(common, ATH_DBG_ANI,
453 " calibrate chan %u/%x nf: %d\n",
454 ah->curchan->channel,
455 ah->curchan->channelFlags,
456 sc->ani.noise_floor);
460 ath9k_ps_restore(sc);
463 spin_unlock(&sc->ani_lock);
465 * Set timer interval based on previous results.
466 * The interval must be the shortest necessary to satisfy ANI,
467 * short calibration and long calibration.
469 cal_interval = ATH_LONG_CALINTERVAL;
470 if (sc->sc_ah->config.enable_ani)
471 cal_interval = min(cal_interval, (u32)ATH_ANI_POLLINTERVAL);
472 if (!sc->ani.caldone)
473 cal_interval = min(cal_interval, (u32)short_cal_interval);
475 mod_timer(&sc->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
478 static void ath_start_ani(struct ath_softc *sc)
480 unsigned long timestamp = jiffies_to_msecs(jiffies);
482 sc->ani.longcal_timer = timestamp;
483 sc->ani.shortcal_timer = timestamp;
484 sc->ani.checkani_timer = timestamp;
486 mod_timer(&sc->ani.timer,
487 jiffies + msecs_to_jiffies(ATH_ANI_POLLINTERVAL));
491 * Update tx/rx chainmask. For legacy association,
492 * hard code chainmask to 1x1, for 11n association, use
493 * the chainmask configuration, for bt coexistence, use
494 * the chainmask configuration even in legacy mode.
496 void ath_update_chainmask(struct ath_softc *sc, int is_ht)
498 struct ath_hw *ah = sc->sc_ah;
499 struct ath_common *common = ath9k_hw_common(ah);
501 if ((sc->sc_flags & SC_OP_SCANNING) || is_ht ||
502 (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) {
503 common->tx_chainmask = ah->caps.tx_chainmask;
504 common->rx_chainmask = ah->caps.rx_chainmask;
506 common->tx_chainmask = 1;
507 common->rx_chainmask = 1;
510 ath_print(common, ATH_DBG_CONFIG,
511 "tx chmask: %d, rx chmask: %d\n",
512 common->tx_chainmask,
513 common->rx_chainmask);
516 static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
520 an = (struct ath_node *)sta->drv_priv;
522 if (sc->sc_flags & SC_OP_TXAGGR) {
523 ath_tx_node_init(sc, an);
524 an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
525 sta->ht_cap.ampdu_factor);
526 an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
527 an->last_rssi = ATH_RSSI_DUMMY_MARKER;
531 static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
533 struct ath_node *an = (struct ath_node *)sta->drv_priv;
535 if (sc->sc_flags & SC_OP_TXAGGR)
536 ath_tx_node_cleanup(sc, an);
539 static void ath9k_tasklet(unsigned long data)
541 struct ath_softc *sc = (struct ath_softc *)data;
542 struct ath_hw *ah = sc->sc_ah;
543 struct ath_common *common = ath9k_hw_common(ah);
545 u32 status = sc->intrstatus;
549 if (status & ATH9K_INT_FATAL) {
550 ath_reset(sc, false);
551 ath9k_ps_restore(sc);
555 if (status & (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN)) {
556 spin_lock_bh(&sc->rx.rxflushlock);
557 ath_rx_tasklet(sc, 0);
558 spin_unlock_bh(&sc->rx.rxflushlock);
561 if (status & ATH9K_INT_TX)
564 if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
566 * TSF sync does not look correct; remain awake to sync with
569 ath_print(common, ATH_DBG_PS,
570 "TSFOOR - Sync with next Beacon\n");
571 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC;
574 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
575 if (status & ATH9K_INT_GENTIMER)
576 ath_gen_timer_isr(sc->sc_ah);
578 /* re-enable hardware interrupt */
579 ath9k_hw_set_interrupts(ah, sc->imask);
580 ath9k_ps_restore(sc);
583 irqreturn_t ath_isr(int irq, void *dev)
585 #define SCHED_INTR ( \
596 struct ath_softc *sc = dev;
597 struct ath_hw *ah = sc->sc_ah;
598 enum ath9k_int status;
602 * The hardware is not ready/present, don't
603 * touch anything. Note this can happen early
604 * on if the IRQ is shared.
606 if (sc->sc_flags & SC_OP_INVALID)
610 /* shared irq, not for us */
612 if (!ath9k_hw_intrpend(ah))
616 * Figure out the reason(s) for the interrupt. Note
617 * that the hal returns a pseudo-ISR that may include
618 * bits we haven't explicitly enabled so we mask the
619 * value to insure we only process bits we requested.
621 ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
622 status &= sc->imask; /* discard unasked-for bits */
625 * If there are no status bits set, then this interrupt was not
626 * for me (should have been caught above).
631 /* Cache the status */
632 sc->intrstatus = status;
634 if (status & SCHED_INTR)
638 * If a FATAL or RXORN interrupt is received, we have to reset the
641 if (status & (ATH9K_INT_FATAL | ATH9K_INT_RXORN))
644 if (status & ATH9K_INT_SWBA)
645 tasklet_schedule(&sc->bcon_tasklet);
647 if (status & ATH9K_INT_TXURN)
648 ath9k_hw_updatetxtriglevel(ah, true);
650 if (status & ATH9K_INT_MIB) {
652 * Disable interrupts until we service the MIB
653 * interrupt; otherwise it will continue to
656 ath9k_hw_set_interrupts(ah, 0);
658 * Let the hal handle the event. We assume
659 * it will clear whatever condition caused
662 ath9k_hw_procmibevent(ah);
663 ath9k_hw_set_interrupts(ah, sc->imask);
666 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
667 if (status & ATH9K_INT_TIM_TIMER) {
668 /* Clear RxAbort bit so that we can
670 ath9k_setpower(sc, ATH9K_PM_AWAKE);
671 ath9k_hw_setrxabort(sc->sc_ah, 0);
672 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON;
677 ath_debug_stat_interrupt(sc, status);
680 /* turn off every interrupt except SWBA */
681 ath9k_hw_set_interrupts(ah, (sc->imask & ATH9K_INT_SWBA));
682 tasklet_schedule(&sc->intr_tq);
690 static u32 ath_get_extchanmode(struct ath_softc *sc,
691 struct ieee80211_channel *chan,
692 enum nl80211_channel_type channel_type)
696 switch (chan->band) {
697 case IEEE80211_BAND_2GHZ:
698 switch(channel_type) {
699 case NL80211_CHAN_NO_HT:
700 case NL80211_CHAN_HT20:
701 chanmode = CHANNEL_G_HT20;
703 case NL80211_CHAN_HT40PLUS:
704 chanmode = CHANNEL_G_HT40PLUS;
706 case NL80211_CHAN_HT40MINUS:
707 chanmode = CHANNEL_G_HT40MINUS;
711 case IEEE80211_BAND_5GHZ:
712 switch(channel_type) {
713 case NL80211_CHAN_NO_HT:
714 case NL80211_CHAN_HT20:
715 chanmode = CHANNEL_A_HT20;
717 case NL80211_CHAN_HT40PLUS:
718 chanmode = CHANNEL_A_HT40PLUS;
720 case NL80211_CHAN_HT40MINUS:
721 chanmode = CHANNEL_A_HT40MINUS;
732 static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
733 struct ath9k_keyval *hk, const u8 *addr,
739 key_txmic = key + NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY;
740 key_rxmic = key + NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY;
744 * Group key installation - only two key cache entries are used
745 * regardless of splitmic capability since group key is only
746 * used either for TX or RX.
749 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
750 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_mic));
752 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
753 memcpy(hk->kv_txmic, key_rxmic, sizeof(hk->kv_mic));
755 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
758 /* TX and RX keys share the same key cache entry. */
759 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
760 memcpy(hk->kv_txmic, key_txmic, sizeof(hk->kv_txmic));
761 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, addr);
764 /* Separate key cache entries for TX and RX */
766 /* TX key goes at first index, RX key at +32. */
767 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
768 if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
769 /* TX MIC entry failed. No need to proceed further */
770 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
771 "Setting TX MIC Key Failed\n");
775 memcpy(hk->kv_mic, key_rxmic, sizeof(hk->kv_mic));
776 /* XXX delete tx key on failure? */
777 return ath9k_hw_set_keycache_entry(sc->sc_ah, keyix + 32, hk, addr);
780 static int ath_reserve_key_cache_slot_tkip(struct ath_softc *sc)
784 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
785 if (test_bit(i, sc->keymap) ||
786 test_bit(i + 64, sc->keymap))
787 continue; /* At least one part of TKIP key allocated */
789 (test_bit(i + 32, sc->keymap) ||
790 test_bit(i + 64 + 32, sc->keymap)))
791 continue; /* At least one part of TKIP key allocated */
793 /* Found a free slot for a TKIP key */
799 static int ath_reserve_key_cache_slot(struct ath_softc *sc)
803 /* First, try to find slots that would not be available for TKIP. */
805 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 4; i++) {
806 if (!test_bit(i, sc->keymap) &&
807 (test_bit(i + 32, sc->keymap) ||
808 test_bit(i + 64, sc->keymap) ||
809 test_bit(i + 64 + 32, sc->keymap)))
811 if (!test_bit(i + 32, sc->keymap) &&
812 (test_bit(i, sc->keymap) ||
813 test_bit(i + 64, sc->keymap) ||
814 test_bit(i + 64 + 32, sc->keymap)))
816 if (!test_bit(i + 64, sc->keymap) &&
817 (test_bit(i , sc->keymap) ||
818 test_bit(i + 32, sc->keymap) ||
819 test_bit(i + 64 + 32, sc->keymap)))
821 if (!test_bit(i + 64 + 32, sc->keymap) &&
822 (test_bit(i, sc->keymap) ||
823 test_bit(i + 32, sc->keymap) ||
824 test_bit(i + 64, sc->keymap)))
828 for (i = IEEE80211_WEP_NKID; i < sc->keymax / 2; i++) {
829 if (!test_bit(i, sc->keymap) &&
830 test_bit(i + 64, sc->keymap))
832 if (test_bit(i, sc->keymap) &&
833 !test_bit(i + 64, sc->keymap))
838 /* No partially used TKIP slots, pick any available slot */
839 for (i = IEEE80211_WEP_NKID; i < sc->keymax; i++) {
840 /* Do not allow slots that could be needed for TKIP group keys
841 * to be used. This limitation could be removed if we know that
842 * TKIP will not be used. */
843 if (i >= 64 && i < 64 + IEEE80211_WEP_NKID)
846 if (i >= 32 && i < 32 + IEEE80211_WEP_NKID)
848 if (i >= 64 + 32 && i < 64 + 32 + IEEE80211_WEP_NKID)
852 if (!test_bit(i, sc->keymap))
853 return i; /* Found a free slot for a key */
856 /* No free slot found */
860 static int ath_key_config(struct ath_softc *sc,
861 struct ieee80211_vif *vif,
862 struct ieee80211_sta *sta,
863 struct ieee80211_key_conf *key)
865 struct ath9k_keyval hk;
866 const u8 *mac = NULL;
870 memset(&hk, 0, sizeof(hk));
874 hk.kv_type = ATH9K_CIPHER_WEP;
877 hk.kv_type = ATH9K_CIPHER_TKIP;
880 hk.kv_type = ATH9K_CIPHER_AES_CCM;
886 hk.kv_len = key->keylen;
887 memcpy(hk.kv_val, key->key, key->keylen);
889 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) {
890 /* For now, use the default keys for broadcast keys. This may
891 * need to change with virtual interfaces. */
893 } else if (key->keyidx) {
898 if (vif->type != NL80211_IFTYPE_AP) {
899 /* Only keyidx 0 should be used with unicast key, but
900 * allow this for client mode for now. */
909 if (key->alg == ALG_TKIP)
910 idx = ath_reserve_key_cache_slot_tkip(sc);
912 idx = ath_reserve_key_cache_slot(sc);
914 return -ENOSPC; /* no free key cache entries */
917 if (key->alg == ALG_TKIP)
918 ret = ath_setkey_tkip(sc, idx, key->key, &hk, mac,
919 vif->type == NL80211_IFTYPE_AP);
921 ret = ath9k_hw_set_keycache_entry(sc->sc_ah, idx, &hk, mac);
926 set_bit(idx, sc->keymap);
927 if (key->alg == ALG_TKIP) {
928 set_bit(idx + 64, sc->keymap);
930 set_bit(idx + 32, sc->keymap);
931 set_bit(idx + 64 + 32, sc->keymap);
938 static void ath_key_delete(struct ath_softc *sc, struct ieee80211_key_conf *key)
940 ath9k_hw_keyreset(sc->sc_ah, key->hw_key_idx);
941 if (key->hw_key_idx < IEEE80211_WEP_NKID)
944 clear_bit(key->hw_key_idx, sc->keymap);
945 if (key->alg != ALG_TKIP)
948 clear_bit(key->hw_key_idx + 64, sc->keymap);
950 clear_bit(key->hw_key_idx + 32, sc->keymap);
951 clear_bit(key->hw_key_idx + 64 + 32, sc->keymap);
955 static void setup_ht_cap(struct ath_softc *sc,
956 struct ieee80211_sta_ht_cap *ht_info)
958 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
959 u8 tx_streams, rx_streams;
961 ht_info->ht_supported = true;
962 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
963 IEEE80211_HT_CAP_SM_PS |
964 IEEE80211_HT_CAP_SGI_40 |
965 IEEE80211_HT_CAP_DSSSCCK40;
967 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
968 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8;
970 /* set up supported mcs set */
971 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs));
972 tx_streams = !(common->tx_chainmask & (common->tx_chainmask - 1)) ?
974 rx_streams = !(common->rx_chainmask & (common->rx_chainmask - 1)) ?
977 if (tx_streams != rx_streams) {
978 ath_print(common, ATH_DBG_CONFIG,
979 "TX streams %d, RX streams: %d\n",
980 tx_streams, rx_streams);
981 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
982 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
983 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
986 ht_info->mcs.rx_mask[0] = 0xff;
988 ht_info->mcs.rx_mask[1] = 0xff;
990 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED;
993 static void ath9k_bss_assoc_info(struct ath_softc *sc,
994 struct ieee80211_vif *vif,
995 struct ieee80211_bss_conf *bss_conf)
997 struct ath_hw *ah = sc->sc_ah;
998 struct ath_common *common = ath9k_hw_common(ah);
1000 if (bss_conf->assoc) {
1001 ath_print(common, ATH_DBG_CONFIG,
1002 "Bss Info ASSOC %d, bssid: %pM\n",
1003 bss_conf->aid, common->curbssid);
1005 /* New association, store aid */
1006 common->curaid = bss_conf->aid;
1007 ath9k_hw_write_associd(ah);
1010 * Request a re-configuration of Beacon related timers
1011 * on the receipt of the first Beacon frame (i.e.,
1012 * after time sync with the AP).
1014 sc->sc_flags |= SC_OP_BEACON_SYNC;
1016 /* Configure the beacon */
1017 ath_beacon_config(sc, vif);
1019 /* Reset rssi stats */
1020 sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
1024 ath_print(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
1027 del_timer_sync(&sc->ani.timer);
1031 /********************************/
1033 /********************************/
1035 static void ath_led_blink_work(struct work_struct *work)
1037 struct ath_softc *sc = container_of(work, struct ath_softc,
1038 ath_led_blink_work.work);
1040 if (!(sc->sc_flags & SC_OP_LED_ASSOCIATED))
1043 if ((sc->led_on_duration == ATH_LED_ON_DURATION_IDLE) ||
1044 (sc->led_off_duration == ATH_LED_OFF_DURATION_IDLE))
1045 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
1047 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
1048 (sc->sc_flags & SC_OP_LED_ON) ? 1 : 0);
1050 ieee80211_queue_delayed_work(sc->hw,
1051 &sc->ath_led_blink_work,
1052 (sc->sc_flags & SC_OP_LED_ON) ?
1053 msecs_to_jiffies(sc->led_off_duration) :
1054 msecs_to_jiffies(sc->led_on_duration));
1056 sc->led_on_duration = sc->led_on_cnt ?
1057 max((ATH_LED_ON_DURATION_IDLE - sc->led_on_cnt), 25) :
1058 ATH_LED_ON_DURATION_IDLE;
1059 sc->led_off_duration = sc->led_off_cnt ?
1060 max((ATH_LED_OFF_DURATION_IDLE - sc->led_off_cnt), 10) :
1061 ATH_LED_OFF_DURATION_IDLE;
1062 sc->led_on_cnt = sc->led_off_cnt = 0;
1063 if (sc->sc_flags & SC_OP_LED_ON)
1064 sc->sc_flags &= ~SC_OP_LED_ON;
1066 sc->sc_flags |= SC_OP_LED_ON;
1069 static void ath_led_brightness(struct led_classdev *led_cdev,
1070 enum led_brightness brightness)
1072 struct ath_led *led = container_of(led_cdev, struct ath_led, led_cdev);
1073 struct ath_softc *sc = led->sc;
1075 switch (brightness) {
1077 if (led->led_type == ATH_LED_ASSOC ||
1078 led->led_type == ATH_LED_RADIO) {
1079 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin,
1080 (led->led_type == ATH_LED_RADIO));
1081 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1082 if (led->led_type == ATH_LED_RADIO)
1083 sc->sc_flags &= ~SC_OP_LED_ON;
1089 if (led->led_type == ATH_LED_ASSOC) {
1090 sc->sc_flags |= SC_OP_LED_ASSOCIATED;
1091 ieee80211_queue_delayed_work(sc->hw,
1092 &sc->ath_led_blink_work, 0);
1093 } else if (led->led_type == ATH_LED_RADIO) {
1094 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 0);
1095 sc->sc_flags |= SC_OP_LED_ON;
1105 static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1111 led->led_cdev.name = led->name;
1112 led->led_cdev.default_trigger = trigger;
1113 led->led_cdev.brightness_set = ath_led_brightness;
1115 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1117 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1118 "Failed to register led:%s", led->name);
1120 led->registered = 1;
1124 static void ath_unregister_led(struct ath_led *led)
1126 if (led->registered) {
1127 led_classdev_unregister(&led->led_cdev);
1128 led->registered = 0;
1132 static void ath_deinit_leds(struct ath_softc *sc)
1134 ath_unregister_led(&sc->assoc_led);
1135 sc->sc_flags &= ~SC_OP_LED_ASSOCIATED;
1136 ath_unregister_led(&sc->tx_led);
1137 ath_unregister_led(&sc->rx_led);
1138 ath_unregister_led(&sc->radio_led);
1139 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
1142 static void ath_init_leds(struct ath_softc *sc)
1147 if (AR_SREV_9287(sc->sc_ah))
1148 sc->sc_ah->led_pin = ATH_LED_PIN_9287;
1150 sc->sc_ah->led_pin = ATH_LED_PIN_DEF;
1152 /* Configure gpio 1 for output */
1153 ath9k_hw_cfg_output(sc->sc_ah, sc->sc_ah->led_pin,
1154 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1155 /* LED off, active low */
1156 ath9k_hw_set_gpio(sc->sc_ah, sc->sc_ah->led_pin, 1);
1158 INIT_DELAYED_WORK(&sc->ath_led_blink_work, ath_led_blink_work);
1160 trigger = ieee80211_get_radio_led_name(sc->hw);
1161 snprintf(sc->radio_led.name, sizeof(sc->radio_led.name),
1162 "ath9k-%s::radio", wiphy_name(sc->hw->wiphy));
1163 ret = ath_register_led(sc, &sc->radio_led, trigger);
1164 sc->radio_led.led_type = ATH_LED_RADIO;
1168 trigger = ieee80211_get_assoc_led_name(sc->hw);
1169 snprintf(sc->assoc_led.name, sizeof(sc->assoc_led.name),
1170 "ath9k-%s::assoc", wiphy_name(sc->hw->wiphy));
1171 ret = ath_register_led(sc, &sc->assoc_led, trigger);
1172 sc->assoc_led.led_type = ATH_LED_ASSOC;
1176 trigger = ieee80211_get_tx_led_name(sc->hw);
1177 snprintf(sc->tx_led.name, sizeof(sc->tx_led.name),
1178 "ath9k-%s::tx", wiphy_name(sc->hw->wiphy));
1179 ret = ath_register_led(sc, &sc->tx_led, trigger);
1180 sc->tx_led.led_type = ATH_LED_TX;
1184 trigger = ieee80211_get_rx_led_name(sc->hw);
1185 snprintf(sc->rx_led.name, sizeof(sc->rx_led.name),
1186 "ath9k-%s::rx", wiphy_name(sc->hw->wiphy));
1187 ret = ath_register_led(sc, &sc->rx_led, trigger);
1188 sc->rx_led.led_type = ATH_LED_RX;
1195 cancel_delayed_work_sync(&sc->ath_led_blink_work);
1196 ath_deinit_leds(sc);
1199 void ath_radio_enable(struct ath_softc *sc)
1201 struct ath_hw *ah = sc->sc_ah;
1202 struct ath_common *common = ath9k_hw_common(ah);
1203 struct ieee80211_channel *channel = sc->hw->conf.channel;
1206 ath9k_ps_wakeup(sc);
1207 ath9k_hw_configpcipowersave(ah, 0, 0);
1210 ah->curchan = ath_get_curchannel(sc, sc->hw);
1212 spin_lock_bh(&sc->sc_resetlock);
1213 r = ath9k_hw_reset(ah, ah->curchan, false);
1215 ath_print(common, ATH_DBG_FATAL,
1216 "Unable to reset channel %u (%uMhz) ",
1217 "reset status %d\n",
1218 channel->center_freq, r);
1220 spin_unlock_bh(&sc->sc_resetlock);
1222 ath_update_txpow(sc);
1223 if (ath_startrecv(sc) != 0) {
1224 ath_print(common, ATH_DBG_FATAL,
1225 "Unable to restart recv logic\n");
1229 if (sc->sc_flags & SC_OP_BEACONS)
1230 ath_beacon_config(sc, NULL); /* restart beacons */
1232 /* Re-Enable interrupts */
1233 ath9k_hw_set_interrupts(ah, sc->imask);
1236 ath9k_hw_cfg_output(ah, ah->led_pin,
1237 AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1238 ath9k_hw_set_gpio(ah, ah->led_pin, 0);
1240 ieee80211_wake_queues(sc->hw);
1241 ath9k_ps_restore(sc);
1244 void ath_radio_disable(struct ath_softc *sc)
1246 struct ath_hw *ah = sc->sc_ah;
1247 struct ieee80211_channel *channel = sc->hw->conf.channel;
1250 ath9k_ps_wakeup(sc);
1251 ieee80211_stop_queues(sc->hw);
1254 ath9k_hw_set_gpio(ah, ah->led_pin, 1);
1255 ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
1257 /* Disable interrupts */
1258 ath9k_hw_set_interrupts(ah, 0);
1260 ath_drain_all_txq(sc, false); /* clear pending tx frames */
1261 ath_stoprecv(sc); /* turn off frame recv */
1262 ath_flushrecv(sc); /* flush recv queue */
1265 ah->curchan = ath_get_curchannel(sc, sc->hw);
1267 spin_lock_bh(&sc->sc_resetlock);
1268 r = ath9k_hw_reset(ah, ah->curchan, false);
1270 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
1271 "Unable to reset channel %u (%uMhz) "
1272 "reset status %d\n",
1273 channel->center_freq, r);
1275 spin_unlock_bh(&sc->sc_resetlock);
1277 ath9k_hw_phy_disable(ah);
1278 ath9k_hw_configpcipowersave(ah, 1, 1);
1279 ath9k_ps_restore(sc);
1280 ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
1283 /*******************/
1285 /*******************/
1287 static bool ath_is_rfkill_set(struct ath_softc *sc)
1289 struct ath_hw *ah = sc->sc_ah;
1291 return ath9k_hw_gpio_get(ah, ah->rfkill_gpio) ==
1292 ah->rfkill_polarity;
1295 static void ath9k_rfkill_poll_state(struct ieee80211_hw *hw)
1297 struct ath_wiphy *aphy = hw->priv;
1298 struct ath_softc *sc = aphy->sc;
1299 bool blocked = !!ath_is_rfkill_set(sc);
1301 wiphy_rfkill_set_hw_state(hw->wiphy, blocked);
1304 static void ath_start_rfkill_poll(struct ath_softc *sc)
1306 struct ath_hw *ah = sc->sc_ah;
1308 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1309 wiphy_rfkill_start_polling(sc->hw->wiphy);
1312 void ath_cleanup(struct ath_softc *sc)
1314 struct ath_hw *ah = sc->sc_ah;
1315 struct ath_common *common = ath9k_hw_common(ah);
1318 free_irq(sc->irq, sc);
1319 ath_bus_cleanup(common);
1320 kfree(sc->sec_wiphy);
1321 ieee80211_free_hw(sc->hw);
1324 void ath_detach(struct ath_softc *sc)
1326 struct ieee80211_hw *hw = sc->hw;
1327 struct ath_hw *ah = sc->sc_ah;
1330 ath9k_ps_wakeup(sc);
1332 dev_dbg(sc->dev, "Detach ATH hw\n");
1334 ath_deinit_leds(sc);
1335 wiphy_rfkill_stop_polling(sc->hw->wiphy);
1337 for (i = 0; i < sc->num_sec_wiphy; i++) {
1338 struct ath_wiphy *aphy = sc->sec_wiphy[i];
1341 sc->sec_wiphy[i] = NULL;
1342 ieee80211_unregister_hw(aphy->hw);
1343 ieee80211_free_hw(aphy->hw);
1345 ieee80211_unregister_hw(hw);
1349 tasklet_kill(&sc->intr_tq);
1350 tasklet_kill(&sc->bcon_tasklet);
1352 if (!(sc->sc_flags & SC_OP_INVALID))
1353 ath9k_setpower(sc, ATH9K_PM_AWAKE);
1355 /* cleanup tx queues */
1356 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1357 if (ATH_TXQ_SETUP(sc, i))
1358 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1360 if ((sc->btcoex.no_stomp_timer) &&
1361 ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
1362 ath_gen_timer_free(ah, sc->btcoex.no_stomp_timer);
1364 ath9k_hw_detach(ah);
1365 ath9k_exit_debug(ah);
1369 static int ath9k_reg_notifier(struct wiphy *wiphy,
1370 struct regulatory_request *request)
1372 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
1373 struct ath_wiphy *aphy = hw->priv;
1374 struct ath_softc *sc = aphy->sc;
1375 struct ath_regulatory *reg = ath9k_hw_regulatory(sc->sc_ah);
1377 return ath_reg_notifier_apply(wiphy, request, reg);
1381 * Detects if there is any priority bt traffic
1383 static void ath_detect_bt_priority(struct ath_softc *sc)
1385 struct ath_btcoex *btcoex = &sc->btcoex;
1386 struct ath_hw *ah = sc->sc_ah;
1388 if (ath9k_hw_gpio_get(sc->sc_ah, ah->btcoex_hw.btpriority_gpio))
1389 btcoex->bt_priority_cnt++;
1391 if (time_after(jiffies, btcoex->bt_priority_time +
1392 msecs_to_jiffies(ATH_BT_PRIORITY_TIME_THRESHOLD))) {
1393 if (btcoex->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) {
1394 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_BTCOEX,
1395 "BT priority traffic detected");
1396 sc->sc_flags |= SC_OP_BT_PRIORITY_DETECTED;
1398 sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
1401 btcoex->bt_priority_cnt = 0;
1402 btcoex->bt_priority_time = jiffies;
1407 * Configures appropriate weight based on stomp type.
1409 static void ath9k_btcoex_bt_stomp(struct ath_softc *sc,
1410 enum ath_stomp_type stomp_type)
1412 struct ath_hw *ah = sc->sc_ah;
1414 switch (stomp_type) {
1415 case ATH_BTCOEX_STOMP_ALL:
1416 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1417 AR_STOMP_ALL_WLAN_WGHT);
1419 case ATH_BTCOEX_STOMP_LOW:
1420 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1421 AR_STOMP_LOW_WLAN_WGHT);
1423 case ATH_BTCOEX_STOMP_NONE:
1424 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
1425 AR_STOMP_NONE_WLAN_WGHT);
1428 ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
1429 "Invalid Stomptype\n");
1433 ath9k_hw_btcoex_enable(ah);
1436 static void ath9k_gen_timer_start(struct ath_hw *ah,
1437 struct ath_gen_timer *timer,
1441 struct ath_common *common = ath9k_hw_common(ah);
1442 struct ath_softc *sc = (struct ath_softc *) common->priv;
1444 ath9k_hw_gen_timer_start(ah, timer, timer_next, timer_period);
1446 if ((sc->imask & ATH9K_INT_GENTIMER) == 0) {
1447 ath9k_hw_set_interrupts(ah, 0);
1448 sc->imask |= ATH9K_INT_GENTIMER;
1449 ath9k_hw_set_interrupts(ah, sc->imask);
1453 static void ath9k_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
1455 struct ath_common *common = ath9k_hw_common(ah);
1456 struct ath_softc *sc = (struct ath_softc *) common->priv;
1457 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
1459 ath9k_hw_gen_timer_stop(ah, timer);
1461 /* if no timer is enabled, turn off interrupt mask */
1462 if (timer_table->timer_mask.val == 0) {
1463 ath9k_hw_set_interrupts(ah, 0);
1464 sc->imask &= ~ATH9K_INT_GENTIMER;
1465 ath9k_hw_set_interrupts(ah, sc->imask);
1470 * This is the master bt coex timer which runs for every
1471 * 45ms, bt traffic will be given priority during 55% of this
1472 * period while wlan gets remaining 45%
1474 static void ath_btcoex_period_timer(unsigned long data)
1476 struct ath_softc *sc = (struct ath_softc *) data;
1477 struct ath_hw *ah = sc->sc_ah;
1478 struct ath_btcoex *btcoex = &sc->btcoex;
1480 ath_detect_bt_priority(sc);
1482 spin_lock_bh(&btcoex->btcoex_lock);
1484 ath9k_btcoex_bt_stomp(sc, btcoex->bt_stomp_type);
1486 spin_unlock_bh(&btcoex->btcoex_lock);
1488 if (btcoex->btcoex_period != btcoex->btcoex_no_stomp) {
1489 if (btcoex->hw_timer_enabled)
1490 ath9k_gen_timer_stop(ah, btcoex->no_stomp_timer);
1492 ath9k_gen_timer_start(ah,
1493 btcoex->no_stomp_timer,
1494 (ath9k_hw_gettsf32(ah) +
1495 btcoex->btcoex_no_stomp),
1496 btcoex->btcoex_no_stomp * 10);
1497 btcoex->hw_timer_enabled = true;
1500 mod_timer(&btcoex->period_timer, jiffies +
1501 msecs_to_jiffies(ATH_BTCOEX_DEF_BT_PERIOD));
1505 * Generic tsf based hw timer which configures weight
1506 * registers to time slice between wlan and bt traffic
1508 static void ath_btcoex_no_stomp_timer(void *arg)
1510 struct ath_softc *sc = (struct ath_softc *)arg;
1511 struct ath_hw *ah = sc->sc_ah;
1512 struct ath_btcoex *btcoex = &sc->btcoex;
1514 ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
1515 "no stomp timer running \n");
1517 spin_lock_bh(&btcoex->btcoex_lock);
1519 if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_LOW)
1520 ath9k_btcoex_bt_stomp(sc, ATH_BTCOEX_STOMP_NONE);
1521 else if (btcoex->bt_stomp_type == ATH_BTCOEX_STOMP_ALL)
1522 ath9k_btcoex_bt_stomp(sc, ATH_BTCOEX_STOMP_LOW);
1524 spin_unlock_bh(&btcoex->btcoex_lock);
1527 static int ath_init_btcoex_timer(struct ath_softc *sc)
1529 struct ath_btcoex *btcoex = &sc->btcoex;
1531 btcoex->btcoex_period = ATH_BTCOEX_DEF_BT_PERIOD * 1000;
1532 btcoex->btcoex_no_stomp = (100 - ATH_BTCOEX_DEF_DUTY_CYCLE) *
1533 btcoex->btcoex_period / 100;
1535 setup_timer(&btcoex->period_timer, ath_btcoex_period_timer,
1536 (unsigned long) sc);
1538 spin_lock_init(&btcoex->btcoex_lock);
1540 btcoex->no_stomp_timer = ath_gen_timer_alloc(sc->sc_ah,
1541 ath_btcoex_no_stomp_timer,
1542 ath_btcoex_no_stomp_timer,
1543 (void *) sc, AR_FIRST_NDP_TIMER);
1545 if (!btcoex->no_stomp_timer)
1552 * Read and write, they both share the same lock. We do this to serialize
1553 * reads and writes on Atheros 802.11n PCI devices only. This is required
1554 * as the FIFO on these devices can only accept sanely 2 requests. After
1555 * that the device goes bananas. Serializing the reads/writes prevents this
1559 static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
1561 struct ath_hw *ah = (struct ath_hw *) hw_priv;
1562 struct ath_common *common = ath9k_hw_common(ah);
1563 struct ath_softc *sc = (struct ath_softc *) common->priv;
1565 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
1566 unsigned long flags;
1567 spin_lock_irqsave(&sc->sc_serial_rw, flags);
1568 iowrite32(val, sc->mem + reg_offset);
1569 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
1571 iowrite32(val, sc->mem + reg_offset);
1574 static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
1576 struct ath_hw *ah = (struct ath_hw *) hw_priv;
1577 struct ath_common *common = ath9k_hw_common(ah);
1578 struct ath_softc *sc = (struct ath_softc *) common->priv;
1581 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
1582 unsigned long flags;
1583 spin_lock_irqsave(&sc->sc_serial_rw, flags);
1584 val = ioread32(sc->mem + reg_offset);
1585 spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
1587 val = ioread32(sc->mem + reg_offset);
1591 static const struct ath_ops ath9k_common_ops = {
1592 .read = ath9k_ioread32,
1593 .write = ath9k_iowrite32,
1597 * Initialize and fill ath_softc, ath_sofct is the
1598 * "Software Carrier" struct. Historically it has existed
1599 * to allow the separation between hardware specific
1600 * variables (now in ath_hw) and driver specific variables.
1602 static int ath_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid,
1603 const struct ath_bus_ops *bus_ops)
1605 struct ath_hw *ah = NULL;
1606 struct ath_common *common;
1611 /* XXX: hardware will not be ready until ath_open() being called */
1612 sc->sc_flags |= SC_OP_INVALID;
1614 spin_lock_init(&sc->wiphy_lock);
1615 spin_lock_init(&sc->sc_resetlock);
1616 spin_lock_init(&sc->sc_serial_rw);
1617 spin_lock_init(&sc->ani_lock);
1618 spin_lock_init(&sc->sc_pm_lock);
1619 mutex_init(&sc->mutex);
1620 tasklet_init(&sc->intr_tq, ath9k_tasklet, (unsigned long)sc);
1621 tasklet_init(&sc->bcon_tasklet, ath_beacon_tasklet,
1624 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
1630 ah->hw_version.devid = devid;
1631 ah->hw_version.subsysid = subsysid;
1634 common = ath9k_hw_common(ah);
1635 common->ops = &ath9k_common_ops;
1636 common->bus_ops = bus_ops;
1638 common->hw = sc->hw;
1642 * Cache line size is used to size and align various
1643 * structures used to communicate with the hardware.
1645 ath_read_cachesize(common, &csz);
1646 /* XXX assert csz is non-zero */
1647 common->cachelsz = csz << 2; /* convert to bytes */
1649 if (ath9k_init_debug(ah) < 0)
1650 dev_err(sc->dev, "Unable to create debugfs files\n");
1652 r = ath9k_hw_init(ah);
1654 ath_print(common, ATH_DBG_FATAL,
1655 "Unable to initialize hardware; "
1656 "initialization status: %d\n", r);
1660 /* Get the hardware key cache size. */
1661 sc->keymax = ah->caps.keycache_size;
1662 if (sc->keymax > ATH_KEYMAX) {
1663 ath_print(common, ATH_DBG_ANY,
1664 "Warning, using only %u entries in %u key cache\n",
1665 ATH_KEYMAX, sc->keymax);
1666 sc->keymax = ATH_KEYMAX;
1670 * Reset the key cache since some parts do not
1671 * reset the contents on initial power up.
1673 for (i = 0; i < sc->keymax; i++)
1674 ath9k_hw_keyreset(ah, (u16) i);
1676 /* default to MONITOR mode */
1677 sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
1679 /* Setup rate tables */
1681 ath_rate_attach(sc);
1682 ath_setup_rates(sc, IEEE80211_BAND_2GHZ);
1683 ath_setup_rates(sc, IEEE80211_BAND_5GHZ);
1686 * Allocate hardware transmit queues: one queue for
1687 * beacon frames and one data queue for each QoS
1688 * priority. Note that the hal handles reseting
1689 * these queues at the needed time.
1691 sc->beacon.beaconq = ath_beaconq_setup(ah);
1692 if (sc->beacon.beaconq == -1) {
1693 ath_print(common, ATH_DBG_FATAL,
1694 "Unable to setup a beacon xmit queue\n");
1698 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1699 if (sc->beacon.cabq == NULL) {
1700 ath_print(common, ATH_DBG_FATAL,
1701 "Unable to setup CAB xmit queue\n");
1706 sc->config.cabqReadytime = ATH_CABQ_READY_TIME;
1707 ath_cabq_update(sc);
1709 for (i = 0; i < ARRAY_SIZE(sc->tx.hwq_map); i++)
1710 sc->tx.hwq_map[i] = -1;
1712 /* Setup data queues */
1713 /* NB: ensure BK queue is the lowest priority h/w queue */
1714 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1715 ath_print(common, ATH_DBG_FATAL,
1716 "Unable to setup xmit queue for BK traffic\n");
1721 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1722 ath_print(common, ATH_DBG_FATAL,
1723 "Unable to setup xmit queue for BE traffic\n");
1727 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1728 ath_print(common, ATH_DBG_FATAL,
1729 "Unable to setup xmit queue for VI traffic\n");
1733 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1734 ath_print(common, ATH_DBG_FATAL,
1735 "Unable to setup xmit queue for VO traffic\n");
1740 /* Initializes the noise floor to a reasonable default value.
1741 * Later on this will be updated during ANI processing. */
1743 sc->ani.noise_floor = ATH_DEFAULT_NOISE_FLOOR;
1744 setup_timer(&sc->ani.timer, ath_ani_calibrate, (unsigned long)sc);
1746 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1747 ATH9K_CIPHER_TKIP, NULL)) {
1749 * Whether we should enable h/w TKIP MIC.
1750 * XXX: if we don't support WME TKIP MIC, then we wouldn't
1751 * report WMM capable, so it's always safe to turn on
1752 * TKIP MIC in this case.
1754 ath9k_hw_setcapability(sc->sc_ah, ATH9K_CAP_TKIP_MIC,
1759 * Check whether the separate key cache entries
1760 * are required to handle both tx+rx MIC keys.
1761 * With split mic keys the number of stations is limited
1762 * to 27 otherwise 59.
1764 if (ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1765 ATH9K_CIPHER_TKIP, NULL)
1766 && ath9k_hw_getcapability(ah, ATH9K_CAP_CIPHER,
1767 ATH9K_CIPHER_MIC, NULL)
1768 && ath9k_hw_getcapability(ah, ATH9K_CAP_TKIP_SPLIT,
1772 /* turn on mcast key search if possible */
1773 if (!ath9k_hw_getcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 0, NULL))
1774 (void)ath9k_hw_setcapability(ah, ATH9K_CAP_MCAST_KEYSRCH, 1,
1777 sc->config.txpowlimit = ATH_TXPOWER_MAX;
1779 /* 11n Capabilities */
1780 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1781 sc->sc_flags |= SC_OP_TXAGGR;
1782 sc->sc_flags |= SC_OP_RXAGGR;
1785 common->tx_chainmask = ah->caps.tx_chainmask;
1786 common->rx_chainmask = ah->caps.rx_chainmask;
1788 ath9k_hw_setcapability(ah, ATH9K_CAP_DIVERSITY, 1, true, NULL);
1789 sc->rx.defant = ath9k_hw_getdefantenna(ah);
1791 if (ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
1792 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN);
1794 sc->beacon.slottime = ATH9K_SLOT_TIME_9; /* default to short slot time */
1796 /* initialize beacon slots */
1797 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
1798 sc->beacon.bslot[i] = NULL;
1799 sc->beacon.bslot_aphy[i] = NULL;
1802 /* setup channels and rates */
1804 sc->sbands[IEEE80211_BAND_2GHZ].channels = ath9k_2ghz_chantable;
1805 sc->sbands[IEEE80211_BAND_2GHZ].bitrates =
1806 sc->rates[IEEE80211_BAND_2GHZ];
1807 sc->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ;
1808 sc->sbands[IEEE80211_BAND_2GHZ].n_channels =
1809 ARRAY_SIZE(ath9k_2ghz_chantable);
1811 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) {
1812 sc->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_chantable;
1813 sc->sbands[IEEE80211_BAND_5GHZ].bitrates =
1814 sc->rates[IEEE80211_BAND_5GHZ];
1815 sc->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ;
1816 sc->sbands[IEEE80211_BAND_5GHZ].n_channels =
1817 ARRAY_SIZE(ath9k_5ghz_chantable);
1820 switch (ah->btcoex_hw.scheme) {
1821 case ATH_BTCOEX_CFG_NONE:
1823 case ATH_BTCOEX_CFG_2WIRE:
1824 ath9k_hw_btcoex_init_2wire(ah);
1826 case ATH_BTCOEX_CFG_3WIRE:
1827 ath9k_hw_btcoex_init_3wire(ah);
1828 r = ath_init_btcoex_timer(sc);
1831 qnum = ath_tx_get_qnum(sc, ATH9K_TX_QUEUE_DATA, ATH9K_WME_AC_BE);
1832 ath9k_hw_init_btcoex_hw(ah, qnum);
1833 sc->btcoex.bt_stomp_type = ATH_BTCOEX_STOMP_LOW;
1842 /* cleanup tx queues */
1843 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1844 if (ATH_TXQ_SETUP(sc, i))
1845 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1847 ath9k_hw_detach(ah);
1849 ath9k_exit_debug(sc->sc_ah);
1855 void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
1857 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
1858 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1859 IEEE80211_HW_SIGNAL_DBM |
1860 IEEE80211_HW_AMPDU_AGGREGATION |
1861 IEEE80211_HW_SUPPORTS_PS |
1862 IEEE80211_HW_PS_NULLFUNC_STACK |
1863 IEEE80211_HW_SPECTRUM_MGMT;
1865 if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || modparam_nohwcrypt)
1866 hw->flags |= IEEE80211_HW_MFP_CAPABLE;
1868 hw->wiphy->interface_modes =
1869 BIT(NL80211_IFTYPE_AP) |
1870 BIT(NL80211_IFTYPE_STATION) |
1871 BIT(NL80211_IFTYPE_ADHOC) |
1872 BIT(NL80211_IFTYPE_MESH_POINT);
1876 hw->channel_change_time = 5000;
1877 hw->max_listen_interval = 10;
1878 /* Hardware supports 10 but we use 4 */
1879 hw->max_rate_tries = 4;
1880 hw->sta_data_size = sizeof(struct ath_node);
1881 hw->vif_data_size = sizeof(struct ath_vif);
1883 hw->rate_control_algorithm = "ath9k_rate_control";
1885 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
1886 &sc->sbands[IEEE80211_BAND_2GHZ];
1887 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes))
1888 hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
1889 &sc->sbands[IEEE80211_BAND_5GHZ];
1892 /* Device driver core initialization */
1893 int ath_init_device(u16 devid, struct ath_softc *sc, u16 subsysid,
1894 const struct ath_bus_ops *bus_ops)
1896 struct ieee80211_hw *hw = sc->hw;
1897 struct ath_common *common;
1900 struct ath_regulatory *reg;
1902 dev_dbg(sc->dev, "Attach ATH hw\n");
1904 error = ath_init_softc(devid, sc, subsysid, bus_ops);
1909 common = ath9k_hw_common(ah);
1911 /* get mac address from hardware and set in mac80211 */
1913 SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
1915 ath_set_hw_capab(sc, hw);
1917 error = ath_regd_init(&common->regulatory, sc->hw->wiphy,
1918 ath9k_reg_notifier);
1922 reg = &common->regulatory;
1924 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1925 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1926 if (test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes))
1927 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1930 /* initialize tx/rx engine */
1931 error = ath_tx_init(sc, ATH_TXBUF);
1935 error = ath_rx_init(sc, ATH_RXBUF);
1939 INIT_WORK(&sc->chan_work, ath9k_wiphy_chan_work);
1940 INIT_DELAYED_WORK(&sc->wiphy_work, ath9k_wiphy_work);
1941 sc->wiphy_scheduler_int = msecs_to_jiffies(500);
1943 error = ieee80211_register_hw(hw);
1945 if (!ath_is_world_regd(reg)) {
1946 error = regulatory_hint(hw->wiphy, reg->alpha2);
1951 /* Initialize LED control */
1954 ath_start_rfkill_poll(sc);
1959 /* cleanup tx queues */
1960 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1961 if (ATH_TXQ_SETUP(sc, i))
1962 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1964 ath9k_hw_detach(ah);
1965 ath9k_exit_debug(ah);
1971 int ath_reset(struct ath_softc *sc, bool retry_tx)
1973 struct ath_hw *ah = sc->sc_ah;
1974 struct ath_common *common = ath9k_hw_common(ah);
1975 struct ieee80211_hw *hw = sc->hw;
1978 ath9k_hw_set_interrupts(ah, 0);
1979 ath_drain_all_txq(sc, retry_tx);
1983 spin_lock_bh(&sc->sc_resetlock);
1984 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1986 ath_print(common, ATH_DBG_FATAL,
1987 "Unable to reset hardware; reset status %d\n", r);
1988 spin_unlock_bh(&sc->sc_resetlock);
1990 if (ath_startrecv(sc) != 0)
1991 ath_print(common, ATH_DBG_FATAL,
1992 "Unable to start recv logic\n");
1995 * We may be doing a reset in response to a request
1996 * that changes the channel so update any state that
1997 * might change as a result.
1999 ath_cache_conf_rate(sc, &hw->conf);
2001 ath_update_txpow(sc);
2003 if (sc->sc_flags & SC_OP_BEACONS)
2004 ath_beacon_config(sc, NULL); /* restart beacons */
2006 ath9k_hw_set_interrupts(ah, sc->imask);
2010 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2011 if (ATH_TXQ_SETUP(sc, i)) {
2012 spin_lock_bh(&sc->tx.txq[i].axq_lock);
2013 ath_txq_schedule(sc, &sc->tx.txq[i]);
2014 spin_unlock_bh(&sc->tx.txq[i].axq_lock);
2023 * This function will allocate both the DMA descriptor structure, and the
2024 * buffers it contains. These are used to contain the descriptors used
2027 int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
2028 struct list_head *head, const char *name,
2029 int nbuf, int ndesc)
2031 #define DS2PHYS(_dd, _ds) \
2032 ((_dd)->dd_desc_paddr + ((caddr_t)(_ds) - (caddr_t)(_dd)->dd_desc))
2033 #define ATH_DESC_4KB_BOUND_CHECK(_daddr) ((((_daddr) & 0xFFF) > 0xF7F) ? 1 : 0)
2034 #define ATH_DESC_4KB_BOUND_NUM_SKIPPED(_len) ((_len) / 4096)
2035 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2036 struct ath_desc *ds;
2038 int i, bsize, error;
2040 ath_print(common, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
2043 INIT_LIST_HEAD(head);
2044 /* ath_desc must be a multiple of DWORDs */
2045 if ((sizeof(struct ath_desc) % 4) != 0) {
2046 ath_print(common, ATH_DBG_FATAL,
2047 "ath_desc not DWORD aligned\n");
2048 BUG_ON((sizeof(struct ath_desc) % 4) != 0);
2053 dd->dd_desc_len = sizeof(struct ath_desc) * nbuf * ndesc;
2056 * Need additional DMA memory because we can't use
2057 * descriptors that cross the 4K page boundary. Assume
2058 * one skipped descriptor per 4K page.
2060 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
2062 ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
2065 while (ndesc_skipped) {
2066 dma_len = ndesc_skipped * sizeof(struct ath_desc);
2067 dd->dd_desc_len += dma_len;
2069 ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
2073 /* allocate descriptors */
2074 dd->dd_desc = dma_alloc_coherent(sc->dev, dd->dd_desc_len,
2075 &dd->dd_desc_paddr, GFP_KERNEL);
2076 if (dd->dd_desc == NULL) {
2081 ath_print(common, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
2082 name, ds, (u32) dd->dd_desc_len,
2083 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
2085 /* allocate buffers */
2086 bsize = sizeof(struct ath_buf) * nbuf;
2087 bf = kzalloc(bsize, GFP_KERNEL);
2094 for (i = 0; i < nbuf; i++, bf++, ds += ndesc) {
2096 bf->bf_daddr = DS2PHYS(dd, ds);
2098 if (!(sc->sc_ah->caps.hw_caps &
2099 ATH9K_HW_CAP_4KB_SPLITTRANS)) {
2101 * Skip descriptor addresses which can cause 4KB
2102 * boundary crossing (addr + length) with a 32 dword
2105 while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
2106 BUG_ON((caddr_t) bf->bf_desc >=
2107 ((caddr_t) dd->dd_desc +
2112 bf->bf_daddr = DS2PHYS(dd, ds);
2115 list_add_tail(&bf->list, head);
2119 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2122 memset(dd, 0, sizeof(*dd));
2124 #undef ATH_DESC_4KB_BOUND_CHECK
2125 #undef ATH_DESC_4KB_BOUND_NUM_SKIPPED
2129 void ath_descdma_cleanup(struct ath_softc *sc,
2130 struct ath_descdma *dd,
2131 struct list_head *head)
2133 dma_free_coherent(sc->dev, dd->dd_desc_len, dd->dd_desc,
2136 INIT_LIST_HEAD(head);
2137 kfree(dd->dd_bufptr);
2138 memset(dd, 0, sizeof(*dd));
2141 int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
2147 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VO];
2150 qnum = sc->tx.hwq_map[ATH9K_WME_AC_VI];
2153 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
2156 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BK];
2159 qnum = sc->tx.hwq_map[ATH9K_WME_AC_BE];
2166 int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
2171 case ATH9K_WME_AC_VO:
2174 case ATH9K_WME_AC_VI:
2177 case ATH9K_WME_AC_BE:
2180 case ATH9K_WME_AC_BK:
2191 /* XXX: Remove me once we don't depend on ath9k_channel for all
2192 * this redundant data */
2193 void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
2194 struct ath9k_channel *ichan)
2196 struct ieee80211_channel *chan = hw->conf.channel;
2197 struct ieee80211_conf *conf = &hw->conf;
2199 ichan->channel = chan->center_freq;
2202 if (chan->band == IEEE80211_BAND_2GHZ) {
2203 ichan->chanmode = CHANNEL_G;
2204 ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G;
2206 ichan->chanmode = CHANNEL_A;
2207 ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
2210 if (conf_is_ht(conf))
2211 ichan->chanmode = ath_get_extchanmode(sc, chan,
2212 conf->channel_type);
2215 /**********************/
2216 /* mac80211 callbacks */
2217 /**********************/
2220 * (Re)start btcoex timers
2222 static void ath9k_btcoex_timer_resume(struct ath_softc *sc)
2224 struct ath_btcoex *btcoex = &sc->btcoex;
2225 struct ath_hw *ah = sc->sc_ah;
2227 ath_print(ath9k_hw_common(ah), ATH_DBG_BTCOEX,
2228 "Starting btcoex timers");
2230 /* make sure duty cycle timer is also stopped when resuming */
2231 if (btcoex->hw_timer_enabled)
2232 ath9k_gen_timer_stop(sc->sc_ah, btcoex->no_stomp_timer);
2234 btcoex->bt_priority_cnt = 0;
2235 btcoex->bt_priority_time = jiffies;
2236 sc->sc_flags &= ~SC_OP_BT_PRIORITY_DETECTED;
2238 mod_timer(&btcoex->period_timer, jiffies);
2241 static int ath9k_start(struct ieee80211_hw *hw)
2243 struct ath_wiphy *aphy = hw->priv;
2244 struct ath_softc *sc = aphy->sc;
2245 struct ath_hw *ah = sc->sc_ah;
2246 struct ath_common *common = ath9k_hw_common(ah);
2247 struct ieee80211_channel *curchan = hw->conf.channel;
2248 struct ath9k_channel *init_channel;
2251 ath_print(common, ATH_DBG_CONFIG,
2252 "Starting driver with initial channel: %d MHz\n",
2253 curchan->center_freq);
2255 mutex_lock(&sc->mutex);
2257 if (ath9k_wiphy_started(sc)) {
2258 if (sc->chan_idx == curchan->hw_value) {
2260 * Already on the operational channel, the new wiphy
2261 * can be marked active.
2263 aphy->state = ATH_WIPHY_ACTIVE;
2264 ieee80211_wake_queues(hw);
2267 * Another wiphy is on another channel, start the new
2268 * wiphy in paused state.
2270 aphy->state = ATH_WIPHY_PAUSED;
2271 ieee80211_stop_queues(hw);
2273 mutex_unlock(&sc->mutex);
2276 aphy->state = ATH_WIPHY_ACTIVE;
2278 /* setup initial channel */
2280 sc->chan_idx = curchan->hw_value;
2282 init_channel = ath_get_curchannel(sc, hw);
2284 /* Reset SERDES registers */
2285 ath9k_hw_configpcipowersave(ah, 0, 0);
2288 * The basic interface to setting the hardware in a good
2289 * state is ``reset''. On return the hardware is known to
2290 * be powered up and with interrupts disabled. This must
2291 * be followed by initialization of the appropriate bits
2292 * and then setup of the interrupt mask.
2294 spin_lock_bh(&sc->sc_resetlock);
2295 r = ath9k_hw_reset(ah, init_channel, false);
2297 ath_print(common, ATH_DBG_FATAL,
2298 "Unable to reset hardware; reset status %d "
2299 "(freq %u MHz)\n", r,
2300 curchan->center_freq);
2301 spin_unlock_bh(&sc->sc_resetlock);
2304 spin_unlock_bh(&sc->sc_resetlock);
2307 * This is needed only to setup initial state
2308 * but it's best done after a reset.
2310 ath_update_txpow(sc);
2313 * Setup the hardware after reset:
2314 * The receive engine is set going.
2315 * Frame transmit is handled entirely
2316 * in the frame output path; there's nothing to do
2317 * here except setup the interrupt mask.
2319 if (ath_startrecv(sc) != 0) {
2320 ath_print(common, ATH_DBG_FATAL,
2321 "Unable to start recv logic\n");
2326 /* Setup our intr mask. */
2327 sc->imask = ATH9K_INT_RX | ATH9K_INT_TX
2328 | ATH9K_INT_RXEOL | ATH9K_INT_RXORN
2329 | ATH9K_INT_FATAL | ATH9K_INT_GLOBAL;
2331 if (ah->caps.hw_caps & ATH9K_HW_CAP_GTT)
2332 sc->imask |= ATH9K_INT_GTT;
2334 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
2335 sc->imask |= ATH9K_INT_CST;
2337 ath_cache_conf_rate(sc, &hw->conf);
2339 sc->sc_flags &= ~SC_OP_INVALID;
2341 /* Disable BMISS interrupt when we're not associated */
2342 sc->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
2343 ath9k_hw_set_interrupts(ah, sc->imask);
2345 ieee80211_wake_queues(hw);
2347 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
2349 if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
2350 !ah->btcoex_hw.enabled) {
2351 ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
2352 AR_STOMP_LOW_WLAN_WGHT);
2353 ath9k_hw_btcoex_enable(ah);
2355 if (common->bus_ops->bt_coex_prep)
2356 common->bus_ops->bt_coex_prep(common);
2357 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
2358 ath9k_btcoex_timer_resume(sc);
2362 mutex_unlock(&sc->mutex);
2367 static int ath9k_tx(struct ieee80211_hw *hw,
2368 struct sk_buff *skb)
2370 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2371 struct ath_wiphy *aphy = hw->priv;
2372 struct ath_softc *sc = aphy->sc;
2373 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2374 struct ath_tx_control txctl;
2375 int hdrlen, padsize;
2377 if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
2378 ath_print(common, ATH_DBG_XMIT,
2379 "ath9k: %s: TX in unexpected wiphy state "
2380 "%d\n", wiphy_name(hw->wiphy), aphy->state);
2384 if (sc->ps_enabled) {
2385 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2387 * mac80211 does not set PM field for normal data frames, so we
2388 * need to update that based on the current PS mode.
2390 if (ieee80211_is_data(hdr->frame_control) &&
2391 !ieee80211_is_nullfunc(hdr->frame_control) &&
2392 !ieee80211_has_pm(hdr->frame_control)) {
2393 ath_print(common, ATH_DBG_PS, "Add PM=1 for a TX frame "
2394 "while in PS mode\n");
2395 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
2399 if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
2401 * We are using PS-Poll and mac80211 can request TX while in
2402 * power save mode. Need to wake up hardware for the TX to be
2403 * completed and if needed, also for RX of buffered frames.
2405 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2406 ath9k_ps_wakeup(sc);
2407 ath9k_hw_setrxabort(sc->sc_ah, 0);
2408 if (ieee80211_is_pspoll(hdr->frame_control)) {
2409 ath_print(common, ATH_DBG_PS,
2410 "Sending PS-Poll to pick a buffered frame\n");
2411 sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
2413 ath_print(common, ATH_DBG_PS,
2414 "Wake up to complete TX\n");
2415 sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
2418 * The actual restore operation will happen only after
2419 * the sc_flags bit is cleared. We are just dropping
2420 * the ps_usecount here.
2422 ath9k_ps_restore(sc);
2425 memset(&txctl, 0, sizeof(struct ath_tx_control));
2428 * As a temporary workaround, assign seq# here; this will likely need
2429 * to be cleaned up to work better with Beacon transmission and virtual
2432 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
2433 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2434 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2435 sc->tx.seq_no += 0x10;
2436 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2437 hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
2440 /* Add the padding after the header if this is not already done */
2441 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2443 padsize = hdrlen % 4;
2444 if (skb_headroom(skb) < padsize)
2446 skb_push(skb, padsize);
2447 memmove(skb->data, skb->data + padsize, hdrlen);
2450 /* Check if a tx queue is available */
2452 txctl.txq = ath_test_get_txq(sc, skb);
2456 ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2458 if (ath_tx_start(hw, skb, &txctl) != 0) {
2459 ath_print(common, ATH_DBG_XMIT, "TX failed\n");
2465 dev_kfree_skb_any(skb);
2470 * Pause btcoex timer and bt duty cycle timer
2472 static void ath9k_btcoex_timer_pause(struct ath_softc *sc)
2474 struct ath_btcoex *btcoex = &sc->btcoex;
2475 struct ath_hw *ah = sc->sc_ah;
2477 del_timer_sync(&btcoex->period_timer);
2479 if (btcoex->hw_timer_enabled)
2480 ath9k_gen_timer_stop(ah, btcoex->no_stomp_timer);
2482 btcoex->hw_timer_enabled = false;
2485 static void ath9k_stop(struct ieee80211_hw *hw)
2487 struct ath_wiphy *aphy = hw->priv;
2488 struct ath_softc *sc = aphy->sc;
2489 struct ath_hw *ah = sc->sc_ah;
2490 struct ath_common *common = ath9k_hw_common(ah);
2492 mutex_lock(&sc->mutex);
2494 aphy->state = ATH_WIPHY_INACTIVE;
2496 cancel_delayed_work_sync(&sc->ath_led_blink_work);
2497 cancel_delayed_work_sync(&sc->tx_complete_work);
2499 if (!sc->num_sec_wiphy) {
2500 cancel_delayed_work_sync(&sc->wiphy_work);
2501 cancel_work_sync(&sc->chan_work);
2504 if (sc->sc_flags & SC_OP_INVALID) {
2505 ath_print(common, ATH_DBG_ANY, "Device not present\n");
2506 mutex_unlock(&sc->mutex);
2510 if (ath9k_wiphy_started(sc)) {
2511 mutex_unlock(&sc->mutex);
2512 return; /* another wiphy still in use */
2515 if (ah->btcoex_hw.enabled) {
2516 ath9k_hw_btcoex_disable(ah);
2517 if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
2518 ath9k_btcoex_timer_pause(sc);
2521 /* make sure h/w will not generate any interrupt
2522 * before setting the invalid flag. */
2523 ath9k_hw_set_interrupts(ah, 0);
2525 if (!(sc->sc_flags & SC_OP_INVALID)) {
2526 ath_drain_all_txq(sc, false);
2528 ath9k_hw_phy_disable(ah);
2530 sc->rx.rxlink = NULL;
2532 /* disable HAL and put h/w to sleep */
2533 ath9k_hw_disable(ah);
2534 ath9k_hw_configpcipowersave(ah, 1, 1);
2535 ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
2537 sc->sc_flags |= SC_OP_INVALID;
2539 mutex_unlock(&sc->mutex);
2541 ath_print(common, ATH_DBG_CONFIG, "Driver halt\n");
2544 static int ath9k_add_interface(struct ieee80211_hw *hw,
2545 struct ieee80211_if_init_conf *conf)
2547 struct ath_wiphy *aphy = hw->priv;
2548 struct ath_softc *sc = aphy->sc;
2549 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2550 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2551 enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
2554 mutex_lock(&sc->mutex);
2556 if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) &&
2562 switch (conf->type) {
2563 case NL80211_IFTYPE_STATION:
2564 ic_opmode = NL80211_IFTYPE_STATION;
2566 case NL80211_IFTYPE_ADHOC:
2567 case NL80211_IFTYPE_AP:
2568 case NL80211_IFTYPE_MESH_POINT:
2569 if (sc->nbcnvifs >= ATH_BCBUF) {
2573 ic_opmode = conf->type;
2576 ath_print(common, ATH_DBG_FATAL,
2577 "Interface type %d not yet supported\n", conf->type);
2582 ath_print(common, ATH_DBG_CONFIG,
2583 "Attach a VIF of type: %d\n", ic_opmode);
2585 /* Set the VIF opmode */
2586 avp->av_opmode = ic_opmode;
2591 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK)
2592 ath9k_set_bssid_mask(hw);
2595 goto out; /* skip global settings for secondary vif */
2597 if (ic_opmode == NL80211_IFTYPE_AP) {
2598 ath9k_hw_set_tsfadjust(sc->sc_ah, 1);
2599 sc->sc_flags |= SC_OP_TSF_RESET;
2602 /* Set the device opmode */
2603 sc->sc_ah->opmode = ic_opmode;
2606 * Enable MIB interrupts when there are hardware phy counters.
2607 * Note we only do this (at the moment) for station mode.
2609 if ((conf->type == NL80211_IFTYPE_STATION) ||
2610 (conf->type == NL80211_IFTYPE_ADHOC) ||
2611 (conf->type == NL80211_IFTYPE_MESH_POINT)) {
2612 sc->imask |= ATH9K_INT_MIB;
2613 sc->imask |= ATH9K_INT_TSFOOR;
2616 ath9k_hw_set_interrupts(sc->sc_ah, sc->imask);
2618 if (conf->type == NL80211_IFTYPE_AP ||
2619 conf->type == NL80211_IFTYPE_ADHOC ||
2620 conf->type == NL80211_IFTYPE_MONITOR)
2624 mutex_unlock(&sc->mutex);
2628 static void ath9k_remove_interface(struct ieee80211_hw *hw,
2629 struct ieee80211_if_init_conf *conf)
2631 struct ath_wiphy *aphy = hw->priv;
2632 struct ath_softc *sc = aphy->sc;
2633 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2634 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2637 ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n");
2639 mutex_lock(&sc->mutex);
2642 del_timer_sync(&sc->ani.timer);
2644 /* Reclaim beacon resources */
2645 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
2646 (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
2647 (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
2648 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2649 ath_beacon_return(sc, avp);
2652 sc->sc_flags &= ~SC_OP_BEACONS;
2654 for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
2655 if (sc->beacon.bslot[i] == conf->vif) {
2656 printk(KERN_DEBUG "%s: vif had allocated beacon "
2657 "slot\n", __func__);
2658 sc->beacon.bslot[i] = NULL;
2659 sc->beacon.bslot_aphy[i] = NULL;
2665 mutex_unlock(&sc->mutex);
2668 static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2670 struct ath_wiphy *aphy = hw->priv;
2671 struct ath_softc *sc = aphy->sc;
2672 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2673 struct ieee80211_conf *conf = &hw->conf;
2674 struct ath_hw *ah = sc->sc_ah;
2675 bool all_wiphys_idle = false, disable_radio = false;
2677 mutex_lock(&sc->mutex);
2679 /* Leave this as the first check */
2680 if (changed & IEEE80211_CONF_CHANGE_IDLE) {
2682 spin_lock_bh(&sc->wiphy_lock);
2683 all_wiphys_idle = ath9k_all_wiphys_idle(sc);
2684 spin_unlock_bh(&sc->wiphy_lock);
2686 if (conf->flags & IEEE80211_CONF_IDLE){
2687 if (all_wiphys_idle)
2688 disable_radio = true;
2690 else if (all_wiphys_idle) {
2691 ath_radio_enable(sc);
2692 ath_print(common, ATH_DBG_CONFIG,
2693 "not-idle: enabling radio\n");
2697 if (changed & IEEE80211_CONF_CHANGE_PS) {
2698 if (conf->flags & IEEE80211_CONF_PS) {
2699 if (!(ah->caps.hw_caps &
2700 ATH9K_HW_CAP_AUTOSLEEP)) {
2701 if ((sc->imask & ATH9K_INT_TIM_TIMER) == 0) {
2702 sc->imask |= ATH9K_INT_TIM_TIMER;
2703 ath9k_hw_set_interrupts(sc->sc_ah,
2706 ath9k_hw_setrxabort(sc->sc_ah, 1);
2708 sc->ps_enabled = true;
2710 sc->ps_enabled = false;
2711 ath9k_setpower(sc, ATH9K_PM_AWAKE);
2712 if (!(ah->caps.hw_caps &
2713 ATH9K_HW_CAP_AUTOSLEEP)) {
2714 ath9k_hw_setrxabort(sc->sc_ah, 0);
2715 sc->sc_flags &= ~(SC_OP_WAIT_FOR_BEACON |
2716 SC_OP_WAIT_FOR_CAB |
2717 SC_OP_WAIT_FOR_PSPOLL_DATA |
2718 SC_OP_WAIT_FOR_TX_ACK);
2719 if (sc->imask & ATH9K_INT_TIM_TIMER) {
2720 sc->imask &= ~ATH9K_INT_TIM_TIMER;
2721 ath9k_hw_set_interrupts(sc->sc_ah,
2728 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2729 struct ieee80211_channel *curchan = hw->conf.channel;
2730 int pos = curchan->hw_value;
2732 aphy->chan_idx = pos;
2733 aphy->chan_is_ht = conf_is_ht(conf);
2735 if (aphy->state == ATH_WIPHY_SCAN ||
2736 aphy->state == ATH_WIPHY_ACTIVE)
2737 ath9k_wiphy_pause_all_forced(sc, aphy);
2740 * Do not change operational channel based on a paused
2743 goto skip_chan_change;
2746 ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2747 curchan->center_freq);
2749 /* XXX: remove me eventualy */
2750 ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
2752 ath_update_chainmask(sc, conf_is_ht(conf));
2754 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
2755 ath_print(common, ATH_DBG_FATAL,
2756 "Unable to set channel\n");
2757 mutex_unlock(&sc->mutex);
2763 if (changed & IEEE80211_CONF_CHANGE_POWER)
2764 sc->config.txpowlimit = 2 * conf->power_level;
2766 if (disable_radio) {
2767 ath_print(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
2768 ath_radio_disable(sc);
2771 mutex_unlock(&sc->mutex);
2776 #define SUPPORTED_FILTERS \
2777 (FIF_PROMISC_IN_BSS | \
2782 FIF_BCN_PRBRESP_PROMISC | \
2785 /* FIXME: sc->sc_full_reset ? */
2786 static void ath9k_configure_filter(struct ieee80211_hw *hw,
2787 unsigned int changed_flags,
2788 unsigned int *total_flags,
2791 struct ath_wiphy *aphy = hw->priv;
2792 struct ath_softc *sc = aphy->sc;
2795 changed_flags &= SUPPORTED_FILTERS;
2796 *total_flags &= SUPPORTED_FILTERS;
2798 sc->rx.rxfilter = *total_flags;
2799 ath9k_ps_wakeup(sc);
2800 rfilt = ath_calcrxfilter(sc);
2801 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2802 ath9k_ps_restore(sc);
2804 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
2805 "Set HW RX filter: 0x%x\n", rfilt);
2808 static void ath9k_sta_notify(struct ieee80211_hw *hw,
2809 struct ieee80211_vif *vif,
2810 enum sta_notify_cmd cmd,
2811 struct ieee80211_sta *sta)
2813 struct ath_wiphy *aphy = hw->priv;
2814 struct ath_softc *sc = aphy->sc;
2817 case STA_NOTIFY_ADD:
2818 ath_node_attach(sc, sta);
2820 case STA_NOTIFY_REMOVE:
2821 ath_node_detach(sc, sta);
2828 static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2829 const struct ieee80211_tx_queue_params *params)
2831 struct ath_wiphy *aphy = hw->priv;
2832 struct ath_softc *sc = aphy->sc;
2833 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2834 struct ath9k_tx_queue_info qi;
2837 if (queue >= WME_NUM_AC)
2840 mutex_lock(&sc->mutex);
2842 memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
2844 qi.tqi_aifs = params->aifs;
2845 qi.tqi_cwmin = params->cw_min;
2846 qi.tqi_cwmax = params->cw_max;
2847 qi.tqi_burstTime = params->txop;
2848 qnum = ath_get_hal_qnum(queue, sc);
2850 ath_print(common, ATH_DBG_CONFIG,
2851 "Configure tx [queue/halq] [%d/%d], "
2852 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2853 queue, qnum, params->aifs, params->cw_min,
2854 params->cw_max, params->txop);
2856 ret = ath_txq_update(sc, qnum, &qi);
2858 ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n");
2860 mutex_unlock(&sc->mutex);
2865 static int ath9k_set_key(struct ieee80211_hw *hw,
2866 enum set_key_cmd cmd,
2867 struct ieee80211_vif *vif,
2868 struct ieee80211_sta *sta,
2869 struct ieee80211_key_conf *key)
2871 struct ath_wiphy *aphy = hw->priv;
2872 struct ath_softc *sc = aphy->sc;
2873 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2876 if (modparam_nohwcrypt)
2879 mutex_lock(&sc->mutex);
2880 ath9k_ps_wakeup(sc);
2881 ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n");
2885 ret = ath_key_config(sc, vif, sta, key);
2887 key->hw_key_idx = ret;
2888 /* push IV and Michael MIC generation to stack */
2889 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
2890 if (key->alg == ALG_TKIP)
2891 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
2892 if (sc->sc_ah->sw_mgmt_crypto && key->alg == ALG_CCMP)
2893 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
2898 ath_key_delete(sc, key);
2904 ath9k_ps_restore(sc);
2905 mutex_unlock(&sc->mutex);
2910 static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2911 struct ieee80211_vif *vif,
2912 struct ieee80211_bss_conf *bss_conf,
2915 struct ath_wiphy *aphy = hw->priv;
2916 struct ath_softc *sc = aphy->sc;
2917 struct ath_hw *ah = sc->sc_ah;
2918 struct ath_common *common = ath9k_hw_common(ah);
2919 struct ath_vif *avp = (void *)vif->drv_priv;
2923 mutex_lock(&sc->mutex);
2926 * TODO: Need to decide which hw opmode to use for
2927 * multi-interface cases
2928 * XXX: This belongs into add_interface!
2930 if (vif->type == NL80211_IFTYPE_AP &&
2931 ah->opmode != NL80211_IFTYPE_AP) {
2932 ah->opmode = NL80211_IFTYPE_STATION;
2933 ath9k_hw_setopmode(ah);
2934 memcpy(common->curbssid, common->macaddr, ETH_ALEN);
2936 ath9k_hw_write_associd(ah);
2937 /* Request full reset to get hw opmode changed properly */
2938 sc->sc_flags |= SC_OP_FULL_RESET;
2941 if ((changed & BSS_CHANGED_BSSID) &&
2942 !is_zero_ether_addr(bss_conf->bssid)) {
2943 switch (vif->type) {
2944 case NL80211_IFTYPE_STATION:
2945 case NL80211_IFTYPE_ADHOC:
2946 case NL80211_IFTYPE_MESH_POINT:
2948 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
2949 memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
2951 ath9k_hw_write_associd(ah);
2953 /* Set aggregation protection mode parameters */
2954 sc->config.ath_aggr_prot = 0;
2956 ath_print(common, ATH_DBG_CONFIG,
2957 "RX filter 0x%x bssid %pM aid 0x%x\n",
2958 rfilt, common->curbssid, common->curaid);
2960 /* need to reconfigure the beacon */
2961 sc->sc_flags &= ~SC_OP_BEACONS ;
2969 if ((vif->type == NL80211_IFTYPE_ADHOC) ||
2970 (vif->type == NL80211_IFTYPE_AP) ||
2971 (vif->type == NL80211_IFTYPE_MESH_POINT)) {
2972 if ((changed & BSS_CHANGED_BEACON) ||
2973 (changed & BSS_CHANGED_BEACON_ENABLED &&
2974 bss_conf->enable_beacon)) {
2976 * Allocate and setup the beacon frame.
2978 * Stop any previous beacon DMA. This may be
2979 * necessary, for example, when an ibss merge
2980 * causes reconfiguration; we may be called
2981 * with beacon transmission active.
2983 ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
2985 error = ath_beacon_alloc(aphy, vif);
2987 ath_beacon_config(sc, vif);
2991 /* Check for WLAN_CAPABILITY_PRIVACY ? */
2992 if ((avp->av_opmode != NL80211_IFTYPE_STATION)) {
2993 for (i = 0; i < IEEE80211_WEP_NKID; i++)
2994 if (ath9k_hw_keyisvalid(sc->sc_ah, (u16)i))
2995 ath9k_hw_keysetmac(sc->sc_ah,
3000 /* Only legacy IBSS for now */
3001 if (vif->type == NL80211_IFTYPE_ADHOC)
3002 ath_update_chainmask(sc, 0);
3004 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
3005 ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
3006 bss_conf->use_short_preamble);
3007 if (bss_conf->use_short_preamble)
3008 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
3010 sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
3013 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
3014 ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
3015 bss_conf->use_cts_prot);
3016 if (bss_conf->use_cts_prot &&
3017 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
3018 sc->sc_flags |= SC_OP_PROTECT_ENABLE;
3020 sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
3023 if (changed & BSS_CHANGED_ASSOC) {
3024 ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
3026 ath9k_bss_assoc_info(sc, vif, bss_conf);
3030 * The HW TSF has to be reset when the beacon interval changes.
3031 * We set the flag here, and ath_beacon_config_ap() would take this
3032 * into account when it gets called through the subsequent
3033 * config_interface() call - with IFCC_BEACON in the changed field.
3036 if (changed & BSS_CHANGED_BEACON_INT) {
3037 sc->sc_flags |= SC_OP_TSF_RESET;
3038 sc->beacon_interval = bss_conf->beacon_int;
3041 mutex_unlock(&sc->mutex);
3044 static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
3047 struct ath_wiphy *aphy = hw->priv;
3048 struct ath_softc *sc = aphy->sc;
3050 mutex_lock(&sc->mutex);
3051 tsf = ath9k_hw_gettsf64(sc->sc_ah);
3052 mutex_unlock(&sc->mutex);
3057 static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3059 struct ath_wiphy *aphy = hw->priv;
3060 struct ath_softc *sc = aphy->sc;
3062 mutex_lock(&sc->mutex);
3063 ath9k_hw_settsf64(sc->sc_ah, tsf);
3064 mutex_unlock(&sc->mutex);
3067 static void ath9k_reset_tsf(struct ieee80211_hw *hw)
3069 struct ath_wiphy *aphy = hw->priv;
3070 struct ath_softc *sc = aphy->sc;
3072 mutex_lock(&sc->mutex);
3074 ath9k_ps_wakeup(sc);
3075 ath9k_hw_reset_tsf(sc->sc_ah);
3076 ath9k_ps_restore(sc);
3078 mutex_unlock(&sc->mutex);
3081 static int ath9k_ampdu_action(struct ieee80211_hw *hw,
3082 enum ieee80211_ampdu_mlme_action action,
3083 struct ieee80211_sta *sta,
3086 struct ath_wiphy *aphy = hw->priv;
3087 struct ath_softc *sc = aphy->sc;
3091 case IEEE80211_AMPDU_RX_START:
3092 if (!(sc->sc_flags & SC_OP_RXAGGR))
3095 case IEEE80211_AMPDU_RX_STOP:
3097 case IEEE80211_AMPDU_TX_START:
3098 ath_tx_aggr_start(sc, sta, tid, ssn);
3099 ieee80211_start_tx_ba_cb_irqsafe(hw, sta->addr, tid);
3101 case IEEE80211_AMPDU_TX_STOP:
3102 ath_tx_aggr_stop(sc, sta, tid);
3103 ieee80211_stop_tx_ba_cb_irqsafe(hw, sta->addr, tid);
3105 case IEEE80211_AMPDU_TX_OPERATIONAL:
3106 ath_tx_aggr_resume(sc, sta, tid);
3109 ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
3110 "Unknown AMPDU action\n");
3116 static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
3118 struct ath_wiphy *aphy = hw->priv;
3119 struct ath_softc *sc = aphy->sc;
3121 mutex_lock(&sc->mutex);
3122 if (ath9k_wiphy_scanning(sc)) {
3123 printk(KERN_DEBUG "ath9k: Two wiphys trying to scan at the "
3126 * Do not allow the concurrent scanning state for now. This
3127 * could be improved with scanning control moved into ath9k.
3129 mutex_unlock(&sc->mutex);
3133 aphy->state = ATH_WIPHY_SCAN;
3134 ath9k_wiphy_pause_all_forced(sc, aphy);
3136 spin_lock_bh(&sc->ani_lock);
3137 sc->sc_flags |= SC_OP_SCANNING;
3138 spin_unlock_bh(&sc->ani_lock);
3139 mutex_unlock(&sc->mutex);
3142 static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
3144 struct ath_wiphy *aphy = hw->priv;
3145 struct ath_softc *sc = aphy->sc;
3147 mutex_lock(&sc->mutex);
3148 spin_lock_bh(&sc->ani_lock);
3149 aphy->state = ATH_WIPHY_ACTIVE;
3150 sc->sc_flags &= ~SC_OP_SCANNING;
3151 sc->sc_flags |= SC_OP_FULL_RESET;
3152 spin_unlock_bh(&sc->ani_lock);
3153 ath_beacon_config(sc, NULL);
3154 mutex_unlock(&sc->mutex);
3157 struct ieee80211_ops ath9k_ops = {
3159 .start = ath9k_start,
3161 .add_interface = ath9k_add_interface,
3162 .remove_interface = ath9k_remove_interface,
3163 .config = ath9k_config,
3164 .configure_filter = ath9k_configure_filter,
3165 .sta_notify = ath9k_sta_notify,
3166 .conf_tx = ath9k_conf_tx,
3167 .bss_info_changed = ath9k_bss_info_changed,
3168 .set_key = ath9k_set_key,
3169 .get_tsf = ath9k_get_tsf,
3170 .set_tsf = ath9k_set_tsf,
3171 .reset_tsf = ath9k_reset_tsf,
3172 .ampdu_action = ath9k_ampdu_action,
3173 .sw_scan_start = ath9k_sw_scan_start,
3174 .sw_scan_complete = ath9k_sw_scan_complete,
3175 .rfkill_poll = ath9k_rfkill_poll_state,
3181 } ath_mac_bb_names[] = {
3182 { AR_SREV_VERSION_5416_PCI, "5416" },
3183 { AR_SREV_VERSION_5416_PCIE, "5418" },
3184 { AR_SREV_VERSION_9100, "9100" },
3185 { AR_SREV_VERSION_9160, "9160" },
3186 { AR_SREV_VERSION_9280, "9280" },
3187 { AR_SREV_VERSION_9285, "9285" },
3188 { AR_SREV_VERSION_9287, "9287" }
3194 } ath_rf_names[] = {
3196 { AR_RAD5133_SREV_MAJOR, "5133" },
3197 { AR_RAD5122_SREV_MAJOR, "5122" },
3198 { AR_RAD2133_SREV_MAJOR, "2133" },
3199 { AR_RAD2122_SREV_MAJOR, "2122" }
3203 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3206 ath_mac_bb_name(u32 mac_bb_version)
3210 for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3211 if (ath_mac_bb_names[i].version == mac_bb_version) {
3212 return ath_mac_bb_names[i].name;
3220 * Return the RF name. "????" is returned if the RF is unknown.
3223 ath_rf_name(u16 rf_version)
3227 for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3228 if (ath_rf_names[i].version == rf_version) {
3229 return ath_rf_names[i].name;
3236 static int __init ath9k_init(void)
3240 /* Register rate control algorithm */
3241 error = ath_rate_control_register();
3244 "ath9k: Unable to register rate control "
3250 error = ath9k_debug_create_root();
3253 "ath9k: Unable to create debugfs root: %d\n",
3255 goto err_rate_unregister;
3258 error = ath_pci_init();
3261 "ath9k: No PCI devices found, driver not installed.\n");
3263 goto err_remove_root;
3266 error = ath_ahb_init();
3278 ath9k_debug_remove_root();
3279 err_rate_unregister:
3280 ath_rate_control_unregister();
3284 module_init(ath9k_init);
3286 static void __exit ath9k_exit(void)
3290 ath9k_debug_remove_root();
3291 ath_rate_control_unregister();
3292 printk(KERN_INFO "%s: Driver unloaded\n", dev_info);
3294 module_exit(ath9k_exit);