2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include <asm/unaligned.h>
24 #define ATH9K_CLOCK_RATE_CCK 22
25 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
26 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
28 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
29 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
30 enum ath9k_ht_macmode macmode);
31 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
32 struct ar5416_eeprom_def *pEepData,
34 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
35 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
37 /********************/
38 /* Helper Functions */
39 /********************/
41 static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
43 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
45 if (!ah->curchan) /* should really check for CCK instead */
46 return clks / ATH9K_CLOCK_RATE_CCK;
47 if (conf->channel->band == IEEE80211_BAND_2GHZ)
48 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
50 return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
53 static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
55 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
57 if (conf_is_ht40(conf))
58 return ath9k_hw_mac_usec(ah, clks) / 2;
60 return ath9k_hw_mac_usec(ah, clks);
63 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
65 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
67 if (!ah->curchan) /* should really check for CCK instead */
68 return usecs *ATH9K_CLOCK_RATE_CCK;
69 if (conf->channel->band == IEEE80211_BAND_2GHZ)
70 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
71 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
74 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
76 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
78 if (conf_is_ht40(conf))
79 return ath9k_hw_mac_clks(ah, usecs) * 2;
81 return ath9k_hw_mac_clks(ah, usecs);
84 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
88 BUG_ON(timeout < AH_TIME_QUANTUM);
90 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
91 if ((REG_READ(ah, reg) & mask) == val)
94 udelay(AH_TIME_QUANTUM);
97 DPRINTF(ah, ATH_DBG_ANY,
98 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
99 timeout, reg, REG_READ(ah, reg), mask, val);
104 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
109 for (i = 0, retval = 0; i < n; i++) {
110 retval = (retval << 1) | (val & 1);
116 bool ath9k_get_channel_edges(struct ath_hw *ah,
120 struct ath9k_hw_capabilities *pCap = &ah->caps;
122 if (flags & CHANNEL_5GHZ) {
123 *low = pCap->low_5ghz_chan;
124 *high = pCap->high_5ghz_chan;
127 if ((flags & CHANNEL_2GHZ)) {
128 *low = pCap->low_2ghz_chan;
129 *high = pCap->high_2ghz_chan;
135 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
136 const struct ath_rate_table *rates,
137 u32 frameLen, u16 rateix,
140 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
143 kbps = rates->info[rateix].ratekbps;
148 switch (rates->info[rateix].phy) {
149 case WLAN_RC_PHY_CCK:
150 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
151 if (shortPreamble && rates->info[rateix].short_preamble)
153 numBits = frameLen << 3;
154 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
156 case WLAN_RC_PHY_OFDM:
157 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
158 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
159 numBits = OFDM_PLCP_BITS + (frameLen << 3);
160 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
161 txTime = OFDM_SIFS_TIME_QUARTER
162 + OFDM_PREAMBLE_TIME_QUARTER
163 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
164 } else if (ah->curchan &&
165 IS_CHAN_HALF_RATE(ah->curchan)) {
166 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
167 numBits = OFDM_PLCP_BITS + (frameLen << 3);
168 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
169 txTime = OFDM_SIFS_TIME_HALF +
170 OFDM_PREAMBLE_TIME_HALF
171 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
173 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
174 numBits = OFDM_PLCP_BITS + (frameLen << 3);
175 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
176 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
177 + (numSymbols * OFDM_SYMBOL_TIME);
181 DPRINTF(ah, ATH_DBG_FATAL,
182 "Unknown phy %u (rate ix %u)\n",
183 rates->info[rateix].phy, rateix);
191 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
192 struct ath9k_channel *chan,
193 struct chan_centers *centers)
197 if (!IS_CHAN_HT40(chan)) {
198 centers->ctl_center = centers->ext_center =
199 centers->synth_center = chan->channel;
203 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
204 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
205 centers->synth_center =
206 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
209 centers->synth_center =
210 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
214 centers->ctl_center =
215 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
216 centers->ext_center =
217 centers->synth_center + (extoff *
218 ((ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
219 HT40_CHANNEL_CENTER_SHIFT : 15));
226 static void ath9k_hw_read_revisions(struct ath_hw *ah)
230 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
233 val = REG_READ(ah, AR_SREV);
234 ah->hw_version.macVersion =
235 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
236 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
237 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
239 if (!AR_SREV_9100(ah))
240 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
242 ah->hw_version.macRev = val & AR_SREV_REVISION;
244 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
245 ah->is_pciexpress = true;
249 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
254 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
256 for (i = 0; i < 8; i++)
257 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
258 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
259 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
261 return ath9k_hw_reverse_bits(val, 8);
264 /************************************/
265 /* HW Attach, Detach, Init Routines */
266 /************************************/
268 static void ath9k_hw_disablepcie(struct ath_hw *ah)
270 if (AR_SREV_9100(ah))
273 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
274 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
275 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
276 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
277 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
278 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
279 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
280 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
281 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
283 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
286 static bool ath9k_hw_chip_test(struct ath_hw *ah)
288 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
290 u32 patternData[4] = { 0x55555555,
296 for (i = 0; i < 2; i++) {
297 u32 addr = regAddr[i];
300 regHold[i] = REG_READ(ah, addr);
301 for (j = 0; j < 0x100; j++) {
302 wrData = (j << 16) | j;
303 REG_WRITE(ah, addr, wrData);
304 rdData = REG_READ(ah, addr);
305 if (rdData != wrData) {
306 DPRINTF(ah, ATH_DBG_FATAL,
307 "address test failed "
308 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
309 addr, wrData, rdData);
313 for (j = 0; j < 4; j++) {
314 wrData = patternData[j];
315 REG_WRITE(ah, addr, wrData);
316 rdData = REG_READ(ah, addr);
317 if (wrData != rdData) {
318 DPRINTF(ah, ATH_DBG_FATAL,
319 "address test failed "
320 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
321 addr, wrData, rdData);
325 REG_WRITE(ah, regAddr[i], regHold[i]);
332 static const char *ath9k_hw_devname(u16 devid)
335 case AR5416_DEVID_PCI:
336 return "Atheros 5416";
337 case AR5416_DEVID_PCIE:
338 return "Atheros 5418";
339 case AR9160_DEVID_PCI:
340 return "Atheros 9160";
341 case AR5416_AR9100_DEVID:
342 return "Atheros 9100";
343 case AR9280_DEVID_PCI:
344 case AR9280_DEVID_PCIE:
345 return "Atheros 9280";
346 case AR9285_DEVID_PCIE:
347 return "Atheros 9285";
348 case AR5416_DEVID_AR9287_PCI:
349 case AR5416_DEVID_AR9287_PCIE:
350 return "Atheros 9287";
356 static void ath9k_hw_init_config(struct ath_hw *ah)
360 ah->config.dma_beacon_response_time = 2;
361 ah->config.sw_beacon_response_time = 10;
362 ah->config.additional_swba_backoff = 0;
363 ah->config.ack_6mb = 0x0;
364 ah->config.cwm_ignore_extcca = 0;
365 ah->config.pcie_powersave_enable = 0;
366 ah->config.pcie_clock_req = 0;
367 ah->config.pcie_waen = 0;
368 ah->config.analog_shiftreg = 1;
369 ah->config.ht_enable = 1;
370 ah->config.ofdm_trig_low = 200;
371 ah->config.ofdm_trig_high = 500;
372 ah->config.cck_trig_high = 200;
373 ah->config.cck_trig_low = 100;
374 ah->config.enable_ani = 1;
375 ah->config.diversity_control = ATH9K_ANT_VARIABLE;
376 ah->config.antenna_switch_swap = 0;
378 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
379 ah->config.spurchans[i][0] = AR_NO_SPUR;
380 ah->config.spurchans[i][1] = AR_NO_SPUR;
383 ah->config.intr_mitigation = true;
386 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
387 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
388 * This means we use it for all AR5416 devices, and the few
389 * minor PCI AR9280 devices out there.
391 * Serialization is required because these devices do not handle
392 * well the case of two concurrent reads/writes due to the latency
393 * involved. During one read/write another read/write can be issued
394 * on another CPU while the previous read/write may still be working
395 * on our hardware, if we hit this case the hardware poops in a loop.
396 * We prevent this by serializing reads and writes.
398 * This issue is not present on PCI-Express devices or pre-AR5416
399 * devices (legacy, 802.11abg).
401 if (num_possible_cpus() > 1)
402 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
405 static void ath9k_hw_init_defaults(struct ath_hw *ah)
407 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
409 regulatory->country_code = CTRY_DEFAULT;
410 regulatory->power_limit = MAX_RATE_POWER;
411 regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
413 ah->hw_version.magic = AR5416_MAGIC;
414 ah->hw_version.subvendorid = 0;
417 if (ah->hw_version.devid == AR5416_AR9100_DEVID)
418 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
419 if (!AR_SREV_9100(ah))
420 ah->ah_flags = AH_USE_EEPROM;
423 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
424 ah->beacon_interval = 100;
425 ah->enable_32kHz_clock = DONT_USE_32KHZ;
426 ah->slottime = (u32) -1;
427 ah->acktimeout = (u32) -1;
428 ah->ctstimeout = (u32) -1;
429 ah->globaltxtimeout = (u32) -1;
431 ah->gbeacon_rate = 0;
433 ah->power_mode = ATH9K_PM_UNDEFINED;
436 static int ath9k_hw_rfattach(struct ath_hw *ah)
438 bool rfStatus = false;
441 rfStatus = ath9k_hw_init_rf(ah, &ecode);
443 DPRINTF(ah, ATH_DBG_FATAL,
444 "RF setup failed, status: %u\n", ecode);
451 static int ath9k_hw_rf_claim(struct ath_hw *ah)
455 REG_WRITE(ah, AR_PHY(0), 0x00000007);
457 val = ath9k_hw_get_radiorev(ah);
458 switch (val & AR_RADIO_SREV_MAJOR) {
460 val = AR_RAD5133_SREV_MAJOR;
462 case AR_RAD5133_SREV_MAJOR:
463 case AR_RAD5122_SREV_MAJOR:
464 case AR_RAD2133_SREV_MAJOR:
465 case AR_RAD2122_SREV_MAJOR:
468 DPRINTF(ah, ATH_DBG_FATAL,
469 "Radio Chip Rev 0x%02X not supported\n",
470 val & AR_RADIO_SREV_MAJOR);
474 ah->hw_version.analog5GhzRev = val;
479 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
481 struct ath_common *common = ath9k_hw_common(ah);
487 for (i = 0; i < 3; i++) {
488 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
490 common->macaddr[2 * i] = eeval >> 8;
491 common->macaddr[2 * i + 1] = eeval & 0xff;
493 if (sum == 0 || sum == 0xffff * 3)
494 return -EADDRNOTAVAIL;
499 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
503 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
504 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
506 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
507 INIT_INI_ARRAY(&ah->iniModesRxGain,
508 ar9280Modes_backoff_13db_rxgain_9280_2,
509 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
510 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
511 INIT_INI_ARRAY(&ah->iniModesRxGain,
512 ar9280Modes_backoff_23db_rxgain_9280_2,
513 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
515 INIT_INI_ARRAY(&ah->iniModesRxGain,
516 ar9280Modes_original_rxgain_9280_2,
517 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
519 INIT_INI_ARRAY(&ah->iniModesRxGain,
520 ar9280Modes_original_rxgain_9280_2,
521 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
525 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
529 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
530 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
532 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
533 INIT_INI_ARRAY(&ah->iniModesTxGain,
534 ar9280Modes_high_power_tx_gain_9280_2,
535 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
537 INIT_INI_ARRAY(&ah->iniModesTxGain,
538 ar9280Modes_original_tx_gain_9280_2,
539 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
541 INIT_INI_ARRAY(&ah->iniModesTxGain,
542 ar9280Modes_original_tx_gain_9280_2,
543 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
547 static int ath9k_hw_post_init(struct ath_hw *ah)
551 if (!ath9k_hw_chip_test(ah))
554 ecode = ath9k_hw_rf_claim(ah);
558 ecode = ath9k_hw_eeprom_init(ah);
562 DPRINTF(ah, ATH_DBG_CONFIG, "Eeprom VER: %d, REV: %d\n",
563 ah->eep_ops->get_eeprom_ver(ah), ah->eep_ops->get_eeprom_rev(ah));
565 ecode = ath9k_hw_rfattach(ah);
569 if (!AR_SREV_9100(ah)) {
570 ath9k_hw_ani_setup(ah);
571 ath9k_hw_ani_init(ah);
577 static bool ath9k_hw_devid_supported(u16 devid)
580 case AR5416_DEVID_PCI:
581 case AR5416_DEVID_PCIE:
582 case AR5416_AR9100_DEVID:
583 case AR9160_DEVID_PCI:
584 case AR9280_DEVID_PCI:
585 case AR9280_DEVID_PCIE:
586 case AR9285_DEVID_PCIE:
587 case AR5416_DEVID_AR9287_PCI:
588 case AR5416_DEVID_AR9287_PCIE:
596 static bool ath9k_hw_macversion_supported(u32 macversion)
598 switch (macversion) {
599 case AR_SREV_VERSION_5416_PCI:
600 case AR_SREV_VERSION_5416_PCIE:
601 case AR_SREV_VERSION_9160:
602 case AR_SREV_VERSION_9100:
603 case AR_SREV_VERSION_9280:
604 case AR_SREV_VERSION_9285:
605 case AR_SREV_VERSION_9287:
608 case AR_SREV_VERSION_9271:
615 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
617 if (AR_SREV_9160_10_OR_LATER(ah)) {
618 if (AR_SREV_9280_10_OR_LATER(ah)) {
619 ah->iq_caldata.calData = &iq_cal_single_sample;
620 ah->adcgain_caldata.calData =
621 &adc_gain_cal_single_sample;
622 ah->adcdc_caldata.calData =
623 &adc_dc_cal_single_sample;
624 ah->adcdc_calinitdata.calData =
627 ah->iq_caldata.calData = &iq_cal_multi_sample;
628 ah->adcgain_caldata.calData =
629 &adc_gain_cal_multi_sample;
630 ah->adcdc_caldata.calData =
631 &adc_dc_cal_multi_sample;
632 ah->adcdc_calinitdata.calData =
635 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
639 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
641 if (AR_SREV_9271(ah)) {
642 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271_1_0,
643 ARRAY_SIZE(ar9271Modes_9271_1_0), 6);
644 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271_1_0,
645 ARRAY_SIZE(ar9271Common_9271_1_0), 2);
649 if (AR_SREV_9287_11_OR_LATER(ah)) {
650 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
651 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
652 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
653 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
654 if (ah->config.pcie_clock_req)
655 INIT_INI_ARRAY(&ah->iniPcieSerdes,
656 ar9287PciePhy_clkreq_off_L1_9287_1_1,
657 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
659 INIT_INI_ARRAY(&ah->iniPcieSerdes,
660 ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
661 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
663 } else if (AR_SREV_9287_10_OR_LATER(ah)) {
664 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
665 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
666 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
667 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
669 if (ah->config.pcie_clock_req)
670 INIT_INI_ARRAY(&ah->iniPcieSerdes,
671 ar9287PciePhy_clkreq_off_L1_9287_1_0,
672 ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
674 INIT_INI_ARRAY(&ah->iniPcieSerdes,
675 ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
676 ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
678 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
681 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
682 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
683 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
684 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
686 if (ah->config.pcie_clock_req) {
687 INIT_INI_ARRAY(&ah->iniPcieSerdes,
688 ar9285PciePhy_clkreq_off_L1_9285_1_2,
689 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
691 INIT_INI_ARRAY(&ah->iniPcieSerdes,
692 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
693 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
696 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
697 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
698 ARRAY_SIZE(ar9285Modes_9285), 6);
699 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
700 ARRAY_SIZE(ar9285Common_9285), 2);
702 if (ah->config.pcie_clock_req) {
703 INIT_INI_ARRAY(&ah->iniPcieSerdes,
704 ar9285PciePhy_clkreq_off_L1_9285,
705 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
707 INIT_INI_ARRAY(&ah->iniPcieSerdes,
708 ar9285PciePhy_clkreq_always_on_L1_9285,
709 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
711 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
712 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
713 ARRAY_SIZE(ar9280Modes_9280_2), 6);
714 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
715 ARRAY_SIZE(ar9280Common_9280_2), 2);
717 if (ah->config.pcie_clock_req) {
718 INIT_INI_ARRAY(&ah->iniPcieSerdes,
719 ar9280PciePhy_clkreq_off_L1_9280,
720 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
722 INIT_INI_ARRAY(&ah->iniPcieSerdes,
723 ar9280PciePhy_clkreq_always_on_L1_9280,
724 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
726 INIT_INI_ARRAY(&ah->iniModesAdditional,
727 ar9280Modes_fast_clock_9280_2,
728 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
729 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
730 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
731 ARRAY_SIZE(ar9280Modes_9280), 6);
732 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
733 ARRAY_SIZE(ar9280Common_9280), 2);
734 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
735 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
736 ARRAY_SIZE(ar5416Modes_9160), 6);
737 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
738 ARRAY_SIZE(ar5416Common_9160), 2);
739 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
740 ARRAY_SIZE(ar5416Bank0_9160), 2);
741 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
742 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
743 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
744 ARRAY_SIZE(ar5416Bank1_9160), 2);
745 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
746 ARRAY_SIZE(ar5416Bank2_9160), 2);
747 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
748 ARRAY_SIZE(ar5416Bank3_9160), 3);
749 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
750 ARRAY_SIZE(ar5416Bank6_9160), 3);
751 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
752 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
753 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
754 ARRAY_SIZE(ar5416Bank7_9160), 2);
755 if (AR_SREV_9160_11(ah)) {
756 INIT_INI_ARRAY(&ah->iniAddac,
758 ARRAY_SIZE(ar5416Addac_91601_1), 2);
760 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
761 ARRAY_SIZE(ar5416Addac_9160), 2);
763 } else if (AR_SREV_9100_OR_LATER(ah)) {
764 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
765 ARRAY_SIZE(ar5416Modes_9100), 6);
766 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
767 ARRAY_SIZE(ar5416Common_9100), 2);
768 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
769 ARRAY_SIZE(ar5416Bank0_9100), 2);
770 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
771 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
772 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
773 ARRAY_SIZE(ar5416Bank1_9100), 2);
774 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
775 ARRAY_SIZE(ar5416Bank2_9100), 2);
776 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
777 ARRAY_SIZE(ar5416Bank3_9100), 3);
778 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
779 ARRAY_SIZE(ar5416Bank6_9100), 3);
780 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
781 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
782 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
783 ARRAY_SIZE(ar5416Bank7_9100), 2);
784 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
785 ARRAY_SIZE(ar5416Addac_9100), 2);
787 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
788 ARRAY_SIZE(ar5416Modes), 6);
789 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
790 ARRAY_SIZE(ar5416Common), 2);
791 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
792 ARRAY_SIZE(ar5416Bank0), 2);
793 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
794 ARRAY_SIZE(ar5416BB_RfGain), 3);
795 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
796 ARRAY_SIZE(ar5416Bank1), 2);
797 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
798 ARRAY_SIZE(ar5416Bank2), 2);
799 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
800 ARRAY_SIZE(ar5416Bank3), 3);
801 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
802 ARRAY_SIZE(ar5416Bank6), 3);
803 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
804 ARRAY_SIZE(ar5416Bank6TPC), 3);
805 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
806 ARRAY_SIZE(ar5416Bank7), 2);
807 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
808 ARRAY_SIZE(ar5416Addac), 2);
812 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
814 if (AR_SREV_9287_11_OR_LATER(ah))
815 INIT_INI_ARRAY(&ah->iniModesRxGain,
816 ar9287Modes_rx_gain_9287_1_1,
817 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
818 else if (AR_SREV_9287_10(ah))
819 INIT_INI_ARRAY(&ah->iniModesRxGain,
820 ar9287Modes_rx_gain_9287_1_0,
821 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
822 else if (AR_SREV_9280_20(ah))
823 ath9k_hw_init_rxgain_ini(ah);
825 if (AR_SREV_9287_11_OR_LATER(ah)) {
826 INIT_INI_ARRAY(&ah->iniModesTxGain,
827 ar9287Modes_tx_gain_9287_1_1,
828 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
829 } else if (AR_SREV_9287_10(ah)) {
830 INIT_INI_ARRAY(&ah->iniModesTxGain,
831 ar9287Modes_tx_gain_9287_1_0,
832 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
833 } else if (AR_SREV_9280_20(ah)) {
834 ath9k_hw_init_txgain_ini(ah);
835 } else if (AR_SREV_9285_12_OR_LATER(ah)) {
836 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
839 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
840 INIT_INI_ARRAY(&ah->iniModesTxGain,
841 ar9285Modes_high_power_tx_gain_9285_1_2,
842 ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
844 INIT_INI_ARRAY(&ah->iniModesTxGain,
845 ar9285Modes_original_tx_gain_9285_1_2,
846 ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
852 static void ath9k_hw_init_11a_eeprom_fix(struct ath_hw *ah)
856 if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
857 test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
860 for (i = 0; i < ah->iniModes.ia_rows; i++) {
861 u32 reg = INI_RA(&ah->iniModes, i, 0);
863 for (j = 1; j < ah->iniModes.ia_columns; j++) {
864 u32 val = INI_RA(&ah->iniModes, i, j);
866 INI_RA(&ah->iniModes, i, j) =
867 ath9k_hw_ini_fixup(ah,
875 int ath9k_hw_init(struct ath_hw *ah)
879 if (!ath9k_hw_devid_supported(ah->hw_version.devid))
882 ath9k_hw_init_defaults(ah);
883 ath9k_hw_init_config(ah);
885 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
886 DPRINTF(ah, ATH_DBG_FATAL, "Couldn't reset chip\n");
890 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
891 DPRINTF(ah, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
895 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
896 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
897 (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
898 ah->config.serialize_regmode =
901 ah->config.serialize_regmode =
906 DPRINTF(ah, ATH_DBG_RESET, "serialize_regmode is %d\n",
907 ah->config.serialize_regmode);
909 if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
910 DPRINTF(ah, ATH_DBG_FATAL,
911 "Mac Chip Rev 0x%02x.%x is not supported by "
912 "this driver\n", ah->hw_version.macVersion,
913 ah->hw_version.macRev);
917 if (AR_SREV_9100(ah)) {
918 ah->iq_caldata.calData = &iq_cal_multi_sample;
919 ah->supp_cals = IQ_MISMATCH_CAL;
920 ah->is_pciexpress = false;
923 if (AR_SREV_9271(ah))
924 ah->is_pciexpress = false;
926 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
928 ath9k_hw_init_cal_settings(ah);
930 ah->ani_function = ATH9K_ANI_ALL;
931 if (AR_SREV_9280_10_OR_LATER(ah))
932 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
934 ath9k_hw_init_mode_regs(ah);
936 if (ah->is_pciexpress)
937 ath9k_hw_configpcipowersave(ah, 0, 0);
939 ath9k_hw_disablepcie(ah);
941 r = ath9k_hw_post_init(ah);
945 ath9k_hw_init_mode_gain_regs(ah);
946 ath9k_hw_fill_cap_info(ah);
947 ath9k_hw_init_11a_eeprom_fix(ah);
949 r = ath9k_hw_init_macaddr(ah);
951 DPRINTF(ah, ATH_DBG_FATAL,
952 "Failed to initialize MAC address\n");
956 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
957 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
959 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
961 ath9k_init_nfcal_hist_buffer(ah);
966 static void ath9k_hw_init_bb(struct ath_hw *ah,
967 struct ath9k_channel *chan)
971 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
973 synthDelay = (4 * synthDelay) / 22;
977 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
979 udelay(synthDelay + BASE_ACTIVATE_DELAY);
982 static void ath9k_hw_init_qos(struct ath_hw *ah)
984 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
985 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
987 REG_WRITE(ah, AR_QOS_NO_ACK,
988 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
989 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
990 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
992 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
993 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
994 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
995 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
996 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
999 static void ath9k_hw_init_pll(struct ath_hw *ah,
1000 struct ath9k_channel *chan)
1004 if (AR_SREV_9100(ah)) {
1005 if (chan && IS_CHAN_5GHZ(chan))
1010 if (AR_SREV_9280_10_OR_LATER(ah)) {
1011 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1013 if (chan && IS_CHAN_HALF_RATE(chan))
1014 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1015 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1016 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1018 if (chan && IS_CHAN_5GHZ(chan)) {
1019 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1022 if (AR_SREV_9280_20(ah)) {
1023 if (((chan->channel % 20) == 0)
1024 || ((chan->channel % 10) == 0))
1030 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1033 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1035 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1037 if (chan && IS_CHAN_HALF_RATE(chan))
1038 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1039 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1040 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1042 if (chan && IS_CHAN_5GHZ(chan))
1043 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1045 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1047 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1049 if (chan && IS_CHAN_HALF_RATE(chan))
1050 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1051 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1052 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1054 if (chan && IS_CHAN_5GHZ(chan))
1055 pll |= SM(0xa, AR_RTC_PLL_DIV);
1057 pll |= SM(0xb, AR_RTC_PLL_DIV);
1060 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1062 udelay(RTC_PLL_SETTLE_DELAY);
1064 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1067 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1069 int rx_chainmask, tx_chainmask;
1071 rx_chainmask = ah->rxchainmask;
1072 tx_chainmask = ah->txchainmask;
1074 switch (rx_chainmask) {
1076 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1077 AR_PHY_SWAP_ALT_CHAIN);
1079 if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) {
1080 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1081 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1087 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1088 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1094 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1095 if (tx_chainmask == 0x5) {
1096 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1097 AR_PHY_SWAP_ALT_CHAIN);
1099 if (AR_SREV_9100(ah))
1100 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1101 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1104 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1105 enum nl80211_iftype opmode)
1107 ah->mask_reg = AR_IMR_TXERR |
1113 if (ah->config.intr_mitigation)
1114 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1116 ah->mask_reg |= AR_IMR_RXOK;
1118 ah->mask_reg |= AR_IMR_TXOK;
1120 if (opmode == NL80211_IFTYPE_AP)
1121 ah->mask_reg |= AR_IMR_MIB;
1123 REG_WRITE(ah, AR_IMR, ah->mask_reg);
1124 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1126 if (!AR_SREV_9100(ah)) {
1127 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1128 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1129 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1133 static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1135 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1136 DPRINTF(ah, ATH_DBG_RESET, "bad ack timeout %u\n", us);
1137 ah->acktimeout = (u32) -1;
1140 REG_RMW_FIELD(ah, AR_TIME_OUT,
1141 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1142 ah->acktimeout = us;
1147 static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1149 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1150 DPRINTF(ah, ATH_DBG_RESET, "bad cts timeout %u\n", us);
1151 ah->ctstimeout = (u32) -1;
1154 REG_RMW_FIELD(ah, AR_TIME_OUT,
1155 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1156 ah->ctstimeout = us;
1161 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1164 DPRINTF(ah, ATH_DBG_XMIT,
1165 "bad global tx timeout %u\n", tu);
1166 ah->globaltxtimeout = (u32) -1;
1169 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1170 ah->globaltxtimeout = tu;
1175 static void ath9k_hw_init_user_settings(struct ath_hw *ah)
1177 DPRINTF(ah, ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1180 if (ah->misc_mode != 0)
1181 REG_WRITE(ah, AR_PCU_MISC,
1182 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1183 if (ah->slottime != (u32) -1)
1184 ath9k_hw_setslottime(ah, ah->slottime);
1185 if (ah->acktimeout != (u32) -1)
1186 ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
1187 if (ah->ctstimeout != (u32) -1)
1188 ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
1189 if (ah->globaltxtimeout != (u32) -1)
1190 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1193 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1195 return vendorid == ATHEROS_VENDOR_ID ?
1196 ath9k_hw_devname(devid) : NULL;
1199 void ath9k_hw_detach(struct ath_hw *ah)
1201 if (!AR_SREV_9100(ah))
1202 ath9k_hw_ani_disable(ah);
1204 ath9k_hw_rf_free(ah);
1205 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1214 static void ath9k_hw_override_ini(struct ath_hw *ah,
1215 struct ath9k_channel *chan)
1219 if (AR_SREV_9271(ah)) {
1221 * Enable spectral scan to solution for issues with stuck
1222 * beacons on AR9271 1.0. The beacon stuck issue is not seeon on
1225 if (AR_SREV_9271_10(ah)) {
1226 val = REG_READ(ah, AR_PHY_SPECTRAL_SCAN) | AR_PHY_SPECTRAL_SCAN_ENABLE;
1227 REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val);
1229 else if (AR_SREV_9271_11(ah))
1231 * change AR_PHY_RF_CTL3 setting to fix MAC issue
1232 * present on AR9271 1.1
1234 REG_WRITE(ah, AR_PHY_RF_CTL3, 0x3a020001);
1239 * Set the RX_ABORT and RX_DIS and clear if off only after
1240 * RXE is set for MAC. This prevents frames with corrupted
1241 * descriptor status.
1243 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1245 if (AR_SREV_9280_10_OR_LATER(ah)) {
1246 val = REG_READ(ah, AR_PCU_MISC_MODE2) &
1247 (~AR_PCU_MISC_MODE2_HWWAR1);
1249 if (AR_SREV_9287_10_OR_LATER(ah))
1250 val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
1252 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
1255 if (!AR_SREV_5416_20_OR_LATER(ah) ||
1256 AR_SREV_9280_10_OR_LATER(ah))
1259 * Disable BB clock gating
1260 * Necessary to avoid issues on AR5416 2.0
1262 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1265 static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1266 struct ar5416_eeprom_def *pEepData,
1269 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1271 switch (ah->hw_version.devid) {
1272 case AR9280_DEVID_PCI:
1273 if (reg == 0x7894) {
1274 DPRINTF(ah, ATH_DBG_EEPROM,
1275 "ini VAL: %x EEPROM: %x\n", value,
1276 (pBase->version & 0xff));
1278 if ((pBase->version & 0xff) > 0x0a) {
1279 DPRINTF(ah, ATH_DBG_EEPROM,
1282 value &= ~AR_AN_TOP2_PWDCLKIND;
1283 value |= AR_AN_TOP2_PWDCLKIND &
1284 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1286 DPRINTF(ah, ATH_DBG_EEPROM,
1287 "PWDCLKIND Earlier Rev\n");
1290 DPRINTF(ah, ATH_DBG_EEPROM,
1291 "final ini VAL: %x\n", value);
1299 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1300 struct ar5416_eeprom_def *pEepData,
1303 if (ah->eep_map == EEP_MAP_4KBITS)
1306 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1309 static void ath9k_olc_init(struct ath_hw *ah)
1313 if (OLC_FOR_AR9287_10_LATER) {
1314 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
1315 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
1316 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
1317 AR9287_AN_TXPC0_TXPCMODE,
1318 AR9287_AN_TXPC0_TXPCMODE_S,
1319 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
1322 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1323 ah->originalGain[i] =
1324 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1330 static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1331 struct ath9k_channel *chan)
1333 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1335 if (IS_CHAN_B(chan))
1337 else if (IS_CHAN_G(chan))
1345 static int ath9k_hw_process_ini(struct ath_hw *ah,
1346 struct ath9k_channel *chan,
1347 enum ath9k_ht_macmode macmode)
1349 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1350 int i, regWrites = 0;
1351 struct ieee80211_channel *channel = chan->chan;
1352 u32 modesIndex, freqIndex;
1354 switch (chan->chanmode) {
1356 case CHANNEL_A_HT20:
1360 case CHANNEL_A_HT40PLUS:
1361 case CHANNEL_A_HT40MINUS:
1366 case CHANNEL_G_HT20:
1371 case CHANNEL_G_HT40PLUS:
1372 case CHANNEL_G_HT40MINUS:
1381 REG_WRITE(ah, AR_PHY(0), 0x00000007);
1382 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1383 ah->eep_ops->set_addac(ah, chan);
1385 if (AR_SREV_5416_22_OR_LATER(ah)) {
1386 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1388 struct ar5416IniArray temp;
1390 sizeof(u32) * ah->iniAddac.ia_rows *
1391 ah->iniAddac.ia_columns;
1393 memcpy(ah->addac5416_21,
1394 ah->iniAddac.ia_array, addacSize);
1396 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1398 temp.ia_array = ah->addac5416_21;
1399 temp.ia_columns = ah->iniAddac.ia_columns;
1400 temp.ia_rows = ah->iniAddac.ia_rows;
1401 REG_WRITE_ARRAY(&temp, 1, regWrites);
1404 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1406 for (i = 0; i < ah->iniModes.ia_rows; i++) {
1407 u32 reg = INI_RA(&ah->iniModes, i, 0);
1408 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1410 REG_WRITE(ah, reg, val);
1412 if (reg >= 0x7800 && reg < 0x78a0
1413 && ah->config.analog_shiftreg) {
1417 DO_DELAY(regWrites);
1420 if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
1421 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1423 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1424 AR_SREV_9287_10_OR_LATER(ah))
1425 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1427 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1428 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1429 u32 val = INI_RA(&ah->iniCommon, i, 1);
1431 REG_WRITE(ah, reg, val);
1433 if (reg >= 0x7800 && reg < 0x78a0
1434 && ah->config.analog_shiftreg) {
1438 DO_DELAY(regWrites);
1441 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1443 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1444 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1448 ath9k_hw_override_ini(ah, chan);
1449 ath9k_hw_set_regs(ah, chan, macmode);
1450 ath9k_hw_init_chain_masks(ah);
1452 if (OLC_FOR_AR9280_20_LATER)
1455 ah->eep_ops->set_txpower(ah, chan,
1456 ath9k_regd_get_ctl(regulatory, chan),
1457 channel->max_antenna_gain * 2,
1458 channel->max_power * 2,
1459 min((u32) MAX_RATE_POWER,
1460 (u32) regulatory->power_limit));
1462 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1463 DPRINTF(ah, ATH_DBG_FATAL,
1464 "ar5416SetRfRegs failed\n");
1471 /****************************************/
1472 /* Reset and Channel Switching Routines */
1473 /****************************************/
1475 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1482 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1483 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1485 if (!AR_SREV_9280_10_OR_LATER(ah))
1486 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1487 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1489 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1490 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1492 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1495 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1497 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1500 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1505 * set AHB_MODE not to do cacheline prefetches
1507 regval = REG_READ(ah, AR_AHB_MODE);
1508 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1511 * let mac dma reads be in 128 byte chunks
1513 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1514 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1517 * Restore TX Trigger Level to its pre-reset value.
1518 * The initial value depends on whether aggregation is enabled, and is
1519 * adjusted whenever underruns are detected.
1521 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1524 * let mac dma writes be in 128 byte chunks
1526 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1527 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1530 * Setup receive FIFO threshold to hold off TX activities
1532 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1535 * reduce the number of usable entries in PCU TXBUF to avoid
1536 * wrap around issues.
1538 if (AR_SREV_9285(ah)) {
1539 /* For AR9285 the number of Fifos are reduced to half.
1540 * So set the usable tx buf size also to half to
1541 * avoid data/delimiter underruns
1543 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1544 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1545 } else if (!AR_SREV_9271(ah)) {
1546 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1547 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1551 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1555 val = REG_READ(ah, AR_STA_ID1);
1556 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1558 case NL80211_IFTYPE_AP:
1559 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1560 | AR_STA_ID1_KSRCH_MODE);
1561 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1563 case NL80211_IFTYPE_ADHOC:
1564 case NL80211_IFTYPE_MESH_POINT:
1565 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1566 | AR_STA_ID1_KSRCH_MODE);
1567 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1569 case NL80211_IFTYPE_STATION:
1570 case NL80211_IFTYPE_MONITOR:
1571 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1576 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1581 u32 coef_exp, coef_man;
1583 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1584 if ((coef_scaled >> coef_exp) & 0x1)
1587 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1589 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1591 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1592 *coef_exponent = coef_exp - 16;
1595 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1596 struct ath9k_channel *chan)
1598 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1599 u32 clockMhzScaled = 0x64000000;
1600 struct chan_centers centers;
1602 if (IS_CHAN_HALF_RATE(chan))
1603 clockMhzScaled = clockMhzScaled >> 1;
1604 else if (IS_CHAN_QUARTER_RATE(chan))
1605 clockMhzScaled = clockMhzScaled >> 2;
1607 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
1608 coef_scaled = clockMhzScaled / centers.synth_center;
1610 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1613 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1614 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1615 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1616 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1618 coef_scaled = (9 * coef_scaled) / 10;
1620 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1623 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1624 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1625 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1626 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1629 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1634 if (AR_SREV_9100(ah)) {
1635 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1636 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1637 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1638 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1639 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1642 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1643 AR_RTC_FORCE_WAKE_ON_INT);
1645 if (AR_SREV_9100(ah)) {
1646 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1647 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1649 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1651 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1652 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1653 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1654 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1656 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1659 rst_flags = AR_RTC_RC_MAC_WARM;
1660 if (type == ATH9K_RESET_COLD)
1661 rst_flags |= AR_RTC_RC_MAC_COLD;
1664 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1667 REG_WRITE(ah, AR_RTC_RC, 0);
1668 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1669 DPRINTF(ah, ATH_DBG_RESET,
1670 "RTC stuck in MAC reset\n");
1674 if (!AR_SREV_9100(ah))
1675 REG_WRITE(ah, AR_RC, 0);
1677 ath9k_hw_init_pll(ah, NULL);
1679 if (AR_SREV_9100(ah))
1685 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1687 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1688 AR_RTC_FORCE_WAKE_ON_INT);
1690 if (!AR_SREV_9100(ah))
1691 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1693 REG_WRITE(ah, AR_RTC_RESET, 0);
1696 if (!AR_SREV_9100(ah))
1697 REG_WRITE(ah, AR_RC, 0);
1699 REG_WRITE(ah, AR_RTC_RESET, 1);
1701 if (!ath9k_hw_wait(ah,
1706 DPRINTF(ah, ATH_DBG_RESET, "RTC not waking up\n");
1710 ath9k_hw_read_revisions(ah);
1712 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1715 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1717 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1718 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1721 case ATH9K_RESET_POWER_ON:
1722 return ath9k_hw_set_reset_power_on(ah);
1723 case ATH9K_RESET_WARM:
1724 case ATH9K_RESET_COLD:
1725 return ath9k_hw_set_reset(ah, type);
1731 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
1732 enum ath9k_ht_macmode macmode)
1735 u32 enableDacFifo = 0;
1737 if (AR_SREV_9285_10_OR_LATER(ah))
1738 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1739 AR_PHY_FC_ENABLE_DAC_FIFO);
1741 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1742 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1744 if (IS_CHAN_HT40(chan)) {
1745 phymode |= AR_PHY_FC_DYN2040_EN;
1747 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1748 (chan->chanmode == CHANNEL_G_HT40PLUS))
1749 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1751 if (ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1752 phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1754 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1756 ath9k_hw_set11nmac2040(ah, macmode);
1758 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1759 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1762 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1763 struct ath9k_channel *chan)
1765 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1766 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1768 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1771 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1774 ah->chip_fullsleep = false;
1775 ath9k_hw_init_pll(ah, chan);
1776 ath9k_hw_set_rfmode(ah, chan);
1781 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1782 struct ath9k_channel *chan,
1783 enum ath9k_ht_macmode macmode)
1785 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1786 struct ieee80211_channel *channel = chan->chan;
1787 u32 synthDelay, qnum;
1789 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1790 if (ath9k_hw_numtxpending(ah, qnum)) {
1791 DPRINTF(ah, ATH_DBG_QUEUE,
1792 "Transmit frames pending on queue %d\n", qnum);
1797 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1798 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1799 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1800 DPRINTF(ah, ATH_DBG_FATAL,
1801 "Could not kill baseband RX\n");
1805 ath9k_hw_set_regs(ah, chan, macmode);
1807 if (AR_SREV_9280_10_OR_LATER(ah)) {
1808 ath9k_hw_ar9280_set_channel(ah, chan);
1810 if (!(ath9k_hw_set_channel(ah, chan))) {
1811 DPRINTF(ah, ATH_DBG_FATAL,
1812 "Failed to set channel\n");
1817 ah->eep_ops->set_txpower(ah, chan,
1818 ath9k_regd_get_ctl(regulatory, chan),
1819 channel->max_antenna_gain * 2,
1820 channel->max_power * 2,
1821 min((u32) MAX_RATE_POWER,
1822 (u32) regulatory->power_limit));
1824 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1825 if (IS_CHAN_B(chan))
1826 synthDelay = (4 * synthDelay) / 22;
1830 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1832 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1834 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1835 ath9k_hw_set_delta_slope(ah, chan);
1837 if (AR_SREV_9280_10_OR_LATER(ah))
1838 ath9k_hw_9280_spur_mitigate(ah, chan);
1840 ath9k_hw_spur_mitigate(ah, chan);
1842 if (!chan->oneTimeCalsDone)
1843 chan->oneTimeCalsDone = true;
1848 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1850 int bb_spur = AR_NO_SPUR;
1853 int bb_spur_off, spur_subchannel_sd;
1855 int spur_delta_phase;
1857 int upper, lower, cur_vit_mask;
1860 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1861 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1863 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1864 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1866 int inc[4] = { 0, 100, 0, 0 };
1867 struct chan_centers centers;
1874 bool is2GHz = IS_CHAN_2GHZ(chan);
1876 memset(&mask_m, 0, sizeof(int8_t) * 123);
1877 memset(&mask_p, 0, sizeof(int8_t) * 123);
1879 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
1880 freq = centers.synth_center;
1882 ah->config.spurmode = SPUR_ENABLE_EEPROM;
1883 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1884 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1887 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1889 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1891 if (AR_NO_SPUR == cur_bb_spur)
1893 cur_bb_spur = cur_bb_spur - freq;
1895 if (IS_CHAN_HT40(chan)) {
1896 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1897 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1898 bb_spur = cur_bb_spur;
1901 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1902 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1903 bb_spur = cur_bb_spur;
1908 if (AR_NO_SPUR == bb_spur) {
1909 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1910 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1913 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1914 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1917 bin = bb_spur * 320;
1919 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1921 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1922 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1923 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1924 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1925 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1927 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1928 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1929 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1930 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1931 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1932 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1934 if (IS_CHAN_HT40(chan)) {
1936 spur_subchannel_sd = 1;
1937 bb_spur_off = bb_spur + 10;
1939 spur_subchannel_sd = 0;
1940 bb_spur_off = bb_spur - 10;
1943 spur_subchannel_sd = 0;
1944 bb_spur_off = bb_spur;
1947 if (IS_CHAN_HT40(chan))
1949 ((bb_spur * 262144) /
1950 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1953 ((bb_spur * 524288) /
1954 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1956 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1957 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1959 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1960 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1961 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1962 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1964 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1965 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1971 for (i = 0; i < 4; i++) {
1975 for (bp = 0; bp < 30; bp++) {
1976 if ((cur_bin > lower) && (cur_bin < upper)) {
1977 pilot_mask = pilot_mask | 0x1 << bp;
1978 chan_mask = chan_mask | 0x1 << bp;
1983 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1984 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1987 cur_vit_mask = 6100;
1991 for (i = 0; i < 123; i++) {
1992 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1994 /* workaround for gcc bug #37014 */
1995 volatile int tmp_v = abs(cur_vit_mask - bin);
2001 if (cur_vit_mask < 0)
2002 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2004 mask_p[cur_vit_mask / 100] = mask_amt;
2006 cur_vit_mask -= 100;
2009 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2010 | (mask_m[48] << 26) | (mask_m[49] << 24)
2011 | (mask_m[50] << 22) | (mask_m[51] << 20)
2012 | (mask_m[52] << 18) | (mask_m[53] << 16)
2013 | (mask_m[54] << 14) | (mask_m[55] << 12)
2014 | (mask_m[56] << 10) | (mask_m[57] << 8)
2015 | (mask_m[58] << 6) | (mask_m[59] << 4)
2016 | (mask_m[60] << 2) | (mask_m[61] << 0);
2017 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2018 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2020 tmp_mask = (mask_m[31] << 28)
2021 | (mask_m[32] << 26) | (mask_m[33] << 24)
2022 | (mask_m[34] << 22) | (mask_m[35] << 20)
2023 | (mask_m[36] << 18) | (mask_m[37] << 16)
2024 | (mask_m[48] << 14) | (mask_m[39] << 12)
2025 | (mask_m[40] << 10) | (mask_m[41] << 8)
2026 | (mask_m[42] << 6) | (mask_m[43] << 4)
2027 | (mask_m[44] << 2) | (mask_m[45] << 0);
2028 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2029 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2031 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2032 | (mask_m[18] << 26) | (mask_m[18] << 24)
2033 | (mask_m[20] << 22) | (mask_m[20] << 20)
2034 | (mask_m[22] << 18) | (mask_m[22] << 16)
2035 | (mask_m[24] << 14) | (mask_m[24] << 12)
2036 | (mask_m[25] << 10) | (mask_m[26] << 8)
2037 | (mask_m[27] << 6) | (mask_m[28] << 4)
2038 | (mask_m[29] << 2) | (mask_m[30] << 0);
2039 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2040 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2042 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2043 | (mask_m[2] << 26) | (mask_m[3] << 24)
2044 | (mask_m[4] << 22) | (mask_m[5] << 20)
2045 | (mask_m[6] << 18) | (mask_m[7] << 16)
2046 | (mask_m[8] << 14) | (mask_m[9] << 12)
2047 | (mask_m[10] << 10) | (mask_m[11] << 8)
2048 | (mask_m[12] << 6) | (mask_m[13] << 4)
2049 | (mask_m[14] << 2) | (mask_m[15] << 0);
2050 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2051 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2053 tmp_mask = (mask_p[15] << 28)
2054 | (mask_p[14] << 26) | (mask_p[13] << 24)
2055 | (mask_p[12] << 22) | (mask_p[11] << 20)
2056 | (mask_p[10] << 18) | (mask_p[9] << 16)
2057 | (mask_p[8] << 14) | (mask_p[7] << 12)
2058 | (mask_p[6] << 10) | (mask_p[5] << 8)
2059 | (mask_p[4] << 6) | (mask_p[3] << 4)
2060 | (mask_p[2] << 2) | (mask_p[1] << 0);
2061 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2062 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2064 tmp_mask = (mask_p[30] << 28)
2065 | (mask_p[29] << 26) | (mask_p[28] << 24)
2066 | (mask_p[27] << 22) | (mask_p[26] << 20)
2067 | (mask_p[25] << 18) | (mask_p[24] << 16)
2068 | (mask_p[23] << 14) | (mask_p[22] << 12)
2069 | (mask_p[21] << 10) | (mask_p[20] << 8)
2070 | (mask_p[19] << 6) | (mask_p[18] << 4)
2071 | (mask_p[17] << 2) | (mask_p[16] << 0);
2072 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2073 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2075 tmp_mask = (mask_p[45] << 28)
2076 | (mask_p[44] << 26) | (mask_p[43] << 24)
2077 | (mask_p[42] << 22) | (mask_p[41] << 20)
2078 | (mask_p[40] << 18) | (mask_p[39] << 16)
2079 | (mask_p[38] << 14) | (mask_p[37] << 12)
2080 | (mask_p[36] << 10) | (mask_p[35] << 8)
2081 | (mask_p[34] << 6) | (mask_p[33] << 4)
2082 | (mask_p[32] << 2) | (mask_p[31] << 0);
2083 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2084 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2086 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2087 | (mask_p[59] << 26) | (mask_p[58] << 24)
2088 | (mask_p[57] << 22) | (mask_p[56] << 20)
2089 | (mask_p[55] << 18) | (mask_p[54] << 16)
2090 | (mask_p[53] << 14) | (mask_p[52] << 12)
2091 | (mask_p[51] << 10) | (mask_p[50] << 8)
2092 | (mask_p[49] << 6) | (mask_p[48] << 4)
2093 | (mask_p[47] << 2) | (mask_p[46] << 0);
2094 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2095 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2098 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
2100 int bb_spur = AR_NO_SPUR;
2103 int spur_delta_phase;
2105 int upper, lower, cur_vit_mask;
2108 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
2109 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
2111 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
2112 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
2114 int inc[4] = { 0, 100, 0, 0 };
2121 bool is2GHz = IS_CHAN_2GHZ(chan);
2123 memset(&mask_m, 0, sizeof(int8_t) * 123);
2124 memset(&mask_p, 0, sizeof(int8_t) * 123);
2126 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2127 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
2128 if (AR_NO_SPUR == cur_bb_spur)
2130 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2131 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2132 bb_spur = cur_bb_spur;
2137 if (AR_NO_SPUR == bb_spur)
2142 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2143 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2144 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2145 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2146 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2148 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2150 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2151 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2152 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2153 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2154 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2155 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2157 spur_delta_phase = ((bb_spur * 524288) / 100) &
2158 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2160 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2161 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2163 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2164 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2165 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2166 REG_WRITE(ah, AR_PHY_TIMING11, new);
2172 for (i = 0; i < 4; i++) {
2176 for (bp = 0; bp < 30; bp++) {
2177 if ((cur_bin > lower) && (cur_bin < upper)) {
2178 pilot_mask = pilot_mask | 0x1 << bp;
2179 chan_mask = chan_mask | 0x1 << bp;
2184 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2185 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2188 cur_vit_mask = 6100;
2192 for (i = 0; i < 123; i++) {
2193 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2195 /* workaround for gcc bug #37014 */
2196 volatile int tmp_v = abs(cur_vit_mask - bin);
2202 if (cur_vit_mask < 0)
2203 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2205 mask_p[cur_vit_mask / 100] = mask_amt;
2207 cur_vit_mask -= 100;
2210 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2211 | (mask_m[48] << 26) | (mask_m[49] << 24)
2212 | (mask_m[50] << 22) | (mask_m[51] << 20)
2213 | (mask_m[52] << 18) | (mask_m[53] << 16)
2214 | (mask_m[54] << 14) | (mask_m[55] << 12)
2215 | (mask_m[56] << 10) | (mask_m[57] << 8)
2216 | (mask_m[58] << 6) | (mask_m[59] << 4)
2217 | (mask_m[60] << 2) | (mask_m[61] << 0);
2218 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2219 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2221 tmp_mask = (mask_m[31] << 28)
2222 | (mask_m[32] << 26) | (mask_m[33] << 24)
2223 | (mask_m[34] << 22) | (mask_m[35] << 20)
2224 | (mask_m[36] << 18) | (mask_m[37] << 16)
2225 | (mask_m[48] << 14) | (mask_m[39] << 12)
2226 | (mask_m[40] << 10) | (mask_m[41] << 8)
2227 | (mask_m[42] << 6) | (mask_m[43] << 4)
2228 | (mask_m[44] << 2) | (mask_m[45] << 0);
2229 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2230 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2232 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2233 | (mask_m[18] << 26) | (mask_m[18] << 24)
2234 | (mask_m[20] << 22) | (mask_m[20] << 20)
2235 | (mask_m[22] << 18) | (mask_m[22] << 16)
2236 | (mask_m[24] << 14) | (mask_m[24] << 12)
2237 | (mask_m[25] << 10) | (mask_m[26] << 8)
2238 | (mask_m[27] << 6) | (mask_m[28] << 4)
2239 | (mask_m[29] << 2) | (mask_m[30] << 0);
2240 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2241 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2243 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2244 | (mask_m[2] << 26) | (mask_m[3] << 24)
2245 | (mask_m[4] << 22) | (mask_m[5] << 20)
2246 | (mask_m[6] << 18) | (mask_m[7] << 16)
2247 | (mask_m[8] << 14) | (mask_m[9] << 12)
2248 | (mask_m[10] << 10) | (mask_m[11] << 8)
2249 | (mask_m[12] << 6) | (mask_m[13] << 4)
2250 | (mask_m[14] << 2) | (mask_m[15] << 0);
2251 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2252 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2254 tmp_mask = (mask_p[15] << 28)
2255 | (mask_p[14] << 26) | (mask_p[13] << 24)
2256 | (mask_p[12] << 22) | (mask_p[11] << 20)
2257 | (mask_p[10] << 18) | (mask_p[9] << 16)
2258 | (mask_p[8] << 14) | (mask_p[7] << 12)
2259 | (mask_p[6] << 10) | (mask_p[5] << 8)
2260 | (mask_p[4] << 6) | (mask_p[3] << 4)
2261 | (mask_p[2] << 2) | (mask_p[1] << 0);
2262 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2263 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2265 tmp_mask = (mask_p[30] << 28)
2266 | (mask_p[29] << 26) | (mask_p[28] << 24)
2267 | (mask_p[27] << 22) | (mask_p[26] << 20)
2268 | (mask_p[25] << 18) | (mask_p[24] << 16)
2269 | (mask_p[23] << 14) | (mask_p[22] << 12)
2270 | (mask_p[21] << 10) | (mask_p[20] << 8)
2271 | (mask_p[19] << 6) | (mask_p[18] << 4)
2272 | (mask_p[17] << 2) | (mask_p[16] << 0);
2273 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2274 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2276 tmp_mask = (mask_p[45] << 28)
2277 | (mask_p[44] << 26) | (mask_p[43] << 24)
2278 | (mask_p[42] << 22) | (mask_p[41] << 20)
2279 | (mask_p[40] << 18) | (mask_p[39] << 16)
2280 | (mask_p[38] << 14) | (mask_p[37] << 12)
2281 | (mask_p[36] << 10) | (mask_p[35] << 8)
2282 | (mask_p[34] << 6) | (mask_p[33] << 4)
2283 | (mask_p[32] << 2) | (mask_p[31] << 0);
2284 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2285 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2287 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2288 | (mask_p[59] << 26) | (mask_p[58] << 24)
2289 | (mask_p[57] << 22) | (mask_p[56] << 20)
2290 | (mask_p[55] << 18) | (mask_p[54] << 16)
2291 | (mask_p[53] << 14) | (mask_p[52] << 12)
2292 | (mask_p[51] << 10) | (mask_p[50] << 8)
2293 | (mask_p[49] << 6) | (mask_p[48] << 4)
2294 | (mask_p[47] << 2) | (mask_p[46] << 0);
2295 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2296 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2299 static void ath9k_enable_rfkill(struct ath_hw *ah)
2301 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
2302 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
2304 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
2305 AR_GPIO_INPUT_MUX2_RFSILENT);
2307 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
2308 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
2311 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2312 bool bChannelChange)
2314 struct ath_common *common = ath9k_hw_common(ah);
2316 struct ath_softc *sc = ah->ah_sc;
2317 struct ath9k_channel *curchan = ah->curchan;
2321 int i, rx_chainmask, r;
2323 ah->extprotspacing = sc->ht_extprotspacing;
2324 ah->txchainmask = sc->tx_chainmask;
2325 ah->rxchainmask = sc->rx_chainmask;
2327 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2330 if (curchan && !ah->chip_fullsleep)
2331 ath9k_hw_getnf(ah, curchan);
2333 if (bChannelChange &&
2334 (ah->chip_fullsleep != true) &&
2335 (ah->curchan != NULL) &&
2336 (chan->channel != ah->curchan->channel) &&
2337 ((chan->channelFlags & CHANNEL_ALL) ==
2338 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
2339 !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
2340 IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
2342 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
2343 ath9k_hw_loadnf(ah, ah->curchan);
2344 ath9k_hw_start_nfcal(ah);
2349 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2350 if (saveDefAntenna == 0)
2353 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2355 /* For chips on which RTC reset is done, save TSF before it gets cleared */
2356 if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
2357 tsf = ath9k_hw_gettsf64(ah);
2359 saveLedState = REG_READ(ah, AR_CFG_LED) &
2360 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2361 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2363 ath9k_hw_mark_phy_inactive(ah);
2365 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
2367 AR9271_RESET_POWER_DOWN_CONTROL,
2368 AR9271_RADIO_RF_RST);
2372 if (!ath9k_hw_chip_reset(ah, chan)) {
2373 DPRINTF(ah, ATH_DBG_FATAL, "Chip reset failed\n");
2377 if (AR_SREV_9271(ah) && ah->htc_reset_init) {
2378 ah->htc_reset_init = false;
2380 AR9271_RESET_POWER_DOWN_CONTROL,
2381 AR9271_GATE_MAC_CTL);
2386 if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
2387 ath9k_hw_settsf64(ah, tsf);
2389 if (AR_SREV_9280_10_OR_LATER(ah))
2390 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
2392 if (AR_SREV_9287_12_OR_LATER(ah)) {
2393 /* Enable ASYNC FIFO */
2394 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2395 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
2396 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
2397 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2398 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2399 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2400 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2402 r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
2406 /* Setup MFP options for CCMP */
2407 if (AR_SREV_9280_20_OR_LATER(ah)) {
2408 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2409 * frames when constructing CCMP AAD. */
2410 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2412 ah->sw_mgmt_crypto = false;
2413 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2414 /* Disable hardware crypto for management frames */
2415 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2416 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2417 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2418 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2419 ah->sw_mgmt_crypto = true;
2421 ah->sw_mgmt_crypto = true;
2423 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2424 ath9k_hw_set_delta_slope(ah, chan);
2426 if (AR_SREV_9280_10_OR_LATER(ah))
2427 ath9k_hw_9280_spur_mitigate(ah, chan);
2429 ath9k_hw_spur_mitigate(ah, chan);
2431 ah->eep_ops->set_board_values(ah, chan);
2433 ath9k_hw_decrease_chain_power(ah, chan);
2435 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
2436 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
2438 | AR_STA_ID1_RTS_USE_DEF
2440 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2441 | ah->sta_id1_defaults);
2442 ath9k_hw_set_operating_mode(ah, ah->opmode);
2444 ath9k_hw_setbssidmask(ah);
2446 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2448 ath9k_hw_write_associd(ah);
2450 REG_WRITE(ah, AR_ISR, ~0);
2452 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2454 if (AR_SREV_9280_10_OR_LATER(ah))
2455 ath9k_hw_ar9280_set_channel(ah, chan);
2457 if (!(ath9k_hw_set_channel(ah, chan)))
2460 for (i = 0; i < AR_NUM_DCU; i++)
2461 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2464 for (i = 0; i < ah->caps.total_queues; i++)
2465 ath9k_hw_resettxqueue(ah, i);
2467 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2468 ath9k_hw_init_qos(ah);
2470 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2471 ath9k_enable_rfkill(ah);
2473 ath9k_hw_init_user_settings(ah);
2475 if (AR_SREV_9287_12_OR_LATER(ah)) {
2476 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
2477 AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
2478 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
2479 AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
2480 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
2481 AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
2483 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
2484 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
2486 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2487 AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2488 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2489 AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2491 if (AR_SREV_9287_12_OR_LATER(ah)) {
2492 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2493 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2496 REG_WRITE(ah, AR_STA_ID1,
2497 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2499 ath9k_hw_set_dma(ah);
2501 REG_WRITE(ah, AR_OBS, 8);
2503 if (ah->config.intr_mitigation) {
2504 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2505 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2508 ath9k_hw_init_bb(ah, chan);
2510 if (!ath9k_hw_init_cal(ah, chan))
2513 rx_chainmask = ah->rxchainmask;
2514 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2515 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2516 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2519 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2522 * For big endian systems turn on swapping for descriptors
2524 if (AR_SREV_9100(ah)) {
2526 mask = REG_READ(ah, AR_CFG);
2527 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2528 DPRINTF(ah, ATH_DBG_RESET,
2529 "CFG Byte Swap Set 0x%x\n", mask);
2532 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2533 REG_WRITE(ah, AR_CFG, mask);
2534 DPRINTF(ah, ATH_DBG_RESET,
2535 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2538 /* Configure AR9271 target WLAN */
2539 if (AR_SREV_9271(ah))
2540 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
2543 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2547 if (ah->btcoex_hw.enabled)
2548 ath9k_hw_btcoex_enable(ah);
2553 /************************/
2554 /* Key Cache Management */
2555 /************************/
2557 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2561 if (entry >= ah->caps.keycache_size) {
2562 DPRINTF(ah, ATH_DBG_FATAL,
2563 "keychache entry %u out of range\n", entry);
2567 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2569 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2570 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2571 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2572 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2573 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2574 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2575 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2576 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2578 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2579 u16 micentry = entry + 64;
2581 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2582 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2583 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2584 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2591 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2595 if (entry >= ah->caps.keycache_size) {
2596 DPRINTF(ah, ATH_DBG_FATAL,
2597 "keychache entry %u out of range\n", entry);
2602 macHi = (mac[5] << 8) | mac[4];
2603 macLo = (mac[3] << 24) |
2608 macLo |= (macHi & 1) << 31;
2613 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2614 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2619 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2620 const struct ath9k_keyval *k,
2623 const struct ath9k_hw_capabilities *pCap = &ah->caps;
2624 u32 key0, key1, key2, key3, key4;
2627 if (entry >= pCap->keycache_size) {
2628 DPRINTF(ah, ATH_DBG_FATAL,
2629 "keycache entry %u out of range\n", entry);
2633 switch (k->kv_type) {
2634 case ATH9K_CIPHER_AES_OCB:
2635 keyType = AR_KEYTABLE_TYPE_AES;
2637 case ATH9K_CIPHER_AES_CCM:
2638 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2639 DPRINTF(ah, ATH_DBG_ANY,
2640 "AES-CCM not supported by mac rev 0x%x\n",
2641 ah->hw_version.macRev);
2644 keyType = AR_KEYTABLE_TYPE_CCM;
2646 case ATH9K_CIPHER_TKIP:
2647 keyType = AR_KEYTABLE_TYPE_TKIP;
2648 if (ATH9K_IS_MIC_ENABLED(ah)
2649 && entry + 64 >= pCap->keycache_size) {
2650 DPRINTF(ah, ATH_DBG_ANY,
2651 "entry %u inappropriate for TKIP\n", entry);
2655 case ATH9K_CIPHER_WEP:
2656 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
2657 DPRINTF(ah, ATH_DBG_ANY,
2658 "WEP key length %u too small\n", k->kv_len);
2661 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
2662 keyType = AR_KEYTABLE_TYPE_40;
2663 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2664 keyType = AR_KEYTABLE_TYPE_104;
2666 keyType = AR_KEYTABLE_TYPE_128;
2668 case ATH9K_CIPHER_CLR:
2669 keyType = AR_KEYTABLE_TYPE_CLR;
2672 DPRINTF(ah, ATH_DBG_FATAL,
2673 "cipher %u not supported\n", k->kv_type);
2677 key0 = get_unaligned_le32(k->kv_val + 0);
2678 key1 = get_unaligned_le16(k->kv_val + 4);
2679 key2 = get_unaligned_le32(k->kv_val + 6);
2680 key3 = get_unaligned_le16(k->kv_val + 10);
2681 key4 = get_unaligned_le32(k->kv_val + 12);
2682 if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2686 * Note: Key cache registers access special memory area that requires
2687 * two 32-bit writes to actually update the values in the internal
2688 * memory. Consequently, the exact order and pairs used here must be
2692 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2693 u16 micentry = entry + 64;
2696 * Write inverted key[47:0] first to avoid Michael MIC errors
2697 * on frames that could be sent or received at the same time.
2698 * The correct key will be written in the end once everything
2701 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2702 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2704 /* Write key[95:48] */
2705 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2706 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2708 /* Write key[127:96] and key type */
2709 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2710 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2712 /* Write MAC address for the entry */
2713 (void) ath9k_hw_keysetmac(ah, entry, mac);
2715 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2717 * TKIP uses two key cache entries:
2718 * Michael MIC TX/RX keys in the same key cache entry
2719 * (idx = main index + 64):
2720 * key0 [31:0] = RX key [31:0]
2721 * key1 [15:0] = TX key [31:16]
2722 * key1 [31:16] = reserved
2723 * key2 [31:0] = RX key [63:32]
2724 * key3 [15:0] = TX key [15:0]
2725 * key3 [31:16] = reserved
2726 * key4 [31:0] = TX key [63:32]
2728 u32 mic0, mic1, mic2, mic3, mic4;
2730 mic0 = get_unaligned_le32(k->kv_mic + 0);
2731 mic2 = get_unaligned_le32(k->kv_mic + 4);
2732 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2733 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2734 mic4 = get_unaligned_le32(k->kv_txmic + 4);
2736 /* Write RX[31:0] and TX[31:16] */
2737 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2738 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2740 /* Write RX[63:32] and TX[15:0] */
2741 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2742 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2744 /* Write TX[63:32] and keyType(reserved) */
2745 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2746 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2747 AR_KEYTABLE_TYPE_CLR);
2751 * TKIP uses four key cache entries (two for group
2753 * Michael MIC TX/RX keys are in different key cache
2754 * entries (idx = main index + 64 for TX and
2755 * main index + 32 + 96 for RX):
2756 * key0 [31:0] = TX/RX MIC key [31:0]
2757 * key1 [31:0] = reserved
2758 * key2 [31:0] = TX/RX MIC key [63:32]
2759 * key3 [31:0] = reserved
2760 * key4 [31:0] = reserved
2762 * Upper layer code will call this function separately
2763 * for TX and RX keys when these registers offsets are
2768 mic0 = get_unaligned_le32(k->kv_mic + 0);
2769 mic2 = get_unaligned_le32(k->kv_mic + 4);
2771 /* Write MIC key[31:0] */
2772 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2773 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2775 /* Write MIC key[63:32] */
2776 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2777 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2779 /* Write TX[63:32] and keyType(reserved) */
2780 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2781 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2782 AR_KEYTABLE_TYPE_CLR);
2785 /* MAC address registers are reserved for the MIC entry */
2786 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2787 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2790 * Write the correct (un-inverted) key[47:0] last to enable
2791 * TKIP now that all other registers are set with correct
2794 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2795 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2797 /* Write key[47:0] */
2798 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2799 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2801 /* Write key[95:48] */
2802 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2803 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2805 /* Write key[127:96] and key type */
2806 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2807 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2809 /* Write MAC address for the entry */
2810 (void) ath9k_hw_keysetmac(ah, entry, mac);
2816 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2818 if (entry < ah->caps.keycache_size) {
2819 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2820 if (val & AR_KEYTABLE_VALID)
2826 /******************************/
2827 /* Power Management (Chipset) */
2828 /******************************/
2830 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2832 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2834 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2835 AR_RTC_FORCE_WAKE_EN);
2836 if (!AR_SREV_9100(ah))
2837 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2839 REG_CLR_BIT(ah, (AR_RTC_RESET),
2844 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2846 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2848 struct ath9k_hw_capabilities *pCap = &ah->caps;
2850 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2851 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2852 AR_RTC_FORCE_WAKE_ON_INT);
2854 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2855 AR_RTC_FORCE_WAKE_EN);
2860 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2866 if ((REG_READ(ah, AR_RTC_STATUS) &
2867 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2868 if (ath9k_hw_set_reset_reg(ah,
2869 ATH9K_RESET_POWER_ON) != true) {
2873 if (AR_SREV_9100(ah))
2874 REG_SET_BIT(ah, AR_RTC_RESET,
2877 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2878 AR_RTC_FORCE_WAKE_EN);
2881 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2882 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2883 if (val == AR_RTC_STATUS_ON)
2886 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2887 AR_RTC_FORCE_WAKE_EN);
2890 DPRINTF(ah, ATH_DBG_FATAL,
2891 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
2896 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2901 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2903 int status = true, setChip = true;
2904 static const char *modes[] = {
2911 if (ah->power_mode == mode)
2914 DPRINTF(ah, ATH_DBG_RESET, "%s -> %s\n",
2915 modes[ah->power_mode], modes[mode]);
2918 case ATH9K_PM_AWAKE:
2919 status = ath9k_hw_set_power_awake(ah, setChip);
2921 case ATH9K_PM_FULL_SLEEP:
2922 ath9k_set_power_sleep(ah, setChip);
2923 ah->chip_fullsleep = true;
2925 case ATH9K_PM_NETWORK_SLEEP:
2926 ath9k_set_power_network_sleep(ah, setChip);
2929 DPRINTF(ah, ATH_DBG_FATAL,
2930 "Unknown power mode %u\n", mode);
2933 ah->power_mode = mode;
2939 * Helper for ASPM support.
2941 * Disable PLL when in L0s as well as receiver clock when in L1.
2942 * This power saving option must be enabled through the SerDes.
2944 * Programming the SerDes must go through the same 288 bit serial shift
2945 * register as the other analog registers. Hence the 9 writes.
2947 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
2952 if (ah->is_pciexpress != true)
2955 /* Do not touch SerDes registers */
2956 if (ah->config.pcie_powersave_enable == 2)
2959 /* Nothing to do on restore for 11N */
2961 if (AR_SREV_9280_20_OR_LATER(ah)) {
2963 * AR9280 2.0 or later chips use SerDes values from the
2964 * initvals.h initialized depending on chipset during
2967 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2968 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2969 INI_RA(&ah->iniPcieSerdes, i, 1));
2971 } else if (AR_SREV_9280(ah) &&
2972 (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2973 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2974 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2976 /* RX shut off when elecidle is asserted */
2977 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2978 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2979 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2981 /* Shut off CLKREQ active in L1 */
2982 if (ah->config.pcie_clock_req)
2983 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2985 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2987 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2988 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2989 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2991 /* Load the new settings */
2992 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2995 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2996 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2998 /* RX shut off when elecidle is asserted */
2999 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
3000 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
3001 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
3004 * Ignore ah->ah_config.pcie_clock_req setting for
3007 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
3009 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3010 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3011 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
3013 /* Load the new settings */
3014 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
3019 /* set bit 19 to allow forcing of pcie core into L1 state */
3020 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
3022 /* Several PCIe massages to ensure proper behaviour */
3023 if (ah->config.pcie_waen) {
3024 val = ah->config.pcie_waen;
3026 val &= (~AR_WA_D3_L1_DISABLE);
3028 if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
3030 val = AR9285_WA_DEFAULT;
3032 val &= (~AR_WA_D3_L1_DISABLE);
3033 } else if (AR_SREV_9280(ah)) {
3035 * On AR9280 chips bit 22 of 0x4004 needs to be
3036 * set otherwise card may disappear.
3038 val = AR9280_WA_DEFAULT;
3040 val &= (~AR_WA_D3_L1_DISABLE);
3042 val = AR_WA_DEFAULT;
3045 REG_WRITE(ah, AR_WA, val);
3050 * Set PCIe workaround bits
3051 * bit 14 in WA register (disable L1) should only
3052 * be set when device enters D3 and be cleared
3053 * when device comes back to D0.
3055 if (ah->config.pcie_waen) {
3056 if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
3057 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
3059 if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
3060 AR_SREV_9287(ah)) &&
3061 (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
3062 (AR_SREV_9280(ah) &&
3063 (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
3064 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
3070 /**********************/
3071 /* Interrupt Handling */
3072 /**********************/
3074 bool ath9k_hw_intrpend(struct ath_hw *ah)
3078 if (AR_SREV_9100(ah))
3081 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
3082 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
3085 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
3086 if ((host_isr & AR_INTR_SYNC_DEFAULT)
3087 && (host_isr != AR_INTR_SPURIOUS))
3093 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
3097 struct ath9k_hw_capabilities *pCap = &ah->caps;
3099 bool fatal_int = false;
3101 if (!AR_SREV_9100(ah)) {
3102 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
3103 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
3104 == AR_RTC_STATUS_ON) {
3105 isr = REG_READ(ah, AR_ISR);
3109 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
3110 AR_INTR_SYNC_DEFAULT;
3114 if (!isr && !sync_cause)
3118 isr = REG_READ(ah, AR_ISR);
3122 if (isr & AR_ISR_BCNMISC) {
3124 isr2 = REG_READ(ah, AR_ISR_S2);
3125 if (isr2 & AR_ISR_S2_TIM)
3126 mask2 |= ATH9K_INT_TIM;
3127 if (isr2 & AR_ISR_S2_DTIM)
3128 mask2 |= ATH9K_INT_DTIM;
3129 if (isr2 & AR_ISR_S2_DTIMSYNC)
3130 mask2 |= ATH9K_INT_DTIMSYNC;
3131 if (isr2 & (AR_ISR_S2_CABEND))
3132 mask2 |= ATH9K_INT_CABEND;
3133 if (isr2 & AR_ISR_S2_GTT)
3134 mask2 |= ATH9K_INT_GTT;
3135 if (isr2 & AR_ISR_S2_CST)
3136 mask2 |= ATH9K_INT_CST;
3137 if (isr2 & AR_ISR_S2_TSFOOR)
3138 mask2 |= ATH9K_INT_TSFOOR;
3141 isr = REG_READ(ah, AR_ISR_RAC);
3142 if (isr == 0xffffffff) {
3147 *masked = isr & ATH9K_INT_COMMON;
3149 if (ah->config.intr_mitigation) {
3150 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
3151 *masked |= ATH9K_INT_RX;
3154 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
3155 *masked |= ATH9K_INT_RX;
3157 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
3161 *masked |= ATH9K_INT_TX;
3163 s0_s = REG_READ(ah, AR_ISR_S0_S);
3164 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
3165 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
3167 s1_s = REG_READ(ah, AR_ISR_S1_S);
3168 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
3169 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
3172 if (isr & AR_ISR_RXORN) {
3173 DPRINTF(ah, ATH_DBG_INTERRUPT,
3174 "receive FIFO overrun interrupt\n");
3177 if (!AR_SREV_9100(ah)) {
3178 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3179 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
3180 if (isr5 & AR_ISR_S5_TIM_TIMER)
3181 *masked |= ATH9K_INT_TIM_TIMER;
3188 if (AR_SREV_9100(ah))
3191 if (isr & AR_ISR_GENTMR) {
3194 s5_s = REG_READ(ah, AR_ISR_S5_S);
3195 if (isr & AR_ISR_GENTMR) {
3196 ah->intr_gen_timer_trigger =
3197 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
3199 ah->intr_gen_timer_thresh =
3200 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
3202 if (ah->intr_gen_timer_trigger)
3203 *masked |= ATH9K_INT_GENTIMER;
3211 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
3215 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
3216 DPRINTF(ah, ATH_DBG_ANY,
3217 "received PCI FATAL interrupt\n");
3219 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
3220 DPRINTF(ah, ATH_DBG_ANY,
3221 "received PCI PERR interrupt\n");
3223 *masked |= ATH9K_INT_FATAL;
3225 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
3226 DPRINTF(ah, ATH_DBG_INTERRUPT,
3227 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
3228 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
3229 REG_WRITE(ah, AR_RC, 0);
3230 *masked |= ATH9K_INT_FATAL;
3232 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
3233 DPRINTF(ah, ATH_DBG_INTERRUPT,
3234 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
3237 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
3238 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
3244 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
3246 u32 omask = ah->mask_reg;
3248 struct ath9k_hw_capabilities *pCap = &ah->caps;
3250 DPRINTF(ah, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
3252 if (omask & ATH9K_INT_GLOBAL) {
3253 DPRINTF(ah, ATH_DBG_INTERRUPT, "disable IER\n");
3254 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
3255 (void) REG_READ(ah, AR_IER);
3256 if (!AR_SREV_9100(ah)) {
3257 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
3258 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
3260 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
3261 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
3265 mask = ints & ATH9K_INT_COMMON;
3268 if (ints & ATH9K_INT_TX) {
3269 if (ah->txok_interrupt_mask)
3270 mask |= AR_IMR_TXOK;
3271 if (ah->txdesc_interrupt_mask)
3272 mask |= AR_IMR_TXDESC;
3273 if (ah->txerr_interrupt_mask)
3274 mask |= AR_IMR_TXERR;
3275 if (ah->txeol_interrupt_mask)
3276 mask |= AR_IMR_TXEOL;
3278 if (ints & ATH9K_INT_RX) {
3279 mask |= AR_IMR_RXERR;
3280 if (ah->config.intr_mitigation)
3281 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
3283 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
3284 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
3285 mask |= AR_IMR_GENTMR;
3288 if (ints & (ATH9K_INT_BMISC)) {
3289 mask |= AR_IMR_BCNMISC;
3290 if (ints & ATH9K_INT_TIM)
3291 mask2 |= AR_IMR_S2_TIM;
3292 if (ints & ATH9K_INT_DTIM)
3293 mask2 |= AR_IMR_S2_DTIM;
3294 if (ints & ATH9K_INT_DTIMSYNC)
3295 mask2 |= AR_IMR_S2_DTIMSYNC;
3296 if (ints & ATH9K_INT_CABEND)
3297 mask2 |= AR_IMR_S2_CABEND;
3298 if (ints & ATH9K_INT_TSFOOR)
3299 mask2 |= AR_IMR_S2_TSFOOR;
3302 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
3303 mask |= AR_IMR_BCNMISC;
3304 if (ints & ATH9K_INT_GTT)
3305 mask2 |= AR_IMR_S2_GTT;
3306 if (ints & ATH9K_INT_CST)
3307 mask2 |= AR_IMR_S2_CST;
3310 DPRINTF(ah, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
3311 REG_WRITE(ah, AR_IMR, mask);
3312 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3314 AR_IMR_S2_DTIMSYNC |
3318 AR_IMR_S2_GTT | AR_IMR_S2_CST);
3319 REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3320 ah->mask_reg = ints;
3322 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3323 if (ints & ATH9K_INT_TIM_TIMER)
3324 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3326 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3329 if (ints & ATH9K_INT_GLOBAL) {
3330 DPRINTF(ah, ATH_DBG_INTERRUPT, "enable IER\n");
3331 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3332 if (!AR_SREV_9100(ah)) {
3333 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3335 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3338 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3339 AR_INTR_SYNC_DEFAULT);
3340 REG_WRITE(ah, AR_INTR_SYNC_MASK,
3341 AR_INTR_SYNC_DEFAULT);
3343 DPRINTF(ah, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3344 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3350 /*******************/
3351 /* Beacon Handling */
3352 /*******************/
3354 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
3358 ah->beacon_interval = beacon_period;
3360 switch (ah->opmode) {
3361 case NL80211_IFTYPE_STATION:
3362 case NL80211_IFTYPE_MONITOR:
3363 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3364 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3365 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3366 flags |= AR_TBTT_TIMER_EN;
3368 case NL80211_IFTYPE_ADHOC:
3369 case NL80211_IFTYPE_MESH_POINT:
3370 REG_SET_BIT(ah, AR_TXCFG,
3371 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3372 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3373 TU_TO_USEC(next_beacon +
3374 (ah->atim_window ? ah->
3376 flags |= AR_NDP_TIMER_EN;
3377 case NL80211_IFTYPE_AP:
3378 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3379 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3380 TU_TO_USEC(next_beacon -
3382 dma_beacon_response_time));
3383 REG_WRITE(ah, AR_NEXT_SWBA,
3384 TU_TO_USEC(next_beacon -
3386 sw_beacon_response_time));
3388 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3391 DPRINTF(ah, ATH_DBG_BEACON,
3392 "%s: unsupported opmode: %d\n",
3393 __func__, ah->opmode);
3398 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3399 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3400 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3401 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3403 beacon_period &= ~ATH9K_BEACON_ENA;
3404 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3405 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3406 ath9k_hw_reset_tsf(ah);
3409 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3412 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3413 const struct ath9k_beacon_state *bs)
3415 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3416 struct ath9k_hw_capabilities *pCap = &ah->caps;
3418 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3420 REG_WRITE(ah, AR_BEACON_PERIOD,
3421 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3422 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3423 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3425 REG_RMW_FIELD(ah, AR_RSSI_THR,
3426 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3428 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3430 if (bs->bs_sleepduration > beaconintval)
3431 beaconintval = bs->bs_sleepduration;
3433 dtimperiod = bs->bs_dtimperiod;
3434 if (bs->bs_sleepduration > dtimperiod)
3435 dtimperiod = bs->bs_sleepduration;
3437 if (beaconintval == dtimperiod)
3438 nextTbtt = bs->bs_nextdtim;
3440 nextTbtt = bs->bs_nexttbtt;
3442 DPRINTF(ah, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3443 DPRINTF(ah, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3444 DPRINTF(ah, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3445 DPRINTF(ah, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3447 REG_WRITE(ah, AR_NEXT_DTIM,
3448 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3449 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3451 REG_WRITE(ah, AR_SLEEP1,
3452 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3453 | AR_SLEEP1_ASSUME_DTIM);
3455 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3456 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3458 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3460 REG_WRITE(ah, AR_SLEEP2,
3461 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3463 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3464 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3466 REG_SET_BIT(ah, AR_TIMER_MODE,
3467 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3470 /* TSF Out of Range Threshold */
3471 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3474 /*******************/
3475 /* HW Capabilities */
3476 /*******************/
3478 void ath9k_hw_fill_cap_info(struct ath_hw *ah)
3480 struct ath9k_hw_capabilities *pCap = &ah->caps;
3481 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3482 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
3484 u16 capField = 0, eeval;
3486 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3487 regulatory->current_rd = eeval;
3489 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3490 if (AR_SREV_9285_10_OR_LATER(ah))
3491 eeval |= AR9285_RDEXT_DEFAULT;
3492 regulatory->current_rd_ext = eeval;
3494 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3496 if (ah->opmode != NL80211_IFTYPE_AP &&
3497 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3498 if (regulatory->current_rd == 0x64 ||
3499 regulatory->current_rd == 0x65)
3500 regulatory->current_rd += 5;
3501 else if (regulatory->current_rd == 0x41)
3502 regulatory->current_rd = 0x43;
3503 DPRINTF(ah, ATH_DBG_REGULATORY,
3504 "regdomain mapped to 0x%x\n", regulatory->current_rd);
3507 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3508 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3510 if (eeval & AR5416_OPFLAGS_11A) {
3511 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3512 if (ah->config.ht_enable) {
3513 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3514 set_bit(ATH9K_MODE_11NA_HT20,
3515 pCap->wireless_modes);
3516 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3517 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3518 pCap->wireless_modes);
3519 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3520 pCap->wireless_modes);
3525 if (eeval & AR5416_OPFLAGS_11G) {
3526 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3527 if (ah->config.ht_enable) {
3528 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3529 set_bit(ATH9K_MODE_11NG_HT20,
3530 pCap->wireless_modes);
3531 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3532 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3533 pCap->wireless_modes);
3534 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3535 pCap->wireless_modes);
3540 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3542 * For AR9271 we will temporarilly uses the rx chainmax as read from
3545 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3546 !(eeval & AR5416_OPFLAGS_11A) &&
3547 !(AR_SREV_9271(ah)))
3548 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
3549 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3551 /* Use rx_chainmask from EEPROM. */
3552 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3554 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3555 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3557 pCap->low_2ghz_chan = 2312;
3558 pCap->high_2ghz_chan = 2732;
3560 pCap->low_5ghz_chan = 4920;
3561 pCap->high_5ghz_chan = 6100;
3563 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3564 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3565 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3567 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3568 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3569 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3571 if (ah->config.ht_enable)
3572 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3574 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3576 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3577 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3578 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3579 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3581 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3582 pCap->total_queues =
3583 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3585 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3587 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3588 pCap->keycache_size =
3589 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3591 pCap->keycache_size = AR_KEYTABLE_SIZE;
3593 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3594 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3596 if (AR_SREV_9285_10_OR_LATER(ah))
3597 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3598 else if (AR_SREV_9280_10_OR_LATER(ah))
3599 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3601 pCap->num_gpio_pins = AR_NUM_GPIO;
3603 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3604 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3605 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3607 pCap->rts_aggr_limit = (8 * 1024);
3610 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3612 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3613 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3614 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3616 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3617 ah->rfkill_polarity =
3618 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3620 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3624 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3626 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3627 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3629 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3631 if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3633 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3634 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3635 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3636 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3639 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3640 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3643 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3645 pCap->num_antcfg_5ghz =
3646 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3647 pCap->num_antcfg_2ghz =
3648 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3650 if (AR_SREV_9280_10_OR_LATER(ah) &&
3651 ath9k_hw_btcoex_supported(ah)) {
3652 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
3653 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
3655 if (AR_SREV_9285(ah)) {
3656 btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
3657 btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
3659 btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
3662 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
3666 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3667 u32 capability, u32 *result)
3669 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3671 case ATH9K_CAP_CIPHER:
3672 switch (capability) {
3673 case ATH9K_CIPHER_AES_CCM:
3674 case ATH9K_CIPHER_AES_OCB:
3675 case ATH9K_CIPHER_TKIP:
3676 case ATH9K_CIPHER_WEP:
3677 case ATH9K_CIPHER_MIC:
3678 case ATH9K_CIPHER_CLR:
3683 case ATH9K_CAP_TKIP_MIC:
3684 switch (capability) {
3688 return (ah->sta_id1_defaults &
3689 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3692 case ATH9K_CAP_TKIP_SPLIT:
3693 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3695 case ATH9K_CAP_DIVERSITY:
3696 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3697 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3699 case ATH9K_CAP_MCAST_KEYSRCH:
3700 switch (capability) {
3704 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3707 return (ah->sta_id1_defaults &
3708 AR_STA_ID1_MCAST_KSRCH) ? true :
3713 case ATH9K_CAP_TXPOW:
3714 switch (capability) {
3718 *result = regulatory->power_limit;
3721 *result = regulatory->max_power_level;
3724 *result = regulatory->tp_scale;
3729 return (AR_SREV_9280_20_OR_LATER(ah) &&
3730 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3737 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3738 u32 capability, u32 setting, int *status)
3743 case ATH9K_CAP_TKIP_MIC:
3745 ah->sta_id1_defaults |=
3746 AR_STA_ID1_CRPT_MIC_ENABLE;
3748 ah->sta_id1_defaults &=
3749 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3751 case ATH9K_CAP_DIVERSITY:
3752 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3754 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3756 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3757 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3759 case ATH9K_CAP_MCAST_KEYSRCH:
3761 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3763 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3770 /****************************/
3771 /* GPIO / RFKILL / Antennae */
3772 /****************************/
3774 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3778 u32 gpio_shift, tmp;
3781 addr = AR_GPIO_OUTPUT_MUX3;
3783 addr = AR_GPIO_OUTPUT_MUX2;
3785 addr = AR_GPIO_OUTPUT_MUX1;
3787 gpio_shift = (gpio % 6) * 5;
3789 if (AR_SREV_9280_20_OR_LATER(ah)
3790 || (addr != AR_GPIO_OUTPUT_MUX1)) {
3791 REG_RMW(ah, addr, (type << gpio_shift),
3792 (0x1f << gpio_shift));
3794 tmp = REG_READ(ah, addr);
3795 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3796 tmp &= ~(0x1f << gpio_shift);
3797 tmp |= (type << gpio_shift);
3798 REG_WRITE(ah, addr, tmp);
3802 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3806 ASSERT(gpio < ah->caps.num_gpio_pins);
3808 gpio_shift = gpio << 1;
3812 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3813 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3816 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3818 #define MS_REG_READ(x, y) \
3819 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3821 if (gpio >= ah->caps.num_gpio_pins)
3824 if (AR_SREV_9287_10_OR_LATER(ah))
3825 return MS_REG_READ(AR9287, gpio) != 0;
3826 else if (AR_SREV_9285_10_OR_LATER(ah))
3827 return MS_REG_READ(AR9285, gpio) != 0;
3828 else if (AR_SREV_9280_10_OR_LATER(ah))
3829 return MS_REG_READ(AR928X, gpio) != 0;
3831 return MS_REG_READ(AR, gpio) != 0;
3834 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3839 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3841 gpio_shift = 2 * gpio;
3845 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3846 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3849 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3851 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3855 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3857 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3860 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3862 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3865 bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
3866 enum ath9k_ant_setting settings,
3867 struct ath9k_channel *chan,
3872 static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3874 if (AR_SREV_9280(ah)) {
3875 if (!tx_chainmask_cfg) {
3877 tx_chainmask_cfg = *tx_chainmask;
3878 rx_chainmask_cfg = *rx_chainmask;
3882 case ATH9K_ANT_FIXED_A:
3883 *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3884 *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3885 *antenna_cfgd = true;
3887 case ATH9K_ANT_FIXED_B:
3888 if (ah->caps.tx_chainmask >
3889 ATH9K_ANTENNA1_CHAINMASK) {
3890 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3892 *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3893 *antenna_cfgd = true;
3895 case ATH9K_ANT_VARIABLE:
3896 *tx_chainmask = tx_chainmask_cfg;
3897 *rx_chainmask = rx_chainmask_cfg;
3898 *antenna_cfgd = true;
3904 ah->config.diversity_control = settings;
3910 /*********************/
3911 /* General Operation */
3912 /*********************/
3914 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3916 u32 bits = REG_READ(ah, AR_RX_FILTER);
3917 u32 phybits = REG_READ(ah, AR_PHY_ERR);
3919 if (phybits & AR_PHY_ERR_RADAR)
3920 bits |= ATH9K_RX_FILTER_PHYRADAR;
3921 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3922 bits |= ATH9K_RX_FILTER_PHYERR;
3927 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3931 REG_WRITE(ah, AR_RX_FILTER, bits);
3934 if (bits & ATH9K_RX_FILTER_PHYRADAR)
3935 phybits |= AR_PHY_ERR_RADAR;
3936 if (bits & ATH9K_RX_FILTER_PHYERR)
3937 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3938 REG_WRITE(ah, AR_PHY_ERR, phybits);
3941 REG_WRITE(ah, AR_RXCFG,
3942 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3944 REG_WRITE(ah, AR_RXCFG,
3945 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3948 bool ath9k_hw_phy_disable(struct ath_hw *ah)
3950 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3953 bool ath9k_hw_disable(struct ath_hw *ah)
3955 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3958 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3961 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3963 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3964 struct ath9k_channel *chan = ah->curchan;
3965 struct ieee80211_channel *channel = chan->chan;
3967 regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
3969 ah->eep_ops->set_txpower(ah, chan,
3970 ath9k_regd_get_ctl(regulatory, chan),
3971 channel->max_antenna_gain * 2,
3972 channel->max_power * 2,
3973 min((u32) MAX_RATE_POWER,
3974 (u32) regulatory->power_limit));
3977 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3979 memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
3982 void ath9k_hw_setopmode(struct ath_hw *ah)
3984 ath9k_hw_set_operating_mode(ah, ah->opmode);
3987 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3989 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3990 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3993 void ath9k_hw_setbssidmask(struct ath_hw *ah)
3995 struct ath_common *common = ath9k_hw_common(ah);
3997 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(common->bssidmask));
3998 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(common->bssidmask + 4));
4001 void ath9k_hw_write_associd(struct ath_hw *ah)
4003 struct ath_common *common = ath9k_hw_common(ah);
4005 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
4006 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
4007 ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
4010 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
4014 tsf = REG_READ(ah, AR_TSF_U32);
4015 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
4020 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
4022 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
4023 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
4026 void ath9k_hw_reset_tsf(struct ath_hw *ah)
4028 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
4029 AH_TSF_WRITE_TIMEOUT))
4030 DPRINTF(ah, ATH_DBG_RESET,
4031 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
4033 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
4036 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
4039 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
4041 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
4044 bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
4046 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
4047 DPRINTF(ah, ATH_DBG_RESET, "bad slot time %u\n", us);
4048 ah->slottime = (u32) -1;
4051 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
4057 void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode)
4061 if (mode == ATH9K_HT_MACMODE_2040 &&
4062 !ah->config.cwm_ignore_extcca)
4063 macmode = AR_2040_JOINED_RX_CLEAR;
4067 REG_WRITE(ah, AR_2040_MODE, macmode);
4070 /* HW Generic timers configuration */
4072 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
4074 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4075 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4076 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4077 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4078 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4079 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4080 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4081 {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4082 {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
4083 {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
4084 AR_NDP2_TIMER_MODE, 0x0002},
4085 {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
4086 AR_NDP2_TIMER_MODE, 0x0004},
4087 {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
4088 AR_NDP2_TIMER_MODE, 0x0008},
4089 {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
4090 AR_NDP2_TIMER_MODE, 0x0010},
4091 {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
4092 AR_NDP2_TIMER_MODE, 0x0020},
4093 {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
4094 AR_NDP2_TIMER_MODE, 0x0040},
4095 {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
4096 AR_NDP2_TIMER_MODE, 0x0080}
4099 /* HW generic timer primitives */
4101 /* compute and clear index of rightmost 1 */
4102 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
4112 return timer_table->gen_timer_index[b];
4115 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
4117 return REG_READ(ah, AR_TSF_L32);
4120 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
4121 void (*trigger)(void *),
4122 void (*overflow)(void *),
4126 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4127 struct ath_gen_timer *timer;
4129 timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
4131 if (timer == NULL) {
4132 printk(KERN_DEBUG "Failed to allocate memory"
4133 "for hw timer[%d]\n", timer_index);
4137 /* allocate a hardware generic timer slot */
4138 timer_table->timers[timer_index] = timer;
4139 timer->index = timer_index;
4140 timer->trigger = trigger;
4141 timer->overflow = overflow;
4147 void ath_gen_timer_start(struct ath_hw *ah,
4148 struct ath_gen_timer *timer,
4149 u32 timer_next, u32 timer_period)
4151 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4154 BUG_ON(!timer_period);
4156 set_bit(timer->index, &timer_table->timer_mask.timer_bits);
4158 tsf = ath9k_hw_gettsf32(ah);
4160 DPRINTF(ah, ATH_DBG_HWTIMER, "curent tsf %x period %x"
4161 "timer_next %x\n", tsf, timer_period, timer_next);
4164 * Pull timer_next forward if the current TSF already passed it
4165 * because of software latency
4167 if (timer_next < tsf)
4168 timer_next = tsf + timer_period;
4171 * Program generic timer registers
4173 REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
4175 REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
4177 REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
4178 gen_tmr_configuration[timer->index].mode_mask);
4180 /* Enable both trigger and thresh interrupt masks */
4181 REG_SET_BIT(ah, AR_IMR_S5,
4182 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
4183 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
4185 if ((ah->ah_sc->imask & ATH9K_INT_GENTIMER) == 0) {
4186 ath9k_hw_set_interrupts(ah, 0);
4187 ah->ah_sc->imask |= ATH9K_INT_GENTIMER;
4188 ath9k_hw_set_interrupts(ah, ah->ah_sc->imask);
4192 void ath_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
4194 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4196 if ((timer->index < AR_FIRST_NDP_TIMER) ||
4197 (timer->index >= ATH_MAX_GEN_TIMER)) {
4201 /* Clear generic timer enable bits. */
4202 REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
4203 gen_tmr_configuration[timer->index].mode_mask);
4205 /* Disable both trigger and thresh interrupt masks */
4206 REG_CLR_BIT(ah, AR_IMR_S5,
4207 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
4208 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
4210 clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
4212 /* if no timer is enabled, turn off interrupt mask */
4213 if (timer_table->timer_mask.val == 0) {
4214 ath9k_hw_set_interrupts(ah, 0);
4215 ah->ah_sc->imask &= ~ATH9K_INT_GENTIMER;
4216 ath9k_hw_set_interrupts(ah, ah->ah_sc->imask);
4220 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
4222 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4224 /* free the hardware generic timer slot */
4225 timer_table->timers[timer->index] = NULL;
4230 * Generic Timer Interrupts handling
4232 void ath_gen_timer_isr(struct ath_hw *ah)
4234 struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4235 struct ath_gen_timer *timer;
4236 u32 trigger_mask, thresh_mask, index;
4238 /* get hardware generic timer interrupt status */
4239 trigger_mask = ah->intr_gen_timer_trigger;
4240 thresh_mask = ah->intr_gen_timer_thresh;
4241 trigger_mask &= timer_table->timer_mask.val;
4242 thresh_mask &= timer_table->timer_mask.val;
4244 trigger_mask &= ~thresh_mask;
4246 while (thresh_mask) {
4247 index = rightmost_index(timer_table, &thresh_mask);
4248 timer = timer_table->timers[index];
4250 DPRINTF(ah, ATH_DBG_HWTIMER,
4251 "TSF overflow for Gen timer %d\n", index);
4252 timer->overflow(timer->arg);
4255 while (trigger_mask) {
4256 index = rightmost_index(timer_table, &trigger_mask);
4257 timer = timer_table->timers[index];
4259 DPRINTF(ah, ATH_DBG_HWTIMER,
4260 "Gen timer[%d] trigger\n", index);
4261 timer->trigger(timer->arg);