SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/ath/ath9k/hw.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <asm/unaligned.h>
  19
  20 #include "ath9k.h"
  21 #include "initvals.h"
  22
  23 static int btcoex_enable;
  24 module_param(btcoex_enable, bool, 0);
  25 MODULE_PARM_DESC(btcoex_enable, "Enable Bluetooth coexistence support");
  26
  27 #define ATH9K_CLOCK_RATE_CCK            22
  28 #define ATH9K_CLOCK_RATE_5GHZ_OFDM      40
  29 #define ATH9K_CLOCK_RATE_2GHZ_OFDM      44
  30
  31 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
  32 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
  33                               enum ath9k_ht_macmode macmode);
  34 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
  35                               struct ar5416_eeprom_def *pEepData,
  36                               u32 reg, u32 value);
  37 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
  38 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
  39
  40 /********************/
  41 /* Helper Functions */
  42 /********************/
  43
  44 static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
  45 {
  46         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  47
  48         if (!ah->curchan) /* should really check for CCK instead */
  49                 return clks / ATH9K_CLOCK_RATE_CCK;
  50         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  51                 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
  52
  53         return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
  54 }
  55
  56 static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
  57 {
  58         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  59
  60         if (conf_is_ht40(conf))
  61                 return ath9k_hw_mac_usec(ah, clks) / 2;
  62         else
  63                 return ath9k_hw_mac_usec(ah, clks);
  64 }
  65
  66 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
  67 {
  68         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  69
  70         if (!ah->curchan) /* should really check for CCK instead */
  71                 return usecs *ATH9K_CLOCK_RATE_CCK;
  72         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  73                 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
  74         return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
  75 }
  76
  77 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
  78 {
  79         struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
  80
  81         if (conf_is_ht40(conf))
  82                 return ath9k_hw_mac_clks(ah, usecs) * 2;
  83         else
  84                 return ath9k_hw_mac_clks(ah, usecs);
  85 }
  86
  87 /*
  88  * Read and write, they both share the same lock. We do this to serialize
  89  * reads and writes on Atheros 802.11n PCI devices only. This is required
  90  * as the FIFO on these devices can only accept sanely 2 requests. After
  91  * that the device goes bananas. Serializing the reads/writes prevents this
  92  * from happening.
  93  */
  94
  95 void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val)
  96 {
  97         if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
  98                 unsigned long flags;
  99                 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
 100                 iowrite32(val, ah->ah_sc->mem + reg_offset);
 101                 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
 102         } else
 103                 iowrite32(val, ah->ah_sc->mem + reg_offset);
 104 }
 105
 106 unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset)
 107 {
 108         u32 val;
 109         if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
 110                 unsigned long flags;
 111                 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
 112                 val = ioread32(ah->ah_sc->mem + reg_offset);
 113                 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
 114         } else
 115                 val = ioread32(ah->ah_sc->mem + reg_offset);
 116         return val;
 117 }
 118
 119 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
 120 {
 121         int i;
 122
 123         BUG_ON(timeout < AH_TIME_QUANTUM);
 124
 125         for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
 126                 if ((REG_READ(ah, reg) & mask) == val)
 127                         return true;
 128
 129                 udelay(AH_TIME_QUANTUM);
 130         }
 131
 132         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
 133                 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
 134                 timeout, reg, REG_READ(ah, reg), mask, val);
 135
 136         return false;
 137 }
 138
 139 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
 140 {
 141         u32 retval;
 142         int i;
 143
 144         for (i = 0, retval = 0; i < n; i++) {
 145                 retval = (retval << 1) | (val & 1);
 146                 val >>= 1;
 147         }
 148         return retval;
 149 }
 150
 151 bool ath9k_get_channel_edges(struct ath_hw *ah,
 152                              u16 flags, u16 *low,
 153                              u16 *high)
 154 {
 155         struct ath9k_hw_capabilities *pCap = &ah->caps;
 156
 157         if (flags & CHANNEL_5GHZ) {
 158                 *low = pCap->low_5ghz_chan;
 159                 *high = pCap->high_5ghz_chan;
 160                 return true;
 161         }
 162         if ((flags & CHANNEL_2GHZ)) {
 163                 *low = pCap->low_2ghz_chan;
 164                 *high = pCap->high_2ghz_chan;
 165                 return true;
 166         }
 167         return false;
 168 }
 169
 170 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
 171                            const struct ath_rate_table *rates,
 172                            u32 frameLen, u16 rateix,
 173                            bool shortPreamble)
 174 {
 175         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
 176         u32 kbps;
 177
 178         kbps = rates->info[rateix].ratekbps;
 179
 180         if (kbps == 0)
 181                 return 0;
 182
 183         switch (rates->info[rateix].phy) {
 184         case WLAN_RC_PHY_CCK:
 185                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
 186                 if (shortPreamble && rates->info[rateix].short_preamble)
 187                         phyTime >>= 1;
 188                 numBits = frameLen << 3;
 189                 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
 190                 break;
 191         case WLAN_RC_PHY_OFDM:
 192                 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
 193                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
 194                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 195                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 196                         txTime = OFDM_SIFS_TIME_QUARTER
 197                                 + OFDM_PREAMBLE_TIME_QUARTER
 198                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
 199                 } else if (ah->curchan &&
 200                            IS_CHAN_HALF_RATE(ah->curchan)) {
 201                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
 202                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 203                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 204                         txTime = OFDM_SIFS_TIME_HALF +
 205                                 OFDM_PREAMBLE_TIME_HALF
 206                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
 207                 } else {
 208                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
 209                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 210                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 211                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
 212                                 + (numSymbols * OFDM_SYMBOL_TIME);
 213                 }
 214                 break;
 215         default:
 216                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 217                         "Unknown phy %u (rate ix %u)\n",
 218                         rates->info[rateix].phy, rateix);
 219                 txTime = 0;
 220                 break;
 221         }
 222
 223         return txTime;
 224 }
 225
 226 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
 227                                   struct ath9k_channel *chan,
 228                                   struct chan_centers *centers)
 229 {
 230         int8_t extoff;
 231
 232         if (!IS_CHAN_HT40(chan)) {
 233                 centers->ctl_center = centers->ext_center =
 234                         centers->synth_center = chan->channel;
 235                 return;
 236         }
 237
 238         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 239             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
 240                 centers->synth_center =
 241                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
 242                 extoff = 1;
 243         } else {
 244                 centers->synth_center =
 245                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
 246                 extoff = -1;
 247         }
 248
 249         centers->ctl_center =
 250                 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
 251         centers->ext_center =
 252                 centers->synth_center + (extoff *
 253                          ((ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
 254                           HT40_CHANNEL_CENTER_SHIFT : 15));
 255 }
 256
 257 /******************/
 258 /* Chip Revisions */
 259 /******************/
 260
 261 static void ath9k_hw_read_revisions(struct ath_hw *ah)
 262 {
 263         u32 val;
 264
 265         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
 266
 267         if (val == 0xFF) {
 268                 val = REG_READ(ah, AR_SREV);
 269                 ah->hw_version.macVersion =
 270                         (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
 271                 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
 272                 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
 273         } else {
 274                 if (!AR_SREV_9100(ah))
 275                         ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
 276
 277                 ah->hw_version.macRev = val & AR_SREV_REVISION;
 278
 279                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
 280                         ah->is_pciexpress = true;
 281         }
 282 }
 283
 284 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
 285 {
 286         u32 val;
 287         int i;
 288
 289         REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
 290
 291         for (i = 0; i < 8; i++)
 292                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
 293         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
 294         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
 295
 296         return ath9k_hw_reverse_bits(val, 8);
 297 }
 298
 299 /************************************/
 300 /* HW Attach, Detach, Init Routines */
 301 /************************************/
 302
 303 static void ath9k_hw_disablepcie(struct ath_hw *ah)
 304 {
 305         if (AR_SREV_9100(ah))
 306                 return;
 307
 308         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 309         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 310         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
 311         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
 312         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
 313         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
 314         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 315         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 316         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
 317
 318         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 319 }
 320
 321 static bool ath9k_hw_chip_test(struct ath_hw *ah)
 322 {
 323         u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
 324         u32 regHold[2];
 325         u32 patternData[4] = { 0x55555555,
 326                                0xaaaaaaaa,
 327                                0x66666666,
 328                                0x99999999 };
 329         int i, j;
 330
 331         for (i = 0; i < 2; i++) {
 332                 u32 addr = regAddr[i];
 333                 u32 wrData, rdData;
 334
 335                 regHold[i] = REG_READ(ah, addr);
 336                 for (j = 0; j < 0x100; j++) {
 337                         wrData = (j << 16) | j;
 338                         REG_WRITE(ah, addr, wrData);
 339                         rdData = REG_READ(ah, addr);
 340                         if (rdData != wrData) {
 341                                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 342                                         "address test failed "
 343                                         "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 344                                         addr, wrData, rdData);
 345                                 return false;
 346                         }
 347                 }
 348                 for (j = 0; j < 4; j++) {
 349                         wrData = patternData[j];
 350                         REG_WRITE(ah, addr, wrData);
 351                         rdData = REG_READ(ah, addr);
 352                         if (wrData != rdData) {
 353                                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 354                                         "address test failed "
 355                                         "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 356                                         addr, wrData, rdData);
 357                                 return false;
 358                         }
 359                 }
 360                 REG_WRITE(ah, regAddr[i], regHold[i]);
 361         }
 362         udelay(100);
 363
 364         return true;
 365 }
 366
 367 static const char *ath9k_hw_devname(u16 devid)
 368 {
 369         switch (devid) {
 370         case AR5416_DEVID_PCI:
 371                 return "Atheros 5416";
 372         case AR5416_DEVID_PCIE:
 373                 return "Atheros 5418";
 374         case AR9160_DEVID_PCI:
 375                 return "Atheros 9160";
 376         case AR5416_AR9100_DEVID:
 377                 return "Atheros 9100";
 378         case AR9280_DEVID_PCI:
 379         case AR9280_DEVID_PCIE:
 380                 return "Atheros 9280";
 381         case AR9285_DEVID_PCIE:
 382                 return "Atheros 9285";
 383         case AR5416_DEVID_AR9287_PCI:
 384         case AR5416_DEVID_AR9287_PCIE:
 385                 return "Atheros 9287";
 386         }
 387
 388         return NULL;
 389 }
 390
 391 static void ath9k_hw_set_defaults(struct ath_hw *ah)
 392 {
 393         int i;
 394
 395         ah->config.dma_beacon_response_time = 2;
 396         ah->config.sw_beacon_response_time = 10;
 397         ah->config.additional_swba_backoff = 0;
 398         ah->config.ack_6mb = 0x0;
 399         ah->config.cwm_ignore_extcca = 0;
 400         ah->config.pcie_powersave_enable = 0;
 401         ah->config.pcie_clock_req = 0;
 402         ah->config.pcie_waen = 0;
 403         ah->config.analog_shiftreg = 1;
 404         ah->config.ht_enable = 1;
 405         ah->config.ofdm_trig_low = 200;
 406         ah->config.ofdm_trig_high = 500;
 407         ah->config.cck_trig_high = 200;
 408         ah->config.cck_trig_low = 100;
 409         ah->config.enable_ani = 1;
 410         ah->config.diversity_control = 0;
 411         ah->config.antenna_switch_swap = 0;
 412
 413         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 414                 ah->config.spurchans[i][0] = AR_NO_SPUR;
 415                 ah->config.spurchans[i][1] = AR_NO_SPUR;
 416         }
 417
 418         ah->config.intr_mitigation = true;
 419
 420         /*
 421          * We need this for PCI devices only (Cardbus, PCI, miniPCI)
 422          * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
 423          * This means we use it for all AR5416 devices, and the few
 424          * minor PCI AR9280 devices out there.
 425          *
 426          * Serialization is required because these devices do not handle
 427          * well the case of two concurrent reads/writes due to the latency
 428          * involved. During one read/write another read/write can be issued
 429          * on another CPU while the previous read/write may still be working
 430          * on our hardware, if we hit this case the hardware poops in a loop.
 431          * We prevent this by serializing reads and writes.
 432          *
 433          * This issue is not present on PCI-Express devices or pre-AR5416
 434          * devices (legacy, 802.11abg).
 435          */
 436         if (num_possible_cpus() > 1)
 437                 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
 438 }
 439
 440 static struct ath_hw *ath9k_hw_newstate(u16 devid, struct ath_softc *sc,
 441                                         int *status)
 442 {
 443         struct ath_hw *ah;
 444
 445         ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
 446         if (ah == NULL) {
 447                 DPRINTF(sc, ATH_DBG_FATAL,
 448                         "Cannot allocate memory for state block\n");
 449                 *status = -ENOMEM;
 450                 return NULL;
 451         }
 452
 453         ah->ah_sc = sc;
 454         ah->hw_version.magic = AR5416_MAGIC;
 455         ah->regulatory.country_code = CTRY_DEFAULT;
 456         ah->hw_version.devid = devid;
 457         ah->hw_version.subvendorid = 0;
 458
 459         ah->ah_flags = 0;
 460         if ((devid == AR5416_AR9100_DEVID))
 461                 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
 462         if (!AR_SREV_9100(ah))
 463                 ah->ah_flags = AH_USE_EEPROM;
 464
 465         ah->regulatory.power_limit = MAX_RATE_POWER;
 466         ah->regulatory.tp_scale = ATH9K_TP_SCALE_MAX;
 467         ah->atim_window = 0;
 468         ah->diversity_control = ah->config.diversity_control;
 469         ah->antenna_switch_swap =
 470                 ah->config.antenna_switch_swap;
 471         ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
 472         ah->beacon_interval = 100;
 473         ah->enable_32kHz_clock = DONT_USE_32KHZ;
 474         ah->slottime = (u32) -1;
 475         ah->acktimeout = (u32) -1;
 476         ah->ctstimeout = (u32) -1;
 477         ah->globaltxtimeout = (u32) -1;
 478
 479         ah->gbeacon_rate = 0;
 480
 481         ah->power_mode = ATH9K_PM_UNDEFINED;
 482
 483         return ah;
 484 }
 485
 486 static int ath9k_hw_rfattach(struct ath_hw *ah)
 487 {
 488         bool rfStatus = false;
 489         int ecode = 0;
 490
 491         rfStatus = ath9k_hw_init_rf(ah, &ecode);
 492         if (!rfStatus) {
 493                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 494                         "RF setup failed, status: %u\n", ecode);
 495                 return ecode;
 496         }
 497
 498         return 0;
 499 }
 500
 501 static int ath9k_hw_rf_claim(struct ath_hw *ah)
 502 {
 503         u32 val;
 504
 505         REG_WRITE(ah, AR_PHY(0), 0x00000007);
 506
 507         val = ath9k_hw_get_radiorev(ah);
 508         switch (val & AR_RADIO_SREV_MAJOR) {
 509         case 0:
 510                 val = AR_RAD5133_SREV_MAJOR;
 511                 break;
 512         case AR_RAD5133_SREV_MAJOR:
 513         case AR_RAD5122_SREV_MAJOR:
 514         case AR_RAD2133_SREV_MAJOR:
 515         case AR_RAD2122_SREV_MAJOR:
 516                 break;
 517         default:
 518                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
 519                         "Radio Chip Rev 0x%02X not supported\n",
 520                         val & AR_RADIO_SREV_MAJOR);
 521                 return -EOPNOTSUPP;
 522         }
 523
 524         ah->hw_version.analog5GhzRev = val;
 525
 526         return 0;
 527 }
 528
 529 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
 530 {
 531         u32 sum;
 532         int i;
 533         u16 eeval;
 534
 535         sum = 0;
 536         for (i = 0; i < 3; i++) {
 537                 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
 538                 sum += eeval;
 539                 ah->macaddr[2 * i] = eeval >> 8;
 540                 ah->macaddr[2 * i + 1] = eeval & 0xff;
 541         }
 542         if (sum == 0 || sum == 0xffff * 3)
 543                 return -EADDRNOTAVAIL;
 544
 545         return 0;
 546 }
 547
 548 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
 549 {
 550         u32 rxgain_type;
 551
 552         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
 553                 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
 554
 555                 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
 556                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 557                         ar9280Modes_backoff_13db_rxgain_9280_2,
 558                         ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
 559                 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
 560                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 561                         ar9280Modes_backoff_23db_rxgain_9280_2,
 562                         ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
 563                 else
 564                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 565                         ar9280Modes_original_rxgain_9280_2,
 566                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 567         } else {
 568                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 569                         ar9280Modes_original_rxgain_9280_2,
 570                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 571         }
 572 }
 573
 574 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
 575 {
 576         u32 txgain_type;
 577
 578         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
 579                 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 580
 581                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
 582                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 583                         ar9280Modes_high_power_tx_gain_9280_2,
 584                         ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
 585                 else
 586                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 587                         ar9280Modes_original_tx_gain_9280_2,
 588                         ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 589         } else {
 590                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 591                 ar9280Modes_original_tx_gain_9280_2,
 592                 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 593         }
 594 }
 595
 596 static int ath9k_hw_post_attach(struct ath_hw *ah)
 597 {
 598         int ecode;
 599
 600         if (!ath9k_hw_chip_test(ah))
 601                 return -ENODEV;
 602
 603         ecode = ath9k_hw_rf_claim(ah);
 604         if (ecode != 0)
 605                 return ecode;
 606
 607         ecode = ath9k_hw_eeprom_attach(ah);
 608         if (ecode != 0)
 609                 return ecode;
 610
 611         DPRINTF(ah->ah_sc, ATH_DBG_CONFIG, "Eeprom VER: %d, REV: %d\n",
 612                 ah->eep_ops->get_eeprom_ver(ah), ah->eep_ops->get_eeprom_rev(ah));
 613
 614         ecode = ath9k_hw_rfattach(ah);
 615         if (ecode != 0)
 616                 return ecode;
 617
 618         if (!AR_SREV_9100(ah)) {
 619                 ath9k_hw_ani_setup(ah);
 620                 ath9k_hw_ani_attach(ah);
 621         }
 622
 623         return 0;
 624 }
 625
 626 static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
 627                                          int *status)
 628 {
 629         struct ath_hw *ah;
 630         int ecode;
 631         u32 i, j;
 632
 633         ah = ath9k_hw_newstate(devid, sc, status);
 634         if (ah == NULL)
 635                 return NULL;
 636
 637         ath9k_hw_set_defaults(ah);
 638
 639         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
 640                 DPRINTF(sc, ATH_DBG_FATAL, "Couldn't reset chip\n");
 641                 ecode = -EIO;
 642                 goto bad;
 643         }
 644
 645         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
 646                 DPRINTF(sc, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
 647                 ecode = -EIO;
 648                 goto bad;
 649         }
 650
 651         if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
 652                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
 653                     (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
 654                         ah->config.serialize_regmode =
 655                                 SER_REG_MODE_ON;
 656                 } else {
 657                         ah->config.serialize_regmode =
 658                                 SER_REG_MODE_OFF;
 659                 }
 660         }
 661
 662         DPRINTF(sc, ATH_DBG_RESET, "serialize_regmode is %d\n",
 663                 ah->config.serialize_regmode);
 664
 665         switch (ah->hw_version.macVersion) {
 666         case AR_SREV_VERSION_5416_PCI:
 667         case AR_SREV_VERSION_5416_PCIE:
 668         case AR_SREV_VERSION_9160:
 669         case AR_SREV_VERSION_9100:
 670         case AR_SREV_VERSION_9280:
 671         case AR_SREV_VERSION_9285:
 672         case AR_SREV_VERSION_9287:
 673                 break;
 674         default:
 675                 DPRINTF(sc, ATH_DBG_FATAL,
 676                         "Mac Chip Rev 0x%02x.%x is not supported by "
 677                         "this driver\n", ah->hw_version.macVersion,
 678                         ah->hw_version.macRev);
 679                 ecode = -EOPNOTSUPP;
 680                 goto bad;
 681         }
 682
 683         if (AR_SREV_9100(ah)) {
 684                 ah->iq_caldata.calData = &iq_cal_multi_sample;
 685                 ah->supp_cals = IQ_MISMATCH_CAL;
 686                 ah->is_pciexpress = false;
 687         }
 688         ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
 689
 690         if (AR_SREV_9160_10_OR_LATER(ah)) {
 691                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 692                         ah->iq_caldata.calData = &iq_cal_single_sample;
 693                         ah->adcgain_caldata.calData =
 694                                 &adc_gain_cal_single_sample;
 695                         ah->adcdc_caldata.calData =
 696                                 &adc_dc_cal_single_sample;
 697                         ah->adcdc_calinitdata.calData =
 698                                 &adc_init_dc_cal;
 699                 } else {
 700                         ah->iq_caldata.calData = &iq_cal_multi_sample;
 701                         ah->adcgain_caldata.calData =
 702                                 &adc_gain_cal_multi_sample;
 703                         ah->adcdc_caldata.calData =
 704                                 &adc_dc_cal_multi_sample;
 705                         ah->adcdc_calinitdata.calData =
 706                                 &adc_init_dc_cal;
 707                 }
 708                 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
 709         }
 710
 711         ah->ani_function = ATH9K_ANI_ALL;
 712         if (AR_SREV_9280_10_OR_LATER(ah))
 713                 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
 714         if (AR_SREV_9287_11_OR_LATER(ah)) {
 715                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
 716                                 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
 717                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
 718                                 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
 719                 if (ah->config.pcie_clock_req)
 720                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 721                         ar9287PciePhy_clkreq_off_L1_9287_1_1,
 722                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
 723                 else
 724                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 725                         ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
 726                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
 727                                         2);
 728         } else if (AR_SREV_9287_10_OR_LATER(ah)) {
 729                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
 730                                 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
 731                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
 732                                 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
 733
 734                 if (ah->config.pcie_clock_req)
 735                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 736                         ar9287PciePhy_clkreq_off_L1_9287_1_0,
 737                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
 738                 else
 739                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 740                         ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
 741                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
 742                                   2);
 743         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
 744
 745
 746                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
 747                                ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
 748                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
 749                                ARRAY_SIZE(ar9285Common_9285_1_2), 2);
 750
 751                 if (ah->config.pcie_clock_req) {
 752                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 753                         ar9285PciePhy_clkreq_off_L1_9285_1_2,
 754                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
 755                 } else {
 756                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 757                         ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
 758                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
 759                                   2);
 760                 }
 761         } else if (AR_SREV_9285_10_OR_LATER(ah)) {
 762                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
 763                                ARRAY_SIZE(ar9285Modes_9285), 6);
 764                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
 765                                ARRAY_SIZE(ar9285Common_9285), 2);
 766
 767                 if (ah->config.pcie_clock_req) {
 768                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 769                         ar9285PciePhy_clkreq_off_L1_9285,
 770                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
 771                 } else {
 772                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 773                         ar9285PciePhy_clkreq_always_on_L1_9285,
 774                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
 775                 }
 776         } else if (AR_SREV_9280_20_OR_LATER(ah)) {
 777                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
 778                                ARRAY_SIZE(ar9280Modes_9280_2), 6);
 779                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
 780                                ARRAY_SIZE(ar9280Common_9280_2), 2);
 781
 782                 if (ah->config.pcie_clock_req) {
 783                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 784                                ar9280PciePhy_clkreq_off_L1_9280,
 785                                ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
 786                 } else {
 787                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 788                                ar9280PciePhy_clkreq_always_on_L1_9280,
 789                                ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
 790                 }
 791                 INIT_INI_ARRAY(&ah->iniModesAdditional,
 792                                ar9280Modes_fast_clock_9280_2,
 793                                ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
 794         } else if (AR_SREV_9280_10_OR_LATER(ah)) {
 795                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
 796                                ARRAY_SIZE(ar9280Modes_9280), 6);
 797                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
 798                                ARRAY_SIZE(ar9280Common_9280), 2);
 799         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 800                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
 801                                ARRAY_SIZE(ar5416Modes_9160), 6);
 802                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
 803                                ARRAY_SIZE(ar5416Common_9160), 2);
 804                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
 805                                ARRAY_SIZE(ar5416Bank0_9160), 2);
 806                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
 807                                ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
 808                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
 809                                ARRAY_SIZE(ar5416Bank1_9160), 2);
 810                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
 811                                ARRAY_SIZE(ar5416Bank2_9160), 2);
 812                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
 813                                ARRAY_SIZE(ar5416Bank3_9160), 3);
 814                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
 815                                ARRAY_SIZE(ar5416Bank6_9160), 3);
 816                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
 817                                ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
 818                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
 819                                ARRAY_SIZE(ar5416Bank7_9160), 2);
 820                 if (AR_SREV_9160_11(ah)) {
 821                         INIT_INI_ARRAY(&ah->iniAddac,
 822                                        ar5416Addac_91601_1,
 823                                        ARRAY_SIZE(ar5416Addac_91601_1), 2);
 824                 } else {
 825                         INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
 826                                        ARRAY_SIZE(ar5416Addac_9160), 2);
 827                 }
 828         } else if (AR_SREV_9100_OR_LATER(ah)) {
 829                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
 830                                ARRAY_SIZE(ar5416Modes_9100), 6);
 831                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
 832                                ARRAY_SIZE(ar5416Common_9100), 2);
 833                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
 834                                ARRAY_SIZE(ar5416Bank0_9100), 2);
 835                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
 836                                ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
 837                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
 838                                ARRAY_SIZE(ar5416Bank1_9100), 2);
 839                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
 840                                ARRAY_SIZE(ar5416Bank2_9100), 2);
 841                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
 842                                ARRAY_SIZE(ar5416Bank3_9100), 3);
 843                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
 844                                ARRAY_SIZE(ar5416Bank6_9100), 3);
 845                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
 846                                ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
 847                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
 848                                ARRAY_SIZE(ar5416Bank7_9100), 2);
 849                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
 850                                ARRAY_SIZE(ar5416Addac_9100), 2);
 851         } else {
 852                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
 853                                ARRAY_SIZE(ar5416Modes), 6);
 854                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
 855                                ARRAY_SIZE(ar5416Common), 2);
 856                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
 857                                ARRAY_SIZE(ar5416Bank0), 2);
 858                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
 859                                ARRAY_SIZE(ar5416BB_RfGain), 3);
 860                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
 861                                ARRAY_SIZE(ar5416Bank1), 2);
 862                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
 863                                ARRAY_SIZE(ar5416Bank2), 2);
 864                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
 865                                ARRAY_SIZE(ar5416Bank3), 3);
 866                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
 867                                ARRAY_SIZE(ar5416Bank6), 3);
 868                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
 869                                ARRAY_SIZE(ar5416Bank6TPC), 3);
 870                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
 871                                ARRAY_SIZE(ar5416Bank7), 2);
 872                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
 873                                ARRAY_SIZE(ar5416Addac), 2);
 874         }
 875
 876         if (ah->is_pciexpress)
 877                 ath9k_hw_configpcipowersave(ah, 0);
 878         else
 879                 ath9k_hw_disablepcie(ah);
 880
 881         ecode = ath9k_hw_post_attach(ah);
 882         if (ecode != 0)
 883                 goto bad;
 884
 885         if (AR_SREV_9287_11(ah))
 886                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 887                 ar9287Modes_rx_gain_9287_1_1,
 888                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
 889         else if (AR_SREV_9287_10(ah))
 890                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 891                 ar9287Modes_rx_gain_9287_1_0,
 892                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
 893         else if (AR_SREV_9280_20(ah))
 894                 ath9k_hw_init_rxgain_ini(ah);
 895
 896         if (AR_SREV_9287_11(ah)) {
 897                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 898                 ar9287Modes_tx_gain_9287_1_1,
 899                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
 900         } else if (AR_SREV_9287_10(ah)) {
 901                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 902                 ar9287Modes_tx_gain_9287_1_0,
 903                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
 904         } else if (AR_SREV_9280_20(ah)) {
 905                 ath9k_hw_init_txgain_ini(ah);
 906         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
 907                 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 908
 909                 /* txgain table */
 910                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
 911                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 912                         ar9285Modes_high_power_tx_gain_9285_1_2,
 913                         ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
 914                 } else {
 915                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 916                         ar9285Modes_original_tx_gain_9285_1_2,
 917                         ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
 918                 }
 919
 920         }
 921
 922         ath9k_hw_fill_cap_info(ah);
 923
 924         if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
 925             test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
 926
 927                 /* EEPROM Fixup */
 928                 for (i = 0; i < ah->iniModes.ia_rows; i++) {
 929                         u32 reg = INI_RA(&ah->iniModes, i, 0);
 930
 931                         for (j = 1; j < ah->iniModes.ia_columns; j++) {
 932                                 u32 val = INI_RA(&ah->iniModes, i, j);
 933
 934                                 INI_RA(&ah->iniModes, i, j) =
 935                                         ath9k_hw_ini_fixup(ah,
 936                                                            &ah->eeprom.def,
 937                                                            reg, val);
 938                         }
 939                 }
 940         }
 941
 942         ecode = ath9k_hw_init_macaddr(ah);
 943         if (ecode != 0) {
 944                 DPRINTF(sc, ATH_DBG_FATAL,
 945                         "Failed to initialize MAC address\n");
 946                 goto bad;
 947         }
 948
 949         if (AR_SREV_9285(ah))
 950                 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
 951         else
 952                 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
 953
 954         ath9k_init_nfcal_hist_buffer(ah);
 955
 956         return ah;
 957 bad:
 958         if (ah)
 959                 ath9k_hw_detach(ah);
 960         if (status)
 961                 *status = ecode;
 962
 963         return NULL;
 964 }
 965
 966 static void ath9k_hw_init_bb(struct ath_hw *ah,
 967                              struct ath9k_channel *chan)
 968 {
 969         u32 synthDelay;
 970
 971         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 972         if (IS_CHAN_B(chan))
 973                 synthDelay = (4 * synthDelay) / 22;
 974         else
 975                 synthDelay /= 10;
 976
 977         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
 978
 979         udelay(synthDelay + BASE_ACTIVATE_DELAY);
 980 }
 981
 982 static void ath9k_hw_init_qos(struct ath_hw *ah)
 983 {
 984         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
 985         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
 986
 987         REG_WRITE(ah, AR_QOS_NO_ACK,
 988                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
 989                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
 990                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
 991
 992         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
 993         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
 994         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
 995         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
 996         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
 997 }
 998
 999 static void ath9k_hw_init_pll(struct ath_hw *ah,
1000                               struct ath9k_channel *chan)
1001 {
1002         u32 pll;
1003
1004         if (AR_SREV_9100(ah)) {
1005                 if (chan && IS_CHAN_5GHZ(chan))
1006                         pll = 0x1450;
1007                 else
1008                         pll = 0x1458;
1009         } else {
1010                 if (AR_SREV_9280_10_OR_LATER(ah)) {
1011                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1012
1013                         if (chan && IS_CHAN_HALF_RATE(chan))
1014                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1015                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1016                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1017
1018                         if (chan && IS_CHAN_5GHZ(chan)) {
1019                                 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1020
1021
1022                                 if (AR_SREV_9280_20(ah)) {
1023                                         if (((chan->channel % 20) == 0)
1024                                             || ((chan->channel % 10) == 0))
1025                                                 pll = 0x2850;
1026                                         else
1027                                                 pll = 0x142c;
1028                                 }
1029                         } else {
1030                                 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1031                         }
1032
1033                 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1034
1035                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1036
1037                         if (chan && IS_CHAN_HALF_RATE(chan))
1038                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1039                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1040                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1041
1042                         if (chan && IS_CHAN_5GHZ(chan))
1043                                 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1044                         else
1045                                 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1046                 } else {
1047                         pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1048
1049                         if (chan && IS_CHAN_HALF_RATE(chan))
1050                                 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1051                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1052                                 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1053
1054                         if (chan && IS_CHAN_5GHZ(chan))
1055                                 pll |= SM(0xa, AR_RTC_PLL_DIV);
1056                         else
1057                                 pll |= SM(0xb, AR_RTC_PLL_DIV);
1058                 }
1059         }
1060         REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1061
1062         udelay(RTC_PLL_SETTLE_DELAY);
1063
1064         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1065 }
1066
1067 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1068 {
1069         int rx_chainmask, tx_chainmask;
1070
1071         rx_chainmask = ah->rxchainmask;
1072         tx_chainmask = ah->txchainmask;
1073
1074         switch (rx_chainmask) {
1075         case 0x5:
1076                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1077                             AR_PHY_SWAP_ALT_CHAIN);
1078         case 0x3:
1079                 if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) {
1080                         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1081                         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1082                         break;
1083                 }
1084         case 0x1:
1085         case 0x2:
1086         case 0x7:
1087                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1088                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1089                 break;
1090         default:
1091                 break;
1092         }
1093
1094         REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1095         if (tx_chainmask == 0x5) {
1096                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1097                             AR_PHY_SWAP_ALT_CHAIN);
1098         }
1099         if (AR_SREV_9100(ah))
1100                 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1101                           REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1102 }
1103
1104 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1105                                           enum nl80211_iftype opmode)
1106 {
1107         ah->mask_reg = AR_IMR_TXERR |
1108                 AR_IMR_TXURN |
1109                 AR_IMR_RXERR |
1110                 AR_IMR_RXORN |
1111                 AR_IMR_BCNMISC;
1112
1113         if (ah->config.intr_mitigation)
1114                 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1115         else
1116                 ah->mask_reg |= AR_IMR_RXOK;
1117
1118         ah->mask_reg |= AR_IMR_TXOK;
1119
1120         if (opmode == NL80211_IFTYPE_AP)
1121                 ah->mask_reg |= AR_IMR_MIB;
1122
1123         REG_WRITE(ah, AR_IMR, ah->mask_reg);
1124         REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1125
1126         if (!AR_SREV_9100(ah)) {
1127                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1128                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1129                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1130         }
1131 }
1132
1133 static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1134 {
1135         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1136                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
1137                 ah->acktimeout = (u32) -1;
1138                 return false;
1139         } else {
1140                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1141                               AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1142                 ah->acktimeout = us;
1143                 return true;
1144         }
1145 }
1146
1147 static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1148 {
1149         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1150                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
1151                 ah->ctstimeout = (u32) -1;
1152                 return false;
1153         } else {
1154                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1155                               AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1156                 ah->ctstimeout = us;
1157                 return true;
1158         }
1159 }
1160
1161 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1162 {
1163         if (tu > 0xFFFF) {
1164                 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1165                         "bad global tx timeout %u\n", tu);
1166                 ah->globaltxtimeout = (u32) -1;
1167                 return false;
1168         } else {
1169                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1170                 ah->globaltxtimeout = tu;
1171                 return true;
1172         }
1173 }
1174
1175 static void ath9k_hw_init_user_settings(struct ath_hw *ah)
1176 {
1177         DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1178                 ah->misc_mode);
1179
1180         if (ah->misc_mode != 0)
1181                 REG_WRITE(ah, AR_PCU_MISC,
1182                           REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1183         if (ah->slottime != (u32) -1)
1184                 ath9k_hw_setslottime(ah, ah->slottime);
1185         if (ah->acktimeout != (u32) -1)
1186                 ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
1187         if (ah->ctstimeout != (u32) -1)
1188                 ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
1189         if (ah->globaltxtimeout != (u32) -1)
1190                 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1191 }
1192
1193 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1194 {
1195         return vendorid == ATHEROS_VENDOR_ID ?
1196                 ath9k_hw_devname(devid) : NULL;
1197 }
1198
1199 void ath9k_hw_detach(struct ath_hw *ah)
1200 {
1201         if (!AR_SREV_9100(ah))
1202                 ath9k_hw_ani_detach(ah);
1203
1204         ath9k_hw_rfdetach(ah);
1205         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1206         kfree(ah);
1207 }
1208
1209 struct ath_hw *ath9k_hw_attach(u16 devid, struct ath_softc *sc, int *error)
1210 {
1211         struct ath_hw *ah = NULL;
1212
1213         switch (devid) {
1214         case AR5416_DEVID_PCI:
1215         case AR5416_DEVID_PCIE:
1216         case AR5416_AR9100_DEVID:
1217         case AR9160_DEVID_PCI:
1218         case AR9280_DEVID_PCI:
1219         case AR9280_DEVID_PCIE:
1220         case AR9285_DEVID_PCIE:
1221         case AR5416_DEVID_AR9287_PCI:
1222         case AR5416_DEVID_AR9287_PCIE:
1223                 ah = ath9k_hw_do_attach(devid, sc, error);
1224                 break;
1225         default:
1226                 *error = -EOPNOTSUPP;
1227                 break;
1228         }
1229
1230         return ah;
1231 }
1232
1233 /*******/
1234 /* INI */
1235 /*******/
1236
1237 static void ath9k_hw_override_ini(struct ath_hw *ah,
1238                                   struct ath9k_channel *chan)
1239 {
1240         /*
1241          * Set the RX_ABORT and RX_DIS and clear if off only after
1242          * RXE is set for MAC. This prevents frames with corrupted
1243          * descriptor status.
1244          */
1245         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1246
1247
1248         if (!AR_SREV_5416_20_OR_LATER(ah) ||
1249             AR_SREV_9280_10_OR_LATER(ah))
1250                 return;
1251
1252         REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1253 }
1254
1255 static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1256                               struct ar5416_eeprom_def *pEepData,
1257                               u32 reg, u32 value)
1258 {
1259         struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1260
1261         switch (ah->hw_version.devid) {
1262         case AR9280_DEVID_PCI:
1263                 if (reg == 0x7894) {
1264                         DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1265                                 "ini VAL: %x  EEPROM: %x\n", value,
1266                                 (pBase->version & 0xff));
1267
1268                         if ((pBase->version & 0xff) > 0x0a) {
1269                                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1270                                         "PWDCLKIND: %d\n",
1271                                         pBase->pwdclkind);
1272                                 value &= ~AR_AN_TOP2_PWDCLKIND;
1273                                 value |= AR_AN_TOP2_PWDCLKIND &
1274                                         (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1275                         } else {
1276                                 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1277                                         "PWDCLKIND Earlier Rev\n");
1278                         }
1279
1280                         DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1281                                 "final ini VAL: %x\n", value);
1282                 }
1283                 break;
1284         }
1285
1286         return value;
1287 }
1288
1289 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1290                               struct ar5416_eeprom_def *pEepData,
1291                               u32 reg, u32 value)
1292 {
1293         if (ah->eep_map == EEP_MAP_4KBITS)
1294                 return value;
1295         else
1296                 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1297 }
1298
1299 static void ath9k_olc_init(struct ath_hw *ah)
1300 {
1301         u32 i;
1302
1303         for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1304                 ah->originalGain[i] =
1305                         MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1306                                         AR_PHY_TX_GAIN);
1307         ah->PDADCdelta = 0;
1308 }
1309
1310 static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1311                               struct ath9k_channel *chan)
1312 {
1313         u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1314
1315         if (IS_CHAN_B(chan))
1316                 ctl |= CTL_11B;
1317         else if (IS_CHAN_G(chan))
1318                 ctl |= CTL_11G;
1319         else
1320                 ctl |= CTL_11A;
1321
1322         return ctl;
1323 }
1324
1325 static int ath9k_hw_process_ini(struct ath_hw *ah,
1326                                 struct ath9k_channel *chan,
1327                                 enum ath9k_ht_macmode macmode)
1328 {
1329         int i, regWrites = 0;
1330         struct ieee80211_channel *channel = chan->chan;
1331         u32 modesIndex, freqIndex;
1332
1333         switch (chan->chanmode) {
1334         case CHANNEL_A:
1335         case CHANNEL_A_HT20:
1336                 modesIndex = 1;
1337                 freqIndex = 1;
1338                 break;
1339         case CHANNEL_A_HT40PLUS:
1340         case CHANNEL_A_HT40MINUS:
1341                 modesIndex = 2;
1342                 freqIndex = 1;
1343                 break;
1344         case CHANNEL_G:
1345         case CHANNEL_G_HT20:
1346         case CHANNEL_B:
1347                 modesIndex = 4;
1348                 freqIndex = 2;
1349                 break;
1350         case CHANNEL_G_HT40PLUS:
1351         case CHANNEL_G_HT40MINUS:
1352                 modesIndex = 3;
1353                 freqIndex = 2;
1354                 break;
1355
1356         default:
1357                 return -EINVAL;
1358         }
1359
1360         REG_WRITE(ah, AR_PHY(0), 0x00000007);
1361         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1362         ah->eep_ops->set_addac(ah, chan);
1363
1364         if (AR_SREV_5416_22_OR_LATER(ah)) {
1365                 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1366         } else {
1367                 struct ar5416IniArray temp;
1368                 u32 addacSize =
1369                         sizeof(u32) * ah->iniAddac.ia_rows *
1370                         ah->iniAddac.ia_columns;
1371
1372                 memcpy(ah->addac5416_21,
1373                        ah->iniAddac.ia_array, addacSize);
1374
1375                 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1376
1377                 temp.ia_array = ah->addac5416_21;
1378                 temp.ia_columns = ah->iniAddac.ia_columns;
1379                 temp.ia_rows = ah->iniAddac.ia_rows;
1380                 REG_WRITE_ARRAY(&temp, 1, regWrites);
1381         }
1382
1383         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1384
1385         for (i = 0; i < ah->iniModes.ia_rows; i++) {
1386                 u32 reg = INI_RA(&ah->iniModes, i, 0);
1387                 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1388
1389                 REG_WRITE(ah, reg, val);
1390
1391                 if (reg >= 0x7800 && reg < 0x78a0
1392                     && ah->config.analog_shiftreg) {
1393                         udelay(100);
1394                 }
1395
1396                 DO_DELAY(regWrites);
1397         }
1398
1399         if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
1400                 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1401
1402         if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1403             AR_SREV_9287_10_OR_LATER(ah))
1404                 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1405
1406         for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1407                 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1408                 u32 val = INI_RA(&ah->iniCommon, i, 1);
1409
1410                 REG_WRITE(ah, reg, val);
1411
1412                 if (reg >= 0x7800 && reg < 0x78a0
1413                     && ah->config.analog_shiftreg) {
1414                         udelay(100);
1415                 }
1416
1417                 DO_DELAY(regWrites);
1418         }
1419
1420         ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1421
1422         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1423                 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1424                                 regWrites);
1425         }
1426
1427         ath9k_hw_override_ini(ah, chan);
1428         ath9k_hw_set_regs(ah, chan, macmode);
1429         ath9k_hw_init_chain_masks(ah);
1430
1431         if (OLC_FOR_AR9280_20_LATER)
1432                 ath9k_olc_init(ah);
1433
1434         ah->eep_ops->set_txpower(ah, chan,
1435                                  ath9k_regd_get_ctl(&ah->regulatory, chan),
1436                                  channel->max_antenna_gain * 2,
1437                                  channel->max_power * 2,
1438                                  min((u32) MAX_RATE_POWER,
1439                                  (u32) ah->regulatory.power_limit));
1440
1441         if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1442                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1443                         "ar5416SetRfRegs failed\n");
1444                 return -EIO;
1445         }
1446
1447         return 0;
1448 }
1449
1450 /****************************************/
1451 /* Reset and Channel Switching Routines */
1452 /****************************************/
1453
1454 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1455 {
1456         u32 rfMode = 0;
1457
1458         if (chan == NULL)
1459                 return;
1460
1461         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1462                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1463
1464         if (!AR_SREV_9280_10_OR_LATER(ah))
1465                 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1466                         AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1467
1468         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1469                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1470
1471         REG_WRITE(ah, AR_PHY_MODE, rfMode);
1472 }
1473
1474 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1475 {
1476         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1477 }
1478
1479 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1480 {
1481         u32 regval;
1482
1483         regval = REG_READ(ah, AR_AHB_MODE);
1484         REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1485
1486         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1487         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1488
1489         REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1490
1491         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1492         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1493
1494         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1495
1496         if (AR_SREV_9285(ah)) {
1497                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1498                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1499         } else {
1500                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1501                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1502         }
1503 }
1504
1505 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1506 {
1507         u32 val;
1508
1509         val = REG_READ(ah, AR_STA_ID1);
1510         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1511         switch (opmode) {
1512         case NL80211_IFTYPE_AP:
1513                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1514                           | AR_STA_ID1_KSRCH_MODE);
1515                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1516                 break;
1517         case NL80211_IFTYPE_ADHOC:
1518         case NL80211_IFTYPE_MESH_POINT:
1519                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1520                           | AR_STA_ID1_KSRCH_MODE);
1521                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1522                 break;
1523         case NL80211_IFTYPE_STATION:
1524         case NL80211_IFTYPE_MONITOR:
1525                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1526                 break;
1527         }
1528 }
1529
1530 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1531                                                  u32 coef_scaled,
1532                                                  u32 *coef_mantissa,
1533                                                  u32 *coef_exponent)
1534 {
1535         u32 coef_exp, coef_man;
1536
1537         for (coef_exp = 31; coef_exp > 0; coef_exp--)
1538                 if ((coef_scaled >> coef_exp) & 0x1)
1539                         break;
1540
1541         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1542
1543         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1544
1545         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1546         *coef_exponent = coef_exp - 16;
1547 }
1548
1549 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1550                                      struct ath9k_channel *chan)
1551 {
1552         u32 coef_scaled, ds_coef_exp, ds_coef_man;
1553         u32 clockMhzScaled = 0x64000000;
1554         struct chan_centers centers;
1555
1556         if (IS_CHAN_HALF_RATE(chan))
1557                 clockMhzScaled = clockMhzScaled >> 1;
1558         else if (IS_CHAN_QUARTER_RATE(chan))
1559                 clockMhzScaled = clockMhzScaled >> 2;
1560
1561         ath9k_hw_get_channel_centers(ah, chan, &centers);
1562         coef_scaled = clockMhzScaled / centers.synth_center;
1563
1564         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1565                                       &ds_coef_exp);
1566
1567         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1568                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1569         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1570                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1571
1572         coef_scaled = (9 * coef_scaled) / 10;
1573
1574         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1575                                       &ds_coef_exp);
1576
1577         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1578                       AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1579         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1580                       AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1581 }
1582
1583 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1584 {
1585         u32 rst_flags;
1586         u32 tmpReg;
1587
1588         if (AR_SREV_9100(ah)) {
1589                 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1590                 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1591                 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1592                 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1593                 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1594         }
1595
1596         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1597                   AR_RTC_FORCE_WAKE_ON_INT);
1598
1599         if (AR_SREV_9100(ah)) {
1600                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1601                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1602         } else {
1603                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1604                 if (tmpReg &
1605                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
1606                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1607                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1608                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1609                 } else {
1610                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1611                 }
1612
1613                 rst_flags = AR_RTC_RC_MAC_WARM;
1614                 if (type == ATH9K_RESET_COLD)
1615                         rst_flags |= AR_RTC_RC_MAC_COLD;
1616         }
1617
1618         REG_WRITE(ah, AR_RTC_RC, rst_flags);
1619         udelay(50);
1620
1621         REG_WRITE(ah, AR_RTC_RC, 0);
1622         if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1623                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1624                         "RTC stuck in MAC reset\n");
1625                 return false;
1626         }
1627
1628         if (!AR_SREV_9100(ah))
1629                 REG_WRITE(ah, AR_RC, 0);
1630
1631         ath9k_hw_init_pll(ah, NULL);
1632
1633         if (AR_SREV_9100(ah))
1634                 udelay(50);
1635
1636         return true;
1637 }
1638
1639 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1640 {
1641         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1642                   AR_RTC_FORCE_WAKE_ON_INT);
1643
1644         REG_WRITE(ah, AR_RTC_RESET, 0);
1645         udelay(2);
1646         REG_WRITE(ah, AR_RTC_RESET, 1);
1647
1648         if (!ath9k_hw_wait(ah,
1649                            AR_RTC_STATUS,
1650                            AR_RTC_STATUS_M,
1651                            AR_RTC_STATUS_ON,
1652                            AH_WAIT_TIMEOUT)) {
1653                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
1654                 return false;
1655         }
1656
1657         ath9k_hw_read_revisions(ah);
1658
1659         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1660 }
1661
1662 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1663 {
1664         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1665                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1666
1667         switch (type) {
1668         case ATH9K_RESET_POWER_ON:
1669                 return ath9k_hw_set_reset_power_on(ah);
1670         case ATH9K_RESET_WARM:
1671         case ATH9K_RESET_COLD:
1672                 return ath9k_hw_set_reset(ah, type);
1673         default:
1674                 return false;
1675         }
1676 }
1677
1678 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
1679                               enum ath9k_ht_macmode macmode)
1680 {
1681         u32 phymode;
1682         u32 enableDacFifo = 0;
1683
1684         if (AR_SREV_9285_10_OR_LATER(ah))
1685                 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1686                                          AR_PHY_FC_ENABLE_DAC_FIFO);
1687
1688         phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1689                 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1690
1691         if (IS_CHAN_HT40(chan)) {
1692                 phymode |= AR_PHY_FC_DYN2040_EN;
1693
1694                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1695                     (chan->chanmode == CHANNEL_G_HT40PLUS))
1696                         phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1697
1698                 if (ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1699                         phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1700         }
1701         REG_WRITE(ah, AR_PHY_TURBO, phymode);
1702
1703         ath9k_hw_set11nmac2040(ah, macmode);
1704
1705         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1706         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1707 }
1708
1709 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1710                                 struct ath9k_channel *chan)
1711 {
1712         if (OLC_FOR_AR9280_20_LATER) {
1713                 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1714                         return false;
1715         } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1716                 return false;
1717
1718         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1719                 return false;
1720
1721         ah->chip_fullsleep = false;
1722         ath9k_hw_init_pll(ah, chan);
1723         ath9k_hw_set_rfmode(ah, chan);
1724
1725         return true;
1726 }
1727
1728 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1729                                     struct ath9k_channel *chan,
1730                                     enum ath9k_ht_macmode macmode)
1731 {
1732         struct ieee80211_channel *channel = chan->chan;
1733         u32 synthDelay, qnum;
1734
1735         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1736                 if (ath9k_hw_numtxpending(ah, qnum)) {
1737                         DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1738                                 "Transmit frames pending on queue %d\n", qnum);
1739                         return false;
1740                 }
1741         }
1742
1743         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1744         if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1745                            AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1746                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1747                         "Could not kill baseband RX\n");
1748                 return false;
1749         }
1750
1751         ath9k_hw_set_regs(ah, chan, macmode);
1752
1753         if (AR_SREV_9280_10_OR_LATER(ah)) {
1754                 ath9k_hw_ar9280_set_channel(ah, chan);
1755         } else {
1756                 if (!(ath9k_hw_set_channel(ah, chan))) {
1757                         DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1758                                 "Failed to set channel\n");
1759                         return false;
1760                 }
1761         }
1762
1763         ah->eep_ops->set_txpower(ah, chan,
1764                              ath9k_regd_get_ctl(&ah->regulatory, chan),
1765                              channel->max_antenna_gain * 2,
1766                              channel->max_power * 2,
1767                              min((u32) MAX_RATE_POWER,
1768                              (u32) ah->regulatory.power_limit));
1769
1770         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1771         if (IS_CHAN_B(chan))
1772                 synthDelay = (4 * synthDelay) / 22;
1773         else
1774                 synthDelay /= 10;
1775
1776         udelay(synthDelay + BASE_ACTIVATE_DELAY);
1777
1778         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1779
1780         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1781                 ath9k_hw_set_delta_slope(ah, chan);
1782
1783         if (AR_SREV_9280_10_OR_LATER(ah))
1784                 ath9k_hw_9280_spur_mitigate(ah, chan);
1785         else
1786                 ath9k_hw_spur_mitigate(ah, chan);
1787
1788         if (!chan->oneTimeCalsDone)
1789                 chan->oneTimeCalsDone = true;
1790
1791         return true;
1792 }
1793
1794 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1795 {
1796         int bb_spur = AR_NO_SPUR;
1797         int freq;
1798         int bin, cur_bin;
1799         int bb_spur_off, spur_subchannel_sd;
1800         int spur_freq_sd;
1801         int spur_delta_phase;
1802         int denominator;
1803         int upper, lower, cur_vit_mask;
1804         int tmp, newVal;
1805         int i;
1806         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1807                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1808         };
1809         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1810                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1811         };
1812         int inc[4] = { 0, 100, 0, 0 };
1813         struct chan_centers centers;
1814
1815         int8_t mask_m[123];
1816         int8_t mask_p[123];
1817         int8_t mask_amt;
1818         int tmp_mask;
1819         int cur_bb_spur;
1820         bool is2GHz = IS_CHAN_2GHZ(chan);
1821
1822         memset(&mask_m, 0, sizeof(int8_t) * 123);
1823         memset(&mask_p, 0, sizeof(int8_t) * 123);
1824
1825         ath9k_hw_get_channel_centers(ah, chan, &centers);
1826         freq = centers.synth_center;
1827
1828         ah->config.spurmode = SPUR_ENABLE_EEPROM;
1829         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1830                 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1831
1832                 if (is2GHz)
1833                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1834                 else
1835                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1836
1837                 if (AR_NO_SPUR == cur_bb_spur)
1838                         break;
1839                 cur_bb_spur = cur_bb_spur - freq;
1840
1841                 if (IS_CHAN_HT40(chan)) {
1842                         if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1843                             (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1844                                 bb_spur = cur_bb_spur;
1845                                 break;
1846                         }
1847                 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1848                            (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1849                         bb_spur = cur_bb_spur;
1850                         break;
1851                 }
1852         }
1853
1854         if (AR_NO_SPUR == bb_spur) {
1855                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1856                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1857                 return;
1858         } else {
1859                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1860                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1861         }
1862
1863         bin = bb_spur * 320;
1864
1865         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1866
1867         newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1868                         AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1869                         AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1870                         AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1871         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1872
1873         newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1874                   AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1875                   AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1876                   AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1877                   SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1878         REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1879
1880         if (IS_CHAN_HT40(chan)) {
1881                 if (bb_spur < 0) {
1882                         spur_subchannel_sd = 1;
1883                         bb_spur_off = bb_spur + 10;
1884                 } else {
1885                         spur_subchannel_sd = 0;
1886                         bb_spur_off = bb_spur - 10;
1887                 }
1888         } else {
1889                 spur_subchannel_sd = 0;
1890                 bb_spur_off = bb_spur;
1891         }
1892
1893         if (IS_CHAN_HT40(chan))
1894                 spur_delta_phase =
1895                         ((bb_spur * 262144) /
1896                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1897         else
1898                 spur_delta_phase =
1899                         ((bb_spur * 524288) /
1900                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1901
1902         denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1903         spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1904
1905         newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1906                   SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1907                   SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1908         REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1909
1910         newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1911         REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1912
1913         cur_bin = -6000;
1914         upper = bin + 100;
1915         lower = bin - 100;
1916
1917         for (i = 0; i < 4; i++) {
1918                 int pilot_mask = 0;
1919                 int chan_mask = 0;
1920                 int bp = 0;
1921                 for (bp = 0; bp < 30; bp++) {
1922                         if ((cur_bin > lower) && (cur_bin < upper)) {
1923                                 pilot_mask = pilot_mask | 0x1 << bp;
1924                                 chan_mask = chan_mask | 0x1 << bp;
1925                         }
1926                         cur_bin += 100;
1927                 }
1928                 cur_bin += inc[i];
1929                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1930                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1931         }
1932
1933         cur_vit_mask = 6100;
1934         upper = bin + 120;
1935         lower = bin - 120;
1936
1937         for (i = 0; i < 123; i++) {
1938                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1939
1940                         /* workaround for gcc bug #37014 */
1941                         volatile int tmp_v = abs(cur_vit_mask - bin);
1942
1943                         if (tmp_v < 75)
1944                                 mask_amt = 1;
1945                         else
1946                                 mask_amt = 0;
1947                         if (cur_vit_mask < 0)
1948                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1949                         else
1950                                 mask_p[cur_vit_mask / 100] = mask_amt;
1951                 }
1952                 cur_vit_mask -= 100;
1953         }
1954
1955         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1956                 | (mask_m[48] << 26) | (mask_m[49] << 24)
1957                 | (mask_m[50] << 22) | (mask_m[51] << 20)
1958                 | (mask_m[52] << 18) | (mask_m[53] << 16)
1959                 | (mask_m[54] << 14) | (mask_m[55] << 12)
1960                 | (mask_m[56] << 10) | (mask_m[57] << 8)
1961                 | (mask_m[58] << 6) | (mask_m[59] << 4)
1962                 | (mask_m[60] << 2) | (mask_m[61] << 0);
1963         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1964         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1965
1966         tmp_mask = (mask_m[31] << 28)
1967                 | (mask_m[32] << 26) | (mask_m[33] << 24)
1968                 | (mask_m[34] << 22) | (mask_m[35] << 20)
1969                 | (mask_m[36] << 18) | (mask_m[37] << 16)
1970                 | (mask_m[48] << 14) | (mask_m[39] << 12)
1971                 | (mask_m[40] << 10) | (mask_m[41] << 8)
1972                 | (mask_m[42] << 6) | (mask_m[43] << 4)
1973                 | (mask_m[44] << 2) | (mask_m[45] << 0);
1974         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1975         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1976
1977         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1978                 | (mask_m[18] << 26) | (mask_m[18] << 24)
1979                 | (mask_m[20] << 22) | (mask_m[20] << 20)
1980                 | (mask_m[22] << 18) | (mask_m[22] << 16)
1981                 | (mask_m[24] << 14) | (mask_m[24] << 12)
1982                 | (mask_m[25] << 10) | (mask_m[26] << 8)
1983                 | (mask_m[27] << 6) | (mask_m[28] << 4)
1984                 | (mask_m[29] << 2) | (mask_m[30] << 0);
1985         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1986         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1987
1988         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1989                 | (mask_m[2] << 26) | (mask_m[3] << 24)
1990                 | (mask_m[4] << 22) | (mask_m[5] << 20)
1991                 | (mask_m[6] << 18) | (mask_m[7] << 16)
1992                 | (mask_m[8] << 14) | (mask_m[9] << 12)
1993                 | (mask_m[10] << 10) | (mask_m[11] << 8)
1994                 | (mask_m[12] << 6) | (mask_m[13] << 4)
1995                 | (mask_m[14] << 2) | (mask_m[15] << 0);
1996         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
1997         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
1998
1999         tmp_mask = (mask_p[15] << 28)
2000                 | (mask_p[14] << 26) | (mask_p[13] << 24)
2001                 | (mask_p[12] << 22) | (mask_p[11] << 20)
2002                 | (mask_p[10] << 18) | (mask_p[9] << 16)
2003                 | (mask_p[8] << 14) | (mask_p[7] << 12)
2004                 | (mask_p[6] << 10) | (mask_p[5] << 8)
2005                 | (mask_p[4] << 6) | (mask_p[3] << 4)
2006                 | (mask_p[2] << 2) | (mask_p[1] << 0);
2007         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2008         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2009
2010         tmp_mask = (mask_p[30] << 28)
2011                 | (mask_p[29] << 26) | (mask_p[28] << 24)
2012                 | (mask_p[27] << 22) | (mask_p[26] << 20)
2013                 | (mask_p[25] << 18) | (mask_p[24] << 16)
2014                 | (mask_p[23] << 14) | (mask_p[22] << 12)
2015                 | (mask_p[21] << 10) | (mask_p[20] << 8)
2016                 | (mask_p[19] << 6) | (mask_p[18] << 4)
2017                 | (mask_p[17] << 2) | (mask_p[16] << 0);
2018         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2019         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2020
2021         tmp_mask = (mask_p[45] << 28)
2022                 | (mask_p[44] << 26) | (mask_p[43] << 24)
2023                 | (mask_p[42] << 22) | (mask_p[41] << 20)
2024                 | (mask_p[40] << 18) | (mask_p[39] << 16)
2025                 | (mask_p[38] << 14) | (mask_p[37] << 12)
2026                 | (mask_p[36] << 10) | (mask_p[35] << 8)
2027                 | (mask_p[34] << 6) | (mask_p[33] << 4)
2028                 | (mask_p[32] << 2) | (mask_p[31] << 0);
2029         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2030         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2031
2032         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2033                 | (mask_p[59] << 26) | (mask_p[58] << 24)
2034                 | (mask_p[57] << 22) | (mask_p[56] << 20)
2035                 | (mask_p[55] << 18) | (mask_p[54] << 16)
2036                 | (mask_p[53] << 14) | (mask_p[52] << 12)
2037                 | (mask_p[51] << 10) | (mask_p[50] << 8)
2038                 | (mask_p[49] << 6) | (mask_p[48] << 4)
2039                 | (mask_p[47] << 2) | (mask_p[46] << 0);
2040         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2041         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2042 }
2043
2044 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
2045 {
2046         int bb_spur = AR_NO_SPUR;
2047         int bin, cur_bin;
2048         int spur_freq_sd;
2049         int spur_delta_phase;
2050         int denominator;
2051         int upper, lower, cur_vit_mask;
2052         int tmp, new;
2053         int i;
2054         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
2055                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
2056         };
2057         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
2058                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
2059         };
2060         int inc[4] = { 0, 100, 0, 0 };
2061
2062         int8_t mask_m[123];
2063         int8_t mask_p[123];
2064         int8_t mask_amt;
2065         int tmp_mask;
2066         int cur_bb_spur;
2067         bool is2GHz = IS_CHAN_2GHZ(chan);
2068
2069         memset(&mask_m, 0, sizeof(int8_t) * 123);
2070         memset(&mask_p, 0, sizeof(int8_t) * 123);
2071
2072         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2073                 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
2074                 if (AR_NO_SPUR == cur_bb_spur)
2075                         break;
2076                 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2077                 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2078                         bb_spur = cur_bb_spur;
2079                         break;
2080                 }
2081         }
2082
2083         if (AR_NO_SPUR == bb_spur)
2084                 return;
2085
2086         bin = bb_spur * 32;
2087
2088         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2089         new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2090                      AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2091                      AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2092                      AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2093
2094         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2095
2096         new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2097                AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2098                AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2099                AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2100                SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2101         REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2102
2103         spur_delta_phase = ((bb_spur * 524288) / 100) &
2104                 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2105
2106         denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2107         spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2108
2109         new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2110                SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2111                SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2112         REG_WRITE(ah, AR_PHY_TIMING11, new);
2113
2114         cur_bin = -6000;
2115         upper = bin + 100;
2116         lower = bin - 100;
2117
2118         for (i = 0; i < 4; i++) {
2119                 int pilot_mask = 0;
2120                 int chan_mask = 0;
2121                 int bp = 0;
2122                 for (bp = 0; bp < 30; bp++) {
2123                         if ((cur_bin > lower) && (cur_bin < upper)) {
2124                                 pilot_mask = pilot_mask | 0x1 << bp;
2125                                 chan_mask = chan_mask | 0x1 << bp;
2126                         }
2127                         cur_bin += 100;
2128                 }
2129                 cur_bin += inc[i];
2130                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2131                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2132         }
2133
2134         cur_vit_mask = 6100;
2135         upper = bin + 120;
2136         lower = bin - 120;
2137
2138         for (i = 0; i < 123; i++) {
2139                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2140
2141                         /* workaround for gcc bug #37014 */
2142                         volatile int tmp_v = abs(cur_vit_mask - bin);
2143
2144                         if (tmp_v < 75)
2145                                 mask_amt = 1;
2146                         else
2147                                 mask_amt = 0;
2148                         if (cur_vit_mask < 0)
2149                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2150                         else
2151                                 mask_p[cur_vit_mask / 100] = mask_amt;
2152                 }
2153                 cur_vit_mask -= 100;
2154         }
2155
2156         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2157                 | (mask_m[48] << 26) | (mask_m[49] << 24)
2158                 | (mask_m[50] << 22) | (mask_m[51] << 20)
2159                 | (mask_m[52] << 18) | (mask_m[53] << 16)
2160                 | (mask_m[54] << 14) | (mask_m[55] << 12)
2161                 | (mask_m[56] << 10) | (mask_m[57] << 8)
2162                 | (mask_m[58] << 6) | (mask_m[59] << 4)
2163                 | (mask_m[60] << 2) | (mask_m[61] << 0);
2164         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2165         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2166
2167         tmp_mask = (mask_m[31] << 28)
2168                 | (mask_m[32] << 26) | (mask_m[33] << 24)
2169                 | (mask_m[34] << 22) | (mask_m[35] << 20)
2170                 | (mask_m[36] << 18) | (mask_m[37] << 16)
2171                 | (mask_m[48] << 14) | (mask_m[39] << 12)
2172                 | (mask_m[40] << 10) | (mask_m[41] << 8)
2173                 | (mask_m[42] << 6) | (mask_m[43] << 4)
2174                 | (mask_m[44] << 2) | (mask_m[45] << 0);
2175         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2176         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2177
2178         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2179                 | (mask_m[18] << 26) | (mask_m[18] << 24)
2180                 | (mask_m[20] << 22) | (mask_m[20] << 20)
2181                 | (mask_m[22] << 18) | (mask_m[22] << 16)
2182                 | (mask_m[24] << 14) | (mask_m[24] << 12)
2183                 | (mask_m[25] << 10) | (mask_m[26] << 8)
2184                 | (mask_m[27] << 6) | (mask_m[28] << 4)
2185                 | (mask_m[29] << 2) | (mask_m[30] << 0);
2186         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2187         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2188
2189         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2190                 | (mask_m[2] << 26) | (mask_m[3] << 24)
2191                 | (mask_m[4] << 22) | (mask_m[5] << 20)
2192                 | (mask_m[6] << 18) | (mask_m[7] << 16)
2193                 | (mask_m[8] << 14) | (mask_m[9] << 12)
2194                 | (mask_m[10] << 10) | (mask_m[11] << 8)
2195                 | (mask_m[12] << 6) | (mask_m[13] << 4)
2196                 | (mask_m[14] << 2) | (mask_m[15] << 0);
2197         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2198         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2199
2200         tmp_mask = (mask_p[15] << 28)
2201                 | (mask_p[14] << 26) | (mask_p[13] << 24)
2202                 | (mask_p[12] << 22) | (mask_p[11] << 20)
2203                 | (mask_p[10] << 18) | (mask_p[9] << 16)
2204                 | (mask_p[8] << 14) | (mask_p[7] << 12)
2205                 | (mask_p[6] << 10) | (mask_p[5] << 8)
2206                 | (mask_p[4] << 6) | (mask_p[3] << 4)
2207                 | (mask_p[2] << 2) | (mask_p[1] << 0);
2208         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2209         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2210
2211         tmp_mask = (mask_p[30] << 28)
2212                 | (mask_p[29] << 26) | (mask_p[28] << 24)
2213                 | (mask_p[27] << 22) | (mask_p[26] << 20)
2214                 | (mask_p[25] << 18) | (mask_p[24] << 16)
2215                 | (mask_p[23] << 14) | (mask_p[22] << 12)
2216                 | (mask_p[21] << 10) | (mask_p[20] << 8)
2217                 | (mask_p[19] << 6) | (mask_p[18] << 4)
2218                 | (mask_p[17] << 2) | (mask_p[16] << 0);
2219         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2220         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2221
2222         tmp_mask = (mask_p[45] << 28)
2223                 | (mask_p[44] << 26) | (mask_p[43] << 24)
2224                 | (mask_p[42] << 22) | (mask_p[41] << 20)
2225                 | (mask_p[40] << 18) | (mask_p[39] << 16)
2226                 | (mask_p[38] << 14) | (mask_p[37] << 12)
2227                 | (mask_p[36] << 10) | (mask_p[35] << 8)
2228                 | (mask_p[34] << 6) | (mask_p[33] << 4)
2229                 | (mask_p[32] << 2) | (mask_p[31] << 0);
2230         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2231         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2232
2233         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2234                 | (mask_p[59] << 26) | (mask_p[58] << 24)
2235                 | (mask_p[57] << 22) | (mask_p[56] << 20)
2236                 | (mask_p[55] << 18) | (mask_p[54] << 16)
2237                 | (mask_p[53] << 14) | (mask_p[52] << 12)
2238                 | (mask_p[51] << 10) | (mask_p[50] << 8)
2239                 | (mask_p[49] << 6) | (mask_p[48] << 4)
2240                 | (mask_p[47] << 2) | (mask_p[46] << 0);
2241         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2242         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2243 }
2244
2245 static void ath9k_enable_rfkill(struct ath_hw *ah)
2246 {
2247         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
2248                     AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
2249
2250         REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
2251                     AR_GPIO_INPUT_MUX2_RFSILENT);
2252
2253         ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
2254         REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
2255 }
2256
2257 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2258                     bool bChannelChange)
2259 {
2260         u32 saveLedState;
2261         struct ath_softc *sc = ah->ah_sc;
2262         struct ath9k_channel *curchan = ah->curchan;
2263         u32 saveDefAntenna;
2264         u32 macStaId1;
2265         int i, rx_chainmask, r;
2266
2267         ah->extprotspacing = sc->ht_extprotspacing;
2268         ah->txchainmask = sc->tx_chainmask;
2269         ah->rxchainmask = sc->rx_chainmask;
2270
2271         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2272                 return -EIO;
2273
2274         if (curchan)
2275                 ath9k_hw_getnf(ah, curchan);
2276
2277         if (bChannelChange &&
2278             (ah->chip_fullsleep != true) &&
2279             (ah->curchan != NULL) &&
2280             (chan->channel != ah->curchan->channel) &&
2281             ((chan->channelFlags & CHANNEL_ALL) ==
2282              (ah->curchan->channelFlags & CHANNEL_ALL)) &&
2283             (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2284                                    !IS_CHAN_A_5MHZ_SPACED(ah->curchan)))) {
2285
2286                 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
2287                         ath9k_hw_loadnf(ah, ah->curchan);
2288                         ath9k_hw_start_nfcal(ah);
2289                         return 0;
2290                 }
2291         }
2292
2293         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2294         if (saveDefAntenna == 0)
2295                 saveDefAntenna = 1;
2296
2297         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2298
2299         saveLedState = REG_READ(ah, AR_CFG_LED) &
2300                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2301                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2302
2303         ath9k_hw_mark_phy_inactive(ah);
2304
2305         if (!ath9k_hw_chip_reset(ah, chan)) {
2306                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Chip reset failed\n");
2307                 return -EINVAL;
2308         }
2309
2310         if (AR_SREV_9280_10_OR_LATER(ah))
2311                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
2312
2313         if (AR_SREV_9287_10_OR_LATER(ah)) {
2314                 /* Enable ASYNC FIFO */
2315                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2316                                 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
2317                 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
2318                 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2319                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2320                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2321                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2322         }
2323         r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
2324         if (r)
2325                 return r;
2326
2327         /* Setup MFP options for CCMP */
2328         if (AR_SREV_9280_20_OR_LATER(ah)) {
2329                 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2330                  * frames when constructing CCMP AAD. */
2331                 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2332                               0xc7ff);
2333                 ah->sw_mgmt_crypto = false;
2334         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2335                 /* Disable hardware crypto for management frames */
2336                 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2337                             AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2338                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2339                             AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2340                 ah->sw_mgmt_crypto = true;
2341         } else
2342                 ah->sw_mgmt_crypto = true;
2343
2344         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2345                 ath9k_hw_set_delta_slope(ah, chan);
2346
2347         if (AR_SREV_9280_10_OR_LATER(ah))
2348                 ath9k_hw_9280_spur_mitigate(ah, chan);
2349         else
2350                 ath9k_hw_spur_mitigate(ah, chan);
2351
2352         ah->eep_ops->set_board_values(ah, chan);
2353
2354         ath9k_hw_decrease_chain_power(ah, chan);
2355
2356         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ah->macaddr));
2357         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ah->macaddr + 4)
2358                   | macStaId1
2359                   | AR_STA_ID1_RTS_USE_DEF
2360                   | (ah->config.
2361                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2362                   | ah->sta_id1_defaults);
2363         ath9k_hw_set_operating_mode(ah, ah->opmode);
2364
2365         REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
2366         REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
2367
2368         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2369
2370         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
2371         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
2372                   ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2373
2374         REG_WRITE(ah, AR_ISR, ~0);
2375
2376         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2377
2378         if (AR_SREV_9280_10_OR_LATER(ah))
2379                 ath9k_hw_ar9280_set_channel(ah, chan);
2380         else
2381                 if (!(ath9k_hw_set_channel(ah, chan)))
2382                         return -EIO;
2383
2384         for (i = 0; i < AR_NUM_DCU; i++)
2385                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2386
2387         ah->intr_txqs = 0;
2388         for (i = 0; i < ah->caps.total_queues; i++)
2389                 ath9k_hw_resettxqueue(ah, i);
2390
2391         ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2392         ath9k_hw_init_qos(ah);
2393
2394         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2395                 ath9k_enable_rfkill(ah);
2396
2397         ath9k_hw_init_user_settings(ah);
2398
2399         if (AR_SREV_9287_10_OR_LATER(ah)) {
2400                 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
2401                           AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
2402                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
2403                           AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
2404                 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
2405                           AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
2406
2407                 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
2408                 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
2409
2410                 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2411                             AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2412                 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2413                               AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2414         }
2415         if (AR_SREV_9287_10_OR_LATER(ah)) {
2416                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2417                                 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2418         }
2419
2420         REG_WRITE(ah, AR_STA_ID1,
2421                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2422
2423         ath9k_hw_set_dma(ah);
2424
2425         REG_WRITE(ah, AR_OBS, 8);
2426
2427         if (ah->config.intr_mitigation) {
2428                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2429                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2430         }
2431
2432         ath9k_hw_init_bb(ah, chan);
2433
2434         if (!ath9k_hw_init_cal(ah, chan))
2435                 return -EIO;
2436
2437         rx_chainmask = ah->rxchainmask;
2438         if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2439                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2440                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2441         }
2442
2443         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2444
2445         if (AR_SREV_9100(ah)) {
2446                 u32 mask;
2447                 mask = REG_READ(ah, AR_CFG);
2448                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2449                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2450                                 "CFG Byte Swap Set 0x%x\n", mask);
2451                 } else {
2452                         mask =
2453                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2454                         REG_WRITE(ah, AR_CFG, mask);
2455                         DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2456                                 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2457                 }
2458         } else {
2459 #ifdef __BIG_ENDIAN
2460                 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2461 #endif
2462         }
2463
2464         return 0;
2465 }
2466
2467 /************************/
2468 /* Key Cache Management */
2469 /************************/
2470
2471 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2472 {
2473         u32 keyType;
2474
2475         if (entry >= ah->caps.keycache_size) {
2476                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2477                         "keychache entry %u out of range\n", entry);
2478                 return false;
2479         }
2480
2481         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2482
2483         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2484         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2485         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2486         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2487         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2488         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2489         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2490         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2491
2492         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2493                 u16 micentry = entry + 64;
2494
2495                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2496                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2497                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2498                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2499
2500         }
2501
2502         if (ah->curchan == NULL)
2503                 return true;
2504
2505         return true;
2506 }
2507
2508 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2509 {
2510         u32 macHi, macLo;
2511
2512         if (entry >= ah->caps.keycache_size) {
2513                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2514                         "keychache entry %u out of range\n", entry);
2515                 return false;
2516         }
2517
2518         if (mac != NULL) {
2519                 macHi = (mac[5] << 8) | mac[4];
2520                 macLo = (mac[3] << 24) |
2521                         (mac[2] << 16) |
2522                         (mac[1] << 8) |
2523                         mac[0];
2524                 macLo >>= 1;
2525                 macLo |= (macHi & 1) << 31;
2526                 macHi >>= 1;
2527         } else {
2528                 macLo = macHi = 0;
2529         }
2530         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2531         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2532
2533         return true;
2534 }
2535
2536 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2537                                  const struct ath9k_keyval *k,
2538                                  const u8 *mac)
2539 {
2540         const struct ath9k_hw_capabilities *pCap = &ah->caps;
2541         u32 key0, key1, key2, key3, key4;
2542         u32 keyType;
2543
2544         if (entry >= pCap->keycache_size) {
2545                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2546                         "keycache entry %u out of range\n", entry);
2547                 return false;
2548         }
2549
2550         switch (k->kv_type) {
2551         case ATH9K_CIPHER_AES_OCB:
2552                 keyType = AR_KEYTABLE_TYPE_AES;
2553                 break;
2554         case ATH9K_CIPHER_AES_CCM:
2555                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2556                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2557                                 "AES-CCM not supported by mac rev 0x%x\n",
2558                                 ah->hw_version.macRev);
2559                         return false;
2560                 }
2561                 keyType = AR_KEYTABLE_TYPE_CCM;
2562                 break;
2563         case ATH9K_CIPHER_TKIP:
2564                 keyType = AR_KEYTABLE_TYPE_TKIP;
2565                 if (ATH9K_IS_MIC_ENABLED(ah)
2566                     && entry + 64 >= pCap->keycache_size) {
2567                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2568                                 "entry %u inappropriate for TKIP\n", entry);
2569                         return false;
2570                 }
2571                 break;
2572         case ATH9K_CIPHER_WEP:
2573                 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
2574                         DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2575                                 "WEP key length %u too small\n", k->kv_len);
2576                         return false;
2577                 }
2578                 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
2579                         keyType = AR_KEYTABLE_TYPE_40;
2580                 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2581                         keyType = AR_KEYTABLE_TYPE_104;
2582                 else
2583                         keyType = AR_KEYTABLE_TYPE_128;
2584                 break;
2585         case ATH9K_CIPHER_CLR:
2586                 keyType = AR_KEYTABLE_TYPE_CLR;
2587                 break;
2588         default:
2589                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2590                         "cipher %u not supported\n", k->kv_type);
2591                 return false;
2592         }
2593
2594         key0 = get_unaligned_le32(k->kv_val + 0);
2595         key1 = get_unaligned_le16(k->kv_val + 4);
2596         key2 = get_unaligned_le32(k->kv_val + 6);
2597         key3 = get_unaligned_le16(k->kv_val + 10);
2598         key4 = get_unaligned_le32(k->kv_val + 12);
2599         if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2600                 key4 &= 0xff;
2601
2602         /*
2603          * Note: Key cache registers access special memory area that requires
2604          * two 32-bit writes to actually update the values in the internal
2605          * memory. Consequently, the exact order and pairs used here must be
2606          * maintained.
2607          */
2608
2609         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2610                 u16 micentry = entry + 64;
2611
2612                 /*
2613                  * Write inverted key[47:0] first to avoid Michael MIC errors
2614                  * on frames that could be sent or received at the same time.
2615                  * The correct key will be written in the end once everything
2616                  * else is ready.
2617                  */
2618                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2619                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2620
2621                 /* Write key[95:48] */
2622                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2623                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2624
2625                 /* Write key[127:96] and key type */
2626                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2627                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2628
2629                 /* Write MAC address for the entry */
2630                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2631
2632                 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2633                         /*
2634                          * TKIP uses two key cache entries:
2635                          * Michael MIC TX/RX keys in the same key cache entry
2636                          * (idx = main index + 64):
2637                          * key0 [31:0] = RX key [31:0]
2638                          * key1 [15:0] = TX key [31:16]
2639                          * key1 [31:16] = reserved
2640                          * key2 [31:0] = RX key [63:32]
2641                          * key3 [15:0] = TX key [15:0]
2642                          * key3 [31:16] = reserved
2643                          * key4 [31:0] = TX key [63:32]
2644                          */
2645                         u32 mic0, mic1, mic2, mic3, mic4;
2646
2647                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2648                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2649                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2650                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2651                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
2652
2653                         /* Write RX[31:0] and TX[31:16] */
2654                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2655                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2656
2657                         /* Write RX[63:32] and TX[15:0] */
2658                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2659                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2660
2661                         /* Write TX[63:32] and keyType(reserved) */
2662                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2663                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2664                                   AR_KEYTABLE_TYPE_CLR);
2665
2666                 } else {
2667                         /*
2668                          * TKIP uses four key cache entries (two for group
2669                          * keys):
2670                          * Michael MIC TX/RX keys are in different key cache
2671                          * entries (idx = main index + 64 for TX and
2672                          * main index + 32 + 96 for RX):
2673                          * key0 [31:0] = TX/RX MIC key [31:0]
2674                          * key1 [31:0] = reserved
2675                          * key2 [31:0] = TX/RX MIC key [63:32]
2676                          * key3 [31:0] = reserved
2677                          * key4 [31:0] = reserved
2678                          *
2679                          * Upper layer code will call this function separately
2680                          * for TX and RX keys when these registers offsets are
2681                          * used.
2682                          */
2683                         u32 mic0, mic2;
2684
2685                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2686                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2687
2688                         /* Write MIC key[31:0] */
2689                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2690                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2691
2692                         /* Write MIC key[63:32] */
2693                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2694                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2695
2696                         /* Write TX[63:32] and keyType(reserved) */
2697                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2698                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2699                                   AR_KEYTABLE_TYPE_CLR);
2700                 }
2701
2702                 /* MAC address registers are reserved for the MIC entry */
2703                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2704                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2705
2706                 /*
2707                  * Write the correct (un-inverted) key[47:0] last to enable
2708                  * TKIP now that all other registers are set with correct
2709                  * values.
2710                  */
2711                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2712                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2713         } else {
2714                 /* Write key[47:0] */
2715                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2716                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2717
2718                 /* Write key[95:48] */
2719                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2720                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2721
2722                 /* Write key[127:96] and key type */
2723                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2724                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2725
2726                 /* Write MAC address for the entry */
2727                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2728         }
2729
2730         return true;
2731 }
2732
2733 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2734 {
2735         if (entry < ah->caps.keycache_size) {
2736                 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2737                 if (val & AR_KEYTABLE_VALID)
2738                         return true;
2739         }
2740         return false;
2741 }
2742
2743 /******************************/
2744 /* Power Management (Chipset) */
2745 /******************************/
2746
2747 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2748 {
2749         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2750         if (setChip) {
2751                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2752                             AR_RTC_FORCE_WAKE_EN);
2753                 if (!AR_SREV_9100(ah))
2754                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2755
2756                 REG_CLR_BIT(ah, (AR_RTC_RESET),
2757                             AR_RTC_RESET_EN);
2758         }
2759 }
2760
2761 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2762 {
2763         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2764         if (setChip) {
2765                 struct ath9k_hw_capabilities *pCap = &ah->caps;
2766
2767                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2768                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2769                                   AR_RTC_FORCE_WAKE_ON_INT);
2770                 } else {
2771                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2772                                     AR_RTC_FORCE_WAKE_EN);
2773                 }
2774         }
2775 }
2776
2777 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2778 {
2779         u32 val;
2780         int i;
2781
2782         if (setChip) {
2783                 if ((REG_READ(ah, AR_RTC_STATUS) &
2784                      AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2785                         if (ath9k_hw_set_reset_reg(ah,
2786                                            ATH9K_RESET_POWER_ON) != true) {
2787                                 return false;
2788                         }
2789                 }
2790                 if (AR_SREV_9100(ah))
2791                         REG_SET_BIT(ah, AR_RTC_RESET,
2792                                     AR_RTC_RESET_EN);
2793
2794                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2795                             AR_RTC_FORCE_WAKE_EN);
2796                 udelay(50);
2797
2798                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2799                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2800                         if (val == AR_RTC_STATUS_ON)
2801                                 break;
2802                         udelay(50);
2803                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2804                                     AR_RTC_FORCE_WAKE_EN);
2805                 }
2806                 if (i == 0) {
2807                         DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2808                                 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
2809                         return false;
2810                 }
2811         }
2812
2813         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2814
2815         return true;
2816 }
2817
2818 static bool ath9k_hw_setpower_nolock(struct ath_hw *ah,
2819                                      enum ath9k_power_mode mode)
2820 {
2821         int status = true, setChip = true;
2822         static const char *modes[] = {
2823                 "AWAKE",
2824                 "FULL-SLEEP",
2825                 "NETWORK SLEEP",
2826                 "UNDEFINED"
2827         };
2828
2829         if (ah->power_mode == mode)
2830                 return status;
2831
2832         DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s -> %s\n",
2833                 modes[ah->power_mode], modes[mode]);
2834
2835         switch (mode) {
2836         case ATH9K_PM_AWAKE:
2837                 status = ath9k_hw_set_power_awake(ah, setChip);
2838                 break;
2839         case ATH9K_PM_FULL_SLEEP:
2840                 ath9k_set_power_sleep(ah, setChip);
2841                 ah->chip_fullsleep = true;
2842                 break;
2843         case ATH9K_PM_NETWORK_SLEEP:
2844                 ath9k_set_power_network_sleep(ah, setChip);
2845                 break;
2846         default:
2847                 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2848                         "Unknown power mode %u\n", mode);
2849                 return false;
2850         }
2851         ah->power_mode = mode;
2852
2853         return status;
2854 }
2855
2856 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2857 {
2858         unsigned long flags;
2859         bool ret;
2860
2861         spin_lock_irqsave(&ah->ah_sc->sc_pm_lock, flags);
2862         ret = ath9k_hw_setpower_nolock(ah, mode);
2863         spin_unlock_irqrestore(&ah->ah_sc->sc_pm_lock, flags);
2864
2865         return ret;
2866 }
2867
2868 void ath9k_ps_wakeup(struct ath_softc *sc)
2869 {
2870         unsigned long flags;
2871
2872         spin_lock_irqsave(&sc->sc_pm_lock, flags);
2873         if (++sc->ps_usecount != 1)
2874                 goto unlock;
2875
2876         ath9k_hw_setpower_nolock(sc->sc_ah, ATH9K_PM_AWAKE);
2877
2878  unlock:
2879         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2880 }
2881
2882 void ath9k_ps_restore(struct ath_softc *sc)
2883 {
2884         unsigned long flags;
2885
2886         spin_lock_irqsave(&sc->sc_pm_lock, flags);
2887         if (--sc->ps_usecount != 0)
2888                 goto unlock;
2889
2890         if (sc->ps_enabled &&
2891             !(sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
2892                               SC_OP_WAIT_FOR_CAB |
2893                               SC_OP_WAIT_FOR_PSPOLL_DATA |
2894                               SC_OP_WAIT_FOR_TX_ACK)))
2895                 ath9k_hw_setpower_nolock(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
2896
2897  unlock:
2898         spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2899 }
2900
2901 /*
2902  * Helper for ASPM support.
2903  *
2904  * Disable PLL when in L0s as well as receiver clock when in L1.
2905  * This power saving option must be enabled through the SerDes.
2906  *
2907  * Programming the SerDes must go through the same 288 bit serial shift
2908  * register as the other analog registers.  Hence the 9 writes.
2909  */
2910 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
2911 {
2912         u8 i;
2913
2914         if (ah->is_pciexpress != true)
2915                 return;
2916
2917         /* Do not touch SerDes registers */
2918         if (ah->config.pcie_powersave_enable == 2)
2919                 return;
2920
2921         /* Nothing to do on restore for 11N */
2922         if (restore)
2923                 return;
2924
2925         if (AR_SREV_9280_20_OR_LATER(ah)) {
2926                 /*
2927                  * AR9280 2.0 or later chips use SerDes values from the
2928                  * initvals.h initialized depending on chipset during
2929                  * ath9k_hw_do_attach()
2930                  */
2931                 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2932                         REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2933                                   INI_RA(&ah->iniPcieSerdes, i, 1));
2934                 }
2935         } else if (AR_SREV_9280(ah) &&
2936                    (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2937                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2938                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2939
2940                 /* RX shut off when elecidle is asserted */
2941                 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2942                 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2943                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2944
2945                 /* Shut off CLKREQ active in L1 */
2946                 if (ah->config.pcie_clock_req)
2947                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2948                 else
2949                         REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2950
2951                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2952                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2953                 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2954
2955                 /* Load the new settings */
2956                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2957
2958         } else {
2959                 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2960                 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2961
2962                 /* RX shut off when elecidle is asserted */
2963                 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2964                 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2965                 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2966
2967                 /*
2968                  * Ignore ah->ah_config.pcie_clock_req setting for
2969                  * pre-AR9280 11n
2970                  */
2971                 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2972
2973                 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2974                 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2975                 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2976
2977                 /* Load the new settings */
2978                 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2979         }
2980
2981         udelay(1000);
2982
2983         /* set bit 19 to allow forcing of pcie core into L1 state */
2984         REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2985
2986         /* Several PCIe massages to ensure proper behaviour */
2987         if (ah->config.pcie_waen) {
2988                 REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
2989         } else {
2990                 if (AR_SREV_9285(ah))
2991                         REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
2992                 /*
2993                  * On AR9280 chips bit 22 of 0x4004 needs to be set to
2994                  * otherwise card may disappear.
2995                  */
2996                 else if (AR_SREV_9280(ah))
2997                         REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
2998                 else
2999                         REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
3000         }
3001 }
3002
3003 /**********************/
3004 /* Interrupt Handling */
3005 /**********************/
3006
3007 bool ath9k_hw_intrpend(struct ath_hw *ah)
3008 {
3009         u32 host_isr;
3010
3011         if (AR_SREV_9100(ah))
3012                 return true;
3013
3014         host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
3015         if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
3016                 return true;
3017
3018         host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
3019         if ((host_isr & AR_INTR_SYNC_DEFAULT)
3020             && (host_isr != AR_INTR_SPURIOUS))
3021                 return true;
3022
3023         return false;
3024 }
3025
3026 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
3027 {
3028         u32 isr = 0;
3029         u32 mask2 = 0;
3030         struct ath9k_hw_capabilities *pCap = &ah->caps;
3031         u32 sync_cause = 0;
3032         bool fatal_int = false;
3033
3034         if (!AR_SREV_9100(ah)) {
3035                 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
3036                         if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
3037                             == AR_RTC_STATUS_ON) {
3038                                 isr = REG_READ(ah, AR_ISR);
3039                         }
3040                 }
3041
3042                 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
3043                         AR_INTR_SYNC_DEFAULT;
3044
3045                 *masked = 0;
3046
3047                 if (!isr && !sync_cause)
3048                         return false;
3049         } else {
3050                 *masked = 0;
3051                 isr = REG_READ(ah, AR_ISR);
3052         }
3053
3054         if (isr) {
3055                 if (isr & AR_ISR_BCNMISC) {
3056                         u32 isr2;
3057                         isr2 = REG_READ(ah, AR_ISR_S2);
3058                         if (isr2 & AR_ISR_S2_TIM)
3059                                 mask2 |= ATH9K_INT_TIM;
3060                         if (isr2 & AR_ISR_S2_DTIM)
3061                                 mask2 |= ATH9K_INT_DTIM;
3062                         if (isr2 & AR_ISR_S2_DTIMSYNC)
3063                                 mask2 |= ATH9K_INT_DTIMSYNC;
3064                         if (isr2 & (AR_ISR_S2_CABEND))
3065                                 mask2 |= ATH9K_INT_CABEND;
3066                         if (isr2 & AR_ISR_S2_GTT)
3067                                 mask2 |= ATH9K_INT_GTT;
3068                         if (isr2 & AR_ISR_S2_CST)
3069                                 mask2 |= ATH9K_INT_CST;
3070                         if (isr2 & AR_ISR_S2_TSFOOR)
3071                                 mask2 |= ATH9K_INT_TSFOOR;
3072                 }
3073
3074                 isr = REG_READ(ah, AR_ISR_RAC);
3075                 if (isr == 0xffffffff) {
3076                         *masked = 0;
3077                         return false;
3078                 }
3079
3080                 *masked = isr & ATH9K_INT_COMMON;
3081
3082                 if (ah->config.intr_mitigation) {
3083                         if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
3084                                 *masked |= ATH9K_INT_RX;
3085                 }
3086
3087                 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
3088                         *masked |= ATH9K_INT_RX;
3089                 if (isr &
3090                     (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
3091                      AR_ISR_TXEOL)) {
3092                         u32 s0_s, s1_s;
3093
3094                         *masked |= ATH9K_INT_TX;
3095
3096                         s0_s = REG_READ(ah, AR_ISR_S0_S);
3097                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
3098                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
3099
3100                         s1_s = REG_READ(ah, AR_ISR_S1_S);
3101                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
3102                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
3103                 }
3104
3105                 if (isr & AR_ISR_RXORN) {
3106                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3107                                 "receive FIFO overrun interrupt\n");
3108                 }
3109
3110                 if (!AR_SREV_9100(ah)) {
3111                         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3112                                 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
3113                                 if (isr5 & AR_ISR_S5_TIM_TIMER)
3114                                         *masked |= ATH9K_INT_TIM_TIMER;
3115                         }
3116                 }
3117
3118                 *masked |= mask2;
3119         }
3120
3121         if (AR_SREV_9100(ah))
3122                 return true;
3123
3124         if (sync_cause) {
3125                 fatal_int =
3126                         (sync_cause &
3127                          (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
3128                         ? true : false;
3129
3130                 if (fatal_int) {
3131                         if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
3132                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
3133                                         "received PCI FATAL interrupt\n");
3134                         }
3135                         if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
3136                                 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
3137                                         "received PCI PERR interrupt\n");
3138                         }
3139                         *masked |= ATH9K_INT_FATAL;
3140                 }
3141                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
3142                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3143                                 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
3144                         REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
3145                         REG_WRITE(ah, AR_RC, 0);
3146                         *masked |= ATH9K_INT_FATAL;
3147                 }
3148                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
3149                         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3150                                 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
3151                 }
3152
3153                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
3154                 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
3155         }
3156
3157         return true;
3158 }
3159
3160 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
3161 {
3162         u32 omask = ah->mask_reg;
3163         u32 mask, mask2;
3164         struct ath9k_hw_capabilities *pCap = &ah->caps;
3165
3166         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
3167
3168         if (omask & ATH9K_INT_GLOBAL) {
3169                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
3170                 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
3171                 (void) REG_READ(ah, AR_IER);
3172                 if (!AR_SREV_9100(ah)) {
3173                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
3174                         (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
3175
3176                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
3177                         (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
3178                 }
3179         }
3180
3181         mask = ints & ATH9K_INT_COMMON;
3182         mask2 = 0;
3183
3184         if (ints & ATH9K_INT_TX) {
3185                 if (ah->txok_interrupt_mask)
3186                         mask |= AR_IMR_TXOK;
3187                 if (ah->txdesc_interrupt_mask)
3188                         mask |= AR_IMR_TXDESC;
3189                 if (ah->txerr_interrupt_mask)
3190                         mask |= AR_IMR_TXERR;
3191                 if (ah->txeol_interrupt_mask)
3192                         mask |= AR_IMR_TXEOL;
3193         }
3194         if (ints & ATH9K_INT_RX) {
3195                 mask |= AR_IMR_RXERR;
3196                 if (ah->config.intr_mitigation)
3197                         mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
3198                 else
3199                         mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
3200                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
3201                         mask |= AR_IMR_GENTMR;
3202         }
3203
3204         if (ints & (ATH9K_INT_BMISC)) {
3205                 mask |= AR_IMR_BCNMISC;
3206                 if (ints & ATH9K_INT_TIM)
3207                         mask2 |= AR_IMR_S2_TIM;
3208                 if (ints & ATH9K_INT_DTIM)
3209                         mask2 |= AR_IMR_S2_DTIM;
3210                 if (ints & ATH9K_INT_DTIMSYNC)
3211                         mask2 |= AR_IMR_S2_DTIMSYNC;
3212                 if (ints & ATH9K_INT_CABEND)
3213                         mask2 |= AR_IMR_S2_CABEND;
3214                 if (ints & ATH9K_INT_TSFOOR)
3215                         mask2 |= AR_IMR_S2_TSFOOR;
3216         }
3217
3218         if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
3219                 mask |= AR_IMR_BCNMISC;
3220                 if (ints & ATH9K_INT_GTT)
3221                         mask2 |= AR_IMR_S2_GTT;
3222                 if (ints & ATH9K_INT_CST)
3223                         mask2 |= AR_IMR_S2_CST;
3224         }
3225
3226         DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
3227         REG_WRITE(ah, AR_IMR, mask);
3228         mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3229                                            AR_IMR_S2_DTIM |
3230                                            AR_IMR_S2_DTIMSYNC |
3231                                            AR_IMR_S2_CABEND |
3232                                            AR_IMR_S2_CABTO |
3233                                            AR_IMR_S2_TSFOOR |
3234                                            AR_IMR_S2_GTT | AR_IMR_S2_CST);
3235         REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3236         ah->mask_reg = ints;
3237
3238         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3239                 if (ints & ATH9K_INT_TIM_TIMER)
3240                         REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3241                 else
3242                         REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3243         }
3244
3245         if (ints & ATH9K_INT_GLOBAL) {
3246                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
3247                 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3248                 if (!AR_SREV_9100(ah)) {
3249                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3250                                   AR_INTR_MAC_IRQ);
3251                         REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3252
3253
3254                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3255                                   AR_INTR_SYNC_DEFAULT);
3256                         REG_WRITE(ah, AR_INTR_SYNC_MASK,
3257                                   AR_INTR_SYNC_DEFAULT);
3258                 }
3259                 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3260                          REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3261         }
3262
3263         return omask;
3264 }
3265
3266 /*******************/
3267 /* Beacon Handling */
3268 /*******************/
3269
3270 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
3271 {
3272         int flags = 0;
3273
3274         ah->beacon_interval = beacon_period;
3275
3276         switch (ah->opmode) {
3277         case NL80211_IFTYPE_STATION:
3278         case NL80211_IFTYPE_MONITOR:
3279                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3280                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3281                 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3282                 flags |= AR_TBTT_TIMER_EN;
3283                 break;
3284         case NL80211_IFTYPE_ADHOC:
3285         case NL80211_IFTYPE_MESH_POINT:
3286                 REG_SET_BIT(ah, AR_TXCFG,
3287                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3288                 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3289                           TU_TO_USEC(next_beacon +
3290                                      (ah->atim_window ? ah->
3291                                       atim_window : 1)));
3292                 flags |= AR_NDP_TIMER_EN;
3293         case NL80211_IFTYPE_AP:
3294                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3295                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3296                           TU_TO_USEC(next_beacon -
3297                                      ah->config.
3298                                      dma_beacon_response_time));
3299                 REG_WRITE(ah, AR_NEXT_SWBA,
3300                           TU_TO_USEC(next_beacon -
3301                                      ah->config.
3302                                      sw_beacon_response_time));
3303                 flags |=
3304                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3305                 break;
3306         default:
3307                 DPRINTF(ah->ah_sc, ATH_DBG_BEACON,
3308                         "%s: unsupported opmode: %d\n",
3309                         __func__, ah->opmode);
3310                 return;
3311                 break;
3312         }
3313
3314         REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3315         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3316         REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3317         REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3318
3319         beacon_period &= ~ATH9K_BEACON_ENA;
3320         if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3321                 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3322                 ath9k_hw_reset_tsf(ah);
3323         }
3324
3325         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3326 }
3327
3328 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3329                                     const struct ath9k_beacon_state *bs)
3330 {
3331         u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3332         struct ath9k_hw_capabilities *pCap = &ah->caps;
3333
3334         REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3335
3336         REG_WRITE(ah, AR_BEACON_PERIOD,
3337                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3338         REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3339                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3340
3341         REG_RMW_FIELD(ah, AR_RSSI_THR,
3342                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3343
3344         beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3345
3346         if (bs->bs_sleepduration > beaconintval)
3347                 beaconintval = bs->bs_sleepduration;
3348
3349         dtimperiod = bs->bs_dtimperiod;
3350         if (bs->bs_sleepduration > dtimperiod)
3351                 dtimperiod = bs->bs_sleepduration;
3352
3353         if (beaconintval == dtimperiod)
3354                 nextTbtt = bs->bs_nextdtim;
3355         else
3356                 nextTbtt = bs->bs_nexttbtt;
3357
3358         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3359         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3360         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3361         DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3362
3363         REG_WRITE(ah, AR_NEXT_DTIM,
3364                   TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3365         REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3366
3367         REG_WRITE(ah, AR_SLEEP1,
3368                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3369                   | AR_SLEEP1_ASSUME_DTIM);
3370
3371         if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3372                 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3373         else
3374                 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3375
3376         REG_WRITE(ah, AR_SLEEP2,
3377                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3378
3379         REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3380         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3381
3382         REG_SET_BIT(ah, AR_TIMER_MODE,
3383                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3384                     AR_DTIM_TIMER_EN);
3385
3386         /* TSF Out of Range Threshold */
3387         REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3388 }
3389
3390 /*******************/
3391 /* HW Capabilities */
3392 /*******************/
3393
3394 void ath9k_hw_fill_cap_info(struct ath_hw *ah)
3395 {
3396         struct ath9k_hw_capabilities *pCap = &ah->caps;
3397         u16 capField = 0, eeval;
3398
3399         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3400         ah->regulatory.current_rd = eeval;
3401
3402         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3403         if (AR_SREV_9285_10_OR_LATER(ah))
3404                 eeval |= AR9285_RDEXT_DEFAULT;
3405         ah->regulatory.current_rd_ext = eeval;
3406
3407         capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3408
3409         if (ah->opmode != NL80211_IFTYPE_AP &&
3410             ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3411                 if (ah->regulatory.current_rd == 0x64 ||
3412                     ah->regulatory.current_rd == 0x65)
3413                         ah->regulatory.current_rd += 5;
3414                 else if (ah->regulatory.current_rd == 0x41)
3415                         ah->regulatory.current_rd = 0x43;
3416                 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
3417                         "regdomain mapped to 0x%x\n", ah->regulatory.current_rd);
3418         }
3419
3420         eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3421         bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3422
3423         if (eeval & AR5416_OPFLAGS_11A) {
3424                 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3425                 if (ah->config.ht_enable) {
3426                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3427                                 set_bit(ATH9K_MODE_11NA_HT20,
3428                                         pCap->wireless_modes);
3429                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3430                                 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3431                                         pCap->wireless_modes);
3432                                 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3433                                         pCap->wireless_modes);
3434                         }
3435                 }
3436         }
3437
3438         if (eeval & AR5416_OPFLAGS_11G) {
3439                 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3440                 if (ah->config.ht_enable) {
3441                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3442                                 set_bit(ATH9K_MODE_11NG_HT20,
3443                                         pCap->wireless_modes);
3444                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3445                                 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3446                                         pCap->wireless_modes);
3447                                 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3448                                         pCap->wireless_modes);
3449                         }
3450                 }
3451         }
3452
3453         pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3454         if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3455             !(eeval & AR5416_OPFLAGS_11A))
3456                 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3457         else
3458                 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3459
3460         if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3461                 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3462
3463         pCap->low_2ghz_chan = 2312;
3464         pCap->high_2ghz_chan = 2732;
3465
3466         pCap->low_5ghz_chan = 4920;
3467         pCap->high_5ghz_chan = 6100;
3468
3469         pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3470         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3471         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3472
3473         pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3474         pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3475         pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3476
3477         if (ah->config.ht_enable)
3478                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3479         else
3480                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3481
3482         pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3483         pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3484         pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3485         pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3486
3487         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3488                 pCap->total_queues =
3489                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3490         else
3491                 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3492
3493         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3494                 pCap->keycache_size =
3495                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3496         else
3497                 pCap->keycache_size = AR_KEYTABLE_SIZE;
3498
3499         pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3500         pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3501
3502         if (AR_SREV_9285_10_OR_LATER(ah))
3503                 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3504         else if (AR_SREV_9280_10_OR_LATER(ah))
3505                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3506         else
3507                 pCap->num_gpio_pins = AR_NUM_GPIO;
3508
3509         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3510                 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3511                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3512         } else {
3513                 pCap->rts_aggr_limit = (8 * 1024);
3514         }
3515
3516         pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3517
3518 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3519         ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3520         if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3521                 ah->rfkill_gpio =
3522                         MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3523                 ah->rfkill_polarity =
3524                         MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3525
3526                 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3527         }
3528 #endif
3529
3530         if ((ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) ||
3531             (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) ||
3532             (ah->hw_version.macVersion == AR_SREV_VERSION_9160) ||
3533             (ah->hw_version.macVersion == AR_SREV_VERSION_9100) ||
3534             (ah->hw_version.macVersion == AR_SREV_VERSION_9280) ||
3535             (ah->hw_version.macVersion == AR_SREV_VERSION_9285))
3536                 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3537         else
3538                 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3539
3540         if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3541                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3542         else
3543                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3544
3545         if (ah->regulatory.current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3546                 pCap->reg_cap =
3547                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3548                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3549                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
3550                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3551         } else {
3552                 pCap->reg_cap =
3553                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3554                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3555         }
3556
3557         pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3558
3559         pCap->num_antcfg_5ghz =
3560                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3561         pCap->num_antcfg_2ghz =
3562                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3563
3564         if (AR_SREV_9280_10_OR_LATER(ah) && btcoex_enable) {
3565                 pCap->hw_caps |= ATH9K_HW_CAP_BT_COEX;
3566                 ah->btactive_gpio = 6;
3567                 ah->wlanactive_gpio = 5;
3568         }
3569 }
3570
3571 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3572                             u32 capability, u32 *result)
3573 {
3574         switch (type) {
3575         case ATH9K_CAP_CIPHER:
3576                 switch (capability) {
3577                 case ATH9K_CIPHER_AES_CCM:
3578                 case ATH9K_CIPHER_AES_OCB:
3579                 case ATH9K_CIPHER_TKIP:
3580                 case ATH9K_CIPHER_WEP:
3581                 case ATH9K_CIPHER_MIC:
3582                 case ATH9K_CIPHER_CLR:
3583                         return true;
3584                 default:
3585                         return false;
3586                 }
3587         case ATH9K_CAP_TKIP_MIC:
3588                 switch (capability) {
3589                 case 0:
3590                         return true;
3591                 case 1:
3592                         return (ah->sta_id1_defaults &
3593                                 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3594                         false;
3595                 }
3596         case ATH9K_CAP_TKIP_SPLIT:
3597                 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3598                         false : true;
3599         case ATH9K_CAP_DIVERSITY:
3600                 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3601                         AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3602                         true : false;
3603         case ATH9K_CAP_MCAST_KEYSRCH:
3604                 switch (capability) {
3605                 case 0:
3606                         return true;
3607                 case 1:
3608                         if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3609                                 return false;
3610                         } else {
3611                                 return (ah->sta_id1_defaults &
3612                                         AR_STA_ID1_MCAST_KSRCH) ? true :
3613                                         false;
3614                         }
3615                 }
3616                 return false;
3617         case ATH9K_CAP_TXPOW:
3618                 switch (capability) {
3619                 case 0:
3620                         return 0;
3621                 case 1:
3622                         *result = ah->regulatory.power_limit;
3623                         return 0;
3624                 case 2:
3625                         *result = ah->regulatory.max_power_level;
3626                         return 0;
3627                 case 3:
3628                         *result = ah->regulatory.tp_scale;
3629                         return 0;
3630                 }
3631                 return false;
3632         case ATH9K_CAP_DS:
3633                 return (AR_SREV_9280_20_OR_LATER(ah) &&
3634                         (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3635                         ? false : true;
3636         default:
3637                 return false;
3638         }
3639 }
3640
3641 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3642                             u32 capability, u32 setting, int *status)
3643 {
3644         u32 v;
3645
3646         switch (type) {
3647         case ATH9K_CAP_TKIP_MIC:
3648                 if (setting)
3649                         ah->sta_id1_defaults |=
3650                                 AR_STA_ID1_CRPT_MIC_ENABLE;
3651                 else
3652                         ah->sta_id1_defaults &=
3653                                 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3654                 return true;
3655         case ATH9K_CAP_DIVERSITY:
3656                 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3657                 if (setting)
3658                         v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3659                 else
3660                         v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3661                 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3662                 return true;
3663         case ATH9K_CAP_MCAST_KEYSRCH:
3664                 if (setting)
3665                         ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3666                 else
3667                         ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3668                 return true;
3669         default:
3670                 return false;
3671         }
3672 }
3673
3674 /****************************/
3675 /* GPIO / RFKILL / Antennae */
3676 /****************************/
3677
3678 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3679                                          u32 gpio, u32 type)
3680 {
3681         int addr;
3682         u32 gpio_shift, tmp;
3683
3684         if (gpio > 11)
3685                 addr = AR_GPIO_OUTPUT_MUX3;
3686         else if (gpio > 5)
3687                 addr = AR_GPIO_OUTPUT_MUX2;
3688         else
3689                 addr = AR_GPIO_OUTPUT_MUX1;
3690
3691         gpio_shift = (gpio % 6) * 5;
3692
3693         if (AR_SREV_9280_20_OR_LATER(ah)
3694             || (addr != AR_GPIO_OUTPUT_MUX1)) {
3695                 REG_RMW(ah, addr, (type << gpio_shift),
3696                         (0x1f << gpio_shift));
3697         } else {
3698                 tmp = REG_READ(ah, addr);
3699                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3700                 tmp &= ~(0x1f << gpio_shift);
3701                 tmp |= (type << gpio_shift);
3702                 REG_WRITE(ah, addr, tmp);
3703         }
3704 }
3705
3706 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3707 {
3708         u32 gpio_shift;
3709
3710         ASSERT(gpio < ah->caps.num_gpio_pins);
3711
3712         gpio_shift = gpio << 1;
3713
3714         REG_RMW(ah,
3715                 AR_GPIO_OE_OUT,
3716                 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3717                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3718 }
3719
3720 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3721 {
3722 #define MS_REG_READ(x, y) \
3723         (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3724
3725         if (gpio >= ah->caps.num_gpio_pins)
3726                 return 0xffffffff;
3727
3728         if (AR_SREV_9287_10_OR_LATER(ah))
3729                 return MS_REG_READ(AR9287, gpio) != 0;
3730         else if (AR_SREV_9285_10_OR_LATER(ah))
3731                 return MS_REG_READ(AR9285, gpio) != 0;
3732         else if (AR_SREV_9280_10_OR_LATER(ah))
3733                 return MS_REG_READ(AR928X, gpio) != 0;
3734         else
3735                 return MS_REG_READ(AR, gpio) != 0;
3736 }
3737
3738 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3739                          u32 ah_signal_type)
3740 {
3741         u32 gpio_shift;
3742
3743         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3744
3745         gpio_shift = 2 * gpio;
3746
3747         REG_RMW(ah,
3748                 AR_GPIO_OE_OUT,
3749                 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3750                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3751 }
3752
3753 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3754 {
3755         REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3756                 AR_GPIO_BIT(gpio));
3757 }
3758
3759 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3760 {
3761         return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3762 }
3763
3764 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3765 {
3766         REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3767 }
3768
3769 bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
3770                                enum ath9k_ant_setting settings,
3771                                struct ath9k_channel *chan,
3772                                u8 *tx_chainmask,
3773                                u8 *rx_chainmask,
3774                                u8 *antenna_cfgd)
3775 {
3776         static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3777
3778         if (AR_SREV_9280(ah)) {
3779                 if (!tx_chainmask_cfg) {
3780
3781                         tx_chainmask_cfg = *tx_chainmask;
3782                         rx_chainmask_cfg = *rx_chainmask;
3783                 }
3784
3785                 switch (settings) {
3786                 case ATH9K_ANT_FIXED_A:
3787                         *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3788                         *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3789                         *antenna_cfgd = true;
3790                         break;
3791                 case ATH9K_ANT_FIXED_B:
3792                         if (ah->caps.tx_chainmask >
3793                             ATH9K_ANTENNA1_CHAINMASK) {
3794                                 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3795                         }
3796                         *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3797                         *antenna_cfgd = true;
3798                         break;
3799                 case ATH9K_ANT_VARIABLE:
3800                         *tx_chainmask = tx_chainmask_cfg;
3801                         *rx_chainmask = rx_chainmask_cfg;
3802                         *antenna_cfgd = true;
3803                         break;
3804                 default:
3805                         break;
3806                 }
3807         } else {
3808                 ah->diversity_control = settings;
3809         }
3810
3811         return true;
3812 }
3813
3814 /*********************/
3815 /* General Operation */
3816 /*********************/
3817
3818 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3819 {
3820         u32 bits = REG_READ(ah, AR_RX_FILTER);
3821         u32 phybits = REG_READ(ah, AR_PHY_ERR);
3822
3823         if (phybits & AR_PHY_ERR_RADAR)
3824                 bits |= ATH9K_RX_FILTER_PHYRADAR;
3825         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3826                 bits |= ATH9K_RX_FILTER_PHYERR;
3827
3828         return bits;
3829 }
3830
3831 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3832 {
3833         u32 phybits;
3834
3835         REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
3836         phybits = 0;
3837         if (bits & ATH9K_RX_FILTER_PHYRADAR)
3838                 phybits |= AR_PHY_ERR_RADAR;
3839         if (bits & ATH9K_RX_FILTER_PHYERR)
3840                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3841         REG_WRITE(ah, AR_PHY_ERR, phybits);
3842
3843         if (phybits)
3844                 REG_WRITE(ah, AR_RXCFG,
3845                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3846         else
3847                 REG_WRITE(ah, AR_RXCFG,
3848                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3849 }
3850
3851 bool ath9k_hw_phy_disable(struct ath_hw *ah)
3852 {
3853         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3854 }
3855
3856 bool ath9k_hw_disable(struct ath_hw *ah)
3857 {
3858         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3859                 return false;
3860
3861         return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3862 }
3863
3864 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3865 {
3866         struct ath9k_channel *chan = ah->curchan;
3867         struct ieee80211_channel *channel = chan->chan;
3868
3869         ah->regulatory.power_limit = min(limit, (u32) MAX_RATE_POWER);
3870
3871         ah->eep_ops->set_txpower(ah, chan,
3872                                  ath9k_regd_get_ctl(&ah->regulatory, chan),
3873                                  channel->max_antenna_gain * 2,
3874                                  channel->max_power * 2,
3875                                  min((u32) MAX_RATE_POWER,
3876                                  (u32) ah->regulatory.power_limit));
3877 }
3878
3879 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3880 {
3881         memcpy(ah->macaddr, mac, ETH_ALEN);
3882 }
3883
3884 void ath9k_hw_setopmode(struct ath_hw *ah)
3885 {
3886         ath9k_hw_set_operating_mode(ah, ah->opmode);
3887 }
3888
3889 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3890 {
3891         REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3892         REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3893 }
3894
3895 void ath9k_hw_setbssidmask(struct ath_softc *sc)
3896 {
3897         REG_WRITE(sc->sc_ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
3898         REG_WRITE(sc->sc_ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
3899 }
3900
3901 void ath9k_hw_write_associd(struct ath_softc *sc)
3902 {
3903         REG_WRITE(sc->sc_ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
3904         REG_WRITE(sc->sc_ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
3905                   ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3906 }
3907
3908 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3909 {
3910         u64 tsf;
3911
3912         tsf = REG_READ(ah, AR_TSF_U32);
3913         tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3914
3915         return tsf;
3916 }
3917
3918 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3919 {
3920         REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3921         REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3922 }
3923
3924 void ath9k_hw_reset_tsf(struct ath_hw *ah)
3925 {
3926         ath9k_ps_wakeup(ah->ah_sc);
3927         if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
3928                            AH_TSF_WRITE_TIMEOUT))
3929                 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3930                         "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3931
3932         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3933         ath9k_ps_restore(ah->ah_sc);
3934 }
3935
3936 bool ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
3937 {
3938         if (setting)
3939                 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3940         else
3941                 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3942
3943         return true;
3944 }
3945
3946 bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
3947 {
3948         if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
3949                 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
3950                 ah->slottime = (u32) -1;
3951                 return false;
3952         } else {
3953                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
3954                 ah->slottime = us;
3955                 return true;
3956         }
3957 }
3958
3959 void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode)
3960 {
3961         u32 macmode;
3962
3963         if (mode == ATH9K_HT_MACMODE_2040 &&
3964             !ah->config.cwm_ignore_extcca)
3965                 macmode = AR_2040_JOINED_RX_CLEAR;
3966         else
3967                 macmode = 0;
3968
3969         REG_WRITE(ah, AR_2040_MODE, macmode);
3970 }
3971
3972 /***************************/
3973 /*  Bluetooth Coexistence  */
3974 /***************************/
3975
3976 void ath9k_hw_btcoex_enable(struct ath_hw *ah)
3977 {
3978         /* connect bt_active to baseband */
3979         REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3980                         (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
3981                          AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
3982
3983         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3984                         AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
3985
3986         /* Set input mux for bt_active to gpio pin */
3987         REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
3988                         AR_GPIO_INPUT_MUX1_BT_ACTIVE,
3989                         ah->btactive_gpio);
3990
3991         /* Configure the desired gpio port for input */
3992         ath9k_hw_cfg_gpio_input(ah, ah->btactive_gpio);
3993
3994         /* Configure the desired GPIO port for TX_FRAME output */
3995         ath9k_hw_cfg_output(ah, ah->wlanactive_gpio,
3996                             AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
3997 }