SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/ath/ath9k/hw.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <asm/unaligned.h>
  19
  20 #include "hw.h"
  21 #include "rc.h"
  22 #include "initvals.h"
  23
  24 #define ATH9K_CLOCK_RATE_CCK            22
  25 #define ATH9K_CLOCK_RATE_5GHZ_OFDM      40
  26 #define ATH9K_CLOCK_RATE_2GHZ_OFDM      44
  27
  28 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
  29 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan);
  30 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
  31                               struct ar5416_eeprom_def *pEepData,
  32                               u32 reg, u32 value);
  33 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
  34 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
  35
  36 MODULE_AUTHOR("Atheros Communications");
  37 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  38 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  39 MODULE_LICENSE("Dual BSD/GPL");
  40
  41 static int __init ath9k_init(void)
  42 {
  43         return 0;
  44 }
  45 module_init(ath9k_init);
  46
  47 static void __exit ath9k_exit(void)
  48 {
  49         return;
  50 }
  51 module_exit(ath9k_exit);
  52
  53 /********************/
  54 /* Helper Functions */
  55 /********************/
  56
  57 static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
  58 {
  59         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
  60
  61         if (!ah->curchan) /* should really check for CCK instead */
  62                 return clks / ATH9K_CLOCK_RATE_CCK;
  63         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  64                 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
  65
  66         return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
  67 }
  68
  69 static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
  70 {
  71         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
  72
  73         if (conf_is_ht40(conf))
  74                 return ath9k_hw_mac_usec(ah, clks) / 2;
  75         else
  76                 return ath9k_hw_mac_usec(ah, clks);
  77 }
  78
  79 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
  80 {
  81         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
  82
  83         if (!ah->curchan) /* should really check for CCK instead */
  84                 return usecs *ATH9K_CLOCK_RATE_CCK;
  85         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  86                 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
  87         return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
  88 }
  89
  90 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
  91 {
  92         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
  93
  94         if (conf_is_ht40(conf))
  95                 return ath9k_hw_mac_clks(ah, usecs) * 2;
  96         else
  97                 return ath9k_hw_mac_clks(ah, usecs);
  98 }
  99
 100 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
 101 {
 102         int i;
 103
 104         BUG_ON(timeout < AH_TIME_QUANTUM);
 105
 106         for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
 107                 if ((REG_READ(ah, reg) & mask) == val)
 108                         return true;
 109
 110                 udelay(AH_TIME_QUANTUM);
 111         }
 112
 113         ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
 114                   "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
 115                   timeout, reg, REG_READ(ah, reg), mask, val);
 116
 117         return false;
 118 }
 119 EXPORT_SYMBOL(ath9k_hw_wait);
 120
 121 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
 122 {
 123         u32 retval;
 124         int i;
 125
 126         for (i = 0, retval = 0; i < n; i++) {
 127                 retval = (retval << 1) | (val & 1);
 128                 val >>= 1;
 129         }
 130         return retval;
 131 }
 132
 133 bool ath9k_get_channel_edges(struct ath_hw *ah,
 134                              u16 flags, u16 *low,
 135                              u16 *high)
 136 {
 137         struct ath9k_hw_capabilities *pCap = &ah->caps;
 138
 139         if (flags & CHANNEL_5GHZ) {
 140                 *low = pCap->low_5ghz_chan;
 141                 *high = pCap->high_5ghz_chan;
 142                 return true;
 143         }
 144         if ((flags & CHANNEL_2GHZ)) {
 145                 *low = pCap->low_2ghz_chan;
 146                 *high = pCap->high_2ghz_chan;
 147                 return true;
 148         }
 149         return false;
 150 }
 151
 152 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
 153                            const struct ath_rate_table *rates,
 154                            u32 frameLen, u16 rateix,
 155                            bool shortPreamble)
 156 {
 157         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
 158         u32 kbps;
 159
 160         kbps = rates->info[rateix].ratekbps;
 161
 162         if (kbps == 0)
 163                 return 0;
 164
 165         switch (rates->info[rateix].phy) {
 166         case WLAN_RC_PHY_CCK:
 167                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
 168                 if (shortPreamble && rates->info[rateix].short_preamble)
 169                         phyTime >>= 1;
 170                 numBits = frameLen << 3;
 171                 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
 172                 break;
 173         case WLAN_RC_PHY_OFDM:
 174                 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
 175                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
 176                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 177                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 178                         txTime = OFDM_SIFS_TIME_QUARTER
 179                                 + OFDM_PREAMBLE_TIME_QUARTER
 180                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
 181                 } else if (ah->curchan &&
 182                            IS_CHAN_HALF_RATE(ah->curchan)) {
 183                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
 184                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 185                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 186                         txTime = OFDM_SIFS_TIME_HALF +
 187                                 OFDM_PREAMBLE_TIME_HALF
 188                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
 189                 } else {
 190                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
 191                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 192                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 193                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
 194                                 + (numSymbols * OFDM_SYMBOL_TIME);
 195                 }
 196                 break;
 197         default:
 198                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 199                           "Unknown phy %u (rate ix %u)\n",
 200                           rates->info[rateix].phy, rateix);
 201                 txTime = 0;
 202                 break;
 203         }
 204
 205         return txTime;
 206 }
 207 EXPORT_SYMBOL(ath9k_hw_computetxtime);
 208
 209 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
 210                                   struct ath9k_channel *chan,
 211                                   struct chan_centers *centers)
 212 {
 213         int8_t extoff;
 214
 215         if (!IS_CHAN_HT40(chan)) {
 216                 centers->ctl_center = centers->ext_center =
 217                         centers->synth_center = chan->channel;
 218                 return;
 219         }
 220
 221         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 222             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
 223                 centers->synth_center =
 224                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
 225                 extoff = 1;
 226         } else {
 227                 centers->synth_center =
 228                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
 229                 extoff = -1;
 230         }
 231
 232         centers->ctl_center =
 233                 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
 234         /* 25 MHz spacing is supported by hw but not on upper layers */
 235         centers->ext_center =
 236                 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
 237 }
 238
 239 /******************/
 240 /* Chip Revisions */
 241 /******************/
 242
 243 static void ath9k_hw_read_revisions(struct ath_hw *ah)
 244 {
 245         u32 val;
 246
 247         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
 248
 249         if (val == 0xFF) {
 250                 val = REG_READ(ah, AR_SREV);
 251                 ah->hw_version.macVersion =
 252                         (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
 253                 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
 254                 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
 255         } else {
 256                 if (!AR_SREV_9100(ah))
 257                         ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
 258
 259                 ah->hw_version.macRev = val & AR_SREV_REVISION;
 260
 261                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
 262                         ah->is_pciexpress = true;
 263         }
 264 }
 265
 266 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
 267 {
 268         u32 val;
 269         int i;
 270
 271         REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
 272
 273         for (i = 0; i < 8; i++)
 274                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
 275         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
 276         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
 277
 278         return ath9k_hw_reverse_bits(val, 8);
 279 }
 280
 281 /************************************/
 282 /* HW Attach, Detach, Init Routines */
 283 /************************************/
 284
 285 static void ath9k_hw_disablepcie(struct ath_hw *ah)
 286 {
 287         if (AR_SREV_9100(ah))
 288                 return;
 289
 290         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 291         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 292         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
 293         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
 294         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
 295         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
 296         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 297         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 298         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
 299
 300         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 301 }
 302
 303 static bool ath9k_hw_chip_test(struct ath_hw *ah)
 304 {
 305         struct ath_common *common = ath9k_hw_common(ah);
 306         u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
 307         u32 regHold[2];
 308         u32 patternData[4] = { 0x55555555,
 309                                0xaaaaaaaa,
 310                                0x66666666,
 311                                0x99999999 };
 312         int i, j;
 313
 314         for (i = 0; i < 2; i++) {
 315                 u32 addr = regAddr[i];
 316                 u32 wrData, rdData;
 317
 318                 regHold[i] = REG_READ(ah, addr);
 319                 for (j = 0; j < 0x100; j++) {
 320                         wrData = (j << 16) | j;
 321                         REG_WRITE(ah, addr, wrData);
 322                         rdData = REG_READ(ah, addr);
 323                         if (rdData != wrData) {
 324                                 ath_print(common, ATH_DBG_FATAL,
 325                                           "address test failed "
 326                                           "addr: 0x%08x - wr:0x%08x != "
 327                                           "rd:0x%08x\n",
 328                                           addr, wrData, rdData);
 329                                 return false;
 330                         }
 331                 }
 332                 for (j = 0; j < 4; j++) {
 333                         wrData = patternData[j];
 334                         REG_WRITE(ah, addr, wrData);
 335                         rdData = REG_READ(ah, addr);
 336                         if (wrData != rdData) {
 337                                 ath_print(common, ATH_DBG_FATAL,
 338                                           "address test failed "
 339                                           "addr: 0x%08x - wr:0x%08x != "
 340                                           "rd:0x%08x\n",
 341                                           addr, wrData, rdData);
 342                                 return false;
 343                         }
 344                 }
 345                 REG_WRITE(ah, regAddr[i], regHold[i]);
 346         }
 347         udelay(100);
 348
 349         return true;
 350 }
 351
 352 static const char *ath9k_hw_devname(u16 devid)
 353 {
 354         switch (devid) {
 355         case AR5416_DEVID_PCI:
 356                 return "Atheros 5416";
 357         case AR5416_DEVID_PCIE:
 358                 return "Atheros 5418";
 359         case AR9160_DEVID_PCI:
 360                 return "Atheros 9160";
 361         case AR5416_AR9100_DEVID:
 362                 return "Atheros 9100";
 363         case AR9280_DEVID_PCI:
 364         case AR9280_DEVID_PCIE:
 365                 return "Atheros 9280";
 366         case AR9285_DEVID_PCIE:
 367                 return "Atheros 9285";
 368         case AR5416_DEVID_AR9287_PCI:
 369         case AR5416_DEVID_AR9287_PCIE:
 370                 return "Atheros 9287";
 371         }
 372
 373         return NULL;
 374 }
 375
 376 static void ath9k_hw_init_config(struct ath_hw *ah)
 377 {
 378         int i;
 379
 380         ah->config.dma_beacon_response_time = 2;
 381         ah->config.sw_beacon_response_time = 10;
 382         ah->config.additional_swba_backoff = 0;
 383         ah->config.ack_6mb = 0x0;
 384         ah->config.cwm_ignore_extcca = 0;
 385         ah->config.pcie_powersave_enable = 0;
 386         ah->config.pcie_clock_req = 0;
 387         ah->config.pcie_waen = 0;
 388         ah->config.analog_shiftreg = 1;
 389         ah->config.ht_enable = 1;
 390         ah->config.ofdm_trig_low = 200;
 391         ah->config.ofdm_trig_high = 500;
 392         ah->config.cck_trig_high = 200;
 393         ah->config.cck_trig_low = 100;
 394         ah->config.enable_ani = 1;
 395         ah->config.diversity_control = ATH9K_ANT_VARIABLE;
 396         ah->config.antenna_switch_swap = 0;
 397
 398         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 399                 ah->config.spurchans[i][0] = AR_NO_SPUR;
 400                 ah->config.spurchans[i][1] = AR_NO_SPUR;
 401         }
 402
 403         ah->config.intr_mitigation = true;
 404
 405         /*
 406          * We need this for PCI devices only (Cardbus, PCI, miniPCI)
 407          * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
 408          * This means we use it for all AR5416 devices, and the few
 409          * minor PCI AR9280 devices out there.
 410          *
 411          * Serialization is required because these devices do not handle
 412          * well the case of two concurrent reads/writes due to the latency
 413          * involved. During one read/write another read/write can be issued
 414          * on another CPU while the previous read/write may still be working
 415          * on our hardware, if we hit this case the hardware poops in a loop.
 416          * We prevent this by serializing reads and writes.
 417          *
 418          * This issue is not present on PCI-Express devices or pre-AR5416
 419          * devices (legacy, 802.11abg).
 420          */
 421         if (num_possible_cpus() > 1)
 422                 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
 423 }
 424 EXPORT_SYMBOL(ath9k_hw_init);
 425
 426 static void ath9k_hw_init_defaults(struct ath_hw *ah)
 427 {
 428         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
 429
 430         regulatory->country_code = CTRY_DEFAULT;
 431         regulatory->power_limit = MAX_RATE_POWER;
 432         regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
 433
 434         ah->hw_version.magic = AR5416_MAGIC;
 435         ah->hw_version.subvendorid = 0;
 436
 437         ah->ah_flags = 0;
 438         if (ah->hw_version.devid == AR5416_AR9100_DEVID)
 439                 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
 440         if (!AR_SREV_9100(ah))
 441                 ah->ah_flags = AH_USE_EEPROM;
 442
 443         ah->atim_window = 0;
 444         ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
 445         ah->beacon_interval = 100;
 446         ah->enable_32kHz_clock = DONT_USE_32KHZ;
 447         ah->slottime = (u32) -1;
 448         ah->acktimeout = (u32) -1;
 449         ah->ctstimeout = (u32) -1;
 450         ah->globaltxtimeout = (u32) -1;
 451
 452         ah->gbeacon_rate = 0;
 453
 454         ah->power_mode = ATH9K_PM_UNDEFINED;
 455 }
 456
 457 static int ath9k_hw_rfattach(struct ath_hw *ah)
 458 {
 459         bool rfStatus = false;
 460         int ecode = 0;
 461
 462         rfStatus = ath9k_hw_init_rf(ah, &ecode);
 463         if (!rfStatus) {
 464                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 465                           "RF setup failed, status: %u\n", ecode);
 466                 return ecode;
 467         }
 468
 469         return 0;
 470 }
 471
 472 static int ath9k_hw_rf_claim(struct ath_hw *ah)
 473 {
 474         u32 val;
 475
 476         REG_WRITE(ah, AR_PHY(0), 0x00000007);
 477
 478         val = ath9k_hw_get_radiorev(ah);
 479         switch (val & AR_RADIO_SREV_MAJOR) {
 480         case 0:
 481                 val = AR_RAD5133_SREV_MAJOR;
 482                 break;
 483         case AR_RAD5133_SREV_MAJOR:
 484         case AR_RAD5122_SREV_MAJOR:
 485         case AR_RAD2133_SREV_MAJOR:
 486         case AR_RAD2122_SREV_MAJOR:
 487                 break;
 488         default:
 489                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 490                           "Radio Chip Rev 0x%02X not supported\n",
 491                           val & AR_RADIO_SREV_MAJOR);
 492                 return -EOPNOTSUPP;
 493         }
 494
 495         ah->hw_version.analog5GhzRev = val;
 496
 497         return 0;
 498 }
 499
 500 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
 501 {
 502         struct ath_common *common = ath9k_hw_common(ah);
 503         u32 sum;
 504         int i;
 505         u16 eeval;
 506
 507         sum = 0;
 508         for (i = 0; i < 3; i++) {
 509                 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
 510                 sum += eeval;
 511                 common->macaddr[2 * i] = eeval >> 8;
 512                 common->macaddr[2 * i + 1] = eeval & 0xff;
 513         }
 514         if (sum == 0 || sum == 0xffff * 3)
 515                 return -EADDRNOTAVAIL;
 516
 517         return 0;
 518 }
 519
 520 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
 521 {
 522         u32 rxgain_type;
 523
 524         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
 525                 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
 526
 527                 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
 528                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 529                         ar9280Modes_backoff_13db_rxgain_9280_2,
 530                         ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
 531                 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
 532                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 533                         ar9280Modes_backoff_23db_rxgain_9280_2,
 534                         ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
 535                 else
 536                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 537                         ar9280Modes_original_rxgain_9280_2,
 538                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 539         } else {
 540                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 541                         ar9280Modes_original_rxgain_9280_2,
 542                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 543         }
 544 }
 545
 546 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
 547 {
 548         u32 txgain_type;
 549
 550         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
 551                 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 552
 553                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
 554                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 555                         ar9280Modes_high_power_tx_gain_9280_2,
 556                         ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
 557                 else
 558                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 559                         ar9280Modes_original_tx_gain_9280_2,
 560                         ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 561         } else {
 562                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 563                 ar9280Modes_original_tx_gain_9280_2,
 564                 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 565         }
 566 }
 567
 568 static int ath9k_hw_post_init(struct ath_hw *ah)
 569 {
 570         int ecode;
 571
 572         if (!ath9k_hw_chip_test(ah))
 573                 return -ENODEV;
 574
 575         ecode = ath9k_hw_rf_claim(ah);
 576         if (ecode != 0)
 577                 return ecode;
 578
 579         ecode = ath9k_hw_eeprom_init(ah);
 580         if (ecode != 0)
 581                 return ecode;
 582
 583         ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
 584                   "Eeprom VER: %d, REV: %d\n",
 585                   ah->eep_ops->get_eeprom_ver(ah),
 586                   ah->eep_ops->get_eeprom_rev(ah));
 587
 588         ecode = ath9k_hw_rfattach(ah);
 589         if (ecode != 0)
 590                 return ecode;
 591
 592         if (!AR_SREV_9100(ah)) {
 593                 ath9k_hw_ani_setup(ah);
 594                 ath9k_hw_ani_init(ah);
 595         }
 596
 597         return 0;
 598 }
 599
 600 static bool ath9k_hw_devid_supported(u16 devid)
 601 {
 602         switch (devid) {
 603         case AR5416_DEVID_PCI:
 604         case AR5416_DEVID_PCIE:
 605         case AR5416_AR9100_DEVID:
 606         case AR9160_DEVID_PCI:
 607         case AR9280_DEVID_PCI:
 608         case AR9280_DEVID_PCIE:
 609         case AR9285_DEVID_PCIE:
 610         case AR5416_DEVID_AR9287_PCI:
 611         case AR5416_DEVID_AR9287_PCIE:
 612                 return true;
 613         default:
 614                 break;
 615         }
 616         return false;
 617 }
 618
 619 static bool ath9k_hw_macversion_supported(u32 macversion)
 620 {
 621         switch (macversion) {
 622         case AR_SREV_VERSION_5416_PCI:
 623         case AR_SREV_VERSION_5416_PCIE:
 624         case AR_SREV_VERSION_9160:
 625         case AR_SREV_VERSION_9100:
 626         case AR_SREV_VERSION_9280:
 627         case AR_SREV_VERSION_9285:
 628         case AR_SREV_VERSION_9287:
 629                 return true;
 630         /* Not yet */
 631         case AR_SREV_VERSION_9271:
 632         default:
 633                 break;
 634         }
 635         return false;
 636 }
 637
 638 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
 639 {
 640         if (AR_SREV_9160_10_OR_LATER(ah)) {
 641                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 642                         ah->iq_caldata.calData = &iq_cal_single_sample;
 643                         ah->adcgain_caldata.calData =
 644                                 &adc_gain_cal_single_sample;
 645                         ah->adcdc_caldata.calData =
 646                                 &adc_dc_cal_single_sample;
 647                         ah->adcdc_calinitdata.calData =
 648                                 &adc_init_dc_cal;
 649                 } else {
 650                         ah->iq_caldata.calData = &iq_cal_multi_sample;
 651                         ah->adcgain_caldata.calData =
 652                                 &adc_gain_cal_multi_sample;
 653                         ah->adcdc_caldata.calData =
 654                                 &adc_dc_cal_multi_sample;
 655                         ah->adcdc_calinitdata.calData =
 656                                 &adc_init_dc_cal;
 657                 }
 658                 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
 659         }
 660 }
 661
 662 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
 663 {
 664         if (AR_SREV_9271(ah)) {
 665                 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271_1_0,
 666                                ARRAY_SIZE(ar9271Modes_9271_1_0), 6);
 667                 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271_1_0,
 668                                ARRAY_SIZE(ar9271Common_9271_1_0), 2);
 669                 return;
 670         }
 671
 672         if (AR_SREV_9287_11_OR_LATER(ah)) {
 673                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
 674                                 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
 675                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
 676                                 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
 677                 if (ah->config.pcie_clock_req)
 678                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 679                         ar9287PciePhy_clkreq_off_L1_9287_1_1,
 680                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
 681                 else
 682                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 683                         ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
 684                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
 685                                         2);
 686         } else if (AR_SREV_9287_10_OR_LATER(ah)) {
 687                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
 688                                 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
 689                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
 690                                 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
 691
 692                 if (ah->config.pcie_clock_req)
 693                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 694                         ar9287PciePhy_clkreq_off_L1_9287_1_0,
 695                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
 696                 else
 697                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 698                         ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
 699                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
 700                                   2);
 701         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
 702
 703
 704                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
 705                                ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
 706                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
 707                                ARRAY_SIZE(ar9285Common_9285_1_2), 2);
 708
 709                 if (ah->config.pcie_clock_req) {
 710                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 711                         ar9285PciePhy_clkreq_off_L1_9285_1_2,
 712                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
 713                 } else {
 714                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 715                         ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
 716                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
 717                                   2);
 718                 }
 719         } else if (AR_SREV_9285_10_OR_LATER(ah)) {
 720                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
 721                                ARRAY_SIZE(ar9285Modes_9285), 6);
 722                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
 723                                ARRAY_SIZE(ar9285Common_9285), 2);
 724
 725                 if (ah->config.pcie_clock_req) {
 726                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 727                         ar9285PciePhy_clkreq_off_L1_9285,
 728                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
 729                 } else {
 730                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 731                         ar9285PciePhy_clkreq_always_on_L1_9285,
 732                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
 733                 }
 734         } else if (AR_SREV_9280_20_OR_LATER(ah)) {
 735                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
 736                                ARRAY_SIZE(ar9280Modes_9280_2), 6);
 737                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
 738                                ARRAY_SIZE(ar9280Common_9280_2), 2);
 739
 740                 if (ah->config.pcie_clock_req) {
 741                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 742                                ar9280PciePhy_clkreq_off_L1_9280,
 743                                ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
 744                 } else {
 745                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 746                                ar9280PciePhy_clkreq_always_on_L1_9280,
 747                                ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
 748                 }
 749                 INIT_INI_ARRAY(&ah->iniModesAdditional,
 750                                ar9280Modes_fast_clock_9280_2,
 751                                ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
 752         } else if (AR_SREV_9280_10_OR_LATER(ah)) {
 753                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
 754                                ARRAY_SIZE(ar9280Modes_9280), 6);
 755                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
 756                                ARRAY_SIZE(ar9280Common_9280), 2);
 757         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 758                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
 759                                ARRAY_SIZE(ar5416Modes_9160), 6);
 760                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
 761                                ARRAY_SIZE(ar5416Common_9160), 2);
 762                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
 763                                ARRAY_SIZE(ar5416Bank0_9160), 2);
 764                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
 765                                ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
 766                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
 767                                ARRAY_SIZE(ar5416Bank1_9160), 2);
 768                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
 769                                ARRAY_SIZE(ar5416Bank2_9160), 2);
 770                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
 771                                ARRAY_SIZE(ar5416Bank3_9160), 3);
 772                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
 773                                ARRAY_SIZE(ar5416Bank6_9160), 3);
 774                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
 775                                ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
 776                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
 777                                ARRAY_SIZE(ar5416Bank7_9160), 2);
 778                 if (AR_SREV_9160_11(ah)) {
 779                         INIT_INI_ARRAY(&ah->iniAddac,
 780                                        ar5416Addac_91601_1,
 781                                        ARRAY_SIZE(ar5416Addac_91601_1), 2);
 782                 } else {
 783                         INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
 784                                        ARRAY_SIZE(ar5416Addac_9160), 2);
 785                 }
 786         } else if (AR_SREV_9100_OR_LATER(ah)) {
 787                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
 788                                ARRAY_SIZE(ar5416Modes_9100), 6);
 789                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
 790                                ARRAY_SIZE(ar5416Common_9100), 2);
 791                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
 792                                ARRAY_SIZE(ar5416Bank0_9100), 2);
 793                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
 794                                ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
 795                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
 796                                ARRAY_SIZE(ar5416Bank1_9100), 2);
 797                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
 798                                ARRAY_SIZE(ar5416Bank2_9100), 2);
 799                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
 800                                ARRAY_SIZE(ar5416Bank3_9100), 3);
 801                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
 802                                ARRAY_SIZE(ar5416Bank6_9100), 3);
 803                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
 804                                ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
 805                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
 806                                ARRAY_SIZE(ar5416Bank7_9100), 2);
 807                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
 808                                ARRAY_SIZE(ar5416Addac_9100), 2);
 809         } else {
 810                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
 811                                ARRAY_SIZE(ar5416Modes), 6);
 812                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
 813                                ARRAY_SIZE(ar5416Common), 2);
 814                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
 815                                ARRAY_SIZE(ar5416Bank0), 2);
 816                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
 817                                ARRAY_SIZE(ar5416BB_RfGain), 3);
 818                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
 819                                ARRAY_SIZE(ar5416Bank1), 2);
 820                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
 821                                ARRAY_SIZE(ar5416Bank2), 2);
 822                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
 823                                ARRAY_SIZE(ar5416Bank3), 3);
 824                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
 825                                ARRAY_SIZE(ar5416Bank6), 3);
 826                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
 827                                ARRAY_SIZE(ar5416Bank6TPC), 3);
 828                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
 829                                ARRAY_SIZE(ar5416Bank7), 2);
 830                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
 831                                ARRAY_SIZE(ar5416Addac), 2);
 832         }
 833 }
 834
 835 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
 836 {
 837         if (AR_SREV_9287_11_OR_LATER(ah))
 838                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 839                 ar9287Modes_rx_gain_9287_1_1,
 840                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
 841         else if (AR_SREV_9287_10(ah))
 842                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 843                 ar9287Modes_rx_gain_9287_1_0,
 844                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
 845         else if (AR_SREV_9280_20(ah))
 846                 ath9k_hw_init_rxgain_ini(ah);
 847
 848         if (AR_SREV_9287_11_OR_LATER(ah)) {
 849                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 850                 ar9287Modes_tx_gain_9287_1_1,
 851                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
 852         } else if (AR_SREV_9287_10(ah)) {
 853                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 854                 ar9287Modes_tx_gain_9287_1_0,
 855                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
 856         } else if (AR_SREV_9280_20(ah)) {
 857                 ath9k_hw_init_txgain_ini(ah);
 858         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
 859                 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 860
 861                 /* txgain table */
 862                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
 863                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 864                         ar9285Modes_high_power_tx_gain_9285_1_2,
 865                         ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
 866                 } else {
 867                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 868                         ar9285Modes_original_tx_gain_9285_1_2,
 869                         ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
 870                 }
 871
 872         }
 873 }
 874
 875 static void ath9k_hw_init_11a_eeprom_fix(struct ath_hw *ah)
 876 {
 877         u32 i, j;
 878
 879         if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
 880             test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
 881
 882                 /* EEPROM Fixup */
 883                 for (i = 0; i < ah->iniModes.ia_rows; i++) {
 884                         u32 reg = INI_RA(&ah->iniModes, i, 0);
 885
 886                         for (j = 1; j < ah->iniModes.ia_columns; j++) {
 887                                 u32 val = INI_RA(&ah->iniModes, i, j);
 888
 889                                 INI_RA(&ah->iniModes, i, j) =
 890                                         ath9k_hw_ini_fixup(ah,
 891                                                            &ah->eeprom.def,
 892                                                            reg, val);
 893                         }
 894                 }
 895         }
 896 }
 897
 898 int ath9k_hw_init(struct ath_hw *ah)
 899 {
 900         struct ath_common *common = ath9k_hw_common(ah);
 901         int r = 0;
 902
 903         if (!ath9k_hw_devid_supported(ah->hw_version.devid))
 904                 return -EOPNOTSUPP;
 905
 906         ath9k_hw_init_defaults(ah);
 907         ath9k_hw_init_config(ah);
 908
 909         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
 910                 ath_print(common, ATH_DBG_FATAL,
 911                           "Couldn't reset chip\n");
 912                 return -EIO;
 913         }
 914
 915         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
 916                 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
 917                 return -EIO;
 918         }
 919
 920         if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
 921                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
 922                     (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
 923                         ah->config.serialize_regmode =
 924                                 SER_REG_MODE_ON;
 925                 } else {
 926                         ah->config.serialize_regmode =
 927                                 SER_REG_MODE_OFF;
 928                 }
 929         }
 930
 931         ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
 932                 ah->config.serialize_regmode);
 933
 934         if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
 935                 ath_print(common, ATH_DBG_FATAL,
 936                           "Mac Chip Rev 0x%02x.%x is not supported by "
 937                           "this driver\n", ah->hw_version.macVersion,
 938                           ah->hw_version.macRev);
 939                 return -EOPNOTSUPP;
 940         }
 941
 942         if (AR_SREV_9100(ah)) {
 943                 ah->iq_caldata.calData = &iq_cal_multi_sample;
 944                 ah->supp_cals = IQ_MISMATCH_CAL;
 945                 ah->is_pciexpress = false;
 946         }
 947
 948         if (AR_SREV_9271(ah))
 949                 ah->is_pciexpress = false;
 950
 951         ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
 952
 953         ath9k_hw_init_cal_settings(ah);
 954
 955         ah->ani_function = ATH9K_ANI_ALL;
 956         if (AR_SREV_9280_10_OR_LATER(ah))
 957                 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
 958
 959         ath9k_hw_init_mode_regs(ah);
 960
 961         if (ah->is_pciexpress)
 962                 ath9k_hw_configpcipowersave(ah, 0, 0);
 963         else
 964                 ath9k_hw_disablepcie(ah);
 965
 966         /* Support for Japan ch.14 (2484) spread */
 967         if (AR_SREV_9287_11_OR_LATER(ah)) {
 968                 INIT_INI_ARRAY(&ah->iniCckfirNormal,
 969                        ar9287Common_normal_cck_fir_coeff_92871_1,
 970                        ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2);
 971                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 972                        ar9287Common_japan_2484_cck_fir_coeff_92871_1,
 973                        ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2);
 974         }
 975
 976         r = ath9k_hw_post_init(ah);
 977         if (r)
 978                 return r;
 979
 980         ath9k_hw_init_mode_gain_regs(ah);
 981         ath9k_hw_fill_cap_info(ah);
 982         ath9k_hw_init_11a_eeprom_fix(ah);
 983
 984         r = ath9k_hw_init_macaddr(ah);
 985         if (r) {
 986                 ath_print(common, ATH_DBG_FATAL,
 987                           "Failed to initialize MAC address\n");
 988                 return r;
 989         }
 990
 991         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
 992                 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
 993         else
 994                 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
 995
 996         ath9k_init_nfcal_hist_buffer(ah);
 997
 998         return 0;
 999 }
1000
1001 static void ath9k_hw_init_bb(struct ath_hw *ah,
1002                              struct ath9k_channel *chan)
1003 {
1004         u32 synthDelay;
1005
1006         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1007         if (IS_CHAN_B(chan))
1008                 synthDelay = (4 * synthDelay) / 22;
1009         else
1010                 synthDelay /= 10;
1011
1012         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
1013
1014         udelay(synthDelay + BASE_ACTIVATE_DELAY);
1015 }
1016
1017 static void ath9k_hw_init_qos(struct ath_hw *ah)
1018 {
1019         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
1020         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
1021
1022         REG_WRITE(ah, AR_QOS_NO_ACK,
1023                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
1024                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
1025                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
1026
1027         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
1028         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
1029         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
1030         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
1031         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
1032 }
1033
1034 static void ath9k_hw_init_pll(struct ath_hw *ah,
1035                               struct ath9k_channel *chan)
1036 {
1037         u32 pll;
1038
1039         if (AR_SREV_9100(ah)) {
1040                 if (chan && IS_CHAN_5GHZ(chan))
1041                         pll = 0x1450;
1042                 else
1043                         pll = 0x1458;
1044         } else {
1045                 if (AR_SREV_9280_10_OR_LATER(ah)) {
1046                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1047
1048                         if (chan && IS_CHAN_HALF_RATE(chan))
1049                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1050                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1051                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1052
1053                         if (chan && IS_CHAN_5GHZ(chan)) {
1054                                 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1055
1056
1057                                 if (AR_SREV_9280_20(ah)) {
1058                                         if (((chan->channel % 20) == 0)
1059                                             || ((chan->channel % 10) == 0))
1060                                                 pll = 0x2850;
1061                                         else
1062                                                 pll = 0x142c;
1063                                 }
1064                         } else {
1065                                 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1066                         }
1067
1068                 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1069
1070                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1071
1072                         if (chan && IS_CHAN_HALF_RATE(chan))
1073                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1074                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1075                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1076
1077                         if (chan && IS_CHAN_5GHZ(chan))
1078                                 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1079                         else
1080                                 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1081                 } else {
1082                         pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1083
1084                         if (chan && IS_CHAN_HALF_RATE(chan))
1085                                 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1086                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1087                                 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1088
1089                         if (chan && IS_CHAN_5GHZ(chan))
1090                                 pll |= SM(0xa, AR_RTC_PLL_DIV);
1091                         else
1092                                 pll |= SM(0xb, AR_RTC_PLL_DIV);
1093                 }
1094         }
1095         REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1096
1097         udelay(RTC_PLL_SETTLE_DELAY);
1098
1099         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1100 }
1101
1102 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1103 {
1104         int rx_chainmask, tx_chainmask;
1105
1106         rx_chainmask = ah->rxchainmask;
1107         tx_chainmask = ah->txchainmask;
1108
1109         switch (rx_chainmask) {
1110         case 0x5:
1111                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1112                             AR_PHY_SWAP_ALT_CHAIN);
1113         case 0x3:
1114                 if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) {
1115                         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1116                         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1117                         break;
1118                 }
1119         case 0x1:
1120         case 0x2:
1121         case 0x7:
1122                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1123                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1124                 break;
1125         default:
1126                 break;
1127         }
1128
1129         REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1130         if (tx_chainmask == 0x5) {
1131                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1132                             AR_PHY_SWAP_ALT_CHAIN);
1133         }
1134         if (AR_SREV_9100(ah))
1135                 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1136                           REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1137 }
1138
1139 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1140                                           enum nl80211_iftype opmode)
1141 {
1142         ah->mask_reg = AR_IMR_TXERR |
1143                 AR_IMR_TXURN |
1144                 AR_IMR_RXERR |
1145                 AR_IMR_RXORN |
1146                 AR_IMR_BCNMISC;
1147
1148         if (ah->config.intr_mitigation)
1149                 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1150         else
1151                 ah->mask_reg |= AR_IMR_RXOK;
1152
1153         ah->mask_reg |= AR_IMR_TXOK;
1154
1155         if (opmode == NL80211_IFTYPE_AP)
1156                 ah->mask_reg |= AR_IMR_MIB;
1157
1158         REG_WRITE(ah, AR_IMR, ah->mask_reg);
1159         REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1160
1161         if (!AR_SREV_9100(ah)) {
1162                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1163                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1164                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1165         }
1166 }
1167
1168 static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1169 {
1170         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1171                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1172                           "bad ack timeout %u\n", us);
1173                 ah->acktimeout = (u32) -1;
1174                 return false;
1175         } else {
1176                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1177                               AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1178                 ah->acktimeout = us;
1179                 return true;
1180         }
1181 }
1182
1183 static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1184 {
1185         if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1186                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1187                           "bad cts timeout %u\n", us);
1188                 ah->ctstimeout = (u32) -1;
1189                 return false;
1190         } else {
1191                 REG_RMW_FIELD(ah, AR_TIME_OUT,
1192                               AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1193                 ah->ctstimeout = us;
1194                 return true;
1195         }
1196 }
1197
1198 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1199 {
1200         if (tu > 0xFFFF) {
1201                 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
1202                           "bad global tx timeout %u\n", tu);
1203                 ah->globaltxtimeout = (u32) -1;
1204                 return false;
1205         } else {
1206                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1207                 ah->globaltxtimeout = tu;
1208                 return true;
1209         }
1210 }
1211
1212 static void ath9k_hw_init_user_settings(struct ath_hw *ah)
1213 {
1214         ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1215                   ah->misc_mode);
1216
1217         if (ah->misc_mode != 0)
1218                 REG_WRITE(ah, AR_PCU_MISC,
1219                           REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1220         if (ah->slottime != (u32) -1)
1221                 ath9k_hw_setslottime(ah, ah->slottime);
1222         if (ah->acktimeout != (u32) -1)
1223                 ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
1224         if (ah->ctstimeout != (u32) -1)
1225                 ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
1226         if (ah->globaltxtimeout != (u32) -1)
1227                 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1228 }
1229
1230 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1231 {
1232         return vendorid == ATHEROS_VENDOR_ID ?
1233                 ath9k_hw_devname(devid) : NULL;
1234 }
1235
1236 void ath9k_hw_detach(struct ath_hw *ah)
1237 {
1238         if (!AR_SREV_9100(ah))
1239                 ath9k_hw_ani_disable(ah);
1240
1241         ath9k_hw_rf_free(ah);
1242         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1243         kfree(ah);
1244         ah = NULL;
1245 }
1246 EXPORT_SYMBOL(ath9k_hw_detach);
1247
1248 /*******/
1249 /* INI */
1250 /*******/
1251
1252 static void ath9k_hw_override_ini(struct ath_hw *ah,
1253                                   struct ath9k_channel *chan)
1254 {
1255         u32 val;
1256
1257         if (AR_SREV_9271(ah)) {
1258                 /*
1259                  * Enable spectral scan to solution for issues with stuck
1260                  * beacons on AR9271 1.0. The beacon stuck issue is not seeon on
1261                  * AR9271 1.1
1262                  */
1263                 if (AR_SREV_9271_10(ah)) {
1264                         val = REG_READ(ah, AR_PHY_SPECTRAL_SCAN) | AR_PHY_SPECTRAL_SCAN_ENABLE;
1265                         REG_WRITE(ah, AR_PHY_SPECTRAL_SCAN, val);
1266                 }
1267                 else if (AR_SREV_9271_11(ah))
1268                         /*
1269                          * change AR_PHY_RF_CTL3 setting to fix MAC issue
1270                          * present on AR9271 1.1
1271                          */
1272                         REG_WRITE(ah, AR_PHY_RF_CTL3, 0x3a020001);
1273                 return;
1274         }
1275
1276         /*
1277          * Set the RX_ABORT and RX_DIS and clear if off only after
1278          * RXE is set for MAC. This prevents frames with corrupted
1279          * descriptor status.
1280          */
1281         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1282
1283         if (AR_SREV_9280_10_OR_LATER(ah)) {
1284                 val = REG_READ(ah, AR_PCU_MISC_MODE2) &
1285                                (~AR_PCU_MISC_MODE2_HWWAR1);
1286
1287                 if (AR_SREV_9287_10_OR_LATER(ah))
1288                         val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
1289
1290                 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
1291         }
1292
1293         if (!AR_SREV_5416_20_OR_LATER(ah) ||
1294             AR_SREV_9280_10_OR_LATER(ah))
1295                 return;
1296         /*
1297          * Disable BB clock gating
1298          * Necessary to avoid issues on AR5416 2.0
1299          */
1300         REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1301 }
1302
1303 static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1304                               struct ar5416_eeprom_def *pEepData,
1305                               u32 reg, u32 value)
1306 {
1307         struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1308         struct ath_common *common = ath9k_hw_common(ah);
1309
1310         switch (ah->hw_version.devid) {
1311         case AR9280_DEVID_PCI:
1312                 if (reg == 0x7894) {
1313                         ath_print(common, ATH_DBG_EEPROM,
1314                                 "ini VAL: %x  EEPROM: %x\n", value,
1315                                 (pBase->version & 0xff));
1316
1317                         if ((pBase->version & 0xff) > 0x0a) {
1318                                 ath_print(common, ATH_DBG_EEPROM,
1319                                           "PWDCLKIND: %d\n",
1320                                           pBase->pwdclkind);
1321                                 value &= ~AR_AN_TOP2_PWDCLKIND;
1322                                 value |= AR_AN_TOP2_PWDCLKIND &
1323                                         (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1324                         } else {
1325                                 ath_print(common, ATH_DBG_EEPROM,
1326                                           "PWDCLKIND Earlier Rev\n");
1327                         }
1328
1329                         ath_print(common, ATH_DBG_EEPROM,
1330                                   "final ini VAL: %x\n", value);
1331                 }
1332                 break;
1333         }
1334
1335         return value;
1336 }
1337
1338 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1339                               struct ar5416_eeprom_def *pEepData,
1340                               u32 reg, u32 value)
1341 {
1342         if (ah->eep_map == EEP_MAP_4KBITS)
1343                 return value;
1344         else
1345                 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1346 }
1347
1348 static void ath9k_olc_init(struct ath_hw *ah)
1349 {
1350         u32 i;
1351
1352         if (OLC_FOR_AR9287_10_LATER) {
1353                 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
1354                                 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
1355                 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
1356                                 AR9287_AN_TXPC0_TXPCMODE,
1357                                 AR9287_AN_TXPC0_TXPCMODE_S,
1358                                 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
1359                 udelay(100);
1360         } else {
1361                 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1362                         ah->originalGain[i] =
1363                                 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1364                                                 AR_PHY_TX_GAIN);
1365                 ah->PDADCdelta = 0;
1366         }
1367 }
1368
1369 static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1370                               struct ath9k_channel *chan)
1371 {
1372         u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1373
1374         if (IS_CHAN_B(chan))
1375                 ctl |= CTL_11B;
1376         else if (IS_CHAN_G(chan))
1377                 ctl |= CTL_11G;
1378         else
1379                 ctl |= CTL_11A;
1380
1381         return ctl;
1382 }
1383
1384 static int ath9k_hw_process_ini(struct ath_hw *ah,
1385                                 struct ath9k_channel *chan)
1386 {
1387         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1388         int i, regWrites = 0;
1389         struct ieee80211_channel *channel = chan->chan;
1390         u32 modesIndex, freqIndex;
1391
1392         switch (chan->chanmode) {
1393         case CHANNEL_A:
1394         case CHANNEL_A_HT20:
1395                 modesIndex = 1;
1396                 freqIndex = 1;
1397                 break;
1398         case CHANNEL_A_HT40PLUS:
1399         case CHANNEL_A_HT40MINUS:
1400                 modesIndex = 2;
1401                 freqIndex = 1;
1402                 break;
1403         case CHANNEL_G:
1404         case CHANNEL_G_HT20:
1405         case CHANNEL_B:
1406                 modesIndex = 4;
1407                 freqIndex = 2;
1408                 break;
1409         case CHANNEL_G_HT40PLUS:
1410         case CHANNEL_G_HT40MINUS:
1411                 modesIndex = 3;
1412                 freqIndex = 2;
1413                 break;
1414
1415         default:
1416                 return -EINVAL;
1417         }
1418
1419         REG_WRITE(ah, AR_PHY(0), 0x00000007);
1420         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1421         ah->eep_ops->set_addac(ah, chan);
1422
1423         if (AR_SREV_5416_22_OR_LATER(ah)) {
1424                 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1425         } else {
1426                 struct ar5416IniArray temp;
1427                 u32 addacSize =
1428                         sizeof(u32) * ah->iniAddac.ia_rows *
1429                         ah->iniAddac.ia_columns;
1430
1431                 memcpy(ah->addac5416_21,
1432                        ah->iniAddac.ia_array, addacSize);
1433
1434                 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1435
1436                 temp.ia_array = ah->addac5416_21;
1437                 temp.ia_columns = ah->iniAddac.ia_columns;
1438                 temp.ia_rows = ah->iniAddac.ia_rows;
1439                 REG_WRITE_ARRAY(&temp, 1, regWrites);
1440         }
1441
1442         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1443
1444         for (i = 0; i < ah->iniModes.ia_rows; i++) {
1445                 u32 reg = INI_RA(&ah->iniModes, i, 0);
1446                 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1447
1448                 REG_WRITE(ah, reg, val);
1449
1450                 if (reg >= 0x7800 && reg < 0x78a0
1451                     && ah->config.analog_shiftreg) {
1452                         udelay(100);
1453                 }
1454
1455                 DO_DELAY(regWrites);
1456         }
1457
1458         if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
1459                 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1460
1461         if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1462             AR_SREV_9287_10_OR_LATER(ah))
1463                 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1464
1465         for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1466                 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1467                 u32 val = INI_RA(&ah->iniCommon, i, 1);
1468
1469                 REG_WRITE(ah, reg, val);
1470
1471                 if (reg >= 0x7800 && reg < 0x78a0
1472                     && ah->config.analog_shiftreg) {
1473                         udelay(100);
1474                 }
1475
1476                 DO_DELAY(regWrites);
1477         }
1478
1479         ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1480
1481         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1482                 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1483                                 regWrites);
1484         }
1485
1486         ath9k_hw_override_ini(ah, chan);
1487         ath9k_hw_set_regs(ah, chan);
1488         ath9k_hw_init_chain_masks(ah);
1489
1490         if (OLC_FOR_AR9280_20_LATER)
1491                 ath9k_olc_init(ah);
1492
1493         ah->eep_ops->set_txpower(ah, chan,
1494                                  ath9k_regd_get_ctl(regulatory, chan),
1495                                  channel->max_antenna_gain * 2,
1496                                  channel->max_power * 2,
1497                                  min((u32) MAX_RATE_POWER,
1498                                  (u32) regulatory->power_limit));
1499
1500         if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1501                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1502                           "ar5416SetRfRegs failed\n");
1503                 return -EIO;
1504         }
1505
1506         return 0;
1507 }
1508
1509 /****************************************/
1510 /* Reset and Channel Switching Routines */
1511 /****************************************/
1512
1513 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1514 {
1515         u32 rfMode = 0;
1516
1517         if (chan == NULL)
1518                 return;
1519
1520         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1521                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1522
1523         if (!AR_SREV_9280_10_OR_LATER(ah))
1524                 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1525                         AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1526
1527         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1528                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1529
1530         REG_WRITE(ah, AR_PHY_MODE, rfMode);
1531 }
1532
1533 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1534 {
1535         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1536 }
1537
1538 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1539 {
1540         u32 regval;
1541
1542         /*
1543          * set AHB_MODE not to do cacheline prefetches
1544         */
1545         regval = REG_READ(ah, AR_AHB_MODE);
1546         REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1547
1548         /*
1549          * let mac dma reads be in 128 byte chunks
1550          */
1551         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1552         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1553
1554         /*
1555          * Restore TX Trigger Level to its pre-reset value.
1556          * The initial value depends on whether aggregation is enabled, and is
1557          * adjusted whenever underruns are detected.
1558          */
1559         REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1560
1561         /*
1562          * let mac dma writes be in 128 byte chunks
1563          */
1564         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1565         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1566
1567         /*
1568          * Setup receive FIFO threshold to hold off TX activities
1569          */
1570         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1571
1572         /*
1573          * reduce the number of usable entries in PCU TXBUF to avoid
1574          * wrap around issues.
1575          */
1576         if (AR_SREV_9285(ah)) {
1577                 /* For AR9285 the number of Fifos are reduced to half.
1578                  * So set the usable tx buf size also to half to
1579                  * avoid data/delimiter underruns
1580                  */
1581                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1582                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1583         } else if (!AR_SREV_9271(ah)) {
1584                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1585                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1586         }
1587 }
1588
1589 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1590 {
1591         u32 val;
1592
1593         val = REG_READ(ah, AR_STA_ID1);
1594         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1595         switch (opmode) {
1596         case NL80211_IFTYPE_AP:
1597                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1598                           | AR_STA_ID1_KSRCH_MODE);
1599                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1600                 break;
1601         case NL80211_IFTYPE_ADHOC:
1602         case NL80211_IFTYPE_MESH_POINT:
1603                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1604                           | AR_STA_ID1_KSRCH_MODE);
1605                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1606                 break;
1607         case NL80211_IFTYPE_STATION:
1608         case NL80211_IFTYPE_MONITOR:
1609                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1610                 break;
1611         }
1612 }
1613
1614 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1615                                                  u32 coef_scaled,
1616                                                  u32 *coef_mantissa,
1617                                                  u32 *coef_exponent)
1618 {
1619         u32 coef_exp, coef_man;
1620
1621         for (coef_exp = 31; coef_exp > 0; coef_exp--)
1622                 if ((coef_scaled >> coef_exp) & 0x1)
1623                         break;
1624
1625         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1626
1627         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1628
1629         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1630         *coef_exponent = coef_exp - 16;
1631 }
1632
1633 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1634                                      struct ath9k_channel *chan)
1635 {
1636         u32 coef_scaled, ds_coef_exp, ds_coef_man;
1637         u32 clockMhzScaled = 0x64000000;
1638         struct chan_centers centers;
1639
1640         if (IS_CHAN_HALF_RATE(chan))
1641                 clockMhzScaled = clockMhzScaled >> 1;
1642         else if (IS_CHAN_QUARTER_RATE(chan))
1643                 clockMhzScaled = clockMhzScaled >> 2;
1644
1645         ath9k_hw_get_channel_centers(ah, chan, &centers);
1646         coef_scaled = clockMhzScaled / centers.synth_center;
1647
1648         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1649                                       &ds_coef_exp);
1650
1651         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1652                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1653         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1654                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1655
1656         coef_scaled = (9 * coef_scaled) / 10;
1657
1658         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1659                                       &ds_coef_exp);
1660
1661         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1662                       AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1663         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1664                       AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1665 }
1666
1667 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1668 {
1669         u32 rst_flags;
1670         u32 tmpReg;
1671
1672         if (AR_SREV_9100(ah)) {
1673                 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1674                 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1675                 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1676                 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1677                 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1678         }
1679
1680         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1681                   AR_RTC_FORCE_WAKE_ON_INT);
1682
1683         if (AR_SREV_9100(ah)) {
1684                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1685                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1686         } else {
1687                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1688                 if (tmpReg &
1689                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
1690                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1691                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1692                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1693                 } else {
1694                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1695                 }
1696
1697                 rst_flags = AR_RTC_RC_MAC_WARM;
1698                 if (type == ATH9K_RESET_COLD)
1699                         rst_flags |= AR_RTC_RC_MAC_COLD;
1700         }
1701
1702         REG_WRITE(ah, AR_RTC_RC, rst_flags);
1703         udelay(50);
1704
1705         REG_WRITE(ah, AR_RTC_RC, 0);
1706         if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1707                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1708                           "RTC stuck in MAC reset\n");
1709                 return false;
1710         }
1711
1712         if (!AR_SREV_9100(ah))
1713                 REG_WRITE(ah, AR_RC, 0);
1714
1715         if (AR_SREV_9100(ah))
1716                 udelay(50);
1717
1718         return true;
1719 }
1720
1721 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1722 {
1723         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1724                   AR_RTC_FORCE_WAKE_ON_INT);
1725
1726         if (!AR_SREV_9100(ah))
1727                 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1728
1729         REG_WRITE(ah, AR_RTC_RESET, 0);
1730         udelay(2);
1731
1732         if (!AR_SREV_9100(ah))
1733                 REG_WRITE(ah, AR_RC, 0);
1734
1735         REG_WRITE(ah, AR_RTC_RESET, 1);
1736
1737         if (!ath9k_hw_wait(ah,
1738                            AR_RTC_STATUS,
1739                            AR_RTC_STATUS_M,
1740                            AR_RTC_STATUS_ON,
1741                            AH_WAIT_TIMEOUT)) {
1742                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1743                           "RTC not waking up\n");
1744                 return false;
1745         }
1746
1747         ath9k_hw_read_revisions(ah);
1748
1749         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1750 }
1751
1752 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1753 {
1754         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1755                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1756
1757         switch (type) {
1758         case ATH9K_RESET_POWER_ON:
1759                 return ath9k_hw_set_reset_power_on(ah);
1760         case ATH9K_RESET_WARM:
1761         case ATH9K_RESET_COLD:
1762                 return ath9k_hw_set_reset(ah, type);
1763         default:
1764                 return false;
1765         }
1766 }
1767
1768 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan)
1769 {
1770         u32 phymode;
1771         u32 enableDacFifo = 0;
1772
1773         if (AR_SREV_9285_10_OR_LATER(ah))
1774                 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1775                                          AR_PHY_FC_ENABLE_DAC_FIFO);
1776
1777         phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1778                 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1779
1780         if (IS_CHAN_HT40(chan)) {
1781                 phymode |= AR_PHY_FC_DYN2040_EN;
1782
1783                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1784                     (chan->chanmode == CHANNEL_G_HT40PLUS))
1785                         phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1786
1787         }
1788         REG_WRITE(ah, AR_PHY_TURBO, phymode);
1789
1790         ath9k_hw_set11nmac2040(ah);
1791
1792         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1793         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1794 }
1795
1796 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1797                                 struct ath9k_channel *chan)
1798 {
1799         if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1800                 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1801                         return false;
1802         } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1803                 return false;
1804
1805         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1806                 return false;
1807
1808         ah->chip_fullsleep = false;
1809         ath9k_hw_init_pll(ah, chan);
1810         ath9k_hw_set_rfmode(ah, chan);
1811
1812         return true;
1813 }
1814
1815 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1816                                     struct ath9k_channel *chan)
1817 {
1818         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1819         struct ath_common *common = ath9k_hw_common(ah);
1820         struct ieee80211_channel *channel = chan->chan;
1821         u32 synthDelay, qnum;
1822
1823         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1824                 if (ath9k_hw_numtxpending(ah, qnum)) {
1825                         ath_print(common, ATH_DBG_QUEUE,
1826                                   "Transmit frames pending on "
1827                                   "queue %d\n", qnum);
1828                         return false;
1829                 }
1830         }
1831
1832         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1833         if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1834                            AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1835                 ath_print(common, ATH_DBG_FATAL,
1836                           "Could not kill baseband RX\n");
1837                 return false;
1838         }
1839
1840         ath9k_hw_set_regs(ah, chan);
1841
1842         if (AR_SREV_9280_10_OR_LATER(ah)) {
1843                 ath9k_hw_ar9280_set_channel(ah, chan);
1844         } else {
1845                 if (!(ath9k_hw_set_channel(ah, chan))) {
1846                         ath_print(common, ATH_DBG_FATAL,
1847                                   "Failed to set channel\n");
1848                         return false;
1849                 }
1850         }
1851
1852         ah->eep_ops->set_txpower(ah, chan,
1853                              ath9k_regd_get_ctl(regulatory, chan),
1854                              channel->max_antenna_gain * 2,
1855                              channel->max_power * 2,
1856                              min((u32) MAX_RATE_POWER,
1857                              (u32) regulatory->power_limit));
1858
1859         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1860         if (IS_CHAN_B(chan))
1861                 synthDelay = (4 * synthDelay) / 22;
1862         else
1863                 synthDelay /= 10;
1864
1865         udelay(synthDelay + BASE_ACTIVATE_DELAY);
1866
1867         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1868
1869         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1870                 ath9k_hw_set_delta_slope(ah, chan);
1871
1872         if (AR_SREV_9280_10_OR_LATER(ah))
1873                 ath9k_hw_9280_spur_mitigate(ah, chan);
1874         else
1875                 ath9k_hw_spur_mitigate(ah, chan);
1876
1877         if (!chan->oneTimeCalsDone)
1878                 chan->oneTimeCalsDone = true;
1879
1880         return true;
1881 }
1882
1883 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1884 {
1885         int bb_spur = AR_NO_SPUR;
1886         int freq;
1887         int bin, cur_bin;
1888         int bb_spur_off, spur_subchannel_sd;
1889         int spur_freq_sd;
1890         int spur_delta_phase;
1891         int denominator;
1892         int upper, lower, cur_vit_mask;
1893         int tmp, newVal;
1894         int i;
1895         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1896                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1897         };
1898         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1899                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1900         };
1901         int inc[4] = { 0, 100, 0, 0 };
1902         struct chan_centers centers;
1903
1904         int8_t mask_m[123];
1905         int8_t mask_p[123];
1906         int8_t mask_amt;
1907         int tmp_mask;
1908         int cur_bb_spur;
1909         bool is2GHz = IS_CHAN_2GHZ(chan);
1910
1911         memset(&mask_m, 0, sizeof(int8_t) * 123);
1912         memset(&mask_p, 0, sizeof(int8_t) * 123);
1913
1914         ath9k_hw_get_channel_centers(ah, chan, &centers);
1915         freq = centers.synth_center;
1916
1917         ah->config.spurmode = SPUR_ENABLE_EEPROM;
1918         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1919                 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1920
1921                 if (is2GHz)
1922                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1923                 else
1924                         cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1925
1926                 if (AR_NO_SPUR == cur_bb_spur)
1927                         break;
1928                 cur_bb_spur = cur_bb_spur - freq;
1929
1930                 if (IS_CHAN_HT40(chan)) {
1931                         if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1932                             (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1933                                 bb_spur = cur_bb_spur;
1934                                 break;
1935                         }
1936                 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1937                            (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1938                         bb_spur = cur_bb_spur;
1939                         break;
1940                 }
1941         }
1942
1943         if (AR_NO_SPUR == bb_spur) {
1944                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1945                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1946                 return;
1947         } else {
1948                 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1949                             AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1950         }
1951
1952         bin = bb_spur * 320;
1953
1954         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1955
1956         newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1957                         AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1958                         AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1959                         AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1960         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1961
1962         newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1963                   AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1964                   AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1965                   AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1966                   SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1967         REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1968
1969         if (IS_CHAN_HT40(chan)) {
1970                 if (bb_spur < 0) {
1971                         spur_subchannel_sd = 1;
1972                         bb_spur_off = bb_spur + 10;
1973                 } else {
1974                         spur_subchannel_sd = 0;
1975                         bb_spur_off = bb_spur - 10;
1976                 }
1977         } else {
1978                 spur_subchannel_sd = 0;
1979                 bb_spur_off = bb_spur;
1980         }
1981
1982         if (IS_CHAN_HT40(chan))
1983                 spur_delta_phase =
1984                         ((bb_spur * 262144) /
1985                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1986         else
1987                 spur_delta_phase =
1988                         ((bb_spur * 524288) /
1989                          10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1990
1991         denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1992         spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1993
1994         newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1995                   SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1996                   SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1997         REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1998
1999         newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
2000         REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
2001
2002         cur_bin = -6000;
2003         upper = bin + 100;
2004         lower = bin - 100;
2005
2006         for (i = 0; i < 4; i++) {
2007                 int pilot_mask = 0;
2008                 int chan_mask = 0;
2009                 int bp = 0;
2010                 for (bp = 0; bp < 30; bp++) {
2011                         if ((cur_bin > lower) && (cur_bin < upper)) {
2012                                 pilot_mask = pilot_mask | 0x1 << bp;
2013                                 chan_mask = chan_mask | 0x1 << bp;
2014                         }
2015                         cur_bin += 100;
2016                 }
2017                 cur_bin += inc[i];
2018                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2019                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2020         }
2021
2022         cur_vit_mask = 6100;
2023         upper = bin + 120;
2024         lower = bin - 120;
2025
2026         for (i = 0; i < 123; i++) {
2027                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2028
2029                         /* workaround for gcc bug #37014 */
2030                         volatile int tmp_v = abs(cur_vit_mask - bin);
2031
2032                         if (tmp_v < 75)
2033                                 mask_amt = 1;
2034                         else
2035                                 mask_amt = 0;
2036                         if (cur_vit_mask < 0)
2037                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2038                         else
2039                                 mask_p[cur_vit_mask / 100] = mask_amt;
2040                 }
2041                 cur_vit_mask -= 100;
2042         }
2043
2044         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2045                 | (mask_m[48] << 26) | (mask_m[49] << 24)
2046                 | (mask_m[50] << 22) | (mask_m[51] << 20)
2047                 | (mask_m[52] << 18) | (mask_m[53] << 16)
2048                 | (mask_m[54] << 14) | (mask_m[55] << 12)
2049                 | (mask_m[56] << 10) | (mask_m[57] << 8)
2050                 | (mask_m[58] << 6) | (mask_m[59] << 4)
2051                 | (mask_m[60] << 2) | (mask_m[61] << 0);
2052         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2053         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2054
2055         tmp_mask = (mask_m[31] << 28)
2056                 | (mask_m[32] << 26) | (mask_m[33] << 24)
2057                 | (mask_m[34] << 22) | (mask_m[35] << 20)
2058                 | (mask_m[36] << 18) | (mask_m[37] << 16)
2059                 | (mask_m[48] << 14) | (mask_m[39] << 12)
2060                 | (mask_m[40] << 10) | (mask_m[41] << 8)
2061                 | (mask_m[42] << 6) | (mask_m[43] << 4)
2062                 | (mask_m[44] << 2) | (mask_m[45] << 0);
2063         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2064         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2065
2066         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2067                 | (mask_m[18] << 26) | (mask_m[18] << 24)
2068                 | (mask_m[20] << 22) | (mask_m[20] << 20)
2069                 | (mask_m[22] << 18) | (mask_m[22] << 16)
2070                 | (mask_m[24] << 14) | (mask_m[24] << 12)
2071                 | (mask_m[25] << 10) | (mask_m[26] << 8)
2072                 | (mask_m[27] << 6) | (mask_m[28] << 4)
2073                 | (mask_m[29] << 2) | (mask_m[30] << 0);
2074         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2075         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2076
2077         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2078                 | (mask_m[2] << 26) | (mask_m[3] << 24)
2079                 | (mask_m[4] << 22) | (mask_m[5] << 20)
2080                 | (mask_m[6] << 18) | (mask_m[7] << 16)
2081                 | (mask_m[8] << 14) | (mask_m[9] << 12)
2082                 | (mask_m[10] << 10) | (mask_m[11] << 8)
2083                 | (mask_m[12] << 6) | (mask_m[13] << 4)
2084                 | (mask_m[14] << 2) | (mask_m[15] << 0);
2085         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2086         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2087
2088         tmp_mask = (mask_p[15] << 28)
2089                 | (mask_p[14] << 26) | (mask_p[13] << 24)
2090                 | (mask_p[12] << 22) | (mask_p[11] << 20)
2091                 | (mask_p[10] << 18) | (mask_p[9] << 16)
2092                 | (mask_p[8] << 14) | (mask_p[7] << 12)
2093                 | (mask_p[6] << 10) | (mask_p[5] << 8)
2094                 | (mask_p[4] << 6) | (mask_p[3] << 4)
2095                 | (mask_p[2] << 2) | (mask_p[1] << 0);
2096         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2097         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2098
2099         tmp_mask = (mask_p[30] << 28)
2100                 | (mask_p[29] << 26) | (mask_p[28] << 24)
2101                 | (mask_p[27] << 22) | (mask_p[26] << 20)
2102                 | (mask_p[25] << 18) | (mask_p[24] << 16)
2103                 | (mask_p[23] << 14) | (mask_p[22] << 12)
2104                 | (mask_p[21] << 10) | (mask_p[20] << 8)
2105                 | (mask_p[19] << 6) | (mask_p[18] << 4)
2106                 | (mask_p[17] << 2) | (mask_p[16] << 0);
2107         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2108         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2109
2110         tmp_mask = (mask_p[45] << 28)
2111                 | (mask_p[44] << 26) | (mask_p[43] << 24)
2112                 | (mask_p[42] << 22) | (mask_p[41] << 20)
2113                 | (mask_p[40] << 18) | (mask_p[39] << 16)
2114                 | (mask_p[38] << 14) | (mask_p[37] << 12)
2115                 | (mask_p[36] << 10) | (mask_p[35] << 8)
2116                 | (mask_p[34] << 6) | (mask_p[33] << 4)
2117                 | (mask_p[32] << 2) | (mask_p[31] << 0);
2118         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2119         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2120
2121         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2122                 | (mask_p[59] << 26) | (mask_p[58] << 24)
2123                 | (mask_p[57] << 22) | (mask_p[56] << 20)
2124                 | (mask_p[55] << 18) | (mask_p[54] << 16)
2125                 | (mask_p[53] << 14) | (mask_p[52] << 12)
2126                 | (mask_p[51] << 10) | (mask_p[50] << 8)
2127                 | (mask_p[49] << 6) | (mask_p[48] << 4)
2128                 | (mask_p[47] << 2) | (mask_p[46] << 0);
2129         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2130         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2131 }
2132
2133 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
2134 {
2135         int bb_spur = AR_NO_SPUR;
2136         int bin, cur_bin;
2137         int spur_freq_sd;
2138         int spur_delta_phase;
2139         int denominator;
2140         int upper, lower, cur_vit_mask;
2141         int tmp, new;
2142         int i;
2143         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
2144                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
2145         };
2146         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
2147                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
2148         };
2149         int inc[4] = { 0, 100, 0, 0 };
2150
2151         int8_t mask_m[123];
2152         int8_t mask_p[123];
2153         int8_t mask_amt;
2154         int tmp_mask;
2155         int cur_bb_spur;
2156         bool is2GHz = IS_CHAN_2GHZ(chan);
2157
2158         memset(&mask_m, 0, sizeof(int8_t) * 123);
2159         memset(&mask_p, 0, sizeof(int8_t) * 123);
2160
2161         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2162                 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
2163                 if (AR_NO_SPUR == cur_bb_spur)
2164                         break;
2165                 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2166                 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2167                         bb_spur = cur_bb_spur;
2168                         break;
2169                 }
2170         }
2171
2172         if (AR_NO_SPUR == bb_spur)
2173                 return;
2174
2175         bin = bb_spur * 32;
2176
2177         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2178         new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2179                      AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2180                      AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2181                      AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2182
2183         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2184
2185         new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2186                AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2187                AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2188                AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2189                SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2190         REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2191
2192         spur_delta_phase = ((bb_spur * 524288) / 100) &
2193                 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2194
2195         denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2196         spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2197
2198         new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2199                SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2200                SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2201         REG_WRITE(ah, AR_PHY_TIMING11, new);
2202
2203         cur_bin = -6000;
2204         upper = bin + 100;
2205         lower = bin - 100;
2206
2207         for (i = 0; i < 4; i++) {
2208                 int pilot_mask = 0;
2209                 int chan_mask = 0;
2210                 int bp = 0;
2211                 for (bp = 0; bp < 30; bp++) {
2212                         if ((cur_bin > lower) && (cur_bin < upper)) {
2213                                 pilot_mask = pilot_mask | 0x1 << bp;
2214                                 chan_mask = chan_mask | 0x1 << bp;
2215                         }
2216                         cur_bin += 100;
2217                 }
2218                 cur_bin += inc[i];
2219                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2220                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2221         }
2222
2223         cur_vit_mask = 6100;
2224         upper = bin + 120;
2225         lower = bin - 120;
2226
2227         for (i = 0; i < 123; i++) {
2228                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2229
2230                         /* workaround for gcc bug #37014 */
2231                         volatile int tmp_v = abs(cur_vit_mask - bin);
2232
2233                         if (tmp_v < 75)
2234                                 mask_amt = 1;
2235                         else
2236                                 mask_amt = 0;
2237                         if (cur_vit_mask < 0)
2238                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2239                         else
2240                                 mask_p[cur_vit_mask / 100] = mask_amt;
2241                 }
2242                 cur_vit_mask -= 100;
2243         }
2244
2245         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2246                 | (mask_m[48] << 26) | (mask_m[49] << 24)
2247                 | (mask_m[50] << 22) | (mask_m[51] << 20)
2248                 | (mask_m[52] << 18) | (mask_m[53] << 16)
2249                 | (mask_m[54] << 14) | (mask_m[55] << 12)
2250                 | (mask_m[56] << 10) | (mask_m[57] << 8)
2251                 | (mask_m[58] << 6) | (mask_m[59] << 4)
2252                 | (mask_m[60] << 2) | (mask_m[61] << 0);
2253         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2254         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2255
2256         tmp_mask = (mask_m[31] << 28)
2257                 | (mask_m[32] << 26) | (mask_m[33] << 24)
2258                 | (mask_m[34] << 22) | (mask_m[35] << 20)
2259                 | (mask_m[36] << 18) | (mask_m[37] << 16)
2260                 | (mask_m[48] << 14) | (mask_m[39] << 12)
2261                 | (mask_m[40] << 10) | (mask_m[41] << 8)
2262                 | (mask_m[42] << 6) | (mask_m[43] << 4)
2263                 | (mask_m[44] << 2) | (mask_m[45] << 0);
2264         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2265         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2266
2267         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2268                 | (mask_m[18] << 26) | (mask_m[18] << 24)
2269                 | (mask_m[20] << 22) | (mask_m[20] << 20)
2270                 | (mask_m[22] << 18) | (mask_m[22] << 16)
2271                 | (mask_m[24] << 14) | (mask_m[24] << 12)
2272                 | (mask_m[25] << 10) | (mask_m[26] << 8)
2273                 | (mask_m[27] << 6) | (mask_m[28] << 4)
2274                 | (mask_m[29] << 2) | (mask_m[30] << 0);
2275         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2276         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2277
2278         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2279                 | (mask_m[2] << 26) | (mask_m[3] << 24)
2280                 | (mask_m[4] << 22) | (mask_m[5] << 20)
2281                 | (mask_m[6] << 18) | (mask_m[7] << 16)
2282                 | (mask_m[8] << 14) | (mask_m[9] << 12)
2283                 | (mask_m[10] << 10) | (mask_m[11] << 8)
2284                 | (mask_m[12] << 6) | (mask_m[13] << 4)
2285                 | (mask_m[14] << 2) | (mask_m[15] << 0);
2286         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2287         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2288
2289         tmp_mask = (mask_p[15] << 28)
2290                 | (mask_p[14] << 26) | (mask_p[13] << 24)
2291                 | (mask_p[12] << 22) | (mask_p[11] << 20)
2292                 | (mask_p[10] << 18) | (mask_p[9] << 16)
2293                 | (mask_p[8] << 14) | (mask_p[7] << 12)
2294                 | (mask_p[6] << 10) | (mask_p[5] << 8)
2295                 | (mask_p[4] << 6) | (mask_p[3] << 4)
2296                 | (mask_p[2] << 2) | (mask_p[1] << 0);
2297         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2298         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2299
2300         tmp_mask = (mask_p[30] << 28)
2301                 | (mask_p[29] << 26) | (mask_p[28] << 24)
2302                 | (mask_p[27] << 22) | (mask_p[26] << 20)
2303                 | (mask_p[25] << 18) | (mask_p[24] << 16)
2304                 | (mask_p[23] << 14) | (mask_p[22] << 12)
2305                 | (mask_p[21] << 10) | (mask_p[20] << 8)
2306                 | (mask_p[19] << 6) | (mask_p[18] << 4)
2307                 | (mask_p[17] << 2) | (mask_p[16] << 0);
2308         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2309         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2310
2311         tmp_mask = (mask_p[45] << 28)
2312                 | (mask_p[44] << 26) | (mask_p[43] << 24)
2313                 | (mask_p[42] << 22) | (mask_p[41] << 20)
2314                 | (mask_p[40] << 18) | (mask_p[39] << 16)
2315                 | (mask_p[38] << 14) | (mask_p[37] << 12)
2316                 | (mask_p[36] << 10) | (mask_p[35] << 8)
2317                 | (mask_p[34] << 6) | (mask_p[33] << 4)
2318                 | (mask_p[32] << 2) | (mask_p[31] << 0);
2319         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2320         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2321
2322         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2323                 | (mask_p[59] << 26) | (mask_p[58] << 24)
2324                 | (mask_p[57] << 22) | (mask_p[56] << 20)
2325                 | (mask_p[55] << 18) | (mask_p[54] << 16)
2326                 | (mask_p[53] << 14) | (mask_p[52] << 12)
2327                 | (mask_p[51] << 10) | (mask_p[50] << 8)
2328                 | (mask_p[49] << 6) | (mask_p[48] << 4)
2329                 | (mask_p[47] << 2) | (mask_p[46] << 0);
2330         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2331         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2332 }
2333
2334 static void ath9k_enable_rfkill(struct ath_hw *ah)
2335 {
2336         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
2337                     AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
2338
2339         REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
2340                     AR_GPIO_INPUT_MUX2_RFSILENT);
2341
2342         ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
2343         REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
2344 }
2345
2346 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2347                     bool bChannelChange)
2348 {
2349         struct ath_common *common = ath9k_hw_common(ah);
2350         u32 saveLedState;
2351         struct ath9k_channel *curchan = ah->curchan;
2352         u32 saveDefAntenna;
2353         u32 macStaId1;
2354         u64 tsf = 0;
2355         int i, rx_chainmask, r;
2356
2357         ah->txchainmask = common->tx_chainmask;
2358         ah->rxchainmask = common->rx_chainmask;
2359
2360         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2361                 return -EIO;
2362
2363         if (curchan && !ah->chip_fullsleep)
2364                 ath9k_hw_getnf(ah, curchan);
2365
2366         if (bChannelChange &&
2367             (ah->chip_fullsleep != true) &&
2368             (ah->curchan != NULL) &&
2369             (chan->channel != ah->curchan->channel) &&
2370             ((chan->channelFlags & CHANNEL_ALL) ==
2371              (ah->curchan->channelFlags & CHANNEL_ALL)) &&
2372              !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
2373              IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
2374
2375                 if (ath9k_hw_channel_change(ah, chan)) {
2376                         ath9k_hw_loadnf(ah, ah->curchan);
2377                         ath9k_hw_start_nfcal(ah);
2378                         return 0;
2379                 }
2380         }
2381
2382         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2383         if (saveDefAntenna == 0)
2384                 saveDefAntenna = 1;
2385
2386         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2387
2388         /* For chips on which RTC reset is done, save TSF before it gets cleared */
2389         if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
2390                 tsf = ath9k_hw_gettsf64(ah);
2391
2392         saveLedState = REG_READ(ah, AR_CFG_LED) &
2393                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2394                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2395
2396         ath9k_hw_mark_phy_inactive(ah);
2397
2398         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
2399                 REG_WRITE(ah,
2400                           AR9271_RESET_POWER_DOWN_CONTROL,
2401                           AR9271_RADIO_RF_RST);
2402                 udelay(50);
2403         }
2404
2405         if (!ath9k_hw_chip_reset(ah, chan)) {
2406                 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
2407                 return -EINVAL;
2408         }
2409
2410         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
2411                 ah->htc_reset_init = false;
2412                 REG_WRITE(ah,
2413                           AR9271_RESET_POWER_DOWN_CONTROL,
2414                           AR9271_GATE_MAC_CTL);
2415                 udelay(50);
2416         }
2417
2418         /* Restore TSF */
2419         if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
2420                 ath9k_hw_settsf64(ah, tsf);
2421
2422         if (AR_SREV_9280_10_OR_LATER(ah))
2423                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
2424
2425         if (AR_SREV_9287_12_OR_LATER(ah)) {
2426                 /* Enable ASYNC FIFO */
2427                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2428                                 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
2429                 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
2430                 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2431                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2432                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2433                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2434         }
2435         r = ath9k_hw_process_ini(ah, chan);
2436         if (r)
2437                 return r;
2438
2439         /* Setup MFP options for CCMP */
2440         if (AR_SREV_9280_20_OR_LATER(ah)) {
2441                 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2442                  * frames when constructing CCMP AAD. */
2443                 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2444                               0xc7ff);
2445                 ah->sw_mgmt_crypto = false;
2446         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2447                 /* Disable hardware crypto for management frames */
2448                 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2449                             AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2450                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2451                             AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2452                 ah->sw_mgmt_crypto = true;
2453         } else
2454                 ah->sw_mgmt_crypto = true;
2455
2456         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2457                 ath9k_hw_set_delta_slope(ah, chan);
2458
2459         if (AR_SREV_9280_10_OR_LATER(ah))
2460                 ath9k_hw_9280_spur_mitigate(ah, chan);
2461         else
2462                 ath9k_hw_spur_mitigate(ah, chan);
2463
2464         ah->eep_ops->set_board_values(ah, chan);
2465
2466         ath9k_hw_decrease_chain_power(ah, chan);
2467
2468         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
2469         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
2470                   | macStaId1
2471                   | AR_STA_ID1_RTS_USE_DEF
2472                   | (ah->config.
2473                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2474                   | ah->sta_id1_defaults);
2475         ath9k_hw_set_operating_mode(ah, ah->opmode);
2476
2477         ath_hw_setbssidmask(common);
2478
2479         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2480
2481         ath9k_hw_write_associd(ah);
2482
2483         REG_WRITE(ah, AR_ISR, ~0);
2484
2485         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2486
2487         if (AR_SREV_9280_10_OR_LATER(ah))
2488                 ath9k_hw_ar9280_set_channel(ah, chan);
2489         else
2490                 if (!(ath9k_hw_set_channel(ah, chan)))
2491                         return -EIO;
2492
2493         for (i = 0; i < AR_NUM_DCU; i++)
2494                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2495
2496         ah->intr_txqs = 0;
2497         for (i = 0; i < ah->caps.total_queues; i++)
2498                 ath9k_hw_resettxqueue(ah, i);
2499
2500         ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2501         ath9k_hw_init_qos(ah);
2502
2503         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2504                 ath9k_enable_rfkill(ah);
2505
2506         ath9k_hw_init_user_settings(ah);
2507
2508         if (AR_SREV_9287_12_OR_LATER(ah)) {
2509                 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
2510                           AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
2511                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
2512                           AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
2513                 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
2514                           AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
2515
2516                 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
2517                 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
2518
2519                 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2520                             AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2521                 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2522                               AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2523         }
2524         if (AR_SREV_9287_12_OR_LATER(ah)) {
2525                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2526                                 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2527         }
2528
2529         REG_WRITE(ah, AR_STA_ID1,
2530                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2531
2532         ath9k_hw_set_dma(ah);
2533
2534         REG_WRITE(ah, AR_OBS, 8);
2535
2536         if (ah->config.intr_mitigation) {
2537                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2538                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2539         }
2540
2541         ath9k_hw_init_bb(ah, chan);
2542
2543         if (!ath9k_hw_init_cal(ah, chan))
2544                 return -EIO;
2545
2546         rx_chainmask = ah->rxchainmask;
2547         if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2548                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2549                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2550         }
2551
2552         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2553
2554         /*
2555          * For big endian systems turn on swapping for descriptors
2556          */
2557         if (AR_SREV_9100(ah)) {
2558                 u32 mask;
2559                 mask = REG_READ(ah, AR_CFG);
2560                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2561                         ath_print(common, ATH_DBG_RESET,
2562                                 "CFG Byte Swap Set 0x%x\n", mask);
2563                 } else {
2564                         mask =
2565                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2566                         REG_WRITE(ah, AR_CFG, mask);
2567                         ath_print(common, ATH_DBG_RESET,
2568                                 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2569                 }
2570         } else {
2571                 /* Configure AR9271 target WLAN */
2572                 if (AR_SREV_9271(ah))
2573                         REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
2574 #ifdef __BIG_ENDIAN
2575                 else
2576                         REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2577 #endif
2578         }
2579
2580         if (ah->btcoex_hw.enabled)
2581                 ath9k_hw_btcoex_enable(ah);
2582
2583         return 0;
2584 }
2585 EXPORT_SYMBOL(ath9k_hw_reset);
2586
2587 /************************/
2588 /* Key Cache Management */
2589 /************************/
2590
2591 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2592 {
2593         u32 keyType;
2594
2595         if (entry >= ah->caps.keycache_size) {
2596                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2597                           "keychache entry %u out of range\n", entry);
2598                 return false;
2599         }
2600
2601         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2602
2603         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2604         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2605         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2606         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2607         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2608         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2609         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2610         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2611
2612         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2613                 u16 micentry = entry + 64;
2614
2615                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2616                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2617                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2618                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2619
2620         }
2621
2622         return true;
2623 }
2624 EXPORT_SYMBOL(ath9k_hw_keyreset);
2625
2626 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2627 {
2628         u32 macHi, macLo;
2629
2630         if (entry >= ah->caps.keycache_size) {
2631                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2632                           "keychache entry %u out of range\n", entry);
2633                 return false;
2634         }
2635
2636         if (mac != NULL) {
2637                 macHi = (mac[5] << 8) | mac[4];
2638                 macLo = (mac[3] << 24) |
2639                         (mac[2] << 16) |
2640                         (mac[1] << 8) |
2641                         mac[0];
2642                 macLo >>= 1;
2643                 macLo |= (macHi & 1) << 31;
2644                 macHi >>= 1;
2645         } else {
2646                 macLo = macHi = 0;
2647         }
2648         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2649         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2650
2651         return true;
2652 }
2653 EXPORT_SYMBOL(ath9k_hw_keysetmac);
2654
2655 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2656                                  const struct ath9k_keyval *k,
2657                                  const u8 *mac)
2658 {
2659         const struct ath9k_hw_capabilities *pCap = &ah->caps;
2660         struct ath_common *common = ath9k_hw_common(ah);
2661         u32 key0, key1, key2, key3, key4;
2662         u32 keyType;
2663
2664         if (entry >= pCap->keycache_size) {
2665                 ath_print(common, ATH_DBG_FATAL,
2666                           "keycache entry %u out of range\n", entry);
2667                 return false;
2668         }
2669
2670         switch (k->kv_type) {
2671         case ATH9K_CIPHER_AES_OCB:
2672                 keyType = AR_KEYTABLE_TYPE_AES;
2673                 break;
2674         case ATH9K_CIPHER_AES_CCM:
2675                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2676                         ath_print(common, ATH_DBG_ANY,
2677                                   "AES-CCM not supported by mac rev 0x%x\n",
2678                                   ah->hw_version.macRev);
2679                         return false;
2680                 }
2681                 keyType = AR_KEYTABLE_TYPE_CCM;
2682                 break;
2683         case ATH9K_CIPHER_TKIP:
2684                 keyType = AR_KEYTABLE_TYPE_TKIP;
2685                 if (ATH9K_IS_MIC_ENABLED(ah)
2686                     && entry + 64 >= pCap->keycache_size) {
2687                         ath_print(common, ATH_DBG_ANY,
2688                                   "entry %u inappropriate for TKIP\n", entry);
2689                         return false;
2690                 }
2691                 break;
2692         case ATH9K_CIPHER_WEP:
2693                 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
2694                         ath_print(common, ATH_DBG_ANY,
2695                                   "WEP key length %u too small\n", k->kv_len);
2696                         return false;
2697                 }
2698                 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
2699                         keyType = AR_KEYTABLE_TYPE_40;
2700                 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2701                         keyType = AR_KEYTABLE_TYPE_104;
2702                 else
2703                         keyType = AR_KEYTABLE_TYPE_128;
2704                 break;
2705         case ATH9K_CIPHER_CLR:
2706                 keyType = AR_KEYTABLE_TYPE_CLR;
2707                 break;
2708         default:
2709                 ath_print(common, ATH_DBG_FATAL,
2710                           "cipher %u not supported\n", k->kv_type);
2711                 return false;
2712         }
2713
2714         key0 = get_unaligned_le32(k->kv_val + 0);
2715         key1 = get_unaligned_le16(k->kv_val + 4);
2716         key2 = get_unaligned_le32(k->kv_val + 6);
2717         key3 = get_unaligned_le16(k->kv_val + 10);
2718         key4 = get_unaligned_le32(k->kv_val + 12);
2719         if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2720                 key4 &= 0xff;
2721
2722         /*
2723          * Note: Key cache registers access special memory area that requires
2724          * two 32-bit writes to actually update the values in the internal
2725          * memory. Consequently, the exact order and pairs used here must be
2726          * maintained.
2727          */
2728
2729         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2730                 u16 micentry = entry + 64;
2731
2732                 /*
2733                  * Write inverted key[47:0] first to avoid Michael MIC errors
2734                  * on frames that could be sent or received at the same time.
2735                  * The correct key will be written in the end once everything
2736                  * else is ready.
2737                  */
2738                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2739                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2740
2741                 /* Write key[95:48] */
2742                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2743                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2744
2745                 /* Write key[127:96] and key type */
2746                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2747                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2748
2749                 /* Write MAC address for the entry */
2750                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2751
2752                 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2753                         /*
2754                          * TKIP uses two key cache entries:
2755                          * Michael MIC TX/RX keys in the same key cache entry
2756                          * (idx = main index + 64):
2757                          * key0 [31:0] = RX key [31:0]
2758                          * key1 [15:0] = TX key [31:16]
2759                          * key1 [31:16] = reserved
2760                          * key2 [31:0] = RX key [63:32]
2761                          * key3 [15:0] = TX key [15:0]
2762                          * key3 [31:16] = reserved
2763                          * key4 [31:0] = TX key [63:32]
2764                          */
2765                         u32 mic0, mic1, mic2, mic3, mic4;
2766
2767                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2768                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2769                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2770                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2771                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
2772
2773                         /* Write RX[31:0] and TX[31:16] */
2774                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2775                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2776
2777                         /* Write RX[63:32] and TX[15:0] */
2778                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2779                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2780
2781                         /* Write TX[63:32] and keyType(reserved) */
2782                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2783                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2784                                   AR_KEYTABLE_TYPE_CLR);
2785
2786                 } else {
2787                         /*
2788                          * TKIP uses four key cache entries (two for group
2789                          * keys):
2790                          * Michael MIC TX/RX keys are in different key cache
2791                          * entries (idx = main index + 64 for TX and
2792                          * main index + 32 + 96 for RX):
2793                          * key0 [31:0] = TX/RX MIC key [31:0]
2794                          * key1 [31:0] = reserved
2795                          * key2 [31:0] = TX/RX MIC key [63:32]
2796                          * key3 [31:0] = reserved
2797                          * key4 [31:0] = reserved
2798                          *
2799                          * Upper layer code will call this function separately
2800                          * for TX and RX keys when these registers offsets are
2801                          * used.
2802                          */
2803                         u32 mic0, mic2;
2804
2805                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2806                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2807
2808                         /* Write MIC key[31:0] */
2809                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2810                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2811
2812                         /* Write MIC key[63:32] */
2813                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2814                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2815
2816                         /* Write TX[63:32] and keyType(reserved) */
2817                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2818                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2819                                   AR_KEYTABLE_TYPE_CLR);
2820                 }
2821
2822                 /* MAC address registers are reserved for the MIC entry */
2823                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2824                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2825
2826                 /*
2827                  * Write the correct (un-inverted) key[47:0] last to enable
2828                  * TKIP now that all other registers are set with correct
2829                  * values.
2830                  */
2831                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2832                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2833         } else {
2834                 /* Write key[47:0] */
2835                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2836                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2837
2838                 /* Write key[95:48] */
2839                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2840                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2841
2842                 /* Write key[127:96] and key type */
2843                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2844                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2845
2846                 /* Write MAC address for the entry */
2847                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2848         }
2849
2850         return true;
2851 }
2852 EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
2853
2854 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2855 {
2856         if (entry < ah->caps.keycache_size) {
2857                 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2858                 if (val & AR_KEYTABLE_VALID)
2859                         return true;
2860         }
2861         return false;
2862 }
2863 EXPORT_SYMBOL(ath9k_hw_keyisvalid);
2864
2865 /******************************/
2866 /* Power Management (Chipset) */
2867 /******************************/
2868
2869 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2870 {
2871         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2872         if (setChip) {
2873                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2874                             AR_RTC_FORCE_WAKE_EN);
2875                 if (!AR_SREV_9100(ah))
2876                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2877
2878                 if(!AR_SREV_5416(ah))
2879                         REG_CLR_BIT(ah, (AR_RTC_RESET),
2880                                     AR_RTC_RESET_EN);
2881         }
2882 }
2883
2884 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2885 {
2886         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2887         if (setChip) {
2888                 struct ath9k_hw_capabilities *pCap = &ah->caps;
2889
2890                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2891                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2892                                   AR_RTC_FORCE_WAKE_ON_INT);
2893                 } else {
2894                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2895                                     AR_RTC_FORCE_WAKE_EN);
2896                 }
2897         }
2898 }
2899
2900 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2901 {
2902         u32 val;
2903         int i;
2904
2905         if (setChip) {
2906                 if ((REG_READ(ah, AR_RTC_STATUS) &
2907                      AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2908                         if (ath9k_hw_set_reset_reg(ah,
2909                                            ATH9K_RESET_POWER_ON) != true) {
2910                                 return false;
2911                         }
2912                         ath9k_hw_init_pll(ah, NULL);
2913                 }
2914                 if (AR_SREV_9100(ah))
2915                         REG_SET_BIT(ah, AR_RTC_RESET,
2916                                     AR_RTC_RESET_EN);
2917
2918                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2919                             AR_RTC_FORCE_WAKE_EN);
2920                 udelay(50);
2921
2922                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2923                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2924                         if (val == AR_RTC_STATUS_ON)
2925                                 break;
2926                         udelay(50);
2927                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2928                                     AR_RTC_FORCE_WAKE_EN);
2929                 }
2930                 if (i == 0) {
2931                         ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2932                                   "Failed to wakeup in %uus\n",
2933                                   POWER_UP_TIME / 20);
2934                         return false;
2935                 }
2936         }
2937
2938         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2939
2940         return true;
2941 }
2942
2943 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2944 {
2945         struct ath_common *common = ath9k_hw_common(ah);
2946         int status = true, setChip = true;
2947         static const char *modes[] = {
2948                 "AWAKE",
2949                 "FULL-SLEEP",
2950                 "NETWORK SLEEP",
2951                 "UNDEFINED"
2952         };
2953
2954         if (ah->power_mode == mode)
2955                 return status;
2956
2957         ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
2958                   modes[ah->power_mode], modes[mode]);
2959
2960         switch (mode) {
2961         case ATH9K_PM_AWAKE:
2962                 status = ath9k_hw_set_power_awake(ah, setChip);
2963                 break;
2964         case ATH9K_PM_FULL_SLEEP:
2965                 ath9k_set_power_sleep(ah, setChip);
2966                 ah->chip_fullsleep = true;
2967                 break;
2968         case ATH9K_PM_NETWORK_SLEEP:
2969                 ath9k_set_power_network_sleep(ah, setChip);
2970                 break;
2971         default:
2972                 ath_print(common, ATH_DBG_FATAL,
2973                           "Unknown power mode %u\n", mode);
2974                 return false;
2975         }
2976         ah->power_mode = mode;
2977
2978         return status;
2979 }
2980 EXPORT_SYMBOL(ath9k_hw_setpower);
2981
2982 /*
2983  * Helper for ASPM support.
2984  *
2985  * Disable PLL when in L0s as well as receiver clock when in L1.
2986  * This power saving option must be enabled through the SerDes.
2987  *
2988  * Programming the SerDes must go through the same 288 bit serial shift
2989  * register as the other analog registers.  Hence the 9 writes.
2990  */
2991 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
2992 {
2993         u8 i;
2994         u32 val;
2995
2996         if (ah->is_pciexpress != true)
2997                 return;
2998
2999         /* Do not touch SerDes registers */
3000         if (ah->config.pcie_powersave_enable == 2)
3001                 return;
3002
3003         /* Nothing to do on restore for 11N */
3004         if (!restore) {
3005                 if (AR_SREV_9280_20_OR_LATER(ah)) {
3006                         /*
3007                          * AR9280 2.0 or later chips use SerDes values from the
3008                          * initvals.h initialized depending on chipset during
3009                          * ath9k_hw_init()
3010                          */
3011                         for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
3012                                 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
3013                                           INI_RA(&ah->iniPcieSerdes, i, 1));
3014                         }
3015                 } else if (AR_SREV_9280(ah) &&
3016                            (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
3017                         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
3018                         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
3019
3020                         /* RX shut off when elecidle is asserted */
3021                         REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
3022                         REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
3023                         REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
3024
3025                         /* Shut off CLKREQ active in L1 */
3026                         if (ah->config.pcie_clock_req)
3027                                 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
3028                         else
3029                                 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
3030
3031                         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3032                         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3033                         REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
3034
3035                         /* Load the new settings */
3036                         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
3037
3038                 } else {
3039                         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
3040                         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
3041
3042                         /* RX shut off when elecidle is asserted */
3043                         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
3044                         REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
3045                         REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
3046
3047                         /*
3048                          * Ignore ah->ah_config.pcie_clock_req setting for
3049                          * pre-AR9280 11n
3050                          */
3051                         REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
3052
3053                         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3054                         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3055                         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
3056
3057                         /* Load the new settings */
3058                         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
3059                 }
3060
3061                 udelay(1000);
3062
3063                 /* set bit 19 to allow forcing of pcie core into L1 state */
3064                 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
3065
3066                 /* Several PCIe massages to ensure proper behaviour */
3067                 if (ah->config.pcie_waen) {
3068                         val = ah->config.pcie_waen;
3069                         if (!power_off)
3070                                 val &= (~AR_WA_D3_L1_DISABLE);
3071                 } else {
3072                         if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
3073                             AR_SREV_9287(ah)) {
3074                                 val = AR9285_WA_DEFAULT;
3075                                 if (!power_off)
3076                                         val &= (~AR_WA_D3_L1_DISABLE);
3077                         } else if (AR_SREV_9280(ah)) {
3078                                 /*
3079                                  * On AR9280 chips bit 22 of 0x4004 needs to be
3080                                  * set otherwise card may disappear.
3081                                  */
3082                                 val = AR9280_WA_DEFAULT;
3083                                 if (!power_off)
3084                                         val &= (~AR_WA_D3_L1_DISABLE);
3085                         } else
3086                                 val = AR_WA_DEFAULT;
3087                 }
3088
3089                 REG_WRITE(ah, AR_WA, val);
3090         }
3091
3092         if (power_off) {
3093                 /*
3094                  * Set PCIe workaround bits
3095                  * bit 14 in WA register (disable L1) should only
3096                  * be set when device enters D3 and be cleared
3097                  * when device comes back to D0.
3098                  */
3099                 if (ah->config.pcie_waen) {
3100                         if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
3101                                 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
3102                 } else {
3103                         if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
3104                               AR_SREV_9287(ah)) &&
3105                              (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
3106                             (AR_SREV_9280(ah) &&
3107                              (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
3108                                 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
3109                         }
3110                 }
3111         }
3112 }
3113 EXPORT_SYMBOL(ath9k_hw_configpcipowersave);
3114
3115 /**********************/
3116 /* Interrupt Handling */
3117 /**********************/
3118
3119 bool ath9k_hw_intrpend(struct ath_hw *ah)
3120 {
3121         u32 host_isr;
3122
3123         if (AR_SREV_9100(ah))
3124                 return true;
3125
3126         host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
3127         if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
3128                 return true;
3129
3130         host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
3131         if ((host_isr & AR_INTR_SYNC_DEFAULT)
3132             && (host_isr != AR_INTR_SPURIOUS))
3133                 return true;
3134
3135         return false;
3136 }
3137 EXPORT_SYMBOL(ath9k_hw_intrpend);
3138
3139 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
3140 {
3141         u32 isr = 0;
3142         u32 mask2 = 0;
3143         struct ath9k_hw_capabilities *pCap = &ah->caps;
3144         u32 sync_cause = 0;
3145         bool fatal_int = false;
3146         struct ath_common *common = ath9k_hw_common(ah);
3147
3148         if (!AR_SREV_9100(ah)) {
3149                 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
3150                         if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
3151                             == AR_RTC_STATUS_ON) {
3152                                 isr = REG_READ(ah, AR_ISR);
3153                         }
3154                 }
3155
3156                 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
3157                         AR_INTR_SYNC_DEFAULT;
3158
3159                 *masked = 0;
3160
3161                 if (!isr && !sync_cause)
3162                         return false;
3163         } else {
3164                 *masked = 0;
3165                 isr = REG_READ(ah, AR_ISR);
3166         }
3167
3168         if (isr) {
3169                 if (isr & AR_ISR_BCNMISC) {
3170                         u32 isr2;
3171                         isr2 = REG_READ(ah, AR_ISR_S2);
3172                         if (isr2 & AR_ISR_S2_TIM)
3173                                 mask2 |= ATH9K_INT_TIM;
3174                         if (isr2 & AR_ISR_S2_DTIM)
3175                                 mask2 |= ATH9K_INT_DTIM;
3176                         if (isr2 & AR_ISR_S2_DTIMSYNC)
3177                                 mask2 |= ATH9K_INT_DTIMSYNC;
3178                         if (isr2 & (AR_ISR_S2_CABEND))
3179                                 mask2 |= ATH9K_INT_CABEND;
3180                         if (isr2 & AR_ISR_S2_GTT)
3181                                 mask2 |= ATH9K_INT_GTT;
3182                         if (isr2 & AR_ISR_S2_CST)
3183                                 mask2 |= ATH9K_INT_CST;
3184                         if (isr2 & AR_ISR_S2_TSFOOR)
3185                                 mask2 |= ATH9K_INT_TSFOOR;
3186                 }
3187
3188                 isr = REG_READ(ah, AR_ISR_RAC);
3189                 if (isr == 0xffffffff) {
3190                         *masked = 0;
3191                         return false;
3192                 }
3193
3194                 *masked = isr & ATH9K_INT_COMMON;
3195
3196                 if (ah->config.intr_mitigation) {
3197                         if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
3198                                 *masked |= ATH9K_INT_RX;
3199                 }
3200
3201                 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
3202                         *masked |= ATH9K_INT_RX;
3203                 if (isr &
3204                     (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
3205                      AR_ISR_TXEOL)) {
3206                         u32 s0_s, s1_s;
3207
3208                         *masked |= ATH9K_INT_TX;
3209
3210                         s0_s = REG_READ(ah, AR_ISR_S0_S);
3211                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
3212                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
3213
3214                         s1_s = REG_READ(ah, AR_ISR_S1_S);
3215                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
3216                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
3217                 }
3218
3219                 if (isr & AR_ISR_RXORN) {
3220                         ath_print(common, ATH_DBG_INTERRUPT,
3221                                   "receive FIFO overrun interrupt\n");
3222                 }
3223
3224                 if (!AR_SREV_9100(ah)) {
3225                         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3226                                 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
3227                                 if (isr5 & AR_ISR_S5_TIM_TIMER)
3228                                         *masked |= ATH9K_INT_TIM_TIMER;
3229                         }
3230                 }
3231
3232                 *masked |= mask2;
3233         }
3234
3235         if (AR_SREV_9100(ah))
3236                 return true;
3237
3238         if (isr & AR_ISR_GENTMR) {
3239                 u32 s5_s;
3240
3241                 s5_s = REG_READ(ah, AR_ISR_S5_S);
3242                 if (isr & AR_ISR_GENTMR) {
3243                         ah->intr_gen_timer_trigger =
3244                                 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
3245
3246                         ah->intr_gen_timer_thresh =
3247                                 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
3248
3249                         if (ah->intr_gen_timer_trigger)
3250                                 *masked |= ATH9K_INT_GENTIMER;
3251
3252                 }
3253         }
3254
3255         if (sync_cause) {
3256                 fatal_int =
3257                         (sync_cause &
3258                          (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
3259                         ? true : false;
3260
3261                 if (fatal_int) {
3262                         if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
3263                                 ath_print(common, ATH_DBG_ANY,
3264                                           "received PCI FATAL interrupt\n");
3265                         }
3266                         if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
3267                                 ath_print(common, ATH_DBG_ANY,
3268                                           "received PCI PERR interrupt\n");
3269                         }
3270                         *masked |= ATH9K_INT_FATAL;
3271                 }
3272                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
3273                         ath_print(common, ATH_DBG_INTERRUPT,
3274                                   "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
3275                         REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
3276                         REG_WRITE(ah, AR_RC, 0);
3277                         *masked |= ATH9K_INT_FATAL;
3278                 }
3279                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
3280                         ath_print(common, ATH_DBG_INTERRUPT,
3281                                   "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
3282                 }
3283
3284                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
3285                 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
3286         }
3287
3288         return true;
3289 }
3290 EXPORT_SYMBOL(ath9k_hw_getisr);
3291
3292 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
3293 {
3294         u32 omask = ah->mask_reg;
3295         u32 mask, mask2;
3296         struct ath9k_hw_capabilities *pCap = &ah->caps;
3297         struct ath_common *common = ath9k_hw_common(ah);
3298
3299         ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
3300
3301         if (omask & ATH9K_INT_GLOBAL) {
3302                 ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
3303                 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
3304                 (void) REG_READ(ah, AR_IER);
3305                 if (!AR_SREV_9100(ah)) {
3306                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
3307                         (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
3308
3309                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
3310                         (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
3311                 }
3312         }
3313
3314         mask = ints & ATH9K_INT_COMMON;
3315         mask2 = 0;
3316
3317         if (ints & ATH9K_INT_TX) {
3318                 if (ah->txok_interrupt_mask)
3319                         mask |= AR_IMR_TXOK;
3320                 if (ah->txdesc_interrupt_mask)
3321                         mask |= AR_IMR_TXDESC;
3322                 if (ah->txerr_interrupt_mask)
3323                         mask |= AR_IMR_TXERR;
3324                 if (ah->txeol_interrupt_mask)
3325                         mask |= AR_IMR_TXEOL;
3326         }
3327         if (ints & ATH9K_INT_RX) {
3328                 mask |= AR_IMR_RXERR;
3329                 if (ah->config.intr_mitigation)
3330                         mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
3331                 else
3332                         mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
3333                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
3334                         mask |= AR_IMR_GENTMR;
3335         }
3336
3337         if (ints & (ATH9K_INT_BMISC)) {
3338                 mask |= AR_IMR_BCNMISC;
3339                 if (ints & ATH9K_INT_TIM)
3340                         mask2 |= AR_IMR_S2_TIM;
3341                 if (ints & ATH9K_INT_DTIM)
3342                         mask2 |= AR_IMR_S2_DTIM;
3343                 if (ints & ATH9K_INT_DTIMSYNC)
3344                         mask2 |= AR_IMR_S2_DTIMSYNC;
3345                 if (ints & ATH9K_INT_CABEND)
3346                         mask2 |= AR_IMR_S2_CABEND;
3347                 if (ints & ATH9K_INT_TSFOOR)
3348                         mask2 |= AR_IMR_S2_TSFOOR;
3349         }
3350
3351         if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
3352                 mask |= AR_IMR_BCNMISC;
3353                 if (ints & ATH9K_INT_GTT)
3354                         mask2 |= AR_IMR_S2_GTT;
3355                 if (ints & ATH9K_INT_CST)
3356                         mask2 |= AR_IMR_S2_CST;
3357         }
3358
3359         ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
3360         REG_WRITE(ah, AR_IMR, mask);
3361         mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3362                                            AR_IMR_S2_DTIM |
3363                                            AR_IMR_S2_DTIMSYNC |
3364                                            AR_IMR_S2_CABEND |
3365                                            AR_IMR_S2_CABTO |
3366                                            AR_IMR_S2_TSFOOR |
3367                                            AR_IMR_S2_GTT | AR_IMR_S2_CST);
3368         REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3369         ah->mask_reg = ints;
3370
3371         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3372                 if (ints & ATH9K_INT_TIM_TIMER)
3373                         REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3374                 else
3375                         REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3376         }
3377
3378         if (ints & ATH9K_INT_GLOBAL) {
3379                 ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
3380                 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3381                 if (!AR_SREV_9100(ah)) {
3382                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3383                                   AR_INTR_MAC_IRQ);
3384                         REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3385
3386
3387                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3388                                   AR_INTR_SYNC_DEFAULT);
3389                         REG_WRITE(ah, AR_INTR_SYNC_MASK,
3390                                   AR_INTR_SYNC_DEFAULT);
3391                 }
3392                 ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3393                           REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3394         }
3395
3396         return omask;
3397 }
3398 EXPORT_SYMBOL(ath9k_hw_set_interrupts);
3399
3400 /*******************/
3401 /* Beacon Handling */
3402 /*******************/
3403
3404 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
3405 {
3406         int flags = 0;
3407
3408         ah->beacon_interval = beacon_period;
3409
3410         switch (ah->opmode) {
3411         case NL80211_IFTYPE_STATION:
3412         case NL80211_IFTYPE_MONITOR:
3413                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3414                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3415                 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3416                 flags |= AR_TBTT_TIMER_EN;
3417                 break;
3418         case NL80211_IFTYPE_ADHOC:
3419         case NL80211_IFTYPE_MESH_POINT:
3420                 REG_SET_BIT(ah, AR_TXCFG,
3421                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3422                 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3423                           TU_TO_USEC(next_beacon +
3424                                      (ah->atim_window ? ah->
3425                                       atim_window : 1)));
3426                 flags |= AR_NDP_TIMER_EN;
3427         case NL80211_IFTYPE_AP:
3428                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3429                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3430                           TU_TO_USEC(next_beacon -
3431                                      ah->config.
3432                                      dma_beacon_response_time));
3433                 REG_WRITE(ah, AR_NEXT_SWBA,
3434                           TU_TO_USEC(next_beacon -
3435                                      ah->config.
3436                                      sw_beacon_response_time));
3437                 flags |=
3438                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3439                 break;
3440         default:
3441                 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
3442                           "%s: unsupported opmode: %d\n",
3443                           __func__, ah->opmode);
3444                 return;
3445                 break;
3446         }
3447
3448         REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3449         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3450         REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3451         REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3452
3453         beacon_period &= ~ATH9K_BEACON_ENA;
3454         if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3455                 ath9k_hw_reset_tsf(ah);
3456         }
3457
3458         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3459 }
3460 EXPORT_SYMBOL(ath9k_hw_beaconinit);
3461
3462 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3463                                     const struct ath9k_beacon_state *bs)
3464 {
3465         u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3466         struct ath9k_hw_capabilities *pCap = &ah->caps;
3467         struct ath_common *common = ath9k_hw_common(ah);
3468
3469         REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3470
3471         REG_WRITE(ah, AR_BEACON_PERIOD,
3472                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3473         REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3474                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3475
3476         REG_RMW_FIELD(ah, AR_RSSI_THR,
3477                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3478
3479         beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3480
3481         if (bs->bs_sleepduration > beaconintval)
3482                 beaconintval = bs->bs_sleepduration;
3483
3484         dtimperiod = bs->bs_dtimperiod;
3485         if (bs->bs_sleepduration > dtimperiod)
3486                 dtimperiod = bs->bs_sleepduration;
3487
3488         if (beaconintval == dtimperiod)
3489                 nextTbtt = bs->bs_nextdtim;
3490         else
3491                 nextTbtt = bs->bs_nexttbtt;
3492
3493         ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3494         ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3495         ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3496         ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3497
3498         REG_WRITE(ah, AR_NEXT_DTIM,
3499                   TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3500         REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3501
3502         REG_WRITE(ah, AR_SLEEP1,
3503                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3504                   | AR_SLEEP1_ASSUME_DTIM);
3505
3506         if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3507                 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3508         else
3509                 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3510
3511         REG_WRITE(ah, AR_SLEEP2,
3512                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3513
3514         REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3515         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3516
3517         REG_SET_BIT(ah, AR_TIMER_MODE,
3518                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3519                     AR_DTIM_TIMER_EN);
3520
3521         /* TSF Out of Range Threshold */
3522         REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3523 }
3524 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
3525
3526 /*******************/
3527 /* HW Capabilities */
3528 /*******************/
3529
3530 void ath9k_hw_fill_cap_info(struct ath_hw *ah)
3531 {
3532         struct ath9k_hw_capabilities *pCap = &ah->caps;
3533         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3534         struct ath_common *common = ath9k_hw_common(ah);
3535         struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
3536
3537         u16 capField = 0, eeval;
3538
3539         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3540         regulatory->current_rd = eeval;
3541
3542         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3543         if (AR_SREV_9285_10_OR_LATER(ah))
3544                 eeval |= AR9285_RDEXT_DEFAULT;
3545         regulatory->current_rd_ext = eeval;
3546
3547         capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3548
3549         if (ah->opmode != NL80211_IFTYPE_AP &&
3550             ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3551                 if (regulatory->current_rd == 0x64 ||
3552                     regulatory->current_rd == 0x65)
3553                         regulatory->current_rd += 5;
3554                 else if (regulatory->current_rd == 0x41)
3555                         regulatory->current_rd = 0x43;
3556                 ath_print(common, ATH_DBG_REGULATORY,
3557                           "regdomain mapped to 0x%x\n", regulatory->current_rd);
3558         }
3559
3560         eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3561         bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3562
3563         if (eeval & AR5416_OPFLAGS_11A) {
3564                 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3565                 if (ah->config.ht_enable) {
3566                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3567                                 set_bit(ATH9K_MODE_11NA_HT20,
3568                                         pCap->wireless_modes);
3569                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3570                                 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3571                                         pCap->wireless_modes);
3572                                 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3573                                         pCap->wireless_modes);
3574                         }
3575                 }
3576         }
3577
3578         if (eeval & AR5416_OPFLAGS_11G) {
3579                 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3580                 if (ah->config.ht_enable) {
3581                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3582                                 set_bit(ATH9K_MODE_11NG_HT20,
3583                                         pCap->wireless_modes);
3584                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3585                                 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3586                                         pCap->wireless_modes);
3587                                 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3588                                         pCap->wireless_modes);
3589                         }
3590                 }
3591         }
3592
3593         pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3594         /*
3595          * For AR9271 we will temporarilly uses the rx chainmax as read from
3596          * the EEPROM.
3597          */
3598         if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3599             !(eeval & AR5416_OPFLAGS_11A) &&
3600             !(AR_SREV_9271(ah)))
3601                 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
3602                 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3603         else
3604                 /* Use rx_chainmask from EEPROM. */
3605                 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3606
3607         if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3608                 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3609
3610         pCap->low_2ghz_chan = 2312;
3611         pCap->high_2ghz_chan = 2732;
3612
3613         pCap->low_5ghz_chan = 4920;
3614         pCap->high_5ghz_chan = 6100;
3615
3616         pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3617         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3618         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3619
3620         pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3621         pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3622         pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3623
3624         if (ah->config.ht_enable)
3625                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3626         else
3627                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3628
3629         pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3630         pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3631         pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3632         pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3633
3634         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3635                 pCap->total_queues =
3636                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3637         else
3638                 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3639
3640         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3641                 pCap->keycache_size =
3642                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3643         else
3644                 pCap->keycache_size = AR_KEYTABLE_SIZE;
3645
3646         pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3647         pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3648
3649         if (AR_SREV_9285_10_OR_LATER(ah))
3650                 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3651         else if (AR_SREV_9280_10_OR_LATER(ah))
3652                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3653         else
3654                 pCap->num_gpio_pins = AR_NUM_GPIO;
3655
3656         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3657                 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3658                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3659         } else {
3660                 pCap->rts_aggr_limit = (8 * 1024);
3661         }
3662
3663         pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3664
3665 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3666         ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3667         if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3668                 ah->rfkill_gpio =
3669                         MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3670                 ah->rfkill_polarity =
3671                         MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3672
3673                 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3674         }
3675 #endif
3676
3677         pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3678
3679         if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3680                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3681         else
3682                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3683
3684         if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3685                 pCap->reg_cap =
3686                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3687                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3688                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
3689                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3690         } else {
3691                 pCap->reg_cap =
3692                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3693                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3694         }
3695
3696         /* Advertise midband for AR5416 with FCC midband set in eeprom */
3697         if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
3698             AR_SREV_5416(ah))
3699                 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3700
3701         pCap->num_antcfg_5ghz =
3702                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3703         pCap->num_antcfg_2ghz =
3704                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3705
3706         if (AR_SREV_9280_10_OR_LATER(ah) &&
3707             ath9k_hw_btcoex_supported(ah)) {
3708                 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
3709                 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
3710
3711                 if (AR_SREV_9285(ah)) {
3712                         btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
3713                         btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
3714                 } else {
3715                         btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
3716                 }
3717         } else {
3718                 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
3719         }
3720 }
3721
3722 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3723                             u32 capability, u32 *result)
3724 {
3725         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3726         switch (type) {
3727         case ATH9K_CAP_CIPHER:
3728                 switch (capability) {
3729                 case ATH9K_CIPHER_AES_CCM:
3730                 case ATH9K_CIPHER_AES_OCB:
3731                 case ATH9K_CIPHER_TKIP:
3732                 case ATH9K_CIPHER_WEP:
3733                 case ATH9K_CIPHER_MIC:
3734                 case ATH9K_CIPHER_CLR:
3735                         return true;
3736                 default:
3737                         return false;
3738                 }
3739         case ATH9K_CAP_TKIP_MIC:
3740                 switch (capability) {
3741                 case 0:
3742                         return true;
3743                 case 1:
3744                         return (ah->sta_id1_defaults &
3745                                 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3746                         false;
3747                 }
3748         case ATH9K_CAP_TKIP_SPLIT:
3749                 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3750                         false : true;
3751         case ATH9K_CAP_DIVERSITY:
3752                 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3753                         AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3754                         true : false;
3755         case ATH9K_CAP_MCAST_KEYSRCH:
3756                 switch (capability) {
3757                 case 0:
3758                         return true;
3759                 case 1:
3760                         if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3761                                 return false;
3762                         } else {
3763                                 return (ah->sta_id1_defaults &
3764                                         AR_STA_ID1_MCAST_KSRCH) ? true :
3765                                         false;
3766                         }
3767                 }
3768                 return false;
3769         case ATH9K_CAP_TXPOW:
3770                 switch (capability) {
3771                 case 0:
3772                         return 0;
3773                 case 1:
3774                         *result = regulatory->power_limit;
3775                         return 0;
3776                 case 2:
3777                         *result = regulatory->max_power_level;
3778                         return 0;
3779                 case 3:
3780                         *result = regulatory->tp_scale;
3781                         return 0;
3782                 }
3783                 return false;
3784         case ATH9K_CAP_DS:
3785                 return (AR_SREV_9280_20_OR_LATER(ah) &&
3786                         (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3787                         ? false : true;
3788         default:
3789                 return false;
3790         }
3791 }
3792 EXPORT_SYMBOL(ath9k_hw_getcapability);
3793
3794 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3795                             u32 capability, u32 setting, int *status)
3796 {
3797         u32 v;
3798
3799         switch (type) {
3800         case ATH9K_CAP_TKIP_MIC:
3801                 if (setting)
3802                         ah->sta_id1_defaults |=
3803                                 AR_STA_ID1_CRPT_MIC_ENABLE;
3804                 else
3805                         ah->sta_id1_defaults &=
3806                                 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3807                 return true;
3808         case ATH9K_CAP_DIVERSITY:
3809                 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3810                 if (setting)
3811                         v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3812                 else
3813                         v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3814                 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3815                 return true;
3816         case ATH9K_CAP_MCAST_KEYSRCH:
3817                 if (setting)
3818                         ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3819                 else
3820                         ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3821                 return true;
3822         default:
3823                 return false;
3824         }
3825 }
3826 EXPORT_SYMBOL(ath9k_hw_setcapability);
3827
3828 /****************************/
3829 /* GPIO / RFKILL / Antennae */
3830 /****************************/
3831
3832 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3833                                          u32 gpio, u32 type)
3834 {
3835         int addr;
3836         u32 gpio_shift, tmp;
3837
3838         if (gpio > 11)
3839                 addr = AR_GPIO_OUTPUT_MUX3;
3840         else if (gpio > 5)
3841                 addr = AR_GPIO_OUTPUT_MUX2;
3842         else
3843                 addr = AR_GPIO_OUTPUT_MUX1;
3844
3845         gpio_shift = (gpio % 6) * 5;
3846
3847         if (AR_SREV_9280_20_OR_LATER(ah)
3848             || (addr != AR_GPIO_OUTPUT_MUX1)) {
3849                 REG_RMW(ah, addr, (type << gpio_shift),
3850                         (0x1f << gpio_shift));
3851         } else {
3852                 tmp = REG_READ(ah, addr);
3853                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3854                 tmp &= ~(0x1f << gpio_shift);
3855                 tmp |= (type << gpio_shift);
3856                 REG_WRITE(ah, addr, tmp);
3857         }
3858 }
3859
3860 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3861 {
3862         u32 gpio_shift;
3863
3864         BUG_ON(gpio >= ah->caps.num_gpio_pins);
3865
3866         gpio_shift = gpio << 1;
3867
3868         REG_RMW(ah,
3869                 AR_GPIO_OE_OUT,
3870                 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3871                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3872 }
3873 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
3874
3875 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3876 {
3877 #define MS_REG_READ(x, y) \
3878         (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3879
3880         if (gpio >= ah->caps.num_gpio_pins)
3881                 return 0xffffffff;
3882
3883         if (AR_SREV_9287_10_OR_LATER(ah))
3884                 return MS_REG_READ(AR9287, gpio) != 0;
3885         else if (AR_SREV_9285_10_OR_LATER(ah))
3886                 return MS_REG_READ(AR9285, gpio) != 0;
3887         else if (AR_SREV_9280_10_OR_LATER(ah))
3888                 return MS_REG_READ(AR928X, gpio) != 0;
3889         else
3890                 return MS_REG_READ(AR, gpio) != 0;
3891 }
3892 EXPORT_SYMBOL(ath9k_hw_gpio_get);
3893
3894 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3895                          u32 ah_signal_type)
3896 {
3897         u32 gpio_shift;
3898
3899         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3900
3901         gpio_shift = 2 * gpio;
3902
3903         REG_RMW(ah,
3904                 AR_GPIO_OE_OUT,
3905                 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3906                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3907 }
3908 EXPORT_SYMBOL(ath9k_hw_cfg_output);
3909
3910 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3911 {
3912         REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3913                 AR_GPIO_BIT(gpio));
3914 }
3915 EXPORT_SYMBOL(ath9k_hw_set_gpio);
3916
3917 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3918 {
3919         return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3920 }
3921 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
3922
3923 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3924 {
3925         REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3926 }
3927 EXPORT_SYMBOL(ath9k_hw_setantenna);
3928
3929 bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
3930                                enum ath9k_ant_setting settings,
3931                                struct ath9k_channel *chan,
3932                                u8 *tx_chainmask,
3933                                u8 *rx_chainmask,
3934                                u8 *antenna_cfgd)
3935 {
3936         static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3937
3938         if (AR_SREV_9280(ah)) {
3939                 if (!tx_chainmask_cfg) {
3940
3941                         tx_chainmask_cfg = *tx_chainmask;
3942                         rx_chainmask_cfg = *rx_chainmask;
3943                 }
3944
3945                 switch (settings) {
3946                 case ATH9K_ANT_FIXED_A:
3947                         *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3948                         *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3949                         *antenna_cfgd = true;
3950                         break;
3951                 case ATH9K_ANT_FIXED_B:
3952                         if (ah->caps.tx_chainmask >
3953                             ATH9K_ANTENNA1_CHAINMASK) {
3954                                 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3955                         }
3956                         *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3957                         *antenna_cfgd = true;
3958                         break;
3959                 case ATH9K_ANT_VARIABLE:
3960                         *tx_chainmask = tx_chainmask_cfg;
3961                         *rx_chainmask = rx_chainmask_cfg;
3962                         *antenna_cfgd = true;
3963                         break;
3964                 default:
3965                         break;
3966                 }
3967         } else {
3968                 ah->config.diversity_control = settings;
3969         }
3970
3971         return true;
3972 }
3973
3974 /*********************/
3975 /* General Operation */
3976 /*********************/
3977
3978 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3979 {
3980         u32 bits = REG_READ(ah, AR_RX_FILTER);
3981         u32 phybits = REG_READ(ah, AR_PHY_ERR);
3982
3983         if (phybits & AR_PHY_ERR_RADAR)
3984                 bits |= ATH9K_RX_FILTER_PHYRADAR;
3985         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3986                 bits |= ATH9K_RX_FILTER_PHYERR;
3987
3988         return bits;
3989 }
3990 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
3991
3992 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3993 {
3994         u32 phybits;
3995
3996         REG_WRITE(ah, AR_RX_FILTER, bits);
3997
3998         phybits = 0;
3999         if (bits & ATH9K_RX_FILTER_PHYRADAR)
4000                 phybits |= AR_PHY_ERR_RADAR;
4001         if (bits & ATH9K_RX_FILTER_PHYERR)
4002                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
4003         REG_WRITE(ah, AR_PHY_ERR, phybits);
4004
4005         if (phybits)
4006                 REG_WRITE(ah, AR_RXCFG,
4007                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
4008         else
4009                 REG_WRITE(ah, AR_RXCFG,
4010                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
4011 }
4012 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
4013
4014 bool ath9k_hw_phy_disable(struct ath_hw *ah)
4015 {
4016         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
4017                 return false;
4018
4019         ath9k_hw_init_pll(ah, NULL);
4020         return true;
4021 }
4022 EXPORT_SYMBOL(ath9k_hw_phy_disable);
4023
4024 bool ath9k_hw_disable(struct ath_hw *ah)
4025 {
4026         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
4027                 return false;
4028
4029         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
4030                 return false;
4031
4032         ath9k_hw_init_pll(ah, NULL);
4033         return true;
4034 }
4035 EXPORT_SYMBOL(ath9k_hw_disable);
4036
4037 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
4038 {
4039         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
4040         struct ath9k_channel *chan = ah->curchan;
4041         struct ieee80211_channel *channel = chan->chan;
4042
4043         regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
4044
4045         ah->eep_ops->set_txpower(ah, chan,
4046                                  ath9k_regd_get_ctl(regulatory, chan),
4047                                  channel->max_antenna_gain * 2,
4048                                  channel->max_power * 2,
4049                                  min((u32) MAX_RATE_POWER,
4050                                  (u32) regulatory->power_limit));
4051 }
4052 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
4053
4054 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
4055 {
4056         memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
4057 }
4058 EXPORT_SYMBOL(ath9k_hw_setmac);
4059
4060 void ath9k_hw_setopmode(struct ath_hw *ah)
4061 {
4062         ath9k_hw_set_operating_mode(ah, ah->opmode);
4063 }
4064 EXPORT_SYMBOL(ath9k_hw_setopmode);
4065
4066 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
4067 {
4068         REG_WRITE(ah, AR_MCAST_FIL0, filter0);
4069         REG_WRITE(ah, AR_MCAST_FIL1, filter1);
4070 }
4071 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
4072
4073 void ath9k_hw_write_associd(struct ath_hw *ah)
4074 {
4075         struct ath_common *common = ath9k_hw_common(ah);
4076
4077         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
4078         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
4079                   ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
4080 }
4081 EXPORT_SYMBOL(ath9k_hw_write_associd);
4082
4083 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
4084 {
4085         u64 tsf;
4086
4087         tsf = REG_READ(ah, AR_TSF_U32);
4088         tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
4089
4090         return tsf;
4091 }
4092 EXPORT_SYMBOL(ath9k_hw_gettsf64);
4093
4094 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
4095 {
4096         REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
4097         REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
4098 }
4099 EXPORT_SYMBOL(ath9k_hw_settsf64);
4100
4101 void ath9k_hw_reset_tsf(struct ath_hw *ah)
4102 {
4103         if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
4104                            AH_TSF_WRITE_TIMEOUT))
4105                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
4106                           "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
4107
4108         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
4109 }
4110 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
4111
4112 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
4113 {
4114         if (setting)
4115                 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
4116         else
4117                 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
4118 }
4119 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
4120
4121 bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
4122 {
4123         if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
4124                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
4125                           "bad slot time %u\n", us);
4126                 ah->slottime = (u32) -1;
4127                 return false;
4128         } else {
4129                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
4130                 ah->slottime = us;
4131                 return true;
4132         }
4133 }
4134 EXPORT_SYMBOL(ath9k_hw_setslottime);
4135
4136 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
4137 {
4138         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
4139         u32 macmode;
4140
4141         if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
4142                 macmode = AR_2040_JOINED_RX_CLEAR;
4143         else
4144                 macmode = 0;
4145
4146         REG_WRITE(ah, AR_2040_MODE, macmode);
4147 }
4148
4149 /* HW Generic timers configuration */
4150
4151 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
4152 {
4153         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4154         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4155         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4156         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4157         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4158         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4159         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4160         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
4161         {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
4162         {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
4163                                 AR_NDP2_TIMER_MODE, 0x0002},
4164         {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
4165                                 AR_NDP2_TIMER_MODE, 0x0004},
4166         {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
4167                                 AR_NDP2_TIMER_MODE, 0x0008},
4168         {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
4169                                 AR_NDP2_TIMER_MODE, 0x0010},
4170         {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
4171                                 AR_NDP2_TIMER_MODE, 0x0020},
4172         {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
4173                                 AR_NDP2_TIMER_MODE, 0x0040},
4174         {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
4175                                 AR_NDP2_TIMER_MODE, 0x0080}
4176 };
4177
4178 /* HW generic timer primitives */
4179
4180 /* compute and clear index of rightmost 1 */
4181 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
4182 {
4183         u32 b;
4184
4185         b = *mask;
4186         b &= (0-b);
4187         *mask &= ~b;
4188         b *= debruijn32;
4189         b >>= 27;
4190
4191         return timer_table->gen_timer_index[b];
4192 }
4193
4194 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
4195 {
4196         return REG_READ(ah, AR_TSF_L32);
4197 }
4198 EXPORT_SYMBOL(ath9k_hw_gettsf32);
4199
4200 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
4201                                           void (*trigger)(void *),
4202                                           void (*overflow)(void *),
4203                                           void *arg,
4204                                           u8 timer_index)
4205 {
4206         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4207         struct ath_gen_timer *timer;
4208
4209         timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
4210
4211         if (timer == NULL) {
4212                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
4213                           "Failed to allocate memory"
4214                           "for hw timer[%d]\n", timer_index);
4215                 return NULL;
4216         }
4217
4218         /* allocate a hardware generic timer slot */
4219         timer_table->timers[timer_index] = timer;
4220         timer->index = timer_index;
4221         timer->trigger = trigger;
4222         timer->overflow = overflow;
4223         timer->arg = arg;
4224
4225         return timer;
4226 }
4227 EXPORT_SYMBOL(ath_gen_timer_alloc);
4228
4229 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
4230                               struct ath_gen_timer *timer,
4231                               u32 timer_next,
4232                               u32 timer_period)
4233 {
4234         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4235         u32 tsf;
4236
4237         BUG_ON(!timer_period);
4238
4239         set_bit(timer->index, &timer_table->timer_mask.timer_bits);
4240
4241         tsf = ath9k_hw_gettsf32(ah);
4242
4243         ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
4244                   "curent tsf %x period %x"
4245                   "timer_next %x\n", tsf, timer_period, timer_next);
4246
4247         /*
4248          * Pull timer_next forward if the current TSF already passed it
4249          * because of software latency
4250          */
4251         if (timer_next < tsf)
4252                 timer_next = tsf + timer_period;
4253
4254         /*
4255          * Program generic timer registers
4256          */
4257         REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
4258                  timer_next);
4259         REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
4260                   timer_period);
4261         REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
4262                     gen_tmr_configuration[timer->index].mode_mask);
4263
4264         /* Enable both trigger and thresh interrupt masks */
4265         REG_SET_BIT(ah, AR_IMR_S5,
4266                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
4267                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
4268 }
4269 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
4270
4271 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
4272 {
4273         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4274
4275         if ((timer->index < AR_FIRST_NDP_TIMER) ||
4276                 (timer->index >= ATH_MAX_GEN_TIMER)) {
4277                 return;
4278         }
4279
4280         /* Clear generic timer enable bits. */
4281         REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
4282                         gen_tmr_configuration[timer->index].mode_mask);
4283
4284         /* Disable both trigger and thresh interrupt masks */
4285         REG_CLR_BIT(ah, AR_IMR_S5,
4286                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
4287                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
4288
4289         clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
4290 }
4291 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
4292
4293 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
4294 {
4295         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4296
4297         /* free the hardware generic timer slot */
4298         timer_table->timers[timer->index] = NULL;
4299         kfree(timer);
4300 }
4301 EXPORT_SYMBOL(ath_gen_timer_free);
4302
4303 /*
4304  * Generic Timer Interrupts handling
4305  */
4306 void ath_gen_timer_isr(struct ath_hw *ah)
4307 {
4308         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
4309         struct ath_gen_timer *timer;
4310         struct ath_common *common = ath9k_hw_common(ah);
4311         u32 trigger_mask, thresh_mask, index;
4312
4313         /* get hardware generic timer interrupt status */
4314         trigger_mask = ah->intr_gen_timer_trigger;
4315         thresh_mask = ah->intr_gen_timer_thresh;
4316         trigger_mask &= timer_table->timer_mask.val;
4317         thresh_mask &= timer_table->timer_mask.val;
4318
4319         trigger_mask &= ~thresh_mask;
4320
4321         while (thresh_mask) {
4322                 index = rightmost_index(timer_table, &thresh_mask);
4323                 timer = timer_table->timers[index];
4324                 BUG_ON(!timer);
4325                 ath_print(common, ATH_DBG_HWTIMER,
4326                           "TSF overflow for Gen timer %d\n", index);
4327                 timer->overflow(timer->arg);
4328         }
4329
4330         while (trigger_mask) {
4331                 index = rightmost_index(timer_table, &trigger_mask);
4332                 timer = timer_table->timers[index];
4333                 BUG_ON(!timer);
4334                 ath_print(common, ATH_DBG_HWTIMER,
4335                           "Gen timer[%d] trigger\n", index);
4336                 timer->trigger(timer->arg);
4337         }
4338 }
4339 EXPORT_SYMBOL(ath_gen_timer_isr);