SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/ath/ath9k/hw.c

   1 /*
   2  * Copyright (c) 2008-2009 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <asm/unaligned.h>
  19
  20 #include "hw.h"
  21 #include "rc.h"
  22 #include "initvals.h"
  23
  24 #define ATH9K_CLOCK_RATE_CCK            22
  25 #define ATH9K_CLOCK_RATE_5GHZ_OFDM      40
  26 #define ATH9K_CLOCK_RATE_2GHZ_OFDM      44
  27
  28 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
  29 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan);
  30 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
  31                               struct ar5416_eeprom_def *pEepData,
  32                               u32 reg, u32 value);
  33
  34 MODULE_AUTHOR("Atheros Communications");
  35 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  36 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  37 MODULE_LICENSE("Dual BSD/GPL");
  38
  39 static int __init ath9k_init(void)
  40 {
  41         return 0;
  42 }
  43 module_init(ath9k_init);
  44
  45 static void __exit ath9k_exit(void)
  46 {
  47         return;
  48 }
  49 module_exit(ath9k_exit);
  50
  51 /********************/
  52 /* Helper Functions */
  53 /********************/
  54
  55 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
  56 {
  57         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
  58
  59         if (!ah->curchan) /* should really check for CCK instead */
  60                 return usecs *ATH9K_CLOCK_RATE_CCK;
  61         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  62                 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
  63         return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
  64 }
  65
  66 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
  67 {
  68         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
  69
  70         if (conf_is_ht40(conf))
  71                 return ath9k_hw_mac_clks(ah, usecs) * 2;
  72         else
  73                 return ath9k_hw_mac_clks(ah, usecs);
  74 }
  75
  76 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
  77 {
  78         int i;
  79
  80         BUG_ON(timeout < AH_TIME_QUANTUM);
  81
  82         for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
  83                 if ((REG_READ(ah, reg) & mask) == val)
  84                         return true;
  85
  86                 udelay(AH_TIME_QUANTUM);
  87         }
  88
  89         ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
  90                   "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
  91                   timeout, reg, REG_READ(ah, reg), mask, val);
  92
  93         return false;
  94 }
  95 EXPORT_SYMBOL(ath9k_hw_wait);
  96
  97 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
  98 {
  99         u32 retval;
 100         int i;
 101
 102         for (i = 0, retval = 0; i < n; i++) {
 103                 retval = (retval << 1) | (val & 1);
 104                 val >>= 1;
 105         }
 106         return retval;
 107 }
 108
 109 bool ath9k_get_channel_edges(struct ath_hw *ah,
 110                              u16 flags, u16 *low,
 111                              u16 *high)
 112 {
 113         struct ath9k_hw_capabilities *pCap = &ah->caps;
 114
 115         if (flags & CHANNEL_5GHZ) {
 116                 *low = pCap->low_5ghz_chan;
 117                 *high = pCap->high_5ghz_chan;
 118                 return true;
 119         }
 120         if ((flags & CHANNEL_2GHZ)) {
 121                 *low = pCap->low_2ghz_chan;
 122                 *high = pCap->high_2ghz_chan;
 123                 return true;
 124         }
 125         return false;
 126 }
 127
 128 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
 129                            u8 phy, int kbps,
 130                            u32 frameLen, u16 rateix,
 131                            bool shortPreamble)
 132 {
 133         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
 134
 135         if (kbps == 0)
 136                 return 0;
 137
 138         switch (phy) {
 139         case WLAN_RC_PHY_CCK:
 140                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
 141                 if (shortPreamble)
 142                         phyTime >>= 1;
 143                 numBits = frameLen << 3;
 144                 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
 145                 break;
 146         case WLAN_RC_PHY_OFDM:
 147                 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
 148                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
 149                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 150                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 151                         txTime = OFDM_SIFS_TIME_QUARTER
 152                                 + OFDM_PREAMBLE_TIME_QUARTER
 153                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
 154                 } else if (ah->curchan &&
 155                            IS_CHAN_HALF_RATE(ah->curchan)) {
 156                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
 157                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 158                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 159                         txTime = OFDM_SIFS_TIME_HALF +
 160                                 OFDM_PREAMBLE_TIME_HALF
 161                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
 162                 } else {
 163                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
 164                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 165                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 166                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
 167                                 + (numSymbols * OFDM_SYMBOL_TIME);
 168                 }
 169                 break;
 170         default:
 171                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 172                           "Unknown phy %u (rate ix %u)\n", phy, rateix);
 173                 txTime = 0;
 174                 break;
 175         }
 176
 177         return txTime;
 178 }
 179 EXPORT_SYMBOL(ath9k_hw_computetxtime);
 180
 181 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
 182                                   struct ath9k_channel *chan,
 183                                   struct chan_centers *centers)
 184 {
 185         int8_t extoff;
 186
 187         if (!IS_CHAN_HT40(chan)) {
 188                 centers->ctl_center = centers->ext_center =
 189                         centers->synth_center = chan->channel;
 190                 return;
 191         }
 192
 193         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 194             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
 195                 centers->synth_center =
 196                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
 197                 extoff = 1;
 198         } else {
 199                 centers->synth_center =
 200                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
 201                 extoff = -1;
 202         }
 203
 204         centers->ctl_center =
 205                 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
 206         /* 25 MHz spacing is supported by hw but not on upper layers */
 207         centers->ext_center =
 208                 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
 209 }
 210
 211 /******************/
 212 /* Chip Revisions */
 213 /******************/
 214
 215 static void ath9k_hw_read_revisions(struct ath_hw *ah)
 216 {
 217         u32 val;
 218
 219         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
 220
 221         if (val == 0xFF) {
 222                 val = REG_READ(ah, AR_SREV);
 223                 ah->hw_version.macVersion =
 224                         (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
 225                 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
 226                 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
 227         } else {
 228                 if (!AR_SREV_9100(ah))
 229                         ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
 230
 231                 ah->hw_version.macRev = val & AR_SREV_REVISION;
 232
 233                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
 234                         ah->is_pciexpress = true;
 235         }
 236 }
 237
 238 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
 239 {
 240         u32 val;
 241         int i;
 242
 243         REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
 244
 245         for (i = 0; i < 8; i++)
 246                 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
 247         val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
 248         val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
 249
 250         return ath9k_hw_reverse_bits(val, 8);
 251 }
 252
 253 /************************************/
 254 /* HW Attach, Detach, Init Routines */
 255 /************************************/
 256
 257 static void ath9k_hw_disablepcie(struct ath_hw *ah)
 258 {
 259         if (AR_SREV_9100(ah))
 260                 return;
 261
 262         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 263         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 264         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
 265         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
 266         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
 267         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
 268         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 269         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 270         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
 271
 272         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 273 }
 274
 275 static bool ath9k_hw_chip_test(struct ath_hw *ah)
 276 {
 277         struct ath_common *common = ath9k_hw_common(ah);
 278         u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
 279         u32 regHold[2];
 280         u32 patternData[4] = { 0x55555555,
 281                                0xaaaaaaaa,
 282                                0x66666666,
 283                                0x99999999 };
 284         int i, j;
 285
 286         for (i = 0; i < 2; i++) {
 287                 u32 addr = regAddr[i];
 288                 u32 wrData, rdData;
 289
 290                 regHold[i] = REG_READ(ah, addr);
 291                 for (j = 0; j < 0x100; j++) {
 292                         wrData = (j << 16) | j;
 293                         REG_WRITE(ah, addr, wrData);
 294                         rdData = REG_READ(ah, addr);
 295                         if (rdData != wrData) {
 296                                 ath_print(common, ATH_DBG_FATAL,
 297                                           "address test failed "
 298                                           "addr: 0x%08x - wr:0x%08x != "
 299                                           "rd:0x%08x\n",
 300                                           addr, wrData, rdData);
 301                                 return false;
 302                         }
 303                 }
 304                 for (j = 0; j < 4; j++) {
 305                         wrData = patternData[j];
 306                         REG_WRITE(ah, addr, wrData);
 307                         rdData = REG_READ(ah, addr);
 308                         if (wrData != rdData) {
 309                                 ath_print(common, ATH_DBG_FATAL,
 310                                           "address test failed "
 311                                           "addr: 0x%08x - wr:0x%08x != "
 312                                           "rd:0x%08x\n",
 313                                           addr, wrData, rdData);
 314                                 return false;
 315                         }
 316                 }
 317                 REG_WRITE(ah, regAddr[i], regHold[i]);
 318         }
 319         udelay(100);
 320
 321         return true;
 322 }
 323
 324 static void ath9k_hw_init_config(struct ath_hw *ah)
 325 {
 326         int i;
 327
 328         ah->config.dma_beacon_response_time = 2;
 329         ah->config.sw_beacon_response_time = 10;
 330         ah->config.additional_swba_backoff = 0;
 331         ah->config.ack_6mb = 0x0;
 332         ah->config.cwm_ignore_extcca = 0;
 333         ah->config.pcie_powersave_enable = 0;
 334         ah->config.pcie_clock_req = 0;
 335         ah->config.pcie_waen = 0;
 336         ah->config.analog_shiftreg = 1;
 337         ah->config.ofdm_trig_low = 200;
 338         ah->config.ofdm_trig_high = 500;
 339         ah->config.cck_trig_high = 200;
 340         ah->config.cck_trig_low = 100;
 341         ah->config.enable_ani = 1;
 342
 343         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 344                 ah->config.spurchans[i][0] = AR_NO_SPUR;
 345                 ah->config.spurchans[i][1] = AR_NO_SPUR;
 346         }
 347
 348         if (ah->hw_version.devid != AR2427_DEVID_PCIE)
 349                 ah->config.ht_enable = 1;
 350         else
 351                 ah->config.ht_enable = 0;
 352
 353         ah->config.rx_intr_mitigation = true;
 354
 355         /*
 356          * We need this for PCI devices only (Cardbus, PCI, miniPCI)
 357          * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
 358          * This means we use it for all AR5416 devices, and the few
 359          * minor PCI AR9280 devices out there.
 360          *
 361          * Serialization is required because these devices do not handle
 362          * well the case of two concurrent reads/writes due to the latency
 363          * involved. During one read/write another read/write can be issued
 364          * on another CPU while the previous read/write may still be working
 365          * on our hardware, if we hit this case the hardware poops in a loop.
 366          * We prevent this by serializing reads and writes.
 367          *
 368          * This issue is not present on PCI-Express devices or pre-AR5416
 369          * devices (legacy, 802.11abg).
 370          */
 371         if (num_possible_cpus() > 1)
 372                 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
 373 }
 374 EXPORT_SYMBOL(ath9k_hw_init);
 375
 376 static void ath9k_hw_init_defaults(struct ath_hw *ah)
 377 {
 378         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
 379
 380         regulatory->country_code = CTRY_DEFAULT;
 381         regulatory->power_limit = MAX_RATE_POWER;
 382         regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
 383
 384         ah->hw_version.magic = AR5416_MAGIC;
 385         ah->hw_version.subvendorid = 0;
 386
 387         ah->ah_flags = 0;
 388         if (ah->hw_version.devid == AR5416_AR9100_DEVID)
 389                 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
 390         if (!AR_SREV_9100(ah))
 391                 ah->ah_flags = AH_USE_EEPROM;
 392
 393         ah->atim_window = 0;
 394         ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
 395         ah->beacon_interval = 100;
 396         ah->enable_32kHz_clock = DONT_USE_32KHZ;
 397         ah->slottime = (u32) -1;
 398         ah->globaltxtimeout = (u32) -1;
 399         ah->power_mode = ATH9K_PM_UNDEFINED;
 400 }
 401
 402 static int ath9k_hw_rf_claim(struct ath_hw *ah)
 403 {
 404         u32 val;
 405
 406         REG_WRITE(ah, AR_PHY(0), 0x00000007);
 407
 408         val = ath9k_hw_get_radiorev(ah);
 409         switch (val & AR_RADIO_SREV_MAJOR) {
 410         case 0:
 411                 val = AR_RAD5133_SREV_MAJOR;
 412                 break;
 413         case AR_RAD5133_SREV_MAJOR:
 414         case AR_RAD5122_SREV_MAJOR:
 415         case AR_RAD2133_SREV_MAJOR:
 416         case AR_RAD2122_SREV_MAJOR:
 417                 break;
 418         default:
 419                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 420                           "Radio Chip Rev 0x%02X not supported\n",
 421                           val & AR_RADIO_SREV_MAJOR);
 422                 return -EOPNOTSUPP;
 423         }
 424
 425         ah->hw_version.analog5GhzRev = val;
 426
 427         return 0;
 428 }
 429
 430 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
 431 {
 432         struct ath_common *common = ath9k_hw_common(ah);
 433         u32 sum;
 434         int i;
 435         u16 eeval;
 436
 437         sum = 0;
 438         for (i = 0; i < 3; i++) {
 439                 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
 440                 sum += eeval;
 441                 common->macaddr[2 * i] = eeval >> 8;
 442                 common->macaddr[2 * i + 1] = eeval & 0xff;
 443         }
 444         if (sum == 0 || sum == 0xffff * 3)
 445                 return -EADDRNOTAVAIL;
 446
 447         return 0;
 448 }
 449
 450 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
 451 {
 452         u32 rxgain_type;
 453
 454         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
 455                 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
 456
 457                 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
 458                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 459                         ar9280Modes_backoff_13db_rxgain_9280_2,
 460                         ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
 461                 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
 462                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 463                         ar9280Modes_backoff_23db_rxgain_9280_2,
 464                         ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
 465                 else
 466                         INIT_INI_ARRAY(&ah->iniModesRxGain,
 467                         ar9280Modes_original_rxgain_9280_2,
 468                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 469         } else {
 470                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 471                         ar9280Modes_original_rxgain_9280_2,
 472                         ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
 473         }
 474 }
 475
 476 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
 477 {
 478         u32 txgain_type;
 479
 480         if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
 481                 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 482
 483                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
 484                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 485                         ar9280Modes_high_power_tx_gain_9280_2,
 486                         ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
 487                 else
 488                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 489                         ar9280Modes_original_tx_gain_9280_2,
 490                         ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 491         } else {
 492                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 493                 ar9280Modes_original_tx_gain_9280_2,
 494                 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
 495         }
 496 }
 497
 498 static int ath9k_hw_post_init(struct ath_hw *ah)
 499 {
 500         int ecode;
 501
 502         if (!ath9k_hw_chip_test(ah))
 503                 return -ENODEV;
 504
 505         ecode = ath9k_hw_rf_claim(ah);
 506         if (ecode != 0)
 507                 return ecode;
 508
 509         ecode = ath9k_hw_eeprom_init(ah);
 510         if (ecode != 0)
 511                 return ecode;
 512
 513         ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
 514                   "Eeprom VER: %d, REV: %d\n",
 515                   ah->eep_ops->get_eeprom_ver(ah),
 516                   ah->eep_ops->get_eeprom_rev(ah));
 517
 518         if (!AR_SREV_9280_10_OR_LATER(ah)) {
 519                 ecode = ath9k_hw_rf_alloc_ext_banks(ah);
 520                 if (ecode) {
 521                         ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 522                                   "Failed allocating banks for "
 523                                   "external radio\n");
 524                         return ecode;
 525                 }
 526         }
 527
 528         if (!AR_SREV_9100(ah)) {
 529                 ath9k_hw_ani_setup(ah);
 530                 ath9k_hw_ani_init(ah);
 531         }
 532
 533         return 0;
 534 }
 535
 536 static bool ath9k_hw_devid_supported(u16 devid)
 537 {
 538         switch (devid) {
 539         case AR5416_DEVID_PCI:
 540         case AR5416_DEVID_PCIE:
 541         case AR5416_AR9100_DEVID:
 542         case AR9160_DEVID_PCI:
 543         case AR9280_DEVID_PCI:
 544         case AR9280_DEVID_PCIE:
 545         case AR9285_DEVID_PCIE:
 546         case AR5416_DEVID_AR9287_PCI:
 547         case AR5416_DEVID_AR9287_PCIE:
 548         case AR9271_USB:
 549         case AR2427_DEVID_PCIE:
 550                 return true;
 551         default:
 552                 break;
 553         }
 554         return false;
 555 }
 556
 557 static bool ath9k_hw_macversion_supported(u32 macversion)
 558 {
 559         switch (macversion) {
 560         case AR_SREV_VERSION_5416_PCI:
 561         case AR_SREV_VERSION_5416_PCIE:
 562         case AR_SREV_VERSION_9160:
 563         case AR_SREV_VERSION_9100:
 564         case AR_SREV_VERSION_9280:
 565         case AR_SREV_VERSION_9285:
 566         case AR_SREV_VERSION_9287:
 567         case AR_SREV_VERSION_9271:
 568                 return true;
 569         default:
 570                 break;
 571         }
 572         return false;
 573 }
 574
 575 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
 576 {
 577         if (AR_SREV_9160_10_OR_LATER(ah)) {
 578                 if (AR_SREV_9280_10_OR_LATER(ah)) {
 579                         ah->iq_caldata.calData = &iq_cal_single_sample;
 580                         ah->adcgain_caldata.calData =
 581                                 &adc_gain_cal_single_sample;
 582                         ah->adcdc_caldata.calData =
 583                                 &adc_dc_cal_single_sample;
 584                         ah->adcdc_calinitdata.calData =
 585                                 &adc_init_dc_cal;
 586                 } else {
 587                         ah->iq_caldata.calData = &iq_cal_multi_sample;
 588                         ah->adcgain_caldata.calData =
 589                                 &adc_gain_cal_multi_sample;
 590                         ah->adcdc_caldata.calData =
 591                                 &adc_dc_cal_multi_sample;
 592                         ah->adcdc_calinitdata.calData =
 593                                 &adc_init_dc_cal;
 594                 }
 595                 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
 596         }
 597 }
 598
 599 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
 600 {
 601         if (AR_SREV_9271(ah)) {
 602                 INIT_INI_ARRAY(&ah->iniModes, ar9271Modes_9271,
 603                                ARRAY_SIZE(ar9271Modes_9271), 6);
 604                 INIT_INI_ARRAY(&ah->iniCommon, ar9271Common_9271,
 605                                ARRAY_SIZE(ar9271Common_9271), 2);
 606                 INIT_INI_ARRAY(&ah->iniCommon_normal_cck_fir_coeff_9271,
 607                                ar9271Common_normal_cck_fir_coeff_9271,
 608                                ARRAY_SIZE(ar9271Common_normal_cck_fir_coeff_9271), 2);
 609                 INIT_INI_ARRAY(&ah->iniCommon_japan_2484_cck_fir_coeff_9271,
 610                                ar9271Common_japan_2484_cck_fir_coeff_9271,
 611                                ARRAY_SIZE(ar9271Common_japan_2484_cck_fir_coeff_9271), 2);
 612                 INIT_INI_ARRAY(&ah->iniModes_9271_1_0_only,
 613                                ar9271Modes_9271_1_0_only,
 614                                ARRAY_SIZE(ar9271Modes_9271_1_0_only), 6);
 615                 INIT_INI_ARRAY(&ah->iniModes_9271_ANI_reg, ar9271Modes_9271_ANI_reg,
 616                                ARRAY_SIZE(ar9271Modes_9271_ANI_reg), 6);
 617                 INIT_INI_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
 618                                ar9271Modes_high_power_tx_gain_9271,
 619                                ARRAY_SIZE(ar9271Modes_high_power_tx_gain_9271), 6);
 620                 INIT_INI_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
 621                                ar9271Modes_normal_power_tx_gain_9271,
 622                                ARRAY_SIZE(ar9271Modes_normal_power_tx_gain_9271), 6);
 623                 return;
 624         }
 625
 626         if (AR_SREV_9287_11_OR_LATER(ah)) {
 627                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_1,
 628                                 ARRAY_SIZE(ar9287Modes_9287_1_1), 6);
 629                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_1,
 630                                 ARRAY_SIZE(ar9287Common_9287_1_1), 2);
 631                 if (ah->config.pcie_clock_req)
 632                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 633                         ar9287PciePhy_clkreq_off_L1_9287_1_1,
 634                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_1), 2);
 635                 else
 636                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 637                         ar9287PciePhy_clkreq_always_on_L1_9287_1_1,
 638                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_1),
 639                                         2);
 640         } else if (AR_SREV_9287_10_OR_LATER(ah)) {
 641                 INIT_INI_ARRAY(&ah->iniModes, ar9287Modes_9287_1_0,
 642                                 ARRAY_SIZE(ar9287Modes_9287_1_0), 6);
 643                 INIT_INI_ARRAY(&ah->iniCommon, ar9287Common_9287_1_0,
 644                                 ARRAY_SIZE(ar9287Common_9287_1_0), 2);
 645
 646                 if (ah->config.pcie_clock_req)
 647                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 648                         ar9287PciePhy_clkreq_off_L1_9287_1_0,
 649                         ARRAY_SIZE(ar9287PciePhy_clkreq_off_L1_9287_1_0), 2);
 650                 else
 651                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 652                         ar9287PciePhy_clkreq_always_on_L1_9287_1_0,
 653                         ARRAY_SIZE(ar9287PciePhy_clkreq_always_on_L1_9287_1_0),
 654                                   2);
 655         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
 656
 657
 658                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
 659                                ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
 660                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
 661                                ARRAY_SIZE(ar9285Common_9285_1_2), 2);
 662
 663                 if (ah->config.pcie_clock_req) {
 664                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 665                         ar9285PciePhy_clkreq_off_L1_9285_1_2,
 666                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
 667                 } else {
 668                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 669                         ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
 670                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
 671                                   2);
 672                 }
 673         } else if (AR_SREV_9285_10_OR_LATER(ah)) {
 674                 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
 675                                ARRAY_SIZE(ar9285Modes_9285), 6);
 676                 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
 677                                ARRAY_SIZE(ar9285Common_9285), 2);
 678
 679                 if (ah->config.pcie_clock_req) {
 680                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 681                         ar9285PciePhy_clkreq_off_L1_9285,
 682                         ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
 683                 } else {
 684                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 685                         ar9285PciePhy_clkreq_always_on_L1_9285,
 686                         ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
 687                 }
 688         } else if (AR_SREV_9280_20_OR_LATER(ah)) {
 689                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
 690                                ARRAY_SIZE(ar9280Modes_9280_2), 6);
 691                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
 692                                ARRAY_SIZE(ar9280Common_9280_2), 2);
 693
 694                 if (ah->config.pcie_clock_req) {
 695                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 696                                ar9280PciePhy_clkreq_off_L1_9280,
 697                                ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
 698                 } else {
 699                         INIT_INI_ARRAY(&ah->iniPcieSerdes,
 700                                ar9280PciePhy_clkreq_always_on_L1_9280,
 701                                ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
 702                 }
 703                 INIT_INI_ARRAY(&ah->iniModesAdditional,
 704                                ar9280Modes_fast_clock_9280_2,
 705                                ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
 706         } else if (AR_SREV_9280_10_OR_LATER(ah)) {
 707                 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
 708                                ARRAY_SIZE(ar9280Modes_9280), 6);
 709                 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
 710                                ARRAY_SIZE(ar9280Common_9280), 2);
 711         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
 712                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
 713                                ARRAY_SIZE(ar5416Modes_9160), 6);
 714                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
 715                                ARRAY_SIZE(ar5416Common_9160), 2);
 716                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
 717                                ARRAY_SIZE(ar5416Bank0_9160), 2);
 718                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
 719                                ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
 720                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
 721                                ARRAY_SIZE(ar5416Bank1_9160), 2);
 722                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
 723                                ARRAY_SIZE(ar5416Bank2_9160), 2);
 724                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
 725                                ARRAY_SIZE(ar5416Bank3_9160), 3);
 726                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
 727                                ARRAY_SIZE(ar5416Bank6_9160), 3);
 728                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
 729                                ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
 730                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
 731                                ARRAY_SIZE(ar5416Bank7_9160), 2);
 732                 if (AR_SREV_9160_11(ah)) {
 733                         INIT_INI_ARRAY(&ah->iniAddac,
 734                                        ar5416Addac_91601_1,
 735                                        ARRAY_SIZE(ar5416Addac_91601_1), 2);
 736                 } else {
 737                         INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
 738                                        ARRAY_SIZE(ar5416Addac_9160), 2);
 739                 }
 740         } else if (AR_SREV_9100_OR_LATER(ah)) {
 741                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
 742                                ARRAY_SIZE(ar5416Modes_9100), 6);
 743                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
 744                                ARRAY_SIZE(ar5416Common_9100), 2);
 745                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
 746                                ARRAY_SIZE(ar5416Bank0_9100), 2);
 747                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
 748                                ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
 749                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
 750                                ARRAY_SIZE(ar5416Bank1_9100), 2);
 751                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
 752                                ARRAY_SIZE(ar5416Bank2_9100), 2);
 753                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
 754                                ARRAY_SIZE(ar5416Bank3_9100), 3);
 755                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
 756                                ARRAY_SIZE(ar5416Bank6_9100), 3);
 757                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
 758                                ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
 759                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
 760                                ARRAY_SIZE(ar5416Bank7_9100), 2);
 761                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
 762                                ARRAY_SIZE(ar5416Addac_9100), 2);
 763         } else {
 764                 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
 765                                ARRAY_SIZE(ar5416Modes), 6);
 766                 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
 767                                ARRAY_SIZE(ar5416Common), 2);
 768                 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
 769                                ARRAY_SIZE(ar5416Bank0), 2);
 770                 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
 771                                ARRAY_SIZE(ar5416BB_RfGain), 3);
 772                 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
 773                                ARRAY_SIZE(ar5416Bank1), 2);
 774                 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
 775                                ARRAY_SIZE(ar5416Bank2), 2);
 776                 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
 777                                ARRAY_SIZE(ar5416Bank3), 3);
 778                 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
 779                                ARRAY_SIZE(ar5416Bank6), 3);
 780                 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
 781                                ARRAY_SIZE(ar5416Bank6TPC), 3);
 782                 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
 783                                ARRAY_SIZE(ar5416Bank7), 2);
 784                 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
 785                                ARRAY_SIZE(ar5416Addac), 2);
 786         }
 787 }
 788
 789 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
 790 {
 791         if (AR_SREV_9287_11_OR_LATER(ah))
 792                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 793                 ar9287Modes_rx_gain_9287_1_1,
 794                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_1), 6);
 795         else if (AR_SREV_9287_10(ah))
 796                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 797                 ar9287Modes_rx_gain_9287_1_0,
 798                 ARRAY_SIZE(ar9287Modes_rx_gain_9287_1_0), 6);
 799         else if (AR_SREV_9280_20(ah))
 800                 ath9k_hw_init_rxgain_ini(ah);
 801
 802         if (AR_SREV_9287_11_OR_LATER(ah)) {
 803                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 804                 ar9287Modes_tx_gain_9287_1_1,
 805                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_1), 6);
 806         } else if (AR_SREV_9287_10(ah)) {
 807                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 808                 ar9287Modes_tx_gain_9287_1_0,
 809                 ARRAY_SIZE(ar9287Modes_tx_gain_9287_1_0), 6);
 810         } else if (AR_SREV_9280_20(ah)) {
 811                 ath9k_hw_init_txgain_ini(ah);
 812         } else if (AR_SREV_9285_12_OR_LATER(ah)) {
 813                 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
 814
 815                 /* txgain table */
 816                 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
 817                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 818                         ar9285Modes_high_power_tx_gain_9285_1_2,
 819                         ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
 820                 } else {
 821                         INIT_INI_ARRAY(&ah->iniModesTxGain,
 822                         ar9285Modes_original_tx_gain_9285_1_2,
 823                         ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
 824                 }
 825
 826         }
 827 }
 828
 829 static void ath9k_hw_init_eeprom_fix(struct ath_hw *ah)
 830 {
 831         u32 i, j;
 832
 833         if (ah->hw_version.devid == AR9280_DEVID_PCI) {
 834
 835                 /* EEPROM Fixup */
 836                 for (i = 0; i < ah->iniModes.ia_rows; i++) {
 837                         u32 reg = INI_RA(&ah->iniModes, i, 0);
 838
 839                         for (j = 1; j < ah->iniModes.ia_columns; j++) {
 840                                 u32 val = INI_RA(&ah->iniModes, i, j);
 841
 842                                 INI_RA(&ah->iniModes, i, j) =
 843                                         ath9k_hw_ini_fixup(ah,
 844                                                            &ah->eeprom.def,
 845                                                            reg, val);
 846                         }
 847                 }
 848         }
 849 }
 850
 851 int ath9k_hw_init(struct ath_hw *ah)
 852 {
 853         struct ath_common *common = ath9k_hw_common(ah);
 854         int r = 0;
 855
 856         if (!ath9k_hw_devid_supported(ah->hw_version.devid)) {
 857                 ath_print(common, ATH_DBG_FATAL,
 858                           "Unsupported device ID: 0x%0x\n",
 859                           ah->hw_version.devid);
 860                 return -EOPNOTSUPP;
 861         }
 862
 863         ath9k_hw_init_defaults(ah);
 864         ath9k_hw_init_config(ah);
 865
 866         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
 867                 ath_print(common, ATH_DBG_FATAL,
 868                           "Couldn't reset chip\n");
 869                 return -EIO;
 870         }
 871
 872         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
 873                 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
 874                 return -EIO;
 875         }
 876
 877         if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
 878                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
 879                     (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
 880                         ah->config.serialize_regmode =
 881                                 SER_REG_MODE_ON;
 882                 } else {
 883                         ah->config.serialize_regmode =
 884                                 SER_REG_MODE_OFF;
 885                 }
 886         }
 887
 888         ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
 889                 ah->config.serialize_regmode);
 890
 891         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
 892                 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
 893         else
 894                 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
 895
 896         if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
 897                 ath_print(common, ATH_DBG_FATAL,
 898                           "Mac Chip Rev 0x%02x.%x is not supported by "
 899                           "this driver\n", ah->hw_version.macVersion,
 900                           ah->hw_version.macRev);
 901                 return -EOPNOTSUPP;
 902         }
 903
 904         if (AR_SREV_9100(ah)) {
 905                 ah->iq_caldata.calData = &iq_cal_multi_sample;
 906                 ah->supp_cals = IQ_MISMATCH_CAL;
 907                 ah->is_pciexpress = false;
 908         }
 909
 910         if (AR_SREV_9271(ah))
 911                 ah->is_pciexpress = false;
 912
 913         ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
 914
 915         ath9k_hw_init_cal_settings(ah);
 916
 917         ah->ani_function = ATH9K_ANI_ALL;
 918         if (AR_SREV_9280_10_OR_LATER(ah)) {
 919                 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
 920                 ah->ath9k_hw_rf_set_freq = &ath9k_hw_ar9280_set_channel;
 921                 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_9280_spur_mitigate;
 922         } else {
 923                 ah->ath9k_hw_rf_set_freq = &ath9k_hw_set_channel;
 924                 ah->ath9k_hw_spur_mitigate_freq = &ath9k_hw_spur_mitigate;
 925         }
 926
 927         ath9k_hw_init_mode_regs(ah);
 928
 929         if (ah->is_pciexpress)
 930                 ath9k_hw_configpcipowersave(ah, 0, 0);
 931         else
 932                 ath9k_hw_disablepcie(ah);
 933
 934         /* Support for Japan ch.14 (2484) spread */
 935         if (AR_SREV_9287_11_OR_LATER(ah)) {
 936                 INIT_INI_ARRAY(&ah->iniCckfirNormal,
 937                        ar9287Common_normal_cck_fir_coeff_92871_1,
 938                        ARRAY_SIZE(ar9287Common_normal_cck_fir_coeff_92871_1), 2);
 939                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 940                        ar9287Common_japan_2484_cck_fir_coeff_92871_1,
 941                        ARRAY_SIZE(ar9287Common_japan_2484_cck_fir_coeff_92871_1), 2);
 942         }
 943
 944         r = ath9k_hw_post_init(ah);
 945         if (r)
 946                 return r;
 947
 948         ath9k_hw_init_mode_gain_regs(ah);
 949         r = ath9k_hw_fill_cap_info(ah);
 950         if (r)
 951                 return r;
 952
 953         ath9k_hw_init_eeprom_fix(ah);
 954
 955         r = ath9k_hw_init_macaddr(ah);
 956         if (r) {
 957                 ath_print(common, ATH_DBG_FATAL,
 958                           "Failed to initialize MAC address\n");
 959                 return r;
 960         }
 961
 962         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
 963                 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
 964         else
 965                 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
 966
 967         ath9k_init_nfcal_hist_buffer(ah);
 968
 969         common->state = ATH_HW_INITIALIZED;
 970
 971         return 0;
 972 }
 973
 974 static void ath9k_hw_init_bb(struct ath_hw *ah,
 975                              struct ath9k_channel *chan)
 976 {
 977         u32 synthDelay;
 978
 979         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 980         if (IS_CHAN_B(chan))
 981                 synthDelay = (4 * synthDelay) / 22;
 982         else
 983                 synthDelay /= 10;
 984
 985         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
 986
 987         udelay(synthDelay + BASE_ACTIVATE_DELAY);
 988 }
 989
 990 static void ath9k_hw_init_qos(struct ath_hw *ah)
 991 {
 992         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
 993         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
 994
 995         REG_WRITE(ah, AR_QOS_NO_ACK,
 996                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
 997                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
 998                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
 999
1000         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
1001         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
1002         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
1003         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
1004         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
1005 }
1006
1007 static void ath9k_hw_change_target_baud(struct ath_hw *ah, u32 freq, u32 baud)
1008 {
1009         u32 lcr;
1010         u32 baud_divider = freq * 1000 * 1000 / 16 / baud;
1011
1012         lcr = REG_READ(ah , 0x5100c);
1013         lcr |= 0x80;
1014
1015         REG_WRITE(ah, 0x5100c, lcr);
1016         REG_WRITE(ah, 0x51004, (baud_divider >> 8));
1017         REG_WRITE(ah, 0x51000, (baud_divider & 0xff));
1018
1019         lcr &= ~0x80;
1020         REG_WRITE(ah, 0x5100c, lcr);
1021 }
1022
1023 static void ath9k_hw_init_pll(struct ath_hw *ah,
1024                               struct ath9k_channel *chan)
1025 {
1026         u32 pll;
1027
1028         if (AR_SREV_9100(ah)) {
1029                 if (chan && IS_CHAN_5GHZ(chan))
1030                         pll = 0x1450;
1031                 else
1032                         pll = 0x1458;
1033         } else {
1034                 if (AR_SREV_9280_10_OR_LATER(ah)) {
1035                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1036
1037                         if (chan && IS_CHAN_HALF_RATE(chan))
1038                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1039                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1040                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1041
1042                         if (chan && IS_CHAN_5GHZ(chan)) {
1043                                 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1044
1045
1046                                 if (AR_SREV_9280_20(ah)) {
1047                                         if (((chan->channel % 20) == 0)
1048                                             || ((chan->channel % 10) == 0))
1049                                                 pll = 0x2850;
1050                                         else
1051                                                 pll = 0x142c;
1052                                 }
1053                         } else {
1054                                 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1055                         }
1056
1057                 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1058
1059                         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1060
1061                         if (chan && IS_CHAN_HALF_RATE(chan))
1062                                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1063                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1064                                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1065
1066                         if (chan && IS_CHAN_5GHZ(chan))
1067                                 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1068                         else
1069                                 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1070                 } else {
1071                         pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1072
1073                         if (chan && IS_CHAN_HALF_RATE(chan))
1074                                 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1075                         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1076                                 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1077
1078                         if (chan && IS_CHAN_5GHZ(chan))
1079                                 pll |= SM(0xa, AR_RTC_PLL_DIV);
1080                         else
1081                                 pll |= SM(0xb, AR_RTC_PLL_DIV);
1082                 }
1083         }
1084         REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1085
1086         /* Switch the core clock for ar9271 to 117Mhz */
1087         if (AR_SREV_9271(ah)) {
1088                 if ((pll == 0x142c) || (pll == 0x2850) ) {
1089                         udelay(500);
1090                         /* set CLKOBS to output AHB clock */
1091                         REG_WRITE(ah, 0x7020, 0xe);
1092                         /*
1093                          * 0x304: 117Mhz, ahb_ratio: 1x1
1094                          * 0x306: 40Mhz, ahb_ratio: 1x1
1095                          */
1096                         REG_WRITE(ah, 0x50040, 0x304);
1097                         /*
1098                          * makes adjustments for the baud dividor to keep the
1099                          * targetted baud rate based on the used core clock.
1100                          */
1101                         ath9k_hw_change_target_baud(ah, AR9271_CORE_CLOCK,
1102                                                     AR9271_TARGET_BAUD_RATE);
1103                 }
1104         }
1105
1106         udelay(RTC_PLL_SETTLE_DELAY);
1107
1108         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1109 }
1110
1111 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1112 {
1113         int rx_chainmask, tx_chainmask;
1114
1115         rx_chainmask = ah->rxchainmask;
1116         tx_chainmask = ah->txchainmask;
1117
1118         switch (rx_chainmask) {
1119         case 0x5:
1120                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1121                             AR_PHY_SWAP_ALT_CHAIN);
1122         case 0x3:
1123                 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
1124                         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1125                         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1126                         break;
1127                 }
1128         case 0x1:
1129         case 0x2:
1130         case 0x7:
1131                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1132                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1133                 break;
1134         default:
1135                 break;
1136         }
1137
1138         REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1139         if (tx_chainmask == 0x5) {
1140                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1141                             AR_PHY_SWAP_ALT_CHAIN);
1142         }
1143         if (AR_SREV_9100(ah))
1144                 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1145                           REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1146 }
1147
1148 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1149                                           enum nl80211_iftype opmode)
1150 {
1151         ah->mask_reg = AR_IMR_TXERR |
1152                 AR_IMR_TXURN |
1153                 AR_IMR_RXERR |
1154                 AR_IMR_RXORN |
1155                 AR_IMR_BCNMISC;
1156
1157         if (ah->config.rx_intr_mitigation)
1158                 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1159         else
1160                 ah->mask_reg |= AR_IMR_RXOK;
1161
1162         ah->mask_reg |= AR_IMR_TXOK;
1163
1164         if (opmode == NL80211_IFTYPE_AP)
1165                 ah->mask_reg |= AR_IMR_MIB;
1166
1167         REG_WRITE(ah, AR_IMR, ah->mask_reg);
1168         ah->imrs2_reg |= AR_IMR_S2_GTT;
1169         REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
1170
1171         if (!AR_SREV_9100(ah)) {
1172                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1173                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1174                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1175         }
1176 }
1177
1178 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
1179 {
1180         u32 val = ath9k_hw_mac_to_clks(ah, us);
1181         val = min(val, (u32) 0xFFFF);
1182         REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
1183 }
1184
1185 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1186 {
1187         u32 val = ath9k_hw_mac_to_clks(ah, us);
1188         val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
1189         REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
1190 }
1191
1192 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1193 {
1194         u32 val = ath9k_hw_mac_to_clks(ah, us);
1195         val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
1196         REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
1197 }
1198
1199 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1200 {
1201         if (tu > 0xFFFF) {
1202                 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
1203                           "bad global tx timeout %u\n", tu);
1204                 ah->globaltxtimeout = (u32) -1;
1205                 return false;
1206         } else {
1207                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1208                 ah->globaltxtimeout = tu;
1209                 return true;
1210         }
1211 }
1212
1213 void ath9k_hw_init_global_settings(struct ath_hw *ah)
1214 {
1215         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
1216         int acktimeout;
1217         int slottime;
1218         int sifstime;
1219
1220         ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1221                   ah->misc_mode);
1222
1223         if (ah->misc_mode != 0)
1224                 REG_WRITE(ah, AR_PCU_MISC,
1225                           REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1226
1227         if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
1228                 sifstime = 16;
1229         else
1230                 sifstime = 10;
1231
1232         /* As defined by IEEE 802.11-2007 17.3.8.6 */
1233         slottime = ah->slottime + 3 * ah->coverage_class;
1234         acktimeout = slottime + sifstime;
1235
1236         /*
1237          * Workaround for early ACK timeouts, add an offset to match the
1238          * initval's 64us ack timeout value.
1239          * This was initially only meant to work around an issue with delayed
1240          * BA frames in some implementations, but it has been found to fix ACK
1241          * timeout issues in other cases as well.
1242          */
1243         if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
1244                 acktimeout += 64 - sifstime - ah->slottime;
1245
1246         ath9k_hw_setslottime(ah, slottime);
1247         ath9k_hw_set_ack_timeout(ah, acktimeout);
1248         ath9k_hw_set_cts_timeout(ah, acktimeout);
1249         if (ah->globaltxtimeout != (u32) -1)
1250                 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1251 }
1252 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
1253
1254 void ath9k_hw_deinit(struct ath_hw *ah)
1255 {
1256         struct ath_common *common = ath9k_hw_common(ah);
1257
1258         if (common->state <= ATH_HW_INITIALIZED)
1259                 goto free_hw;
1260
1261         if (!AR_SREV_9100(ah))
1262                 ath9k_hw_ani_disable(ah);
1263
1264         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1265
1266 free_hw:
1267         if (!AR_SREV_9280_10_OR_LATER(ah))
1268                 ath9k_hw_rf_free_ext_banks(ah);
1269         kfree(ah);
1270         ah = NULL;
1271 }
1272 EXPORT_SYMBOL(ath9k_hw_deinit);
1273
1274 /*******/
1275 /* INI */
1276 /*******/
1277
1278 static void ath9k_hw_override_ini(struct ath_hw *ah,
1279                                   struct ath9k_channel *chan)
1280 {
1281         u32 val;
1282
1283         /*
1284          * Set the RX_ABORT and RX_DIS and clear if off only after
1285          * RXE is set for MAC. This prevents frames with corrupted
1286          * descriptor status.
1287          */
1288         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1289
1290         if (AR_SREV_9280_10_OR_LATER(ah)) {
1291                 val = REG_READ(ah, AR_PCU_MISC_MODE2);
1292
1293                 if (!AR_SREV_9271(ah))
1294                         val &= ~AR_PCU_MISC_MODE2_HWWAR1;
1295
1296                 if (AR_SREV_9287_10_OR_LATER(ah))
1297                         val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
1298
1299                 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
1300         }
1301
1302         if (!AR_SREV_5416_20_OR_LATER(ah) ||
1303             AR_SREV_9280_10_OR_LATER(ah))
1304                 return;
1305         /*
1306          * Disable BB clock gating
1307          * Necessary to avoid issues on AR5416 2.0
1308          */
1309         REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1310
1311         /*
1312          * Disable RIFS search on some chips to avoid baseband
1313          * hang issues.
1314          */
1315         if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) {
1316                 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
1317                 val &= ~AR_PHY_RIFS_INIT_DELAY;
1318                 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
1319         }
1320 }
1321
1322 static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1323                               struct ar5416_eeprom_def *pEepData,
1324                               u32 reg, u32 value)
1325 {
1326         struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1327         struct ath_common *common = ath9k_hw_common(ah);
1328
1329         switch (ah->hw_version.devid) {
1330         case AR9280_DEVID_PCI:
1331                 if (reg == 0x7894) {
1332                         ath_print(common, ATH_DBG_EEPROM,
1333                                 "ini VAL: %x  EEPROM: %x\n", value,
1334                                 (pBase->version & 0xff));
1335
1336                         if ((pBase->version & 0xff) > 0x0a) {
1337                                 ath_print(common, ATH_DBG_EEPROM,
1338                                           "PWDCLKIND: %d\n",
1339                                           pBase->pwdclkind);
1340                                 value &= ~AR_AN_TOP2_PWDCLKIND;
1341                                 value |= AR_AN_TOP2_PWDCLKIND &
1342                                         (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1343                         } else {
1344                                 ath_print(common, ATH_DBG_EEPROM,
1345                                           "PWDCLKIND Earlier Rev\n");
1346                         }
1347
1348                         ath_print(common, ATH_DBG_EEPROM,
1349                                   "final ini VAL: %x\n", value);
1350                 }
1351                 break;
1352         }
1353
1354         return value;
1355 }
1356
1357 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1358                               struct ar5416_eeprom_def *pEepData,
1359                               u32 reg, u32 value)
1360 {
1361         if (ah->eep_map == EEP_MAP_4KBITS)
1362                 return value;
1363         else
1364                 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1365 }
1366
1367 static void ath9k_olc_init(struct ath_hw *ah)
1368 {
1369         u32 i;
1370
1371         if (OLC_FOR_AR9287_10_LATER) {
1372                 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
1373                                 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
1374                 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
1375                                 AR9287_AN_TXPC0_TXPCMODE,
1376                                 AR9287_AN_TXPC0_TXPCMODE_S,
1377                                 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
1378                 udelay(100);
1379         } else {
1380                 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1381                         ah->originalGain[i] =
1382                                 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1383                                                 AR_PHY_TX_GAIN);
1384                 ah->PDADCdelta = 0;
1385         }
1386 }
1387
1388 static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1389                               struct ath9k_channel *chan)
1390 {
1391         u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1392
1393         if (IS_CHAN_B(chan))
1394                 ctl |= CTL_11B;
1395         else if (IS_CHAN_G(chan))
1396                 ctl |= CTL_11G;
1397         else
1398                 ctl |= CTL_11A;
1399
1400         return ctl;
1401 }
1402
1403 static int ath9k_hw_process_ini(struct ath_hw *ah,
1404                                 struct ath9k_channel *chan)
1405 {
1406         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1407         int i, regWrites = 0;
1408         struct ieee80211_channel *channel = chan->chan;
1409         u32 modesIndex, freqIndex;
1410
1411         switch (chan->chanmode) {
1412         case CHANNEL_A:
1413         case CHANNEL_A_HT20:
1414                 modesIndex = 1;
1415                 freqIndex = 1;
1416                 break;
1417         case CHANNEL_A_HT40PLUS:
1418         case CHANNEL_A_HT40MINUS:
1419                 modesIndex = 2;
1420                 freqIndex = 1;
1421                 break;
1422         case CHANNEL_G:
1423         case CHANNEL_G_HT20:
1424         case CHANNEL_B:
1425                 modesIndex = 4;
1426                 freqIndex = 2;
1427                 break;
1428         case CHANNEL_G_HT40PLUS:
1429         case CHANNEL_G_HT40MINUS:
1430                 modesIndex = 3;
1431                 freqIndex = 2;
1432                 break;
1433
1434         default:
1435                 return -EINVAL;
1436         }
1437
1438         /* Set correct baseband to analog shift setting to access analog chips */
1439         REG_WRITE(ah, AR_PHY(0), 0x00000007);
1440
1441         /* Write ADDAC shifts */
1442         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1443         ah->eep_ops->set_addac(ah, chan);
1444
1445         if (AR_SREV_5416_22_OR_LATER(ah)) {
1446                 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1447         } else {
1448                 struct ar5416IniArray temp;
1449                 u32 addacSize =
1450                         sizeof(u32) * ah->iniAddac.ia_rows *
1451                         ah->iniAddac.ia_columns;
1452
1453                 /* For AR5416 2.0/2.1 */
1454                 memcpy(ah->addac5416_21,
1455                        ah->iniAddac.ia_array, addacSize);
1456
1457                 /* override CLKDRV value at [row, column] = [31, 1] */
1458                 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1459
1460                 temp.ia_array = ah->addac5416_21;
1461                 temp.ia_columns = ah->iniAddac.ia_columns;
1462                 temp.ia_rows = ah->iniAddac.ia_rows;
1463                 REG_WRITE_ARRAY(&temp, 1, regWrites);
1464         }
1465
1466         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1467
1468         for (i = 0; i < ah->iniModes.ia_rows; i++) {
1469                 u32 reg = INI_RA(&ah->iniModes, i, 0);
1470                 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1471
1472                 REG_WRITE(ah, reg, val);
1473
1474                 if (reg >= 0x7800 && reg < 0x78a0
1475                     && ah->config.analog_shiftreg) {
1476                         udelay(100);
1477                 }
1478
1479                 DO_DELAY(regWrites);
1480         }
1481
1482         if (AR_SREV_9280(ah) || AR_SREV_9287_10_OR_LATER(ah))
1483                 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1484
1485         if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
1486             AR_SREV_9287_10_OR_LATER(ah))
1487                 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1488
1489         if (AR_SREV_9271_10(ah))
1490                 REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
1491                                 modesIndex, regWrites);
1492
1493         /* Write common array parameters */
1494         for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1495                 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1496                 u32 val = INI_RA(&ah->iniCommon, i, 1);
1497
1498                 REG_WRITE(ah, reg, val);
1499
1500                 if (reg >= 0x7800 && reg < 0x78a0
1501                     && ah->config.analog_shiftreg) {
1502                         udelay(100);
1503                 }
1504
1505                 DO_DELAY(regWrites);
1506         }
1507
1508         if (AR_SREV_9271(ah)) {
1509                 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 1)
1510                         REG_WRITE_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
1511                                         modesIndex, regWrites);
1512                 else
1513                         REG_WRITE_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
1514                                         modesIndex, regWrites);
1515         }
1516
1517         ath9k_hw_write_regs(ah, freqIndex, regWrites);
1518
1519         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1520                 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1521                                 regWrites);
1522         }
1523
1524         ath9k_hw_override_ini(ah, chan);
1525         ath9k_hw_set_regs(ah, chan);
1526         ath9k_hw_init_chain_masks(ah);
1527
1528         if (OLC_FOR_AR9280_20_LATER)
1529                 ath9k_olc_init(ah);
1530
1531         /* Set TX power */
1532         ah->eep_ops->set_txpower(ah, chan,
1533                                  ath9k_regd_get_ctl(regulatory, chan),
1534                                  channel->max_antenna_gain * 2,
1535                                  channel->max_power * 2,
1536                                  min((u32) MAX_RATE_POWER,
1537                                  (u32) regulatory->power_limit));
1538
1539         /* Write analog registers */
1540         if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1541                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1542                           "ar5416SetRfRegs failed\n");
1543                 return -EIO;
1544         }
1545
1546         return 0;
1547 }
1548
1549 /****************************************/
1550 /* Reset and Channel Switching Routines */
1551 /****************************************/
1552
1553 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1554 {
1555         u32 rfMode = 0;
1556
1557         if (chan == NULL)
1558                 return;
1559
1560         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1561                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1562
1563         if (!AR_SREV_9280_10_OR_LATER(ah))
1564                 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1565                         AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1566
1567         if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1568                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1569
1570         REG_WRITE(ah, AR_PHY_MODE, rfMode);
1571 }
1572
1573 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1574 {
1575         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1576 }
1577
1578 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1579 {
1580         u32 regval;
1581
1582         /*
1583          * set AHB_MODE not to do cacheline prefetches
1584         */
1585         regval = REG_READ(ah, AR_AHB_MODE);
1586         REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1587
1588         /*
1589          * let mac dma reads be in 128 byte chunks
1590          */
1591         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1592         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1593
1594         /*
1595          * Restore TX Trigger Level to its pre-reset value.
1596          * The initial value depends on whether aggregation is enabled, and is
1597          * adjusted whenever underruns are detected.
1598          */
1599         REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1600
1601         /*
1602          * let mac dma writes be in 128 byte chunks
1603          */
1604         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1605         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1606
1607         /*
1608          * Setup receive FIFO threshold to hold off TX activities
1609          */
1610         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1611
1612         /*
1613          * reduce the number of usable entries in PCU TXBUF to avoid
1614          * wrap around issues.
1615          */
1616         if (AR_SREV_9285(ah)) {
1617                 /* For AR9285 the number of Fifos are reduced to half.
1618                  * So set the usable tx buf size also to half to
1619                  * avoid data/delimiter underruns
1620                  */
1621                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1622                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1623         } else if (!AR_SREV_9271(ah)) {
1624                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1625                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1626         }
1627 }
1628
1629 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1630 {
1631         u32 val;
1632
1633         val = REG_READ(ah, AR_STA_ID1);
1634         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1635         switch (opmode) {
1636         case NL80211_IFTYPE_AP:
1637                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1638                           | AR_STA_ID1_KSRCH_MODE);
1639                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1640                 break;
1641         case NL80211_IFTYPE_ADHOC:
1642         case NL80211_IFTYPE_MESH_POINT:
1643                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1644                           | AR_STA_ID1_KSRCH_MODE);
1645                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1646                 break;
1647         case NL80211_IFTYPE_STATION:
1648         case NL80211_IFTYPE_MONITOR:
1649                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1650                 break;
1651         }
1652 }
1653
1654 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1655                                                  u32 coef_scaled,
1656                                                  u32 *coef_mantissa,
1657                                                  u32 *coef_exponent)
1658 {
1659         u32 coef_exp, coef_man;
1660
1661         for (coef_exp = 31; coef_exp > 0; coef_exp--)
1662                 if ((coef_scaled >> coef_exp) & 0x1)
1663                         break;
1664
1665         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1666
1667         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1668
1669         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1670         *coef_exponent = coef_exp - 16;
1671 }
1672
1673 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1674                                      struct ath9k_channel *chan)
1675 {
1676         u32 coef_scaled, ds_coef_exp, ds_coef_man;
1677         u32 clockMhzScaled = 0x64000000;
1678         struct chan_centers centers;
1679
1680         if (IS_CHAN_HALF_RATE(chan))
1681                 clockMhzScaled = clockMhzScaled >> 1;
1682         else if (IS_CHAN_QUARTER_RATE(chan))
1683                 clockMhzScaled = clockMhzScaled >> 2;
1684
1685         ath9k_hw_get_channel_centers(ah, chan, &centers);
1686         coef_scaled = clockMhzScaled / centers.synth_center;
1687
1688         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1689                                       &ds_coef_exp);
1690
1691         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1692                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1693         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1694                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1695
1696         coef_scaled = (9 * coef_scaled) / 10;
1697
1698         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1699                                       &ds_coef_exp);
1700
1701         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1702                       AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1703         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1704                       AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1705 }
1706
1707 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1708 {
1709         u32 rst_flags;
1710         u32 tmpReg;
1711
1712         if (AR_SREV_9100(ah)) {
1713                 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1714                 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1715                 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1716                 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1717                 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1718         }
1719
1720         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1721                   AR_RTC_FORCE_WAKE_ON_INT);
1722
1723         if (AR_SREV_9100(ah)) {
1724                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1725                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1726         } else {
1727                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1728                 if (tmpReg &
1729                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
1730                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1731                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1732                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1733                 } else {
1734                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1735                 }
1736
1737                 rst_flags = AR_RTC_RC_MAC_WARM;
1738                 if (type == ATH9K_RESET_COLD)
1739                         rst_flags |= AR_RTC_RC_MAC_COLD;
1740         }
1741
1742         REG_WRITE(ah, AR_RTC_RC, rst_flags);
1743         udelay(50);
1744
1745         REG_WRITE(ah, AR_RTC_RC, 0);
1746         if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1747                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1748                           "RTC stuck in MAC reset\n");
1749                 return false;
1750         }
1751
1752         if (!AR_SREV_9100(ah))
1753                 REG_WRITE(ah, AR_RC, 0);
1754
1755         if (AR_SREV_9100(ah))
1756                 udelay(50);
1757
1758         return true;
1759 }
1760
1761 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1762 {
1763         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1764                   AR_RTC_FORCE_WAKE_ON_INT);
1765
1766         if (!AR_SREV_9100(ah))
1767                 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1768
1769         REG_WRITE(ah, AR_RTC_RESET, 0);
1770         udelay(2);
1771
1772         if (!AR_SREV_9100(ah))
1773                 REG_WRITE(ah, AR_RC, 0);
1774
1775         REG_WRITE(ah, AR_RTC_RESET, 1);
1776
1777         if (!ath9k_hw_wait(ah,
1778                            AR_RTC_STATUS,
1779                            AR_RTC_STATUS_M,
1780                            AR_RTC_STATUS_ON,
1781                            AH_WAIT_TIMEOUT)) {
1782                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1783                           "RTC not waking up\n");
1784                 return false;
1785         }
1786
1787         ath9k_hw_read_revisions(ah);
1788
1789         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1790 }
1791
1792 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1793 {
1794         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1795                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1796
1797         switch (type) {
1798         case ATH9K_RESET_POWER_ON:
1799                 return ath9k_hw_set_reset_power_on(ah);
1800         case ATH9K_RESET_WARM:
1801         case ATH9K_RESET_COLD:
1802                 return ath9k_hw_set_reset(ah, type);
1803         default:
1804                 return false;
1805         }
1806 }
1807
1808 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan)
1809 {
1810         u32 phymode;
1811         u32 enableDacFifo = 0;
1812
1813         if (AR_SREV_9285_10_OR_LATER(ah))
1814                 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1815                                          AR_PHY_FC_ENABLE_DAC_FIFO);
1816
1817         phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1818                 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1819
1820         if (IS_CHAN_HT40(chan)) {
1821                 phymode |= AR_PHY_FC_DYN2040_EN;
1822
1823                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1824                     (chan->chanmode == CHANNEL_G_HT40PLUS))
1825                         phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1826
1827         }
1828         REG_WRITE(ah, AR_PHY_TURBO, phymode);
1829
1830         ath9k_hw_set11nmac2040(ah);
1831
1832         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1833         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1834 }
1835
1836 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1837                                 struct ath9k_channel *chan)
1838 {
1839         if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1840                 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1841                         return false;
1842         } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1843                 return false;
1844
1845         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1846                 return false;
1847
1848         ah->chip_fullsleep = false;
1849         ath9k_hw_init_pll(ah, chan);
1850         ath9k_hw_set_rfmode(ah, chan);
1851
1852         return true;
1853 }
1854
1855 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1856                                     struct ath9k_channel *chan)
1857 {
1858         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1859         struct ath_common *common = ath9k_hw_common(ah);
1860         struct ieee80211_channel *channel = chan->chan;
1861         u32 synthDelay, qnum;
1862         int r;
1863
1864         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1865                 if (ath9k_hw_numtxpending(ah, qnum)) {
1866                         ath_print(common, ATH_DBG_QUEUE,
1867                                   "Transmit frames pending on "
1868                                   "queue %d\n", qnum);
1869                         return false;
1870                 }
1871         }
1872
1873         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1874         if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1875                            AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1876                 ath_print(common, ATH_DBG_FATAL,
1877                           "Could not kill baseband RX\n");
1878                 return false;
1879         }
1880
1881         ath9k_hw_set_regs(ah, chan);
1882
1883         r = ah->ath9k_hw_rf_set_freq(ah, chan);
1884         if (r) {
1885                 ath_print(common, ATH_DBG_FATAL,
1886                           "Failed to set channel\n");
1887                 return false;
1888         }
1889
1890         ah->eep_ops->set_txpower(ah, chan,
1891                              ath9k_regd_get_ctl(regulatory, chan),
1892                              channel->max_antenna_gain * 2,
1893                              channel->max_power * 2,
1894                              min((u32) MAX_RATE_POWER,
1895                              (u32) regulatory->power_limit));
1896
1897         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1898         if (IS_CHAN_B(chan))
1899                 synthDelay = (4 * synthDelay) / 22;
1900         else
1901                 synthDelay /= 10;
1902
1903         udelay(synthDelay + BASE_ACTIVATE_DELAY);
1904
1905         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1906
1907         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1908                 ath9k_hw_set_delta_slope(ah, chan);
1909
1910         ah->ath9k_hw_spur_mitigate_freq(ah, chan);
1911
1912         if (!chan->oneTimeCalsDone)
1913                 chan->oneTimeCalsDone = true;
1914
1915         return true;
1916 }
1917
1918 static void ath9k_enable_rfkill(struct ath_hw *ah)
1919 {
1920         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
1921                     AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
1922
1923         REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
1924                     AR_GPIO_INPUT_MUX2_RFSILENT);
1925
1926         ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
1927         REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
1928 }
1929
1930 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1931                     bool bChannelChange)
1932 {
1933         struct ath_common *common = ath9k_hw_common(ah);
1934         u32 saveLedState;
1935         struct ath9k_channel *curchan = ah->curchan;
1936         u32 saveDefAntenna;
1937         u32 macStaId1;
1938         u64 tsf = 0;
1939         int i, rx_chainmask, r;
1940
1941         ah->txchainmask = common->tx_chainmask;
1942         ah->rxchainmask = common->rx_chainmask;
1943
1944         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1945                 return -EIO;
1946
1947         if (curchan && !ah->chip_fullsleep)
1948                 ath9k_hw_getnf(ah, curchan);
1949
1950         if (bChannelChange &&
1951             (ah->chip_fullsleep != true) &&
1952             (ah->curchan != NULL) &&
1953             (chan->channel != ah->curchan->channel) &&
1954             ((chan->channelFlags & CHANNEL_ALL) ==
1955              (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1956              !(AR_SREV_9280(ah) || IS_CHAN_A_5MHZ_SPACED(chan) ||
1957              IS_CHAN_A_5MHZ_SPACED(ah->curchan))) {
1958
1959                 if (ath9k_hw_channel_change(ah, chan)) {
1960                         ath9k_hw_loadnf(ah, ah->curchan);
1961                         ath9k_hw_start_nfcal(ah);
1962                         return 0;
1963                 }
1964         }
1965
1966         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1967         if (saveDefAntenna == 0)
1968                 saveDefAntenna = 1;
1969
1970         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1971
1972         /* For chips on which RTC reset is done, save TSF before it gets cleared */
1973         if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1974                 tsf = ath9k_hw_gettsf64(ah);
1975
1976         saveLedState = REG_READ(ah, AR_CFG_LED) &
1977                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1978                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1979
1980         ath9k_hw_mark_phy_inactive(ah);
1981
1982         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1983                 REG_WRITE(ah,
1984                           AR9271_RESET_POWER_DOWN_CONTROL,
1985                           AR9271_RADIO_RF_RST);
1986                 udelay(50);
1987         }
1988
1989         if (!ath9k_hw_chip_reset(ah, chan)) {
1990                 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
1991                 return -EINVAL;
1992         }
1993
1994         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1995                 ah->htc_reset_init = false;
1996                 REG_WRITE(ah,
1997                           AR9271_RESET_POWER_DOWN_CONTROL,
1998                           AR9271_GATE_MAC_CTL);
1999                 udelay(50);
2000         }
2001
2002         /* Restore TSF */
2003         if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
2004                 ath9k_hw_settsf64(ah, tsf);
2005
2006         if (AR_SREV_9280_10_OR_LATER(ah))
2007                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
2008
2009         if (AR_SREV_9287_12_OR_LATER(ah)) {
2010                 /* Enable ASYNC FIFO */
2011                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2012                                 AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL);
2013                 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO);
2014                 REG_CLR_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2015                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2016                 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3,
2017                                 AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET);
2018         }
2019         r = ath9k_hw_process_ini(ah, chan);
2020         if (r)
2021                 return r;
2022
2023         /* Setup MFP options for CCMP */
2024         if (AR_SREV_9280_20_OR_LATER(ah)) {
2025                 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2026                  * frames when constructing CCMP AAD. */
2027                 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2028                               0xc7ff);
2029                 ah->sw_mgmt_crypto = false;
2030         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2031                 /* Disable hardware crypto for management frames */
2032                 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2033                             AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2034                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2035                             AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2036                 ah->sw_mgmt_crypto = true;
2037         } else
2038                 ah->sw_mgmt_crypto = true;
2039
2040         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2041                 ath9k_hw_set_delta_slope(ah, chan);
2042
2043         ah->ath9k_hw_spur_mitigate_freq(ah, chan);
2044         ah->eep_ops->set_board_values(ah, chan);
2045
2046         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
2047         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
2048                   | macStaId1
2049                   | AR_STA_ID1_RTS_USE_DEF
2050                   | (ah->config.
2051                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2052                   | ah->sta_id1_defaults);
2053         ath9k_hw_set_operating_mode(ah, ah->opmode);
2054
2055         ath_hw_setbssidmask(common);
2056
2057         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2058
2059         ath9k_hw_write_associd(ah);
2060
2061         REG_WRITE(ah, AR_ISR, ~0);
2062
2063         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2064
2065         r = ah->ath9k_hw_rf_set_freq(ah, chan);
2066         if (r)
2067                 return r;
2068
2069         for (i = 0; i < AR_NUM_DCU; i++)
2070                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2071
2072         ah->intr_txqs = 0;
2073         for (i = 0; i < ah->caps.total_queues; i++)
2074                 ath9k_hw_resettxqueue(ah, i);
2075
2076         ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2077         ath9k_hw_init_qos(ah);
2078
2079         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2080                 ath9k_enable_rfkill(ah);
2081
2082         ath9k_hw_init_global_settings(ah);
2083
2084         if (AR_SREV_9287_12_OR_LATER(ah)) {
2085                 REG_WRITE(ah, AR_D_GBL_IFS_SIFS,
2086                           AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR);
2087                 REG_WRITE(ah, AR_D_GBL_IFS_SLOT,
2088                           AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR);
2089                 REG_WRITE(ah, AR_D_GBL_IFS_EIFS,
2090                           AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR);
2091
2092                 REG_WRITE(ah, AR_TIME_OUT, AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR);
2093                 REG_WRITE(ah, AR_USEC, AR_USEC_ASYNC_FIFO_DUR);
2094
2095                 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2096                             AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2097                 REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2098                               AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2099         }
2100         if (AR_SREV_9287_12_OR_LATER(ah)) {
2101                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2102                                 AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2103         }
2104
2105         REG_WRITE(ah, AR_STA_ID1,
2106                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2107
2108         ath9k_hw_set_dma(ah);
2109
2110         REG_WRITE(ah, AR_OBS, 8);
2111
2112         if (ah->config.rx_intr_mitigation) {
2113                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2114                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2115         }
2116
2117         ath9k_hw_init_bb(ah, chan);
2118
2119         if (!ath9k_hw_init_cal(ah, chan))
2120                 return -EIO;
2121
2122         rx_chainmask = ah->rxchainmask;
2123         if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2124                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2125                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2126         }
2127
2128         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2129
2130         /*
2131          * For big endian systems turn on swapping for descriptors
2132          */
2133         if (AR_SREV_9100(ah)) {
2134                 u32 mask;
2135                 mask = REG_READ(ah, AR_CFG);
2136                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2137                         ath_print(common, ATH_DBG_RESET,
2138                                 "CFG Byte Swap Set 0x%x\n", mask);
2139                 } else {
2140                         mask =
2141                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2142                         REG_WRITE(ah, AR_CFG, mask);
2143                         ath_print(common, ATH_DBG_RESET,
2144                                 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2145                 }
2146         } else {
2147                 /* Configure AR9271 target WLAN */
2148                 if (AR_SREV_9271(ah))
2149                         REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
2150 #ifdef __BIG_ENDIAN
2151                 else
2152                         REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2153 #endif
2154         }
2155
2156         if (ah->btcoex_hw.enabled)
2157                 ath9k_hw_btcoex_enable(ah);
2158
2159         return 0;
2160 }
2161 EXPORT_SYMBOL(ath9k_hw_reset);
2162
2163 /************************/
2164 /* Key Cache Management */
2165 /************************/
2166
2167 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2168 {
2169         u32 keyType;
2170
2171         if (entry >= ah->caps.keycache_size) {
2172                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2173                           "keychache entry %u out of range\n", entry);
2174                 return false;
2175         }
2176
2177         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2178
2179         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2180         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2181         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2182         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2183         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2184         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2185         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2186         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2187
2188         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2189                 u16 micentry = entry + 64;
2190
2191                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2192                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2193                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2194                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2195
2196         }
2197
2198         return true;
2199 }
2200 EXPORT_SYMBOL(ath9k_hw_keyreset);
2201
2202 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2203 {
2204         u32 macHi, macLo;
2205
2206         if (entry >= ah->caps.keycache_size) {
2207                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2208                           "keychache entry %u out of range\n", entry);
2209                 return false;
2210         }
2211
2212         if (mac != NULL) {
2213                 macHi = (mac[5] << 8) | mac[4];
2214                 macLo = (mac[3] << 24) |
2215                         (mac[2] << 16) |
2216                         (mac[1] << 8) |
2217                         mac[0];
2218                 macLo >>= 1;
2219                 macLo |= (macHi & 1) << 31;
2220                 macHi >>= 1;
2221         } else {
2222                 macLo = macHi = 0;
2223         }
2224         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2225         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2226
2227         return true;
2228 }
2229 EXPORT_SYMBOL(ath9k_hw_keysetmac);
2230
2231 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2232                                  const struct ath9k_keyval *k,
2233                                  const u8 *mac)
2234 {
2235         const struct ath9k_hw_capabilities *pCap = &ah->caps;
2236         struct ath_common *common = ath9k_hw_common(ah);
2237         u32 key0, key1, key2, key3, key4;
2238         u32 keyType;
2239
2240         if (entry >= pCap->keycache_size) {
2241                 ath_print(common, ATH_DBG_FATAL,
2242                           "keycache entry %u out of range\n", entry);
2243                 return false;
2244         }
2245
2246         switch (k->kv_type) {
2247         case ATH9K_CIPHER_AES_OCB:
2248                 keyType = AR_KEYTABLE_TYPE_AES;
2249                 break;
2250         case ATH9K_CIPHER_AES_CCM:
2251                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2252                         ath_print(common, ATH_DBG_ANY,
2253                                   "AES-CCM not supported by mac rev 0x%x\n",
2254                                   ah->hw_version.macRev);
2255                         return false;
2256                 }
2257                 keyType = AR_KEYTABLE_TYPE_CCM;
2258                 break;
2259         case ATH9K_CIPHER_TKIP:
2260                 keyType = AR_KEYTABLE_TYPE_TKIP;
2261                 if (ATH9K_IS_MIC_ENABLED(ah)
2262                     && entry + 64 >= pCap->keycache_size) {
2263                         ath_print(common, ATH_DBG_ANY,
2264                                   "entry %u inappropriate for TKIP\n", entry);
2265                         return false;
2266                 }
2267                 break;
2268         case ATH9K_CIPHER_WEP:
2269                 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
2270                         ath_print(common, ATH_DBG_ANY,
2271                                   "WEP key length %u too small\n", k->kv_len);
2272                         return false;
2273                 }
2274                 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
2275                         keyType = AR_KEYTABLE_TYPE_40;
2276                 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2277                         keyType = AR_KEYTABLE_TYPE_104;
2278                 else
2279                         keyType = AR_KEYTABLE_TYPE_128;
2280                 break;
2281         case ATH9K_CIPHER_CLR:
2282                 keyType = AR_KEYTABLE_TYPE_CLR;
2283                 break;
2284         default:
2285                 ath_print(common, ATH_DBG_FATAL,
2286                           "cipher %u not supported\n", k->kv_type);
2287                 return false;
2288         }
2289
2290         key0 = get_unaligned_le32(k->kv_val + 0);
2291         key1 = get_unaligned_le16(k->kv_val + 4);
2292         key2 = get_unaligned_le32(k->kv_val + 6);
2293         key3 = get_unaligned_le16(k->kv_val + 10);
2294         key4 = get_unaligned_le32(k->kv_val + 12);
2295         if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2296                 key4 &= 0xff;
2297
2298         /*
2299          * Note: Key cache registers access special memory area that requires
2300          * two 32-bit writes to actually update the values in the internal
2301          * memory. Consequently, the exact order and pairs used here must be
2302          * maintained.
2303          */
2304
2305         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2306                 u16 micentry = entry + 64;
2307
2308                 /*
2309                  * Write inverted key[47:0] first to avoid Michael MIC errors
2310                  * on frames that could be sent or received at the same time.
2311                  * The correct key will be written in the end once everything
2312                  * else is ready.
2313                  */
2314                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2315                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2316
2317                 /* Write key[95:48] */
2318                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2319                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2320
2321                 /* Write key[127:96] and key type */
2322                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2323                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2324
2325                 /* Write MAC address for the entry */
2326                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2327
2328                 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2329                         /*
2330                          * TKIP uses two key cache entries:
2331                          * Michael MIC TX/RX keys in the same key cache entry
2332                          * (idx = main index + 64):
2333                          * key0 [31:0] = RX key [31:0]
2334                          * key1 [15:0] = TX key [31:16]
2335                          * key1 [31:16] = reserved
2336                          * key2 [31:0] = RX key [63:32]
2337                          * key3 [15:0] = TX key [15:0]
2338                          * key3 [31:16] = reserved
2339                          * key4 [31:0] = TX key [63:32]
2340                          */
2341                         u32 mic0, mic1, mic2, mic3, mic4;
2342
2343                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2344                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2345                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2346                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2347                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
2348
2349                         /* Write RX[31:0] and TX[31:16] */
2350                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2351                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2352
2353                         /* Write RX[63:32] and TX[15:0] */
2354                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2355                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2356
2357                         /* Write TX[63:32] and keyType(reserved) */
2358                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2359                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2360                                   AR_KEYTABLE_TYPE_CLR);
2361
2362                 } else {
2363                         /*
2364                          * TKIP uses four key cache entries (two for group
2365                          * keys):
2366                          * Michael MIC TX/RX keys are in different key cache
2367                          * entries (idx = main index + 64 for TX and
2368                          * main index + 32 + 96 for RX):
2369                          * key0 [31:0] = TX/RX MIC key [31:0]
2370                          * key1 [31:0] = reserved
2371                          * key2 [31:0] = TX/RX MIC key [63:32]
2372                          * key3 [31:0] = reserved
2373                          * key4 [31:0] = reserved
2374                          *
2375                          * Upper layer code will call this function separately
2376                          * for TX and RX keys when these registers offsets are
2377                          * used.
2378                          */
2379                         u32 mic0, mic2;
2380
2381                         mic0 = get_unaligned_le32(k->kv_mic + 0);
2382                         mic2 = get_unaligned_le32(k->kv_mic + 4);
2383
2384                         /* Write MIC key[31:0] */
2385                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2386                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2387
2388                         /* Write MIC key[63:32] */
2389                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2390                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2391
2392                         /* Write TX[63:32] and keyType(reserved) */
2393                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2394                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2395                                   AR_KEYTABLE_TYPE_CLR);
2396                 }
2397
2398                 /* MAC address registers are reserved for the MIC entry */
2399                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2400                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2401
2402                 /*
2403                  * Write the correct (un-inverted) key[47:0] last to enable
2404                  * TKIP now that all other registers are set with correct
2405                  * values.
2406                  */
2407                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2408                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2409         } else {
2410                 /* Write key[47:0] */
2411                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2412                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2413
2414                 /* Write key[95:48] */
2415                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2416                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2417
2418                 /* Write key[127:96] and key type */
2419                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2420                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2421
2422                 /* Write MAC address for the entry */
2423                 (void) ath9k_hw_keysetmac(ah, entry, mac);
2424         }
2425
2426         return true;
2427 }
2428 EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
2429
2430 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2431 {
2432         if (entry < ah->caps.keycache_size) {
2433                 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2434                 if (val & AR_KEYTABLE_VALID)
2435                         return true;
2436         }
2437         return false;
2438 }
2439 EXPORT_SYMBOL(ath9k_hw_keyisvalid);
2440
2441 /******************************/
2442 /* Power Management (Chipset) */
2443 /******************************/
2444
2445 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2446 {
2447         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2448         if (setChip) {
2449                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2450                             AR_RTC_FORCE_WAKE_EN);
2451                 if (!AR_SREV_9100(ah))
2452                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2453
2454                 if(!AR_SREV_5416(ah))
2455                         REG_CLR_BIT(ah, (AR_RTC_RESET),
2456                                     AR_RTC_RESET_EN);
2457         }
2458 }
2459
2460 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2461 {
2462         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2463         if (setChip) {
2464                 struct ath9k_hw_capabilities *pCap = &ah->caps;
2465
2466                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2467                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2468                                   AR_RTC_FORCE_WAKE_ON_INT);
2469                 } else {
2470                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2471                                     AR_RTC_FORCE_WAKE_EN);
2472                 }
2473         }
2474 }
2475
2476 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2477 {
2478         u32 val;
2479         int i;
2480
2481         if (setChip) {
2482                 if ((REG_READ(ah, AR_RTC_STATUS) &
2483                      AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2484                         if (ath9k_hw_set_reset_reg(ah,
2485                                            ATH9K_RESET_POWER_ON) != true) {
2486                                 return false;
2487                         }
2488                         ath9k_hw_init_pll(ah, NULL);
2489                 }
2490                 if (AR_SREV_9100(ah))
2491                         REG_SET_BIT(ah, AR_RTC_RESET,
2492                                     AR_RTC_RESET_EN);
2493
2494                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2495                             AR_RTC_FORCE_WAKE_EN);
2496                 udelay(50);
2497
2498                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2499                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2500                         if (val == AR_RTC_STATUS_ON)
2501                                 break;
2502                         udelay(50);
2503                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2504                                     AR_RTC_FORCE_WAKE_EN);
2505                 }
2506                 if (i == 0) {
2507                         ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2508                                   "Failed to wakeup in %uus\n",
2509                                   POWER_UP_TIME / 20);
2510                         return false;
2511                 }
2512         }
2513
2514         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2515
2516         return true;
2517 }
2518
2519 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2520 {
2521         struct ath_common *common = ath9k_hw_common(ah);
2522         int status = true, setChip = true;
2523         static const char *modes[] = {
2524                 "AWAKE",
2525                 "FULL-SLEEP",
2526                 "NETWORK SLEEP",
2527                 "UNDEFINED"
2528         };
2529
2530         if (ah->power_mode == mode)
2531                 return status;
2532
2533         ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
2534                   modes[ah->power_mode], modes[mode]);
2535
2536         switch (mode) {
2537         case ATH9K_PM_AWAKE:
2538                 status = ath9k_hw_set_power_awake(ah, setChip);
2539                 break;
2540         case ATH9K_PM_FULL_SLEEP:
2541                 ath9k_set_power_sleep(ah, setChip);
2542                 ah->chip_fullsleep = true;
2543                 break;
2544         case ATH9K_PM_NETWORK_SLEEP:
2545                 ath9k_set_power_network_sleep(ah, setChip);
2546                 break;
2547         default:
2548                 ath_print(common, ATH_DBG_FATAL,
2549                           "Unknown power mode %u\n", mode);
2550                 return false;
2551         }
2552         ah->power_mode = mode;
2553
2554         return status;
2555 }
2556 EXPORT_SYMBOL(ath9k_hw_setpower);
2557
2558 /*
2559  * Helper for ASPM support.
2560  *
2561  * Disable PLL when in L0s as well as receiver clock when in L1.
2562  * This power saving option must be enabled through the SerDes.
2563  *
2564  * Programming the SerDes must go through the same 288 bit serial shift
2565  * register as the other analog registers.  Hence the 9 writes.
2566  */
2567 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore, int power_off)
2568 {
2569         u8 i;
2570         u32 val;
2571
2572         if (ah->is_pciexpress != true)
2573                 return;
2574
2575         /* Do not touch SerDes registers */
2576         if (ah->config.pcie_powersave_enable == 2)
2577                 return;
2578
2579         /* Nothing to do on restore for 11N */
2580         if (!restore) {
2581                 if (AR_SREV_9280_20_OR_LATER(ah)) {
2582                         /*
2583                          * AR9280 2.0 or later chips use SerDes values from the
2584                          * initvals.h initialized depending on chipset during
2585                          * ath9k_hw_init()
2586                          */
2587                         for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2588                                 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2589                                           INI_RA(&ah->iniPcieSerdes, i, 1));
2590                         }
2591                 } else if (AR_SREV_9280(ah) &&
2592                            (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2593                         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2594                         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2595
2596                         /* RX shut off when elecidle is asserted */
2597                         REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2598                         REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2599                         REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2600
2601                         /* Shut off CLKREQ active in L1 */
2602                         if (ah->config.pcie_clock_req)
2603                                 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2604                         else
2605                                 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2606
2607                         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2608                         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2609                         REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2610
2611                         /* Load the new settings */
2612                         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2613
2614                 } else {
2615                         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2616                         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2617
2618                         /* RX shut off when elecidle is asserted */
2619                         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2620                         REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2621                         REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2622
2623                         /*
2624                          * Ignore ah->ah_config.pcie_clock_req setting for
2625                          * pre-AR9280 11n
2626                          */
2627                         REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2628
2629                         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2630                         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2631                         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2632
2633                         /* Load the new settings */
2634                         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2635                 }
2636
2637                 udelay(1000);
2638
2639                 /* set bit 19 to allow forcing of pcie core into L1 state */
2640                 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2641
2642                 /* Several PCIe massages to ensure proper behaviour */
2643                 if (ah->config.pcie_waen) {
2644                         val = ah->config.pcie_waen;
2645                         if (!power_off)
2646                                 val &= (~AR_WA_D3_L1_DISABLE);
2647                 } else {
2648                         if (AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2649                             AR_SREV_9287(ah)) {
2650                                 val = AR9285_WA_DEFAULT;
2651                                 if (!power_off)
2652                                         val &= (~AR_WA_D3_L1_DISABLE);
2653                         } else if (AR_SREV_9280(ah)) {
2654                                 /*
2655                                  * On AR9280 chips bit 22 of 0x4004 needs to be
2656                                  * set otherwise card may disappear.
2657                                  */
2658                                 val = AR9280_WA_DEFAULT;
2659                                 if (!power_off)
2660                                         val &= (~AR_WA_D3_L1_DISABLE);
2661                         } else
2662                                 val = AR_WA_DEFAULT;
2663                 }
2664
2665                 REG_WRITE(ah, AR_WA, val);
2666         }
2667
2668         if (power_off) {
2669                 /*
2670                  * Set PCIe workaround bits
2671                  * bit 14 in WA register (disable L1) should only
2672                  * be set when device enters D3 and be cleared
2673                  * when device comes back to D0.
2674                  */
2675                 if (ah->config.pcie_waen) {
2676                         if (ah->config.pcie_waen & AR_WA_D3_L1_DISABLE)
2677                                 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2678                 } else {
2679                         if (((AR_SREV_9285(ah) || AR_SREV_9271(ah) ||
2680                               AR_SREV_9287(ah)) &&
2681                              (AR9285_WA_DEFAULT & AR_WA_D3_L1_DISABLE)) ||
2682                             (AR_SREV_9280(ah) &&
2683                              (AR9280_WA_DEFAULT & AR_WA_D3_L1_DISABLE))) {
2684                                 REG_SET_BIT(ah, AR_WA, AR_WA_D3_L1_DISABLE);
2685                         }
2686                 }
2687         }
2688 }
2689 EXPORT_SYMBOL(ath9k_hw_configpcipowersave);
2690
2691 /**********************/
2692 /* Interrupt Handling */
2693 /**********************/
2694
2695 bool ath9k_hw_intrpend(struct ath_hw *ah)
2696 {
2697         u32 host_isr;
2698
2699         if (AR_SREV_9100(ah))
2700                 return true;
2701
2702         host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2703         if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2704                 return true;
2705
2706         host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2707         if ((host_isr & AR_INTR_SYNC_DEFAULT)
2708             && (host_isr != AR_INTR_SPURIOUS))
2709                 return true;
2710
2711         return false;
2712 }
2713 EXPORT_SYMBOL(ath9k_hw_intrpend);
2714
2715 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
2716 {
2717         u32 isr = 0;
2718         u32 mask2 = 0;
2719         struct ath9k_hw_capabilities *pCap = &ah->caps;
2720         u32 sync_cause = 0;
2721         bool fatal_int = false;
2722         struct ath_common *common = ath9k_hw_common(ah);
2723
2724         if (!AR_SREV_9100(ah)) {
2725                 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2726                         if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2727                             == AR_RTC_STATUS_ON) {
2728                                 isr = REG_READ(ah, AR_ISR);
2729                         }
2730                 }
2731
2732                 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2733                         AR_INTR_SYNC_DEFAULT;
2734
2735                 *masked = 0;
2736
2737                 if (!isr && !sync_cause)
2738                         return false;
2739         } else {
2740                 *masked = 0;
2741                 isr = REG_READ(ah, AR_ISR);
2742         }
2743
2744         if (isr) {
2745                 if (isr & AR_ISR_BCNMISC) {
2746                         u32 isr2;
2747                         isr2 = REG_READ(ah, AR_ISR_S2);
2748                         if (isr2 & AR_ISR_S2_TIM)
2749                                 mask2 |= ATH9K_INT_TIM;
2750                         if (isr2 & AR_ISR_S2_DTIM)
2751                                 mask2 |= ATH9K_INT_DTIM;
2752                         if (isr2 & AR_ISR_S2_DTIMSYNC)
2753                                 mask2 |= ATH9K_INT_DTIMSYNC;
2754                         if (isr2 & (AR_ISR_S2_CABEND))
2755                                 mask2 |= ATH9K_INT_CABEND;
2756                         if (isr2 & AR_ISR_S2_GTT)
2757                                 mask2 |= ATH9K_INT_GTT;
2758                         if (isr2 & AR_ISR_S2_CST)
2759                                 mask2 |= ATH9K_INT_CST;
2760                         if (isr2 & AR_ISR_S2_TSFOOR)
2761                                 mask2 |= ATH9K_INT_TSFOOR;
2762                 }
2763
2764                 isr = REG_READ(ah, AR_ISR_RAC);
2765                 if (isr == 0xffffffff) {
2766                         *masked = 0;
2767                         return false;
2768                 }
2769
2770                 *masked = isr & ATH9K_INT_COMMON;
2771
2772                 if (ah->config.rx_intr_mitigation) {
2773                         if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2774                                 *masked |= ATH9K_INT_RX;
2775                 }
2776
2777                 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2778                         *masked |= ATH9K_INT_RX;
2779                 if (isr &
2780                     (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2781                      AR_ISR_TXEOL)) {
2782                         u32 s0_s, s1_s;
2783
2784                         *masked |= ATH9K_INT_TX;
2785
2786                         s0_s = REG_READ(ah, AR_ISR_S0_S);
2787                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2788                         ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2789
2790                         s1_s = REG_READ(ah, AR_ISR_S1_S);
2791                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2792                         ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2793                 }
2794
2795                 if (isr & AR_ISR_RXORN) {
2796                         ath_print(common, ATH_DBG_INTERRUPT,
2797                                   "receive FIFO overrun interrupt\n");
2798                 }
2799
2800                 if (!AR_SREV_9100(ah)) {
2801                         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2802                                 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2803                                 if (isr5 & AR_ISR_S5_TIM_TIMER)
2804                                         *masked |= ATH9K_INT_TIM_TIMER;
2805                         }
2806                 }
2807
2808                 *masked |= mask2;
2809         }
2810
2811         if (AR_SREV_9100(ah))
2812                 return true;
2813
2814         if (isr & AR_ISR_GENTMR) {
2815                 u32 s5_s;
2816
2817                 s5_s = REG_READ(ah, AR_ISR_S5_S);
2818                 if (isr & AR_ISR_GENTMR) {
2819                         ah->intr_gen_timer_trigger =
2820                                 MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
2821
2822                         ah->intr_gen_timer_thresh =
2823                                 MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
2824
2825                         if (ah->intr_gen_timer_trigger)
2826                                 *masked |= ATH9K_INT_GENTIMER;
2827
2828                 }
2829         }
2830
2831         if (sync_cause) {
2832                 fatal_int =
2833                         (sync_cause &
2834                          (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2835                         ? true : false;
2836
2837                 if (fatal_int) {
2838                         if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2839                                 ath_print(common, ATH_DBG_ANY,
2840                                           "received PCI FATAL interrupt\n");
2841                         }
2842                         if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
2843                                 ath_print(common, ATH_DBG_ANY,
2844                                           "received PCI PERR interrupt\n");
2845                         }
2846                         *masked |= ATH9K_INT_FATAL;
2847                 }
2848                 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
2849                         ath_print(common, ATH_DBG_INTERRUPT,
2850                                   "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
2851                         REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
2852                         REG_WRITE(ah, AR_RC, 0);
2853                         *masked |= ATH9K_INT_FATAL;
2854                 }
2855                 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
2856                         ath_print(common, ATH_DBG_INTERRUPT,
2857                                   "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
2858                 }
2859
2860                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
2861                 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
2862         }
2863
2864         return true;
2865 }
2866 EXPORT_SYMBOL(ath9k_hw_getisr);
2867
2868 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
2869 {
2870         u32 omask = ah->mask_reg;
2871         u32 mask, mask2;
2872         struct ath9k_hw_capabilities *pCap = &ah->caps;
2873         struct ath_common *common = ath9k_hw_common(ah);
2874
2875         ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
2876
2877         if (omask & ATH9K_INT_GLOBAL) {
2878                 ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
2879                 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
2880                 (void) REG_READ(ah, AR_IER);
2881                 if (!AR_SREV_9100(ah)) {
2882                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
2883                         (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
2884
2885                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
2886                         (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
2887                 }
2888         }
2889
2890         mask = ints & ATH9K_INT_COMMON;
2891         mask2 = 0;
2892
2893         if (ints & ATH9K_INT_TX) {
2894                 if (ah->txok_interrupt_mask)
2895                         mask |= AR_IMR_TXOK;
2896                 if (ah->txdesc_interrupt_mask)
2897                         mask |= AR_IMR_TXDESC;
2898                 if (ah->txerr_interrupt_mask)
2899                         mask |= AR_IMR_TXERR;
2900                 if (ah->txeol_interrupt_mask)
2901                         mask |= AR_IMR_TXEOL;
2902         }
2903         if (ints & ATH9K_INT_RX) {
2904                 mask |= AR_IMR_RXERR;
2905                 if (ah->config.rx_intr_mitigation)
2906                         mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
2907                 else
2908                         mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
2909                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
2910                         mask |= AR_IMR_GENTMR;
2911         }
2912
2913         if (ints & (ATH9K_INT_BMISC)) {
2914                 mask |= AR_IMR_BCNMISC;
2915                 if (ints & ATH9K_INT_TIM)
2916                         mask2 |= AR_IMR_S2_TIM;
2917                 if (ints & ATH9K_INT_DTIM)
2918                         mask2 |= AR_IMR_S2_DTIM;
2919                 if (ints & ATH9K_INT_DTIMSYNC)
2920                         mask2 |= AR_IMR_S2_DTIMSYNC;
2921                 if (ints & ATH9K_INT_CABEND)
2922                         mask2 |= AR_IMR_S2_CABEND;
2923                 if (ints & ATH9K_INT_TSFOOR)
2924                         mask2 |= AR_IMR_S2_TSFOOR;
2925         }
2926
2927         if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
2928                 mask |= AR_IMR_BCNMISC;
2929                 if (ints & ATH9K_INT_GTT)
2930                         mask2 |= AR_IMR_S2_GTT;
2931                 if (ints & ATH9K_INT_CST)
2932                         mask2 |= AR_IMR_S2_CST;
2933         }
2934
2935         ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
2936         REG_WRITE(ah, AR_IMR, mask);
2937         ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
2938                            AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
2939                            AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
2940         ah->imrs2_reg |= mask2;
2941         REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
2942         ah->mask_reg = ints;
2943
2944         if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2945                 if (ints & ATH9K_INT_TIM_TIMER)
2946                         REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2947                 else
2948                         REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
2949         }
2950
2951         if (ints & ATH9K_INT_GLOBAL) {
2952                 ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
2953                 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
2954                 if (!AR_SREV_9100(ah)) {
2955                         REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
2956                                   AR_INTR_MAC_IRQ);
2957                         REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
2958
2959
2960                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
2961                                   AR_INTR_SYNC_DEFAULT);
2962                         REG_WRITE(ah, AR_INTR_SYNC_MASK,
2963                                   AR_INTR_SYNC_DEFAULT);
2964                 }
2965                 ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
2966                           REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
2967         }
2968
2969         return omask;
2970 }
2971 EXPORT_SYMBOL(ath9k_hw_set_interrupts);
2972
2973 /*******************/
2974 /* Beacon Handling */
2975 /*******************/
2976
2977 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2978 {
2979         int flags = 0;
2980
2981         ah->beacon_interval = beacon_period;
2982
2983         switch (ah->opmode) {
2984         case NL80211_IFTYPE_STATION:
2985         case NL80211_IFTYPE_MONITOR:
2986                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
2987                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
2988                 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
2989                 flags |= AR_TBTT_TIMER_EN;
2990                 break;
2991         case NL80211_IFTYPE_ADHOC:
2992         case NL80211_IFTYPE_MESH_POINT:
2993                 REG_SET_BIT(ah, AR_TXCFG,
2994                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2995                 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
2996                           TU_TO_USEC(next_beacon +
2997                                      (ah->atim_window ? ah->
2998                                       atim_window : 1)));
2999                 flags |= AR_NDP_TIMER_EN;
3000         case NL80211_IFTYPE_AP:
3001                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3002                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3003                           TU_TO_USEC(next_beacon -
3004                                      ah->config.
3005                                      dma_beacon_response_time));
3006                 REG_WRITE(ah, AR_NEXT_SWBA,
3007                           TU_TO_USEC(next_beacon -
3008                                      ah->config.
3009                                      sw_beacon_response_time));
3010                 flags |=
3011                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3012                 break;
3013         default:
3014                 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
3015                           "%s: unsupported opmode: %d\n",
3016                           __func__, ah->opmode);
3017                 return;
3018                 break;
3019         }
3020
3021         REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3022         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3023         REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3024         REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3025
3026         beacon_period &= ~ATH9K_BEACON_ENA;
3027         if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3028                 ath9k_hw_reset_tsf(ah);
3029         }
3030
3031         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3032 }
3033 EXPORT_SYMBOL(ath9k_hw_beaconinit);
3034
3035 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3036                                     const struct ath9k_beacon_state *bs)
3037 {
3038         u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3039         struct ath9k_hw_capabilities *pCap = &ah->caps;
3040         struct ath_common *common = ath9k_hw_common(ah);
3041
3042         REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3043
3044         REG_WRITE(ah, AR_BEACON_PERIOD,
3045                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3046         REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3047                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3048
3049         REG_RMW_FIELD(ah, AR_RSSI_THR,
3050                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3051
3052         beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3053
3054         if (bs->bs_sleepduration > beaconintval)
3055                 beaconintval = bs->bs_sleepduration;
3056
3057         dtimperiod = bs->bs_dtimperiod;
3058         if (bs->bs_sleepduration > dtimperiod)
3059                 dtimperiod = bs->bs_sleepduration;
3060
3061         if (beaconintval == dtimperiod)
3062                 nextTbtt = bs->bs_nextdtim;
3063         else
3064                 nextTbtt = bs->bs_nexttbtt;
3065
3066         ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3067         ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3068         ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3069         ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3070
3071         REG_WRITE(ah, AR_NEXT_DTIM,
3072                   TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3073         REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3074
3075         REG_WRITE(ah, AR_SLEEP1,
3076                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3077                   | AR_SLEEP1_ASSUME_DTIM);
3078
3079         if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3080                 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3081         else
3082                 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3083
3084         REG_WRITE(ah, AR_SLEEP2,
3085                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3086
3087         REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3088         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3089
3090         REG_SET_BIT(ah, AR_TIMER_MODE,
3091                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3092                     AR_DTIM_TIMER_EN);
3093
3094         /* TSF Out of Range Threshold */
3095         REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3096 }
3097 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
3098
3099 /*******************/
3100 /* HW Capabilities */
3101 /*******************/
3102
3103 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
3104 {
3105         struct ath9k_hw_capabilities *pCap = &ah->caps;
3106         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3107         struct ath_common *common = ath9k_hw_common(ah);
3108         struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
3109
3110         u16 capField = 0, eeval;
3111
3112         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3113         regulatory->current_rd = eeval;
3114
3115         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3116         if (AR_SREV_9285_10_OR_LATER(ah))
3117                 eeval |= AR9285_RDEXT_DEFAULT;
3118         regulatory->current_rd_ext = eeval;
3119
3120         capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3121
3122         if (ah->opmode != NL80211_IFTYPE_AP &&
3123             ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3124                 if (regulatory->current_rd == 0x64 ||
3125                     regulatory->current_rd == 0x65)
3126                         regulatory->current_rd += 5;
3127                 else if (regulatory->current_rd == 0x41)
3128                         regulatory->current_rd = 0x43;
3129                 ath_print(common, ATH_DBG_REGULATORY,
3130                           "regdomain mapped to 0x%x\n", regulatory->current_rd);
3131         }
3132
3133         eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3134         if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
3135                 ath_print(common, ATH_DBG_FATAL,
3136                           "no band has been marked as supported in EEPROM.\n");
3137                 return -EINVAL;
3138         }
3139
3140         bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3141
3142         if (eeval & AR5416_OPFLAGS_11A) {
3143                 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3144                 if (ah->config.ht_enable) {
3145                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3146                                 set_bit(ATH9K_MODE_11NA_HT20,
3147                                         pCap->wireless_modes);
3148                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3149                                 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3150                                         pCap->wireless_modes);
3151                                 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3152                                         pCap->wireless_modes);
3153                         }
3154                 }
3155         }
3156
3157         if (eeval & AR5416_OPFLAGS_11G) {
3158                 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3159                 if (ah->config.ht_enable) {
3160                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3161                                 set_bit(ATH9K_MODE_11NG_HT20,
3162                                         pCap->wireless_modes);
3163                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3164                                 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3165                                         pCap->wireless_modes);
3166                                 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3167                                         pCap->wireless_modes);
3168                         }
3169                 }
3170         }
3171
3172         pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3173         /*
3174          * For AR9271 we will temporarilly uses the rx chainmax as read from
3175          * the EEPROM.
3176          */
3177         if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3178             !(eeval & AR5416_OPFLAGS_11A) &&
3179             !(AR_SREV_9271(ah)))
3180                 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
3181                 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3182         else
3183                 /* Use rx_chainmask from EEPROM. */
3184                 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3185
3186         if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3187                 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3188
3189         pCap->low_2ghz_chan = 2312;
3190         pCap->high_2ghz_chan = 2732;
3191
3192         pCap->low_5ghz_chan = 4920;
3193         pCap->high_5ghz_chan = 6100;
3194
3195         pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3196         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3197         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3198
3199         pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3200         pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3201         pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3202
3203         if (ah->config.ht_enable)
3204                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3205         else
3206                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3207
3208         pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3209         pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3210         pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3211         pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3212
3213         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3214                 pCap->total_queues =
3215                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3216         else
3217                 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3218
3219         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3220                 pCap->keycache_size =
3221                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3222         else
3223                 pCap->keycache_size = AR_KEYTABLE_SIZE;
3224
3225         pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3226
3227         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
3228                 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
3229         else
3230                 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3231
3232         if (AR_SREV_9285_10_OR_LATER(ah))
3233                 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3234         else if (AR_SREV_9280_10_OR_LATER(ah))
3235                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3236         else
3237                 pCap->num_gpio_pins = AR_NUM_GPIO;
3238
3239         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3240                 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3241                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3242         } else {
3243                 pCap->rts_aggr_limit = (8 * 1024);
3244         }
3245
3246         pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3247
3248 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3249         ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3250         if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3251                 ah->rfkill_gpio =
3252                         MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3253                 ah->rfkill_polarity =
3254                         MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3255
3256                 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3257         }
3258 #endif
3259
3260         pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3261
3262         if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3263                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3264         else
3265                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3266
3267         if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3268                 pCap->reg_cap =
3269                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3270                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3271                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
3272                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3273         } else {
3274                 pCap->reg_cap =
3275                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3276                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3277         }
3278
3279         /* Advertise midband for AR5416 with FCC midband set in eeprom */
3280         if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
3281             AR_SREV_5416(ah))
3282                 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3283
3284         pCap->num_antcfg_5ghz =
3285                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3286         pCap->num_antcfg_2ghz =
3287                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3288
3289         if (AR_SREV_9280_10_OR_LATER(ah) &&
3290             ath9k_hw_btcoex_supported(ah)) {
3291                 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
3292                 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
3293
3294                 if (AR_SREV_9285(ah)) {
3295                         btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
3296                         btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
3297                 } else {
3298                         btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
3299                 }
3300         } else {
3301                 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
3302         }
3303
3304         return 0;
3305 }
3306
3307 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3308                             u32 capability, u32 *result)
3309 {
3310         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3311         switch (type) {
3312         case ATH9K_CAP_CIPHER:
3313                 switch (capability) {
3314                 case ATH9K_CIPHER_AES_CCM:
3315                 case ATH9K_CIPHER_AES_OCB:
3316                 case ATH9K_CIPHER_TKIP:
3317                 case ATH9K_CIPHER_WEP:
3318                 case ATH9K_CIPHER_MIC:
3319                 case ATH9K_CIPHER_CLR:
3320                         return true;
3321                 default:
3322                         return false;
3323                 }
3324         case ATH9K_CAP_TKIP_MIC:
3325                 switch (capability) {
3326                 case 0:
3327                         return true;
3328                 case 1:
3329                         return (ah->sta_id1_defaults &
3330                                 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3331                         false;
3332                 }
3333         case ATH9K_CAP_TKIP_SPLIT:
3334                 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3335                         false : true;
3336         case ATH9K_CAP_DIVERSITY:
3337                 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3338                         AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3339                         true : false;
3340         case ATH9K_CAP_MCAST_KEYSRCH:
3341                 switch (capability) {
3342                 case 0:
3343                         return true;
3344                 case 1:
3345                         if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3346                                 return false;
3347                         } else {
3348                                 return (ah->sta_id1_defaults &
3349                                         AR_STA_ID1_MCAST_KSRCH) ? true :
3350                                         false;
3351                         }
3352                 }
3353                 return false;
3354         case ATH9K_CAP_TXPOW:
3355                 switch (capability) {
3356                 case 0:
3357                         return 0;
3358                 case 1:
3359                         *result = regulatory->power_limit;
3360                         return 0;
3361                 case 2:
3362                         *result = regulatory->max_power_level;
3363                         return 0;
3364                 case 3:
3365                         *result = regulatory->tp_scale;
3366                         return 0;
3367                 }
3368                 return false;
3369         case ATH9K_CAP_DS:
3370                 return (AR_SREV_9280_20_OR_LATER(ah) &&
3371                         (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3372                         ? false : true;
3373         default:
3374                 return false;
3375         }
3376 }
3377 EXPORT_SYMBOL(ath9k_hw_getcapability);
3378
3379 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3380                             u32 capability, u32 setting, int *status)
3381 {
3382         u32 v;
3383
3384         switch (type) {
3385         case ATH9K_CAP_TKIP_MIC:
3386                 if (setting)
3387                         ah->sta_id1_defaults |=
3388                                 AR_STA_ID1_CRPT_MIC_ENABLE;
3389                 else
3390                         ah->sta_id1_defaults &=
3391                                 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3392                 return true;
3393         case ATH9K_CAP_DIVERSITY:
3394                 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3395                 if (setting)
3396                         v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3397                 else
3398                         v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3399                 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3400                 return true;
3401         case ATH9K_CAP_MCAST_KEYSRCH:
3402                 if (setting)
3403                         ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3404                 else
3405                         ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3406                 return true;
3407         default:
3408                 return false;
3409         }
3410 }
3411 EXPORT_SYMBOL(ath9k_hw_setcapability);
3412
3413 /****************************/
3414 /* GPIO / RFKILL / Antennae */
3415 /****************************/
3416
3417 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3418                                          u32 gpio, u32 type)
3419 {
3420         int addr;
3421         u32 gpio_shift, tmp;
3422
3423         if (gpio > 11)
3424                 addr = AR_GPIO_OUTPUT_MUX3;
3425         else if (gpio > 5)
3426                 addr = AR_GPIO_OUTPUT_MUX2;
3427         else
3428                 addr = AR_GPIO_OUTPUT_MUX1;
3429
3430         gpio_shift = (gpio % 6) * 5;
3431
3432         if (AR_SREV_9280_20_OR_LATER(ah)
3433             || (addr != AR_GPIO_OUTPUT_MUX1)) {
3434                 REG_RMW(ah, addr, (type << gpio_shift),
3435                         (0x1f << gpio_shift));
3436         } else {
3437                 tmp = REG_READ(ah, addr);
3438                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3439                 tmp &= ~(0x1f << gpio_shift);
3440                 tmp |= (type << gpio_shift);
3441                 REG_WRITE(ah, addr, tmp);
3442         }
3443 }
3444
3445 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3446 {
3447         u32 gpio_shift;
3448
3449         BUG_ON(gpio >= ah->caps.num_gpio_pins);
3450
3451         gpio_shift = gpio << 1;
3452
3453         REG_RMW(ah,
3454                 AR_GPIO_OE_OUT,
3455                 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3456                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3457 }
3458 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
3459
3460 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3461 {
3462 #define MS_REG_READ(x, y) \
3463         (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3464
3465         if (gpio >= ah->caps.num_gpio_pins)
3466                 return 0xffffffff;
3467
3468         if (AR_SREV_9287_10_OR_LATER(ah))
3469                 return MS_REG_READ(AR9287, gpio) != 0;
3470         else if (AR_SREV_9285_10_OR_LATER(ah))
3471                 return MS_REG_READ(AR9285, gpio) != 0;
3472         else if (AR_SREV_9280_10_OR_LATER(ah))
3473                 return MS_REG_READ(AR928X, gpio) != 0;
3474         else
3475                 return MS_REG_READ(AR, gpio) != 0;
3476 }
3477 EXPORT_SYMBOL(ath9k_hw_gpio_get);
3478
3479 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3480                          u32 ah_signal_type)
3481 {
3482         u32 gpio_shift;
3483
3484         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3485
3486         gpio_shift = 2 * gpio;
3487
3488         REG_RMW(ah,
3489                 AR_GPIO_OE_OUT,
3490                 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3491                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3492 }
3493 EXPORT_SYMBOL(ath9k_hw_cfg_output);
3494
3495 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3496 {
3497         REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3498                 AR_GPIO_BIT(gpio));
3499 }
3500 EXPORT_SYMBOL(ath9k_hw_set_gpio);
3501
3502 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3503 {
3504         return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3505 }
3506 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
3507
3508 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3509 {
3510         REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3511 }
3512 EXPORT_SYMBOL(ath9k_hw_setantenna);
3513
3514 /*********************/
3515 /* General Operation */
3516 /*********************/
3517
3518 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3519 {
3520         u32 bits = REG_READ(ah, AR_RX_FILTER);
3521         u32 phybits = REG_READ(ah, AR_PHY_ERR);
3522
3523         if (phybits & AR_PHY_ERR_RADAR)
3524                 bits |= ATH9K_RX_FILTER_PHYRADAR;
3525         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3526                 bits |= ATH9K_RX_FILTER_PHYERR;
3527
3528         return bits;
3529 }
3530 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
3531
3532 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3533 {
3534         u32 phybits;
3535
3536         REG_WRITE(ah, AR_RX_FILTER, bits);
3537
3538         phybits = 0;
3539         if (bits & ATH9K_RX_FILTER_PHYRADAR)
3540                 phybits |= AR_PHY_ERR_RADAR;
3541         if (bits & ATH9K_RX_FILTER_PHYERR)
3542                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3543         REG_WRITE(ah, AR_PHY_ERR, phybits);
3544
3545         if (phybits)
3546                 REG_WRITE(ah, AR_RXCFG,
3547                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3548         else
3549                 REG_WRITE(ah, AR_RXCFG,
3550                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3551 }
3552 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
3553
3554 bool ath9k_hw_phy_disable(struct ath_hw *ah)
3555 {
3556         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
3557                 return false;
3558
3559         ath9k_hw_init_pll(ah, NULL);
3560         return true;
3561 }
3562 EXPORT_SYMBOL(ath9k_hw_phy_disable);
3563
3564 bool ath9k_hw_disable(struct ath_hw *ah)
3565 {
3566         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3567                 return false;
3568
3569         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
3570                 return false;
3571
3572         ath9k_hw_init_pll(ah, NULL);
3573         return true;
3574 }
3575 EXPORT_SYMBOL(ath9k_hw_disable);
3576
3577 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3578 {
3579         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
3580         struct ath9k_channel *chan = ah->curchan;
3581         struct ieee80211_channel *channel = chan->chan;
3582
3583         regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
3584
3585         ah->eep_ops->set_txpower(ah, chan,
3586                                  ath9k_regd_get_ctl(regulatory, chan),
3587                                  channel->max_antenna_gain * 2,
3588                                  channel->max_power * 2,
3589                                  min((u32) MAX_RATE_POWER,
3590                                  (u32) regulatory->power_limit));
3591 }
3592 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
3593
3594 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3595 {
3596         memcpy(ath9k_hw_common(ah)->macaddr, mac, ETH_ALEN);
3597 }
3598 EXPORT_SYMBOL(ath9k_hw_setmac);
3599
3600 void ath9k_hw_setopmode(struct ath_hw *ah)
3601 {
3602         ath9k_hw_set_operating_mode(ah, ah->opmode);
3603 }
3604 EXPORT_SYMBOL(ath9k_hw_setopmode);
3605
3606 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3607 {
3608         REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3609         REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3610 }
3611 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
3612
3613 void ath9k_hw_write_associd(struct ath_hw *ah)
3614 {
3615         struct ath_common *common = ath9k_hw_common(ah);
3616
3617         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
3618         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
3619                   ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3620 }
3621 EXPORT_SYMBOL(ath9k_hw_write_associd);
3622
3623 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3624 {
3625         u64 tsf;
3626
3627         tsf = REG_READ(ah, AR_TSF_U32);
3628         tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3629
3630         return tsf;
3631 }
3632 EXPORT_SYMBOL(ath9k_hw_gettsf64);
3633
3634 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3635 {
3636         REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3637         REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3638 }
3639 EXPORT_SYMBOL(ath9k_hw_settsf64);
3640
3641 void ath9k_hw_reset_tsf(struct ath_hw *ah)
3642 {
3643         if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
3644                            AH_TSF_WRITE_TIMEOUT))
3645                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
3646                           "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3647
3648         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3649 }
3650 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
3651
3652 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
3653 {
3654         if (setting)
3655                 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3656         else
3657                 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3658 }
3659 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
3660
3661 /*
3662  *  Extend 15-bit time stamp from rx descriptor to
3663  *  a full 64-bit TSF using the current h/w TSF.
3664 */
3665 u64 ath9k_hw_extend_tsf(struct ath_hw *ah, u32 rstamp)
3666 {
3667         u64 tsf;
3668
3669         tsf = ath9k_hw_gettsf64(ah);
3670         if ((tsf & 0x7fff) < rstamp)
3671                 tsf -= 0x8000;
3672         return (tsf & ~0x7fff) | rstamp;
3673 }
3674 EXPORT_SYMBOL(ath9k_hw_extend_tsf);
3675
3676 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
3677 {
3678         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
3679         u32 macmode;
3680
3681         if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
3682                 macmode = AR_2040_JOINED_RX_CLEAR;
3683         else
3684                 macmode = 0;
3685
3686         REG_WRITE(ah, AR_2040_MODE, macmode);
3687 }
3688
3689 /* HW Generic timers configuration */
3690
3691 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
3692 {
3693         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3694         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3695         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3696         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3697         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3698         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3699         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3700         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3701         {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
3702         {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
3703                                 AR_NDP2_TIMER_MODE, 0x0002},
3704         {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
3705                                 AR_NDP2_TIMER_MODE, 0x0004},
3706         {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
3707                                 AR_NDP2_TIMER_MODE, 0x0008},
3708         {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
3709                                 AR_NDP2_TIMER_MODE, 0x0010},
3710         {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
3711                                 AR_NDP2_TIMER_MODE, 0x0020},
3712         {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
3713                                 AR_NDP2_TIMER_MODE, 0x0040},
3714         {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
3715                                 AR_NDP2_TIMER_MODE, 0x0080}
3716 };
3717
3718 /* HW generic timer primitives */
3719
3720 /* compute and clear index of rightmost 1 */
3721 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
3722 {
3723         u32 b;
3724
3725         b = *mask;
3726         b &= (0-b);
3727         *mask &= ~b;
3728         b *= debruijn32;
3729         b >>= 27;
3730
3731         return timer_table->gen_timer_index[b];
3732 }
3733
3734 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
3735 {
3736         return REG_READ(ah, AR_TSF_L32);
3737 }
3738 EXPORT_SYMBOL(ath9k_hw_gettsf32);
3739
3740 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
3741                                           void (*trigger)(void *),
3742                                           void (*overflow)(void *),
3743                                           void *arg,
3744                                           u8 timer_index)
3745 {
3746         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3747         struct ath_gen_timer *timer;
3748
3749         timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
3750
3751         if (timer == NULL) {
3752                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
3753                           "Failed to allocate memory"
3754                           "for hw timer[%d]\n", timer_index);
3755                 return NULL;
3756         }
3757
3758         /* allocate a hardware generic timer slot */
3759         timer_table->timers[timer_index] = timer;
3760         timer->index = timer_index;
3761         timer->trigger = trigger;
3762         timer->overflow = overflow;
3763         timer->arg = arg;
3764
3765         return timer;
3766 }
3767 EXPORT_SYMBOL(ath_gen_timer_alloc);
3768
3769 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
3770                               struct ath_gen_timer *timer,
3771                               u32 timer_next,
3772                               u32 timer_period)
3773 {
3774         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3775         u32 tsf;
3776
3777         BUG_ON(!timer_period);
3778
3779         set_bit(timer->index, &timer_table->timer_mask.timer_bits);
3780
3781         tsf = ath9k_hw_gettsf32(ah);
3782
3783         ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
3784                   "curent tsf %x period %x"
3785                   "timer_next %x\n", tsf, timer_period, timer_next);
3786
3787         /*
3788          * Pull timer_next forward if the current TSF already passed it
3789          * because of software latency
3790          */
3791         if (timer_next < tsf)
3792                 timer_next = tsf + timer_period;
3793
3794         /*
3795          * Program generic timer registers
3796          */
3797         REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3798                  timer_next);
3799         REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3800                   timer_period);
3801         REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3802                     gen_tmr_configuration[timer->index].mode_mask);
3803
3804         /* Enable both trigger and thresh interrupt masks */
3805         REG_SET_BIT(ah, AR_IMR_S5,
3806                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3807                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3808 }
3809 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
3810
3811 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
3812 {
3813         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3814
3815         if ((timer->index < AR_FIRST_NDP_TIMER) ||
3816                 (timer->index >= ATH_MAX_GEN_TIMER)) {
3817                 return;
3818         }
3819
3820         /* Clear generic timer enable bits. */
3821         REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3822                         gen_tmr_configuration[timer->index].mode_mask);
3823
3824         /* Disable both trigger and thresh interrupt masks */
3825         REG_CLR_BIT(ah, AR_IMR_S5,
3826                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3827                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3828
3829         clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
3830 }
3831 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
3832
3833 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3834 {
3835         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3836
3837         /* free the hardware generic timer slot */
3838         timer_table->timers[timer->index] = NULL;
3839         kfree(timer);
3840 }
3841 EXPORT_SYMBOL(ath_gen_timer_free);
3842
3843 /*
3844  * Generic Timer Interrupts handling
3845  */
3846 void ath_gen_timer_isr(struct ath_hw *ah)
3847 {
3848         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3849         struct ath_gen_timer *timer;
3850         struct ath_common *common = ath9k_hw_common(ah);
3851         u32 trigger_mask, thresh_mask, index;
3852
3853         /* get hardware generic timer interrupt status */
3854         trigger_mask = ah->intr_gen_timer_trigger;
3855         thresh_mask = ah->intr_gen_timer_thresh;
3856         trigger_mask &= timer_table->timer_mask.val;
3857         thresh_mask &= timer_table->timer_mask.val;
3858
3859         trigger_mask &= ~thresh_mask;
3860
3861         while (thresh_mask) {
3862                 index = rightmost_index(timer_table, &thresh_mask);
3863                 timer = timer_table->timers[index];
3864                 BUG_ON(!timer);
3865                 ath_print(common, ATH_DBG_HWTIMER,
3866                           "TSF overflow for Gen timer %d\n", index);
3867                 timer->overflow(timer->arg);
3868         }
3869
3870         while (trigger_mask) {
3871                 index = rightmost_index(timer_table, &trigger_mask);
3872                 timer = timer_table->timers[index];
3873                 BUG_ON(!timer);
3874                 ath_print(common, ATH_DBG_HWTIMER,
3875                           "Gen timer[%d] trigger\n", index);
3876                 timer->trigger(timer->arg);
3877         }
3878 }
3879 EXPORT_SYMBOL(ath_gen_timer_isr);
3880
3881 static struct {
3882         u32 version;
3883         const char * name;
3884 } ath_mac_bb_names[] = {
3885         /* Devices with external radios */
3886         { AR_SREV_VERSION_5416_PCI,     "5416" },
3887         { AR_SREV_VERSION_5416_PCIE,    "5418" },
3888         { AR_SREV_VERSION_9100,         "9100" },
3889         { AR_SREV_VERSION_9160,         "9160" },
3890         /* Single-chip solutions */
3891         { AR_SREV_VERSION_9280,         "9280" },
3892         { AR_SREV_VERSION_9285,         "9285" },
3893         { AR_SREV_VERSION_9287,         "9287" },
3894         { AR_SREV_VERSION_9271,         "9271" },
3895 };
3896
3897 /* For devices with external radios */
3898 static struct {
3899         u16 version;
3900         const char * name;
3901 } ath_rf_names[] = {
3902         { 0,                            "5133" },
3903         { AR_RAD5133_SREV_MAJOR,        "5133" },
3904         { AR_RAD5122_SREV_MAJOR,        "5122" },
3905         { AR_RAD2133_SREV_MAJOR,        "2133" },
3906         { AR_RAD2122_SREV_MAJOR,        "2122" }
3907 };
3908
3909 /*
3910  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3911  */
3912 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
3913 {
3914         int i;
3915
3916         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3917                 if (ath_mac_bb_names[i].version == mac_bb_version) {
3918                         return ath_mac_bb_names[i].name;
3919                 }
3920         }
3921
3922         return "????";
3923 }
3924
3925 /*
3926  * Return the RF name. "????" is returned if the RF is unknown.
3927  * Used for devices with external radios.
3928  */
3929 static const char *ath9k_hw_rf_name(u16 rf_version)
3930 {
3931         int i;
3932
3933         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3934                 if (ath_rf_names[i].version == rf_version) {
3935                         return ath_rf_names[i].name;
3936                 }
3937         }
3938
3939         return "????";
3940 }
3941
3942 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3943 {
3944         int used;
3945
3946         /* chipsets >= AR9280 are single-chip */
3947         if (AR_SREV_9280_10_OR_LATER(ah)) {
3948                 used = snprintf(hw_name, len,
3949                                "Atheros AR%s Rev:%x",
3950                                ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3951                                ah->hw_version.macRev);
3952         }
3953         else {
3954                 used = snprintf(hw_name, len,
3955                                "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3956                                ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3957                                ah->hw_version.macRev,
3958                                ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
3959                                                 AR_RADIO_SREV_MAJOR)),
3960                                ah->hw_version.phyRev);
3961         }
3962
3963         hw_name[used] = '\0';
3964 }
3965 EXPORT_SYMBOL(ath9k_hw_name);